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Zneo: ESPI needs to configure GPIO for ESPI

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This commit is contained in:
Gregory Nutt 2014-04-26 13:58:38 -06:00
parent 4ba0a0b218
commit 75928b420e
1 changed files with 17 additions and 1 deletions
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18
arch/z16/src/z16f/z16f_espi.c
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@ -838,9 +838,9 @@ struct spi_dev_s *up_spiinitialize(int port)
FAR struct z16f_spi_s *priv; FAR struct z16f_spi_s *priv;
irqstate_t flags; irqstate_t flags;
#ifndef CONFIG_SPI_OWNBUS #ifndef CONFIG_SPI_OWNBUS
uint8_t regval;
unsigned int offset; unsigned int offset;
#endif #endif
uint8_t regval;
spivdbg("port: %d\n", port); spivdbg("port: %d\n", port);
DEBUGASSERT(port == 0); DEBUGASSERT(port == 0);
@ -858,6 +858,22 @@ struct spi_dev_s *up_spiinitialize(int port)
sem_init(&priv->exclsem, 0, 1); sem_init(&priv->exclsem, 0, 1);
#endif #endif
/* Set up the SPI pin configuration (board-specific logic is required to
* configure and manage all chip selects).
*
* SCK - PC3, Alternate function 1
* MOSI - PC4, Alternate function 1
* MISO - PC5, Alternate function 1
*/
regval = getreg8(Z16F_GPIOC_AFL);
regval |= 0x38;
putreg8(regval, Z16F_GPIOC_AFL);
regval = getreg8(Z16F_GPIOC_AFH);
regval &= ~0x38;
putreg8(regval, Z16F_GPIOC_AFH);
/* Initialize the hardware. Mode 0, 8-bits, 400KHz */ /* Initialize the hardware. Mode 0, 8-bits, 400KHz */
spi_putreg8(priv, 0x00, Z16F_ESPI_CTL); /* Disabled the ESPI */ spi_putreg8(priv, 0x00, Z16F_ESPI_CTL); /* Disabled the ESPI */