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xtensa/esp32s3: SPI support psram and flash timing tuning

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Signed-off-by: chenwen@espressif.com <chenwen@espressif.com>
This commit is contained in:
chenwen@espressif.com 2023-09-08 19:35:10 +08:00 committed by Xiang Xiao
parent 33c3abb706
commit 75999d247f
7 changed files with 1363 additions and 12 deletions
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6
arch/xtensa/src/esp32s3/esp32s3_psram_octal.c
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@ -603,6 +603,12 @@ int IRAM_ATTR psram_enable(int mode, int vaddrmode)
psram_reg.mr2.density == 0x5 ? PSRAM_SIZE_16MB :
psram_reg.mr2.density == 0x7 ? PSRAM_SIZE_32MB : 0;
/* Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0
* PSRAM timing related registers accordingly
*/
esp32s3_spi_timing_set_mspi_psram_tuning();
/* Back to the high speed mode. Flash/PSRAM clocks are set to the clock
* that user selected. SPI0/1 registers are all set correctly.
*/

3
arch/xtensa/src/esp32s3/esp32s3_psram_quad.c
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@ -29,6 +29,7 @@
#include "esp32s3_gpio.h"
#include "esp32s3_psram.h"
#include "esp32s3_spi_timing.h"
#include "rom/esp32s3_spiflash.h"
#include "rom/esp32s3_opi_flash.h"
@ -453,7 +454,7 @@ int psram_enable(int mode, int vaddrmode)
* PSRAM timing related registers accordingly
*/
/* FIXME: spi_timing_psram_tuning(); */
esp32s3_spi_timing_set_mspi_psram_tuning();
/* Configure SPI0 PSRAM related SPI Phases */

1210
arch/xtensa/src/esp32s3/esp32s3_spi_timing.c
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File diff suppressed because it is too large Load Diff

147
arch/xtensa/src/esp32s3/esp32s3_spi_timing.h
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@ -72,10 +72,6 @@ extern "C"
# define ESP32S3_SPI_TIMING_FLASH_TUNING 0
#endif
#if ESP32S3_SPI_TIMING_FLASH_TUNING
# error "SPI flash tuning is not supported"
#endif
#if defined(CONFIG_ESP32S3_SPIRAM)
# if defined(CONFIG_ESP32S3_SPIRAM_SPEED_40M)
# define ESP32S3_SPI_TIMING_PSRAM_CLOCK 40
@ -104,8 +100,115 @@ extern "C"
# define ESP32S3_SPI_TIMING_PSRAM_TUNING 0
#endif
#if ESP32S3_SPI_TIMING_PSRAM_TUNING
# error "SPI PSRAM tuning is not supported"
#if ESP32S3_SPI_TIMING_FLASH_TUNING || ESP32S3_SPI_TIMING_PSRAM_TUNING
/* This should be larger than the max available timing config num */
#define MSPI_TIMING_CONFIG_NUM_DEFAULT 20
#define __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) \
(tuning_config_s) { .config_table = MSPI_TIMING_##type##_CONFIG_TABLE_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \
.config_num = MSPI_TIMING_##type##_CONFIG_NUM_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \
.default_config_id = MSPI_TIMING_##type##_DEFAULT_CONFIG_ID_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode }
#define _GET_TUNING_CONFIG(type, core_clock, module_clock, mode) __GET_TUNING_CONFIG(type, core_clock, module_clock, mode)
#define MSPI_TIMING_FLASH_GET_TUNING_CONFIG(core_clock_mhz, module_clock_mhz, mode) _GET_TUNING_CONFIG(FLASH, core_clock_mhz, module_clock_mhz, mode)
#define MSPI_TIMING_PSRAM_GET_TUNING_CONFIG(core_clock_mhz, module_clock_mhz, mode) _GET_TUNING_CONFIG(PSRAM, core_clock_mhz, module_clock_mhz, mode)
/* Timing Tuning Parameters */
/* FLASH: core clock 160M, module clock 40M, DTR mode */
#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_160M_MODULE_CLK_40M_DTR_MODE {{1, 0, 0}, {0, 0, 0}, {2, 1, 1}, {2, 0, 1}, {2, 2, 2}, {2, 1, 2}, {1, 0, 1}, {0, 0, 1}}
#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_160M_MODULE_CLK_40M_DTR_MODE 8
#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_160M_MODULE_CLK_40M_DTR_MODE 2
/* FLASH: core clock 160M, module clock 80M, DTR mode */
#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE {{0, 0, 0}, {4, 2, 2}, {2, 1, 2}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 2, 3}, {2, 1, 3}, {4, 1, 3}, {1, 0, 2}, {4, 0, 3}, {0, 0, 2}, {4, 2, 4}}
#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE 14
#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE 1
/* FLASH: core clock 240M, module clock 120M, DTR mode */
#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE {{0, 0, 0}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 1, 3}, {1, 0, 2}, {4, 0, 3}, {0, 0, 2}, {4, 1, 4}, {1, 0, 3}, {4, 0, 4}, {0, 0, 3}, {4, 1, 5}}
#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE 14
#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE 1
/* FLASH: core clock 160M, module clock 80M, STR mode */
#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_160M_MODULE_CLK_80M_STR_MODE {{1, 0, 0}, {0, 0, 0}, {2, 1, 1}, {2, 0, 1}, {2, 2, 2}, {2, 1, 2}, {1, 0, 1}, {0, 0, 1}}
#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_160M_MODULE_CLK_80M_STR_MODE 8
#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_160M_MODULE_CLK_80M_STR_MODE 2
/* FLASH: core clock 120M, module clock 120M, STR mode */
#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {1, 0, 1}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {1, 0, 2}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {1, 0, 3}}
#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 12
#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 2
/* FLASH: core clock 240M, module clock 120M, STR mode */
#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE {{1, 0, 0}, {0, 0, 0}, {1, 1, 1}, {2, 3, 2}, {1, 0, 1}, {0, 0, 1}, {1, 1, 2}, {2, 3, 3}, {1, 0, 2}, {0, 0, 2}, {1, 1, 3}, {2, 3, 4}}
#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 12
#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 2
/* PSRAM: core clock 80M, module clock 40M, DTR mode */
#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_40M_DTR_MODE {{1, 0, 0}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 1}, {3, 0, 1}, {1, 0, 1}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 2}, {3, 0, 2}}
#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_80M_MODULE_CLK_40M_DTR_MODE 12
#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_80M_MODULE_CLK_40M_DTR_MODE 4
/* PSRAM: core clock 160M, module clock 80M, DTR mode */
#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE {{0, 0, 0}, {4, 2, 2}, {2, 1, 2}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 2, 3}, {2, 1, 3}, {4, 1, 3}, {1, 0, 2}, {4, 0, 3}, {0, 0, 2}, {4, 2, 4}}
#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE 14
#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_160M_MODULE_CLK_80M_DTR_MODE 5
/* PSRAM: core clock 240M, module clock 120M, STR mode */
#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE {{1, 0, 0}, {0, 0, 0}, {1, 1, 1}, {2, 3, 2}, {1, 0, 1}, {0, 0, 1}, {1, 1, 2}, {2, 3, 3}, {1, 0, 2}, {0, 0, 2}, {1, 1, 3}, {2, 3, 4}}
#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 12
#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 2
/* PSRAM: core clock 120M, module clock 120M, STR mode */
#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {1, 0, 1}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {1, 0, 2}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {1, 0, 3}}
#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 12
#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE 2
/* PSRAM: core clock 240M, module clock 120M, DTR mode */
#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE {{0, 0, 0}, {4, 1, 2}, {1, 0, 1}, {4, 0, 2}, {0, 0, 1}, {4, 1, 3}, {1, 0, 2}, {4, 0, 3}, {0, 0, 2}, {4, 1, 4}, {1, 0, 3}, {4, 0, 4}, {0, 0, 3}, {4, 1, 5}}
#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE 14
#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_DTR_MODE 1
#endif
/****************************************************************************
* Public Types
****************************************************************************/
#if ESP32S3_SPI_TIMING_FLASH_TUNING || ESP32S3_SPI_TIMING_PSRAM_TUNING
/* SPI timing tuning registers.
* Upper layer rely on these 3 registers to tune the timing.
*/
typedef struct
{
uint8_t spi_din_mode; /* input signal delay mode */
uint8_t spi_din_num; /* input signal delay number */
uint8_t extra_dummy_len; /* extra dummy length */
} tuning_param_s;
typedef struct
{
tuning_param_s config_table[MSPI_TIMING_CONFIG_NUM_DEFAULT];
uint32_t config_num;
uint32_t default_config_id; /* If tuning fails, we use this one as default */
} tuning_config_s;
#endif
/****************************************************************************
@ -161,6 +264,38 @@ void esp32s3_spi_timing_set_mspi_high_speed(bool control_spi1);
void esp32s3_spi_timing_set_pin_drive_strength(void);
/****************************************************************************
* Name: esp32s3_spi_timing_set_mspi_psram_tuning
*
* Description:
* Tune MSPI psram timing to make it work under high frequency
*
* Input Parameters:
* None
*
* Returned Value:
* None.
*
****************************************************************************/
void esp32s3_spi_timing_set_mspi_psram_tuning(void);
/****************************************************************************
* Name: esp32s3_spi_timing_set_mspi_flash_tuning
*
* Description:
* Tune MSPI flash timing to make it work under high frequency
*
* Input Parameters:
* None
*
* Returned Value:
* None.
*
****************************************************************************/
void esp32s3_spi_timing_set_mspi_flash_tuning(void);
#ifdef __cplusplus
}
#endif

6
arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.c
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@ -123,7 +123,8 @@ static const struct esp32s3_mtd_dev_s g_esp32s3_spiflash =
#endif
.name = "esp32s3_spiflash"
},
.data = &rom_spiflash_legacy_data,
.data = (const struct spiflash_legacy_data_s **)
(&rom_spiflash_legacy_data),
};
static const struct esp32s3_mtd_dev_s g_esp32s3_spiflash_encrypt =
@ -140,7 +141,8 @@ static const struct esp32s3_mtd_dev_s g_esp32s3_spiflash_encrypt =
#endif
.name = "esp32s3_spiflash_encrypt"
},
.data = &rom_spiflash_legacy_data,
.data = (const struct spiflash_legacy_data_s **)
(&rom_spiflash_legacy_data),
};
/* Ensure exclusive access to the driver */

1
arch/xtensa/src/esp32s3/esp32s3_start.c
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@ -356,6 +356,7 @@ void noreturn_function IRAM_ATTR __esp32s3_start(void)
esp32s3_spi_timing_set_pin_drive_strength();
#endif
esp32s3_spi_timing_set_mspi_flash_tuning();
#if defined(CONFIG_ESP32S3_SPIRAM_BOOT_INIT)
if (esp_spiram_init() != OK)
{

2
arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h
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@ -1008,7 +1008,7 @@ void spi_flash_enable_cache(uint32_t cpuid);
* Public Data
*****************************************************************************/
extern const struct spiflash_legacy_data_s *rom_spiflash_legacy_data;
extern struct spiflash_legacy_data_s *rom_spiflash_legacy_data;
#ifdef __cplusplus
}