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Remove support for software prioritization of interrupts

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This commit is contained in:
Gregory Nutt 2016-10-23 06:37:28 -06:00
parent 2c83d79465
commit 75df09fd40
6 changed files with 8 additions and 93 deletions
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4
arch/xtensa/Kconfig
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@ -35,10 +35,6 @@ config XTENSA_NCOPROCESSORS
int "Number of co-processors"
default 1
config XTENSA_USE_SWPRI
bool "Use SWPRI"
default n
config XTENSA_CALL0_ABI
bool "CALL0 ABI"
default y

13
arch/xtensa/include/irq.h
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@ -112,18 +112,9 @@
# define REG_TMP0 (_REG_CALL0_START + 0)
# define REG_TMP1 (_REG_CALL0_START + 1)
# define REG_TMP2 (_REG_CALL0_START + 2)
# define _REG_SWPRI_START (_REG_CALL0_START + 3)
# define _REG_OVLY_START (_REG_CALL0_START + 3)
#else
# define _REG_SWPRI_START _REG_CALL0_START
#endif
#ifdef CONFIG_XTENSA_USE_SWPRI
/* Storage for virtual priority mask */
# define REG_VPRI (_REG_SWPRI_START + 0)
# define _REG_OVLY_START (_REG_SWPRI_START + 1)
#else
# define _REG_OVLY_START _REG_SWPRI_START
# define _REG_OVLY_START _REG_CALL0_START
#endif
#ifdef CONFIG_XTENSA_USE_OVLY

19
arch/xtensa/src/common/xtensa_context.S
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@ -147,14 +147,6 @@ _xtensa_context_save:
s32i a3, a2, (4 * REG_LCOUNT)
#endif
#ifdef CONFIG_XTENSA_USE_SWPRI
/* Save virtual priority mask */
movi a3, _xtensa_vprimask
l32i a3, a3, 0
s32i a3, a2, (4 * REG_VPRI)
#endif
#if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI)
mov a9, a0 /* Preserve ret addr */
#endif
@ -353,17 +345,6 @@ _xtensa_context_restore:
#error Overly support is not implemented
#endif
#ifdef CONFIG_XTENSA_USE_SWPRI
/* Restore virtual interrupt priority and interrupt enable */
movi a3, _xtensa_intdata
l32i a4, a3, 0 /* a4 = _xtensa_intenable */
l32i a5, a2, (4 * REG_VPRI) /* a5 = saved _xtensa_vprimask */
and a4, a4, a5
wsr a4, INTENABLE /* Update INTENABLE */
s32i a5, a3, 4 /* Restore _xtensa_vprimask */
#endif
l32i a3, a2, (4 * REG_SAR)
l32i sp, a2, (4 * REG_A1)
wsr a3, SAR

4
arch/xtensa/src/common/xtensa_dumpstate.c
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@ -127,10 +127,6 @@ static inline void xtensa_registerdump(void)
_alert(" TMP0: %08lx TMP1: %08lx TMP2: %08lx\n",
(unsigned long)regs[REG_TMP0], (unsigned long)regs[REG_TMP1],
(unsigned long)regs[REG_TMP2]);
#endif
#ifdef CONFIG_XTENSA_USE_SWPRI
_alert(" VPRI: %08lx\n",
(unsigned long)regs[REG_VPRI]);
#endif
}
}

6
arch/xtensa/src/common/xtensa_initialstate.c
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@ -99,12 +99,6 @@ void up_initial_state(struct tcb_s *tcb)
xcp->regs[REG_PS] = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1);
#endif
#ifdef CONFIG_XTENSA_USE_SWPRI
/* Set the initial virtual priority mask value to all 1's. */
xcp->regs[REG_VPRI] = 0xffffffff;
#endif
#warning REVISIT co-processor support
#if 0 /* REVISIT */
#if CONFIG_XTENSA_NCOPROCESSORS > 0

55
arch/xtensa/src/common/xtensa_inthandlers.S
View File

@ -114,7 +114,7 @@
movi a4, \mask
and a2, a2, a3
and a2, a2, a4
beqz a2, 9f /* Nothing to do */
beqz a2, 5f /* Nothing to do */
/* This bit of code provides a nice debug backtrace in the debugger.
* It does take a few more instructions, so undef XT_DEBUG_BACKTRACE
@ -139,11 +139,11 @@
#ifdef CONFIG_XTENSA_CALL0_ABI
callx0 a4
beqz a2, 9f
beqz a2, 5f
#else
mov a6, a2
callx4 a4
beqz a6, 9f
beqz a6, 5f
mov a2, a6
#endif
2:
@ -153,31 +153,9 @@
extract_msb a4, a2 /* a4 = MSB of a2, a2 trashed */
#ifdef CONFIG_XTENSA_USE_SWPRI
/* Enable all interrupts at this level that are numerically higher
* than the one we just selected, since they are treated as higher
* priority.
*/
movi a3, \mask /* a3 = all interrupts at this level */
add a2, a4, a4 /* a2 = a4 << 1 */
addi a2, a2, -1 /* a2 = mask of 1's <= a4 bit */
and a2, a2, a3 /* a2 = mask of all bits <= a4 at this level */
movi a3, _xt_intdata
l32i a6, a3, 4 /* a6 = _xt_vpri_mask */
neg a2, a2
addi a2, a2, -1 /* a2 = mask to apply */
and a5, a6, a2 /* Mask off all bits <= a4 bit */
s32i a5, a3, 4 /* Update _xt_vpri_mask */
rsr a3, INTENABLE
and a3, a3, a2 /* Mask off all bits <= a4 bit */
wsr a3, INTENABLE
rsil a3, \level - 1 /* Lower interrupt level by 1 */
#endif
movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */
wsr a4, INTCLEAR /* Clear sw or edge-triggered interrupt */
beq a3, a4, 7f /* If timer interrupt then skip table */
beq a3, a4, 4f /* If timer interrupt then skip table */
/* Call xtensa_int_decode with, passing that address of the register save
* area as a parameter (A2).
@ -201,13 +179,9 @@
addi sp, a4, -(4 * XCPTCONTEXT_SIZE)
3:
#ifdef CONFIG_XTENSA_USE_SWPRI
j 8f
#else
j .L_xt_user_int_&level& /* Check for more interrupts */
#endif
7:
4:
.ifeq XT_TIMER_INTPRI - \level
@ -223,26 +197,9 @@
mov a6, a12 /* Preserve a6 */
.endif
#ifdef CONFIG_XTENSA_USE_SWPRI
j 8f
#else
j .L_xt_user_int_&level& /* Check for more interrupts */
#endif
#ifdef CONFIG_XTENSA_USE_SWPRI
8:
/* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from
virtual _xt_intenable which _could_ have changed during interrupt
processing. */
movi a3, _xt_intdata
l32i a4, a3, 0 /* a4 = _xt_intenable */
s32i a2, a3, 4 /* Update _xt_vpri_mask */
and a4, a4, a2 /* a4 = masked intenable */
wsr a4, INTENABLE /* Update INTENABLE */
#endif
9:
5:
/* done */
.endm