This commit adds support for the Maxim M3421E USB host driver.
Squashed commit of the following:
drivers/usbhost/usbhost_max3421e.c: Add USB tracing support. Fix compilation errors when assertions and debug is enabled.
drivers/usbhost/usbhost_max3421e.c: Fixes to get a clean compilation.
drivers/usbhost/usbhost_max3421e.c: Drivers is basically code complete.
drivers/usbhost/usbhost_max3421e.c: Missed a little bit of logic in the last commit.
drivers/usbhost/usbhost_max3421e.c: Completes implementatin of control transfers.
drivers/usbhost/usbhost_max3421e.c: Implements low-level part of packet receive.
drivers/usbhost/usbhost_max3421e.c: Reorder some functions add a little more transfer-related logic.
drivers/usbhost/usbhost_max3421e.c: Completes basic logic path for sending normal packets.
drivers/usbhost/usbhost_max3421e.c: Correct handling of SNDFIFO double buffering.
drivers/usbhost/usbhost_max3421e.c: Not necessary to set the ACKSTAT bit in host mode. Clean up some comments.
drivers/usbhost/usbhost_max3421e.c: Mostly cosmetic cleanup
drivers/usbhost/usbhost_max3421e.c: Revise some previous logic. Looks like the MAX3421E can handle 16 channels in host mode. A little bit of work on packet transfer logic.
Copy paste error fix
drivers/usbhost/usbhost_max3421e.c: Add some channel allocation logic.
drivers/usbhost/usbhost_max3421e.c: Add some initialization logic.
drivers/usbhost/usbhost_max3421e.c: Add logic to determine if a full or low speed device has been connected.
drivers/usbhost/usbhost_max3421e.c: Add interrupt handling and bus reset logic.
drivers/usbhost/usbhost_max3421e.c: Add framework for an MAX3421E host driver. Initial commit is just the STM32 OTGFS host driver with a few new SPI-related functions.
This commit is contained in:
Gregory Nutt
parent
88f8a09a25
commit
75f7663427
@ -553,6 +553,41 @@ config XBOXCONTROLLER_NPOLLWAITERS
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endif # USBHOST_XBOXCONTROLLER
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config USBHOST_MAX3421E
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bool "Maxim MAX3421E FS host controller"
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default n
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select SPI
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select SCHED_LPWORK
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depends on EXPERIMENTAL
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---help---
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Enable support for the Maxim MAX3421E FS host controller
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if USBHOST_MAX3421E
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config MAX3421E_DESCSIZE
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int "Max descriptor size"
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default 128
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---help---
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Maximum size of a descriptor. Default: 128
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config MAX3421E_USBHOST_REGDEBUG
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bool "MAX3421 register debug"
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default n
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depends on DEBUG_USB_INFO
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---help---
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Enable very low-level register access debug. Depends on
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CONFIG_DEBUG_USB_INFO.
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config MAX3421E_USBHOST_PKTDUMP
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bool "MAX3421 packet dump"
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default n
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depends on DEBUG_USB_INFO
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---help---
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Dump all incoming and outgoing USB packets. Depends on
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CONFIG_DEBUG_USB_INFO.
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endif # USBHOST_MAX3421E
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config USBHOST_TRACE
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bool "Enable USB HCD tracing for debug"
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default n
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@ -1,7 +1,7 @@
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############################################################################
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# drivers/usbhost/Make.defs
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#
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# Copyright (C) 2010-2015 Gregory Nutt. All rights reserved.
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# Copyright (C) 2010-2015, 2018 Gregory Nutt. All rights reserved.
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# Author: Gregory Nutt <gnutt@nuttx.org>
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#
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# Redistribution and use in source and binary forms, with or without
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@ -70,6 +70,10 @@ ifeq ($(CONFIG_USBHOST_XBOXCONTROLLER),y)
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CSRCS += usbhost_xboxcontroller.c
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endif
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ifeq ($(CONFIG_USBHOST_MAX3421E),y)
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CSRCS += usbhost_max3421e.c
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endif
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# HCD debug/trace logic
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ifeq ($(CONFIG_USBHOST_TRACE),y)
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4700
drivers/usbhost/usbhost_max3421e.c
Normal file
4700
drivers/usbhost/usbhost_max3421e.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -4,6 +4,12 @@
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "MAX3421E USB Peripheral/Host Controller with SPI Interface",
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* 19-3953, Rev 4, Maxim Integrated, July 2013 (Datasheet).
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* "MAX3421E Programming Guide", Maxim Integrated, December 2006
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* (Application Note).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@ -49,6 +55,24 @@
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ***************************************************************/
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/* MAX3421E USB Host Driver Support
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*
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* Pre-requisites
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*
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* CONFIG_USBHOST - Enable general USB host support
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* CONFIG_USBHOST_MAX3421E - Enable the MAX3421E USB host support
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* CONFIG_SCHED_LPWORK - Low priority work queue support is required.
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*
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* Options:
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*
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* CONFIG_MAX3421E_DESCSIZE - Maximum size of a descriptor. Default: 128
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* CONFIG_MAX3421E_USBHOST_REGDEBUG - Enable very low-level register access
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* debug. Depends on CONFIG_DEBUG_USB_INFO.
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* CONFIG_MAX3421E_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
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* packets. Depends on CONFIG_DEBUG_USB_INFO.
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*/
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/* Host Mode Register Addresses *********************************************/
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/* The command byte contains the register address, a direction bit, and an
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* ACKSTAT bit:
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@ -137,8 +161,14 @@
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#define USBHOST_USBCTL_CHIPRES (1 << 5)
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#define USBHOST_CPUCTL_IE (1 << 0)
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#define USBHOST_CPUCTL_PULSEWID0 (1 << 6)
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#define USBHOST_CPUCTL_PULSEWID1 (1 << 7)
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#define USBHOST_CPUCTL_PULSEWID_SHIFT (6) /* Bits 6-7: INT Pulsewidth */
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#define USBHOST_CPUCTL_PULSEWID_MASK (3 << USBHOST_CPUCTL_PULSEWID_SHIFT)
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# define USBHOST_CPUCTL_PULSEWID0 (1 << 6)
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# define USBHOST_CPUCTL_PULSEWID1 (1 << 7)
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# define USBHOST_CPUCTL_PULSEWID_10p6US (0 << USBHOST_CPUCTL_PULSEWID_SHIFT) /* 10.6 uS */
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# define USBHOST_CPUCTL_PULSEWID_5p3US (1 << USBHOST_CPUCTL_PULSEWID_SHIFT) /* 5.3 uS */
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# define USBHOST_CPUCTL_PULSEWID_2p6US (2 << USBHOST_CPUCTL_PULSEWID_SHIFT) /* 2.6 uS */
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# define USBHOST_CPUCTL_PULSEWID_1p3US (4 << USBHOST_CPUCTL_PULSEWID_SHIFT) /* 1.3 uS */
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#define USBHOST_PINCTL_PXA (1 << 0)
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#define USBHOST_PINCTL_GPXB (1 << 1)
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@ -192,24 +222,48 @@
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#define USBHOST_HCTL_FRMRST (1 << 1)
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#define USBHOST_HCTL_BUSSAMPLE (1 << 2)
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#define USBHOST_HCTL_SIGRSM (1 << 3)
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#define USBHOST_HCTL_RCVTOG0 (1 << 4)
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#define USBHOST_HCTL_RCVTOG1 (1 << 5)
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#define USBHOST_HCTL_SNDTOG0 (1 << 6)
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#define USBHOST_HCTL_SNDTOG1 (1 << 7)
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#define USBHOST_HCTL_TOGGLES_SHIFT (4) /* Bits 4-7: Data toggles */
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#define USBHOST_HCTL_TOGGLES_MASK (15 << USBHOST_HCTL_TOGGLES_SHIFT)
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# define USBHOST_HCTL_RCVTOG0 (1 << 4)
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# define USBHOST_HCTL_RCVTOG1 (1 << 5)
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# define USBHOST_HCTL_SNDTOG0 (1 << 6)
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# define USBHOST_HCTL_SNDTOG1 (1 << 7)
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#define USBHOST_HXFR_EP0 (1 << 0)
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#define USBHOST_HXFR_EP1 (1 << 1)
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#define USBHOST_HXFR_EP2 (1 << 2)
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#define USBHOST_HXFR_EP3 (1 << 3)
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#define USBHOST_HXFR_SETUP (1 << 4)
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#define USBHOST_HXFR_OUTNIN (1 << 5)
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#define USBHOST_HXFR_ISO (1 << 6)
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#define USBHOST_HXFR_HS (1 << 7)
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#define USBHOST_HXFR_EP_SHIFT (0) /* Bits 0-3: Endpoint number */
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#define USBHOST_HXFR_EP_MASK (15 << USBHOST_HXFR_EP_SHIFT)
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# define USBHOST_HXFR_EP(n) ((uint8_t)(n) << USBHOST_HXFR_EP_SHIFT)
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#define USBHOST_HXFR_TOKEN_SHIFT (4) /* Bits 4-7: Token */
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#define USBHOST_HXFR_TOKEN_MASK (15 << USBHOST_HXFR_EP_SHIFT)
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# define USBHOST_HXFR_SETUP (1 << 4)
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# define USBHOST_HXFR_OUTNIN (1 << 5)
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# define USBHOST_HXFR_ISO (1 << 6)
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# define USBHOST_HXFR_HS (1 << 7)
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# define USBHOST_HXFR_TOKEN_IN (0)
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# define USBHOST_HXFR_TOKEN_SETUP USBHOST_HXFR_SETUP
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# define USBHOST_HXFR_TOKEN_OUT USBHOST_HXFR_OUTNIN
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# define USBHOST_HXFR_TOKEN_INHS USBHOST_HXFR_HS
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# define USBHOST_HXFR_TOKEN_OUTHS (USBHOST_HXFR_OUTNIN | USBHOST_HXFR_HS)
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# define USBHOST_HXFR_TOKEN_ISOIN USBHOST_HXFR_ISO
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# define USBHOST_HXFR_TOKEN_ISOOUT (USBHOST_HXFR_OUTNIN | USBHOST_HXFR_ISO)
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#define USBHOST_HRSL_HRSLT0 (1 << 0)
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#define USBHOST_HRSL_HRSLT1 (1 << 1)
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#define USBHOST_HRSL_HRSLT2 (1 << 2)
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#define USBHOST_HRSL_HRSLT3 (1 << 3)
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#define USBHOST_HRSL_HRSLT_SHIFT (0) /* Bits 0-3: Host result error code */
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#define USBHOST_HRSL_HRSLT_MASK (15 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_SUCCESS (0 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_BUSY (1 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_BADREQ (2 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_UNDEF (3 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_NAK (4 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_STALL (5 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_TOGERR (6 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_WRONGPID (7 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_BADBC (8 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_PIDERR (9 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_PKTERR (10 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_CRCERR (11 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_KERR (12 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_JERR (13 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_TIMEOUT (14 << USBHOST_HRSL_HRSLT_SHIFT)
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# define USBHOST_HRSL_HRSLT_BABBLE (15 << USBHOST_HRSL_HRSLT_SHIFT)
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#define USBHOST_HRSL_RCVTOGRD (1 << 4)
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#define USBHOST_HRSL_SNDTOGRD (1 << 5)
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#define USBHOST_HRSL_KSTATUS (1 << 6)
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@ -312,6 +366,11 @@
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* Bit 2: Unused
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* Bit 1: Direction (read = 0, write = 1)
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* Bit 0: ACKSTAT
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*
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* The ACKSTAT bit sets the ACKSTAT bit in the EPSTALLS (R9) register
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* (peripheral mode only). The SPI master sets this bit to indicate that it
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* has finished servicing a CONTROL transfer. The ACKSTAT bit is ignored in
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* host mode.
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*/
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/* Read/write access to a register */
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@ -322,15 +381,26 @@
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#define MAX3421E_ACKSTAT_TRUE 0x01
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#define MAX3421E_ACKSTAT_FALSE 0x00
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/* Sizes and numbers of things */
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/* Sizes and numbers of things -- Peripheral mode */
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#define MAX3421E_NENDPOINTS 4 /* EP0..EP3 */
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#define MAX3421E_DBLBUF_SET 0x06 /* EP2, EP3 double buffered */
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#define MAX3421E_NENDPOINTS 4 /* EP0-EP3 */
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#define MAX3421E_ALLEP_SET 0x0f /* EP0-EP3 */
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#define MAX3421E_CONTROL_SET 0x01 /* EP0 is the only control EP */
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#define MAX3421E_BULK_SET 0x0e /* EP1-3 can be bulk EPs */
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#define MAX3421E_INTERUPT_SET 0x0e /* EP1-3 can be interrupt EPs */
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#define MAX3421E_OUTEP_SET 0x02 /* EP1 is the only OUT endpoint */
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#define MAX3421E_INEP_SET 0x0c /* EP2-3 are IN endpoints */
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#define MAX3421E_DBLBUF_SET 0x06 /* EP1-2 are double buffered */
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#define MAX3421E_SNDFIFO_SIZE 64
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#define MAX3421E_RCVFIFO_SIZE 64
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#define MAX3421E_SETUPFIFO_SIZE 8
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/* Sizes and numbers of things -- Host mode */
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#define MAX3421E_NHOST_CHANNELS 16 /* Number of host channels */
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#define MAX3421E_SNDFIFO_SIZE 64 /* Send FIFO, double-buffered */
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#define MAX3421E_RCVFIFO_SIZE 64 /* Receive FIFO, double-buffered */
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#define MAX3421E_SUDFIFO_SIZE 8 /* Setup FIFO */
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/* Value of the MODE register HOST bit */
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#define MAX3421E_MODE_PERIPH 0
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@ -359,12 +429,28 @@ struct spi_dev_s; /* Forward reference */
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struct max3421e_lowerhalf_s
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{
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/* Device characterization */
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/* Device characterization.
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*
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* The interrupt configuration byte may have the following values:
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*
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* USBDEV_PINCTL_INTLEVEL=1 USBDEV_PINCTL_POSINT=xx (has no effect)
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* Open-drain, low level active interrupt. In this mode the INT pin is
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* open-drain, so a pull-up resistor on the INT line is necessary.
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*
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* USBDEV_PINCTL_INTLEVEL=0 USBDEV_PINCTL_POSINT=0
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* Push-pull, falling edge-sensitive. When POSINT=0 (and INTLEVEL=0),
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* the INT pin signals pending interrupts with a negative edge.
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*
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* USBDEV_PINCTL_INTLEVEL=0 USBDEV_PINCTL_POSINT=1
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* Push-pull, rising edge-sensitive. When POSINT=1 (and INTLEVEL=0),
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* the INT pin signals pending interrupts with a positive edge.
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*/
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FAR struct spi_dev_s *spi; /* SPI device instance */
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uint32_t frequency; /* SPI frequency < 26MHz */
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enum spi_mode_e mode; /* Either SPIDEV_MODE0 or SPIDEV_MODE3 */
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uint8_t devid; /* Distinguishes multiple MAX3421E on SPI bus */
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uint8_t intconfig; /* Interrupt configuration. See notes above. */
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/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks
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* to isolate the driver from differences in GPIO interrupt handling
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@ -375,8 +461,8 @@ struct max3421e_lowerhalf_s
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* acknowledge - Acknowledge/clear any pending GPIO interrupt
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*/
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CODE int (*attach)(FAR struct max3421e_lowerhalf_s *lower, xcpt_t isr,
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FAR void *arg);
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CODE int (*attach)(FAR const struct max3421e_lowerhalf_s *lower,
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xcpt_t isr, FAR void *arg);
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CODE void (*enable)(FAR const struct max3421e_lowerhalf_s *lower,
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bool enable);
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CODE void (*acknowledge)(FAR const struct max3421e_lowerhalf_s *lower);
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