Add SH-1 system timer setup
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1175 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -190,7 +190,7 @@
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#define SH1_WDTITI_IRQ (SH1_LASTSCI_IRQ+3) /* WDT ITI */
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#define SH1_CMI_IRQ (SH1_LASTSCI_IRQ+4) /* REF CMI */
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#define STR71X_IRQ_SYSTIMER STR71X_IRQ_T0TIMI
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#define SH1_SYSTIMER_IRQ SH1_IMIA0_IRQ
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#define NR_IRQS (SH1_CMI_IRQ+1)
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#endif
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@ -313,6 +313,85 @@
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#define SH1_SCISSR_RDRF (0x40) /* Bit 6: RDR contains valid received data */
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#define SH1_SCISSR_TDRE (0x80) /* Bit 7: TDR does not contain valid transmit data */
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/* Integrated Timer unit (ITU) */
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#define SH1_ITUTSTR_STR0 (0x01) /* Bit 0: TCNT0 is counting */
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#define SH1_ITUTSTR_STR1 (0x02) /* Bit 1: TCNT1 is counting */
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#define SH1_ITUTSTR_STR2 (0x04) /* Bit 2: TCNT2 is counting */
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#define SH1_ITUTSTR_STR3 (0x08) /* Bit 3: TCNT3 is counting */
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#define SH1_ITUTSTR_STR4 (0x10) /* Bit 4: TCNT4 is counting */
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#define SH1_ITUTSNC_SYNC0 (0x01) /* Bit 0: Channel 0 operates synchronously */
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#define SH1_ITUTSNC_SYNC1 (0x02) /* Bit 1: Channel 1 operates synchronously */
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#define SH1_ITUTSNC_SYNC2 (0x04) /* Bit 2: Channel 2 operates synchronously */
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#define SH1_ITUTSNC_SYNC3 (0x08) /* Bit 3: Channel 3 operates synchronously */
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#define SH1_ITUTSNC_SYNC4 (0x10) /* Bit 4: Channel 4 operates synchronously */
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#define SH1_ITUTMDR_PWM0 (0x01) /* Bit 0: Channel 0 operated in PWM mode */
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#define SH1_ITUTMDR_PWM1 (0x02) /* Bit 1: Channel 1 operated in PWM mode */
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#define SH1_ITUTMDR_PWM2 (0x04) /* Bit 2: Channel 2 operated in PWM mode */
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#define SH1_ITUTMDR_PWM3 (0x08) /* Bit 3: Channel 3 operated in PWM mode */
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#define SH1_ITUTMDR_PWM4 (0x10) /* Bit 4: Channel 4 operated in PWM mode */
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#define SH1_ITUTMDR_FDIR (0x20) /* Bit 5: OVF set when TCNT2 overflows */
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#define SH1_ITUTMDR_MDF (0x40) /* Bit 6: Channel 2 operates in phase counting mode */
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#define SH1_ITUTFCR_BFA3 (0x01) /* Bit 0: GRA3 & BRA3 operate in mode in channel 4 */
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#define SH1_ITUTFCR_BFB3 (0x02) /* Bit 1: GRB3 & BRB3 operate in mode in channel 4 */
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#define SH1_ITUTFCR_BFA4 (0x04) /* Bit 2: GRA4 & BRA4 operate in mode in channel 4 */
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#define SH1_ITUTFCR_BFB4 (0x08) /* Bit 3: GRB4 & BRB4 operate in mode in channel 4 */
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#define SH1_ITUTFCR_CMDMASK (0x30) /* Bit 4-5: Command */
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#define SH1_ITUTFCR_34NDEF (0x00) /* Channels 3/4 normal (default) */
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#define SH1_ITUTFCR_34NORM (0x10) /* Channels 3/4 normal */
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#define SH1_ITUTFCR_34CPWM (0x20) /* Channels 3/4 in complementary PWM mode*/
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#define SH1_ITUTFCR_34RSPWN (0x30) /* Channels 3/4 in reset-synchronized PWM mode */
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#define SH1_ITUTOCR_OLS3 (0x01) /* Bit 0: 1=TIOCA3, A4 & B4 not inverted */
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#define SH1_ITUTOCR_OLS4 (0x02) /* Bit 1: 1=TIOCB3, XA4 & XB4 not inverted */
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#define SH1_ITUTCR_TPSCMSK (0x07) /* Bits 0-2: Clock setup, internal/external, divider */
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#define SH1_ITUTCR_DIV1 (0x00) /* Internal clock (phi) */
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#define SH1_ITUTCR_DIV2 (0x01) /* phi / 2 */
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#define SH1_ITUTCR_DIV4 (0x02) /* phi / 4 */
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#define SH1_ITUTCR_DIV8 (0x03) /* phi / 8 */
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#define SH1_ITUTCR_TCLKA (0x04) /* External clock A (TCLKA) */
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#define SH1_ITUTCR_TCLKB (0x05) /* External clock B (TCLKB) */
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#define SH1_ITUTCR_TCLKC (0x06) /* External clock C (TCLKC) */
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#define SH1_ITUTCR_TCLKD (0x07) /* External clock D (TCLKD) */
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#define SH1_ITUTCR_CKEGMSK (0x18) /* Bits 3-4: External clock input edge selection */
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#define SH1_ITUTCR_RISING (0x00) /* Count rising edges */
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#define SH1_ITUTCR_FALLING (0x08) /* Count falling edges */
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#define SH1_ITUTCR_BOTH (0x10) /* Count both */
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#define SH1_ITUTCR_CCLRMSK (0x60) /* Bits 5-6: TCNT clear controls */
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#define SH1_ITUTCR_NCLR (0x00) /* TCNT not cleared */
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#define SH1_ITUTCR_CGRA (0x20) /* TCNT cleared by GRA */
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#define SH1_ITUTCR_CGRB (0x40) /* TCNT cleared by GRB */
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#define SH1_ITUTCR_CSYNC (0x60) /* Synchronized clear */
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#define SH1_ITUTIOR_IOAMSK (0x07) /* Bits 0-3: GRA function */
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#define SH1_ITUTIOR_OCGRAD (0x00) /* GRA output comparator, disabled */
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#define SH1_ITUTIOR_OCGRA0 (0x01) /* GRA output comparator, 0 output at match */
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#define SH1_ITUTIOR_OCGRA1 (0x02) /* GRA output comparator, 1 output at match */
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#define SH1_ITUTIOR_OCATOG (0x03) /* GRA output comparator, output toggles at match */
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#define SH1_ITUTIOR_ICGRAR (0x04) /* GRA input capture, rising edge */
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#define SH1_ITUTIOR_ICGRAF (0x05) /* GRA input capture, falling edge */
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#define SH1_ITUTIOR_ICGRAB (0x06) /* GRA input capture, both edges */
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#define SH1_ITUTIOR_IOBMSK (0x70) /* Bits 4-6: GRB function */
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#define SH1_ITUTIOR_OCGRBD (0x00) /* GRB output comparator, disabled */
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#define SH1_ITUTIOR_OCGRB0 (0x10) /* GRB output comparator, 0 output at match */
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#define SH1_ITUTIOR_OCGRB1 (0x20) /* GRB output comparator, 1 output at match */
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#define SH1_ITUTIOR_OCBTOG (0x30) /* GRB output comparator, output toggles at match */
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#define SH1_ITUTIOR_ICGRBR (0x40) /* GRB input capture, rising edge */
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#define SH1_ITUTIOR_ICGRBF (0x50) /* GRB input capture, falling edge */
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#define SH1_ITUTIOR_ICGRBB (0x60) /* GRB input capture, both edges */
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#define SH1_ITUTSR_IMFA (0x01) /* Bit 0: 0=Clearing condition, 1=setting confition */
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#define SH1_ITUTSR_IMFB (0x02) /* Bit 1: 0=Clearing condition, 1=setting confition */
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#define SH1_ITUTSR_OVF (0x04) /* Bit 2: 0=Clearing condition, 1=setting confition */
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#define SH1_ITUTIER_IMIEA (0x01) /* Bit 0: Enables interrupt request from IMFA */
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#define SH1_ITUTIER_IMIEB (0x02) /* Bit 1: Enables interrupt request from IMFB */
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#define SH1_ITUTIER_OVIE (0x04) /* Bit 2: Enables interrupt request from OVR */
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/* Interrupt Controller (INTC) */
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#define SH1_IPRA_IRQ3MASK (0x000f) /* Bits 0-3: IRQ3 */
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@ -58,7 +58,58 @@
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* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
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* system clock ticks per second. That value is a user configurable setting
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* that defaults to 100 (100 ticks per second = 10 MS interval).
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*
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* ITU1 operates in periodic timer mode. TCNT counts up until it matches
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* the value of GRA0, then an interrupt is generated. Two values must be
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* computed:
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*
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* (1) The divider that determines the rate at which TCNT increments, and
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* (2) The value of GRA0 that cause the interrupt to occur.
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*
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* These must be selected so that the frequency of interrupt generation is
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* CLK_TCK. Ideally, we would like to use the full range of GRA0 for better
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* timing acuracy:
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*/
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#define DESIRED_GRA0 65535
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/* The ideal divider would be one that generates exactly 65535 ticks in
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* 1/CLK_TCK seconds. For example, if SH1_CLOCK is 10MHz and CLK_TCK is
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* 100, then the ideal divider must be less greater than or equal to:
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*
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* (10,000,000 / CLK_TCK) / 65535 = 1.525
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*
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* The actual selected divider would then have to be 2, resulting in a
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* counting rate of 5,000,0000 and a GRA0 setting of 50,000.
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*/
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#define SYSCLKS_PER_TICK ((SH1_CLOCK + (CLK_TCK-1))/ CLK_TCK)
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#define DESIRED_DIVIDER ((SYSCLKS_PER_TICK + (DESIRED_GRA0-1))/ DESIRED_GRA0)
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#if (DESIRED_DIVIDER <= 1)
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# define SYSCLK_DIVIDER 1
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# define SH1_ITUTCR_DIV SH1_ITUTCR_DIV1
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#elif (DESIRED_DIVIDER <= 2)
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# define SYSCLK_DIVIDER 2
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# define SH1_ITUTCR_DIV SH1_ITUTCR_DIV2
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#elif (DESIRED_DIVIDER <= 4)
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# define SYSCLK_DIVIDER 4
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# define SH1_ITUTCR_DIV SH1_ITUTCR_DIV4
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#elif (DESIRED_DIVIDER <= 8)
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# define SYSCLK_DIVIDER 8
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# define SH1_ITUTCR_DIV SH1_ITUTCR_DIV8
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#else
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# error "No divider is available for this system clock"
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#endif
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/* The TCNT will then increment at the following rate: */
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#define TCNT_CLOCK ((SH1_CLOCK + (SYSCLK_DIVIDER/2))/ SYSCLK_DIVIDER)
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/* And the value of GRA0 that generates at CLK_TCK ticks per second is: */
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#define TCNT_PER_TICK ((TCNT_CLOCK + (CLK_TCK-1))/ CLK_TCK)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -82,9 +133,18 @@
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int up_timerisr(int irq, uint32 *regs)
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{
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ubyte reg8;
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/* Process timer interrupt */
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sched_process_timer();
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/* Clear ITU0 interrupt status flag */
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reg8 = getreg8(SH1_ITU0_TSR);
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reg8 &= ~SH1_ITUTSR_IMFA;
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putreg8(reg8, SH1_ITU0_TSR);
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return 0;
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}
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@ -99,19 +159,45 @@ int up_timerisr(int irq, uint32 *regs)
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void up_timerinit(void)
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{
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#warning "Timer initialization logic needed"
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#if 0
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ubyte reg8;
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/* Set the IRQ interrupt priority */
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/* Clear timer counter 0 */
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up_prioritize_irq(STR71X_IRQ_SYSTIMER, 1);
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putreg16(0, SH1_ITU0_TCNT);
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/* Attach the timer interrupt vector */
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/* Set the GRA0 match value. The interrupt will be generated when TNCT
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* increments to this value
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*/
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(void)irq_attach(STR71X_IRQ_SYSTIMER, (xcpt_t)up_timerisr);
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putreg16(TCNT_PER_TICK, SH1_ITU0_GRA);
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/* And enable the timer interrupt */
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/* Set the timer control register. TCNT cleared by FRA */
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up_enable_irq(STR71X_IRQ_SYSTIMER);
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#endif
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putreg8(SH1_ITUTCR_CGRA|SH1_ITUTCR_DIV, SH1_ITU0_TCR);
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/* Set the timer I/O control register */
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putreg8(0, SH1_ITU0_TIOR); /* GRA used but with no inputs/output pins */
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/* Make sure that all status flags are clear */
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putreg8(0, SH1_ITU0_TSR);
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/* Attach the IMIA0 IRQ */
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irq_attach(SH1_SYSTIMER_IRQ, (xcpt_t)up_timerisr);
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/* Enabled interrupts from GRA compare match */
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putreg8(SH1_ITUTIER_IMIEA, SH1_ITU0_TIER);
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/* Set the interrupt priority */
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up_prioritize_irq(SH1_SYSTIMER_IRQ, 7); /* Set ITU priority midway */
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/* Start the timer */
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reg8 = getreg8(SH1_ITU_TSTR);
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reg8 |= SH1_ITUTSTR_STR0; /* Enable TCNT0 */
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putreg8(reg8, SH1_ITU_TSTR); /* TCNT0 is counting */
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}
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