Add FLASH header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3605 42af7a65-404d-4744-a932-0658087f49c3
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arch/mips/src/pic32mx/pic32mx-flash.h
Executable file
130
arch/mips/src/pic32mx/pic32mx-flash.h
Executable file
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/********************************************************************************************
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* arch/mips/src/pic32mx/pic32mx-flash.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "pic32mx-memorymap.h"
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/********************************************************************************************
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* Pre-Processor Definitions
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********************************************************************************************/
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/* Register Offsets *************************************************************************/
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#define PIC32MX_FLASH_NVMCON_OFFSET 0x0000 /* Programming Control Register */
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#define PIC32MX_FLASH_NVMCONCLR_OFFSET 0x0004 /* Programming Control Clear Register */
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#define PIC32MX_FLASH_NVMCONSET_OFFSET 0x0008 /* Programming Control Set Register */
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#define PIC32MX_FLASH_NVMCONINV_OFFSET 0x000c /* Programming Control Invert Register */
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#define PIC32MX_FLASH_NVMKEY_OFFSET 0x0010 /* Programming Unlock Register */
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#define PIC32MX_FLASH_NVMADDR_OFFSET 0x0020 /* Flash Address Register */
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#define PIC32MX_FLASH_NVMADDRCLR_OFFSET 0x0024 /* Flash Address Clear Register */
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#define PIC32MX_FLASH_NVMADDRSET_OFFSET 0x0028 /* Flash Address Set Register */
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#define PIC32MX_FLASH_NVMADDRINV_OFFSET 0x002c /* Flash Address Invert Register */
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#define PIC32MX_FLASH_NVMDATA_OFFSET 0x0030 /* Flash Program Data Register */
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#define PIC32MX_FLASH_NVMSRCADDR_OFFSET 0x0040 /* Source Data Address Register */
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/* Register Addresses ***********************************************************************/
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#define PIC32MX_FLASH_NVMCON (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCON_OFFSET)
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#define PIC32MX_FLASH_NVMCONCLR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONCLR_OFFSET)
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#define PIC32MX_FLASH_NVMCONSET (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONSET_OFFSET)
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#define PIC32MX_FLASH_NVMCONINV (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMCONINV_OFFSET)
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#define PIC32MX_FLASH_NVMKEY (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMKEY_OFFSET)
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#define PIC32MX_FLASH_NVMADDRCLR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRCLR_OFFSET)
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#define PIC32MX_FLASH_NVMADDRSET (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRSET_OFFSET)
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#define PIC32MX_FLASH_NVMADDRINV (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDRINV_OFFSET)
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#define PIC32MX_FLASH_NVMADDR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMADDR_OFFSET)
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#define PIC32MX_FLASH_NVMDATA (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMDATA_OFFSET)
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#define PIC32MX_FLASH_NVMSRCADDR (PIC32MX_FLASH_K1BASE+PIC32MX_FLASH_NVMSRCADDR_OFFSET)
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/* Register Bit-Field Definitions ***********************************************************/
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/* Programming Control Register */
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#define FLASH_NVMCON_NVMOP_SHIFT (0) /* Bits 0-3: NVM operation */
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#define FLASH_NVMCON_NVMOP_MASK (15 << FLASH_NVMCON_NVMOP_SHIFT)
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# define FLASH_NVMCON_NVMOP_NOP (0 << FLASH_NVMCON_NVMOP_SHIFT) /* No operation */
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# define FLASH_NVMCON_NVMOP_WDPROG (1 << FLASH_NVMCON_NVMOP_SHIFT) /* Word program operation */
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# define FLASH_NVMCON_NVMOP_ROWPROG (3 << FLASH_NVMCON_NVMOP_SHIFT) /* Row program operation */
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# define FLASH_NVMCON_NVMOP_PFMERASE (4 << FLASH_NVMCON_NVMOP_SHIFT) /* Page erase operation */
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# define FLASH_NVMCON_NVMOP_PFMERASE (5 << FLASH_NVMCON_NVMOP_SHIFT) /* PFM erase operationxx */
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#define FLASH_NVMCON_LVDSTAT (1 << 11) /* Bit nn: Low-voltage detect status */
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#define FLASH_NVMCON_LVDERR (1 << 12) /* Bit nn: Low-voltage detect error */
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#define FLASH_NVMCON_WRERR (1 << 13) /* Bit nn: Write error */
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#define FLASH_NVMCON_WREN (1 << 14) /* Bit nn: Write enable */
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#define FLASH_NVMCON_WR (1 << 15) /* Bit nn: Write control */
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/* Programming Unlock Register -- 32 Bits of data */
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/* Flash Address Register -- 32 Bits of data */
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/* Flash Program Data Register -- 32 Bits of data */
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/* Source Data Address Register -- 32 Bits of data */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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#ifndef __ASSEMBLY__
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/********************************************************************************************
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* Inline Functions
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********************************************************************************************/
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/********************************************************************************************
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* Public Function Prototypes
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********************************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_FLASH_H */
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@ -1,4 +1,4 @@
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/****************************************************************************
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/************************************************************************************
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* arch/mips/src/pic32mx/pic32mx-memorymap.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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@ -30,184 +30,192 @@
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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****
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// *********************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H
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/****************************************************************************
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/************************************************************************************
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* Included Files
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****************************************************************************/
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************************************************************************************/
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#include <nuttx/config.h>
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#include "mips32-memorymap.h"
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#include "chip.h"
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/****************************************************************************
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/************************************************************************************
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* Pre-Processor Definitions
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****************************************************************************/
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/* Physical Memory Map ******************************************************/
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************************************************************************************/
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/* This memory may be valid for other chips as well, but I don't know that */
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#define PIC32MX_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */
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#define PIC32MX_PROGFLASH_PBASE 0x1d000000 /* Size depends on CHIP_PROGFLASH_KB */
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#define PIC32MX_SFR_PBASE 0x1f800000 /* Special function registers */
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#define PIC32MX_BOOTFLASH_PBASE 0x1fc00000 /* Size depends on CHIP_BOOTFLASH_KB */
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#define PIC32MX_DEVCFG_PBASE 0x1fc02ff0 /* Device configuration registers */
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#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX3)
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/* Virtual Memory Map *******************************************************/
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/* Physical Memory Map **************************************************************/
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#define PIC32MX_DATAMEM_K0BASE (KSEG0_BASE + PIC32MX_DATAMEM_PBASE)
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#define PIC32MX_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MX_PROGFLASH_PBASE)
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#define PIC32MX_BOOTFLASH_K0BASE (KSEG0_BASE + PIC32MX_BOOTFLASH_PBASE)
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#define PIC32MX_DEVCFG_K0BASE (KSEG0_BASE + PIC32MX_DEVCFG_PBASE)
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# define PIC32MX_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */
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# define PIC32MX_PROGFLASH_PBASE 0x1d000000 /* Size depends on CHIP_PROGFLASH_KB */
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# define PIC32MX_SFR_PBASE 0x1f800000 /* Special function registers */
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# define PIC32MX_BOOTFLASH_PBASE 0x1fc00000 /* Size depends on CHIP_BOOTFLASH_KB */
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# define PIC32MX_DEVCFG_PBASE 0x1fc02ff0 /* Device configuration registers */
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#define PIC32MX_DATAMEM_K1BASE (KSEG1_BASE + PIC32MX_DATAMEM_PBASE)
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#define PIC32MX_PROGFLASH_K1BASE (KSEG1_BASE + PIC32MX_PROGFLASH_PBASE)
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#define PIC32MX_SFR_K1BASE (KSEG1_BASE + PIC32MX_SFR_PBASE)
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#define PIC32MX_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MX_BOOTFLASH_PBASE)
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#define PIC32MX_DEVCFG_K1BASE (KSEG1_BASE + PIC32MX_DEVCFG_PBASE)
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/* Virtual Memory Map ***************************************************************/
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/* Register Base Addresses **************************************************/
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# define PIC32MX_DATAMEM_K0BASE (KSEG0_BASE + PIC32MX_DATAMEM_PBASE)
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# define PIC32MX_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MX_PROGFLASH_PBASE)
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# define PIC32MX_BOOTFLASH_K0BASE (KSEG0_BASE + PIC32MX_BOOTFLASH_PBASE)
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# define PIC32MX_DEVCFG_K0BASE (KSEG0_BASE + PIC32MX_DEVCFG_PBASE)
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# define PIC32MX_DATAMEM_K1BASE (KSEG1_BASE + PIC32MX_DATAMEM_PBASE)
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# define PIC32MX_PROGFLASH_K1BASE (KSEG1_BASE + PIC32MX_PROGFLASH_PBASE)
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# define PIC32MX_SFR_K1BASE (KSEG1_BASE + PIC32MX_SFR_PBASE)
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# define PIC32MX_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MX_BOOTFLASH_PBASE)
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# define PIC32MX_DEVCFG_K1BASE (KSEG1_BASE + PIC32MX_DEVCFG_PBASE)
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/* Register Base Addresses **********************************************************/
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/* Watchdog Register Base Address */
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#define PIC32MX_WDT_K1BASE (PIC32MX_SFR_K1BASE + 0x00000000)
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# define PIC32MX_WDT_K1BASE (PIC32MX_SFR_K1BASE + 0x00000000)
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/* RTCC Register Base Address */
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#define PIC32MX_RTCC_K1BASE (PIC32MX_SFR_K1BASE + 0x00000200)
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# define PIC32MX_RTCC_K1BASE (PIC32MX_SFR_K1BASE + 0x00000200)
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/* Timer 1-5 Register Base Addresses */
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#define PIC32MX_TIMER1_K1BASE (PIC32MX_SFR_K1BASE + 0x00000600)
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#define PIC32MX_TIMER2_K1BASE (PIC32MX_SFR_K1BASE + 0x00000800)
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#define PIC32MX_TIMER3_K1BASE (PIC32MX_SFR_K1BASE + 0x00000a00)
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#define PIC32MX_TIMER4_K1BASE (PIC32MX_SFR_K1BASE + 0x00000c00)
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#define PIC32MX_TIMER5_K1BASE (PIC32MX_SFR_K1BASE + 0x00000e00)
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# define PIC32MX_TIMER1_K1BASE (PIC32MX_SFR_K1BASE + 0x00000600)
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# define PIC32MX_TIMER2_K1BASE (PIC32MX_SFR_K1BASE + 0x00000800)
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# define PIC32MX_TIMER3_K1BASE (PIC32MX_SFR_K1BASE + 0x00000a00)
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# define PIC32MX_TIMER4_K1BASE (PIC32MX_SFR_K1BASE + 0x00000c00)
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# define PIC32MX_TIMER5_K1BASE (PIC32MX_SFR_K1BASE + 0x00000e00)
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/* Input Capture 1-5 Register Base Addresses */
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#define PIC32MX_INCAP1_K1BASE (PIC32MX_SFR_K1BASE + 0x00002000)
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#define PIC32MX_INCAP2_K1BASE (PIC32MX_SFR_K1BASE + 0x00002200)
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#define PIC32MX_INCAP3_K1BASE (PIC32MX_SFR_K1BASE + 0x00002400)
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#define PIC32MX_INCAP4_K1BASE (PIC32MX_SFR_K1BASE + 0x00002600)
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#define PIC32MX_INCAP5_K1BASE (PIC32MX_SFR_K1BASE + 0x00002800)
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# define PIC32MX_INCAP1_K1BASE (PIC32MX_SFR_K1BASE + 0x00002000)
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# define PIC32MX_INCAP2_K1BASE (PIC32MX_SFR_K1BASE + 0x00002200)
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# define PIC32MX_INCAP3_K1BASE (PIC32MX_SFR_K1BASE + 0x00002400)
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# define PIC32MX_INCAP4_K1BASE (PIC32MX_SFR_K1BASE + 0x00002600)
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# define PIC32MX_INCAP5_K1BASE (PIC32MX_SFR_K1BASE + 0x00002800)
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/* Output Compare 1-5 Register Base Addresses */
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#define PIC32MX_OUTCMP1_K1BASE (PIC32MX_SFR_K1BASE + 0x00003000)
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#define PIC32MX_OUTCMP2_K1BASE (PIC32MX_SFR_K1BASE + 0x00003200)
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#define PIC32MX_OUTCMP3_K1BASE (PIC32MX_SFR_K1BASE + 0x00003400)
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#define PIC32MX_OUTCMP4_K1BASE (PIC32MX_SFR_K1BASE + 0x00003600)
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#define PIC32MX_OUTCMP5_K1BASE (PIC32MX_SFR_K1BASE + 0x00003800)
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# define PIC32MX_OUTCMP1_K1BASE (PIC32MX_SFR_K1BASE + 0x00003000)
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# define PIC32MX_OUTCMP2_K1BASE (PIC32MX_SFR_K1BASE + 0x00003200)
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# define PIC32MX_OUTCMP3_K1BASE (PIC32MX_SFR_K1BASE + 0x00003400)
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# define PIC32MX_OUTCMP4_K1BASE (PIC32MX_SFR_K1BASE + 0x00003600)
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# define PIC32MX_OUTCMP5_K1BASE (PIC32MX_SFR_K1BASE + 0x00003800)
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/* I2C 1-2 Register Base Addresses */
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#define PIC32MX_I2C1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005000)
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#define PIC32MX_I2C2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005200)
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# define PIC32MX_I2C1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005000)
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# define PIC32MX_I2C2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005200)
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/* SPI 1-2 Register Base Addresses */
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#define PIC32MX_SPI1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005800)
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#define PIC32MX_SPI2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005a00)
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# define PIC32MX_SPI1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005800)
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# define PIC32MX_SPI2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005a00)
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/* UART 1-2 Register Base Addresses */
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#define PIC32MX_UART1_K1BASE (PIC32MX_SFR_K1BASE + 0x00006000)
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#define PIC32MX_UART2_K1BASE (PIC32MX_SFR_K1BASE + 0x00006200)
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# define PIC32MX_UART1_K1BASE (PIC32MX_SFR_K1BASE + 0x00006000)
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# define PIC32MX_UART2_K1BASE (PIC32MX_SFR_K1BASE + 0x00006200)
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/* Parallel Master Register Base Address */
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#define PCI32MX_PMSTR_K1BASE (PIC32MX_SFR_K1BASE + 0x00007000)
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# define PCI32MX_PMSTR_K1BASE (PIC32MX_SFR_K1BASE + 0x00007000)
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/* ADC Register Base Addresses */
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#define PIC32MX_ADC_K1BASE (PIC32MX_SFR_K1BASE + 0x00009000)
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# define PIC32MX_ADC_K1BASE (PIC32MX_SFR_K1BASE + 0x00009000)
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/* Comparator Voltage Reference Register Base Addresses */
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#define PIC32MX_VREF_K1BASE (PIC32MX_SFR_K1BASE + 0x00009800)
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# define PIC32MX_VREF_K1BASE (PIC32MX_SFR_K1BASE + 0x00009800)
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/* Comparator Register Base Addresses */
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#define PIC32MX_COMP_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000)
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# define PIC32MX_COMP_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000)
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/* Oscillator Control Register Base Addresses */
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#define PIC32MX_OSC_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f000)
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# define PIC32MX_OSC_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f000)
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/* Programming and Diagnostics Register Base Addresses */
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#define PIC32MX_SYSCON_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f200)
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# define PIC32MX_SYSCON_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f200)
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/* FLASH Controller Register Base Addresses */
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#define PIC32MX_FLASH_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f400)
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# define PIC32MX_FLASH_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f400)
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/* Reset Control Register Base Address */
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#define PIC32MX_RESET_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f600)
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# define PIC32MX_RESET_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f600)
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/* Interrupt Register Base Address */
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#define PIC32MX_INT_K1BASE (PIC32MX_SFR_K1BASE + 0x00081000)
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# define PIC32MX_INT_K1BASE (PIC32MX_SFR_K1BASE + 0x00081000)
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/* Bus Matrix Register Base Address */
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|
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#define PIC32MX_BMX_K1BASE (PIC32MX_SFR_K1BASE + 0x00082000)
|
||||
# define PIC32MX_BMX_K1BASE (PIC32MX_SFR_K1BASE + 0x00082000)
|
||||
|
||||
/* DMA Register Base Address */
|
||||
|
||||
#define PIC32MX_DMA_K1BASE (PIC32MX_SFR_K1BASE + 0x00083000)
|
||||
#define PIC32MX_DMACH_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00083060 + 0xc0*(n))
|
||||
#define PIC32MX_DMACH0_K1BASE (PIC32MX_SFR_K1BASE + 0x00083060)
|
||||
#define PIC32MX_DMACH1_K1BASE (PIC32MX_SFR_K1BASE + 0x00083120)
|
||||
#define PIC32MX_DMACH2_K1BASE (PIC32MX_SFR_K1BASE + 0x000831e0)
|
||||
#define PIC32MX_DMACH3_K1BASE (PIC32MX_SFR_K1BASE + 0x000832a0)
|
||||
# define PIC32MX_DMA_K1BASE (PIC32MX_SFR_K1BASE + 0x00083000)
|
||||
# define PIC32MX_DMACH_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00083060 + 0xc0*(n))
|
||||
# define PIC32MX_DMACH0_K1BASE (PIC32MX_SFR_K1BASE + 0x00083060)
|
||||
# define PIC32MX_DMACH1_K1BASE (PIC32MX_SFR_K1BASE + 0x00083120)
|
||||
# define PIC32MX_DMACH2_K1BASE (PIC32MX_SFR_K1BASE + 0x000831e0)
|
||||
# define PIC32MX_DMACH3_K1BASE (PIC32MX_SFR_K1BASE + 0x000832a0)
|
||||
|
||||
/* Prefetch Register Base Address */
|
||||
|
||||
#define PIC32MX_CHE_K1BASE (PIC32MX_SFR_K1BASE + 0x00084000)
|
||||
# define PIC32MX_CHE_K1BASE (PIC32MX_SFR_K1BASE + 0x00084000)
|
||||
|
||||
/* USB2 Register Base Addresses */
|
||||
|
||||
#define PIC32MX_USB_K1BASE (PIC32MX_SFR_K1BASE + 0x00085000)
|
||||
# define PIC32MX_USB_K1BASE (PIC32MX_SFR_K1BASE + 0x00085000)
|
||||
|
||||
/* Port Register Base Addresses */
|
||||
|
||||
#define PIC32MX_IOPORTA 0
|
||||
#define PIC32MX_IOPORTB 1
|
||||
#define PIC32MX_IOPORTC 2
|
||||
#define PIC32MX_IOPORTD 3
|
||||
#define PIC32MX_IOPORTE 4
|
||||
#define PIC32MX_IOPORTF 5
|
||||
#define PIC32MX_IOPORTG 6
|
||||
#define PIC32MX_IOPORT_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00086000 + 0x40*(n))
|
||||
# define PIC32MX_IOPORTA 0
|
||||
# define PIC32MX_IOPORTB 1
|
||||
# define PIC32MX_IOPORTC 2
|
||||
# define PIC32MX_IOPORTD 3
|
||||
# define PIC32MX_IOPORTE 4
|
||||
# define PIC32MX_IOPORTF 5
|
||||
# define PIC32MX_IOPORTG 6
|
||||
# define PIC32MX_IOPORT_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00086000 + 0x40*(n))
|
||||
|
||||
#define PIC32MX_IOPORTA_K1BASE (PIC32MX_SFR_K1BASE + 0x00086000)
|
||||
#define PIC32MX_IOPORTB_K1BASE (PIC32MX_SFR_K1BASE + 0x00086040)
|
||||
#define PIC32MX_IOPORTC_K1BASE (PIC32MX_SFR_K1BASE + 0x00086080)
|
||||
#define PIC32MX_IOPORTD_K1BASE (PIC32MX_SFR_K1BASE + 0x000860c0)
|
||||
#define PIC32MX_IOPORTE_K1BASE (PIC32MX_SFR_K1BASE + 0x00086100)
|
||||
#define PIC32MX_IOPORTF_K1BASE (PIC32MX_SFR_K1BASE + 0x00086140)
|
||||
#define PIC32MX_IOPORTG_K1BASE (PIC32MX_SFR_K1BASE + 0x00086180)
|
||||
# define PIC32MX_IOPORTA_K1BASE (PIC32MX_SFR_K1BASE + 0x00086000)
|
||||
# define PIC32MX_IOPORTB_K1BASE (PIC32MX_SFR_K1BASE + 0x00086040)
|
||||
# define PIC32MX_IOPORTC_K1BASE (PIC32MX_SFR_K1BASE + 0x00086080)
|
||||
# define PIC32MX_IOPORTD_K1BASE (PIC32MX_SFR_K1BASE + 0x000860c0)
|
||||
# define PIC32MX_IOPORTE_K1BASE (PIC32MX_SFR_K1BASE + 0x00086100)
|
||||
# define PIC32MX_IOPORTF_K1BASE (PIC32MX_SFR_K1BASE + 0x00086140)
|
||||
# define PIC32MX_IOPORTG_K1BASE (PIC32MX_SFR_K1BASE + 0x00086180)
|
||||
|
||||
#define PIC32MX_IOPORTCN_K1BASE (PIC32MX_SFR_K1BASE + 0x000861c0)
|
||||
# define PIC32MX_IOPORTCN_K1BASE (PIC32MX_SFR_K1BASE + 0x000861c0)
|
||||
|
||||
/****************************************************************************
|
||||
#else
|
||||
# error "Memory map unknown for this PIC32 chip"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
************************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user