From 764e1179658837020164e4a06e94296ffe0d02fa Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sun, 8 Dec 2013 08:51:19 -0600 Subject: [PATCH] A10: Correct handling of the serial busy interrupt --- ChangeLog | 2 ++ arch/arm/src/a1x/a1x_serial.c | 15 +++++++++++++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/ChangeLog b/ChangeLog index cbf96864e2..182d3d2874 100644 --- a/ChangeLog +++ b/ChangeLog @@ -6381,4 +6381,6 @@ * arch/arm/src/armv7-a/arm_head.S and arm_pghead.S: Add more nop's after enabling the MMU. The cortex-a8 seems to need these (2014-1-7). + * arch/arm/src/a1x/a1x_serial.c: Correct handling of the BUSY + interrupt (2014-1-7). diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c index 0864fb5518..fd73ad34bc 100644 --- a/arch/arm/src/a1x/a1x_serial.c +++ b/arch/arm/src/a1x/a1x_serial.c @@ -1176,11 +1176,22 @@ static int uart_interrupt(struct uart_dev_s *dev) /* Busy detect. Just ignore. Cleared by reading the status register */ case UART_IIR_IID_BUSY: - break; + { + /* Read from the UART status register to clear the BUSY condition */ - /* Otherwise, there is no (handled) interrupt pending */ + status = up_serialin(priv, A1X_UART_USR_OFFSET); + break; + } + + /* No further interrupts pending... return now */ case UART_IIR_IID_NONE: + { + return OK; + } + + /* Otherwise we have received an interrupt that we cannot handle */ + default: { lldbg("Unexpected IIR: %02x\n", status);