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Xtensa: Restore XCHAL_ naming convenction

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This commit is contained in:
Gregory Nutt 2016-10-22 09:03:43 -06:00
parent 1ea22b680d
commit 764ef72641
8 changed files with 499 additions and 498 deletions
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915
arch/xtensa/include/esp32/core-isa.h
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File diff suppressed because it is too large Load Diff

2
arch/xtensa/include/irq.h
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@ -97,7 +97,7 @@
#define _REG_LOOPS_START (21)
#ifdef XTENSA_HAVE_LOOPS
#ifdef XCHAL_HAVE_LOOPS
# define REG_LBEG (_REG_LOOPS_START + 0)
# define REG_LEND (_REG_LOOPS_START + 1)
# define REG_LCOUNT (_REG_LOOPS_START + 2)

6
arch/xtensa/src/common/xtensa_context.S
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@ -142,7 +142,7 @@ _xtensa_context_save:
rsr a3, SAR
s32i a3, a2, (4 * REG_SAR)
#ifdef XTENSA_HAVE_LOOPS
#ifdef XCHAL_HAVE_LOOPS
rsr a3, LBEG
s32i a3, a2, (4 * REG_LBEG)
rsr a3, LEND
@ -167,7 +167,7 @@ _xtensa_context_save:
/* To spill the reg windows, temp. need pre-interrupt stack ptr and
* a4-15. Need to save a9,12,13 temporarily (in frame temps) and
* recover originals. Interrupts need to be disabled below
* XTENSA_EXCM_LEVEL and window overflow and underflow exceptions
* XCHAL_EXCM_LEVEL and window overflow and underflow exceptions
* disabled (assured by PS.EXCM == 1).
*/
@ -339,7 +339,7 @@ _xtensa_context_restore:
mov a0, a13 /* Retrieve ret addr */
#endif
#ifdef XTENSA_HAVE_LOOPS
#ifdef XCHAL_HAVE_LOOPS
l32i a2, a2, (4 * REG_LBEG)
l32i a3, a2, (4 * REG_LEND)
wsr a2, LBEG

2
arch/xtensa/src/common/xtensa_dumpstate.c
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@ -118,7 +118,7 @@ static inline void xtensa_registerdump(void)
_alert(" SAR: %08lx CAUSE: %08lx VADDR: %08lx\n",
(unsigned long)regs[REG_SAR], (unsigned long)regs[REG_EXCCAUSE],
(unsigned long)regs[REG_EXCVADDR]);
#ifdef XTENSA_HAVE_LOOPS
#ifdef XCHAL_HAVE_LOOPS
_alert(" LBEG: %08lx LEND: %08lx LCNT: %08lx\n",
(unsigned long)regs[REG_LBEG], (unsigned long)regs[REG_LEND],
(unsigned long)regs[REG_LCOUNT]);

32
arch/xtensa/src/common/xtensa_inthandlers.S
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@ -259,7 +259,7 @@
*
* Description:
* Medium priority interrupts are by definition those with priority greater
* than 1 and not greater than XTENSA_EXCM_LEVEL. These are disabled
* than 1 and not greater than XCHAL_EXCM_LEVEL. These are disabled
* by setting PS.EXCM and therefore can easily support a C environment for
* handlers in C, and interact safely with NuttX.
*
@ -277,7 +277,7 @@
*
****************************************************************************/
#if XTENSA_EXCM_LEVEL >= 2
#if XCHAL_EXCM_LEVEL >= 2
.section .iram1,"ax"
.type _xtensa_level2_handler,@function
.align 4
@ -315,7 +315,7 @@ _xtensa_level2_handler:
* context save area.
*/
dispatch_c_isr 2 XTENSA_INTLEVEL2_MASK
dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK
/* Restore registers in preparation to return from interrupt */
@ -338,14 +338,14 @@ _xtensa_level2_handler:
rfi 2
#endif /* XTENSA_EXCM_LEVEL >= 2 */
#endif /* XCHAL_EXCM_LEVEL >= 2 */
/****************************************************************************
*
* HIGH PRIORITY (LEVEL > XTENSA_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS
* HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS
*
* High priority interrupts are by definition those with priorities greater
* than XTENSA_EXCM_LEVEL. This includes non-maskable (NMI). High priority
* than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority
* interrupts cannot interact with the RTOS, that is they must save all regs
* they use and not call any RTOS function.
*
@ -380,7 +380,7 @@ here. However a template and example can be found in the Cadence Design Systems
documentation: "Microprocessor Programmer's Guide".
*/
#if XTENSA_INT_NLEVELS >=2 && XTENSA_EXCM_LEVEL < 2 && XTENSA_DEBUGLEVEL !=2
#if XCHAL_INT_NLEVELS >=2 && XCHAL_EXCM_LEVEL < 2 && XCHAL_DEBUGLEVEL !=2
.section .iram1,"ax"
.type _xtensa_level2_handler, @function
.align 4
@ -410,9 +410,9 @@ _xtensa_level2_handler:
rsr a0, EXCSAVE_2 /* Restore a0 */
rfi 2
#endif /* XTENSA_INT_NLEVELS >=2 && XTENSA_EXCM_LEVEL < 2 && XTENSA_DEBUGLEVEL !=2 */
#endif /* XCHAL_INT_NLEVELS >=2 && XCHAL_EXCM_LEVEL < 2 && XCHAL_DEBUGLEVEL !=2 */
#if XTENSA_INT_NLEVELS >=3 && XTENSA_EXCM_LEVEL < 3 && XTENSA_DEBUGLEVEL !=3
#if XCHAL_INT_NLEVELS >=3 && XCHAL_EXCM_LEVEL < 3 && XCHAL_DEBUGLEVEL !=3
.section .iram1,"ax"
.type _xtensa_level3_handler, @function
.align 4
@ -441,9 +441,9 @@ _xtensa_level3_handler:
rsr a0, EXCSAVE_3 /* Restore a0 */
rfi 3
#endif /* XTENSA_INT_NLEVELS >=3 && XTENSA_EXCM_LEVEL < 3 && XTENSA_DEBUGLEVEL !=3 */
#endif /* XCHAL_INT_NLEVELS >=3 && XCHAL_EXCM_LEVEL < 3 && XCHAL_DEBUGLEVEL !=3 */
#if XTENSA_INT_NLEVELS >=4 && XTENSA_EXCM_LEVEL < 4 && XTENSA_DEBUGLEVEL !=4
#if XCHAL_INT_NLEVELS >=4 && XCHAL_EXCM_LEVEL < 4 && XCHAL_DEBUGLEVEL !=4
.section .iram1,"ax"
.type _xtensa_level4_handler,@function
.align 4
@ -472,9 +472,9 @@ _xtensa_level4_handler:
rsr a0, EXCSAVE_4 /* Restore a0 */
rfi 4
#endif /* XTENSA_INT_NLEVELS >=4 && XTENSA_EXCM_LEVEL < 4 && XTENSA_DEBUGLEVEL !=4 */
#endif /* XCHAL_INT_NLEVELS >=4 && XCHAL_EXCM_LEVEL < 4 && XCHAL_DEBUGLEVEL !=4 */
#if XTENSA_INT_NLEVELS >=5 && XTENSA_EXCM_LEVEL < 5 && XTENSA_DEBUGLEVEL !=5
#if XCHAL_INT_NLEVELS >=5 && XCHAL_EXCM_LEVEL < 5 && XCHAL_DEBUGLEVEL !=5
.section .iram1,"ax"
.type _xtensa_level5_handler,@function
.align 4
@ -501,9 +501,9 @@ _xtensa_level5_handler:
rsr a0, EXCSAVE_5 /* restore a0 */
rfi 5
#endif /* XTENSA_INT_NLEVELS >=5 && XTENSA_EXCM_LEVEL < 5 && XTENSA_DEBUGLEVEL !=5 */
#endif /* XCHAL_INT_NLEVELS >=5 && XCHAL_EXCM_LEVEL < 5 && XCHAL_DEBUGLEVEL !=5 */
#if XTENSA_INT_NLEVELS >=6 && XTENSA_EXCM_LEVEL < 6 && XTENSA_DEBUGLEVEL !=6
#if XCHAL_INT_NLEVELS >=6 && XCHAL_EXCM_LEVEL < 6 && XCHAL_DEBUGLEVEL !=6
.section .iram1,"ax"
.type _xtensa_level6_handler, @function
.align 4
@ -530,4 +530,4 @@ _xtensa_level6_handler:
rsr a0, EXCSAVE_6 /* Restore a0 */
rfi 6
#endif /* XTENSA_INT_NLEVELS >=6 && XTENSA_EXCM_LEVEL < 6 && XTENSA_DEBUGLEVEL !=6 */
#endif /* XCHAL_INT_NLEVELS >=6 && XCHAL_EXCM_LEVEL < 6 && XCHAL_DEBUGLEVEL !=6 */

10
arch/xtensa/src/common/xtensa_intvectors.S
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@ -60,7 +60,7 @@
*
****************************************************************************/
#if XTENSA_EXCM_LEVEL >= 2
#if XCHAL_EXCM_LEVEL >= 2
.begin literal_prefix .xtensa_level2_vector
.section .xtensa_level2_vector.text, "ax"
.global _xtensa_level2_vector
@ -79,7 +79,7 @@ _xtensa_level2_vector:
.size _xtensa_level2_vector, . - _xtensa_level2_vector
#endif
#if XTENSA_EXCM_LEVEL >= 3
#if XCHAL_EXCM_LEVEL >= 3
.begin literal_prefix .xtensa_level3_vector
.section .xtensa_level3_vector.text, "ax"
.global _xtensa_level3_vector
@ -98,7 +98,7 @@ _xtensa_level3_vector:
.size _xtensa_level3_vector, . - _xtensa_level3_vector
#endif
#if XTENSA_EXCM_LEVEL >= 4
#if XCHAL_EXCM_LEVEL >= 4
.begin literal_prefix .xtensa_level4_vector
.section .xtensa_level4_vector.text, "ax"
.global _xtensa_level4_vector
@ -117,7 +117,7 @@ _xtensa_level4_vector:
.size _xtensa_level5_vector, . - _xtensa_level5_vector
#endif
#if XTENSA_EXCM_LEVEL >= 5
#if XCHAL_EXCM_LEVEL >= 5
.begin literal_prefix .xtensa_level5_vector
.section .xtensa_level5_vector.text, "ax"
.global _xtensa_level5_vector
@ -136,7 +136,7 @@ _xtensa_level5_vector:
.size _xtensa_level5_vector, . - _xtensa_level5_vector
#endif
#if XTENSA_EXCM_LEVEL >= 6
#if XCHAL_EXCM_LEVEL >= 6
.begin literal_prefix .xtensa_level6_vector
.section .xtensa_level6_vector.text, "ax"
.global _xtensa_level6_vector

8
arch/xtensa/src/common/xtensa_irq.S
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@ -43,7 +43,7 @@
* Public Data
****************************************************************************/
#ifdef CONFIG_XTENSA_HAVE_INTERRUPTS
#ifdef CONFIG_XCHAL_HAVE_INTERRUPTS
/* INTENABLE virtualization information. */
@ -64,7 +64,7 @@ _xtensa_vprimask:
.word 0xffffffff /* Virtual priority mask */
.size _xtensa_vprimask, 4
#endif /* CONFIG_XTENSA_HAVE_INTERRUPTS */
#endif /* CONFIG_XCHAL_HAVE_INTERRUPTS */
/****************************************************************************
* Public Functions
@ -89,7 +89,7 @@ _xtensa_vprimask:
xtensa_enable_interrupts:
ENTRY0
#ifdef CONFIG_XTENSA_HAVE_INTERRUPTS
#ifdef CONFIG_XCHAL_HAVE_INTERRUPTS
movi a3, 0
movi a4, _xtensa_intdata
xsr a3, INTENABLE /* Disables all interrupts */
@ -127,7 +127,7 @@ xtensa_enable_interrupts:
xtensa_disable_interrupts:
ENTRY0
#ifdef CONFIG_XTENSA_HAVE_INTERRUPTS
#ifdef CONFIG_XCHAL_HAVE_INTERRUPTS
movi a3, 0
movi a4, _xtensa_intdata
xsr a3, INTENABLE /* Disables all interrupts */

22
arch/xtensa/src/common/xtensa_timer.h
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@ -47,33 +47,33 @@
* Otherwise select the first low or medium priority interrupt timer available.
*/
#if XTENSA_NUM_TIMERS == 0
#if XCHAL_NUM_TIMERS == 0
# error "This Xtensa configuration is unsupported, it has no timers."
#else
#ifndef XT_TIMER_INDEX
# if XTENSA_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
# if XTENSA_INT_LEVEL(XTENSA_TIMER3_INTERRUPT) <= XTENSA_EXCM_LEVEL
# if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
# if XTENSA_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
# undef XT_TIMER_INDEX
# define XT_TIMER_INDEX 3
# endif
# endif
# if XTENSA_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
# if XTENSA_INT_LEVEL(XTENSA_TIMER2_INTERRUPT) <= XTENSA_EXCM_LEVEL
# if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
# if XTENSA_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
# undef XT_TIMER_INDEX
# define XT_TIMER_INDEX 2
# endif
# endif
# if XTENSA_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
# if XTENSA_INT_LEVEL(XTENSA_TIMER1_INTERRUPT) <= XTENSA_EXCM_LEVEL
# if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
# if XTENSA_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
# undef XT_TIMER_INDEX
# define XT_TIMER_INDEX 1
# endif
# endif
# if XTENSA_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
# if XTENSA_INT_LEVEL(XTENSA_TIMER0_INTERRUPT) <= XTENSA_EXCM_LEVEL
# if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
# if XTENSA_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
# undef XT_TIMER_INDEX
# define XT_TIMER_INDEX 0
# endif
@ -90,11 +90,11 @@
#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
# error "The timer selected by XT_TIMER_INDEX does not exist in this core."
#elif XT_TIMER_INTPRI > XTENSA_EXCM_LEVEL
#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
# error "The timer interrupt cannot be high priority (use medium or low)."
#endif
#endif /* XTENSA_NUM_TIMERS */
#endif /* XCHAL_NUM_TIMERS */
/* Set processor clock frequency, used to determine clock divisor for timer
* tick. User should BE SURE TO ADJUST THIS for the Xtensa platform being