sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

LPC17 Ethernet: Add support for the Micrel KSZ8041 PHY.

Browse Source
This commit is contained in:
Gregory Nutt 2015-06-03 17:34:36 -06:00
parent d9d6ff1d1b
commit 7677cf72eb
1 changed files with 45 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
arch/arm/src/lpc17xx/lpc17_ethernet.c
View File

@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/lpc17xx/lpc17_ethernet.c * arch/arm/src/lpc17xx/lpc17_ethernet.c
* *
* Copyright (C) 2010-2014 Gregory Nutt. All rights reserved. * Copyright (C) 2010-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -183,6 +183,11 @@
# define LPC17_PHYID1 MII_PHYID1_KS8721 # define LPC17_PHYID1 MII_PHYID1_KS8721
# define LPC17_PHYID2 MII_PHYID2_KS8721 # define LPC17_PHYID2 MII_PHYID2_KS8721
# define LPC17_HAVE_PHY 1 # define LPC17_HAVE_PHY 1
#if defined(CONFIG_ETH0_PHY_KSZ8041)
# define LPC17_PHYNAME "KSZ8041"
# define LPC17_PHYID1 MII_PHYID1_KSZ8041
# define LPC17_PHYID2 MII_PHYID2_KSZ8041
# define LPC17_HAVE_PHY 1
#elif defined(CONFIG_ETH0_PHY_DP83848C) #elif defined(CONFIG_ETH0_PHY_DP83848C)
# define LPC17_PHYNAME "DP83848C" # define LPC17_PHYNAME "DP83848C"
# define LPC17_PHYID1 MII_PHYID1_DP83848C # define LPC17_PHYID1 MII_PHYID1_DP83848C
@ -2773,20 +2778,53 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
priv->lp_mode = LPC17_10BASET_HD; priv->lp_mode = LPC17_10BASET_HD;
lpc17_putreg(0, LPC17_ETH_SUPP); lpc17_putreg(0, LPC17_ETH_SUPP);
break; break;
case KS8721_10BTCR_MODE_100BTHD: /* 100BASE-T half duplex */ case KS8721_10BTCR_MODE_100BTHD: /* 100BASE-T half duplex */
priv->lp_mode = LPC17_100BASET_HD; priv->lp_mode = LPC17_100BASET_HD;
break; break;
case KS8721_10BTCR_MODE_10BTFD: /* 10BASE-T full duplex */ case KS8721_10BTCR_MODE_10BTFD: /* 10BASE-T full duplex */
priv->lp_mode = LPC17_10BASET_FD; priv->lp_mode = LPC17_10BASET_FD;
lpc17_putreg(0, LPC17_ETH_SUPP); lpc17_putreg(0, LPC17_ETH_SUPP);
break; break;
case KS8721_10BTCR_MODE_100BTFD: /* 100BASE-T full duplex */ case KS8721_10BTCR_MODE_100BTFD: /* 100BASE-T full duplex */
priv->lp_mode = LPC17_100BASET_FD; priv->lp_mode = LPC17_100BASET_FD;
break; break;
default: default:
ndbg("Unrecognized mode: %04x\n", phyreg); ndbg("Unrecognized mode: %04x\n", phyreg);
return -ENODEV; return -ENODEV;
} }
#if defined(CONFIG_ETH0_PHY_KSZ8041)
phyreg = lpc17_phyread(phyaddr, MII_KSZ8041_PHYCTRL2);
switch (phyreg & MII_PHYCTRL2_MODE_MASK)
{
case MII_PHYCTRL2_MODE_10HDX: /* 10BASE-T half duplex */
priv->lp_mode = LPC17_10BASET_HD;
lpc17_putreg(0, LPC17_ETH_SUPP);
break;
case MII_PHYCTRL2_MODE_100HDX: /* 100BASE-T half duplex */
priv->lp_mode = LPC17_100BASET_HD;
break;
case MII_PHYCTRL2_MODE_10FDX: /* 10BASE-T full duplex */
priv->lp_mode = LPC17_10BASET_FD;
lpc17_putreg(0, LPC17_ETH_SUPP);
break;
case MII_PHYCTRL2_MODE_100FDX: /* 100BASE-T full duplex */
priv->lp_mode = LPC17_100BASET_FD;
break;
default:
ndbg("Unrecognized mode: %04x\n", phyreg);
return -ENODEV;
}
#elif defined(CONFIG_ETH0_PHY_DP83848C) #elif defined(CONFIG_ETH0_PHY_DP83848C)
phyreg = lpc17_phyread(phyaddr, MII_DP83848C_STS); phyreg = lpc17_phyread(phyaddr, MII_DP83848C_STS);
@ -2797,19 +2835,24 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
case 0x0000: case 0x0000:
priv->lp_mode = LPC17_100BASET_HD; priv->lp_mode = LPC17_100BASET_HD;
break; break;
case 0x0002: case 0x0002:
priv->lp_mode = LPC17_10BASET_HD; priv->lp_mode = LPC17_10BASET_HD;
break; break;
case 0x0004: case 0x0004:
priv->lp_mode = LPC17_100BASET_FD; priv->lp_mode = LPC17_100BASET_FD;
break; break;
case 0x0006: case 0x0006:
priv->lp_mode = LPC17_10BASET_FD; priv->lp_mode = LPC17_10BASET_FD;
break; break;
default: default:
ndbg("Unrecognized mode: %04x\n", phyreg); ndbg("Unrecognized mode: %04x\n", phyreg);
return -ENODEV; return -ENODEV;
} }
#elif defined(CONFIG_ETH0_PHY_LAN8720) #elif defined(CONFIG_ETH0_PHY_LAN8720)
{ {
uint16_t advertise; uint16_t advertise;
@ -2856,6 +2899,7 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
return -ENODEV; return -ENODEV;
} }
} }
#else #else
# warning "PHY Unknown: speed and duplex are bogus" # warning "PHY Unknown: speed and duplex are bogus"
#endif #endif