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arch/arm/src/stm32: Added Vbat measurement to adc driver for STM32F20xx and STM32F4xxx.

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As with the MCU temperature and VREFINT measurement, this patch requires user to enable the corresponding channel first. For Vbat channel the ioctl cmd is IO_ENABLE_DISABLE_VBAT_CH, and its arg should be a pointer to bool which must be true to enable and false to disable the Vbat channel.

Moreover, since Vbat input contains a built-in voltage divider, it is highly suggested to disable Vbat input channel after measurement is done in order to prevent battery drain through the divider.
This commit is contained in:
Dmitriy Linikov 2018-05-18 06:45:46 -06:00 committed by Gregory Nutt
parent af8b1abf73
commit 76f0e68812
2 changed files with 41 additions and 3 deletions
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41
arch/arm/src/stm32/stm32_adc.c
View File

@ -2254,7 +2254,8 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
*
****************************************************************************/
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX)
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
defined(CONFIG_STM32_STM32F4XXX)
static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev,
bool enable)
{
@ -2297,6 +2298,38 @@ static void adc_ioc_enable_tvref_register(FAR struct adc_dev_s *dev,
}
#endif
/****************************************************************************
* Name: adc_enable_vbat_channel
*
* Description:
* Enable/disable the Vbat voltage measurement channel.
*
* Input Parameters:
* dev - pointer to device structure used by the driver
* enable - true: Vbat input channel enabled (ch 18)
* false: Vbat input channel disabled (ch 18)
*
* Returned Value:
* None.
*
****************************************************************************/
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
static void adc_enable_vbat_channel(FAR struct adc_dev_s *dev, bool enable)
{
if (enable)
{
stm32_modifyreg32(STM32_ADC_CCR, 0, ADC_CCR_VBATE);
}
else
{
stm32_modifyreg32(STM32_ADC_CCR, ADC_CCR_VBATE, 0);
}
ainfo("STM32_ADC_CCR value: 0x%08x\n", getreg32(STM32_ADC_CCR));
}
#endif
/****************************************************************************
* Name: adc_ioc_change_sleep_between_opers
*
@ -2696,11 +2729,15 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
adc_ioc_enable_tvref_register(dev, *(bool *)arg);
break;
#elif defined(CONFIG_STM32_STM32F20XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
case IO_ENABLE_TEMPER_VOLT_CH:
adc_ioc_enable_tvref_register(dev, *(bool *)arg);
break;
case IO_ENABLE_DISABLE_VBAT_CH:
adc_enable_vbat_channel(dev, *(bool *)arg);
break;
#elif defined(CONFIG_STM32_STM32L15XX)
case IO_ENABLE_TEMPER_VOLT_CH:
adc_ioc_enable_tvref_register(dev, *(bool *)arg);

3
arch/arm/src/stm32/stm32_adc.h
View File

@ -1862,10 +1862,11 @@ enum adc_io_cmds_e
IO_ENABLE_TEMPER_VOLT_CH = 0,
};
#elif defined(CONFIG_STM32_STM32F20XX)
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX)
enum adc_io_cmds_e
{
IO_ENABLE_TEMPER_VOLT_CH = 0,
IO_ENABLE_DISABLE_VBAT_CH,
};
#elif defined(CONFIG_STM32_STM32L15XX)