XMC4xxx: A few more SCU register definitions.
This commit is contained in:
Gregory Nutt
parent
cfa75de85a
commit
7706810fc0
@ -537,10 +537,13 @@
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/* Enable Promoting Events to NMI Request */
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#define SCU_NMIREQEN_
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/* Retention Memory Access Control Register */
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#define SCU_RMACR_
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/* Retention Memory Access Data Register */
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#define SCU_RMADATA_
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/* Parity Error Enable Register */
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#define SCU_RMACR_RDWR (1 << 0) /* Bit 0: Hibernate Retention Memory Register Update Control */
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#define SCU_RMACR_ADDR_SHIFT (16) /* Bits 16-19: Hibernate Retention Memory Register Address Select */
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#define SCU_RMACR_ADDR_MASK (15 << SCU_RMACR_ADDR_SHIFT)
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# define SCU_RMACR_ADDR(n) ((uint32_t)(n) << SCU_RMACR_ADDR_SHIFT)
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/* Retention Memory Access Data Register (32-bit data) */
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/* SDMMC Control SCU Registers */
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@ -715,39 +718,62 @@
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#define SCU_RSTCLR_HIBRS (1 << 9) /* Bit 9: Clear Hibernate Reset */
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#define SCU_RSTCLR_LCKEN (1 << 10) /* Bit 10: Clear Hibernate Reset */
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/* Peripheral Reset Status Register 0 */
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#define SCU_PRSTAT0_
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/* Peripheral Reset Set Register 0 */
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#define SCU_PRSET0_
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/* Peripheral Reset Clear Register 0 */
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#define SCU_PRCLR0_
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/* Peripheral Reset Status Register 1 */
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#define SCU_PRSTAT1_
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/* Peripheral Reset Set Register 1 */
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#define SCU_PRSET1_
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/* Peripheral Reset Clear Register 1 */
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#define SCU_PRCLR1_
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/* Peripheral Reset Status Register 2 */
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#define SCU_PRSTAT2_
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/* Peripheral Reset Set Register 2 */
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#define SCU_PRSET2_
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/* Peripheral Reset Clear Register 2 */
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#define SCU_PRCLR2_
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/* Peripheral Reset Status Register 3 */
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#define SCU_PRSTAT3_
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/* Peripheral Reset Set Register 3 */
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#define SCU_PRSET3_
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/* Peripheral Reset Clear Register 3 */
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#define SCU_PRCLR3_
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/* Peripheral Reset Status Register 0, Peripheral Reset Set Register 0, Peripheral
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* Reset Clear Register 0
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*/
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#define SCU_PR0_VADCRS (1 << 0) /* Bit 0: VADC Reset */
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#define SCU_PR0_DSDRS (1 << 1) /* Bit 1: DSD Reset */
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#define SCU_PR0_CCU40RS (1 << 2) /* Bit 2: CCU40 Reset */
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#define SCU_PR0_CCU41RS (1 << 3) /* Bit 3: CCU41 Reset */
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#define SCU_PR0_CCU42RS (1 << 4) /* Bit 4: CCU42 Reset */
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#define SCU_PR0_CCU80RS (1 << 7) /* Bit 7: CCU80 Reset */
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#define SCU_PR0_CCU81RS (1 << 8) /* Bit 8: CCU81 Reset */
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#define SCU_PR0_POSIF0RS (1 << 9) /* Bit 9: POSIF0 Reset */
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#define SCU_PR0_POSIF1RS (1 << 10) /* Bit 10: POSIF1 Reset */
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#define SCU_PR0_USIC0RS (1 << 11) /* Bit 11: USIC0 Reset */
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#define SCU_PR0_ERU1RS (1 << 16) /* Bit 16: ERU1 Reset */
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/* Peripheral Reset Status Register 1, Peripheral Reset Set Register 1, Peripheral
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* Reset Clear Register 1
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*/
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#define SCU_PR1_CCU43RS (1 << 0) /* Bit 0: CCU43 Reset */
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#define SCU_PR1_LEDTSCU0RS (1 << 3) /* Bit 3: LEDTS Reset */
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#define SCU_PR1_MCAN0RS (1 << 4) /* Bit 4: MultiCAN Reset */
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#define SCU_PR1_DACRS (1 << 5) /* Bit 5: DAC Reset */
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#define SCU_PR1_MMCIRS (1 << 6) /* Bit 6: MMC Interface Reset */
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#define SCU_PR1_USIC1RS (1 << 7) /* Bit 7: USIC1 Reset */
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#define SCU_PR1_USIC2RS (1 << 8) /* Bit 8: USIC2 Reset */
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#define SCU_PR1_PPORTSRS (1 << 9) /* Bit 9: PORTS Reset */
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/* Peripheral Reset Status Register 1, Peripheral Reset Set Register 1, Peripheral
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* Reset Clear Register 1
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*/
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#define SCU_PR2_WDTRS (1 << 1) /* Bit 1: WDT Reset */
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#define SCU_PR2_ETH0RS (1 << 2) /* Bit 2: ETH0 Reset */
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#define SCU_PR2_DMA0RS (1 << 4) /* Bit 4: DMA0 Reset */
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#define SCU_PR2_DMA1RS (1 << 5) /* Bit 5: DMA1 Reset */
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#define SCU_PR2_FCERS (1 << 6) /* Bit 6: FCE Reset */
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#define SCU_PR2_USBRS (1 << 7) /* Bit 7: USB Reset */
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/* Peripheral Reset Status Register 3, Peripheral Reset Set Register 3, Peripheral
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* Reset Clear Register 3
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*/
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#define SCU_PR3_EBURS (1 << 2) /* Bit 2: EBU Reset */
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/* Clock Control SCU Registers */
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/* Clock Status Register */
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#define SCU_CLKSTAT_
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/* Clock Set Control Register */
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#define SCU_CLKSET_
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/* Clock clear Control Register */
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#define SCU_CLKCLR_
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/* Clock Status Register, Clock Set Control Register, Clock clear Control Register */
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#define SCU_CLK_USBC (1 << 0) /* Bit 0: USB Clock */
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#define SCU_CLK_MMCC (1 << 1) /* Bit 1: MMC Clock */
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#define SCU_CLK_ETH0C (1 << 2) /* Bit 2: Ethernet Clock */
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#define SCU_CLK_EBUC (1 << 3) /* Bit 3: EBU Clock */
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#define SCU_CLK_CCUC (1 << 4) /* Bit 4: CCU Clock */
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#define SCU_CLK_WDTC (1 << 5) /* Bit 5: WDT Clock */
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/* System Clock Control */
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@ -764,7 +790,10 @@
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#define SCU_CPUCLKCR_CPUDIV (1 << 0) /* Bit 0: CPU Clock Divider Enable */
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/* Peripheral Bus Clock Control */
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#define SCU_PBCLKCR_
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#define SCU_PBCLKCR_PBDIV_Pos (1 << 0) /* Bit 0: PB Clock Divider Enable */
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# define SCU_PBCLKCR_PBDIV_FCPU (0) /* 0=fCPU */
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# define SCU_PBCLKCR_PBDIV_DIV2 ((1 << 0) /* 1=fCPU/2 */
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/* USB Clock Control */
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@ -776,13 +805,39 @@
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# define SCU_USBCLKCR_USBSEL_PLL (1 << 16) /* 1= PLL Clock */
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/* EBU Clock Control */
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#define SCU_EBUCLKCR_
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#define SCU_EBUCLKCR_EBUDIV_SHIFT (0) /* Bitx 0-5: EBU Clock Divider Value */
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#define SCU_EBUCLKCR_EBUDIV_MASK (0x3f << SCU_EBUCLKCR_EBUDIV_SHIFT)
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# define SCU_EBUCLKCR_EBUDIV(n) ((uint32_t)((n)-1) << SCU_EBUCLKCR_EBUDIV_SHIFT)
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/* CCU Clock Control */
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#define SCU_CCUCLKCR_
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#define SCU_CCUCLKCR_CCUDIV_Pos (1 << 0) /* Bit 0: CCU Clock Divider Enable */
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# define SCU_CCUCLKCR_CCUDIV_FSYS (0) /* 0= SYS */
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# define SCU_CCUCLKCR_CCUDIV_DIV2 (1 << 0) /* 1=fSYS/2 */
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/* WDT Clock Control */
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#define SCU_WDTCLKCR_
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#define SCU_WDTCLKCR_WDTDIV_SHIFT (0) /* Bits 0-7: WDT Clock Divider Value */
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#define SCU_WDTCLKCR_WDTDIV_MASK (0xff << SCU_WDTCLKCR_WDTDIV_SHIFT)
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# define SCU_WDTCLKCR_WDTDIV(n) ((uint32_t)((n)-1) << SCU_WDTCLKCR_WDTDIV_SHIFT)
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#define SCU_WDTCLKCR_WDTSEL_SHIFT (16) /* Bits 16-17: WDT Clock Selection Value */
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#define SCU_WDTCLKCR_WDTSEL_MASK (3 << SCU_WDTCLKCR_WDTSEL_SHIFT)
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# define SCU_WDTCLKCR_WDTSEL_FOFI (0 << SCU_WDTCLKCR_WDTSEL_SHIFT) /* fOFI clock */
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# define SCU_WDTCLKCR_WDTSEL_FSTDY (1 << SCU_WDTCLKCR_WDTSEL_SHIFT) /* fSTDBY clock */
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# define SCU_WDTCLKCR_WDTSEL_FPLL (2 << SCU_WDTCLKCR_WDTSEL_SHIFT) /* fPLL clock */
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/* External clock Control Register */
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#define SCU_EXTCLKCR_
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#define SCU_EXTCLKCR_ECKSEL_SHIFT (0) /* Bits 0-1: External Clock Selection Value */
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#define SCU_EXTCLKCR_ECKSEL_MASK (3 << SCU_EXTCLKCR_ECKSEL_SHIFT)
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# define SCU_EXTCLKCR_ECKSEL_FSYS (0 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fSYS clock */
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# define SCU_EXTCLKCR_ECKSEL_FUSB (2 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fUSB clock divided by ECKDIV */
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# define SCU_EXTCLKCR_ECKSEL_FPLL (3 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fPLL clock divided by ECKDIV */
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#define SCU_EXTCLKCR_ECKDIV_SHIFT (16) /* Bits 16-24: External Clock Divider Value */
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#define SCU_EXTCLKCR_ECKDIV_MASK (0x1ff << SCU_EXTCLKCR_ECKDIV_SHIFT)
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# define SCU_EXTCLKCR_ECKDIV(n) ((uint32_t)((n)-1) << SCU_EXTCLKCR_ECKDIV_SHIFT)
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/* Sleep Control Register */
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#define SCU_SLEEPCR_
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/* Deep Sleep Control Register */
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