diff --git a/arch/arm/src/xmc4/chip/xmc4_memorymap.h b/arch/arm/src/xmc4/chip/xmc4_memorymap.h new file mode 100644 index 0000000000..8cf50174b9 --- /dev/null +++ b/arch/arm/src/xmc4/chip/xmc4_memorymap.h @@ -0,0 +1,227 @@ +/************************************************************************************ + * arch/arm/src/xmc4/chip/xmc4_memorymap.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H +#define __ARCH_ARM_SRC_XMC4_CHIP_XMC4_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Peripheral Memory Map ************************************************************/ +/* Acronyms: + * ADC - Analog to Digital Converter + * CCU - Capture Compare Unit + * DAC - Digital to Analog Converter + * DSD - Delta Sigmoid Demodulator + * ERU - External Request Unit + * FCE - Flexible CRC Engine + * GPDMA - General Purpose DMA + * LEDTS - LED and Touch Sense Control Unit + * PMU - Program Management Unit + * POSIF - Position Interface + * SDMMC - Multi Media Card Interface + * USB - Universal Serial Bus + * USCI - Universal Serial Interface + */ + +#define XMC4_PBA0_BASE 0x40000000 +#define XMC4_VADC_BASE 0x40004000 +#define XMC4_VADC_G0_BASE 0x40004400 +#define XMC4_VADC_G1_BASE 0x40004800 +#define XMC4_VADC_G2_BASE 0x40004c00 +#define XMC4_VADC_G3_BASE 0x40005000 +#define XMC4_DSD_BASE 0x40008000 +#define XMC4_DSD_CH0_BASE 0x40008100 +#define XMC4_DSD_CH1_BASE 0x40008200 +#define XMC4_DSD_CH2_BASE 0x40008300 +#define XMC4_DSD_CH3_BASE 0x40008400 +#define XMC4_CCU40_BASE 0x4000c000 +#define XMC4_CCU40_CC40_BASE 0x4000c100 +#define XMC4_CCU40_CC41_BASE 0x4000c200 +#define XMC4_CCU40_CC42_BASE 0x4000c300 +#define XMC4_CCU40_CC43_BASE 0x4000c400 +#define XMC4_CCU41_BASE 0x40010000 +#define XMC4_CCU41_CC40_BASE 0x40010100 +#define XMC4_CCU41_CC41_BASE 0x40010200 +#define XMC4_CCU41_CC42_BASE 0x40010300 +#define XMC4_CCU41_CC43_BASE 0x40010400 +#define XMC4_CCU42_BASE 0x40014000 +#define XMC4_CCU42_CC40_BASE 0x40014100 +#define XMC4_CCU42_CC41_BASE 0x40014200 +#define XMC4_CCU42_CC42_BASE 0x40014300 +#define XMC4_CCU42_CC43_BASE 0x40014400 +#define XMC4_CCU80_BASE 0x40020000 +#define XMC4_CCU80_CC80_BASE 0x40020100 +#define XMC4_CCU80_CC81_BASE 0x40020200 +#define XMC4_CCU80_CC82_BASE 0x40020300 +#define XMC4_CCU80_CC83_BASE 0x40020400 +#define XMC4_CCU81_BASE 0x40024000 +#define XMC4_CCU81_CC80_BASE 0x40024100 +#define XMC4_CCU81_CC81_BASE 0x40024200 +#define XMC4_CCU81_CC82_BASE 0x40024300 +#define XMC4_CCU81_CC83_BASE 0x40024400 +#define XMC4_POSIF0_BASE 0x40028000 +#define XMC4_POSIF1_BASE 0x4002c000 +#define XMC4_USIC0_BASE 0x40030008 +#define XMC4_USIC0_CH0_BASE 0x40030000 +#define XMC4_USIC0_CH1_BASE 0x40030200 +#define XMC4_ERU1_BASE 0x40044000 + +#define XMC4_PBA1_BASE 0x48000000 +#define XMC4_CCU43_BASE 0x48004000 +#define XMC4_CCU43_CC40_BASE 0x48004100 +#define XMC4_CCU43_CC41_BASE 0x48004200 +#define XMC4_CCU43_CC42_BASE 0x48004300 +#define XMC4_CCU43_CC43_BASE 0x48004400 +#define XMC4_LEDTS0_BASE 0x48010000 +#define XMC4_CAN_BASE 0x48014000 +#define XMC4_CAN_NODE0_BASE 0x48014200 +#define XMC4_CAN_NODE1_BASE 0x48014300 +#define XMC4_CAN_NODE2_BASE 0x48014400 +#define XMC4_CAN_NODE3_BASE 0x48014500 +#define XMC4_CAN_NODE4_BASE 0x48014600 +#define XMC4_CAN_NODE5_BASE 0x48014700 +#define XMC4_CAN_MO_BASE 0x48015000 +#define XMC4_DAC_BASE 0x48018000 +#define XMC4_SDMMC_BASE 0x4801c000 +#define XMC4_USIC1_CH0_BASE 0x48020000 +#define XMC4_USIC1_BASE 0x48020008 +#define XMC4_USIC1_CH1_BASE 0x48020200 +#define XMC4_USIC2_CH0_BASE 0x48024000 +#define XMC4_USIC2_BASE 0x48024008 +#define XMC4_USIC2_CH1_BASE 0x48024200 +#define XMC4_PORT0_BASE 0x48028000 +#define XMC4_PORT1_BASE 0x48028100 +#define XMC4_PORT2_BASE 0x48028200 +#define XMC4_PORT3_BASE 0x48028300 +#define XMC4_PORT4_BASE 0x48028400 +#define XMC4_PORT5_BASE 0x48028500 +#define XMC4_PORT6_BASE 0x48028600 +#define XMC4_PORT7_BASE 0x48028700 +#define XMC4_PORT8_BASE 0x48028800 +#define XMC4_PORT9_BASE 0x48028900 +#define XMC4_PORT14_BASE 0x48028e00 +#define XMC4_PORT15_BASE 0x48028f00 + +#define XMC4_SCU_GENERAL_BASE 0x50004000 +#define XMC4_ETH0_CON_BASE 0x50004040 +#define XMC4_SCU_INTERRUPT_BASE 0x50004074 +#define XMC4_SDMMC_CON_BASE 0x500040b4 +#define XMC4_SCU_PARITY_BASE 0x5000413c +#define XMC4_SCU_TRAP_BASE 0x50004160 +#define XMC4_SCU_POWER_BASE 0x50004200 +#define XMC4_SCU_HIBERNATE_BASE 0x50004300 +#define XMC4_SCU_RESET_BASE 0x50004400 +#define XMC4_SCU_CLK_BASE 0x50004600 +#define XMC4_SCU_OSC_BASE 0x50004700 +#define XMC4_SCU_PLL_BASE 0x50004710 +#define XMC4_ERU0_BASE 0x50004800 +#define XMC4_DLR_BASE 0x50004900 +#define XMC4_RTC_BASE 0x50004a00 +#define XMC4_WDT_BASE 0x50008000 +#define XMC4_ETH0_BASE 0x5000c000 +#define XMC4_USB0_BASE 0x50040000 +#define XMC4_USB0_CH0_BASE 0x50040500 +#define XMC4_USB0_CH1_BASE 0x50040520 +#define XMC4_USB0_CH2_BASE 0x50040540 +#define XMC4_USB0_CH3_BASE 0x50040560 +#define XMC4_USB0_CH4_BASE 0x50040580 +#define XMC4_USB0_CH5_BASE 0x500405a0 +#define XMC4_USB0_CH6_BASE 0x500405c0 +#define XMC4_USB0_CH7_BASE 0x500405e0 +#define XMC4_USB0_CH8_BASE 0x50040600 +#define XMC4_USB0_CH9_BASE 0x50040620 +#define XMC4_USB0_CH10_BASE 0x50040640 +#define XMC4_USB0_CH11_BASE 0x50040660 +#define XMC4_USB0_CH12_BASE 0x50040680 +#define XMC4_USB0_CH13_BASE 0x500406a0 +#define XMC4_USB_EP_BASE 0x50040900 +#define XMC4_USB0_EP1_BASE 0x50040920 +#define XMC4_USB0_EP2_BASE 0x50040940 +#define XMC4_USB0_EP3_BASE 0x50040960 +#define XMC4_USB0_EP4_BASE 0x50040980 +#define XMC4_USB0_EP5_BASE 0x500409a0 +#define XMC4_USB0_EP6_BASE 0x500409c0 +#define XMC4_GPDMA0_CH0_BASE 0x50014000 +#define XMC4_GPDMA0_CH1_BASE 0x50014058 +#define XMC4_GPDMA0_CH2_BASE 0x500140b0 +#define XMC4_GPDMA0_CH3_BASE 0x50014108 +#define XMC4_GPDMA0_CH4_BASE 0x50014160 +#define XMC4_GPDMA0_CH5_BASE 0x500141b8 +#define XMC4_GPDMA0_CH6_BASE 0x50014210 +#define XMC4_GPDMA0_CH7_BASE 0x50014268 +#define XMC4_GPDMA0_BASE 0x500142c0 +#define XMC4_GPDMA1_CH0_BASE 0x50018000 +#define XMC4_GPDMA1_CH1_BASE 0x50018058 +#define XMC4_GPDMA1_CH2_BASE 0x500180b0 +#define XMC4_GPDMA1_CH3_BASE 0x50018108 +#define XMC4_GPDMA1_BASE 0x500182c0 +#define XMC4_FCE_BASE 0x50020000 +#define XMC4_FCE_KE0_BASE 0x50020020 +#define XMC4_FCE_KE1_BASE 0x50020040 +#define XMC4_FCE_KE2_BASE 0x50020060 +#define XMC4_FCE_KE3_BASE 0x50020080 + +#define XMC4_PMU0_BASE 0x58000508 +#define XMC4_FLASH0_BASE 0x58001000 +#define XMC4_PREF_BASE 0x58004000 +#define XMC4_EBU_BASE 0x58008000 + +#define XMC4_PPB_BASE 0xe000e000 + +#endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */ diff --git a/arch/arm/src/xmc4/chip/xmc4_scu.h b/arch/arm/src/xmc4/chip/xmc4_scu.h index a3e6d116e7..ab5b771995 100644 --- a/arch/arm/src/xmc4/chip/xmc4_scu.h +++ b/arch/arm/src/xmc4/chip/xmc4_scu.h @@ -4,6 +4,8 @@ * Copyright (C) 2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * + * Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -31,6 +33,20 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use with + * Infineon's microcontrollers. This file can be freely distributed within + * development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, + * OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * ************************************************************************************/ #ifndef __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H @@ -48,406 +64,516 @@ ************************************************************************************/ /* Register Offsets *****************************************************************/ - -#define XMC4_GCU_OFFSET 0x0000 /* Offset address of General Control Unit */ -#define XMC4_PCU_OFFSET 0x0200 /* Offset address of Power Control Unit */ -#define XMC4_HCU_OFFSET 0x0300 /* Offset address of Hibernate Control Unit */ -#define XMC4_RCU_OFFSET 0x0400 /* Offset address of Reset Control Unit */ -#define XMC4_CCU_OFFSET 0x0600 /* Offset address of Clock Control Unit */ - /* General SCU Registers */ -#define XMC4_GCU_ID_OFFSET 0x0000 /* Module Identification Register */ -#define XMC4_GCU_IDCHIP_OFFSET 0x0004 /* Chip ID */ -#define XMC4_GCU_IDMANUF_OFFSET 0x0008 /* Manufactory ID */ -#define XMC4_GCU_STCON_OFFSET 0x0010 /* Start-up Control */ -#define XMC4_GCU_GPR0_OFFSET 0x002c /* General Purpose Register 0 */ -#define XMC4_GCU_GPR1_OFFSET 0x0030 /* General Purpose Register 1 */ -#define XMC4_GCU_ETH0CON_OFFSET 0x0040 /* Ethernet 0 Port Control */ -#define XMC4_GCU_CCUCON_OFFSET 0x004c /* CCUx Global Start Control Register */ -#define XMC4_GCU_SRSTAT_OFFSET 0x0074 /* Service Request Status */ -#define XMC4_GCU_SRRAW_OFFSET 0x0078 /* RAW Service Request Status */ -#define XMC4_GCU_SRMSK_OFFSET 0x007c /* Service Request Mask */ -#define XMC4_GCU_SRCLR_OFFSET 0x0080 /* Service Request Clear */ -#define XMC4_GCU_SRSET_OFFSET 0x0084 /* Service Request Set */ -#define XMC4_GCU_NMIREQEN_OFFSET 0x0088 /* Enable Promoting Events to NMI Request */ -#define XMC4_GCU_DTSCON_OFFSET 0x008c /* DTS Control */ -#define XMC4_GCU_DTSSTAT_OFFSET 0x0090 /* DTS Status */ -#define XMC4_GCU_SDMMCDEL_OFFSET 0x009c /* SD-MMC Delay Control Register */ -#define XMC4_GCU_G0ORCEN_OFFSET 0x00a0 /* Out-Of-Range Comparator Enable Register 0 */ -#define XMC4_GCU_G1ORCEN_OFFSET 0x00a4 /* Out-Of-Range Comparator Enable Register 1 */ -#define XMC4_GCU_MIRRSTS_OFFSET 0x00c4 /* Mirror Update Status Register */ -#define XMC4_GCU_RMACR_OFFSET 0x00c8 /* Retention Memory Access Control Register */ -#define XMC4_GCU_RMADATA_OFFSET 0x00cc /* Retention Memory Access Data Register */ -#define XMC4_GCU_PEEN_OFFSET 0x013c /* Parity Error Enable Register */ -#define XMC4_GCU_MCHKCON_OFFSET 0x0140 /* Memory Checking Control Register */ -#define XMC4_GCU_PETE_OFFSET 0x0144 /* Parity Error Trap Enable Register */ -#define XMC4_GCU_PERSTEN_OFFSET 0x0148 /* Reset upon Parity Error Enable Register */ -#define XMC4_GCU_PEFLAG_OFFSET 0x0150 /* Parity Error Control Register */ -#define XMC4_GCU_PMTPR_OFFSET 0x0154 /* Parity Memory Test Pattern Register */ -#define XMC4_GCU_PMTSR_OFFSET 0x0158 /* Parity Memory Test Select Register */ -#define XMC4_GCU_TRAPSTAT_OFFSET 0x0160 /* Trap Status Register */ -#define XMC4_GCU_TRAPRAW_OFFSET 0x0164 /* Trap Raw Status Register */ -#define XMC4_GCU_TRAPDIS_OFFSET 0x0168 /* Trap Mask Register */ -#define XMC4_GCU_TRAPCLR_OFFSET 0x016c /* Trap Clear Register */ -#define XMC4_GCU_TRAPSET_OFFSET 0x0170 /* Trap Set Register */ +#define XMC4_SCU_ID_OFFSET 0x0000 /* Module Identification Register */ +#define XMC4_SCU_IDCHIP_OFFSET 0x0004 /* Chip ID */ +#define XMC4_SCU_IDMANUF_OFFSET 0x0008 /* Manufactory ID */ +#define XMC4_SCU_STCON_OFFSET 0x0010 /* Start-up Control */ +#define XMC4_SCU_GPR0_OFFSET 0x002c /* General Purpose Register 0 */ +#define XMC4_SCU_GPR1_OFFSET 0x0030 /* General Purpose Register 1 */ +#define XMC4_SCU_ETH0CON_OFFSET 0x0040 /* Ethernet 0 Port Control */ +#define XMC4_SCU_CCUCON_OFFSET 0x004c /* CCUx Global Start Control Register */ +#define XMC4_SCU_DTSCON_OFFSET 0x008c /* DTS Control */ +#define XMC4_SCU_DTSSTAT_OFFSET 0x0090 /* DTS Status */ +#define XMC4_SCU_SDMMCDEL_OFFSET 0x009c /* SD-MMC Delay Control Register */ +#define XMC4_SCU_G0ORCEN_OFFSET 0x00a0 /* Out-Of-Range Comparator Enable Register 0 */ +#define XMC4_SCU_G1ORCEN_OFFSET 0x00a4 /* Out-Of-Range Comparator Enable Register 1 */ +#define XMC4_SCU_MIRRSTS_OFFSET 0x00c4 /* Mirror Update Status Register */ +#define XMC4_SCU_RMACR_OFFSET 0x00c8 /* Retention Memory Access Control Register */ +#define XMC4_SCU_RMADATA_OFFSET 0x00cc /* Retention Memory Access Data Register */ -/* PCU Registers */ +/* Ethernet Control SCU Resters */ -#define XMC4_PCU_PWRSTAT_OFFSET 0x0000 /* Power Status Register */ -#define XMC4_PCU_PWRSET_OFFSET 0x0004 /* Power Set Control Register */ -#define XMC4_PCU_PWRCLR_OFFSET 0x0008 /* Power Clear Control Register */ -#define XMC4_PCU_EVRSTAT_OFFSET 0x0010 /* EVR Status Register */ -#define XMC4_PCU_EVRVADCSTAT_OFFSET 0x0014 /* EVR VADC Status Register */ -#define XMC4_PCU_PWRMON_OFFSET 0x002c /* Power Monitor Value */ +#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */ -/* HCU Registers */ +/* Interrupt Control SCU Registers */ -#define XMC4_HCU_HDSTAT_OFFSET 0x0000 /* Hibernate Domain Status Register */ -#define XMC4_HCU_HDCLR_OFFSET 0x0004 /* Hibernate Domain Status Clear Register */ -#define XMC4_HCU_HDSET_OFFSET 0x0008 /* Hibernate Domain Status Set Register */ -#define XMC4_HCU_HDCR_OFFSET 0x000c /* Hibernate Domain Control Register */ -#define XMC4_HCU_OSCSICTRL_OFFSET 0x0014 /* Internal 32.768 kHz Clock Source Control Register */ -#define XMC4_HCU_OSCULSTAT_OFFSET 0x0018 /* OSC_ULP Status Register */ -#define XMC4_HCU_OSCULCTRL_OFFSET 0x001c /* OSC_ULP Control Register */ +#define XMC4_SCU_SRSTAT_OFFSET 0x0000 /* Service Request Status */ +#define XMC4_SCU_SRRAW_OFFSET 0x0004 /* RAW Service Request Status */ +#define XMC4_SCU_SRMSK_OFFSET 0x0008 /* Service Request Mask */ +#define XMC4_SCU_SRCLR_OFFSET 0x000c /* Service Request Clear */ +#define XMC4_SCU_SRSET_OFFSET 0x0010 /* Service Request Set */ +#define XMC4_SCU_NMIREQEN_OFFSET 0x0014 /* Enable Promoting Events to NMI Request */ -/* RCU Registers */ +/* SDMMC Control SCU Registers */ -#define XMC4_RCU_RSTSTAT_OFFSET 0x0000 /* System Reset Status */ -#define XMC4_RCU_RSTSET_OFFSET 0x0004 /* Reset Set Register */ -#define XMC4_RCU_RSTCLR_OFFSET 0x0008 /* Reset Clear Register */ -#define XMC4_RCU_PRSTAT0_OFFSET 0x000c /* Peripheral Reset Status Register 0 */ -#define XMC4_RCU_PRSET0_OFFSET 0x0010 /* Peripheral Reset Set Register 0 */ -#define XMC4_RCU_PRCLR0_OFFSET 0x0014 /* Peripheral Reset Clear Register 0 */ -#define XMC4_RCU_PRSTAT1_OFFSET 0x0018 /* Peripheral Reset Status Register 1 */ -#define XMC4_RCU_PRSET1_OFFSET 0x001c /* Peripheral Reset Set Register 1 */ -#define XMC4_RCU_PRCLR1_OFFSET 0x0020 /* Peripheral Reset Clear Register 1 */ -#define XMC4_RCU_PRSTAT2_OFFSET 0x0024 /* Peripheral Reset Status Register 2 */ -#define XMC4_RCU_PRSET2_OFFSET 0x0028 /* Peripheral Reset Set Register 2 */ -#define XMC4_RCU_PRCLR2_OFFSET 0x002c /* Peripheral Reset Clear Register 2 */ -#define XMC4_RCU_PRSTAT3_OFFSET 0x0030 /* Peripheral Reset Status Register 3 */ -#define XMC4_RCU_PRSET3_OFFSET 0x0034 /* Peripheral Reset Set Register 3 */ -#define XMC4_RCU_PRCLR3_OFFSET 0x0038 /* Peripheral Reset Clear Register 3 */ +#define XMC4_SCU_SDMMCCON_OFFSET 0x0000 /* SDMMC Configuration */ -/* CCU Registers */ +/* Parity Control Registers */ -#define XMC4_CCU_CLKSTAT_OFFSET 0x0000 /* Clock Status Register */ -#define XMC4_CCU_CLKSET_OFFSET 0x0004 /* Clock Set Control Register */ -#define XMC4_CCU_CLKCLR_OFFSET 0x0008 /* Clock clear Control Register */ -#define XMC4_CCU_SYSCLKCR_OFFSET 0x000c /* System Clock Control */ -#define XMC4_CCU_CPUCLKCR_OFFSET 0x0010 /* CPU Clock Control */ -#define XMC4_CCU_PBCLKCR_OFFSET 0x0014 /* Peripheral Bus Clock Control */ -#define XMC4_CCU_USBCLKCR_OFFSET 0x0018 /* USB Clock Control */ -#define XMC4_CCU_EBUCLKCR_OFFSET 0x001c /* EBU Clock Control */ -#define XMC4_CCU_CCUCLKCR_OFFSET 0x0020 /* CCU Clock Control */ -#define XMC4_CCU_WDTCLKCR_OFFSET 0x0024 /* WDT Clock Control */ -#define XMC4_CCU_EXTCLKCR_OFFSET 0x0028 /* External clock Control Register */ -#define XMC4_CCU_SLEEPCR_OFFSET 0x0030 /* Sleep Control Register */ -#define XMC4_CCU_DSLEEPCR_OFFSET 0x0034 /* Deep Sleep Control Register */ -#define XMC4_CCU_OSCHPSTAT_OFFSET 0x0100 /* OSC_HP Status Register */ -#define XMC4_CCU_OSCHPCTRL_OFFSET 0x0104 /* OSC_HP Control Register */ -#define XMC4_CCU_CLKCALCONST_OFFSET 0x010c /* Clock Calibration Constant Register */ -#define XMC4_CCU_PLLSTAT_OFFSET 0x0110 /* System PLL Status Register */ -#define XMC4_CCU_PLLCON0_OFFSET 0x0114 /* System PLL Configuration 0 Register */ -#define XMC4_CCU_PLLCON1_OFFSET 0x0118 /* System PLL Configuration 1 Register */ -#define XMC4_CCU_PLLCON2_OFFSET 0x011c /* System PLL Configuration 2 Register */ -#define XMC4_CCU_USBPLLSTAT_OFFSET 0x0120 /* USB PLL Status Register */ -#define XMC4_CCU_USBPLLCON_OFFSET 0x0124 /* USB PLL Control Register */ -#define XMC4_CCU_CLKMXSTAT_OFFSET 0x0138 /* Clock Multiplexing Status Register */ +#define XMC4_SCU_PEEN_OFFSET 0x0000 /* Parity Error Enable Register */ +#define XMC4_SCU_MCHKCON_OFFSET 0x0004 /* Memory Checking Control Register */ +#define XMC4_SCU_PETE_OFFSET 0x0008 /* Parity Error Trap Enable Register */ +#define XMC4_SCU_PERSTEN_OFFSET 0x000c /* Reset upon Parity Error Enable Register */ +#define XMC4_SCU_PEFLAG_OFFSET 0x0014 /* Parity Error Control Register */ +#define XMC4_SCU_PMTPR_OFFSET 0x0018 /* Parity Memory Test Pattern Register */ +#define XMC4_SCU_PMTSR_OFFSET 0x001c /* Parity Memory Test Select Register */ + +/* Trap Control Registers */ + +#define XMC4_SCU_TRAPSTAT_OFFSET 0x0000 /* Trap Status Register */ +#define XMC4_SCU_TRAPRAW_OFFSET 0x0004 /* Trap Raw Status Register */ +#define XMC4_SCU_TRAPDIS_OFFSET 0x0008 /* Trap Mask Register */ +#define XMC4_SCU_TRAPCLR_OFFSET 0x000c /* Trap Clear Register */ +#define XMC4_SCU_TRAPSET_OFFSET 0x0010 /* Trap Set Register */ + +/* Power Control SCU Registers */ + +#define XMC4_SCU_PWRSTAT_OFFSET 0x0000 /* Power Status Register */ +#define XMC4_SCU_PWRSET_OFFSET 0x0004 /* Power Set Control Register */ +#define XMC4_SCU_PWRCLR_OFFSET 0x0008 /* Power Clear Control Register */ +#define XMC4_SCU_EVRSTAT_OFFSET 0x0010 /* EVR Status Register */ +#define XMC4_SCU_EVRVADCSTAT_OFFSET 0x0014 /* EVR VADC Status Register */ +#define XMC4_SCU_PWRMON_OFFSET 0x002c /* Power Monitor Value */ + +/* Hibernation SCU Registers */ + +#define XMC4_SCU_HDSTAT_OFFSET 0x0000 /* Hibernate Domain Status Register */ +#define XMC4_SCU_HDCLR_OFFSET 0x0004 /* Hibernate Domain Status Clear Register */ +#define XMC4_SCU_HDSET_OFFSET 0x0008 /* Hibernate Domain Status Set Register */ +#define XMC4_SCU_HDCR_OFFSET 0x000c /* Hibernate Domain Control Register */ +#define XMC4_SCU_OSCSICTRL_OFFSET 0x0014 /* Internal 32.768 kHz Clock Source Control Register */ +#define XMC4_SCU_OSCULSTAT_OFFSET 0x0018 /* OSC_ULP Status Register */ +#define XMC4_SCU_OSCULCTRL_OFFSET 0x001c /* OSC_ULP Control Register */ + +/* Reset SCU Registers */ + +#define XMC4_SCU_RSTSTAT_OFFSET 0x0000 /* System Reset Status */ +#define XMC4_SCU_RSTSET_OFFSET 0x0004 /* Reset Set Register */ +#define XMC4_SCU_RSTCLR_OFFSET 0x0008 /* Reset Clear Register */ +#define XMC4_SCU_PRSTAT0_OFFSET 0x000c /* Peripheral Reset Status Register 0 */ +#define XMC4_SCU_PRSET0_OFFSET 0x0010 /* Peripheral Reset Set Register 0 */ +#define XMC4_SCU_PRCLR0_OFFSET 0x0014 /* Peripheral Reset Clear Register 0 */ +#define XMC4_SCU_PRSTAT1_OFFSET 0x0018 /* Peripheral Reset Status Register 1 */ +#define XMC4_SCU_PRSET1_OFFSET 0x001c /* Peripheral Reset Set Register 1 */ +#define XMC4_SCU_PRCLR1_OFFSET 0x0020 /* Peripheral Reset Clear Register 1 */ +#define XMC4_SCU_PRSTAT2_OFFSET 0x0024 /* Peripheral Reset Status Register 2 */ +#define XMC4_SCU_PRSET2_OFFSET 0x0028 /* Peripheral Reset Set Register 2 */ +#define XMC4_SCU_PRCLR2_OFFSET 0x002c /* Peripheral Reset Clear Register 2 */ +#define XMC4_SCU_PRSTAT3_OFFSET 0x0030 /* Peripheral Reset Status Register 3 */ +#define XMC4_SCU_PRSET3_OFFSET 0x0034 /* Peripheral Reset Set Register 3 */ +#define XMC4_SCU_PRCLR3_OFFSET 0x0038 /* Peripheral Reset Clear Register 3 */ + +/* Clock Control SCU Registers */ + +#define XMC4_SCU_CLKSTAT_OFFSET 0x0000 /* Clock Status Register */ +#define XMC4_SCU_CLKSET_OFFSET 0x0004 /* Clock Set Control Register */ +#define XMC4_SCU_CLKCLR_OFFSET 0x0008 /* Clock clear Control Register */ +#define XMC4_SCU_SYSCLKCR_OFFSET 0x000c /* System Clock Control */ +#define XMC4_SCU_CPUCLKCR_OFFSET 0x0010 /* CPU Clock Control */ +#define XMC4_SCU_PBCLKCR_OFFSET 0x0014 /* Peripheral Bus Clock Control */ +#define XMC4_SCU_USBCLKCR_OFFSET 0x0018 /* USB Clock Control */ +#define XMC4_SCU_EBUCLKCR_OFFSET 0x001c /* EBU Clock Control */ +#define XMC4_SCU_CCUCLKCR_OFFSET 0x0020 /* CCU Clock Control */ +#define XMC4_SCU_WDTCLKCR_OFFSET 0x0024 /* WDT Clock Control */ +#define XMC4_SCU_EXTCLKCR_OFFSET 0x0028 /* External clock Control Register */ +#define XMC4_SCU_SLEEPCR_OFFSET 0x0030 /* Sleep Control Register */ +#define XMC4_SCU_DSLEEPCR_OFFSET 0x0034 /* Deep Sleep Control Register */ +#define XMC4_SCU_CGATSTAT0_OFFSET 0x0040 /* Peripheral 0 Clock Gating Status */ +#define XMC4_SCU_CGATSET0_OFFSET 0x0044 /* Peripheral 0 Clock Gating Set */ +#define XMC4_SCU_CGATCLR0_OFFSET 0x0048 /* Peripheral 0 Clock Gating Clear */ +#define XMC4_SCU_CGATSTAT1_OFFSET 0x004c /* Peripheral 1 Clock Gating Status */ +#define XMC4_SCU_CGATSET1_OFFSET 0x0050 /* Peripheral 1 Clock Gating Set */ +#define XMC4_SCU_CGATCLR1_OFFSET 0x0054 /* Peripheral 1 Clock Gating Clear */ +#define XMC4_SCU_CGATSTAT2_OFFSET 0x0058 /* Peripheral 2 Clock Gating Status */ +#define XMC4_SCU_CGATSET2_OFFSET 0x005c /* Peripheral 2 Clock Gating Set */ +#define XMC4_SCU_CGATCLR2_OFFSET 0x0060 /* Peripheral 2 Clock Gating Clear */ +#define XMC4_SCU_CGATSTAT3_OFFSET 0x0064 /* Peripheral 3 Clock Gating Status */ +#define XMC4_SCU_CGATSET3_OFFSET 0x0068 /* Peripheral 3 Clock Gating Set */ +#define XMC4_SCU_CGATCLR3_OFFSET 0x006c /* Peripheral 3 Clock Gating Clear */ + +/* Oscillator Control SCU Registers */ + +#define XMC4_OCU_OSCHPSTAT_OFFSET 0x0000 /* OSC_HP Status Register */ +#define XMC4_OCU_OSCHPCTRL_OFFSET 0x0004 /* OSC_HP Control Register */ +#define XMC4_OCU_CLKCALCONST_OFFSET 0x000c /* Clock Calibration Constant Register */ + +/* PLL Control SCU Registers */ + +#define XMC4_SCU_PLLSTAT_OFFSET 0x0000 /* System PLL Status Register */ +#define XMC4_SCU_PLLCON0_OFFSET 0x0004 /* System PLL Configuration 0 Register */ +#define XMC4_SCU_PLLCON1_OFFSET 0x0008 /* System PLL Configuration 1 Register */ +#define XMC4_SCU_PLLCON2_OFFSET 0x000c /* System PLL Configuration 2 Register */ +#define XMC4_SCU_USBPLLSTAT_OFFSET 0x0010 /* USB PLL Status Register */ +#define XMC4_SCU_USBPLLCON_OFFSET 0x0014 /* USB PLL Control Register */ +#define XMC4_SCU_CLKMXSTAT_OFFSET 0x0028 /* Clock Multiplexing Status Register */ /* Register Addresses ***************************************************************/ - -#define XMC4_GCU_BASE (XMC4_SCU_BASE+XMC4_GCU_OFFSET) -#define XMC4_PCU_BASE (XMC4_SCU_BASE+XMC4_PCU_OFFSET) -#define XMC4_HCU_BASE (XMC4_SCU_BASE+XMC4_HCU_OFFSET) -#define XMC4_RCU_BASE (XMC4_SCU_BASE+XMC4_RCU_OFFSET) -#define XMC4_CCU_BASE (XMC4_SCU_BASE+XMC4_CCU_OFFSET) - /* General SCU Registers */ -#define XMC4_GCU_ID (XMC4_GCU_BASE+XMC4_GCU_ID_OFFSET) -#define XMC4_GCU_IDCHIP (XMC4_GCU_BASE+XMC4_GCU_IDCHIP_OFFSET) -#define XMC4_GCU_IDMANUF (XMC4_GCU_BASE+XMC4_GCU_IDMANUF_OFFSET) -#define XMC4_GCU_STCON (XMC4_GCU_BASE+XMC4_GCU_STCON_OFFSET) -#define XMC4_GCU_GPR0 (XMC4_GCU_BASE+XMC4_GCU_GPR0_OFFSET) -#define XMC4_GCU_GPR1 (XMC4_GCU_BASE+XMC4_GCU_GPR1_OFFSET) -#define XMC4_GCU_ETH0CON (XMC4_GCU_BASE+XMC4_GCU_ETH0CON_OFFSET) -#define XMC4_GCU_CCUCON (XMC4_GCU_BASE+XMC4_GCU_CCUCON_OFFSET) -#define XMC4_GCU_SRSTAT (XMC4_GCU_BASE+XMC4_GCU_SRSTAT_OFFSET) -#define XMC4_GCU_SRRAW (XMC4_GCU_BASE+XMC4_GCU_SRRAW_OFFSET) -#define XMC4_GCU_SRMSK (XMC4_GCU_BASE+XMC4_GCU_SRMSK_OFFSET) -#define XMC4_GCU_SRCLR (XMC4_GCU_BASE+XMC4_GCU_SRCLR_OFFSET) -#define XMC4_GCU_SRSET (XMC4_GCU_BASE+XMC4_GCU_SRSET_OFFSET) -#define XMC4_GCU_NMIREQEN (XMC4_GCU_BASE+XMC4_GCU_NMIREQEN_OFFSET) -#define XMC4_GCU_DTSCON (XMC4_GCU_BASE+XMC4_GCU_DTSCON_OFFSET) -#define XMC4_GCU_DTSSTAT (XMC4_GCU_BASE+XMC4_GCU_DTSSTAT_OFFSET) -#define XMC4_GCU_SDMMCDEL (XMC4_GCU_BASE+XMC4_GCU_SDMMCDEL_OFFSET) -#define XMC4_GCU_G0ORCEN (XMC4_GCU_BASE+XMC4_GCU_G0ORCEN_OFFSET) -#define XMC4_GCU_G1ORCEN (XMC4_GCU_BASE+XMC4_GCU_G1ORCEN_OFFSET) -#define XMC4_GCU_MIRRSTS (XMC4_GCU_BASE+XMC4_GCU_MIRRSTS_OFFSET) -#define XMC4_GCU_RMACR (XMC4_GCU_BASE+XMC4_GCU_RMACR_OFFSET) -#define XMC4_GCU_RMADATA (XMC4_GCU_BASE+XMC4_GCU_RMADATA_OFFSET) -#define XMC4_GCU_PEEN (XMC4_GCU_BASE+XMC4_GCU_PEEN_OFFSET) -#define XMC4_GCU_MCHKCON (XMC4_GCU_BASE+XMC4_GCU_MCHKCON_OFFSET) -#define XMC4_GCU_PETE (XMC4_GCU_BASE+XMC4_GCU_PETE_OFFSET) -#define XMC4_GCU_PERSTEN (XMC4_GCU_BASE+XMC4_GCU_PERSTEN_OFFSET) -#define XMC4_GCU_PEFLAG (XMC4_GCU_BASE+XMC4_GCU_PEFLAG_OFFSET) -#define XMC4_GCU_PMTPR (XMC4_GCU_BASE+XMC4_GCU_PMTPR_OFFSET) -#define XMC4_GCU_PMTSR (XMC4_GCU_BASE+XMC4_GCU_PMTSR_OFFSET) -#define XMC4_GCU_TRAPSTAT (XMC4_GCU_BASE+XMC4_GCU_TRAPSTAT_OFFSET) -#define XMC4_GCU_TRAPRAW (XMC4_GCU_BASE+XMC4_GCU_TRAPRAW_OFFSET) -#define XMC4_GCU_TRAPDIS (XMC4_GCU_BASE+XMC4_GCU_TRAPDIS_OFFSET) -#define XMC4_GCU_TRAPCLR (XMC4_GCU_BASE+XMC4_GCU_TRAPCLR_OFFSET) -#define XMC4_GCU_TRAPSET (XMC4_GCU_BASE+XMC4_GCU_TRAPSET_OFFSET) +#define XMC4_SCU_ID (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ID_OFFSET) +#define XMC4_SCU_IDCHIP (XMC4_SCU_GENERAL_BASE+XMC4_SCU_IDCHIP_OFFSET) +#define XMC4_SCU_IDMANUF (XMC4_SCU_GENERAL_BASE+XMC4_SCU_IDMANUF_OFFSET) +#define XMC4_SCU_STCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_STCON_OFFSET) +#define XMC4_SCU_GPR0 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_GPR0_OFFSET) +#define XMC4_SCU_GPR1 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_GPR1_OFFSET) +#define XMC4_SCU_ETH0CON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ETH0CON_OFFSET) +#define XMC4_SCU_CCUCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_CCUCON_OFFSET) +#define XMC4_SCU_DTSCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_DTSCON_OFFSET) +#define XMC4_SCU_DTSSTAT (XMC4_SCU_GENERAL_BASE+XMC4_SCU_DTSSTAT_OFFSET) +#define XMC4_SCU_SDMMCDEL (XMC4_SCU_GENERAL_BASE+XMC4_SCU_SDMMCDEL_OFFSET) +#define XMC4_SCU_G0ORCEN (XMC4_SCU_GENERAL_BASE+XMC4_SCU_G0ORCEN_OFFSET) +#define XMC4_SCU_G1ORCEN (XMC4_SCU_GENERAL_BASE+XMC4_SCU_G1ORCEN_OFFSET) +#define XMC4_SCU_MIRRSTS (XMC4_SCU_GENERAL_BASE+XMC4_SCU_MIRRSTS_OFFSET) +#define XMC4_SCU_RMACR (XMC4_SCU_GENERAL_BASE+XMC4_SCU_RMACR_OFFSET) +#define XMC4_SCU_RMADATA (XMC4_SCU_GENERAL_BASE+XMC4_SCU_RMADATA_OFFSET) -/* PCU Registers */ +/* Ethernet Control SCU Registers */ -#define XMC4_PCU_PWRSTAT (XMC4_PCU_BASE+XMC4_PCU_PWRSTAT_OFFSET) -#define XMC4_PCU_PWRSET (XMC4_PCU_BASE+XMC4_PCU_PWRSET_OFFSET) -#define XMC4_PCU_PWRCLR (XMC4_PCU_BASE+XMC4_PCU_PWRCLR_OFFSET) -#define XMC4_PCU_EVRSTAT (XMC4_PCU_BASE+XMC4_PCU_EVRSTAT_OFFSET) -#define XMC4_PCU_EVRVADCSTAT (XMC4_PCU_BASE+XMC4_PCU_EVRVADCSTAT_OFFSET) -#define XMC4_PCU_PWRMON (XMC4_PCU_BASE+XMC4_PCU_PWRMON_OFFSET) +#define XMC4_SCU_ETHCON (XMC4_ETH0_CON_BASE+XMC4_SCU_ETHCON_OFFSET) -/* HCU Registers */ +/* Parity Control Registers */ -#define XMC4_HCU_HDSTAT (XMC4_HCU_BASE+XMC4_HCU_HDSTAT_OFFSET) -#define XMC4_HCU_HDCLR (XMC4_HCU_BASE+XMC4_HCU_HDCLR_OFFSET) -#define XMC4_HCU_HDSET (XMC4_HCU_BASE+XMC4_HCU_HDSET_OFFSET) -#define XMC4_HCU_HDCR (XMC4_HCU_BASE+XMC4_HCU_HDCR_OFFSET) -#define XMC4_HCU_OSCSICTRL (XMC4_HCU_BASE+XMC4_HCU_OSCSICTRL_OFFSET) -#define XMC4_HCU_OSCULSTAT (XMC4_HCU_BASE+XMC4_HCU_OSCULSTAT_OFFSET) -#define XMC4_HCU_OSCULCTRL (XMC4_HCU_BASE+XMC4_HCU_OSCULCTRL_OFFSET) +#define XMC4_SCU_PEEN (XMC4_SCU_PARITY_BASE+XMC4_SCU_PEEN_OFFSET) +#define XMC4_SCU_MCHKCON (XMC4_SCU_PARITY_BASE+XMC4_SCU_MCHKCON_OFFSET) +#define XMC4_SCU_PETE (XMC4_SCU_PARITY_BASE+XMC4_SCU_PETE_OFFSET) +#define XMC4_SCU_PERSTEN (XMC4_SCU_PARITY_BASE+XMC4_SCU_PERSTEN_OFFSET) +#define XMC4_SCU_PEFLAG (XMC4_SCU_PARITY_BASE+XMC4_SCU_PEFLAG_OFFSET) +#define XMC4_SCU_PMTPR (XMC4_SCU_PARITY_BASE+XMC4_SCU_PMTPR_OFFSET) +#define XMC4_SCU_PMTSR (XMC4_SCU_PARITY_BASE+XMC4_SCU_PMTSR_OFFSET) -/* RCU Registers */ +/* Trap Control Registers */ -#define XMC4_RCU_RSTSTAT (XMC4_RCU_BASE+XMC4_RCU_RSTSTAT_OFFSET) -#define XMC4_RCU_RSTSET (XMC4_RCU_BASE+XMC4_RCU_RSTSET_OFFSET) -#define XMC4_RCU_RSTCLR (XMC4_RCU_BASE+XMC4_RCU_RSTCLR_OFFSET) -#define XMC4_RCU_PRSTAT0 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT0_OFFSET) -#define XMC4_RCU_PRSET0 (XMC4_RCU_BASE+XMC4_RCU_PRSET0_OFFSET) -#define XMC4_RCU_PRCLR0 (XMC4_RCU_BASE+XMC4_RCU_PRCLR0_OFFSET) -#define XMC4_RCU_PRSTAT1 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT1_OFFSET) -#define XMC4_RCU_PRSET1 (XMC4_RCU_BASE+XMC4_RCU_PRSET1_OFFSET) -#define XMC4_RCU_PRCLR1 (XMC4_RCU_BASE+XMC4_RCU_PRCLR1_OFFSET) -#define XMC4_RCU_PRSTAT2 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT2_OFFSET) -#define XMC4_RCU_PRSET2 (XMC4_RCU_BASE+XMC4_RCU_PRSET2_OFFSET) -#define XMC4_RCU_PRCLR2 (XMC4_RCU_BASE+XMC4_RCU_PRCLR2_OFFSET) -#define XMC4_RCU_PRSTAT3 (XMC4_RCU_BASE+XMC4_RCU_PRSTAT3_OFFSET) -#define XMC4_RCU_PRSET3 (XMC4_RCU_BASE+XMC4_RCU_PRSET3_OFFSET) -#define XMC4_RCU_PRCLR3 (XMC4_RCU_BASE+XMC4_RCU_PRCLR3_OFFSET) +#define XMC4_SCU_TRAPSTAT (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPSTAT_OFFSET) +#define XMC4_SCU_TRAPRAW (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPRAW_OFFSET) +#define XMC4_SCU_TRAPDIS (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPDIS_OFFSET) +#define XMC4_SCU_TRAPCLR (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPCLR_OFFSET) +#define XMC4_SCU_TRAPSET (XMC4_SCU_TRAP_BASE+XMC4_SCU_TRAPSET_OFFSET) -/* CCU Registers */ +/* Ethernet Control SCU Resters */ -#define XMC4_CCU_CLKSTAT (XMC4_CCU_BASE+XMC4_CCU_CLKSTAT_OFFSET) -#define XMC4_CCU_CLKSET (XMC4_CCU_BASE+XMC4_CCU_CLKSET_OFFSET) -#define XMC4_CCU_CLKCLR (XMC4_CCU_BASE+XMC4_CCU_CLKCLR_OFFSET) -#define XMC4_CCU_SYSCLKCR (XMC4_CCU_BASE+XMC4_CCU_SYSCLKCR_OFFSET) -#define XMC4_CCU_CPUCLKCR (XMC4_CCU_BASE+XMC4_CCU_CPUCLKCR_OFFSET) -#define XMC4_CCU_PBCLKCR (XMC4_CCU_BASE+XMC4_CCU_PBCLKCR_OFFSET) -#define XMC4_CCU_USBCLKCR (XMC4_CCU_BASE+XMC4_CCU_USBCLKCR_OFFSET) -#define XMC4_CCU_EBUCLKCR (XMC4_CCU_BASE+XMC4_CCU_EBUCLKCR_OFFSET) -#define XMC4_CCU_CCUCLKCR (XMC4_CCU_BASE+XMC4_CCU_CCUCLKCR_OFFSET) -#define XMC4_CCU_WDTCLKCR (XMC4_CCU_BASE+XMC4_CCU_WDTCLKCR_OFFSET) -#define XMC4_CCU_EXTCLKCR (XMC4_CCU_BASE+XMC4_CCU_EXTCLKCR_OFFSET) -#define XMC4_CCU_SLEEPCR (XMC4_CCU_BASE+XMC4_CCU_SLEEPCR_OFFSET) -#define XMC4_CCU_DSLEEPCR (XMC4_CCU_BASE+XMC4_CCU_DSLEEPCR_OFFSET) -#define XMC4_CCU_OSCHPSTAT (XMC4_CCU_BASE+XMC4_CCU_OSCHPSTAT_OFFSET) -#define XMC4_CCU_OSCHPCTRL (XMC4_CCU_BASE+XMC4_CCU_OSCHPCTRL_OFFSET) -#define XMC4_CCU_CLKCALCONST (XMC4_CCU_BASE+XMC4_CCU_CLKCALCONST_OFFSET) -#define XMC4_CCU_PLLSTAT (XMC4_CCU_BASE+XMC4_CCU_PLLSTAT_OFFSET) -#define XMC4_CCU_PLLCON0 (XMC4_CCU_BASE+XMC4_CCU_PLLCON0_OFFSET) -#define XMC4_CCU_PLLCON1 (XMC4_CCU_BASE+XMC4_CCU_PLLCON1_OFFSET) -#define XMC4_CCU_PLLCON2 (XMC4_CCU_BASE+XMC4_CCU_PLLCON2_OFFSET) -#define XMC4_CCU_USBPLLSTAT (XMC4_CCU_BASE+XMC4_CCU_USBPLLSTAT_OFFSET) -#define XMC4_CCU_USBPLLCON (XMC4_CCU_BASE+XMC4_CCU_USBPLLCON_OFFSET) -#define XMC4_CCU_CLKMXSTAT (XMC4_CCU_BASE+XMC4_CCU_CLKMXSTAT_OFFSET) +#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */ +#define XMC4_SCU_ETHCON_OFFSET 0x0000 /* Ethernet 0 Port Control Register */ + +/* Interrupt Control SCU Registers */ + +#define XMC4_SCU_SRSTAT (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRSTAT_OFFSET) +#define XMC4_SCU_SRRAW (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRRAW_OFFSET) +#define XMC4_SCU_SRMSK (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRMSK_OFFSET) +#define XMC4_SCU_SRCLR (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRCLR_OFFSET) +#define XMC4_SCU_SRSET (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_SRSET_OFFSET) +#define XMC4_SCU_NMIREQEN (XMC4_SCU_INTERRUPT_BASE+XMC4_SCU_NMIREQEN_OFFSET) + +/* SDMMC Control SCU Registers */ + +#define XMC4_SCU_SDMMCCON (XMC4_SDMMC_CON_BASE+XMC4_SCU_SDMMCCON_OFFSET) + +/* Power control SCU Registers */ + +#define XMC4_SCU_PWRSTAT (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRSTAT_OFFSET) +#define XMC4_SCU_PWRSET (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRSET_OFFSET) +#define XMC4_SCU_PWRCLR (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRCLR_OFFSET) +#define XMC4_SCU_EVRSTAT (XMC4_SCU_POWER_BASE+XMC4_SCU_EVRSTAT_OFFSET) +#define XMC4_SCU_EVRVADCSTAT (XMC4_SCU_POWER_BASE+XMC4_SCU_EVRVADCSTAT_OFFSET) +#define XMC4_SCU_PWRMON (XMC4_SCU_POWER_BASE+XMC4_SCU_PWRMON_OFFSET) + +/* Hibernation SCU Registers */ + +#define XMC4_SCU_HDSTAT (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDSTAT_OFFSET) +#define XMC4_SCU_HDCLR (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDCLR_OFFSET) +#define XMC4_SCU_HDSET (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDSET_OFFSET) +#define XMC4_SCU_HDCR (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_HDCR_OFFSET) +#define XMC4_SCU_OSCSICTRL (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_OSCSICTRL_OFFSET) +#define XMC4_SCU_OSCULSTAT (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_OSCULSTAT_OFFSET) +#define XMC4_SCU_OSCULCTRL (XMC4_SCU_HIBERNATE_BASE+XMC4_SCU_OSCULCTRL_OFFSET) + +/* Reset SCU Registers */ + +#define XMC4_SCU_RSTSTAT (XMC4_SCU_RESET_BASE+XMC4_SCU_RSTSTAT_OFFSET) +#define XMC4_SCU_RSTSET (XMC4_SCU_RESET_BASE+XMC4_SCU_RSTSET_OFFSET) +#define XMC4_SCU_RSTCLR (XMC4_SCU_RESET_BASE+XMC4_SCU_RSTCLR_OFFSET) +#define XMC4_SCU_PRSTAT0 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT0_OFFSET) +#define XMC4_SCU_PRSET0 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET0_OFFSET) +#define XMC4_SCU_PRCLR0 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR0_OFFSET) +#define XMC4_SCU_PRSTAT1 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT1_OFFSET) +#define XMC4_SCU_PRSET1 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET1_OFFSET) +#define XMC4_SCU_PRCLR1 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR1_OFFSET) +#define XMC4_SCU_PRSTAT2 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT2_OFFSET) +#define XMC4_SCU_PRSET2 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET2_OFFSET) +#define XMC4_SCU_PRCLR2 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR2_OFFSET) +#define XMC4_SCU_PRSTAT3 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSTAT3_OFFSET) +#define XMC4_SCU_PRSET3 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRSET3_OFFSET) +#define XMC4_SCU_PRCLR3 (XMC4_SCU_RESET_BASE+XMC4_SCU_PRCLR3_OFFSET) + +/* Clock Control SCU Registers */ + +#define XMC4_SCU_CLKSTAT (XMC4_SCU_CLK_BASE+XMC4_SCU_CLKSTAT_OFFSET) +#define XMC4_SCU_CLKSET (XMC4_SCU_CLK_BASE+XMC4_SCU_CLKSET_OFFSET) +#define XMC4_SCU_CLKCLR (XMC4_SCU_CLK_BASE+XMC4_SCU_CLKCLR_OFFSET) +#define XMC4_SCU_SYSCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_SYSCLKCR_OFFSET) +#define XMC4_SCU_CPUCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_CPUCLKCR_OFFSET) +#define XMC4_SCU_PBCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_PBCLKCR_OFFSET) +#define XMC4_SCU_USBCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_USBCLKCR_OFFSET) +#define XMC4_SCU_EBUCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_EBUCLKCR_OFFSET) +#define XMC4_SCU_CCUCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_CCUCLKCR_OFFSET) +#define XMC4_SCU_WDTCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_WDTCLKCR_OFFSET) +#define XMC4_SCU_EXTCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_EXTCLKCR_OFFSET) +#define XMC4_SCU_SLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_SLEEPCR_OFFSET) +#define XMC4_SCU_DSLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_DSLEEPCR_OFFSET) +#define XMC4_SCU_CGATSTAT0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT0_OFFSET) +#define XMC4_SCU_CGATSET0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET0_OFFSET) +#define XMC4_SCU_CGATCLR0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR0_OFFSET) +#define XMC4_SCU_CGATSTAT1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT1_OFFSET) +#define XMC4_SCU_CGATSET1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET1_OFFSET) +#define XMC4_SCU_CGATCLR1 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR1_OFFSET) +#define XMC4_SCU_CGATSTAT2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT2_OFFSET) +#define XMC4_SCU_CGATSET2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET2_OFFSET +#define XMC4_SCU_CGATCLR2 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR2_OFFSET +#define XMC4_SCU_CGATSTAT3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT3_OFFSET +#define XMC4_SCU_CGATSET3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET3_OFFSET +#define XMC4_SCU_CGATCLR3 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATCLR3_OFFSET_ + +/* Oscillator Control SCU Registers */ + +#define XMC4_OSCU_OSCHPSTAT (XMC4_SCU_OSC_BASE+XMC4_OSCU_OSCHPSTAT_OFFSET) +#define XMC4_OSCU_OSCHPCTRL (XMC4_SCU_OSC_BASE+XMC4_OSCU_OSCHPCTRL_OFFSET) +#define XMC4_OSCU_CLKCALCONST (XMC4_SCU_OSC_BASE+XMC4_OSCU_CLKCALCONST_OFFSET) + +/* PLL Control SCU Registers */ + +#define XMC4_SCU_PLLSTAT (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLSTAT_OFFSET) +#define XMC4_SCU_PLLCON0 (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLCON0_OFFSET) +#define XMC4_SCU_PLLCON1 (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLCON1_OFFSET) +#define XMC4_SCU_PLLCON2 (XMC4_SCU_PLL_BASE+XMC4_SCU_PLLCON2_OFFSET) +#define XMC4_SCU_USBPLLSTAT (XMC4_SCU_PLL_BASE+XMC4_SCU_USBPLLSTAT_OFFSET) +#define XMC4_SCU_USBPLLCON (XMC4_SCU_PLL_BASE+XMC4_SCU_USBPLLCON_OFFSET) +#define XMC4_SCU_CLKMXSTAT (XMC4_SCU_PLL_BASE+XMC4_SCU_CLKMXSTAT_OFFSET) /* Register Bit-Field Definitions ***************************************************/ /* General SCU Registers */ /* Module Identification Register */ -#define GCU_ID_ +#define SCU_ID_ /* Chip ID */ -#define GCU_IDCHIP_ +#define SCU_IDCHIP_ /* Manufactory ID */ -#define GCU_IDMANUF_ +#define SCU_IDMANUF_ /* Start-up Control */ -#define GCU_STCON_ +#define SCU_STCON_ /* General Purpose Register 0 */ -#define GCU_GPR0_ +#define SCU_GPR0_ /* General Purpose Register 1 */ -#define GCU_GPR1_ +#define SCU_GPR1_ /* Ethernet 0 Port Control */ -#define GCU_ETH0CON_ +#define SCU_ETH0CON_ /* CCUx Global Start Control Register */ -#define GCU_CCUCON_ -/* Service Request Status */ -#define GCU_SRSTAT_ -/* RAW Service Request Status */ -#define GCU_SRRAW_ -/* Service Request Mask */ -#define GCU_SRMSK_ -/* Service Request Clear */ -#define GCU_SRCLR_ -/* Service Request Set */ -#define GCU_SRSET_ -/* Enable Promoting Events to NMI Request */ -#define GCU_NMIREQEN_ +#define SCU_CCUCON_ /* DTS Control */ -#define GCU_DTSCON_ +#define SCU_DTSCON_ /* DTS Status */ -#define GCU_DTSSTAT_ -/* SD-MMC Delay Control Register */ -#define GCU_SDMMCDEL_ +#define SCU_DTSSTAT_ +/* SD-MMC Delay Control Register */ +#define SCU_SDMMCDEL_ /* Out-Of-Range Comparator Enable Register 0 */ -#define GCU_G0ORCEN_ +#define SCU_G0ORCEN_ /* Out-Of-Range Comparator Enable Register 1 */ -#define GCU_G1ORCEN_ +#define SCU_G1ORCEN_ /* Mirror Update Status Register */ -#define GCU_MIRRSTS_ -/* Retention Memory Access Control Register */ -#define GCU_RMACR_ -/* Retention Memory Access Data Register */ -#define GCU_RMADATA_ -/* Parity Error Enable Register */ -#define GCU_PEEN_ -/* Memory Checking Control Register */ -#define GCU_MCHKCON_ -/* Parity Error Trap Enable Register */ -#define GCU_PETE_ -/* Reset upon Parity Error Enable Register */ -#define GCU_PERSTEN_ -/* Parity Error Control Register */ -#define GCU_PEFLAG_ -/* Parity Memory Test Pattern Register */ -#define GCU_PMTPR_ -/* Parity Memory Test Select Register */ -#define GCU_PMTSR_ -/* Trap Status Register */ -#define GCU_TRAPSTAT_ -/* Trap Raw Status Register */ -#define GCU_TRAPRAW_ -/* Trap Mask Register */ -#define GCU_TRAPDIS_ -/* Trap Clear Register */ -#define GCU_TRAPCLR_ -/* Trap Set Register */ -#define GCU_TRAPSET_ +#define SCU_MIRRSTS_ -/* PCU Registers */ +/* Ethernet Control SCU Resters */ + +/* Ethernet 0 Port Control Register */ +#define SCU_ETHCON_ + +/* Interrupt Control SCU Registers */ + +/* Service Request Status */ +#define SCU_SRSTAT_ +/* RAW Service Request Status */ +#define SCU_SRRAW_ +/* Service Request Mask */ +#define SCU_SRMSK_ +/* Service Request Clear */ +#define SCU_SRCLR_ +/* Service Request Set */ +#define SCU_SRSET_ +/* Enable Promoting Events to NMI Request */ +#define SCU_NMIREQEN_ +/* Retention Memory Access Control Register */ +#define SCU_RMACR_ +/* Retention Memory Access Data Register */ +#define SCU_RMADATA_ +/* Parity Error Enable Register */ + +/* SDMMC Control SCU Registers */ + +/* SDMMC Configuration */ +#define SCU_SDMMCCON_ + +/* Parity Control Registers */ + +#define SCU_PEEN_ +/* Memory Checking Control Register */ +#define SCU_MCHKCON_ +/* Parity Error Trap Enable Register */ +#define SCU_PETE_ +/* Reset upon Parity Error Enable Register */ +#define SCU_PERSTEN_ +/* Parity Error Control Register */ +#define SCU_PEFLAG_ +/* Parity Memory Test Pattern Register */ +#define SCU_PMTPR_ +/* Parity Memory Test Select Register */ +#define SCU_PMTSR_ + +/* Trap Control Registers */ + +/* Trap Status Register */ +#define SCU_TRAPSTAT_ +/* Trap Raw Status Register */ +#define SCU_TRAPRAW_ +/* Trap Mask Register */ +#define SCU_TRAPDIS_ +/* Trap Clear Register */ +#define SCU_TRAPCLR_ +/* Trap Set Register */ +#define SCU_TRAPSET_ + +/* Power Control SCU Registers */ /* Power Status Register */ -#define PCU_PWRSTAT_ +#define SCU_PWRSTAT_ /* Power Set Control Register */ -#define PCU_PWRSET_ +#define SCU_PWRSET_ /* Power Clear Control Register */ -#define PCU_PWRCLR_ +#define SCU_PWRCLR_ /* EVR Status Register */ -#define PCU_EVRSTAT_ +#define SCU_EVRSTAT_ /* EVR VADC Status Register */ -#define PCU_EVRVADCSTAT_ +#define SCU_EVRVADCSTAT_ /* Power Monitor Value */ -#define PCU_PWRMON_ +#define SCU_PWRMON_ /* HCU Registers */ /* Hibernate Domain Status Register */ -#define HCU_HDSTAT_ +#define SCU_HDSTAT_ /* Hibernate Domain Status Clear Register */ -#define HCU_HDCLR_ +#define SCU_HDCLR_ /* Hibernate Domain Status Set Register */ -#define HCU_HDSET_ +#define SCU_HDSET_ /* Hibernate Domain Control Register */ -#define HCU_HDCR_ +#define SCU_HDCR_ /* Internal 32.768 kHz Clock Source Control Register */ -#define HCU_OSCSICTRL_ +#define SCU_OSCSICTRL_ /* OSC_ULP Status Register */ -#define HCU_OSCULSTAT_ +#define SCU_OSCULSTAT_ /* OSC_ULP Control Register */ -#define HCU_OSCULCTRL_ +#define SCU_OSCULCTRL_ -/* RCU Registers */ +/* Reset SCU Registers */ /* System Reset Status */ -#define RCU_RSTSTAT_ +#define SCU_RSTSTAT_ /* Reset Set Register */ -#define RCU_RSTSET_ +#define SCU_RSTSET_ /* Reset Clear Register */ -#define RCU_RSTCLR_ +#define SCU_RSTCLR_ /* Peripheral Reset Status Register 0 */ -#define RCU_PRSTAT0_ +#define SCU_PRSTAT0_ /* Peripheral Reset Set Register 0 */ -#define RCU_PRSET0_ +#define SCU_PRSET0_ /* Peripheral Reset Clear Register 0 */ -#define RCU_PRCLR0_ +#define SCU_PRCLR0_ /* Peripheral Reset Status Register 1 */ -#define RCU_PRSTAT1_ +#define SCU_PRSTAT1_ /* Peripheral Reset Set Register 1 */ -#define RCU_PRSET1_ +#define SCU_PRSET1_ /* Peripheral Reset Clear Register 1 */ -#define RCU_PRCLR1_ +#define SCU_PRCLR1_ /* Peripheral Reset Status Register 2 */ -#define RCU_PRSTAT2_ +#define SCU_PRSTAT2_ /* Peripheral Reset Set Register 2 */ -#define RCU_PRSET2_ +#define SCU_PRSET2_ /* Peripheral Reset Clear Register 2 */ -#define RCU_PRCLR2_ +#define SCU_PRCLR2_ /* Peripheral Reset Status Register 3 */ -#define RCU_PRSTAT3_ +#define SCU_PRSTAT3_ /* Peripheral Reset Set Register 3 */ -#define RCU_PRSET3_ +#define SCU_PRSET3_ /* Peripheral Reset Clear Register 3 */ -#define RCU_PRCLR3_ +#define SCU_PRCLR3_ -/* CCU Registers */ +/* Clock Control SCU Registers */ /* Clock Status Register */ -#define CCU_CLKSTAT_ +#define SCU_CLKSTAT_ /* Clock Set Control Register */ -#define CCU_CLKSET_ +#define SCU_CLKSET_ /* Clock clear Control Register */ -#define CCU_CLKCLR_ +#define SCU_CLKCLR_ /* System Clock Control */ -#define CCU_SYSCLKCR_ +#define SCU_SYSCLKCR_ /* CPU Clock Control */ -#define CCU_CPUCLKCR_ +#define SCU_CPUCLKCR_ /* Peripheral Bus Clock Control */ -#define CCU_PBCLKCR_ +#define SCU_PBCLKCR_ /* USB Clock Control */ -#define CCU_USBCLKCR_ +#define SCU_USBCLKCR_ /* EBU Clock Control */ -#define CCU_EBUCLKCR_ +#define SCU_EBUCLKCR_ /* CCU Clock Control */ -#define CCU_CCUCLKCR_ +#define SCU_CCUCLKCR_ /* WDT Clock Control */ -#define CCU_WDTCLKCR_ +#define SCU_WDTCLKCR_ /* External clock Control Register */ -#define CCU_EXTCLKCR_ +#define SCU_EXTCLKCR_ /* Sleep Control Register */ -#define CCU_SLEEPCR_ +#define SCU_SLEEPCR_ /* Deep Sleep Control Register */ -#define CCU_DSLEEPCR_ +#define SCU_DSLEEPCR_ +/* Peripheral 0 Clock Gating Status */ +#define SCU_CGATSTAT0_ +/* Peripheral 0 Clock Gating Set */ +#define SCU_CGATSET0_ +/* Peripheral 0 Clock Gating Clear */ +#define SCU_CGATCLR0_ +/* Peripheral 1 Clock Gating Status */ +#define SCU_CGATSTAT1_ +/* Peripheral 1 Clock Gating Set */ +#define SCU_CGATSET1_ +/* Peripheral 1 Clock Gating Clear */ +#define SCU_CGATCLR1_ +/* Peripheral 2 Clock Gating Status */ +#define SCU_CGATSTAT2_ +/* Peripheral 2 Clock Gating Set */ +#define SCU_CGATSET2_ +/* Peripheral 2 Clock Gating Clear */ +#define SCU_CGATCLR2_ +/* Peripheral 3 Clock Gating Status */ +#define SCU_CGATSTAT3_ +/* Peripheral 3 Clock Gating Set */ +#define SCU_CGATSET3_ +/* Peripheral 3 Clock Gating Clear */ +#define SCU_CGATCLR3_ + +/* Oscillator Control SCU Registers */ + /* OSC_HP Status Register */ -#define CCU_OSCHPSTAT_ +#define OSCU_OSCHPSTAT_ /* OSC_HP Control Register */ -#define CCU_OSCHPCTRL_ +#define OSCU_OSCHPCTRL_ /* Clock Calibration Constant Register */ -#define CCU_CLKCALCONST_ +#define OSCU_CLKCALCONST_ + +/* PLL Control SCU Registers */ + /* System PLL Status Register */ -#define CCU_PLLSTAT_ +#define SCU_PLLSTAT_ /* System PLL Configuration 0 Register */ -#define CCU_PLLCON0_ +#define SCU_PLLCON0_ /* System PLL Configuration 1 Register */ -#define CCU_PLLCON1_ +#define SCU_PLLCON1_ /* System PLL Configuration 2 Register */ -#define CCU_PLLCON2_ +#define SCU_PLLCON2_ /* USB PLL Status Register */ -#define CCU_USBPLLSTAT_ +#define SCU_USBPLLSTAT_ /* USB PLL Control Register */ -#define CCU_USBPLLCON_ +#define SCU_USBPLLCON_ /* Clock Multiplexing Status Register */ -#define CCU_CLKMXSTAT_ +#define SCU_CLKMXSTAT_ #endif /* __ARCH_ARM_SRC_XMC4_CHIP_XMC4_SCU_H */