sergiotarxz/nuttx
sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Add initial ESP32S2 Xtensa support

Browse Source
This commit is contained in:
Alan C. Assis 2021-05-20 17:07:54 -03:00 committed by Alin Jerpelea
parent 85f9b893b2
commit 7767acd24a
58 changed files with 52163 additions and 3 deletions

39
arch/xtensa/Kconfig

@ -37,6 +37,32 @@ config ARCH_CHIP_ESP32
"application"), however for most purposes the two CPUs are
interchangeable.
config ARCH_CHIP_ESP32S2
bool "Espressif ESP32-S2"
select ARCH_FAMILY_LX7
select XTENSA_HAVE_INTERRUPTS
select ARCH_HAVE_MODULE_TEXT
select ARCH_HAVE_SDRAM
select ARCH_HAVE_RESET
select ARCH_TOOLCHAIN_GNU
select ARCH_VECNOTIRQ
select LIBC_ARCH_MEMCPY
select LIBC_ARCH_MEMCHR
select LIBC_ARCH_MEMCMP
select LIBC_ARCH_MEMCCMP
select LIBC_ARCH_MEMMOVE
select LIBC_ARCH_MEMSET
select LIBC_ARCH_STRCHR
select LIBC_ARCH_STRCMP
select LIBC_ARCH_STRCPY
select LIBC_ARCH_STRLCPY
select LIBC_ARCH_STRNCPY
select LIBC_ARCH_STRLEN
select LIBC_ARCH_STRNLEN
---help---
The ESP32-S2 is a dual-core system from Espressif with a
Harvard architecture Xtensa LX7 CPU.
config ARCH_CHIP_XTENSA_CUSTOM
bool "Custom XTENSA chip"
select ARCH_CHIP_CUSTOM
@ -53,9 +79,17 @@ config ARCH_FAMILY_LX6
Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU).
The LX6 is a configurable and extensible processor core.
config ARCH_FAMILY_LX7
bool
default n
---help---
Cadence® Tensilica® Xtensa® LX7 data plane processing unit (DPU).
The LX7 is a configurable and extensible processor core.
config ARCH_CHIP
string
default "esp32" if ARCH_CHIP_ESP32
default "esp32s2" if ARCH_CHIP_ESP32S2
config XTENSA_CP_LAZY
bool "Lazy co-processor state restoration"
@ -143,4 +177,9 @@ if ARCH_CHIP_ESP32
source arch/xtensa/src/esp32/Kconfig
endif
source arch/xtensa/src/lx7/Kconfig
if ARCH_CHIP_ESP32S2
source arch/xtensa/src/esp32s2/Kconfig
endif
endif # ARCH_XTENSA

74
arch/xtensa/include/esp32s2/chip.h Normal file

@ -0,0 +1,74 @@
/****************************************************************************
* arch/xtensa/include/esp32s2/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_CHIP_H
#define __ARCH_XTENSA_INCLUDE_ESP32S2_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Characterize each supported ESP32S2 part */
#define ESP32S2_NDAC 2 /* DAC0-1 */
#define ESP32S2_NI2C 1 /* I2C0 */
#define ESP32S2_NI2S 1 /* I2S0 */
#define ESP32S2_NLCD 1 /* LCD0 */
#define ESP32S2_NSPI 4 /* SPI0-3 */
#define ESP32S2_NUARTS 2 /* UART0-1 */
#define ESP32S2_NUSBOTG 1 /* USB OTG */
#define ESP32S2_NGPIOS 46 /* GPIO0-45 */
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_CHIP_H */

738
arch/xtensa/include/esp32s2/core-isa.h Normal file

@ -0,0 +1,738 @@
/****************************************************************************
* arch/xtensa/include/esp32s2/core-isa.h
* Xtensa processor CORE configuration
*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_CORE_ISA_H
#define __ARCH_XTENSA_INCLUDE_ESP32S2_CORE_ISA_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Parameters Useful for Any Code, USER or PRIVILEGED
****************************************************************************/
/* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option
* is configured, and a value of 0 otherwise. These macros are always
* defined.
*/
/****************************************************************************
* ISA
****************************************************************************/
#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
#define XCHAL_HAVE_DEBUG 1 /* debug option */
#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
#define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */
#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
#define XCHAL_HAVE_L32R 1 /* L32R instruction */
#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
/* #define XCHAL_HAVE_POPC 0 */ /* POPC instruction */
/* #define XCHAL_HAVE_CRC 0 */ /* CRC instruction */
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
#define XCHAL_NUM_CONTEXTS 1 /* */
#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */
#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
#define XCHAL_HAVE_PRID 1 /* processor ID register */
#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */
#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
#define XCHAL_HAVE_FUSION 0 /* Fusion*/
#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
#define XCHAL_HAVE_FUSION_16BIT_BB 0 /* Fusion 16-bit Baseband option */
#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */
#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */
#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
#define XCHAL_HAVE_HIFI_MINI 0
#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */
#define XCHAL_HAVE_FP 0 /* single prec floating point */
#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */
#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */
#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */
#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */
#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
#define XCHAL_HAVE_FUSIONG 0 /* FusionG */
#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */
#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */
#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */
#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */
#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */
#define XCHAL_HAVE_PDX 0 /* PDX */
#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */
#define XCHAL_HAVE_PDX4 0 /* PDX4 */
#define XCHAL_HAVE_PDX8 0 /* PDX8 */
#define XCHAL_HAVE_PDX16 0 /* PDX16 */
#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */
#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */
#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */
#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */
#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */
#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */
#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */
#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */
#define XCHAL_HAVE_VISIONC 0 /* Vision C */
/****************************************************************************
* MISC
****************************************************************************/
#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
#define XCHAL_DATA_WIDTH 4 /* data width in bytes */
#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay
* (1 = 5-stage, 2 = 7-stage)
*/
#define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */
#define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */
/* In T1050, applies to selected core load and store instr. (see ISA): */
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc. */
#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw */
#define XCHAL_SW_VERSION 1200008 /* sw version of this header */
#define XCHAL_CORE_ID "test_0731_1_TIE_GPIO_f" /* alphanum core name
* (CoreID) set in the Xtensa
* Processor Generator
*/
#define XCHAL_BUILD_UNIQUE_ID 0x00075F76 /* 22-bit sw build ID */
/* These definitions describe the hardware targeted by this software. */
#define XCHAL_HW_CONFIGID0 0xC2ECFAFE /* ConfigID hi 32 bits*/
#define XCHAL_HW_CONFIGID1 0x22075F76 /* ConfigID lo 32 bits*/
#define XCHAL_HW_VERSION_NAME "LX7.0.8" /* full version name */
#define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */
#define XCHAL_HW_VERSION_MINOR 8 /* minor ver# of targeted hw */
#define XCHAL_HW_VERSION 270008 /* major*100+minor */
#define XCHAL_HW_REL_LX7 1
#define XCHAL_HW_REL_LX7_0 1
#define XCHAL_HW_REL_LX7_0_8 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
/* If software targets a range of hardware versions, these are the bounds: */
#define XCHAL_HW_MIN_VERSION_MAJOR 2700 /* major v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION_MINOR 8 /* minor v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION 270008 /* earliest targeted hw */
#define XCHAL_HW_MAX_VERSION_MAJOR 2700 /* major v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION_MINOR 8 /* minor v of latest tgt hw */
#define XCHAL_HW_MAX_VERSION 270008 /* latest targeted hw */
/****************************************************************************
* CACHE
****************************************************************************/
#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */
#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */
#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
/****************************************************************************
* Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
****************************************************************************/
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
/****************************************************************************
* CACHE
****************************************************************************/
#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
#define XCHAL_HAVE_AXI 0 /* AXI bus */
#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
/* Number of cache sets in log2(lines per way): */
#define XCHAL_ICACHE_SETWIDTH 0
#define XCHAL_DCACHE_SETWIDTH 0
/* Cache set associativity (number of ways): */
#define XCHAL_ICACHE_WAYS 1
#define XCHAL_DCACHE_WAYS 1
/* Cache features: */
#define XCHAL_ICACHE_LINE_LOCKABLE 0
#define XCHAL_DCACHE_LINE_LOCKABLE 0
#define XCHAL_ICACHE_ECC_PARITY 0
#define XCHAL_DCACHE_ECC_PARITY 0
/* Cache access size in bytes (affects operation of SICW instruction): */
#define XCHAL_ICACHE_ACCESS_SIZE 1
#define XCHAL_DCACHE_ACCESS_SIZE 1
#define XCHAL_DCACHE_BANKS 0 /* number of banks */
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
#define XCHAL_CA_BITS 4
/****************************************************************************
* INTERNAL I/D RAM/ROMs and XLMI
****************************************************************************/
#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */
#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */
#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
/* Instruction ROM 0: */
#define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */
#define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */
#define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
/* Instruction RAM 0: */
#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
#define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_HAVE_INSTRAM0 1
#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */
/* Instruction RAM 1: */
#define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */
#define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */
#define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_HAVE_INSTRAM1 1
#define XCHAL_INSTRAM1_HAVE_IDMA 0 /* idma supported by this local memory */
/* Data ROM 0: */
#define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */
#define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */
#define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */
#define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATAROM0_BANKS 1 /* number of banks */
/* Data RAM 0: */
#define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */
#define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */
#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */
#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
#define XCHAL_HAVE_DATARAM0 1
#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */
/* Data RAM 1: */
#define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */
#define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */
#define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */
#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATARAM1_BANKS 1 /* number of banks */
#define XCHAL_HAVE_DATARAM1 1
#define XCHAL_DATARAM1_HAVE_IDMA 0 /* idma supported by this local memory */
/* XLMI Port 0: */
#define XCHAL_XLMI0_VADDR 0x3FE00000 /* virtual address */
#define XCHAL_XLMI0_PADDR 0x3FE00000 /* physical address */
#define XCHAL_XLMI0_SIZE 1048576 /* size in bytes */
#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_HAVE_IDMA 0
#define XCHAL_HAVE_IDMA_TRANSPOSE 0
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM */
/****************************************************************************
* INTERRUPTS and TIMERS
****************************************************************************/
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
* (not including level zero)
*/
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
/* Masks of interrupts at each interrupt level: */
#define XCHAL_INTLEVEL1_MASK 0x000637FF
#define XCHAL_INTLEVEL2_MASK 0x00380000
#define XCHAL_INTLEVEL3_MASK 0x28C08800
#define XCHAL_INTLEVEL4_MASK 0x53000000
#define XCHAL_INTLEVEL5_MASK 0x84010000
#define XCHAL_INTLEVEL6_MASK 0x00000000
#define XCHAL_INTLEVEL7_MASK 0x00004000
/* Masks of interrupts at each range 1..n of interrupt levels: */
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF
/* Level of each interrupt: */
#define XCHAL_INT0_LEVEL 1
#define XCHAL_INT1_LEVEL 1
#define XCHAL_INT2_LEVEL 1
#define XCHAL_INT3_LEVEL 1
#define XCHAL_INT4_LEVEL 1
#define XCHAL_INT5_LEVEL 1
#define XCHAL_INT6_LEVEL 1
#define XCHAL_INT7_LEVEL 1
#define XCHAL_INT8_LEVEL 1
#define XCHAL_INT9_LEVEL 1
#define XCHAL_INT10_LEVEL 1
#define XCHAL_INT11_LEVEL 3
#define XCHAL_INT12_LEVEL 1
#define XCHAL_INT13_LEVEL 1
#define XCHAL_INT14_LEVEL 7
#define XCHAL_INT15_LEVEL 3
#define XCHAL_INT16_LEVEL 5
#define XCHAL_INT17_LEVEL 1
#define XCHAL_INT18_LEVEL 1
#define XCHAL_INT19_LEVEL 2
#define XCHAL_INT20_LEVEL 2
#define XCHAL_INT21_LEVEL 2
#define XCHAL_INT22_LEVEL 3
#define XCHAL_INT23_LEVEL 3
#define XCHAL_INT24_LEVEL 4
#define XCHAL_INT25_LEVEL 4
#define XCHAL_INT26_LEVEL 5
#define XCHAL_INT27_LEVEL 3
#define XCHAL_INT28_LEVEL 4
#define XCHAL_INT29_LEVEL 3
#define XCHAL_INT30_LEVEL 4
#define XCHAL_INT31_LEVEL 5
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
* EXCSAVE/EPS/EPC_n, RFI n)
*/
/* Type of each interrupt: */
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE
#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE
#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
/* Masks of interrupts for each type of interrupt: */
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F
#define XCHAL_INTTYPE_MASK_TIMER 0x00018040
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800
#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000
/* Interrupt numbers assigned to specific interrupt sources: */
#define XTHAL_TIMER_UNCONFIGURED -1 /* REVISIT: should be in hal.h */
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */
#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
#define XCHAL_PROFILING_INTERRUPT 11
/* Interrupt numbers for levels at which only one interrupt is configured: */
#define XCHAL_INTLEVEL7_NUM 14
/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
/* External interrupt mapping.
* These macros describe how Xtensa processor interrupt numbers
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
* map to external BInterrupt<n> pins, for those interrupts
* configured as external (level-triggered, edge-triggered, or NMI).
* See the Xtensa processor databook for more details.
*/
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */
#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */
#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */
#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */
#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */
#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */
#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */
#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */
#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */
#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */
#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */
#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */
#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */
#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */
#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */
#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */
#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */
#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */
#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */
#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */
#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */
#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */
#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */
#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */
#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */
#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */
#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */
#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */
#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */
#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */
#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */
#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */
/****************************************************************************
* EXCEPTIONS and VECTORS
****************************************************************************/
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
* number: 1 == XEA1 (old)
* 2 == XEA2 (new)
* 0 == XEAX (extern) or TX
*/
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
#define XCHAL_VECBASE_RESET_PADDR 0x40000000
#define XCHAL_RESET_VECBASE_OVERLAP 0
#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
#define XCHAL_RESET_VECTOR_VADDR 0x40000400
#define XCHAL_RESET_VECTOR_PADDR 0x40000400
#define XCHAL_USER_VECOFS 0x00000340
#define XCHAL_USER_VECTOR_VADDR 0x40000340
#define XCHAL_USER_VECTOR_PADDR 0x40000340
#define XCHAL_KERNEL_VECOFS 0x00000300
#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300
#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
#define XCHAL_NMI_VECOFS 0x000002C0
#define XCHAL_NMI_VECTOR_VADDR 0x400002C0
#define XCHAL_NMI_VECTOR_PADDR 0x400002C0
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
/****************************************************************************
* DEBUG MODULE
****************************************************************************/
/* Misc */
#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
/* On-Chip Debug (OCD) */
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
/* TRAX (in core) */
#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */
#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
/* Perf counters */
#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */
/****************************************************************************
* MMU
****************************************************************************/
/* See core-matmap.h header file for more details. */
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
* [autorefill] and protection)
* usable for an MMU-based OS
*/
/* If none of the above last 5 are set, it's a custom TLB configuration. */
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
/****************************************************************************
* MPU
****************************************************************************/
#define XCHAL_HAVE_MPU 0
#define XCHAL_MPU_ENTRIES 0
#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/
#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */
#define XCHAL_MPU_ALIGN_BITS 0
#define XCHAL_MPU_ALIGN 0
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_CORE_ISA_H */

495
arch/xtensa/include/esp32s2/irq.h Normal file

@ -0,0 +1,495 @@
/****************************************************************************
* arch/xtensa/include/esp32s2/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H
#define __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/esp32s2/chip.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Interrupt Matrix
*
* Features
* - Accepts 95 peripheral interrupt sources as input.
* - Generates 26 peripheral interrupt sources as output.
* - CPU NMI Interrupt Mask.
* - Queries current interrupt status of peripheral interrupt sources.
*
* Peripheral Interrupt Source
*
* ESP32S2 has 95 peripheral interrupt sources in total. 67 of 71 ESP32S2
* peripheral interrupt sources can be allocated to either CPU. The four
* remaining peripheral interrupt sources are CPU-specific, two per CPU.
*
* - GPIO_INTERRUPT_PRO and GPIO_INTERRUPT_PRO_NMI can only be allocated to
* PRO_CPU.
* - GPIO_INTERRUPT_APP and GPIO_INTERRUPT_APP_NMI can only be allocated to
* APP_CPU.
*
* As a result, PRO_CPU and APP_CPU each have 69 peripheral interrupt
* sources.
*/
/* PRO_INTR_STATUS_REG_0 */
#define ESP32S2_PERI_MAC 0 /* INTR_STATUS_REG_0, bit 0 */
#define ESP32S2_PERI_MAC_NMI 1 /* INTR_STATUS_REG_0, bit 1 */
#define ESP32S2_PERI_PWR 2 /* INTR_STATUS_REG_0, bit 2 */
#define ESP32S2_PERI_BB 3 /* INTR_STATUS_REG_0, bit 3 */
#define ESP32S2_PERI_BT_MAC 4 /* INTR_STATUS_REG_0, bit 4 */
#define ESP32S2_PERI_BT_BB 5 /* INTR_STATUS_REG_0, bit 5 */
#define ESP32S2_PERI_BT_BB_NMI 6 /* INTR_STATUS_REG_0, bit 6 */
#define ESP32S2_PERI_RWBT 7 /* INTR_STATUS_REG_0, bit 7 */
#define ESP32S2_PERI_RWBLE 8 /* INTR_STATUS_REG_0, bit 8 */
#define ESP32S2_PERI_RWBT_NMI 9 /* INTR_STATUS_REG_0, bit 9 */
#define ESP32S2_PERI_RWBLE_NMI 10 /* INTR_STATUS_REG_0, bit 10 */
#define ESP32S2_PERI_SLC0 11 /* INTR_STATUS_REG_0, bit 11 */
#define ESP32S2_PERI_SLC1 12 /* INTR_STATUS_REG_0, bit 12 */
#define ESP32S2_PERI_UHCI0 13 /* INTR_STATUS_REG_0, bit 13 */
#define ESP32S2_PERI_UHCI1 14 /* INTR_STATUS_REG_0, bit 14 */
#define ESP32S2_PERI_TG_T0_LEVEL 15 /* INTR_STATUS_REG_0, bit 15 */
#define ESP32S2_PERI_TG_T1_LEVEL 16 /* INTR_STATUS_REG_0, bit 16 */
#define ESP32S2_PERI_TG_WDT_LEVEL 17 /* INTR_STATUS_REG_0, bit 17 */
#define ESP32S2_PERI_TG_LACT_LEVEL 18 /* INTR_STATUS_REG_0, bit 18 */
#define ESP32S2_PERI_TG1_T0_LEVEL 19 /* INTR_STATUS_REG_0, bit 19 */
#define ESP32S2_PERI_TG1_T1_LEVEL 20 /* INTR_STATUS_REG_0, bit 20 */
#define ESP32S2_PERI_TG1_WDT_LEVEL 21 /* INTR_STATUS_REG_0, bit 21 */
#define ESP32S2_PERI_TG1_LACT_LEVEL 22 /* INTR_STATUS_REG_0, bit 22 */
#define ESP32S2_PERI_GPIO_INT_PRO 23 /* INTR_STATUS_REG_0, bit 23 */
#define ESP32S2_PERI_GPIO_INT_PRO_NMI 24 /* INTR_STATUS_REG_0, bit 24 */
#define ESP32S2_PERI_GPIO_INT_APP 25 /* INTR_STATUS_REG_0, bit 25 */
#define ESP32S2_PERI_GPIO_INT_APP_NMI 26 /* INTR_STATUS_REG_0, bit 26 */
#define ESP32S2_PERI_DEDICATED_GPIO_IN 27 /* INTR_STATUS_REG_0, bit 27 */
#define ESP32S2_PERI_INT_FROM_CPU0 28 /* INTR_STATUS_REG_0, bit 28 */
#define ESP32S2_PERI_INT_FROM_CPU1 29 /* INTR_STATUS_REG_0, bit 29 */
#define ESP32S2_PERI_INT_FROM_CPU2 30 /* INTR_STATUS_REG_0, bit 30 */
#define ESP32S2_PERI_INT_FROM_CPU3 31 /* INTR_STATUS_REG_0, bit 31 */
/* PRO_INTR_STATUS_REG_1 */
#define ESP32S2_PERI_SPI1 32 /* INTR_STATUS_REG_1, bit 0 */
#define ESP32S2_PERI_SPI2 33 /* INTR_STATUS_REG_1, bit 1 */
#define ESP32S2_PERI_SPI3 34 /* INTR_STATUS_REG_1, bit 2 */
#define ESP32S2_PERI_I2S0 35 /* INTR_STATUS_REG_1, bit 3 */
#define ESP32S2_PERI_I2S1 36 /* INTR_STATUS_REG_1, bit 4 */
#define ESP32S2_PERI_UART 37 /* INTR_STATUS_REG_1, bit 5 */
#define ESP32S2_PERI_UART1 38 /* INTR_STATUS_REG_1, bit 6 */
#define ESP32S2_PERI_UART2 39 /* INTR_STATUS_REG_1, bit 7 */
#define ESP32S2_PERI_SDIO_HOST 40 /* INTR_STATUS_REG_1, bit 8 */
#define ESP32S2_PERI_PWM0 41 /* INTR_STATUS_REG_1, bit 9 */
#define ESP32S2_PERI_PWM1 42 /* INTR_STATUS_REG_1, bit 10 */
#define ESP32S2_PERI_PWM2 43 /* INTR_STATUS_REG_1, bit 11 */
#define ESP32S2_PERI_PWM3 44 /* INTR_STATUS_REG_1, bit 12 */
#define ESP32S2_PERI_LEDC 45 /* INTR_STATUS_REG_1, bit 13 */
#define ESP32S2_PERI_EFUSE 46 /* INTR_STATUS_REG_1, bit 14 */
#define ESP32S2_PERI_CAN 47 /* INTR_STATUS_REG_1, bit 15 */
#define ESP32S2_PERI_USB 48 /* INTR_STATUS_REG_1, bit 16 */
#define ESP32S2_PERI_RTC_CORE 49 /* INTR_STATUS_REG_1, bit 17 */
#define ESP32S2_PERI_RMT 50 /* INTR_STATUS_REG_1, bit 18 */
#define ESP32S2_PERI_PCNT 51 /* INTR_STATUS_REG_1, bit 19 */
#define ESP32S2_PERI_I2C_EXT0 52 /* INTR_STATUS_REG_1, bit 20 */
#define ESP32S2_PERI_I2C_EXT1 53 /* INTR_STATUS_REG_1, bit 21 */
#define ESP32S2_PERI_RSA 54 /* INTR_STATUS_REG_1, bit 22 */
#define ESP32S2_PERI_SHA 55 /* INTR_STATUS_REG_1, bit 23 */
#define ESP32S2_PERI_AES 56 /* INTR_STATUS_REG_1, bit 24 */
#define ESP32S2_PERI_SPI2_DMA 57 /* INTR_STATUS_REG_1, bit 25 */
#define ESP32S2_PERI_SPI3_DMA 58 /* INTR_STATUS_REG_1, bit 26 */
#define ESP32S2_PERI_WDG 59 /* INTR_STATUS_REG_1, bit 27 */
#define ESP32S2_PERI_TIMER 60 /* INTR_STATUS_REG_1, bit 28 */
#define ESP32S2_PERI_TIMER_INT2 61 /* INTR_STATUS_REG_1, bit 29 */
#define ESP32S2_PERI_TG_T0_EDGE 62 /* INTR_STATUS_REG_1, bit 30 */
#define ESP32S2_PERI_TG_T1_EDGE 63 /* INTR_STATUS_REG_1, bit 31 */
/* PRO_INTR_STATUS_REG_2 */
#define ESP32S2_PERI_TG_WDT_EDGE 64 /* INTR_STATUS_REG_2, bit 0 */
#define ESP32S2_PERI_TG_LACT_EDGE 65 /* INTR_STATUS_REG_2, bit 1 */
#define ESP32S2_PERI_TG1_T0_EDGE 66 /* INTR_STATUS_REG_2, bit 2 */
#define ESP32S2_PERI_TG1_T1_EDGE 67 /* INTR_STATUS_REG_2, bit 3 */
#define ESP32S2_PERI_TG1_WDT_EDGE 68 /* INTR_STATUS_REG_2, bit 4 */
#define ESP32S2_PERI_TG1_LACT_EDGE 69 /* INTR_STATUS_REG_2, bit 5 */
#define ESP32S2_PERI_CACHE_IA 70 /* INTR_STATUS_REG_2, bit 6 */
#define ESP32S2_PERI_SYSTIMER_TARGET0 71 /* INTR_STATUS_REG_2, bit 7 */
#define ESP32S2_PERI_SYSTIMER_TARGET1 72 /* INTR_STATUS_REG_2, bit 8 */
#define ESP32S2_PERI_SYSTIMER_TARGET2 73 /* INTR_STATUS_REG_2, bit 9 */
#define ESP32S2_PERI_ASSIST_DEBUG 74 /* INTR_STATUS_REG_2, bit 10 */
#define ESP32S2_PERI_PMS_PRO_IRAM0_ILG 75 /* INTR_STATUS_REG_2, bit 11 */
#define ESP32S2_PERI_PMS_PRO_DRAM0_ILG 76 /* INTR_STATUS_REG_2, bit 12 */
#define ESP32S2_PERI_PMS_PRO_DPORT_ILG 77 /* INTR_STATUS_REG_2, bit 13 */
#define ESP32S2_PERI_PMS_PRO_AHB_ILG 78 /* INTR_STATUS_REG_2, bit 14 */
#define ESP32S2_PERI_PMS_PRO_CACHE_ILG 79 /* INTR_STATUS_REG_2, bit 15 */
#define ESP32S2_PERI_PMS_DMA_APB_I_ILG 80 /* INTR_STATUS_REG_2, bit 16 */
#define ESP32S2_PERI_PMS_DMA_RX_I_ILG 81 /* INTR_STATUS_REG_2, bit 17 */
#define ESP32S2_PERI_PMS_DMA_TX_I_ILG 82 /* INTR_STATUS_REG_2, bit 18 */
#define ESP32S2_PERI_SPI_MEM_REJECT 83 /* INTR_STATUS_REG_2, bit 19 */
#define ESP32S2_PERI_DMA_COPY 84 /* INTR_STATUS_REG_2, bit 20 */
#define ESP32S2_PERI_SPI4_DMA 85 /* INTR_STATUS_REG_2, bit 21 */
#define ESP32S2_PERI_SPI4 86 /* INTR_STATUS_REG_2, bit 22 */
#define ESP32S2_PERI_DCACHE_PRELOAD 87 /* INTR_STATUS_REG_2, bit 23 */
#define ESP32S2_PERI_ICACHE_PRELOAD 88 /* INTR_STATUS_REG_2, bit 24 */
#define ESP32S2_PERI_APB_ADC 89 /* INTR_STATUS_REG_2, bit 25 */
#define ESP32S2_PERI_CRYPTO_DMA 90 /* INTR_STATUS_REG_2, bit 26 */
#define ESP32S2_PERI_CPU_PERI_ERR 91 /* INTR_STATUS_REG_2, bit 27 */
#define ESP32S2_PERI_APB_PERI_ERR 92 /* INTR_STATUS_REG_2, bit 28 */
#define ESP32S2_PERI_DCACHE_SYNC 93 /* INTR_STATUS_REG_2, bit 29 */
#define ESP32S2_PERI_ICACHE_SYNC 94 /* INTR_STATUS_REG_2, bit 29 */
/* Total number of peripherals */
#define ESP32S2_NPERIPHERALS 95
/* Exceptions
*
* IRAM Offset Description
* 0x0000 Windows
* 0x0180 Level 2 interrupt
* 0x01c0 Level 3 interrupt
* 0x0200 Level 4 interrupt
* 0x0240 Level 5 interrupt
* 0x0280 Debug exception
* 0x02c0 NMI exception
* 0x0300 Kernel exception
* 0x0340 User exception
* 0x03c0 Double exception
*
* REVISIT: In more architectures supported by NuttX, exception errors
* tie into the normal interrupt handling via special IRQ numbers.
* It is still to be determined what will be done for the ESP32S2.
*
*/
/* IRQ numbers for internal interrupts that are dispatched like peripheral
* interrupts
*/
#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
#define XTENSA_NIRQ_INTERNAL 4 /* Number of dispatch internal interrupts */
#define XTENSA_IRQ_FIRSTPERI 4 /* First peripheral IRQ number */
/* IRQ numbers for peripheral interrupts coming through the Interrupt
* Matrix.
*/
#define ESP32S2_IRQ2PERIPH(irq) ((irq)-XTENSA_IRQ_FIRSTPERI)
/* PRO_INTR_STATUS_REG_0 */
#define ESP32S2_IRQ_MAC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_MAC)
#define ESP32S2_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_MAC_NMI)
#define ESP32S2_IRQ_PWR (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWR)
#define ESP32S2_IRQ_BB (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BB)
#define ESP32S2_IRQ_BT_MAC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BT_MAC)
#define ESP32S2_IRQ_BT_BB (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BB)
#define ESP32S2_IRQ_BT_BB_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BB_NMI)
#define ESP32S2_IRQ_RWBT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBT)
#define ESP32S2_IRQ_RWBLE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBLE)
#define ESP32S2_IRQ_RWBT_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBT_NMI)
#define ESP32S2_IRQ_RWBLE_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBLE_NMI)
#define ESP32S2_IRQ_SLC0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SLC0)
#define ESP32S2_IRQ_SLC1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SLC1)
#define ESP32S2_IRQ_UHCI0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UHCI0)
#define ESP32S2_IRQ_UHCI1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UHCI1)
#define ESP32S2_IRQ_TG_T0_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T0_LEVEL)
#define ESP32S2_IRQ_TG_T1_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T1_LEVEL)
#define ESP32S2_IRQ_TG_WDT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_WDT_LEVEL)
#define ESP32S2_IRQ_TG_LACT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_LACT_LEVEL)
#define ESP32S2_IRQ_TG1_T0_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T0_LEVEL)
#define ESP32S2_IRQ_TG1_T1_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T1_LEVEL)
#define ESP32S2_IRQ_TG1_WDT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_WDT_LEVEL)
#define ESP32S2_IRQ_TG1_LACT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_LACT_LEVEL)
#define ESP32S2_IRQ_GPIO_INT_PRO (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_PRO)
#define ESP32S2_IRQ_GPIO_INT_PRO_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_PRO_NMI)
#define ESP32S2_IRQ_GPIO_INT_APP (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_APP)
#define ESP32S2_IRQ_GPIO_INT_APP_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_APP_NMI)
#define ESP32S2_IRQ_DEDICATED_GPIO_IN (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DEDICATED_GPIO_IN)
#define ESP32S2_IRQ_INT_FROM_CPU0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU0
#define ESP32S2_IRQ_INT_FROM_CPU1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU1)
#define ESP32S2_IRQ_INT_FROM_CPU2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU2)
#define ESP32S2_IRQ_INT_FROM_CPU3 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU3)
#define ESP32_IRQ_SREG0 ESP32S2_IRQ_MAC
#define ESP32_NIRQS_SREG0 32
/* PRO_INTR_STATUS_REG_1 */
#define ESP32S2_IRQ_SPI1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI1)
#define ESP32S2_IRQ_SPI2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI2)
#define ESP32S2_IRQ_SPI3 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI3)
#define ESP32S2_IRQ_I2S0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2S0)
#define ESP32S2_IRQ_I2S1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2S1)
#define ESP32S2_IRQ_UART (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UART)
#define ESP32S2_IRQ_UART1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UART1)
#define ESP32S2_IRQ_UART2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UART2)
#define ESP32S2_IRQ_SDIO_HOST (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SDIO_HOST)
#define ESP32S2_IRQ_PWM0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM0)
#define ESP32S2_IRQ_PWM1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM1)
#define ESP32S2_IRQ_PWM2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM2)
#define ESP32S2_IRQ_PWM3 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM3)
#define ESP32S2_IRQ_LEDC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_LEDC)
#define ESP32S2_IRQ_EFUSE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_EFUSE)
#define ESP32S2_IRQ_CAN (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CAN)
#define ESP32S2_IRQ_USB (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_USB)
#define ESP32S2_IRQ_RTC_CORE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RTC_CORE)
#define ESP32S2_IRQ_RMT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RMT)
#define ESP32S2_IRQ_PCNT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PCNT)
#define ESP32S2_IRQ_I2C_EXT0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2C_EXT0)
#define ESP32S2_IRQ_I2C_EXT1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2C_EXT1)
#define ESP32S2_IRQ_RSA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RSA)
#define ESP32S2_IRQ_SHA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SHA)
#define ESP32S2_IRQ_AES (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_AES)
#define ESP32S2_IRQ_SPI2_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI2_DMA)
#define ESP32S2_IRQ_SPI3_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI3_DMA)
#define ESP32S2_IRQ_WDG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_WDG)
#define ESP32S2_IRQ_TIMER (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TIMER)
#define ESP32S2_IRQ_TIMER_INT2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TIMER_INT2)
#define ESP32S2_IRQ_TG_T0_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T0_EDGE)
#define ESP32S2_IRQ_TG_T1_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T1_EDGE)
#define ESP32S2_IRQ_SREG1 ESP32S2_IRQ_SPI1
#define ESP32S2_NIRQS_SREG1 32
/* PRO_INTR_STATUS_REG_2 */
#define ESP32S2_IRQ_TG_WDT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_WDT_EDGE)
#define ESP32S2_IRQ_TG_LACT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_LACT_EDGE)
#define ESP32S2_IRQ_TG1_T0_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T0_EDGE)
#define ESP32S2_IRQ_TG1_T1_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T1_EDGE)
#define ESP32S2_IRQ_TG1_WDT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_WDT_EDGE)
#define ESP32S2_IRQ_TG1_LACT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_LACT_EDGE)
#define ESP32S2_IRQ_CACHE_IA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CACHE_IA)
#define ESP32S2_IRQ_SYSTIMER_TARGET0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SYSTIMER_TARGET0)
#define ESP32S2_IRQ_SYSTIMER_TARGET1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SYSTIMER_TARGET1)
#define ESP32S2_IRQ_SYSTIMER_TARGET2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SYSTIMER_TARGET2)
#define ESP32S2_IRQ_ASSIST_DEBUG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_ASSIST_DEBUG)
#define ESP32S2_IRQ_PMS_PRO_IRAM0_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_IRAM0_ILG)
#define ESP32S2_IRQ_PMS_PRO_DRAM0_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_DRAM0_ILG)
#define ESP32S2_IRQ_PMS_PRO_DPORT_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_DPORT_ILG)
#define ESP32S2_IRQ_PMS_PRO_AHB_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_AHB_ILG)
#define ESP32S2_IRQ_PMS_PRO_CACHE_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_CACHE_ILG)
#define ESP32S2_IRQ_PMS_DMA_APB_I_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_DMA_APB_I_ILG)
#define ESP32S2_IRQ_PMS_DMA_RX_I_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_DMA_RX_I_ILG)
#define ESP32S2_IRQ_PMS_DMA_TX_I_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_DMA_TX_I_ILG)
#define ESP32S2_IRQ_SPI_MEM_REJECT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI_MEM_REJECT)
#define ESP32S2_IRQ_DMA_COPY (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DMA_COPY)
#define ESP32S2_IRQ_SPI4_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI4_DMA)
#define ESP32S2_IRQ_SPI4 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI4)
#define ESP32S2_IRQ_DCACHE_PRELOAD (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DCACHE_PRELOAD)
#define ESP32S2_IRQ_ICACHE_PRELOAD (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_ICACHE_PRELOAD)
#define ESP32S2_IRQ_APB_ADC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_APB_ADC)
#define ESP32S2_IRQ_CRYPTO_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CRYPTO_DMA)
#define ESP32S2_IRQ_CPU_PERI_ERR (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CPU_PERI_ERR)
#define ESP32S2_IRQ_APB_PERI_ERE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_APB_PERI_ERR)
#define ESP32S2_IRQ_DCACHE_SYNC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DCACHE_SYNC)
#define ESP32S2_IRQ_ICACHE_SYNC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_ICACHE_SYNC)
#define ESP32S2_IRQ_SREG2 ESP32S2_IRQ_TG_WDT_EDGE
#define ESP32S2_NIRQS_SREG2 32
/* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */
#define ESP32S2_IRQ_SREG2 ESP32S2_IRQ_TG1_WDT_EDGE
#define ESP32S2_NIRQS_SREG2 5
#define ESP32S2_NIRQ_PERIPH ESP32S2_NPERIPHERALS
/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched
* as a second level of decoding: The first level dispatches to the GPIO
* interrupt handler. The second to the decoded GPIO interrupt handler.
*/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
# define ESP32S2_NIRQ_GPIO 40
# define ESP32S2_FIRST_GPIOIRQ (XTENSA_NIRQ_INTERNAL+ESP32S2_NIRQ_PERIPH)
# define ESP32S2_LAST_GPIOIRQ (ESP32S2_FIRST_GPIOIRQ+ESP32S2_NIRQ_GPIO-1)
# define ESP32S2_PIN2IRQ(p) ((p) + ESP32S2_FIRST_GPIOIRQ)
# define ESP32S2_IRQ2PIN(i) ((i) - ESP32S2_FIRST_GPIOIRQ)
#else
# define ESP32S2_NIRQ_GPIO 0
#endif
/* Total number of interrupts */
#define NR_IRQS (XTENSA_NIRQ_INTERNAL+ESP32S2_NIRQ_PERIPH+ESP32S2_NIRQ_GPIO)
/* Xtensa CPU Interrupts.
*
* Each of the two CPUs (PRO and APP) have 32 interrupts each, of which
* 26 can be mapped to peripheral interrupts:
*
* Level triggered peripherals (21 total):
* 0-5, 8-9, 12-13, 17-18 - Priority 1
* 19-21 - Priority 2
* 23, 27 - Priority 3
* 24-25 - Priority 4
* 26, 31 - Priority 5
* Edge triggered peripherals (4 total):
* 10 - Priority 1
* 22 - Priority 3
* 28, 30 - Priority 4
* NMI (1 total):
* 14 - NMI
*
* CPU peripheral interrupts can be a assigned to a CPU interrupt using the
* PRO_*_MAP_REG or APP_*_MAP_REG. There are a pair of these registers for
* each peripheral source. Multiple peripheral interrupt sources can be
* mapped to the same CPU interrupt.
*
* The remaining, six, internal CPU interrupts are:
*
* 6 Timer0 - Priority 1
* 7 Software - Priority 1
* 11 Profiling - Priority 3
* 15 Timer1 - Priority 3
* 16 Timer2 - Priority 5
* 29 Software - Priority 3
*
* A peripheral interrupt can be disabled
*/
#define ESP32S2_CPUINT_LEVELPERIPH_0 0
#define ESP32S2_CPUINT_LEVELPERIPH_1 1
#define ESP32S2_CPUINT_LEVELPERIPH_2 2
#define ESP32S2_CPUINT_LEVELPERIPH_3 3
#define ESP32S2_CPUINT_LEVELPERIPH_4 4
#define ESP32S2_CPUINT_LEVELPERIPH_5 5
#define ESP32S2_CPUINT_LEVELPERIPH_6 8
#define ESP32S2_CPUINT_LEVELPERIPH_7 9
#define ESP32S2_CPUINT_LEVELPERIPH_8 12
#define ESP32S2_CPUINT_LEVELPERIPH_9 13
#define ESP32S2_CPUINT_LEVELPERIPH_10 17
#define ESP32S2_CPUINT_LEVELPERIPH_11 18
#define ESP32S2_CPUINT_LEVELPERIPH_12 19
#define ESP32S2_CPUINT_LEVELPERIPH_13 20
#define ESP32S2_CPUINT_LEVELPERIPH_14 21
#define ESP32S2_CPUINT_LEVELPERIPH_15 23
#define ESP32S2_CPUINT_LEVELPERIPH_16 24
#define ESP32S2_CPUINT_LEVELPERIPH_17 25
#define ESP32S2_CPUINT_LEVELPERIPH_18 26
#define ESP32S2_CPUINT_LEVELPERIPH_19 27
#define ESP32S2_CPUINT_LEVELPERIPH_20 31
#define ESP32S2_CPUINT_NLEVELPERIPHS 21
#define EPS32_CPUINT_LEVELSET 0x8fbe333f
#define ESP32S2_CPUINT_EDGEPERIPH_0 10
#define ESP32S2_CPUINT_EDGEPERIPH_1 22
#define ESP32S2_CPUINT_EDGEPERIPH_2 28
#define ESP32S2_CPUINT_EDGEPERIPH_3 30
#define ESP32S2_CPUINT_NEDGEPERIPHS 4
#define EPS32_CPUINT_EDGESET 0x50400400
#define ESP32S2_CPUINT_NNMIPERIPHS 1
#define EPS32_CPUINT_NMISET 0x00004000
#define ESP32S2_CPUINT_MAC 0
#define ESP32S2_CPUINT_TIMER0 6
#define ESP32S2_CPUINT_SOFTWARE0 7
#define ESP32S2_CPUINT_PROFILING 11
#define ESP32S2_CPUINT_TIMER1 15
#define ESP32S2_CPUINT_TIMER2 16
#define ESP32S2_CPUINT_SOFTWARE1 29
#define ESP32S2_CPUINT_NINTERNAL 6
#define ESP32S2_NCPUINTS 32
#define ESP32S2_CPUINT_MAX (ESP32S2_NCPUINTS - 1)
#define ESP32_CPUINT_PERIPHSET 0xdffe773f
#define EPS32_CPUINT_INTERNALSET 0x200188c0
/* Priority 1: 0-10, 12-13, 17-18 (15)
* Priority 2: 19-21 (3)
* Priority 3: 11, 15, 22-23, 27, 29 (6)
* Priority 4: 24-25, 28, 30 (4)
* Priority 5: 16, 26, 31 (3)
* Priority NMI: 14 (1)
*/
#define ESP32S2_INTPRI1_MASK 0x000637ff
#define ESP32S2_INTPRI2_MASK 0x00380000
#define ESP32S2_INTPRI3_MASK 0x28c08800
#define ESP32S2_INTPRI4_MASK 0x53000000
#define ESP32S2_INTPRI5_MASK 0x84010000
#define ESP32S2_INTNMI_MASK 0x00004000
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H */

139
arch/xtensa/include/esp32s2/memory_layout.h Normal file

@ -0,0 +1,139 @@
/****************************************************************************
* arch/xtensa/include/esp32s2/memory_layout.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The heap overview:
*
* CONFIG_HEAP2_BASE eg. 3f80 0000
* :
* : g_mmheap (CONFIG_ESP32_SPIRAM)
* :
* CONFIG_HEAP2_BASE + CONFIG_HEAP2_SIZE eg. 3fc0 0000
*
* HEAP_REGION0_START 3ffa e6f0
* :
* : g_mmheap region0
* :
* HEAP_REGION0_END 3ffa fff0
* :
* _sheap eg. 3ffc 8c6c
* :
* : g_mmheap region1
* :
* HEAP_REGION1_END 3ffd fff0
* :
* : ROM data
* :
*---------------------------------------------------------------------
*
* HEAP_REGION2_START 3ffe 0450
* :
* : g_iheap (CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP)
* :
* HEAP_REGION2_START + CONFIG_XTENSA_IMEM_REGION_SIZE
* :
* : g_mmheap region2
* :
*---------------------------------------------------------------------
* _eheap 4000 0000
*/
/* This region is supposed to be part of the ROM data. However, the ROM
* isn't using the last 6KB, so we get it as heap. It's called REGION0
* because it starts before _sheap.
* Although this region is adjacent to 0x3ffb0000 (start of static memory)
* we don't add it to static memory but we add it as heap. The reason is the
* Bluetooth controller uses a fixed 64KB region at the start of 0x3ffb0000.
* It's cleaner, from a source code perspective, to start static memory at
* 0x3ffb0000 and get what's before that as heap.
*/
#define HEAP_REGION0_START 0x3ffae6f0
#define HEAP_REGION0_END 0x3ffafff0
/* Region 1 of the heap is the area from the end of the .data section to the
* beginning of the ROM data. The start address is defined from the linker
* script as "_sheap". The end is defined here, as follows:
*/
#define HEAP_REGION1_END 0x3ffdfff0
/* Region 2 of the heap is the area from the end of the ROM data to the end
* of DRAM. The linker script has already set "_eheap" as the end of DRAM,
* the following defines the start of region2.
* N.B: That ROM data consists of 2 regions, one per CPU. If SMP is not
* enabled include APP's region with the heap.
*
* When an internal heap is enabled this region starts at an offset equal to
* the size of the internal heap.
*
* The QEMU bootloader image is slightly different than the chip's one.
* The ROM on PRO and APP CPUs uses different regions for static data.
* In QEMU, however, we load only one ROM binary, taken from the PRO CPU,
* and it is used by both CPUs. So, in QEMU, if we allocate PRO CPUs region
* early, it will be clobbered once the APP CPU starts.
* We can delay the allocation to when everything has started through the
* board_late_initiliaze hook, as is done for the APP data, however this
* should be fixed from QEMU side. The following macros, then, just skip
* PRO CPU's regions when a QEMU image generation is enabled with SMP.
*/
#if defined(CONFIG_ESP32_QEMU_IMAGE) && defined(CONFIG_SMP)
# define HEAP_REGION2_START 0x3ffe7e40
#else
# define HEAP_REGION2_START 0x3ffe0450
#endif
#ifdef CONFIG_SMP
# define HEAP_REGION2_END 0x3ffe3f10
# define HEAP_REGION3_START 0x3ffe5240
#endif
#ifdef CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP
# define XTENSA_IMEM_REGION_SIZE CONFIG_XTENSA_IMEM_REGION_SIZE
#else
# define XTENSA_IMEM_REGION_SIZE 0
#endif
/* Internal heap starts at the end of the ROM data.
* This is either the start of region2 if SMP is disabled or start of region3
* if SMP is enabled.
*/
#ifndef CONFIG_SMP
# define ESP32_IMEM_START HEAP_REGION2_START
#else
# define ESP32_IMEM_START HEAP_REGION3_START
#endif
/* Region of unused ROM App data */
#define HEAP_REGION_ROMAPP_START 0x3ffe4360
#define HEAP_REGION_ROMAPP_END 0x3ffe5230

150
arch/xtensa/include/esp32s2/tie-asm.h Normal file

@ -0,0 +1,150 @@
/****************************************************************************
* arch/xtensa/include/esp32s2/tie-asm.h
* Compile-time assembler definitions dependent on CORE & TIE
*
* This header file contains assembly-language definitions (assembly
* macros, etc.) for this specific Xtensa processor's TIE extensions
* and options. It is customized to this Xtensa processor configuration.
*
* Customer ID=11657; Build=0x5fe96;
* Copyright (c) 1999-2016 Cadence Design Systems Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H
#define __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Selection parameter values for save-area save/restore macros: */
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
/* Whether used automatically by compiler: */
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
/* ABI handling across function calls: */
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
/* Misc */
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
| ((ccuse) & XTHAL_SAS_ANYCC) \
| ((abi) & XTHAL_SAS_ANYABI) )
/* Macro to store all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first
* XCHAL_NCP_NUM_ATMPS registers are clobbered, the
* remaining are unused).
* Optional parameters:
* continue If macro invoked as part of a larger store sequence,
* set to 1 if this is not the first in the sequence.
* Defaults to 0.
* ofs Offset from start of larger sequence (from value of first
* ptr in sequence) at which to store. Defaults to next
* available space (or 0 if <continue> is 0).
* select Select what category(ies) of registers to store, as a
* bitmask (see XTHAL_SAS_xxx constants). Defaults to all
* registers.
* alloc Select what category(ies) of registers to allocate; if
* any category is selected here that is not in <select>,
* space for the corresponding registers is skipped without
* doing any store.
*/
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
/* Optional global registers used by default by the compiler: */
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
rur.THREADPTR \at1 /* threadptr option */
s32i \at1, \ptr, .Lxchal_ofs_+0
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
.endm /* xchal_ncp_store */
/* Macro to load all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Required parameters:
* ptr Save area pointer address register (clobbered)
* (register must contain a 4 byte aligned address).
* at1..at4 Four temporary address registers (first
* XCHAL_NCP_NUM_ATMPS registers are clobbered, the
* remaining are unused).
* Optional parameters:
* continue If macro invoked as part of a larger load sequence, set
* to 1 if this is not the first in the sequence. Defaults
* to 0.
* ofs Offset from start of larger sequence (from value of first
* ptr in sequence) at which to load. Defaults to next
* available space (or 0 if <continue> is 0).
* select Select what category(ies) of registers to load, as a
* bitmask (see XTHAL_SAS_xxx constants). Defaults to all
* registers.
* alloc Select what category(ies) of registers to allocate; if
* any category is selected here that is not in <select>,
* space for the corresponding registers is skipped without
* doing any load.
*/
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
xchal_sa_start \continue, \ofs
/* Optional global registers used by default by the compiler: */
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
xchal_sa_align \ptr, 0, 1016, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_+0
wur.THREADPTR \at1 /* threadptr option */
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
xchal_sa_align \ptr, 0, 1016, 4, 4
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
.endm /* xchal_ncp_load */
#define XCHAL_NCP_NUM_ATMPS 1
#define XCHAL_SA_NUM_ATMPS 1
#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H */

194
arch/xtensa/include/esp32s2/tie.h Normal file

@ -0,0 +1,194 @@
/****************************************************************************
* arch/xtensa/include/esp32s2/tie.h
* Compile-time HAL definitions dependent on CORE & TIE configuration
*
* NOTE: This header file is not meant to be included directly.
*
* This header file describes this specific Xtensa processor's TIE extensions
* that extend basic Xtensa core functionality. It is customized to this
* Xtensa processor configuration.
*
* Customer ID=11657; Build=0x5fe96;
* Copyright (c) 1999-2016 Cadence Design Systems Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
****************************************************************************/
#ifndef _ARCH_XTENSA_INCLUDE_ESP32S2_TIE_H
#define _ARCH_XTENSA_INCLUDE_ESP32S2_TIE_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define XCHAL_CP_NUM 1 /* number of coprocessors */
#define XCHAL_CP_MAX 1 /* max CP ID + 1 (0 if none) */
#define XCHAL_CP_MASK 0x01 /* bitmask of all CPs by ID */
#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
/* Basic parameters of each coprocessor: */
#define XCHAL_CP0_NAME "FPU"
#define XCHAL_CP0_IDENT FPU
#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP6_SA_SIZE 0
#define XCHAL_CP6_SA_ALIGN 1
#define XCHAL_CP7_SA_SIZE 0
#define XCHAL_CP7_SA_ALIGN 1
/* Save area for non-coprocessor optional and custom (TIE) state: */
#define XCHAL_NCP_SA_SIZE 48
#define XCHAL_NCP_SA_ALIGN 4
/* Total save area for optional and custom state (NCP + CPn): */
#define XCHAL_TOTAL_SA_SIZE 128 /* With 16-byte align padding */
#define XCHAL_TOTAL_SA_ALIGN 4 /* Actual minimum alignment */
/* Detailed contents of save areas.
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
* before expanding the XCHAL_xxx_SA_LIST() macros.
*
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
*
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
* ccused = set if used by compiler without special options or code
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
* name = lowercase reg name (no quotes)
* galign = group byte alignment (power of 2) (galign >= align)
* align = register byte alignment (power of 2)
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
* (not including any pad bytes required to galign this or next reg)
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
* regnum = reg index in regfile, or special/TIE-user reg number
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
* gapsz = intervening bits, if bitsz bits not stored contiguously
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
* reset = register reset value (or 0 if undefined at reset)
* x = reserved for future use (0 until then)
*
* To filter out certain registers, e.g. to expand only the non-global
* registers used by the compiler, you can do something like this:
*
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
* #define SELCC0(p...)
* #define SELCC1(abikind,p...) SELAK##abikind(p)
* #define SELAK0(p...) REG(p)
* #define SELAK1(p...) REG(p)
* #define SELAK2(p...)
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
* ...what you want to expand...
*/
#define XCHAL_NCP_SA_NUM 12
#define XCHAL_NCP_SA_LIST(s) \
XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64r_lo, 4, 4, 4,0x03EA, ur,234, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64r_hi, 4, 4, 4,0x03EB, ur,235, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, f64s, 4, 4, 4,0x03EC, ur,236, 32,0,0,0)
#define XCHAL_CP0_SA_NUM 18
#define XCHAL_CP0_SA_LIST(s) \
XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
#define XCHAL_CP1_SA_NUM 0
#define XCHAL_CP1_SA_LIST(s) /* empty */
#define XCHAL_CP2_SA_NUM 0
#define XCHAL_CP2_SA_LIST(s) /* empty */
#define XCHAL_CP3_SA_NUM 0
#define XCHAL_CP3_SA_LIST(s) /* empty */
#define XCHAL_CP4_SA_NUM 0
#define XCHAL_CP4_SA_LIST(s) /* empty */
#define XCHAL_CP5_SA_NUM 0
#define XCHAL_CP5_SA_LIST(s) /* empty */
#define XCHAL_CP6_SA_NUM 0
#define XCHAL_CP6_SA_LIST(s) /* empty */
#define XCHAL_CP7_SA_NUM 0
#define XCHAL_CP7_SA_LIST(s) /* empty */
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
/* Byte length of instruction from its first byte, per FLIX. */
#define XCHAL_BYTE0_FORMAT_LENGTHS \
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
#endif /* _ARCH_XTENSA_INCLUDE_ESP32S2_TIE_H */

11
arch/xtensa/include/irq.h

@ -55,6 +55,17 @@
# error Unknown LX6 implementation
# endif
#elif CONFIG_ARCH_FAMILY_LX7
# include <arch/lx7/irq.h>
/* Include implementation-specific IRQ definitions (including IRQ numbers) */
# ifdef CONFIG_ARCH_CHIP_ESP32S2
# include <arch/esp32s2/irq.h>
# else
# error Unknown LX7 implementation
# endif
#else
# error Unknown XTENSA architecture
#endif

68
arch/xtensa/include/lx7/irq.h Normal file

@ -0,0 +1,68 @@
/****************************************************************************
* arch/xtensa/include/lx7/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_XTENSA_INCLUDE_LX7_IRQ_H
#define __ARCH_XTENSA_INCLUDE_LX7_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_INCLUDE_LX7_IRQ_H */

2
arch/xtensa/include/xtensa/xtensa_coproc.h

@ -38,7 +38,7 @@
* Included Files
****************************************************************************/
#include <arch/esp32/core-isa.h>
#include <arch/chip/core-isa.h>
/****************************************************************************
* Pre-processor Definitions

4
arch/xtensa/src/Makefile

@ -25,6 +25,10 @@ ifeq ($(CONFIG_ARCH_FAMILY_LX6),y)
ARCH_SUBDIR = lx6
endif
ifeq ($(CONFIG_ARCH_FAMILY_LX7),y)
ARCH_SUBDIR = lx7
endif
ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip}

4
arch/xtensa/src/common/xtensa_coproc.S

@ -128,7 +128,7 @@ _xtensa_coproc_savestate:
bbci.l a2, 0, 2f /* CP 0 not enabled */
l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */
add a3, a14, a15 /* a3 = save area for CP 0 */
xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
xchal_ncp_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif
@ -327,7 +327,7 @@ _xtensa_coproc_restorestate:
bbci.l a2, 0, 2f /* CP 0 not enabled */
l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */
add a3, a14, a15 /* a3 = save area for CP 0 */
xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
xchal_ncp_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
2:
#endif

911
arch/xtensa/src/esp32s2/Kconfig Normal file

@ -0,0 +1,911 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_CHIP_ESP32S2
comment "ESP32S2 Configuration Options"
choice
prompt "ESP32S2 Chip Selection"
default ARCH_CHIP_ESP32S2WROVER
depends on ARCH_CHIP_ESP32S2
config ARCH_CHIP_ESP32S2WROVER
bool "ESP32S2-WROVER"
select ESP32S2_ESP32S2DXWDXX
select ESP32S2_FLASH_4M
select ESP32S2_PSRAM_8M
---help---
Generic module with an embedded ESP32S2
endchoice # ESP32S2 Chip Selection
choice
prompt "Instruction CACHE Size"
default ESP32S2_INSTRUCTION_CACHE_8KB
depends on ARCH_CHIP_ESP32S2
config ESP32S2_INSTRUCTION_CACHE_8KB
bool "8KB"
---help---
Use 8KB of SRAM as Instruction Cache
config ESP32S2_INSTRUCTION_CACHE_16KB
bool "16KB"
---help---
Use 16KB of SRAM as Instruction Cache
endchoice # ESP32S2 Instruction CACHE size
choice
prompt "Instruction CACHE Size"
default ESP32S2_INSTRUCTION_CACHE_8KB
depends on ARCH_CHIP_ESP32S2
config ESP32S2_DATA_CACHE_0KB
bool "No DATA CACHE"
---help---
Use 8KB of SRAM as Data Cache
config ESP32S2_DATA_CACHE_8KB
bool "8KB"
---help---
Use 8KB of SRAM as Data Cache
config ESP32S2_DATA_CACHE_16KB
bool "16KB"
---help---
Use 16KB of SRAM as Data Cache
endchoice # ESP32S2 Data CACHE size
config ESP32S2_SINGLE_CPU
bool
default y
config ESP32S2_FLASH_2M
bool
default n
config ESP32S2_FLASH_4M
bool
default n
config ESP32S2_FLASH_8M
bool
default n
config ESP32S2_FLASH_16M
bool
default n
config ESP32S2_FLASH_DETECT
bool "Auto-detect FLASH size"
default y
help
Auto detect flash size when flashing.
config ESP32S2_PSRAM_8M
bool
default n
config ESP32S2_ESP32S2SXWDXX
bool
default n
select ESP32S2_SINGLE_CPU
select ARCH_HAVE_I2CRESET
choice ESP32S2_FLASH_MODE
prompt "SPI FLASH mode"
default ESP32S2_FLASH_MODE_DIO
help
These options control how many I/O pins are used for communication
with the attached SPI flash chip.
The option selected here is then used by esptool when flashing.
config ESP32S2_FLASH_MODE_DIO
bool "Dual IO (DIO)"
config ESP32S2_FLASH_MODE_DOUT
bool "Dual Output (DOUT)"
config ESP32S2_FLASH_MODE_QIO
bool "Quad IO (QIO)"
config ESP32S2_FLASH_MODE_QOUT
bool "Quad Output (QOUT)"
endchoice # ESP32S2_FLASH_MODE
choice ESP32S2_FLASH_FREQ
prompt "SPI FLASH frequency"
default ESP32S2_FLASH_FREQ_40M
help
SPI FLASH frequency
config ESP32S2_FLASH_FREQ_80M
bool "80 MHz"
config ESP32S2_FLASH_FREQ_40M
bool "40 MHz"
config ESP32S2_FLASH_FREQ_26M
bool "26 MHz"
config ESP32S2_FLASH_FREQ_20M
bool "20 MHz"
endchoice # ESP32S2_FLASH_FREQ
choice ESP32S2_DEFAULT_CPU_FREQ
prompt "CPU frequency"
default ESP32S2_DEFAULT_CPU_FREQ_240
help
CPU frequency to be set on application startup.
config ESP32S2_DEFAULT_CPU_FREQ_80
bool "80 MHz"
config ESP32S2_DEFAULT_CPU_FREQ_160
bool "160 MHz"
config ESP32S2_DEFAULT_CPU_FREQ_240
bool "240 MHz"
endchoice # CPU frequency
config ESP32S2_DEFAULT_CPU_FREQ_MHZ
int
default 80 if ESP32S2_DEFAULT_CPU_FREQ_80
default 160 if ESP32S2_DEFAULT_CPU_FREQ_160
default 240 if ESP32S2_DEFAULT_CPU_FREQ_240
choice
prompt "On-board Crystal Frequency"
default ESP32S2_XTAL_40MZ
config ESP32S2_XTAL_40MZ
bool "40MHz"
config ESP32S2_XTAL_26MHz
bool "26MHz"
endchoice # On-board Crystal Frequency
config ESP32S2_RT_TIMER
bool "Real-time Timer"
default n
config ESP32S2_PARTITION
bool "ESP32S2 Partition"
default n
select ESP32S2_SPIFLASH
---help---
Decode esp-idf's partition file and initialize
partition by nuttx MTD.
config ESP32S2_RUN_IRAM
bool "Run from IRAM"
default n
---help---
This loads all of NuttX inside IRAM. Used to test somewhat small
images that can fit entirely in IRAM.
menu "ESP32S2 Peripheral Selection"
config ESP32S2_UART
bool
default n
config ESP32S2_TIMER
bool
default n
config ESP32S2_WDT
bool
default n
config ESP32S2_BT
bool "Bluetooth"
default n
depends on EXPERIMENTAL
---help---
No yet implemented
config ESP32S2_EFUSE
bool "EFUSE support"
default n
---help---
Enable ESP32S2 efuse support.
config ESP32S2_I2C
bool
default n
config ESP32S2_I2S0
bool "I2S 0"
default n
depends on EXPERIMENTAL
---help---
No yet implemented
config ESP32S2_LEDC
bool "LED PWM (LEDC)"
default n
depends on EXPERIMENTAL
---help---
No yet implemented
config ESP32S2_PCNT
bool "Pulse Count Module (PCNT)"
default n
depends on EXPERIMENTAL
---help---
No yet implemented
config ESP32S2_RMT
bool "Remote Control Module (RMT)"
default n
depends on EXPERIMENTAL
---help---
No yet implemented
config ESP32S2_RNG
bool "Random Number Generator (RNG)"
default n
select ARCH_HAVE_RNG
---help---
ESP32S2 supports a RNG that passed on Dieharder test suite.
config ESP32S2_SPI
bool
default n
config ESP32S2_SPIFLASH
bool "SPI Flash"
default n
select MTD
select MTD_BYTE_WRITE
select MTD_PARTITION
config ESP32S2_SPI2
bool "SPI 2"
default n
select ESP32S2_SPI
select ESP32S2_GPIO_IRQ
select SPI
config ESP32S2_SPI3
bool "SPI 3"
default n
select ESP32S2_SPI
select ESP32S2_GPIO_IRQ
select SPI
config ESP32S2_SPIRAM
bool "SPI RAM Support"
default n
select ARCH_HAVE_HEAP2
select XTENSA_IMEM_USE_SEPARATE_HEAP
if ESP32S2_SPIRAM && SMP
choice
prompt "How does SPIRAM share cache?"
default ESP32S2_MEMMAP_SPIRAM_CACHE_EVENODD
help
Selects the cache mode to CPU access the external memory.
config ESP32S2_MEMMAP_SPIRAM_CACHE_EVENODD
bool "Pro CPU uses even 32 byte ranges, App uses odd ones"
config ESP32S2_MEMMAP_SPIRAM_CACHE_LOWHIGH
bool "Pro CPU uses low 2MB ranges, App uses high ones"
endchoice # CPU frequency
endif
config XTENSA_TIMER1
bool "Xtensa Timer 1"
default n
config XTENSA_TIMER2
bool "Xtensa Timer 2"
default n
config ESP32S2_TIMER0
bool "64-bit Timer 0 (Group 0 Timer 0)"
default n
select ESP32S2_TIMER
---help---
Enables Timer
config ESP32S2_TIMER1
bool "64-bit Timer 1 (Group 0 Timer 1)"
default n
select ESP32S2_TIMER
---help---
Enables Timer
config ESP32S2_TIMER2
bool "64-bit Timer 2 (Group 1 Timer 0)"
default n
select ESP32S2_TIMER
---help---
Enables Timer
config ESP32S2_TIMER3
bool "64-bit Timer 3 (Group 1 Timer 1)"
default n
select ESP32S2_TIMER
---help---
Enables Timer
config ESP32S2_MWDT0
bool "Main System Watchdog Timer (Group 0)"
default n
select ESP32S2_WDT
---help---
Includes MWDT0. This watchdog timer is part of the Group 0
timer submodule.
config ESP32S2_MWDT1
bool "Main System Watchdog Timer (Group 1)"
default n
select ESP32S2_WDT
---help---
Includes MWDT1. This watchdog timer is part of the Group 0
timer submodule.
config ESP32S2_RWDT
bool "RTC Watchdog Timer"
default n
select ESP32S2_WDT
---help---
Includes RWDT. This watchdog timer is from the RTC module.
When it is selected, if the developer sets it to reset on expiration
it will reset Main System and the RTC module. If you don't want
to have the RTC module reset, please, use the Timers' Module WDTs.
They will only reset Main System.
config ESP32S2_UART0
bool "UART 0"
default n
select ESP32S2_UART
select UART0_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config ESP32S2_UART1
bool "UART 1"
default n
select ESP32S2_UART
select UART1_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config ESP32S2_UART2
bool "UART 2"
default n
select ESP32S2_UART
select UART2_SERIALDRIVER
select ARCH_HAVE_SERIAL_TERMIOS
config ESP32S2_WIRELESS
bool "Wireless"
default n
select NET
select ARCH_PHY_INTERRUPT
select ESP32S2_RNG
select ESP32S2_RT_TIMER
select ESP32S2_TIMER0
---help---
Enable Wireless support
config ESP32S2_I2C0
bool "I2C 0"
default n
select ESP32S2_I2C
config ESP32S2_I2C1
bool "I2C 1"
default n
select ESP32S2_I2C
config ESP32S2_AES_ACCELERATOR
bool "AES Accelerator"
default n
endmenu # ESP32S2 Peripheral Selection
menu "Memory Configuration"
config ESP32S2_BT_RESERVE_DRAM
int "Reserved BT DRAM"
default 0
config ESP32S2_TRACEMEM_RESERVE_DRAM
int "Reserved trace memory DRAM"
default 0
config ESP32S2_ULP_COPROC_RESERVE_MEM
int "Reserved ULP co-processor DRAM"
default 0
endmenu # Memory Configuration
config ESP32S2_GPIO_IRQ
bool "GPIO pin interrupts"
---help---
Enable support for interrupting GPIO pins
menu "UART configuration"
depends on ESP32S2_UART
if ESP32S2_UART0
config ESP32S2_UART0_TXPIN
int "UART0 Tx Pin"
default 43
range 0 46
config ESP32S2_UART0_RXPIN
int "UART0 Rx Pin"
default 44
range 0 46
if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL
config ESP32S2_UART0_RTSPIN
int "UART0 RTS Pin"
default 22
range 0 39
config ESP32S2_UART0_CTSPIN
int "UART0 CTS Pin"
default 19
range 0 39
endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL
endif # ESP32S2_UART0
if ESP32S2_UART1
config ESP32S2_UART1_TXPIN
int "UART1 Tx Pin"
default 10
range 0 39
config ESP32S2_UART1_RXPIN
int "UART1 Rx Pin"
default 9
range 0 39
if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL
config ESP32S2_UART1_RTSPIN
int "UART1 RTS Pin"
default 11
range 0 39
config ESP32S2_UART1_CTSPIN
int "UART1 CTS Pin"
default 6
range 0 39
endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL
endif # ESP32S2_UART1
if ESP32S2_UART2
config ESP32S2_UART2_TXPIN
int "UART2 Tx Pin"
default 17
range 0 39
config ESP32S2_UART2_RXPIN
int "UART2 Rx Pin"
default 16
range 0 39
if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL
config ESP32S2_UART2_RTSPIN
int "UART2 RTS Pin"
default 7
range 0 39
config ESP32S2_UART2_CTSPIN
int "UART2 CTS Pin"
default 8
range 0 39
endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL
endif # ESP32S2_UART2
endmenu # UART configuration
menu "I2C configuration"
depends on ESP32S2_I2C
if ESP32S2_I2C0
config ESP32S2_I2C0_SCLPIN
int "I2C0 SCL Pin"
default 22
range 0 39
config ESP32S2_I2C0_SDAPIN
int "I2C0 SDA Pin"
default 23
range 0 39
endif # ESP32S2_I2C0
if ESP32S2_I2C1
config ESP32S2_I2C1_SCLPIN
int "I2C1 SCL Pin"
default 26
range 0 39
config ESP32S2_I2C1_SDAPIN
int "I2C1 SDA Pin"
default 25
range 0 39
endif # ESP32S2_I2C1
endmenu # I2C configuration
menu "SPI configuration"
depends on ESP32S2_SPI
config ESP32S2_SPI_SWCS
bool "SPI software CS"
default y
---help---
Use SPI software CS.
config ESP32S2_SPI_UDCS
bool "User defined CS"
default n
depends on ESP32S2_SPI_SWCS
---help---
Use user defined CS.
config ESP32S2_SPI2_DMA
bool "SPI2 use DMA"
default y
depends on ESP32S2_SPI2
config ESP32S2_SPI3_DMA
bool "SPI3 use DMA"
default y
depends on ESP32S2_SPI3
config SPI_DMADESC_NUM
int "SPI master DMA description number"
default 2
config SPI_SLAVE_BUFSIZE
int "SPI slave buffer size"
default 2048
depends on SPI_SLAVE
config ESP32S2_SPI_DMATHRESHOLD
int "SPI DMA threshold"
default 64
depends on ESP32S2_SPI2_DMA || ESP32S2_SPI3_DMA
---help---
When SPI DMA is enabled, DMA transfers whose size are below the
defined threshold will be performed by polling logic.
if ESP32S2_SPI2
config ESP32S2_SPI2_CSPIN
int "SPI2 CS Pin"
default 15
range 0 39
config ESP32S2_SPI2_CLKPIN
int "SPI2 CLK Pin"
default 14
range 0 39
config ESP32S2_SPI2_MOSIPIN
int "SPI2 MOSI Pin"
default 13
range 0 39
config ESP32S2_SPI2_MISOPIN
int "SPI2 MISO Pin"
default 12
range 0 39
endif # ESP32S2_SPI2
if ESP32S2_SPI3
config ESP32S2_SPI3_CSPIN
int "SPI3 CS Pin"
default 5
range 0 39
config ESP32S2_SPI3_CLKPIN
int "SPI3 CLK Pin"
default 18
range 0 39
config ESP32S2_SPI3_MOSIPIN
int "SPI3 MOSI Pin"
default 23
range 0 39
config ESP32S2_SPI3_MISOPIN
int "SPI3 MISO Pin"
default 19
range 0 39
endif # ESP32S2_SPI3
endmenu # ESP32S2_SPI
menu "SPI Flash configuration"
depends on ESP32S2_SPIFLASH
config ESP32S2_MTD_OFFSET
hex "MTD base address in SPI Flash"
default 0x180000
help
MTD base address in SPI Flash.
config ESP32S2_MTD_SIZE
hex "MTD size in SPI Flash"
default 0x100000
help
MTD size in SPI Flash.
config ESP32S2_SPIFLASH_DEBUG
bool "Debug SPI Flash"
default n
depends on DEBUG_FS_INFO
help
Enable this option, read and write of SPI Flash
will show input arguments and result.
endmenu # ESP32S2_SPIFLASH
menu "SPI RAM Config"
depends on ESP32S2_SPIRAM
choice ESP32S2_SPIRAM_TYPE
prompt "Type of SPI RAM chip in use"
default ESP32S2_SPIRAM_TYPE_AUTO
config ESP32S2_SPIRAM_TYPE_AUTO
bool "Auto-detect"
config ESP32S2_SPIRAM_TYPE_ESPPSRAM32
bool "ESP-PSRAM32 or IS25WP032"
config ESP32S2_SPIRAM_TYPE_ESPPSRAM64
bool "ESP-PSRAM64 or LY68L6400"
endchoice #ESP32S2_SPIRAM_TYPE
config ESP32S2_SPIRAM_SIZE
int
default -1 if ESP32S2_SPIRAM_TYPE_AUTO
default 4194304 if ESP32S2_SPIRAM_TYPE_ESPPSRAM32
default 8388608 if ESP32S2_SPIRAM_TYPE_ESPPSRAM64
default 0
choice ESP32S2_SPIRAM_SPEED
prompt "Set RAM clock speed"
default ESP32S2_SPIRAM_SPEED_40M
help
Select the speed for the SPI RAM chip.
config ESP32S2_SPIRAM_SPEED_40M
bool "40MHz clock speed"
config ESP32S2_SPIRAM_SPEED_80M
bool "80MHz clock speed"
endchoice # ESP32S2_SPIRAM_SPEED
config ESP32S2_SPIRAM_BOOT_INIT
bool "Initialize SPI RAM during startup"
depends on ESP32S2_SPIRAM
default "y"
help
If this is enabled, the SPI RAM will be enabled during initial
boot. Unless you have specific requirements, you'll want to leave
this enabled so memory allocated during boot-up can also be
placed in SPI RAM.
config ESP32S2_SPIRAM_IGNORE_NOTFOUND
bool "Ignore PSRAM when not found"
default "n"
depends on ESP32S2_SPIRAM_BOOT_INIT && !BOOT_SDRAM_DATA
help
Normally, if psram initialization is enabled during compile time
but not found at runtime, it is seen as an error making the CPU
panic. If this is enabled, booting will complete but no PSRAM
will be available.
config ESP32S2_SPIRAM_2T_MODE
bool "Enable SPI PSRAM 2T mode"
depends on ESP32S2_SPIRAM
default "n"
help
Enable this option to fix single bit errors inside 64Mbit PSRAM.
Some 64Mbit PSRAM chips have a hardware issue in the RAM which
causes bit errors at multiple fixed bit positions.
Note: If this option is enabled, the 64Mbit PSRAM chip will appear
to be 32Mbit in size.
Applications will not be affected unless the use the esp_himem
APIs, which are not supported in 2T mode.
config ESP32S2_SPIRAM_BANKSWITCH_ENABLE
bool "Enable bank switching for >4MiB external RAM"
default y
help
The ESP32S2 only supports 4MiB of external RAM in its address
space. The hardware does support larger memories, but these
have to be bank-switched in and out of this address space.
Enabling this allows you to reserve some MMU pages for this,
which allows the use of the esp_himem api to manage these
banks.
#Note that this is limited to 62 banks, as
#esp_spiram_writeback_cache needs some kind of mapping of
#some banks below that mark to work. We cannot at this
#moment guarantee this to exist when himem is enabled.
If spiram 2T mode is enabled, the size of 64Mbit psram will
be changed as 32Mbit, so himem will be unusable.
config SPIRAM_BANKSWITCH_RESERVE
int "Amount of 32K pages to reserve for bank switching"
depends on ESP32S2_SPIRAM_BANKSWITCH_ENABLE
default 8
range 1 62
help
Select the amount of banks reserved for bank switching. Note
that the amount of RAM allocatable with malloc will decrease
by 32K for each page reserved here.
Note that this reservation is only actually done if your
program actually uses the himem API. Without any himem
calls, the reservation is not done and the original amount
of memory will be available.
endmenu #SPI RAM Config
menu "WiFi configuration"
depends on ESP32S2_WIRELESS
choice
prompt "ESP32S2 WiFi mode"
default ESP32S2_WIFI_STATION
config ESP32S2_WIFI_STATION
bool "Station mode"
config ESP32S2_WIFI_SOFTAP
bool "SoftAP mode"
config ESP32S2_WIFI_STATION_SOFTAP_COEXISTENCE
bool "Station + SoftAP coexistence"
endchoice # ESP32S2 WiFi mode
config ESP32S2_WIFI_STATIC_RXBUF_NUM
int "WiFi static RX buffer number"
default 10
config ESP32S2_WIFI_DYNAMIC_RXBUF_NUM
int "WiFi dynamic RX buffer number"
default 32
config ESP32S2_WIFI_DYNAMIC_TXBUF_NUM
int "WiFi dynamic TX buffer number"
default 32
config ESP32S2_WIFI_TX_AMPDU
bool "WiFi TX AMPDU"
default y
config ESP32S2_WIFI_RX_AMPDU
bool "WiFi RX AMPDU"
default y
config ESP32S2_WIFI_RXBA_AMPDU_WZ
int "WiFi RX BA AMPDU windown size"
default 6
config ESP32S2_WLAN_PKTBUF_NUM
int "WLAN netcard packet buffer number per netcard"
default 16
config ESP32S2_WIFI_CONNECT_TIMEOUT
int "Connect timeout by second"
default 10
help
Max waiting time of connecting to AP.
config ESP32S2_WIFI_SCAN_RESULT_SIZE
int "Scan result buffer"
default 4096
help
Maximum scan result buffer size.
config ESP32S2_WIFI_SAVE_PARAM
bool "Save WiFi Parameters"
default n
help
If you enable this option, WiFi adapter parameters will be saved
into the file system instead of computing them each time.
These parameters mainly contains:
- SSID
- Password
- BSSID
- PMK(compute when connecting)
- Author mode
- MAC address
- WiFi hardware configuration parameters
config ESP32S2_WIFI_FS_MOUNTPT
string "Save WiFi Parameters"
default "/mnt/esp/wifi"
depends on ESP32S2_WIFI_SAVE_PARAM
help
Mount point of WiFi storage file system.
endmenu # ESP32S2_WIRELESS
menu "Real-Time Timer"
depends on ESP32S2_RT_TIMER
config ESP32S2_RT_TIMER_TASK_NAME
string "Timer task name"
default "rt_timer"
config ESP32S2_RT_TIMER_TASK_PRIORITY
int "Timer task priority"
default 223 # Lower than high priority workqueue
config ESP32S2_RT_TIMER_TASK_STACK_SIZE
int "Timer task stack size"
default 2048
endmenu # Real-Time Timer
if ESP32S2_TIMER
menu "Timer/counter Configuration"
config ESP32S2_ONESHOT
bool "One-shot wrapper"
default n
---help---
Enable a wrapper around the low level timer/counter functions to
support one-shot timer.
endmenu # Timer/counter Configuration
endif # ESP32S2_TIMER
menu "Partition Configuration"
depends on ESP32S2_PARTITION
config ESP32S2_PARTITION_OFFSET
hex "Partition offset"
default "0x8000"
config ESP32S2_PARTITION_MOUNT
string "Partition mount point"
default "/dev/esp/partition/"
endmenu # ESP32S2_PARTITION
menu "AES accelerate"
depends on ESP32S2_AES_ACCELERATOR
config ESP32S2_AES_ACCELERATOR_TEST
bool "AES driver test"
default n
endmenu # ESP32S2_AES_ACCELERATOR
endif # ARCH_CHIP_ESP32S2

87
arch/xtensa/src/esp32s2/Make.defs Normal file

@ -0,0 +1,87 @@
############################################################################
# arch/xtensa/src/esp32s2/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# The start-up, "head", file. May be either a .S or a .c file.
HEAD_ASRC = xtensa_vectors.S xtensa_window_vector.S xtensa_windowspill.S
HEAD_ASRC += xtensa_int_handlers.S xtensa_user_handler.S
HEAD_CSRC = esp32s2_start.c
# Common XTENSA files (arch/xtensa/src/common)
CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S xtensa_panic.S
CMN_ASRCS += xtensa_sigtramp.S
CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c
CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c
CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c
CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c
CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c
CMN_CSRCS += xtensa_puts.c xtensa_releasepending.c xtensa_releasestack.c
CMN_CSRCS += xtensa_reprioritizertr.c xtensa_schedsigaction.c
CMN_CSRCS += xtensa_sigdeliver.c xtensa_stackframe.c xtensa_udelay.c
CMN_CSRCS += xtensa_unblocktask.c xtensa_usestack.c
CMN_CSRCS += esp32s2_systemreset.c
# Configuration-dependent common XTENSA files
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += esp32s2_idle.c
endif
ifeq ($(CONFIG_DEBUG_ALERT),y)
CMN_CSRCS += xtensa_dumpstate.c
endif
ifeq ($(CONFIG_XTENSA_DUMPBT_ON_ASSERT),y)
CMN_ASRCS += xtensa_backtrace.S
endif
ifeq ($(CONFIG_SPINLOCK),y)
CMN_CSRCS += xtensa_testset.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += xtensa_checkstack.c
endif
ifeq ($(CONFIG_FS_HOSTFS),y)
CMN_ASRCS += xtensa_simcall.S
CMN_CSRCS += xtensa_hostfs.c
endif
# Required ESP32S2 files (arch/xtensa/src/lx7)
CHIP_CSRCS = esp32s2_allocateheap.c esp32s2_clockconfig.c esp32s2_cpuint.c
CHIP_CSRCS += esp32s2_gpio.c esp32s2_intdecode.c esp32s2_irq.c esp32s2_region.c
CHIP_CSRCS += esp32s2_timerisr.c esp32s2_user.c esp32s2_rtc.c
CHIP_CSRCS += esp32s2_lowputc.c
# Configuration-dependent ESP32S2 files
ifeq ($(CONFIG_ESP32S2_UART),y)
CMN_CSRCS += esp32s2_serial.c
endif
ifeq ($(CONFIG_ARCH_USE_MODULE_TEXT),y)
CHIP_CSRCS += esp32s2_modtext.c
CMN_ASRCS += xtensa_loadstore.S
endif

107
arch/xtensa/src/esp32s2/chip_macros.h Normal file

@ -0,0 +1,107 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/chip_macros.h
*
* Adapted from use in NuttX by:
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Derives from logic originally provided by Cadence Design Systems Inc.
*
* Copyright (c) 2006-2015 Cadence Design Systems Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_CHIP_MACROS_H
#define __ARCH_XTENSA_SRC_ESP32S2_CHIP_MACROS_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* This is the name of the section containing the Xtensa low level handlers
* that is used by the board linker scripts.
*/
#define HANDLER_SECTION .iram1
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef __ASSEMBLY__
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Assembly Language Macros
****************************************************************************/
#ifdef __ASSEMBLY__
/* Macro to get the current core ID. Only uses the reg given as an argument.
* Reading PRID on the ESP108 architecture gives us 0xcdcd on the PRO
* processor and 0xabab on the APP CPU. We distinguish between the two by
* simply checking bit 1: it's 1 on the APP and 0 on the PRO processor.
*/
.macro getcoreid reg
rsr.prid \reg
bbci \reg, 1, 1f
movi \reg, 1
j 2f
1:
movi \reg, 0
2:
.endm
#endif /* __ASSEMBLY */
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_CHIP_MACROS_H */

68
arch/xtensa/src/esp32s2/chip_memory.h Normal file

@ -0,0 +1,68 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/chip_memory.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_CHIP_MEMORY_H
#define __ARCH_XTENSA_SRC_ESP32S2_CHIP_MEMORY_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "hardware/esp32s2_soc.h"
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: xtensa_sp_sane
****************************************************************************/
static inline bool xtensa_sp_sane(uint32_t sp)
{
return (esp32s2_sp_dram(sp) && ((sp & 0x0f) == 0));
}
/****************************************************************************
* Name: xtensa_ptr_extram
****************************************************************************/
static inline bool xtensa_ptr_exec(const void *p)
{
return esp32s2_ptr_exec(p);
}
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_CHIP_MEMORY_H */

83
arch/xtensa/src/esp32s2/esp32s2_allocateheap.c Normal file

@ -0,0 +1,83 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_allocateheap.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/mm/mm.h>
#include <nuttx/board.h>
#include <arch/board/board.h>
#include <arch/esp32s2/memory_layout.h>
#include "xtensa.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
* size of the unprotected, user-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated (and protected) by an analogous up_allocate_kheap().
*
****************************************************************************/
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)&_sheap;
DEBUGASSERT(HEAP_REGION1_END > (uintptr_t)*heap_start);
*heap_size = (size_t)(HEAP_REGION1_END - (uintptr_t)*heap_start);
}
/****************************************************************************
* Name: xtensa_add_region
*
* Description:
* Memory may be added in non-contiguous chunks. Additional chunks are
* added by calling this function.
*
****************************************************************************/
#if CONFIG_MM_REGIONS > 1
void xtensa_add_region(void)
{
}
#endif

325
arch/xtensa/src/esp32s2/esp32s2_clockconfig.c Normal file

@ -0,0 +1,325 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_clockconfig.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "hardware/esp32s2_soc.h"
#include "hardware/esp32s2_uart.h"
#include "hardware/esp32s2_rtccntl.h"
#include "hardware/esp32s2_system.h"
#include "esp32s2_rtc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef MIN
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef CONFIG_ESP_CONSOLE_UART_NUM
#define CONFIG_ESP_CONSOLE_UART_NUM 0
#endif
#define DEFAULT_CPU_FREQ 80
/****************************************************************************
* Private Types
****************************************************************************/
enum cpu_freq_e
{
CPU_80M = 0,
CPU_160M = 1,
CPU_240M = 2,
};
enum cpu_clksrc_e
{
XTAL_CLK,
PLL_CLK,
RTC8M_CLK,
APLL_CLK
};
enum pll_freq_e
{
PLL_320,
PLL_480
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_cpuclksrc
*
* Description:
* Select a clock source for CPU clock.
*
* Input Parameters:
* src - Any source from cpu_clksrc_e.
*
* Returned Value:
* None
*
****************************************************************************/
static inline void esp32s2_cpuclksrc(enum cpu_clksrc_e src)
{
uint32_t value;
value = VALUE_TO_FIELD(src, SYSTEM_SOC_CLK_SEL);
modifyreg32(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL_M, value);
}
/****************************************************************************
* Name: esp32s2_cpudiv
*
* Description:
* Select a divider for the CPU clk.
* NOTE: The divider is not necessarily the real divisor. See TRM for the
* equivalences.
*
* Input Parameters:
* divider - A value between 0 to 2.
*
* Returned Value:
* None
*
****************************************************************************/
static inline void esp32s2_cpudiv(uint8_t divider)
{
uint32_t value;
value = VALUE_TO_FIELD(divider, SYSTEM_CPUPERIOD_SEL);
modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL_M, value);
}
/****************************************************************************
* Name: esp32s2_pllfreqsel
*
* Description:
* Select the PLL frequency.
*
* Input Parameters:
* freq - Any clock from enum pll_freq_e
*
* Returned Value:
* None
****************************************************************************/
static inline void esp32s2_pllfreqsel(enum pll_freq_e freq)
{
uint32_t value;
value = VALUE_TO_FIELD(freq, SYSTEM_PLL_FREQ_SEL);
modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL_M, value);
}
/****************************************************************************
* Name: esp32s2_uart_tx_wait_idle
*
* Description:
* Wait until uart tx full empty and the last char send ok.
*
* Input Parameters:
* uart_no - 0 for UART0, 1 for UART1, 2 for UART2
*
* Returned Value:
* None
*
****************************************************************************/
static inline void esp32s2_uart_tx_wait_idle(uint8_t uart_no)
{
uint32_t status;
do
{
status = getreg32(UART_STATUS_REG(uart_no));
/* tx count is non-zero */
}
while ((status & UART_TXFIFO_CNT_M) != 0);
}
/****************************************************************************
* Public Functions
****************************************************************************/
extern uint32_t g_ticks_per_us;
/****************************************************************************
* Name: esp32s2_update_cpu_freq
*
* Description:
* Set the real CPU ticks per us to the ets, so that ets_delay_us
* will be accurate. Call this function when CPU frequency is changed.
*
* Input Parameters:
* ticks_per_us - CPU ticks per us
*
* Returned Value:
* None
*
****************************************************************************/
void IRAM_ATTR esp32s2_update_cpu_freq(uint32_t ticks_per_us)
{
/* Update scale factors used by esp_rom_delay_us */
g_ticks_per_us = ticks_per_us;
}
/****************************************************************************
* Name: esp32s2_set_cpu_freq
*
* Description:
* Switch to one of PLL-based frequencies.
*
* Input Parameters:
* cpu_freq_mhz - Target CPU frequency
*
* Returned Value:
* None
*
****************************************************************************/
void IRAM_ATTR esp32s2_set_cpu_freq(int cpu_freq_mhz)
{
uint32_t dbias;
uint32_t value;
switch (cpu_freq_mhz)
{
case 80:
/* 80 MHz is obtained from the 480 MHz PLL.
* In this case CPU_CLK = PLL_CLK / 6. Config the PLL as 480 MHz
* with a 6 divider and set the source clock as PLL_CLK.
*/
dbias = DIG_DBIAS_80M_160M;
esp32s2_cpudiv(0);
break;
case 160:
/* 160 MHz is obtained from the 480 MHz PLL.
* In this case CPU_CLK = PLL_CLK / 3. Config the PLL as 480 MHz
* with a 3 divider and set the source clock as PLL_CLK.
*/
dbias = DIG_DBIAS_80M_160M;
esp32s2_cpudiv(1);
break;
case 240:
/* 160 MHz is obtained from the 480 MHz PLL.
* In this case CPU_CLK = PLL_CLK / 2. Config the PLL as 480 MHz
* with a 2 divider and set the source clock as PLL_CLK.
*/
dbias = DIG_DBIAS_240M;
esp32s2_cpudiv(2);
break;
default:
/* Unsupported clock config. */
return;
}
value = (((80 * MHZ) >> 12) & UINT16_MAX) |
((((80 * MHZ) >> 12) & UINT16_MAX) << 16);
esp32s2_pllfreqsel(PLL_480);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
esp32s2_cpuclksrc(PLL_CLK);
putreg32(value, RTC_APB_FREQ_REG);
esp32s2_update_cpu_freq(cpu_freq_mhz);
}
/****************************************************************************
* Name: esp32s2_clockconfig
*
* Description:
* Called to initialize the ESP32S2. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void esp32s2_clockconfig(void)
{
/* Wait for the TX FIFO to unload data */
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
esp32s2_uart_tx_wait_idle(0);
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
esp32s2_uart_tx_wait_idle(1);
#endif
/* Configure the CPU frequency */
esp32s2_set_cpu_freq(CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ);
}
/****************************************************************************
* Name: esp_clk_cpu_freq
*
* Description:
* Get CPU frequency
*
* Input Parameters:
* None
*
* Returned Value:
* CPU frequency
*
****************************************************************************/
int IRAM_ATTR esp_clk_cpu_freq(void)
{
return g_ticks_per_us * MHZ;
}
/****************************************************************************
* Name: esp_clk_apb_freq
*
* Description:
* Return current APB clock frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* APB clock frequency, in Hz
*
****************************************************************************/
int IRAM_ATTR esp_clk_apb_freq(void)
{
return MIN(g_ticks_per_us, 80) * MHZ;
}

112
arch/xtensa/src/esp32s2/esp32s2_clockconfig.h Normal file

@ -0,0 +1,112 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_clockconfig.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s2_update_cpu_freq
*
* Description:
* Set the real CPU ticks per us to the ets, so that ets_delay_us
* will be accurate. Call this function when CPU frequency is changed.
*
* Input Parameters:
* ticks_per_us - CPU ticks per us
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_update_cpu_freq(uint32_t ticks_per_us);
/****************************************************************************
* Name: esp32s2_set_cpu_freq
*
* Description:
* Switch to one of PLL-based frequencies.
* Current frequency can be XTAL or PLL.
*
* Input Parameters:
* cpu_freq_mhz - new CPU frequency
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_set_cpu_freq(int cpu_freq_mhz);
/****************************************************************************
* Name: esp32s2_clockconfig
*
* Description:
* Called to initialize the ESP32S2. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void esp32s2_clockconfig(void);
/****************************************************************************
* Name: esp_clk_cpu_freq
*
* Description:
* Get CPU frequency
*
* Input Parameters:
* None
*
* Returned Value:
* CPU frequency
*
****************************************************************************/
int esp_clk_cpu_freq(void);
/****************************************************************************
* Name: esp_clk_apb_freq
*
* Description:
* Return current APB clock frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* APB clock frequency, in Hz
*
****************************************************************************/
int esp_clk_apb_freq(void);
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H */

84
arch/xtensa/src/esp32s2/esp32s2_config.h Normal file

@ -0,0 +1,84 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_config.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CONFIG_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/chip/chip.h>
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* UARTs ********************************************************************/
/* Are any UARTs enabled? */
#undef HAVE_UART_DEVICE
#ifdef CONFIG_ESP32S2_UART
# define HAVE_UART_DEVICE 1
#endif
/* Serial Console ***********************************************************/
/* Is there a serial console? There should be no more than one defined. It
* could be on any UARTn. n E {0,1}
*/
#undef HAVE_SERIAL_CONSOLE
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESP32S2_UART0)
# undef CONFIG_UART1_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESP32S2_UART1)
# undef CONFIG_UART0_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#else
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
#endif
/* SPI **********************************************************************/
/* Don't enable SPI peripherals not supported by the chip. */
#if ESP32S2_NSPI < 1
# undef CONFIG_ESP32S2_SPI0
# undef CONFIG_ESP32S2_SPI1
# undef CONFIG_ESP32S2_SPI2
# undef CONFIG_ESP32S2_SPI3
#elif ESP32S2_NSPI < 2
# undef CONFIG_ESP32S2_SPI1
# undef CONFIG_ESP32S2_SPI2
# undef CONFIG_ESP32S2_SPI3
#elif ESP32S2_NSPI < 3
# undef CONFIG_ESP32S2_SPI2
# undef CONFIG_ESP32S2_SPI3
#elif ESP32S2_NSPI < 4
# undef CONFIG_ESP32S2_SPI3
#endif
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CONFIG_H */

587
arch/xtensa/src/esp32s2/esp32s2_cpuint.c Normal file

@ -0,0 +1,587 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_cpuint.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <string.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <arch/irq.h>
#include "esp32s2_cpuint.h"
#include "hardware/esp32s2_interrupt.h"
#include "xtensa.h"
#include "sched/sched.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Mapping Peripheral IDs to map register addresses
*
* PERIPHERAL ID INTERRUPT_PRO_X_MAP
* MNEMONIC REGISTER OFFSET
* ESP32S2_PERIPH_MAC_INTR 0x0000
* ESP32S2_PERIPH_MAC_NMI 0x0004
* ESP32S2_PERIPH_PWR_INTR 0x0008
* ESP32S2_PERIPH_BB_INT 0x000C
* ESP32S2_PERIPH_BT_MAC_INT 0x0010
* ESP32S2_PERIPH_BT_BB_INT 0x0014
* ESP32S2_PERIPH_BT_BB_NMI 0x0018
* ESP32S2_PERIPH_RWBT_IRQ 0x001C
* ESP32S2_PERIPH_RWBLE_IRQ 0x0020
* ESP32S2_PERIPH_RWBT_NMI 0x0024
* ESP32S2_PERIPH_RWBLE_NMI 0x0028
* ESP32S2_PERIPH_SLC0_INTR 0x002C
* ESP32S2_PERIPH_SLC1_INTR 0x0030
* ESP32S2_PERIPH_UHCI0_INTR 0x0034
* ESP32S2_PERIPH_UHCI1_INTR 0x0038
* ESP32S2_PERIPH_TG_T0_LEVEL_INT 0x003C
* ESP32S2_PERIPH_TG_T1_LEVEL_INT 0x0040
* ESP32S2_PERIPH_TG_WDT_LEVEL_INT 0x0044
* ESP32S2_PERIPH_TG_LACT_LEVEL_INT 0x0048
* ESP32S2_PERIPH_TG1_T0_LEVEL_INT 0x004C
* ESP32S2_PERIPH_TG1_T1_LEVEL_INT 0x0050
* ESP32S2_PERIPH_TG1_WDT_LEVEL_INT 0x0054
* ESP32S2_PERIPH_TG1_LACT_LEVEL_INT 0x0058
* ESP32S2_PERIPH_GPIO_INTERRUPT_PRO 0x005C
* ESP32S2_PERIPH_GPIO_INTERRUPT_PRO_NMI 0x0060
* ESP32S2_PERIPH_GPIO_INTERRUPT_APP 0x0064
* ESP32S2_PERIPH_GPIO_INTERRUPT_APP_NMI 0x0068
* ESP32S2_PERIPH_DEDICATED_GPIO_IN_INTR 0x006C
* ESP32S2_PERIPH_CPU_INTR_FROM_CPU_0 0x0070
* ESP32S2_PERIPH_CPU_INTR_FROM_CPU_1 0x0074
* ESP32S2_PERIPH_CPU_INTR_FROM_CPU_2 0x0078
* ESP32S2_PERIPH_CPU_INTR_FROM_CPU_3 0x007C
* ESP32S2_PERIPH_SPI_INTR_1 0x0080
* ESP32S2_PERIPH_SPI_INTR_2 0x0084
* ESP32S2_PERIPH_SPI_INTR_3 0x0088
* ESP32S2_PERIPH_I2S0_INT 0x008C
* ESP32S2_PERIPH_I2S1_INT 0x0090
* ESP32S2_PERIPH_UART_INT 0x0094
* ESP32S2_PERIPH_UART1_INT 0x0098
* ESP32S2_PERIPH_UART2_INT 0x009C
* ESP32S2_PERIPH_SDIO_HOST_INTERRUPT 0x00A0
* ESP32S2_PERIPH_PWM0_INTR 0x00A4
* ESP32S2_PERIPH_PWM1_INTR 0x00A8
* ESP32S2_PERIPH_PWM2_INTR 0x00AC
* ESP32S2_PERIPH_PWM3_INTR 0x00B0
* ESP32S2_PERIPH_LEDC_INTR 0x00B4
* ESP32S2_PERIPH_EFUSE_INT 0x00B8
* ESP32S2_PERIPH_CAN_INT 0x00BC
* ESP32S2_PERIPH_USB_INT 0x00C0
* ESP32S2_PERIPH_RTC_CORE_INTR 0x00C4
* ESP32S2_PERIPH_RMT_INTR 0x00C8
* ESP32S2_PERIPH_PCNT_INTR 0x00CC
* ESP32S2_PERIPH_I2C_EXT0_INTR 0x00D0
* ESP32S2_PERIPH_I2C_EXT1_INTR 0x00D4
* ESP32S2_PERIPH_RSA_INTR 0x00D8
* ESP32S2_PERIPH_SHA_INTR 0x00DC
* ESP32S2_PERIPH_AES_INTR 0x00E0
* ESP32S2_PERIPH_SPI2_DMA_INT 0x00E4
* ESP32S2_PERIPH_SPI3_DMA_INT 0x00E8
* ESP32S2_PERIPH_WDG_INT 0x00EC
* ESP32S2_PERIPH_TIMER_INT1 0x00F0
* ESP32S2_PERIPH_TIMER_INT2 0x00F4
* ESP32S2_PERIPH_TG_T0_EDGE_INT 0x00F8
* ESP32S2_PERIPH_TG_T1_EDGE_INT 0x00FC
* ESP32S2_PERIPH_TG_WDT_EDGE_INT 0x0100
* ESP32S2_PERIPH_TG_LACT_EDGE_INT 0x0104
* ESP32S2_PERIPH_TG1_T0_EDGE_INT 0x0108
* ESP32S2_PERIPH_TG1_T1_EDGE_INT 0x010C
* ESP32S2_PERIPH_TG1_WDT_EDGE_INT 0x0110
* ESP32S2_PERIPH_TG1_LACT_EDGE_INT 0x0114
* ESP32S2_PERIPH_CACHE_IA_INT 0x0118
* ESP32S2_PERIPH_SYSTIMER_TARGET0_INT 0x011C
* ESP32S2_PERIPH_SYSTIMER_TARGET1_INT 0x0120
* ESP32S2_PERIPH_SYSTIMER_TARGET2 0x0124
* ESP32S2_PERIPH_ASSIST_DEBUG_INTR 0x0128
* ESP32S2_PERIPH_PMS_PRO_IRAM0_ILG 0x012C
* ESP32S2_PERIPH_PMS_PRO_DRAM0_ILG 0x0130
* ESP32S2_PERIPH_PMS_PRO_DPORT_ILG 0x0134
* ESP32S2_PERIPH_PMS_PRO_AHB_ILG 0x0138
* ESP32S2_PERIPH_PMS_PRO_CACHE_ILG 0x013C
* ESP32S2_PERIPH_PMS_DMA_APB_I_ILG 0x0140
* ESP32S2_PERIPH_PMS_DMA_RX_I_ILG 0x0144
* ESP32S2_PERIPH_PMS_DMA_TX_I_ILG 0x0148
* ESP32S2_PERIPH_SPI_MEM_REJECT_INTR 0x014C
* ESP32S2_PERIPH_DMA_COPY_INTR 0x0150
* ESP32S2_PERIPH_SPI4_DMA_INT 0x0154
* ESP32S2_PERIPH_SPI_INTR_4 0x0158
* ESP32S2_PERIPH_DCACHE_PRELOAD_INT 0x015C
* ESP32S2_PERIPH_ICACHE_PRELOAD_INT 0x0160
* ESP32S2_PERIPH_APB_ADC_INT 0x0164
* ESP32S2_PERIPH_CRYPTO_DMA_INT 0x0168
* ESP32S2_PERIPH_CPU_PERI_ERROR_INT 0x016C
* ESP32S2_PERIPH_APB_PERI_ERROR_INT 0x0170
* ESP32S2_PERIPH_DCACHE_SYNC_INT 0x0174
* ESP32S2_PERIPH_ICACHE_SYNC_INT 0x0178
* ESP32S2_PERIPH_NMI 0x0188
*/
#define INTERRUPT_PRO_X_MAP_REG(n) (DR_REG_INTERRUPT_BASE + ((n) << 2))
/* CPU interrupts can be detached from any peripheral source by setting the
* map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29).
*/
#define NO_CPUINT ESP32S2_CPUINT_TIMER0
/* Priority range is 1-5 */
#define ESP32S2_MIN_PRIORITY 1
#define ESP32S2_MAX_PRIORITY 5
#define ESP32S2_PRIO_INDEX(p) ((p) - ESP32S2_MIN_PRIORITY)
#ifdef CONFIG_ESP32S2_WIRELESS
# define ESP32S2_WIRELESS_RESERVE_INT (1 << ESP32S2_CPUINT_MAC)
#else
# define ESP32S2_WIRELESS_RESERVE_INT 0
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
uint8_t g_cpu0_intmap[ESP32S2_NCPUINTS];
/****************************************************************************
* Private Data
****************************************************************************/
/* g_intenable[] is a shadow copy of the CPU INTENABLE register
* content.
*/
static uint32_t g_intenable[1];
/* Bitsets for free, unallocated CPU interrupts available to peripheral
* devices.
*/
static uint32_t g_cpu0_freeints = ESP32_CPUINT_PERIPHSET &
(~ESP32S2_WIRELESS_RESERVE_INT);
/* Bitsets for each interrupt priority 1-5 */
static const uint32_t g_priority[5] =
{
ESP32S2_INTPRI1_MASK,
ESP32S2_INTPRI2_MASK,
ESP32S2_INTPRI3_MASK,
ESP32S2_INTPRI4_MASK,
ESP32S2_INTPRI5_MASK
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: xtensa_disable_all
*
* Description:
* Disable all CPU interrupts.
****************************************************************************/
static inline void xtensa_disable_all(void)
{
__asm__ __volatile__
(
"movi a2, 0\n"
"xsr a2, INTENABLE\n"
: : : "a2"
);
}
/****************************************************************************
* Name: esp32s2_alloc_cpuint
*
* Description:
* Allocate a CPU interrupt for a peripheral device. This function will
* not allocate any of the pre-allocated CPU interrupts for internal
* devices. This current implementation is not supporting multiple
* peripheral interrupts maped to a single CPU interrupt.
*
* Input Parameters:
* intmask - Mask of candidate CPU interrupts. The CPU interrupt will be
* be allocated from free interrupts within this set.
*
* Returned Value:
* On success, the first available CPU interrupt accordingly to the passed
* intmask. If no one is available return -ENOMEM.
*
****************************************************************************/
static int esp32s2_alloc_cpuint(uint32_t intmask)
{
irqstate_t flags;
uint32_t *freeints;
uint32_t bitmask;
uint32_t intset;
int cpuint;
int ret = -ENOMEM;
/* Check if there are CPU interrupts with the requested properties
* available.
*/
flags = enter_critical_section();
freeints = &g_cpu0_freeints;
intset = *freeints & intmask;
if (intset != 0)
{
/* Skip over initial unavailable CPU interrupts quickly in groups
* of 8 interrupt until find the first slot with the required
* CPU interrupt set.
*/
for (cpuint = 0, bitmask = 0xff;
cpuint <= ESP32S2_CPUINT_MAX && (intset & bitmask) == 0;
cpuint += 8, bitmask <<= 8);
/* Search for an unallocated CPU interrupt number in the remaining
* intset.
*/
for (; cpuint <= ESP32S2_CPUINT_MAX; cpuint++)
{
/* If the bit corresponding to the CPU interrupt is '1', then
* that CPU interrupt is available.
*/
bitmask = (1ul << cpuint);
if ((intset & bitmask) != 0)
{
/* Got it!
* Update the available CPU interrupts mask
* and return the cpuint.
*/
*freeints &= ~bitmask;
ret = cpuint;
break;
}
}
}
leave_critical_section(flags);
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_cpuint_initialize
*
* Description:
* Initialize CPU interrupts.
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned on
* any failure.
*
****************************************************************************/
int esp32s2_cpuint_initialize(void)
{
uintptr_t regaddr;
uint8_t *intmap;
int i;
/* Disable all CPU interrupts on this CPU */
xtensa_disable_all();
/* Detach all peripheral sources PRO CPU interrupts */
for (i = 0; i < ESP32S2_NPERIPHERALS; i++)
{
regaddr = INTERRUPT_PRO_X_MAP_REG(i);
putreg32(NO_CPUINT, regaddr);
}
/* Initialize CPU interrupt-to-IRQ mapping table */
intmap = g_cpu0_intmap;
/* Indicate that no peripheral interrupts are assigned to CPU interrupts */
memset(intmap, CPUINT_UNASSIGNED, ESP32S2_NCPUINTS);
/* Special case the 6 internal interrupts.
*
* CPU interrupt bit IRQ number
* --------------------------- ---------------------
* ESP32S2_CPUINT_MAC 0 ESP32S2_IRQ_MAC 4
* ESP32S2_CPUINT_TIMER0 6 XTENSA_IRQ_TIMER0 0
* ESP32S2_CPUINT_SOFTWARE0 7 Not yet defined
* ESP32S2_CPUINT_PROFILING 11 Not yet defined
* ESP32S2_CPUINT_TIMER1 15 XTENSA_IRQ_TIMER1 1
* ESP32S2_CPUINT_TIMER2 16 XTENSA_IRQ_TIMER2 2
* ESP32S2_CPUINT_SOFTWARE1 29 Not yet defined
*/
intmap[ESP32S2_CPUINT_TIMER0] = XTENSA_IRQ_TIMER0;
intmap[ESP32S2_CPUINT_TIMER1] = XTENSA_IRQ_TIMER1;
intmap[ESP32S2_CPUINT_TIMER2] = XTENSA_IRQ_TIMER2;
/* Reserve CPU interrupt for some special drivers */
#ifdef CONFIG_ESP32S2_WIRELESS
intmap[ESP32S2_CPUINT_MAC] = ESP32S2_IRQ_MAC;
#endif
return OK;
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the CPU interrupt specified by 'cpuint'.
*
* Input Parameters:
* cpuint - The CPU interrupt to disable.
*
****************************************************************************/
void up_disable_irq(int cpuint)
{
DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX);
xtensa_disable_cpuint(&g_intenable[0], (1ul << cpuint));
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the CPU interrupt specified by 'cpuint'.
*
* Input Parameters:
* cpuint - The CPU interrupt to disable.
*
****************************************************************************/
void up_enable_irq(int cpuint)
{
DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX);
xtensa_enable_cpuint(&g_intenable[0], (1ul << cpuint));
}
/****************************************************************************
* Name: esp32s2_alloc_levelint
*
* Description:
* Allocate a level CPU interrupt
*
* Input Parameters:
* priority - Priority of the CPU interrupt (1-5)
*
* Returned Value:
* On success, the allocated level-sensitive, CPU interrupt number is
* returned. A negated errno is returned on failure. The only possible
* failure is that all level-sensitive CPU interrupts have already been
* allocated.
*
****************************************************************************/
int esp32s2_alloc_levelint(int priority)
{
uint32_t intmask;
DEBUGASSERT(priority >= ESP32S2_MIN_PRIORITY &&
priority <= ESP32S2_MAX_PRIORITY);
/* Check if there are any level CPU interrupts available at the requested
* interrupt priority.
*/
intmask = g_priority[ESP32S2_PRIO_INDEX(priority)] & EPS32_CPUINT_LEVELSET;
return esp32s2_alloc_cpuint(intmask);
}
/****************************************************************************
* Name: esp32s2_alloc_edgeint
*
* Description:
* Allocate an edge CPU interrupt
*
* Input Parameters:
* priority - Priority of the CPU interrupt (1-5)
*
* Returned Value:
* On success, the allocated edge-sensitive, CPU interrupt number is
* returned. A negated errno is returned on failure. The only possible
* failure is that all edge-sensitive CPU interrupts have already been
* allocated.
*
****************************************************************************/
int esp32s2_alloc_edgeint(int priority)
{
uint32_t intmask;
DEBUGASSERT(priority >= ESP32S2_MIN_PRIORITY &&
priority <= ESP32S2_MAX_PRIORITY);
/* Check if there are any edge CPU interrupts available at the requested
* interrupt priority.
*/
intmask = g_priority[ESP32S2_PRIO_INDEX(priority)] & EPS32_CPUINT_EDGESET;
return esp32s2_alloc_cpuint(intmask);
}
/****************************************************************************
* Name: esp32s2_free_cpuint
*
* Description:
* Free a previously allocated CPU interrupt by making it available in the
* g_cpu0_freeints.
*
* Input Parameters:
* cpuint - The CPU interrupt number to be freed.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_free_cpuint(int cpuint)
{
irqstate_t flags;
uint32_t *freeints;
uint32_t bitmask;
DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX);
/* Mark the CPU interrupt as available */
bitmask = (1ul << cpuint);
flags = enter_critical_section();
freeints = &g_cpu0_freeints;
DEBUGASSERT((*freeints & bitmask) == 0);
*freeints |= bitmask;
leave_critical_section(flags);
}
/****************************************************************************
* Name: esp32s2_attach_peripheral
*
* Description:
* Attach a peripheral interrupt to a CPU interrupt.
* This function may be called after esp32s2_alloc_edgeint or
* esp32s2_alloc_levelint
*
* Input Parameters:
* periphid - The peripheral number from irq.h to be assigned to
* a CPU interrupt.
* cpuint - The CPU interrupt to receive the peripheral interrupt
* assignment. This value is returned by
* esp32s2_alloc_edgeint or esp32s2_alloc_levelint.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_attach_peripheral(int periphid, int cpuint)
{
uintptr_t regaddr;
/* Get the map for CPU interrupts and IRQs */
uint8_t *intmap = g_cpu0_intmap;
DEBUGASSERT(periphid >= 0 && periphid < ESP32S2_NPERIPHERALS);
DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX);
DEBUGASSERT(intmap[cpuint] == CPUINT_UNASSIGNED);
/* Get the INTERRUPT_PRO_X_MAP_REG for that specific peripheral.
* X stands for the peripheral source.
* Fill the interruption map with the IRQ for the new CPU interrupt.
* Allocate one peripheral interrupt to the CPU interrupt.
*/
regaddr = INTERRUPT_PRO_X_MAP_REG(periphid);
intmap[cpuint] = periphid + XTENSA_IRQ_FIRSTPERI;
putreg32(cpuint, regaddr);
}
/****************************************************************************
* Name: esp32s2_detach_peripheral
*
* Description:
* Detach a peripheral interrupt from a CPU interrupt.
*
* Input Parameters:
* periphid - The peripheral number from irq.h to be detached from the
* CPU interrupt.
* cpuint - The CPU interrupt from which the peripheral interrupt will
* be detached.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_detach_peripheral(int periphid, int cpuint)
{
uintptr_t regaddr;
uint8_t *intmap = g_cpu0_intmap;
DEBUGASSERT(periphid >= 0 && periphid < ESP32S2_NPERIPHERALS);
DEBUGASSERT(intmap[cpuint] != CPUINT_UNASSIGNED);
/* Get the INTERRUPT_PRO_X_MAP_REG for that specific peripheral.
* X stands for the peripheral source.
* Unassign the IRQ from the CPU interrupt.
* Deallocate the peripheral interrupt from the CPU interrupt.
*/
regaddr = INTERRUPT_PRO_X_MAP_REG(periphid);
intmap[cpuint] = CPUINT_UNASSIGNED;
putreg32(NO_CPUINT, regaddr);
}

169
arch/xtensa/src/esp32s2/esp32s2_cpuint.h Normal file

@ -0,0 +1,169 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_cpuint.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CPUINT_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CPUINT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/irq.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* No peripheral assigned to this CPU interrupt */
#define CPUINT_UNASSIGNED 0xff
/* A low priority definition to be used by drivers */
#define ESP32S2_INT_PRIO_DEF 1
/****************************************************************************
* Public Data
****************************************************************************/
/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
extern uint8_t g_cpu0_intmap[ESP32S2_NCPUINTS];
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s2_cpuint_initialize
*
* Description:
* Initialize CPU interrupts.
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned on
* any failure.
*
****************************************************************************/
int esp32s2_cpuint_initialize(void);
/****************************************************************************
* Name: esp32s2_alloc_levelint
*
* Description:
* Allocate a level CPU interrupt
*
* Input Parameters:
* priority - Priority of the CPU interrupt (1-5)
*
* Returned Value:
* On success, the allocated level-sensitive, CPU interrupt number is
* returned. A negated errno is returned on failure. The only possible
* failure is that all level-sensitive CPU interrupts have already been
* allocated.
*
****************************************************************************/
int esp32s2_alloc_levelint(int priority);
/****************************************************************************
* Name: esp32s2_alloc_edgeint
*
* Description:
* Allocate an edge CPU interrupt
*
* Input Parameters:
* priority - Priority of the CPU interrupt (1-5)
*
* Returned Value:
* On success, the allocated edge-sensitive, CPU interrupt number is
* returned. A negated errno is returned on failure. The only possible
* failure is that all edge-sensitive CPU interrupts have already been
* allocated.
*
****************************************************************************/
int esp32s2_alloc_edgeint(int priority);
/****************************************************************************
* Name: esp32s2_free_cpuint
*
* Description:
* Free a previously allocated CPU interrupt by making it available in the
* g_cpu0_freeints.
*
* Input Parameters:
* cpuint - The CPU interrupt number to be freed.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_free_cpuint(int cpuint);
/****************************************************************************
* Name: esp32s2_attach_peripheral
*
* Description:
* Attach a peripheral interrupt to a CPU interrupt.
* This function may be called after esp32s2_alloc_edgeint or
* esp32s2_alloc_levelint
*
* Input Parameters:
* periphid - The peripheral number from irq.h to be assigned to
* a CPU interrupt.
* cpuint - The CPU interrupt to receive the peripheral interrupt
* assignment. This value is returned by
* esp32s2_alloc_edgeint or esp32s2_alloc_levelint.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_attach_peripheral(int periphid, int cpuint);
/****************************************************************************
* Name: esp32s2_detach_peripheral
*
* Description:
* Detach a peripheral interrupt from a CPU interrupt.
*
* Input Parameters:
* periphid - The peripheral number from irq.h to be detached from the
* CPU interrupt.
* cpuint - The CPU interrupt from which the peripheral interrupt will
* be detached.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_detach_peripheral(int periphid, int cpuint);
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CPUINT_H */

474
arch/xtensa/src/esp32s2/esp32s2_gpio.c Normal file

@ -0,0 +1,474 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <arch/irq.h>
#include "xtensa.h"
#include "hardware/esp32s2_iomux.h"
#include "hardware/esp32s2_gpio.h"
#include "esp32s2_cpuint.h"
#include "esp32s2_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define NGPIO_HPINS (ESP32S2_NIRQ_GPIO - 32)
#define NGPIO_HMASK ((1ul << NGPIO_HPINS) - 1)
#define _NA_ 0xff
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
static int g_gpio_cpuint;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: gpio_dispatch
*
* Description:
* Second level dispatch for GPIO interrupt handling.
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs)
{
uint32_t mask;
int i;
/* Check each bit in the status register */
for (i = 0; i < 32 && status != 0; i++)
{
/* Check if there is an interrupt pending for this pin */
mask = (1ul << i);
if ((status & mask) != 0)
{
/* Yes... perform the second level dispatch */
irq_dispatch(irq + i, regs);
/* Clear the bit in the status so that we might execute this loop
* sooner.
*/
status &= ~mask;
}
}
}
#endif
/****************************************************************************
* Name: gpio_interrupt
*
* Description:
* GPIO interrupt handler.
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
static int gpio_interrupt(int irq, FAR void *context, FAR void *arg)
{
uint32_t status;
/* Read and clear the lower GPIO interrupt status */
status = getreg32(GPIO_STATUS_REG);
putreg32(status, GPIO_STATUS_W1TC_REG);
/* Dispatch pending interrupts in the lower GPIO status register */
gpio_dispatch(ESP32S2_FIRST_GPIOIRQ, status, (uint32_t *)context);
/* Read and clear the upper GPIO interrupt status */
status = getreg32(GPIO_STATUS1_REG) & NGPIO_HMASK;
putreg32(status, GPIO_STATUS1_W1TC_REG);
/* Dispatch pending interrupts in the lower GPIO status register */
gpio_dispatch(ESP32S2_FIRST_GPIOIRQ + 32, status, (uint32_t *)context);
return OK;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_configgpio
*
* Description:
* Configure a GPIO pin based on encoded pin attributes.
*
****************************************************************************/
int esp32s2_configgpio(int pin, gpio_pinattr_t attr)
{
uintptr_t regaddr;
uint32_t func;
uint32_t cntrl;
uint32_t pin2func;
DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS);
/* Handle input pins */
func = 0;
cntrl = 0;
if ((attr & INPUT) != 0)
{
if (pin < 32)
{
putreg32((1ul << pin), GPIO_ENABLE_W1TC_REG);
}
else
{
putreg32((1ul << (pin - 32)), GPIO_ENABLE1_W1TC_REG);
}
/* Input enable */
func |= FUN_IE;
if ((attr & PULLUP) != 0)
{
func |= FUN_PU;
}
else if (attr & PULLDOWN)
{
func |= FUN_PD;
}
}
/* Handle output pins */
if ((attr & OUTPUT) != 0)
{
if (pin < 32)
{
putreg32((1ul << pin), GPIO_ENABLE_W1TS_REG);
}
else
{
putreg32((1ul << (pin - 32)), GPIO_ENABLE1_W1TS_REG);
}
}
/* Add drivers */
func |= (uint32_t)(2ul << FUN_DRV_S);
/* Select the pad's function. If no function was given, consider it a
* normal input or output (i.e. function3).
*/
if ((attr & FUNCTION_MASK) != 0)
{
func |= (uint32_t)(((attr >> FUNCTION_SHIFT) - 1) << MCU_SEL_S);
}
else
{
func |= (uint32_t)(PIN_FUNC_GPIO << MCU_SEL_S);
}
if ((attr & OPEN_DRAIN) != 0)
{
cntrl |= (1 << GPIO_PIN_PAD_DRIVER_S);
}
pin2func = (pin + 1) * 4;
regaddr = DR_REG_IO_MUX_BASE + pin2func;
putreg32(func, regaddr);
regaddr = GPIO_REG(pin);
putreg32(cntrl, regaddr);
return OK;
}
/****************************************************************************
* Name: esp32s2_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void esp32s2_gpiowrite(int pin, bool value)
{
DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS);
if (value)
{
if (pin < 32)
{
putreg32((uint32_t)(1ul << pin), GPIO_OUT_W1TS_REG);
}
else
{
putreg32((uint32_t)(1ul << (pin - 32)), GPIO_OUT1_W1TS_REG);
}
}
else
{
if (pin < 32)
{
putreg32((uint32_t)(1ul << pin), GPIO_OUT_W1TC_REG);
}
else
{
putreg32((uint32_t)(1ul << (pin - 32)), GPIO_OUT1_W1TC_REG);
}
}
}
/****************************************************************************
* Name: esp32s2_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool esp32s2_gpioread(int pin)
{
uint32_t regval;
DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS);
if (pin < 32)
{
regval = getreg32(GPIO_IN_REG);
return ((regval >> pin) & 1) != 0;
}
else
{
regval = getreg32(GPIO_IN1_REG);
return ((regval >> (pin - 32)) & 1) != 0;
}
}
/****************************************************************************
* Name: esp32s2_gpioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqinitialize(void)
{
/* Allocate a level-sensitive, priority 1 CPU interrupt */
g_gpio_cpuint = esp32s2_alloc_levelint(1);
DEBUGASSERT(g_gpio_cpuint >= 0);
/* Attach the GPIO peripheral to the allocated CPU interrupt */
up_disable_irq(g_gpio_cpuint);
esp32s2_attach_peripheral(ESP32S2_PERI_GPIO_INT_PRO, g_gpio_cpuint);
/* Attach and enable the interrupt handler */
DEBUGVERIFY(irq_attach(ESP32S2_PERI_GPIO_INT_PRO, gpio_interrupt, NULL));
up_enable_irq(g_gpio_cpuint);
}
#endif
/****************************************************************************
* Name: esp32s2_gpioirqenable
*
* Description:
* Enable the COPY interrupt for specified GPIO IRQ
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqenable(int irq, gpio_intrtype_t intrtype)
{
uintptr_t regaddr;
uint32_t regval;
int pin;
DEBUGASSERT(irq >= ESP32S2_FIRST_GPIOIRQ && irq <= ESP32S2_LAST_GPIOIRQ);
/* Convert the IRQ number to a pin number */
pin = ESP32S2_IRQ2PIN(irq);
/* Get the address of the GPIO PIN register for this pin */
up_disable_irq(g_gpio_cpuint);
regaddr = GPIO_REG(pin);
regval = getreg32(regaddr);
regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M);
/* Set the pin ENA field:
*
* Bit 0: APP CPU interrupt enable
* Bit 1: APP CPU non-maskable interrupt enable
* Bit 3: PRO CPU interrupt enable
* Bit 4: PRO CPU non-maskable interrupt enable
* Bit 5: SDIO's extent interrupt enable.
*/
/* PRO_CPU */
regval |= ((1 << 2) << GPIO_PIN_INT_ENA_S);
regval |= (intrtype << GPIO_PIN_INT_TYPE_S);
putreg32(regval, regaddr);
up_enable_irq(g_gpio_cpuint);
}
#endif
/****************************************************************************
* Name: esp32s2_gpioirqdisable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqdisable(int irq)
{
uintptr_t regaddr;
uint32_t regval;
int pin;
DEBUGASSERT(irq >= ESP32S2_FIRST_GPIOIRQ && irq <= ESP32S2_LAST_GPIOIRQ);
/* Convert the IRQ number to a pin number */
pin = ESP32S2_IRQ2PIN(irq);
/* Get the address of the GPIO PIN register for this pin */
up_disable_irq(g_gpio_cpuint);
regaddr = GPIO_REG(pin);
regval = getreg32(regaddr);
regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M);
putreg32(regval, regaddr);
up_enable_irq(g_gpio_cpuint);
}
#endif
/****************************************************************************
* Name: esp32s2_gpio_matrix_in
*
* Description:
* Set gpio input to a signal
* NOTE: one gpio can input to several signals
* If gpio == 0x30, cancel input to the signal, input 0 to signal
* If gpio == 0x38, cancel input to the signal, input 1 to signal,
* for I2C pad
*
****************************************************************************/
void esp32s2_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv)
{
uint32_t regaddr = GPIO_FUNC0_IN_SEL_CFG_REG + (signal_idx * 4);
uint32_t regval = (gpio << GPIO_FUNC0_IN_SEL_S);
if (inv)
{
regval |= GPIO_FUNC0_IN_INV_SEL;
}
if (gpio != 0x34)
{
regval |= GPIO_SIG0_IN_SEL;
}
putreg32(regval, regaddr);
}
/****************************************************************************
* Name: esp32s2_gpio_matrix_out
*
* Description:
* Set signal output to gpio
* NOTE: one signal can output to several gpios
* If signal_idx == 0x100, cancel output put to the gpio
*
****************************************************************************/
void esp32s2_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
bool out_inv, bool oen_inv)
{
uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio * 4);
uint32_t regval = signal_idx << GPIO_FUNC0_OUT_SEL_S;
if (gpio >= GPIO_PIN_COUNT)
{
return;
}
if (gpio < 32)
{
putreg32((1ul << gpio), GPIO_ENABLE_W1TS_REG);
}
else
{
putreg32((1ul << (gpio - 32)), GPIO_ENABLE1_W1TS_REG);
}
if (out_inv)
{
regval |= GPIO_FUNC0_OUT_INV_SEL;
}
if (oen_inv)
{
regval |= GPIO_FUNC0_OEN_INV_SEL;
}
putreg32(regval, regaddr);
}

235
arch/xtensa/src/esp32s2/esp32s2_gpio.h Normal file

@ -0,0 +1,235 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */
#define MATRIX_DETACH_IN_LOW_PIN 0x30 /* Detach non-inverted INPUT sig */
#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */
/* Bit-encoded input to esp32s2_configgpio() ********************************/
/* Encoded pin attributes used with esp32s2_configgpio()
*
* 8 7 6 5 4 3 2 1 0
* -- -- -- -- -- -- -- -- --
* FN FN FN OD PD PU F O I
*/
#define PINMODE_SHIFT 0
#define PINMODE_MASK (7 << PINMODE_SHIFT)
# define INPUT (1 << 0)
# define OUTPUT (1 << 1)
# define FUNCTION (1 << 2)
#define PULLUP (1 << 3)
#define PULLDOWN (1 << 4)
#define OPEN_DRAIN (1 << 5)
#define FUNCTION_SHIFT 6
#define FUNCTION_MASK (7 << FUNCTION_SHIFT)
# define FUNCTION_1 (1 << FUNCTION_SHIFT)
# define FUNCTION_2 (2 << FUNCTION_SHIFT)
# define FUNCTION_3 (3 << FUNCTION_SHIFT)
# define FUNCTION_4 (4 << FUNCTION_SHIFT)
# define FUNCTION_5 (5 << FUNCTION_SHIFT)
# define FUNCTION_6 (6 << FUNCTION_SHIFT)
#define INPUT_PULLUP (INPUT | PULLUP)
#define INPUT_PULLDOWN (INPUT | PULLDOWN)
#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN)
#define INPUT_FUNCTION (INPUT | FUNCTION)
# define INPUT_FUNCTION_1 (INPUT_FUNCTION | FUNCTION_1)
# define INPUT_FUNCTION_2 (INPUT_FUNCTION | FUNCTION_2)
# define INPUT_FUNCTION_3 (INPUT_FUNCTION | FUNCTION_3)
# define INPUT_FUNCTION_4 (INPUT_FUNCTION | FUNCTION_4)
# define INPUT_FUNCTION_5 (INPUT_FUNCTION | FUNCTION_5)
# define INPUT_FUNCTION_6 (INPUT_FUNCTION | FUNCTION_6)
#define OUTPUT_FUNCTION (OUTPUT | FUNCTION)
# define OUTPUT_FUNCTION_1 (OUTPUT_FUNCTION | FUNCTION_1)
# define OUTPUT_FUNCTION_2 (OUTPUT_FUNCTION | FUNCTION_2)
# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3)
# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4)
# define OUTPUT_FUNCTION_5 (OUTPUT_FUNCTION | FUNCTION_5)
# define OUTPUT_FUNCTION_6 (OUTPUT_FUNCTION | FUNCTION_6)
/* Interrupt type used with esp32s2_gpioirqenable() */
#define DISABLED 0x00
#define RISING 0x01
#define FALLING 0x02
#define CHANGE 0x03
#define ONLOW 0x04
#define ONHIGH 0x05
#define ONLOW_WE 0x0c
#define ONHIGH_WE 0x0d
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/* Must be big enough to hold the above encodings */
typedef uint16_t gpio_pinattr_t;
typedef uint8_t gpio_intrtype_t;
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s2_gpioirqinitialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqinitialize(void);
#else
# define esp32s2_gpioirqinitialize()
#endif
/****************************************************************************
* Name: esp32s2_configgpio
*
* Description:
* Configure a GPIO pin based on encoded pin attributes.
*
****************************************************************************/
int esp32s2_configgpio(int pin, gpio_pinattr_t attr);
/****************************************************************************
* Name: esp32s2_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void esp32s2_gpiowrite(int pin, bool value);
/****************************************************************************
* Name: esp32s2_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool esp32s2_gpioread(int pin);
/****************************************************************************
* Name: esp32s2_gpioirqenable
*
* Description:
* Enable the interrupt for specified GPIO IRQ
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqenable(int irq, gpio_intrtype_t intrtype);
#else
# define esp32s2_gpioirqenable(irq,intrtype)
#endif
/****************************************************************************
* Name: esp32s2_gpioirqdisable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
****************************************************************************/
#ifdef CONFIG_ESP32S2_GPIO_IRQ
void esp32s2_gpioirqdisable(int irq);
#else
# define esp32s2_gpioirqdisable(irq)
#endif
/****************************************************************************
* Name: esp32s2_gpio_matrix_in
*
* Description:
* Set gpio input to a signal
* NOTE: one gpio can input to several signals
* If gpio == 0x30, cancel input to the signal, input 0 to signal
* If gpio == 0x38, cancel input to the signal, input 1 to signal,
* for I2C pad
*
****************************************************************************/
void esp32s2_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/****************************************************************************
* Name: esp32s2_gpio_matrix_out
*
* Description:
* Set signal output to gpio
* NOTE: one signal can output to several gpios
* If signal_idx == 0x100, cancel output put to the gpio
*
****************************************************************************/
void esp32s2_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
bool out_inv, bool oen_inv);
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H */

206
arch/xtensa/src/esp32s2/esp32s2_idle.c Normal file

@ -0,0 +1,206 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_idle.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/power/pm.h>
#include "esp32s2_pm.h"
#include "xtensa.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Values for the RTC Alarm to wake up from the PM_STANDBY mode
* (which corresponds to ESP32S2 stop mode). If this alarm expires,
* the logic in this file will wakeup from PM_STANDBY mode and
* transition to PM_SLEEP mode (ESP32S2 standby mode).
*/
#ifdef CONFIG_PM
#ifndef CONFIG_PM_ALARM_SEC
# define CONFIG_PM_ALARM_SEC 15
#endif
#ifndef CONFIG_PM_ALARM_NSEC
# define CONFIG_PM_ALARM_NSEC 0
#endif
#ifndef CONFIG_PM_SLEEP_WAKEUP_SEC
# define CONFIG_PM_SLEEP_WAKEUP_SEC 20
#endif
#ifndef CONFIG_PM_SLEEP_WAKEUP_NSEC
# define CONFIG_PM_SLEEP_WAKEUP_NSEC 0
#endif
#define PM_IDLE_DOMAIN 0 /* Revisit */
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_idlepm
*
* Description:
* Perform IDLE state power management.
*
****************************************************************************/
#ifdef CONFIG_PM
static void up_idlepm(void)
{
static enum pm_state_e oldstate = PM_NORMAL;
enum pm_state_e newstate;
irqstate_t flags;
int ret;
/* Decide, which power saving level can be obtained */
newstate = pm_checkstate(PM_IDLE_DOMAIN);
/* Check for state changes */
if (newstate != oldstate)
{
flags = spin_lock_irqsave(NULL);
/* Perform board-specific, state-dependent logic here */
_info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
ret = pm_changestate(PM_IDLE_DOMAIN, newstate);
if (ret < 0)
{
/* The new state change failed, revert to the preceding state */
pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
/* Save the new state */
oldstate = newstate;
}
spin_unlock_irqrestore(NULL, flags);
/* MCU-specific power management logic */
switch (newstate)
{
case PM_NORMAL:
break;
case PM_IDLE:
break;
case PM_STANDBY:
{
/* Enter Force-sleep mode */
esp32s2_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 +
CONFIG_PM_ALARM_NSEC / 1000);
}
break;
case PM_SLEEP:
{
/* Enter Deep-sleep mode */
esp32s2_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 +
CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000);
}
break;
default:
break;
}
}
else
{
if (oldstate == PM_NORMAL)
{
/* Relax normal operation */
pm_relax(PM_IDLE_DOMAIN, PM_NORMAL);
}
#ifdef CONFIG_WATCHDOG
/* Announce the power management state change to feed watchdog */
pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL);
#endif
}
}
#else
# define up_idlepm()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when their is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* This would be an appropriate place to put some MCU-specific logic to
* sleep in a reduced power mode until an interrupt occurs to save power
*/
#if XCHAL_HAVE_INTERRUPTS
__asm__ __volatile__ ("waiti 0");
#endif
#endif
}

122
arch/xtensa/src/esp32s2/esp32s2_intdecode.c Normal file

@ -0,0 +1,122 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_intdecode.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include "xtensa.h"
#include "esp32s2_cpuint.h"
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: xtensa_intclear
****************************************************************************/
static inline void xtensa_intclear(uint32_t mask)
{
__asm__ __volatile__
(
"wsr %0, INTCLEAR\n"
: "=r"(mask) : :
);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xtensa_int_decode
*
* Description:
* Determine the peripheral that generated the interrupt and dispatch
* handling to the registered interrupt handler via xtensa_irq_dispatch().
*
* Input Parameters:
* cpuints - Set of pending interrupts valid for this level
* regs - Saves processor state on the stack
*
* Returned Value:
* Normally the same value as regs is returned. But, in the event of an
* interrupt level context switch, the returned value will, instead point
* to the saved processor state in the TCB of the newly started task.
*
****************************************************************************/
uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs)
{
uint8_t *intmap;
uint32_t mask;
int bit;
intmap = g_cpu0_intmap;
/* Skip over zero bits, eight at a time */
for (bit = 0, mask = 0xff;
bit < ESP32S2_NCPUINTS && (cpuints & mask) == 0;
bit += 8, mask <<= 8);
/* Process each pending CPU interrupt */
for (; bit < ESP32S2_NCPUINTS && cpuints != 0; bit++)
{
mask = (1 << bit);
if ((cpuints & mask) != 0)
{
/* Extract the IRQ number from the mapping table */
uint8_t irq = intmap[bit];
DEBUGASSERT(irq != CPUINT_UNASSIGNED);
/* Clear software or edge-triggered interrupt */
xtensa_intclear(mask);
/* Dispatch the CPU interrupt.
*
* NOTE that regs may be altered in the case of an interrupt
* level context switch.
*/
regs = xtensa_irq_dispatch((int)irq, regs);
/* Clear the bit in the pending interrupt so that perhaps
* we can exit the look early.
*/
cpuints &= ~mask;
}
}
return regs;
}

109
arch/xtensa/src/esp32s2/esp32s2_irq.c Normal file

@ -0,0 +1,109 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_irq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include "xtensa.h"
#include "esp32s2_cpuint.h"
#include "esp32s2_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/* g_current_regs[] holds a reference to the current interrupt level
* register storage structure. It is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
volatile uint32_t *g_current_regs[1];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_irq_dump
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void esp32s2_irq_dump(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
#warning Missing logic
leave_critical_section(flags);
}
#else
# define esp32s2_irq_dump(msg, irq)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
/* Initialize CPU interrupts */
esp32s2_cpuint_initialize();
/* Attach and enable internal interrupts */
esp32s2_irq_dump("initial", NR_IRQS);
#ifdef CONFIG_ESP32S2_GPIO_IRQ
/* Initialize GPIO interrupt support */
esp32s2_gpioirqinitialize();
#endif
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts. Also clears PS.EXCM */
up_irq_enable();
#endif
}

656
arch/xtensa/src/esp32s2/esp32s2_lowputc.c Normal file

@ -0,0 +1,656 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_lowputc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
#include "xtensa.h"
#include "hardware/esp32s2_system.h"
#include "hardware/esp32s2_uart.h"
#include "hardware/esp32s2_soc.h"
#include "esp32s2_clockconfig.h"
#include "esp32s2_config.h"
#include "esp32s2_gpio.h"
#include "esp32s2_lowputc.h"
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef HAVE_UART_DEVICE
#ifdef CONFIG_ESP32S2_UART0
struct esp32s2_uart_s g_uart0_config =
{
.periph = ESP32S2_PERI_UART,
.id = 0,
.cpuint = -ENOMEM,
.irq = ESP32S2_IRQ_UART,
.baud = CONFIG_UART0_BAUD,
.bits = CONFIG_UART0_BITS,
.parity = CONFIG_UART0_PARITY,
.stop_b2 = CONFIG_UART0_2STOP,
.int_pri = ESP32S2_INT_PRIO_DEF,
.txpin = CONFIG_ESP32S2_UART0_TXPIN,
.txsig = U0TXD_OUT_IDX,
.rxpin = CONFIG_ESP32S2_UART0_RXPIN,
.rxsig = U0RXD_IN_IDX,
};
#endif /* CONFIG_ESP32S2_UART0 */
#ifdef CONFIG_ESP32S2_UART1
struct esp32s2_uart_s g_uart1_config =
{
.periph = ESP32S2_PERI_UART1,
.id = 1,
.cpuint = -ENOMEM,
.irq = ESP32S2_IRQ_UART1,
.baud = CONFIG_UART1_BAUD,
.bits = CONFIG_UART1_BITS,
.parity = CONFIG_UART1_PARITY,
.stop_b2 = CONFIG_UART1_2STOP,
.int_pri = ESP32S2_INT_PRIO_DEF,
.txpin = CONFIG_ESP32S2_UART1_TXPIN,
.txsig = U1TXD_OUT_IDX,
.rxpin = CONFIG_ESP32S2_UART1_RXPIN,
.rxsig = U1RXD_IN_IDX,
};
#endif /* CONFIG_ESP32S2_UART1 */
#endif /* HAVE_UART_DEVICE */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_lowputc_enable_sysclk
*
* Description:
* Enable clock for the UART using the System register.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_enable_sysclk(const struct esp32s2_uart_s *priv)
{
if (priv->id == 0)
{
modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0,
SYSTEM_UART_CLK_EN_M);
}
else
{
modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0,
SYSTEM_UART1_CLK_EN_M);
}
}
/****************************************************************************
* Name: esp32s2_lowputc_enable_memclk
*
* Description:
* Enable memory clock gate enable signal.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_enable_memclk(const struct esp32s2_uart_s *priv)
{
modifyreg32(UART_CONF0_REG(priv->id), 0, UART_MEM_CLK_EN_M);
}
/****************************************************************************
* Name: esp32s2_lowputc_disable_sysclk
*
* Description:
* Disable clock for the UART using the System register.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_disable_sysclk(const struct esp32s2_uart_s *priv)
{
if (priv->id == 0)
{
modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_UART_CLK_EN_M, 0);
}
else
{
modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_UART1_CLK_EN_M, 0);
}
}
/****************************************************************************
* Name: esp32s2_lowputc_disable_memclk
*
* Description:
* Disable memory clock gate enable signal.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_disable_memclk(const struct esp32s2_uart_s *priv)
{
modifyreg32(UART_CONF0_REG(priv->id), UART_MEM_CLK_EN_M, 0);
}
/****************************************************************************
* Name: esp32s2_lowputc_set_sclk
*
* Description:
* Set a source clock for UART.
*
* Parameters:
* priv - Pointer to the private driver struct.
* source - REF_TICK = 0
* APB_CLK = 1 80 MHz
*
****************************************************************************/
void esp32s2_lowputc_set_sclk(const struct esp32s2_uart_s *priv,
enum uart_sclk source)
{
modifyreg32(UART_CONF0_REG(priv->id), UART_TICK_REF_ALWAYS_ON_M, source);
}
/****************************************************************************
* Name: esp32s2_lowputc_get_sclk
*
* Description:
* Get the source clock for UART.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
* Returned Value:
* The frequency of the clock in Hz.
*
****************************************************************************/
uint32_t esp32s2_lowputc_get_sclk(const struct esp32s2_uart_s * priv)
{
uint32_t clk_conf_reg;
uint32_t ret = -ENODATA;
uint32_t clk;
clk_conf_reg = getreg32(UART_CONF0_REG(priv->id));
clk = REG_MASK(clk_conf_reg, UART_TICK_REF_ALWAYS_ON);
if (clk == 1)
{
ret = esp_clk_apb_freq();
}
else
{
/* TODO in esp32s2_clockconfig.c
* ret = esp32s2_clk_ref_freq();
*/
}
return ret;
}
/****************************************************************************
* Name: esp32s2_lowputc_baud
*
* Description:
* Set the baud rate according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_baud(const struct esp32s2_uart_s * priv)
{
uint32_t sclk_freq;
uint32_t clk_div;
uint32_t int_part;
uint32_t frag_part;
/* Get serial clock */
sclk_freq = esp32s2_lowputc_get_sclk(priv);
/* Calculate the clock divisor to achieve the baud rate.
* baud = sclk/clk_div
* clk_div = int_part + (frag_part/16)
* 16*clk_div = 16*int_part + frag
* 16*clk_div = (sclk*16)/baud
*/
clk_div = ((sclk_freq << 4) / (priv->baud));
/* Get the integer part of it. */
int_part = clk_div >> 4;
/* Get the frag part of it. */
frag_part = clk_div & 0xf;
/* Set integer part of the clock divisor for baud rate. */
int_part = VALUE_TO_FIELD(int_part, UART_CLKDIV);
modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_M, int_part);
/* Set decimal part of the clock divisor for baud rate. */
frag_part = VALUE_TO_FIELD(frag_part, UART_CLKDIV_FRAG);
modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_FRAG_M, frag_part);
}
/****************************************************************************
* Name: esp32s2_lowputc_normal_mode
*
* Description:
* Set the UART to operate in normal mode, i.e., disable the RS485 mode and
* IRDA mode.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_normal_mode(const struct esp32s2_uart_s * priv)
{
/* Disable RS485 mode */
modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485_EN_M, 0);
modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485TX_RX_EN_M, 0);
modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485RXBY_TX_EN_M, 0);
/* Disable IRDA mode */
modifyreg32(UART_CONF0_REG(priv->id), UART_IRDA_EN_M, 0);
}
/****************************************************************************
* Name: esp32s2_lowputc_parity
*
* Description:
* Set the parity, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_parity(const struct esp32s2_uart_s * priv)
{
if (priv->parity == UART_PARITY_DISABLE)
{
modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M, 0);
}
else
{
modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_M,
((priv->parity & BIT(0)) << UART_PARITY_S));
modifyreg32(UART_CONF0_REG(priv->id), 0, UART_PARITY_EN_M);
}
}
/****************************************************************************
* Name: esp32s2_lowputc_data_length
*
* Description:
* Set the data bits length, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
int esp32s2_lowputc_data_length(const struct esp32s2_uart_s * priv)
{
int ret = OK;
uint32_t length = (priv->bits - 5);
/* If it is the allowed range */
if (length >= UART_DATA_5_BITS && length <= UART_DATA_8_BITS)
{
modifyreg32(UART_CONF0_REG(priv->id), UART_BIT_NUM_M,
length << UART_BIT_NUM_S);
}
else
{
ret = -EINVAL;
}
return ret;
}
/****************************************************************************
* Name: esp32s2_lowputc_stop_length
*
* Description:
* Set the stop bits length, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_stop_length(const struct esp32s2_uart_s *priv)
{
if (priv->stop_b2 == 0)
{
modifyreg32(UART_CONF0_REG(priv->id), UART_STOP_BIT_NUM_M,
UART_STOP_BITS_1 << UART_STOP_BIT_NUM_S);
}
else
{
modifyreg32(UART_CONF0_REG(priv->id), UART_STOP_BIT_NUM_M,
UART_STOP_BITS_2 << UART_STOP_BIT_NUM_S);
}
}
/****************************************************************************
* Name: esp32s2_lowputc_send_byte
*
* Description:
* Send one byte.
*
* Parameters:
* priv - Pointer to the private driver struct.
* byte - Byte to be sent.
*
****************************************************************************/
void esp32s2_lowputc_send_byte(const struct esp32s2_uart_s * priv,
char byte)
{
putreg32((uint32_t) byte, UART_FIFO_REG(priv->id));
}
/****************************************************************************
* Name: esp32s2_lowputc_is_tx_fifo_full
*
* Description:
* Verify if TX FIFO is full.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
* Returned Value:
* True if it is full, otherwise false.
*
****************************************************************************/
bool esp32s2_lowputc_is_tx_fifo_full(const struct esp32s2_uart_s *priv)
{
uint32_t reg;
uint32_t val;
reg = getreg32(UART_STATUS_REG(priv->id));
val = REG_MASK(reg, UART_TXFIFO_CNT);
if (val < (UART_TX_FIFO_SIZE -1))
{
return false;
}
else
{
return true;
}
}
/****************************************************************************
* Name: esp32s2_lowputc_rst_peripheral
*
* Description:
* Reset the UART peripheral by using System reg.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_rst_peripheral(const struct esp32s2_uart_s *priv)
{
if (priv->id == 0)
{
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, SYSTEM_UART_RST_M);
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART_RST_M, 0);
}
else
{
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, SYSTEM_UART1_RST_M);
modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART1_RST_M, 0);
}
}
/****************************************************************************
* Name: esp32s2_lowputc_rst_txfifo
*
* Description:
* Reset TX FIFO.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_rst_txfifo(const struct esp32s2_uart_s *priv)
{
modifyreg32(UART_CONF0_REG(priv->id), 0, UART_TXFIFO_RST_M);
modifyreg32(UART_CONF0_REG(priv->id), UART_TXFIFO_RST_M, 0);
}
/****************************************************************************
* Name: esp32s2_lowputc_rst_rxfifo
*
* Description:
* Reset RX FIFO.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_rst_rxfifo(const struct esp32s2_uart_s *priv)
{
modifyreg32(UART_CONF0_REG(priv->id), 0, UART_RXFIFO_RST_M);
modifyreg32(UART_CONF0_REG(priv->id), UART_RXFIFO_RST_M, 0);
}
/****************************************************************************
* Name: esp32s2_lowputc_disable_all_uart_int
*
* Description:
* Disable all UART interrupts.
*
* Parameters:
* priv - Pointer to the private driver struct.
* current_status - Pointer to a variable to store the current status of
* the interrupt enable register before disabling
* UART interrupts.
*
****************************************************************************/
void esp32s2_lowputc_disable_all_uart_int(const struct esp32s2_uart_s *priv,
uint32_t *current_status)
{
irqstate_t flags;
flags = enter_critical_section();
if (current_status != NULL)
{
/* Save current status */
*current_status = getreg32(UART_INT_ENA_REG(priv->id));
}
/* Disable all UART int */
putreg32(0, UART_INT_ENA_REG(priv->id));
/* Clear all ints */
putreg32(UINT32_MAX, UART_INT_CLR_REG(priv->id));
leave_critical_section(flags);
}
/****************************************************************************
* Name: esp32s2_lowputc_restore_all_uart_int
*
* Description:
* Restore all UART interrupts.
*
* Parameters:
* priv - Pointer to the private driver struct.
* last_status - Pointer to a variable that stored the last state of the
* interrupt enable register.
*
****************************************************************************/
void esp32s2_lowputc_restore_all_uart_int(const struct esp32s2_uart_s *priv,
uint32_t *last_status)
{
/* Restore the previous behaviour */
putreg32(*last_status, UART_INT_ENA_REG(priv->id));
}
/****************************************************************************
* Name: esp32s2_lowputc_config_pins
*
* Description:
* Configure TX and RX UART pins.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_config_pins(const struct esp32s2_uart_s *priv)
{
/* Configure the pins */
/* Route UART TX signal to the selected TX pin */
esp32s2_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0);
/* Select the GPIO function to the TX pin and configure as output. */
esp32s2_configgpio(priv->txpin, OUTPUT_FUNCTION_1);
/* Select the GPIO function to the RX pin and configure as input. */
esp32s2_configgpio(priv->rxpin, INPUT_FUNCTION_1);
/* Route UART RX signal to the selected RX pin */
esp32s2_gpio_matrix_in(priv->rxpin, priv->rxsig, 0);
}
/****************************************************************************
* Name: up_lowputc
*
* Description:
* Output one byte on the serial console.
*
* Parameters:
* ch - Byte to be sent.
*
****************************************************************************/
void up_lowputc(char ch)
{
#ifdef HAVE_SERIAL_CONSOLE
# if defined(CONFIG_UART0_SERIAL_CONSOLE)
struct esp32s2_uart_s *priv = &g_uart0_config;
#elif defined (CONFIG_UART1_SERIAL_CONSOLE)
struct esp32s2_uart_s *priv = &g_uart1_config;
#endif
/* Wait until the TX FIFO has space to insert new char */
while (esp32s2_lowputc_is_tx_fifo_full(priv));
/* Then send the character */
esp32s2_lowputc_send_byte(priv, ch);
#endif /* HAVE_CONSOLE */
}
/****************************************************************************
* Name: esp32s2_lowsetup
*
* Description:
* This performs only the basic configuration for UART pins.
*
****************************************************************************/
void esp32s2_lowsetup(void)
{
#ifndef CONFIG_SUPPRESS_UART_CONFIG
#ifdef CONFIG_ESP32S2_UART0
esp32s2_lowputc_config_pins(&g_uart0_config);
#endif
#ifdef CONFIG_ESP32S2_UART1
esp32s2_lowputc_config_pins(&g_uart1_config);
#endif
#endif /* !CONFIG_SUPPRESS_UART_CONFIG */
}

391
arch/xtensa/src/esp32s2/esp32s2_lowputc.h Normal file

@ -0,0 +1,391 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_lowputc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_LOWPUTC_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <debug.h>
#include "hardware/esp32s2_uart.h"
#include "hardware/esp32s2_gpio_sigmap.h"
#include "esp32s2_cpuint.h"
/****************************************************************************
* Public Types
****************************************************************************/
enum uart_sclk
{
REF_TICK,
APB_CLK = 1, /* 80 MHz */
};
enum uart_parity
{
UART_PARITY_DISABLE,
UART_PARITY_ODD,
UART_PARITY_EVEN
};
enum uart_data_length
{
UART_DATA_5_BITS,
UART_DATA_6_BITS,
UART_DATA_7_BITS,
UART_DATA_8_BITS
};
enum uart_stop_length
{
UART_STOP_BITS_1 = 0x1, /* Stop bit: 1 bit */
UART_STOP_BITS_2 = 0x3, /* Stop bit: 2 bits */
};
/* Default FIFOs size */
#define UART_TX_FIFO_SIZE 128
#define UART_RX_FIFO_SIZE 128
/* Struct used to store uart driver information and to
* manipulate uart driver
*/
struct esp32s2_uart_s
{
uint8_t periph; /* UART peripheral ID */
int cpuint; /* CPU interrupt assigned to this UART */
uint8_t id; /* UART ID */
uint8_t irq; /* IRQ associated with this UART */
uint32_t baud; /* Configured baud rate */
uint8_t bits; /* Data length (5 to 8 bits). */
uint8_t parity; /* 0=no parity, 1=odd parity, 2=even parity */
uint8_t stop_b2; /* Use 2 stop bits? 0 = no (use 1) 1 = yes (use 2) */
uint8_t int_pri; /* UART Interrupt Priority */
uint8_t txpin; /* TX pin */
uint8_t txsig; /* TX signal */
uint8_t rxpin; /* RX pin */
uint8_t rxsig; /* RX signal */
};
extern struct esp32s2_uart_s g_uart0_config;
extern struct esp32s2_uart_s g_uart1_config;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s2_lowputc_enable_sysclk
*
* Description:
* Enable clock for the UART using the System register.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_enable_sysclk(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_enable_memclk
*
* Description:
* Enable memory clock gate enable signal.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_enable_memclk(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_disable_sysclk
*
* Description:
* Disable clock for the UART using the System register.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_disable_sysclk(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_disable_memclk
*
* Description:
* Disable memory clock gate enable signal.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_disable_memclk(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_set_sclk
*
* Description:
* Set a source clock for UART.
*
* Parameters:
* priv - Pointer to the private driver struct.
* source - REF_TICK = 0
* APB_CLK = 1 80 MHz
*
****************************************************************************/
void esp32s2_lowputc_set_sclk(const struct esp32s2_uart_s *priv,
enum uart_sclk source);
/****************************************************************************
* Name: esp32s2_lowputc_get_sclk
*
* Description:
* Get the source clock for UART.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
* Returned Value:
* The frequency of the clock in Hz.
*
****************************************************************************/
uint32_t esp32s2_lowputc_get_sclk(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_baud
*
* Description:
* Set the baud rate according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_baud(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_normal_mode
*
* Description:
* Set the UART to operate in normal mode, i.e., disable the RS485 mode and
* IRDA mode.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_normal_mode(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_parity
*
* Description:
* Set the parity, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_parity(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_data_length
*
* Description:
* Set the data bits length, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
int esp32s2_lowputc_data_length(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_stop_length
*
* Description:
* Set the stop bits length, according to the value in the private driver
* struct.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_stop_length(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_send_byte
*
* Description:
* Send one byte.
*
* Parameters:
* priv - Pointer to the private driver struct.
* byte - Byte to be sent.
*
****************************************************************************/
void esp32s2_lowputc_send_byte(const struct esp32s2_uart_s *priv,
char byte);
/****************************************************************************
* Name: esp32s2_lowputc_is_tx_fifo_full
*
* Description:
* Verify if TX FIFO is full.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
* Returned Value:
* True if it is full, otherwise false.
*
****************************************************************************/
bool esp32s2_lowputc_is_tx_fifo_full(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_rst_peripheral
*
* Description:
* Reset the UART peripheral by using System reg.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_rst_peripheral(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_rst_txfifo
*
* Description:
* Reset TX FIFO.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_rst_txfifo(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_rst_rxfifo
*
* Description:
* Reset RX FIFO.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_rst_rxfifo(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowputc_disable_all_uart_int
*
* Description:
* Disable all UART interrupts.
*
* Parameters:
* priv - Pointer to the private driver struct.
* current_status - Pointer to a variable to store the current status of
* the interrupt enable register before disabling
* UART interrupts.
*
****************************************************************************/
void esp32s2_lowputc_disable_all_uart_int(const struct esp32s2_uart_s *priv,
uint32_t *current_status);
/****************************************************************************
* Name: esp32s2_lowputc_restore_all_uart_int
*
* Description:
* Restore all UART interrupts.
*
* Parameters:
* priv - Pointer to the private driver struct.
* last_status - Pointer to a variable that stored the last state of the
* interrupt enable register.
*
****************************************************************************/
void esp32s2_lowputc_restore_all_uart_int(const struct esp32s2_uart_s *priv,
uint32_t * last_status);
/****************************************************************************
* Name: esp32s2_lowputc_config_pins
*
* Description:
* Configure TX and RX UART pins.
*
* Parameters:
* priv - Pointer to the private driver struct.
*
****************************************************************************/
void esp32s2_lowputc_config_pins(const struct esp32s2_uart_s *priv);
/****************************************************************************
* Name: esp32s2_lowsetup
*
* Description:
* This performs basic initialization of the UART used for the serial
* console. Its purpose is to get the console output available as soon
* as possible.
*
****************************************************************************/
void esp32s2_lowsetup(void);
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_LOWPUTC_H */

218
arch/xtensa/src/esp32s2/esp32s2_pm.h Normal file

@ -0,0 +1,218 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_pm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PMSLEEP_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PMSLEEP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#ifdef CONFIG_PM
/****************************************************************************
* Public Types
****************************************************************************/
/* Sleep wakeup cause */
enum esp32s2_sleep_source_e
{
/* In case of deep sleep, reset was not caused by exit from deep sleep */
ESP_SLEEP_WAKEUP_UNDEFINED,
/* Not a wakeup cause, used to disable all wakeup sources with
* esp_sleep_disable_wakeup_source
*/
ESP_SLEEP_WAKEUP_ALL,
/* Wakeup caused by external signal using RTC_IO */
ESP_SLEEP_WAKEUP_EXT0,
/* Wakeup caused by external signal using RTC_CNTL */
ESP_SLEEP_WAKEUP_EXT1,
/* Wakeup caused by timer */
ESP_SLEEP_WAKEUP_TIMER,
/* Wakeup caused by touchpad */
ESP_SLEEP_WAKEUP_TOUCHPAD,
/* Wakeup caused by ULP program */
ESP_SLEEP_WAKEUP_ULP,
/* Wakeup caused by GPIO (light sleep only) */
ESP_SLEEP_WAKEUP_GPIO,
/* Wakeup caused by UART (light sleep only) */
ESP_SLEEP_WAKEUP_UART,
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s2_sleep_enable_timer_wakeup
*
* Description:
* Configure wake-up interval
*
* Input Parameters:
* time_in_us - Configure wake-up time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_sleep_enable_timer_wakeup(uint64_t time_in_us);
/****************************************************************************
* Name: esp32s2_light_sleep_start
*
* Description:
* Enter sleep mode
*
* Input Parameters:
* None
*
* Returned Value:
* 0 is returned on success or a negated errno value is returned
*
****************************************************************************/
int esp32s2_light_sleep_start(void);
/****************************************************************************
* Name: esp32s2_pminit
*
* Description:
* Initialize force sleep parameters.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_pminit(void);
/****************************************************************************
* Name: esp32s2_pmstandby
*
* Description:
* Enter force sleep time interval.
*
* Input Parameters:
* time_in_us - force sleep time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_pmstandby(uint64_t time_in_us);
/****************************************************************************
* Name: esp32s2_sleep_get_wakeup_cause
*
* Description:
* Get the wakeup source which caused wakeup from sleep.
*
* Input Parameters:
* None
*
* Returned Value:
* enum esp32s2_sleep_source_e - Cause of wake up from last sleep.
*
****************************************************************************/
enum esp32s2_sleep_source_e esp32s2_sleep_get_wakeup_cause(void);
/****************************************************************************
* Name: esp32s2_deep_sleep_start
*
* Description:
* Enter deep sleep mode
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_deep_sleep_start(void);
/****************************************************************************
* Name: esp32s2_pmsleep
*
* Description:
* Enter deep sleep.
*
* Input Parameters:
* time_in_us - deep sleep time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_pmsleep(uint64_t time_in_us);
#endif /* CONFIG_PM */
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PMSLEEP_H */

102
arch/xtensa/src/esp32s2/esp32s2_region.c Normal file

@ -0,0 +1,102 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_region.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
/****************************************************************************
* Private Data
****************************************************************************/
static const uint32_t g_protected_pages[] =
{
0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000
};
#define NPROTECTED_PAGES (sizeof(g_protected_pages)/sizeof(uint32_t))
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: xtensa_write_dtlb and xtensa_write_itlb
*
* Description:
* Functions to set page attributes for Region Protection option in the
* CPU. See Xtensa ISA Reference manual for explanation of arguments
* (section 4.6.3.2).
*
****************************************************************************/
static inline void xtensa_write_dtlb(uint32_t vpn, unsigned int attr)
{
__asm__ __volatile__
(
"wdtlb %1, %0\n"
"dsync\n"
: : "r" (vpn), "r" (attr)
);
}
static inline void xtensa_write_itlb(unsigned vpn, unsigned int attr)
{
__asm__ __volatile__
(
"witlb %1, %0\n"
"isync\n"
: : "r" (vpn), "r" (attr)
);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_region_protection
*
* Description:
* Make page 0 access raise an exception. Also protect some other unused
* pages so we can catch weirdness.
*
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
*
****************************************************************************/
void esp32s2_region_protection(void)
{
int i;
for (i = 0; i < NPROTECTED_PAGES; ++i)
{
xtensa_write_dtlb(g_protected_pages[i], 0xf);
xtensa_write_itlb(g_protected_pages[i], 0xf);
}
xtensa_write_dtlb(0x20000000, 0);
xtensa_write_itlb(0x20000000, 0);
}

52
arch/xtensa/src/esp32s2/esp32s2_region.h Normal file

@ -0,0 +1,52 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_region.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_REGION_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_REGION_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_region_protection
*
* Description:
* Make page 0 access raise an exception. Also protect some other unused
* pages so we can catch weirdness.
*
* Useful attribute values:
* 0 — cached, RW
* 2 — bypass cache, RWX (default value after CPU reset)
* 15 — no access, raise exception
*
****************************************************************************/
void esp32s2_region_protection(void);
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_REGION_H */

562
arch/xtensa/src/esp32s2/esp32s2_rtc.c Normal file

@ -0,0 +1,562 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_rtc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include <assert.h>
#include "esp32s2_rtc.h"
#include "esp32s2_clockconfig.h"
#include "hardware/esp32s2_i2s.h"
#include "hardware/esp32s2_rtccntl.h"
#include "hardware/esp32s2_i2cbbpll.h"
#include "hardware/esp32s2_system.h"
#include "esp32s2_rtc.h"
#include "xtensa.h"
#include "xtensa_attr.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Various delays to be programmed into power control state machines */
#define RTC_CNTL_XTL_BUF_WAIT_SLP 2
#define RTC_CNTL_CK8M_WAIT_SLP 4
#define OTHER_BLOCKS_POWERUP 1
#define OTHER_BLOCKS_WAIT 1
#define ROM_RAM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define ROM_RAM_WAIT_CYCLES OTHER_BLOCKS_WAIT
#define WIFI_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define WIFI_WAIT_CYCLES OTHER_BLOCKS_WAIT
#define RTC_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define RTC_WAIT_CYCLES OTHER_BLOCKS_WAIT
#define DG_WRAP_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define DG_WRAP_WAIT_CYCLES OTHER_BLOCKS_WAIT
#define RTC_MEM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define RTC_MEM_WAIT_CYCLES OTHER_BLOCKS_WAIT
#define RTC_CNTL_PLL_BUF_WAIT_SLP 2
#define DELAY_FAST_CLK_SWITCH 3
#define XTAL_32K_DAC_VAL 3
#define XTAL_32K_DRES_VAL 3
#define XTAL_32K_DBIAS_VAL 0
#define DELAY_SLOW_CLK_SWITCH 300
/* Number of fractional bits in values returned by rtc_clk_cal */
#define RTC_CLK_CAL_FRACT 19
/* With the default value of CK8M_DFREQ,
* 8M clock frequency is 8.5 MHz +/- 7%
*/
#define RTC_FAST_CLK_FREQ_APPROX 8500000
/* Disable logging from the ROM code. */
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16))
/* Default initializer for esp32s2_rtc_sleep_config_t
* This initializer sets all fields to "reasonable" values
* (e.g. suggested for production use) based on a combination
* of RTC_SLEEP_PD_x flags.
*/
#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
.lslp_mem_inf_fpu = 0, \
.rtc_mem_inf_fpu = 0, \
.rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
.rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
.wifi_pd_en = 0, \
.rom_mem_pd_en = 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \
.dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \
.dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \
.rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \
.rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \
.lslp_meminf_pd = 1, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1 \
}
/* Initializer for rtc_sleep_pd_config_t which
* sets all flags to the same value
*/
#define RTC_SLEEP_PD_CONFIG_ALL(val) {\
.dig_pd = (val), \
.rtc_pd = (val), \
.cpu_pd = (val), \
.i2s_pd = (val), \
.bb_pd = (val), \
.nrx_pd = (val), \
.fe_pd = (val), \
}
/****************************************************************************
* Private Types
****************************************************************************/
/* RTC power and clock control initialization settings */
struct esp32s2_rtc_priv_s
{
uint32_t ck8m_wait : 8; /* Number of rtc_fast_clk cycles to wait for 8M clock to be ready */
uint32_t xtal_wait : 8; /* Number of rtc_fast_clk cycles to wait for XTAL clock to be ready */
uint32_t pll_wait : 8; /* Number of rtc_fast_clk cycles to wait for PLL to be ready */
uint32_t clkctl_init : 1; /* Perform clock control related initialization */
uint32_t pwrctl_init : 1; /* Perform power control related initialization */
uint32_t rtc_dboost_fpd : 1; /* Force power down RTC_DBOOST */
};
/* sleep configuration for rtc_sleep_init function */
struct esp32s2_rtc_sleep_config_s
{
uint32_t lslp_mem_inf_fpu : 1; /* force normal voltage in sleep mode (digital domain memory) */
uint32_t rtc_mem_inf_fpu : 1; /* force normal voltage in sleep mode (RTC memory) */
uint32_t rtc_mem_inf_follow_cpu : 1; /* keep low voltage in sleep mode (even if ULP/touch is used) */
uint32_t rtc_fastmem_pd_en : 1; /* power down RTC fast memory */
uint32_t rtc_slowmem_pd_en : 1; /* power down RTC slow memory */
uint32_t rtc_peri_pd_en : 1; /* power down RTC peripherals */
uint32_t wifi_pd_en : 1; /* power down WiFi */
uint32_t rom_mem_pd_en : 1; /* power down main RAM and ROM */
uint32_t deep_slp : 1; /* power down digital domain */
uint32_t wdt_flashboot_mod_en : 1; /* enable WDT flashboot mode */
uint32_t dig_dbias_wak : 3; /* set bias for digital domain, in active mode */
uint32_t dig_dbias_slp : 3; /* set bias for digital domain, in sleep mode */
uint32_t rtc_dbias_wak : 3; /* set bias for RTC domain, in active mode */
uint32_t rtc_dbias_slp : 3; /* set bias for RTC domain, in sleep mode */
uint32_t lslp_meminf_pd : 1; /* remove all peripheral force power up flags */
uint32_t vddsdio_pd_en : 1; /* power down VDDSDIO regulator */
uint32_t xtal_fpu : 1; /* keep main XTAL powered up in sleep */
};
/* Power down flags for rtc_sleep_pd function */
struct esp32s2_rtc_sleep_pd_config_s
{
uint32_t dig_pd : 1; /* Set to 1 to power down digital part in sleep */
uint32_t rtc_pd : 1; /* Set to 1 to power down RTC memories in sleep */
uint32_t cpu_pd : 1; /* Set to 1 to power down digital memories and CPU in sleep */
uint32_t i2s_pd : 1; /* Set to 1 to power down I2S in sleep */
uint32_t bb_pd : 1; /* Set to 1 to power down WiFi in sleep */
uint32_t nrx_pd : 1; /* Set to 1 to power down WiFi in sleep */
uint32_t fe_pd : 1; /* Set to 1 to power down WiFi in sleep */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static void IRAM_ATTR esp32s2_rtc_sleep_pd(
struct esp32s2_rtc_sleep_pd_config_s cfg);
static inline bool esp32s2_clk_val_is_valid(uint32_t val);
static void IRAM_ATTR esp32s2_rtc_clk_fast_freq_set(
enum esp32s2_rtc_fast_freq_e fast_freq);
static uint32_t IRAM_ATTR esp32s2_rtc_clk_cal_internal(
enum esp32s2_rtc_cal_sel_e cal_clk, uint32_t slowclk_cycles);
static void IRAM_ATTR esp32s2_rtc_clk_slow_freq_set(
enum esp32s2_rtc_slow_freq_e slow_freq);
static void esp32s2_select_rtc_slow_clk(enum esp32s2_slow_clk_sel_e
slow_clk);
/****************************************************************************
* Private Data
****************************************************************************/
static struct esp32s2_rtc_priv_s esp32s2_rtc_priv =
{
.ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT,
.xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT,
.pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT,
.clkctl_init = 1,
.pwrctl_init = 1,
.rtc_dboost_fpd = 1
};
/****************************************************************************
* Private Functions
****************************************************************************/
extern void ets_delay_us(uint32_t us);
/****************************************************************************
* Name: esp32s2_clk_val_is_valid
*
* Description:
* Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are
* stored as two copies in lower and upper 16-bit halves.
* These are the routines to work with such a representation.
*
* Input Parameters:
* val - register value
*
* Returned Value:
* true: Valid register value.
* false: Invalid register value.
*
****************************************************************************/
static inline bool esp32s2_clk_val_is_valid(uint32_t val)
{
return (val & 0xffff) == ((val >> 16) & 0xffff)
&& val != 0 && val != UINT32_MAX;
}
/****************************************************************************
* Public Functions
****************************************************************************/
enum esp32s2_rtc_xtal_freq_e rtc_get_xtal(void)
__attribute__((alias("esp32s2_rtc_clk_xtal_freq_get")));
/****************************************************************************
* Name: esp32s2_rtc_clk_xtal_freq_get
*
* Description:
* Get main XTAL frequency
*
* Input Parameters:
* None
*
* Returned Value:
* XTAL frequency (one of enum esp32s2_rtc_xtal_freq_e values)
*
****************************************************************************/
enum esp32s2_rtc_xtal_freq_e IRAM_ATTR esp32s2_rtc_clk_xtal_freq_get(void)
{
/* We may have already written XTAL value into RTC_XTAL_FREQ_REG */
uint32_t xtal_freq_reg = getreg32(RTC_XTAL_FREQ_REG);
if (!esp32s2_clk_val_is_valid(xtal_freq_reg))
{
return RTC_XTAL_FREQ_AUTO;
}
return (xtal_freq_reg & ~RTC_DISABLE_ROM_LOG) & UINT16_MAX;
}
/****************************************************************************
* Name: esp32s2_rtc_update_to_xtal
*
* Description:
* Switch to XTAL frequency, does not disable the PLL
*
* Input Parameters:
* freq - XTAL frequency
* div - REF_TICK divider
*
* Returned Value:
* none
*
****************************************************************************/
void IRAM_ATTR esp32s2_rtc_update_to_xtal(int freq, int div)
{
uint32_t value = (((freq * MHZ) >> 12) & UINT16_MAX)
| ((((freq * MHZ) >> 12) & UINT16_MAX) << 16);
esp32s2_update_cpu_freq(freq);
/* set divider from XTAL to APB clock */
REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, div - 1);
/* adjust ref_tick */
modifyreg32(APB_CTRL_XTAL_TICK_CONF_REG, 0,
(freq * MHZ) / REF_CLK_FREQ - 1);
/* switch clock source */
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL,
RTC_CNTL_SOC_CLK_SEL_XTL);
putreg32(value, RTC_APB_FREQ_REG);
/* lower the voltage */
if (freq <= 2)
{
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M);
}
else
{
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
}
}
/****************************************************************************
* Name: esp32s2_rtc_bbpll_enable
*
* Description:
* Reset BBPLL configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void IRAM_ATTR esp32s2_rtc_bbpll_enable(void)
{
modifyreg32(RTC_CNTL_OPTIONS0_REG,
RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD, 0);
/* reset BBPLL configuration */
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY,
BBPLL_IR_CAL_DELAY_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP,
BBPLL_IR_CAL_EXT_CAP_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL,
BBPLL_OC_ENB_FCAL_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON,
BBPLL_OC_ENB_VCON_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0,
BBPLL_BBADC_CAL_7_0_VAL);
}
/****************************************************************************
* Name: esp32s2_rtc_bbpll_configure
*
* Description:
* Configure main XTAL frequency values according to pll_freq.
*
* Input Parameters:
* xtal_freq - XTAL frequency values
* pll_freq - PLL frequency values
*
* Returned Value:
* None
*
****************************************************************************/
void IRAM_ATTR esp32s2_rtc_bbpll_configure(
enum esp32s2_rtc_xtal_freq_e xtal_freq, int pll_freq)
{
static uint8_t div_ref = 0;
static uint8_t div7_0 = 0;
static uint8_t dr1 = 0;
static uint8_t dr3 = 0;
static uint8_t dchgp = 0;
static uint8_t dcur = 0;
uint8_t i2c_bbpll_lref = 0;
uint8_t i2c_bbpll_div_7_0 = 0;
uint8_t i2c_bbpll_dcur = 0;
if (pll_freq == RTC_PLL_FREQ_480M)
{
/* Clear this register to let the digital part know 480M PLL is used */
SET_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);
/* Configure 480M PLL */
div_ref = 0;
div7_0 = 8;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 4;
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6b);
}
else
{
/* Clear this register to let the digital part know 320M PLL is used */
CLEAR_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);
/* Configure 320M PLL */
div_ref = 0;
div7_0 = 4;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 5;
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
}
i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
i2c_bbpll_div_7_0 = div7_0;
i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB) |
(1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
/* Enable calibration by software */
I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_ENX_CAP, 1);
for (int ext_cap = 0; ext_cap < 16; ext_cap++)
{
uint8_t cal_result;
I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, ext_cap);
cal_result = I2C_READREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OR_CAL_CAP);
if (cal_result == 0)
{
break;
}
if (ext_cap == 15)
{
ets_printf("BBPLL SOFTWARE CAL FAIL\n");
abort();
}
}
}
/****************************************************************************
* Name: esp32s2_rtc_wait_for_slow_cycle
*
* Description:
* Busy loop until next RTC_SLOW_CLK cycle.
*
* Input Parameters:
* None
*
* Returned Value:
* none
*
****************************************************************************/
void IRAM_ATTR esp32s2_rtc_wait_for_slow_cycle(void)
{
modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING |
TIMG_RTC_CALI_START, 0);
modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY, 0);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL,
RTC_CAL_RTC_MUX);
/* Request to run calibration for 0 slow clock cycles.
* RDY bit will be set on the nearest slow clock cycle.
*/
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, 0);
modifyreg32(TIMG_RTCCALICFG_REG(0), 0, TIMG_RTC_CALI_START);
/* RDY needs some time to go low */
ets_delay_us(1);
while (!(getreg32(TIMG_RTCCALICFG_REG(0)) & TIMG_RTC_CALI_RDY))
{
ets_delay_us(1);
}
}
/****************************************************************************
* Name: esp_rtc_clk_get_cpu_freq
*
* Description:
* Get the currently used CPU frequency configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* CPU frequency
*
****************************************************************************/
int IRAM_ATTR esp_rtc_clk_get_cpu_freq(void)
{
uint32_t source_freq_mhz;
uint32_t div;
uint32_t soc_clk_sel;
uint32_t cpuperiod_sel;
int freq_mhz = 0;
soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
switch (soc_clk_sel)
{
case RTC_CNTL_SOC_CLK_SEL_XTL:
{
div = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG,
APB_CTRL_PRE_DIV_CNT) + 1;
source_freq_mhz = (uint32_t) esp32s2_rtc_clk_xtal_freq_get();
freq_mhz = source_freq_mhz / div;
}
break;
case RTC_CNTL_SOC_CLK_SEL_PLL:
{
cpuperiod_sel = REG_GET_FIELD(DPORT_CPU_PER_CONF_REG,
SYSTEM_CPUPERIOD_SEL);
if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80)
{
freq_mhz = 80;
}
else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160)
{
freq_mhz = 160;
}
else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240)
{
freq_mhz = 240;
}
else
{
DEBUGASSERT(0);
}
}
break;
case RTC_CNTL_SOC_CLK_SEL_8M:
{
freq_mhz = 8;
}
break;
case RTC_CNTL_SOC_CLK_SEL_APLL:
default:
DEBUGASSERT(0);
}
return freq_mhz;
}

358
arch/xtensa/src/esp32s2/esp32s2_rtc.h Normal file

@ -0,0 +1,358 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/esp32s2_soc.h"
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Number of cycles to wait from the 32k XTAL oscillator to
* consider it running. Larger values increase startup delay.
* Smaller values may cause false positive detection
* (i.e. oscillator runs for a few cycles and then stops).
*/
#define SLOW_CLK_CAL_CYCLES 1024
/* Indicates that 32k oscillator gets input from external oscillator
* instead of a crystal.
*/
#define EXT_OSC_FLAG BIT(3)
/****************************************************************************
* Public Types
****************************************************************************/
/* Possible main XTAL frequency values.
* Enum values should be equal to frequency in MHz.
*/
enum esp32s2_rtc_xtal_freq_e
{
RTC_XTAL_FREQ_AUTO = 0, /* Automatic XTAL frequency detection */
RTC_XTAL_FREQ_40M = 40, /* 40 MHz XTAL */
RTC_XTAL_FREQ_26M = 26, /* 26 MHz XTAL */
RTC_XTAL_FREQ_24M = 24, /* 24 MHz XTAL */
};
/* RTC SLOW_CLK frequency values */
enum esp32s2_rtc_slow_freq_e
{
RTC_SLOW_FREQ_RTC = 0, /* Internal 150 kHz RC oscillator */
RTC_SLOW_FREQ_32K_XTAL = 1, /* External 32 kHz XTAL */
RTC_SLOW_FREQ_8MD256 = 2, /* Internal 8 MHz RC oscillator, divided by 256 */
};
/* RTC FAST_CLK frequency values */
enum esp32s2_rtc_fast_freq_e
{
RTC_FAST_FREQ_XTALD4 = 0, /* Main XTAL, divided by 4 */
RTC_FAST_FREQ_8M = 1, /* Internal 8 MHz RC oscillator */
};
/* This is almost the same as esp32s2_rtc_slow_freq_e, except that we define
* an extra enum member for the external 32k oscillator. For convenience,
* lower 2 bits should correspond to esp32s2_rtc_slow_freq_e values.
*/
enum esp32s2_slow_clk_sel_e
{
/* Internal 150 kHz RC oscillator */
SLOW_CLK_150K = RTC_SLOW_FREQ_RTC,
/* External 32 kHz XTAL */
SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL,
/* Internal 8 MHz RC oscillator, divided by 256 */
SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256,
/* External 32k oscillator connected to 32K_XP pin */
SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG
};
/* Clock source to be calibrated using rtc_clk_cal function */
enum esp32s2_rtc_cal_sel_e
{
RTC_CAL_RTC_MUX = 0, /* Currently selected RTC SLOW_CLK */
RTC_CAL_8MD256 = 1, /* Internal 8 MHz RC oscillator, divided by 256 */
RTC_CAL_32K_XTAL = 2 /* External 32 kHz XTAL */
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s2_rtc_get_slow_clk_rtc
*
* Description:
* Get slow_clk_rtc source.
*
* Input Parameters:
* None
*
* Returned Value:
* The clock source:
* - SLOW_CK
* - CK_XTAL_32K
* - CK8M_D256_OUT
*
****************************************************************************/
enum esp32s2_rtc_slow_freq_e esp32s2_rtc_get_slow_clk(void);
/****************************************************************************
* Name: esp32s2_rtc_clk_cal
*
* Description:
* Measure RTC slow clock's period, based on main XTAL frequency
*
* Input Parameters:
* cal_clk - clock to be measured
* slowclk_cycles - number of slow clock cycles to average
*
* Returned Value:
* Average slow clock period in microseconds, Q13.19 fixed point format
* or 0 if calibration has timed out
*
****************************************************************************/
uint32_t esp32s2_rtc_clk_cal(enum esp32s2_rtc_cal_sel_e cal_clk,
uint32_t slowclk_cycles);
/****************************************************************************
* Name: esp32s2_rtc_clk_xtal_freq_get
*
* Description:
* Get main XTAL frequency
*
* Input Parameters:
* None
*
* Returned Value:
* XTAL frequency (one of enum esp32s2_rtc_xtal_freq_e values)
*
****************************************************************************/
enum esp32s2_rtc_xtal_freq_e esp32s2_rtc_clk_xtal_freq_get(void);
/****************************************************************************
* Name: esp32s2_rtc_update_to_xtal
*
* Description:
* Switch to XTAL frequency, does not disable the PLL
*
* Input Parameters:
* freq - XTAL frequency
* div - REF_TICK divider
*
* Returned Value:
* none
*
****************************************************************************/
void esp32s2_rtc_update_to_xtal(int freq, int div);
/****************************************************************************
* Name: esp32s2_rtc_bbpll_enable
*
* Description:
* Reset BBPLL configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_bbpll_enable(void);
/****************************************************************************
* Name: esp32s2_rtc_bbpll_configure
*
* Description:
* Configure main XTAL frequency values according to pll_freq.
*
* Input Parameters:
* xtal_freq - XTAL frequency values
* pll_freq - PLL frequency values
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_bbpll_configure(
enum esp32s2_rtc_xtal_freq_e xtal_freq, int pll_freq);
/****************************************************************************
* Name: esp32s2_rtc_clk_set
*
* Description:
* Set RTC CLK frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_clk_set(void);
/****************************************************************************
* Name: esp32s2_rtc_init
*
* Description:
* Initialize RTC clock and power control related functions.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_init(void);
/****************************************************************************
* Name: esp32s2_rtc_time_get
*
* Description:
* Get current value of RTC counter.
*
* Input Parameters:
* None
*
* Returned Value:
* current value of RTC counter
*
****************************************************************************/
uint64_t esp32s2_rtc_time_get(void);
/****************************************************************************
* Name: esp32s2_rtc_wait_for_slow_cycle
*
* Description:
* Busy loop until next RTC_SLOW_CLK cycle.
*
* Input Parameters:
* None
*
* Returned Value:
* none
*
****************************************************************************/
void esp32s2_rtc_wait_for_slow_cycle(void);
/****************************************************************************
* Name: esp_rtc_clk_get_cpu_freq
*
* Description:
* Get the currently used CPU frequency configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* CPU frequency
*
****************************************************************************/
int esp_rtc_clk_get_cpu_freq(void);
/****************************************************************************
* Name: esp32s2_rtc_sleep_init
*
* Description:
* Prepare the chip to enter sleep mode
*
* Input Parameters:
* flags - sleep mode configuration
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_sleep_init(uint32_t flags);
/****************************************************************************
* Name: esp32s2_rtc_sleep_start
*
* Description:
* Enter force sleep mode.
*
* Input Parameters:
* wakeup_opt - bit mask wake up reasons to enable
* reject_opt - bit mask of sleep reject reasons.
*
* Returned Value:
* non-zero if sleep was rejected by hardware
*
****************************************************************************/
int esp32s2_rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H */

1031
arch/xtensa/src/esp32s2/esp32s2_serial.c Normal file

File diff suppressed because it is too large Load Diff

169
arch/xtensa/src/esp32s2/esp32s2_start.c Normal file

@ -0,0 +1,169 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_start.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <string.h>
#include <nuttx/init.h>
#include <nuttx/irq.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "hardware/esp32s2_rtccntl.h"
#include "esp32s2_clockconfig.h"
#include "esp32s2_region.h"
#include "esp32s2_start.h"
#include "esp32s2_lowputc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) up_lowputc(c)
#else
# define showprogress(c)
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* Address of the CPU0 IDLE thread */
uint32_t g_idlestack[IDLETHREAD_STACKWORDS]
__attribute__((aligned(16), section(".noinit")));
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: __start
*
* Description:
* We arrive here after the bootloader finished loading the program from
* flash. The hardware is mostly uninitialized, and the app CPU is in
* reset. We do have a stack, so we can do the initialization in C.
*
****************************************************************************/
void IRAM_ATTR __start(void)
{
uint32_t *dest;
uint32_t regval;
uint32_t sp;
/* Kill the watchdog timer */
regval = getreg32(RTC_CNTL_WDTCONFIG0_REG);
regval &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN;
putreg32(regval, RTC_CNTL_WDTCONFIG0_REG);
regval = getreg32(DR_REG_BB_BASE + 0x48); /* DR_REG_BB_BASE+48 */
regval &= ~(1 << 14);
putreg32(regval, DR_REG_BB_BASE + 0x48);
/* Make sure that normal interrupts are disabled. This is really only an
* issue when we are started in un-usual ways (such as from IRAM). In this
* case, we can at least defer some unexpected interrupts left over from
* the last program execution.
*/
up_irq_disable();
/* Set CPU frequency configured in board.h */
esp32s2_clockconfig();
esp32s2_lowsetup();
#ifdef USE_EARLYSERIALINIT
/* Perform early serial initialization */
xtensa_earlyserialinit();
#endif
#ifdef CONFIG_STACK_COLORATION
{
register uint32_t *ptr;
register int i;
/* If stack debug is enabled, then fill the stack with a recognizable
* value that we can use later to test for high water marks.
*/
for (i = 0, ptr = g_idlestack; i < IDLETHREAD_STACKWORDS; i++)
{
*ptr++ = STACK_COLOR;
}
}
#endif
/* Move the stack to a known location. Although we were given a stack
* pointer at start-up, we don't know where that stack pointer is
* positioned with respect to our memory map. The only safe option is to
* switch to a well-known IDLE thread stack.
*/
sp = (uint32_t)g_idlestack + IDLETHREAD_STACKSIZE;
__asm__ __volatile__("mov sp, %0\n" : : "r"(sp));
/* Make page 0 access raise an exception */
esp32s2_region_protection();
/* Move CPU0 exception vectors to IRAM */
__asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (&_init_start));
showprogress('A');
/* Set .bss to zero */
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = &_sbss; dest < &_ebss; dest++)
{
*dest = 0;
}
showprogress('B');
/* Initialize onboard resources */
esp32s2_board_initialize();
showprogress('C');
/* Bring up NuttX */
nx_start();
for (; ; ); /* Should not return */
}

54
arch/xtensa/src/esp32s2/esp32s2_start.h Normal file

@ -0,0 +1,54 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_start.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_START_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_START_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_board_initialize
*
* Description:
* Board-specific logic is initialized by calling this function. This
* entry point is called early in the initialization -- after all memory
* has been configured but before any devices have been initialized.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_board_initialize(void);
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_START_H */

54
arch/xtensa/src/esp32s2/esp32s2_systemreset.c Normal file

@ -0,0 +1,54 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_systemreset.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include "xtensa.h"
#include "hardware/esp32s2_rtccntl.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_systemreset
*
* Description:
* Internal reset logic.
*
****************************************************************************/
void up_systemreset(void)
{
putreg32(RTC_CNTL_SW_SYS_RST, RTC_CNTL_OPTIONS0_REG);
/* Wait for the reset */
for (; ; );
}

185
arch/xtensa/src/esp32s2/esp32s2_timerisr.c Normal file

@ -0,0 +1,185 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_timerisr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <arch/xtensa/xtensa_specregs.h>
#include <arch/board/board.h>
#include "clock/clock.h"
#include "xtensa_timer.h"
#include "xtensa.h"
/****************************************************************************
* Private data
****************************************************************************/
static uint32_t g_tick_divisor;
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: xtensa_getcount, xtensa_getcompare, and xtensa_setcompare
*
* Description:
* Lower level operations on Xtensa special registers.
*
****************************************************************************/
/* Return the current value of the cycle count register */
static inline uint32_t xtensa_getcount(void)
{
uint32_t count;
__asm__ __volatile__
(
"rsr %0, CCOUNT" : "=r"(count)
);
return count;
}
/* Return the old value of the compare register */
static inline uint32_t xtensa_getcompare(void)
{
uint32_t compare;
__asm__ __volatile__
(
"rsr %0, %1" : "=r"(compare) : "I"(XT_CCOMPARE)
);
return compare;
}
/* Set the value of the compare register */
static inline void xtensa_setcompare(uint32_t compare)
{
__asm__ __volatile__
(
"wsr %0, %1" : : "r"(compare), "I"(XT_CCOMPARE)
);
}
/****************************************************************************
* Function: esp32s2_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
* Xtensa timers work by comparing a cycle counter with a preset value.
* Once the match occurs an interrupt is generated, and the handler has to
* set a new cycle count into the comparator. To avoid clock drift due to
* interrupt latency, the new cycle count is computed from the old, not the
* time the interrupt was serviced. However if a timer interrupt is ever
* serviced more than one tick late, it is necessary to process multiple
* ticks until the new cycle count is in the future, otherwise the next
* timer interrupt would not occur until after the cycle counter had
* wrapped (2^32 cycles later).
*
****************************************************************************/
static int esp32s2_timerisr(int irq, uint32_t *regs, FAR void *arg)
{
uint32_t divisor;
uint32_t compare;
uint32_t diff;
divisor = g_tick_divisor;
do
{
/* Increment the compare register for the next tick */
compare = xtensa_getcompare();
xtensa_setcompare(compare + divisor);
/* Process one timer tick */
nxsched_process_timer();
/* Check if we are falling behind and need to process multiple timer
* interrupts.
*/
diff = xtensa_getcount() - compare;
}
while (diff >= divisor);
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void up_timer_initialize(void)
{
uint32_t divisor;
uint32_t count;
/* Configured the timer0 as the system timer.
*
* divisor = BOARD_CLOCK_FREQUENCY / ticks_per_sec
*/
divisor = BOARD_CLOCK_FREQUENCY / CLOCKS_PER_SEC;
g_tick_divisor = divisor;
/* Set up periodic timer */
count = xtensa_getcount();
xtensa_setcompare(count + divisor);
/* NOTE: Timer 0 is an internal interrupt source so we do not need to
* attach any peripheral ID to the dedicated CPU interrupt.
*/
/* Attach the timer interrupt */
irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32s2_timerisr, NULL);
/* Enable the timer 0 CPU interrupt. */
up_enable_irq(ESP32S2_CPUINT_TIMER0);
}

395
arch/xtensa/src/esp32s2/esp32s2_user.c Normal file

@ -0,0 +1,395 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_user.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <arch/loadstore.h>
#include <arch/xtensa/core.h>
#include <sys/types.h>
#include <debug.h>
#include "xtensa.h"
/****************************************************************************
* Public Data
****************************************************************************/
#ifdef CONFIG_ARCH_USE_MODULE_TEXT
extern uint32_t _smodtext;
extern uint32_t _emodtext;
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
#ifdef CONFIG_ARCH_USE_MODULE_TEXT
#ifdef CONFIG_ENDIAN_BIG
#error not implemented
#endif
#ifndef CONFIG_BUILD_FLAT
#error permission check not implemented
#endif
/****************************************************************************
* Name: load_uint8
*
* Description:
* Fetch a byte using 32-bit aligned access.
*
****************************************************************************/
static uint8_t load_uint8(const uint8_t *p)
{
const uint32_t *aligned;
uint32_t value;
unsigned int offset;
aligned = (const uint32_t *)(((uintptr_t)p) & ~3);
value = l32i(aligned);
offset = ((uintptr_t)p) & 3;
switch (offset)
{
case 0:
return value & 0xff;
case 1:
return (value >> 8) & 0xff;
case 2:
return (value >> 16) & 0xff;
case 3:
return (value >> 24) & 0xff;
}
/* not reached */
PANIC();
}
/****************************************************************************
* Name: store_uint8
*
* Description:
* Store a byte using 32-bit aligned access.
*
****************************************************************************/
static void store_uint8(uint8_t *p, uint8_t v)
{
uint32_t *aligned;
uint32_t value;
unsigned int offset;
aligned = (uint32_t *)(((uintptr_t)p) & ~3);
value = l32i(aligned);
offset = ((uintptr_t)p) & 3;
switch (offset)
{
case 0:
value = (value & 0xffffff00) | v;
break;
case 1:
value = (value & 0xffff00ff) | (v << 8);
break;
case 2:
value = (value & 0xff00ffff) | (v << 16);
break;
case 3:
value = (value & 0x00ffffff) | (v << 24);
break;
}
s32i(aligned, value);
}
/****************************************************************************
* Name: decode_s8i
*
* Description:
* Decode S8I instruction using 32-bit aligned access.
* Return non-zero on successful decoding.
*
****************************************************************************/
static int decode_s8i(const uint8_t *p, uint8_t *imm8, uint8_t *s,
uint8_t *t)
{
/* 23 16 15 12 11 8 7 4 3 0
* | imm8 |0 1 0 0| s | t |0 0 1 0|
*/
uint8_t b0 = load_uint8(p);
uint8_t b1 = load_uint8(p + 1);
if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0x40)
{
*t = b0 >> 4;
*s = b1 & 0xf;
*imm8 = load_uint8(p + 2);
return 1;
}
return 0;
}
/****************************************************************************
* Name: decode_s16i
*
* Description:
* Decode S16I instruction using 32-bit aligned access.
* Return non-zero on successful decoding.
*
****************************************************************************/
static int decode_s16i(const uint8_t *p, uint8_t *imm8, uint8_t *s,
uint8_t *t)
{
/* 23 16 15 12 11 8 7 4 3 0
* | imm8 |0 1 0 1| s | t |0 0 1 0|
*/
uint8_t b0 = load_uint8(p);
uint8_t b1 = load_uint8(p + 1);
if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0x50)
{
*t = b0 >> 4;
*s = b1 & 0xf;
*imm8 = load_uint8(p + 2);
return 1;
}
return 0;
}
/****************************************************************************
* Name: decode_l8ui
*
* Description:
* Decode L8UI instruction using 32-bit aligned access.
* Return non-zero on successful decoding.
*
****************************************************************************/
static int decode_l8ui(const uint8_t *p, uint8_t *imm8, uint8_t *s,
uint8_t *t)
{
/* 23 16 15 12 11 8 7 4 3 0
* | imm8 |0 0 0 0| s | t |0 0 1 0|
*/
uint8_t b0 = load_uint8(p);
uint8_t b1 = load_uint8(p + 1);
if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0)
{
*t = b0 >> 4;
*s = b1 & 0xf;
*imm8 = load_uint8(p + 2);
return 1;
}
return 0;
}
/****************************************************************************
* Name: decode_l16ui
*
* Description:
* Decode L16UI instruction using 32-bit aligned access.
* Return non-zero on successful decoding.
*
****************************************************************************/
static int decode_l16ui(const uint8_t *p, uint8_t *imm8, uint8_t *s,
uint8_t *t)
{
/* 23 16 15 12 11 8 7 4 3 0
* | imm8 |0 0 0 1| s | t |0 0 1 0|
*/
uint8_t b0 = load_uint8(p);
uint8_t b1 = load_uint8(p + 1);
if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0x10)
{
*t = b0 >> 4;
*s = b1 & 0xf;
*imm8 = load_uint8(p + 2);
return 1;
}
return 0;
}
/****************************************************************************
* Name: advance_pc
*
* Description:
* Advance PC register by the given value.
*
****************************************************************************/
static void advance_pc(uint32_t *regs, int diff)
{
uint32_t nextpc;
/* Advance to the next instruction. */
nextpc = regs[REG_PC] + diff;
#if XCHAL_HAVE_LOOPS
/* See Xtensa ISA 4.3.2.4 Loopback Semantics */
if (regs[REG_LCOUNT] != 0 && nextpc == regs[REG_LEND])
{
regs[REG_LCOUNT]--;
nextpc = regs[REG_LBEG];
}
#endif
regs[REG_PC] = nextpc;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xtensa_user
*
* Description:
* ESP32S2-specific user exception handler.
*
****************************************************************************/
uint32_t *xtensa_user(int exccause, uint32_t *regs)
{
#ifdef CONFIG_ARCH_USE_MODULE_TEXT
/* Emulate byte access for module text.
*
* ESP32S2 only allows word-aligned accesses to the instruction memory
* regions. A non-aligned access raises a LoadStoreErrorCause exception.
* We catch those exception and emulate byte access here because it's
* necessary in a few places during dynamic code loading:
*
* - memcpy as a part of read(2) when loading code from a file system.
* - relocation needs to inspect and modify text.
*
* (thus binfo() is used below)
*/
if (exccause == XCHAL_EXCCAUSE_LOAD_STORE_ERROR &&
(uintptr_t)&_smodtext <= regs[REG_EXCVADDR] &&
(uintptr_t)&_emodtext > regs[REG_EXCVADDR])
{
uint8_t *pc = (uint8_t *)regs[REG_PC];
uint8_t imm8;
uint8_t s;
uint8_t t;
binfo("XCHAL_EXCCAUSE_LOAD_STORE_ERROR at %p, pc=%p\n",
(FAR void *)regs[REG_EXCVADDR],
pc);
if (decode_s8i(pc, &imm8, &s, &t))
{
binfo("Emulating S8I imm8=%u, s=%u (%p), t=%u (%p)\n",
(unsigned int)imm8,
(unsigned int)s,
(void *)regs[REG_A0 + s],
(unsigned int)t,
(void *)regs[REG_A0 + t]);
DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]);
store_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8,
regs[REG_A0 + t]);
advance_pc(regs, 3);
return regs;
}
else if (decode_s16i(pc, &imm8, &s, &t))
{
binfo("Emulating S16I imm8=%u, s=%u (%p), t=%u (%p)\n",
(unsigned int)imm8,
(unsigned int)s,
(void *)regs[REG_A0 + s],
(unsigned int)t,
(void *)regs[REG_A0 + t]);
DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]);
store_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8,
regs[REG_A0 + t]);
store_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8 + 1,
regs[REG_A0 + t] >> 8);
advance_pc(regs, 3);
return regs;
}
else if (decode_l8ui(pc, &imm8, &s, &t))
{
binfo("Emulating L8UI imm8=%u, s=%u (%p), t=%u (%p)\n",
(unsigned int)imm8,
(unsigned int)s,
(void *)regs[REG_A0 + s],
(unsigned int)t,
(void *)regs[REG_A0 + t]);
DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]);
regs[REG_A0 + t] = load_uint8(((uint8_t *)regs[REG_A0 + s]) +
imm8);
advance_pc(regs, 3);
return regs;
}
else if (decode_l16ui(pc, &imm8, &s, &t))
{
binfo("Emulating L16UI imm8=%u, s=%u (%p), t=%u (%p)\n",
(unsigned int)imm8,
(unsigned int)s,
(void *)regs[REG_A0 + s],
(unsigned int)t,
(void *)regs[REG_A0 + t]);
DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]);
uint8_t lo = load_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8);
uint8_t hi = load_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8 + 1);
regs[REG_A0 + t] = (hi << 8) | lo;
advance_pc(regs, 3);
return regs;
}
}
#endif
/* xtensa_user_panic never returns. */
xtensa_user_panic(exccause, regs);
while (1)
{
}
}

780
arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h Normal file

@ -0,0 +1,780 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_AES_H
#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_AES_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32s2_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* AES_KEY_0_REG register
* AES key register 0
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/* AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* Stores AES keys.
*/
#define AES_KEY_0 0xFFFFFFFF
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFF
#define AES_KEY_0_S 0
/* AES_KEY_1_REG register
* AES key register 1
*/
#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
/* AES_KEY_1 : R/W; bitpos: [31:0]; default: 0;
* Stores AES keys.
*/
#define AES_KEY_1 0xFFFFFFFF
#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S)
#define AES_KEY_1_V 0xFFFFFFFF
#define AES_KEY_1_S 0
/* AES_KEY_2_REG register
* AES key register 2
*/
#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
/* AES_KEY_2 : R/W; bitpos: [31:0]; default: 0;
* Stores AES keys.
*/
#define AES_KEY_2 0xFFFFFFFF
#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S)
#define AES_KEY_2_V 0xFFFFFFFF
#define AES_KEY_2_S 0
/* AES_KEY_3_REG register
* AES key register 3
*/
#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
/* AES_KEY_3 : R/W; bitpos: [31:0]; default: 0;
* Stores AES keys.
*/
#define AES_KEY_3 0xFFFFFFFF
#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S)
#define AES_KEY_3_V 0xFFFFFFFF
#define AES_KEY_3_S 0
/* AES_KEY_4_REG register
* AES key register 4
*/
#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
/* AES_KEY_4 : R/W; bitpos: [31:0]; default: 0;
* Stores AES keys.
*/
#define AES_KEY_4 0xFFFFFFFF
#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S)
#define AES_KEY_4_V 0xFFFFFFFF
#define AES_KEY_4_S 0
/* AES_KEY_5_REG register
* AES key register 5
*/
#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
/* AES_KEY_5 : R/W; bitpos: [31:0]; default: 0;
* Stores AES keys.
*/
#define AES_KEY_5 0xFFFFFFFF
#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S)
#define AES_KEY_5_V 0xFFFFFFFF
#define AES_KEY_5_S 0
/* AES_KEY_6_REG register
* AES key register 6
*/
#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
/* AES_KEY_6 : R/W; bitpos: [31:0]; default: 0;
* Stores AES keys.
*/
#define AES_KEY_6 0xFFFFFFFF
#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S)
#define AES_KEY_6_V 0xFFFFFFFF
#define AES_KEY_6_S 0
/* AES_KEY_7_REG register
* AES key register 7
*/
#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
/* AES_KEY_7 : R/W; bitpos: [31:0]; default: 0;
* Stores AES keys.
*/
#define AES_KEY_7 0xFFFFFFFF
#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S)
#define AES_KEY_7_V 0xFFFFFFFF
#define AES_KEY_7_S 0
/* AES_TEXT_IN_0_REG register
* Source data register 0
*/
#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
/* AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* Stores the source data when the AES Accelerator operates in the Typical
* AES working mode.
*/
#define AES_TEXT_IN_0 0xFFFFFFFF
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFF
#define AES_TEXT_IN_0_S 0
/* AES_TEXT_IN_1_REG register
* Source data register 1
*/
#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
/* AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0;
* Stores the source data when the AES Accelerator operates in the Typical
* AES working mode.
*/
#define AES_TEXT_IN_1 0xFFFFFFFF
#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S)
#define AES_TEXT_IN_1_V 0xFFFFFFFF
#define AES_TEXT_IN_1_S 0
/* AES_TEXT_IN_2_REG register
* Source data register 2
*/
#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
/* AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0;
* Stores the source data when the AES Accelerator operates in the Typical
* AES working mode.
*/
#define AES_TEXT_IN_2 0xFFFFFFFF
#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S)
#define AES_TEXT_IN_2_V 0xFFFFFFFF
#define AES_TEXT_IN_2_S 0
/* AES_TEXT_IN_3_REG register
* Source data register 3
*/
#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
/* AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0;
* Stores the source data when the AES Accelerator operates in the Typical
* AES working mode.
*/
#define AES_TEXT_IN_3 0xFFFFFFFF
#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S)
#define AES_TEXT_IN_3_V 0xFFFFFFFF
#define AES_TEXT_IN_3_S 0
/* AES_TEXT_OUT_0_REG register
* Result data register 0
*/
#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
/* AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* Stores the result data when the AES Accelerator operates in the Typical
* AES working mode.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFF
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFF
#define AES_TEXT_OUT_0_S 0
/* AES_TEXT_OUT_1_REG register
* Result data register 1
*/
#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
/* AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0;
* Stores the result data when the AES Accelerator operates in the Typical
* AES working mode.
*/
#define AES_TEXT_OUT_1 0xFFFFFFFF
#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S)
#define AES_TEXT_OUT_1_V 0xFFFFFFFF
#define AES_TEXT_OUT_1_S 0
/* AES_TEXT_OUT_2_REG register
* Result data register 2
*/
#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
/* AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0;
* Stores the result data when the AES Accelerator operates in the Typical
* AES working mode.
*/
#define AES_TEXT_OUT_2 0xFFFFFFFF
#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S)
#define AES_TEXT_OUT_2_V 0xFFFFFFFF
#define AES_TEXT_OUT_2_S 0
/* AES_TEXT_OUT_3_REG register
* Result data register 3
*/
#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
/* AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0;
* Stores the result data when the AES Accelerator operates in the Typical
* AES working mode.
*/
#define AES_TEXT_OUT_3 0xFFFFFFFF
#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S)
#define AES_TEXT_OUT_3_V 0xFFFFFFFF
#define AES_TEXT_OUT_3_S 0
/* AES_MODE_REG register
* AES working mode configuration register
*/
#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
/* AES_MODE : R/W; bitpos: [2:0]; default: 0;
* Defines the operation type of the AES Accelerator operating under the
* Typical AES working mode.
* &
* 0x0(AES_EN_128): AES-EN-128 #
* 0x1(AES_EN_192): AES-EN-192 #
* 0x2(AES_EN_256): AES-EN-256 #
* 0x4(AES_DE_128): AES-DE-128 #
* 0x5(AES_DE_192): AES-DE-192 #
* 0x6(AES_DE_256): AES-DE-256
* &
*/
#define AES_MODE 0x00000007
#define AES_MODE_M (AES_MODE_V << AES_MODE_S)
#define AES_MODE_V 0x00000007
#define AES_MODE_S 0
/* AES_ENDIAN_REG register
* Endian configuration register
*/
#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44)
/* AES_ENDIAN : R/W; bitpos: [5:0]; default: 0;
* Defines the endianness of input and output texts.
* &
* [1:0] key endian #
* [3:2] text_in endian or in_stream endian #
* [5:4] text_out endian or out_stream endian #
* &
*/
#define AES_ENDIAN 0x0000003F
#define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S)
#define AES_ENDIAN_V 0x0000003F
#define AES_ENDIAN_S 0
/* AES_TRIGGER_REG register
* Operation start controlling register
*/
#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
/* AES_TRIGGER : WO; bitpos: [0]; default: 0;
* Set this bit to 1 to start AES operation.
*/
#define AES_TRIGGER (BIT(0))
#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S)
#define AES_TRIGGER_V 0x00000001
#define AES_TRIGGER_S 0
/* AES_STATE_REG register
* Operation status register
*/
#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
/* AES_STATE : RO; bitpos: [1:0]; default: 0;
* Stores the working status of the AES Accelerator. For details, see Table
* 3 for Typical AES working mode and Table 9 for DMA AES working mode.
* For typical AES; 0 = idle; 1 = busy.
* For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done.
*/
#define AES_STATE 0x00000003
#define AES_STATE_M (AES_STATE_V << AES_STATE_S)
#define AES_STATE_V 0x00000003
#define AES_STATE_S 0
/* AES_IV_0_REG register
* initialization vector
*/
#define AES_IV_0_REG (DR_REG_AES_BASE + 0x50)
/* AES_IV_0 : R/W; bitpos: [31:0]; default: 0;
* This register stores the 0th 32-bit piece of 128-bit initialization vector
*/
#define AES_IV_0 0xFFFFFFFF
#define AES_IV_0_M (AES_IV_0_V << AES_IV_0_S)
#define AES_IV_0_V 0xFFFFFFFF
#define AES_IV_0_S 0
/* AES_IV_1_REG register
* initialization vector
*/
#define AES_IV_1_REG (DR_REG_AES_BASE + 0x54)
/* AES_IV_1 : R/W; bitpos: [31:0]; default: 0;
* This register stores the 1th 32-bit piece of 128-bit initialization vector
*/
#define AES_IV_1 0xFFFFFFFF
#define AES_IV_1_M (AES_IV_1_V << AES_IV_1_S)
#define AES_IV_1_V 0xFFFFFFFF
#define AES_IV_1_S 0
/* AES_IV_2_REG register
* initialization vector
*/
#define AES_IV_2_REG (DR_REG_AES_BASE + 0x58)
/* AES_IV_2 : R/W; bitpos: [31:0]; default: 0;
* This register stores the 2th 32-bit piece of 128-bit initialization vector
*/
#define AES_IV_2 0xFFFFFFFF
#define AES_IV_2_M (AES_IV_2_V << AES_IV_2_S)
#define AES_IV_2_V 0xFFFFFFFF
#define AES_IV_2_S 0
/* AES_IV_3_REG register
* initialization vector
*/
#define AES_IV_3_REG (DR_REG_AES_BASE + 0x5c)
/* AES_IV_3 : R/W; bitpos: [31:0]; default: 0;
* This register stores the 3th 32-bit piece of 128-bit initialization vector
*/
#define AES_IV_3 0xFFFFFFFF
#define AES_IV_3_M (AES_IV_3_V << AES_IV_3_S)
#define AES_IV_3_V 0xFFFFFFFF
#define AES_IV_3_S 0
/* AES_H_0_REG register
* GCM hash subkey
*/
#define AES_H_0_REG (DR_REG_AES_BASE + 0x60)
/* AES_H_0 : RO; bitpos: [31:0]; default: 0;
* GCM hash subkey
*/
#define AES_H_0 0xFFFFFFFF
#define AES_H_0_M (AES_H_0_V << AES_H_0_S)
#define AES_H_0_V 0xFFFFFFFF
#define AES_H_0_S 0
/* AES_H_1_REG register
* GCM hash subkey
*/
#define AES_H_1_REG (DR_REG_AES_BASE + 0x64)
/* AES_H_1 : RO; bitpos: [31:0]; default: 0;
* GCM hash subkey
*/
#define AES_H_1 0xFFFFFFFF
#define AES_H_1_M (AES_H_1_V << AES_H_1_S)
#define AES_H_1_V 0xFFFFFFFF
#define AES_H_1_S 0
/* AES_H_2_REG register
* GCM hash subkey
*/
#define AES_H_2_REG (DR_REG_AES_BASE + 0x68)
/* AES_H_2 : RO; bitpos: [31:0]; default: 0;
* GCM hash subkey
*/
#define AES_H_2 0xFFFFFFFF
#define AES_H_2_M (AES_H_2_V << AES_H_2_S)
#define AES_H_2_V 0xFFFFFFFF
#define AES_H_2_S 0
/* AES_H_3_REG register
* GCM hash subkey
*/
#define AES_H_3_REG (DR_REG_AES_BASE + 0x6c)
/* AES_H_3 : RO; bitpos: [31:0]; default: 0;
* GCM hash subkey
*/
#define AES_H_3 0xFFFFFFFF
#define AES_H_3_M (AES_H_3_V << AES_H_3_S)
#define AES_H_3_V 0xFFFFFFFF
#define AES_H_3_S 0
/* AES_J0_0_REG register
* J0
*/
#define AES_J0_0_REG (DR_REG_AES_BASE + 0x70)
/* AES_J0_0 : R/W; bitpos: [31:0]; default: 0;
* This register stores the 0th 32-bit piece of 128-bit J0
*/
#define AES_J0_0 0xFFFFFFFF
#define AES_J0_0_M (AES_J0_0_V << AES_J0_0_S)
#define AES_J0_0_V 0xFFFFFFFF
#define AES_J0_0_S 0
/* AES_J0_1_REG register
* J0
*/
#define AES_J0_1_REG (DR_REG_AES_BASE + 0x74)
/* AES_J0_1 : R/W; bitpos: [31:0]; default: 0;
* This register stores the 1th 32-bit piece of 128-bit J0
*/
#define AES_J0_1 0xFFFFFFFF
#define AES_J0_1_M (AES_J0_1_V << AES_J0_1_S)
#define AES_J0_1_V 0xFFFFFFFF
#define AES_J0_1_S 0
/* AES_J0_2_REG register
* J0
*/
#define AES_J0_2_REG (DR_REG_AES_BASE + 0x78)
/* AES_J0_2 : R/W; bitpos: [31:0]; default: 0;
* This register stores the 2th 32-bit piece of 128-bit J0
*/
#define AES_J0_2 0xFFFFFFFF
#define AES_J0_2_M (AES_J0_2_V << AES_J0_2_S)
#define AES_J0_2_V 0xFFFFFFFF
#define AES_J0_2_S 0
/* AES_J0_3_REG register
* J0
*/
#define AES_J0_3_REG (DR_REG_AES_BASE + 0x7c)
/* AES_J0_3 : R/W; bitpos: [31:0]; default: 0;
* This register stores the 3th 32-bit piece of 128-bit J0
*/
#define AES_J0_3 0xFFFFFFFF
#define AES_J0_3_M (AES_J0_3_V << AES_J0_3_S)
#define AES_J0_3_V 0xFFFFFFFF
#define AES_J0_3_S 0
/* AES_T0_0_REG register
* T0
*/
#define AES_T0_0_REG (DR_REG_AES_BASE + 0x80)
/* AES_T0_0 : RO; bitpos: [31:0]; default: 0;
* This register stores the 0th 32-bit piece of 128-bit T0
*/
#define AES_T0_0 0xFFFFFFFF
#define AES_T0_0_M (AES_T0_0_V << AES_T0_0_S)
#define AES_T0_0_V 0xFFFFFFFF
#define AES_T0_0_S 0
/* AES_T0_1_REG register
* T0
*/
#define AES_T0_1_REG (DR_REG_AES_BASE + 0x84)
/* AES_T0_1 : RO; bitpos: [31:0]; default: 0;
* This register stores the 1th 32-bit piece of 128-bit T0
*/
#define AES_T0_1 0xFFFFFFFF
#define AES_T0_1_M (AES_T0_1_V << AES_T0_1_S)
#define AES_T0_1_V 0xFFFFFFFF
#define AES_T0_1_S 0
/* AES_T0_2_REG register
* T0
*/
#define AES_T0_2_REG (DR_REG_AES_BASE + 0x88)
/* AES_T0_2 : RO; bitpos: [31:0]; default: 0;
* This register stores the 2th 32-bit piece of 128-bit T0
*/
#define AES_T0_2 0xFFFFFFFF
#define AES_T0_2_M (AES_T0_2_V << AES_T0_2_S)
#define AES_T0_2_V 0xFFFFFFFF
#define AES_T0_2_S 0
/* AES_T0_3_REG register
* T0
*/
#define AES_T0_3_REG (DR_REG_AES_BASE + 0x8c)
/* AES_T0_3 : RO; bitpos: [31:0]; default: 0;
* This register stores the 3th 32-bit piece of 128-bit T0
*/
#define AES_T0_3 0xFFFFFFFF
#define AES_T0_3_M (AES_T0_3_V << AES_T0_3_S)
#define AES_T0_3_V 0xFFFFFFFF
#define AES_T0_3_S 0
/* AES_DMA_ENABLE_REG register
* DMA enable register
*/
#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
/* AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
* Defines the working mode of the AES Accelerator. For details, see Table 1.
* 1'h0: typical AES operation
* 1'h1: DMA-AES operation
*/
#define AES_DMA_ENABLE (BIT(0))
#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
#define AES_DMA_ENABLE_V 0x00000001
#define AES_DMA_ENABLE_S 0
/* AES_BLOCK_MODE_REG register
* Block operation type register
*/
#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
/* AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
* Defines the operation type of the AES Accelerator operating under the
* DMA-AES working mode. For details, see Table 8.
* &
* 3'h0(BLOCK_MODE_ECB): ECB #
* 3'h1(BLOCK_MODE_CBC): CBC #
* 3'h2(BLOCK_MODE_OFB): OFB #
* 3'h3(BLOCK_MODE_CTR): CTR #
* 3'h4(BLOCK_MODE_CFB8): CFB-8 #
* 3'h5(BLOCK_MODE_CFB128): CFB-128 #
* 3'h6(BLOCK_MODE_GCM): GCM
* &
*/
#define AES_BLOCK_MODE 0x00000007
#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
#define AES_BLOCK_MODE_V 0x00000007
#define AES_BLOCK_MODE_S 0
/* AES_BLOCK_NUM_REG register
* Block number configuration register
*/
#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
/* AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Stores the Block Number of plaintext or cipertext when the AES
* Accelerator operates under the DMA-AES working mode. For details, see
* Section 1.5.4.
*/
#define AES_BLOCK_NUM 0xFFFFFFFF
#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
#define AES_BLOCK_NUM_V 0xFFFFFFFF
#define AES_BLOCK_NUM_S 0
/* AES_INC_SEL_REG register
* Standard incrementing function register
*/
#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
/* AES_INC_SEL : R/W; bitpos: [0]; default: 0;
* Defines the Standard Incrementing Function for CTR block operation. Set
* this bit to 0 or 1 to choose INC 32 or INC 128 .
*/
#define AES_INC_SEL (BIT(0))
#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S)
#define AES_INC_SEL_V 0x00000001
#define AES_INC_SEL_S 0
/* AES_AAD_BLOCK_NUM_REG register
* AAD block number configuration register
*/
#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0)
/* AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Stores the ADD Block Number for the GCM operation.
*/
#define AES_AAD_BLOCK_NUM 0xFFFFFFFF
#define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S)
#define AES_AAD_BLOCK_NUM_V 0xFFFFFFFF
#define AES_AAD_BLOCK_NUM_S 0
/* AES_REMAINDER_BIT_NUM_REG register
* Remainder bit number of plaintext/ciphertext
*/
#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4)
/* AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0;
* Stores the Remainder Bit Number for the GCM operation.
*/
#define AES_REMAINDER_BIT_NUM 0x0000007F
#define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S)
#define AES_REMAINDER_BIT_NUM_V 0x0000007F
#define AES_REMAINDER_BIT_NUM_S 0
/* AES_CONTINUE_REG register
* Operation continue controlling register
*/
#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8)
/* AES_CONTINUE : WO; bitpos: [0]; default: 0;
* Set this bit to 1 to continue AES operation.
*/
#define AES_CONTINUE (BIT(0))
#define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S)
#define AES_CONTINUE_V 0x00000001
#define AES_CONTINUE_S 0
/* AES_INT_CLR_REG register
* DMA-AES interrupt clear register
*/
#define AES_INT_CLR_REG (DR_REG_AES_BASE + 0xac)
/* AES_INT_CLR : WO; bitpos: [0]; default: 0;
* Set this bit to 1 to clear AES interrupt.
*/
#define AES_INT_CLR (BIT(0))
#define AES_INT_CLR_M (AES_INT_CLR_V << AES_INT_CLR_S)
#define AES_INT_CLR_V 0x00000001
#define AES_INT_CLR_S 0
/* AES_INT_ENA_REG register
* DMA-AES interrupt enable register
*/
#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
/* AES_INT_ENA : R/W; bitpos: [0]; default: 0;
* Set this bit to 1 to enable AES interrupt and 0 to disable interrupt.
*/
#define AES_INT_ENA (BIT(0))
#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S)
#define AES_INT_ENA_V 0x00000001
#define AES_INT_ENA_S 0
/* AES_DATE_REG register
* Version control register
*/
#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
/* AES_DATE : R/W; bitpos: [29:0]; default: 538510612;
* Version control register
*/
#define AES_DATE 0x3FFFFFFF
#define AES_DATE_M (AES_DATE_V << AES_DATE_S)
#define AES_DATE_V 0x3FFFFFFF
#define AES_DATE_S 0
/* AES_DMA_EXIT_REG register
* Operation exit controlling register
*/
#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
/* AES_DMA_EXIT : WO; bitpos: [0]; default: 0;
* Set this bit to 1 to exit AES operation. This register is only effective
* for DMA-AES operation.
*/
#define AES_DMA_EXIT (BIT(0))
#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
#define AES_DMA_EXIT_V 0x00000001
#define AES_DMA_EXIT_S 0
#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_AES_H */

3282
arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h Normal file

File diff suppressed because it is too large Load Diff

16494
arch/xtensa/src/esp32s2/hardware/esp32s2_gpio.h Normal file

File diff suppressed because it is too large Load Diff

327
arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h Normal file

@ -0,0 +1,327 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_SIGMAP_H
#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_SIGMAP_H
#define SPICLK_OUT_IDX SPICLK_OUT_MUX_IDX
#define CLK_I2S_IDX CLK_I2S_MUX_IDX
#define FSPICLK_OUT_IDX FSPICLK_OUT_MUX_IDX
#define SPIQ_IN_IDX 0
#define SPIQ_OUT_IDX 0
#define SPID_IN_IDX 1
#define SPID_OUT_IDX 1
#define SPIHD_IN_IDX 2
#define SPIHD_OUT_IDX 2
#define SPIWP_IN_IDX 3
#define SPIWP_OUT_IDX 3
#define SPICLK_OUT_MUX_IDX 4
#define SPICS0_OUT_IDX 5
#define SPICS1_OUT_IDX 6
#define SPID4_IN_IDX 7
#define SPID4_OUT_IDX 7
#define SPID5_IN_IDX 8
#define SPID5_OUT_IDX 8
#define SPID6_IN_IDX 9
#define SPID6_OUT_IDX 9
#define SPID7_IN_IDX 10
#define SPID7_OUT_IDX 10
#define SPIDQS_IN_IDX 11
#define SPIDQS_OUT_IDX 11
#define U0RXD_IN_IDX 14
#define U0TXD_OUT_IDX 14
#define U0CTS_IN_IDX 15
#define U0RTS_OUT_IDX 15
#define U0DSR_IN_IDX 16
#define U0DTR_OUT_IDX 16
#define U1RXD_IN_IDX 17
#define U1TXD_OUT_IDX 17
#define U1CTS_IN_IDX 18
#define U1RTS_OUT_IDX 18
#define U1DSR_IN_IDX 21
#define U1DTR_OUT_IDX 21
#define I2S0O_BCK_IN_IDX 23
#define I2S0O_BCK_OUT_IDX 23
#define I2S0O_WS_IN_IDX 25
#define I2S0O_WS_OUT_IDX 25
#define I2S0I_BCK_IN_IDX 27
#define I2S0I_BCK_OUT_IDX 27
#define I2S0I_WS_IN_IDX 28
#define I2S0I_WS_OUT_IDX 28
#define I2CEXT0_SCL_IN_IDX 29
#define I2CEXT0_SCL_OUT_IDX 29
#define I2CEXT0_SDA_IN_IDX 30
#define I2CEXT0_SDA_OUT_IDX 30
#define SDIO_TOHOST_INT_OUT_IDX 31
#define GPIO_BT_ACTIVE_IDX 37
#define GPIO_BT_PRIORITY_IDX 38
#define PCNT_SIG_CH0_IN0_IDX 39
#define GPIO_WLAN_PRIO_IDX 39
#define PCNT_SIG_CH1_IN0_IDX 40
#define GPIO_WLAN_ACTIVE_IDX 40
#define PCNT_CTRL_CH0_IN0_IDX 41
#define BB_DIAG0_IDX 41
#define PCNT_CTRL_CH1_IN0_IDX 42
#define BB_DIAG1_IDX 42
#define PCNT_SIG_CH0_IN1_IDX 43
#define BB_DIAG2_IDX 43
#define PCNT_SIG_CH1_IN1_IDX 44
#define BB_DIAG3_IDX 44
#define PCNT_CTRL_CH0_IN1_IDX 45
#define BB_DIAG4_IDX 45
#define PCNT_CTRL_CH1_IN1_IDX 46
#define BB_DIAG5_IDX 46
#define PCNT_SIG_CH0_IN2_IDX 47
#define BB_DIAG6_IDX 47
#define PCNT_SIG_CH1_IN2_IDX 48
#define BB_DIAG7_IDX 48
#define PCNT_CTRL_CH0_IN2_IDX 49
#define BB_DIAG8_IDX 49
#define PCNT_CTRL_CH1_IN2_IDX 50
#define BB_DIAG9_IDX 50
#define PCNT_SIG_CH0_IN3_IDX 51
#define BB_DIAG10_IDX 51
#define PCNT_SIG_CH1_IN3_IDX 52
#define BB_DIAG11_IDX 52
#define PCNT_CTRL_CH0_IN3_IDX 53
#define BB_DIAG12_IDX 53
#define PCNT_CTRL_CH1_IN3_IDX 54
#define BB_DIAG13_IDX 54
#define BB_DIAG14_IDX 55
#define BB_DIAG15_IDX 56
#define BB_DIAG16_IDX 57
#define BB_DIAG17_IDX 58
#define BB_DIAG18_IDX 59
#define BB_DIAG19_IDX 60
#define USB_EXTPHY_VP_IDX 61
#define USB_EXTPHY_OEN_IDX 61
#define USB_EXTPHY_VM_IDX 62
#define USB_EXTPHY_SPEED_IDX 62
#define USB_EXTPHY_RCV_IDX 63
#define USB_EXTPHY_VPO_IDX 63
#define USB_OTG_IDDIG_IN_IDX 64
#define USB_EXTPHY_VMO_IDX 64
#define USB_OTG_AVALID_IN_IDX 65
#define USB_EXTPHY_SUSPND_IDX 65
#define USB_SRP_BVALID_IN_IDX 66
#define USB_OTG_IDPULLUP_IDX 66
#define USB_OTG_VBUSVALID_IN_IDX 67
#define USB_OTG_DPPULLDOWN_IDX 67
#define USB_SRP_SESSEND_IN_IDX 68
#define USB_OTG_DMPULLDOWN_IDX 68
#define USB_OTG_DRVVBUS_IDX 69
#define USB_SRP_CHRGVBUS_IDX 70
#define USB_SRP_DISCHRGVBUS_IDX 71
#define SPI3_CLK_IN_IDX 72
#define SPI3_CLK_OUT_MUX_IDX 72
#define SPI3_Q_IN_IDX 73
#define SPI3_Q_OUT_IDX 73
#define SPI3_D_IN_IDX 74
#define SPI3_D_OUT_IDX 74
#define SPI3_HD_IN_IDX 75
#define SPI3_HD_OUT_IDX 75
#define SPI3_CS0_IN_IDX 76
#define SPI3_CS0_OUT_IDX 76
#define SPI3_CS1_OUT_IDX 77
#define SPI3_CS2_OUT_IDX 78
#define LEDC_LS_SIG_OUT0_IDX 79
#define LEDC_LS_SIG_OUT1_IDX 80
#define LEDC_LS_SIG_OUT2_IDX 81
#define LEDC_LS_SIG_OUT3_IDX 82
#define RMT_SIG_IN0_IDX 83
#define LEDC_LS_SIG_OUT4_IDX 83
#define RMT_SIG_IN1_IDX 84
#define LEDC_LS_SIG_OUT5_IDX 84
#define RMT_SIG_IN2_IDX 85
#define LEDC_LS_SIG_OUT6_IDX 85
#define RMT_SIG_IN3_IDX 86
#define LEDC_LS_SIG_OUT7_IDX 86
#define RMT_SIG_OUT0_IDX 87
#define RMT_SIG_OUT1_IDX 88
#define RMT_SIG_OUT2_IDX 89
#define RMT_SIG_OUT3_IDX 90
#define EXT_ADC_START_IDX 93
#define I2CEXT1_SCL_IN_IDX 95
#define I2CEXT1_SCL_OUT_IDX 95
#define I2CEXT1_SDA_IN_IDX 96
#define I2CEXT1_SDA_OUT_IDX 96
#define GPIO_SD0_OUT_IDX 100
#define GPIO_SD1_OUT_IDX 101
#define GPIO_SD2_OUT_IDX 102
#define GPIO_SD3_OUT_IDX 103
#define GPIO_SD4_OUT_IDX 104
#define GPIO_SD5_OUT_IDX 105
#define GPIO_SD6_OUT_IDX 106
#define GPIO_SD7_OUT_IDX 107
#define FSPICLK_IN_IDX 108
#define FSPICLK_OUT_MUX_IDX 108
#define FSPIQ_IN_IDX 109
#define FSPIQ_OUT_IDX 109
#define FSPID_IN_IDX 110
#define FSPID_OUT_IDX 110
#define FSPIHD_IN_IDX 111
#define FSPIHD_OUT_IDX 111
#define FSPIWP_IN_IDX 112
#define FSPIWP_OUT_IDX 112
#define FSPIIO4_IN_IDX 113
#define FSPIIO4_OUT_IDX 113
#define FSPIIO5_IN_IDX 114
#define FSPIIO5_OUT_IDX 114
#define FSPIIO6_IN_IDX 115
#define FSPIIO6_OUT_IDX 115
#define FSPIIO7_IN_IDX 116
#define FSPIIO7_OUT_IDX 116
#define FSPICS0_IN_IDX 117
#define FSPICS0_OUT_IDX 117
#define FSPICS1_OUT_IDX 118
#define FSPICS2_OUT_IDX 119
#define FSPICS3_OUT_IDX 120
#define FSPICS4_OUT_IDX 121
#define FSPICS5_OUT_IDX 122
#define TWAI_RX_IDX 123
#define TWAI_TX_IDX 123
#define TWAI_BUS_OFF_ON_IDX 124
#define TWAI_CLKOUT_IDX 125
#define SUBSPICLK_OUT_MUX_IDX 126
#define SUBSPIQ_IN_IDX 127
#define SUBSPIQ_OUT_IDX 127
#define SUBSPID_IN_IDX 128
#define SUBSPID_OUT_IDX 128
#define SUBSPIHD_IN_IDX 129
#define SUBSPIHD_OUT_IDX 129
#define SUBSPIWP_IN_IDX 130
#define SUBSPIWP_OUT_IDX 130
#define SUBSPICS0_OUT_IDX 131
#define SUBSPICS1_OUT_IDX 132
#define FSPIDQS_OUT_IDX 133
#define FSPI_HSYNC_OUT_IDX 134
#define FSPI_VSYNC_OUT_IDX 135
#define FSPI_DE_OUT_IDX 136
#define FSPICD_OUT_IDX 137
#define SPI3_CD_OUT_IDX 139
#define SPI3_DQS_OUT_IDX 140
#define I2S0I_DATA_IN0_IDX 143
#define I2S0O_DATA_OUT0_IDX 143
#define I2S0I_DATA_IN1_IDX 144
#define I2S0O_DATA_OUT1_IDX 144
#define I2S0I_DATA_IN2_IDX 145
#define I2S0O_DATA_OUT2_IDX 145
#define I2S0I_DATA_IN3_IDX 146
#define I2S0O_DATA_OUT3_IDX 146
#define I2S0I_DATA_IN4_IDX 147
#define I2S0O_DATA_OUT4_IDX 147
#define I2S0I_DATA_IN5_IDX 148
#define I2S0O_DATA_OUT5_IDX 148
#define I2S0I_DATA_IN6_IDX 149
#define I2S0O_DATA_OUT6_IDX 149
#define I2S0I_DATA_IN7_IDX 150
#define I2S0O_DATA_OUT7_IDX 150
#define I2S0I_DATA_IN8_IDX 151
#define I2S0O_DATA_OUT8_IDX 151
#define I2S0I_DATA_IN9_IDX 152
#define I2S0O_DATA_OUT9_IDX 152
#define I2S0I_DATA_IN10_IDX 153
#define I2S0O_DATA_OUT10_IDX 153
#define I2S0I_DATA_IN11_IDX 154
#define I2S0O_DATA_OUT11_IDX 154
#define I2S0I_DATA_IN12_IDX 155
#define I2S0O_DATA_OUT12_IDX 155
#define I2S0I_DATA_IN13_IDX 156
#define I2S0O_DATA_OUT13_IDX 156
#define I2S0I_DATA_IN14_IDX 157
#define I2S0O_DATA_OUT14_IDX 157
#define I2S0I_DATA_IN15_IDX 158
#define I2S0O_DATA_OUT15_IDX 158
#define I2S0O_DATA_OUT16_IDX 159
#define I2S0O_DATA_OUT17_IDX 160
#define I2S0O_DATA_OUT18_IDX 161
#define I2S0O_DATA_OUT19_IDX 162
#define I2S0O_DATA_OUT20_IDX 163
#define I2S0O_DATA_OUT21_IDX 164
#define I2S0O_DATA_OUT22_IDX 165
#define I2S0O_DATA_OUT23_IDX 166
#define SUBSPID4_IN_IDX 167
#define SUBSPID4_OUT_IDX 167
#define SUBSPID5_IN_IDX 168
#define SUBSPID5_OUT_IDX 168
#define SUBSPID6_IN_IDX 169
#define SUBSPID6_OUT_IDX 169
#define SUBSPID7_IN_IDX 170
#define SUBSPID7_OUT_IDX 170
#define SUBSPIDQS_IN_IDX 171
#define SUBSPIDQS_OUT_IDX 171
#define I2S0I_H_SYNC_IDX 193
#define I2S0I_V_SYNC_IDX 194
#define I2S0I_H_ENABLE_IDX 195
#define PCMFSYNC_IN_IDX 203
#define BT_AUDIO0_IRQ_IDX 203
#define PCMCLK_IN_IDX 204
#define BT_AUDIO1_IRQ_IDX 204
#define PCMDIN_IDX 205
#define BT_AUDIO2_IRQ_IDX 205
#define RW_WAKEUP_REQ_IDX 206
#define BLE_AUDIO0_IRQ_IDX 206
#define BLE_AUDIO1_IRQ_IDX 207
#define BLE_AUDIO2_IRQ_IDX 208
#define PCMFSYNC_OUT_IDX 209
#define PCMCLK_OUT_IDX 210
#define PCMDOUT_IDX 211
#define BLE_AUDIO_SYNC0_P_IDX 212
#define BLE_AUDIO_SYNC1_P_IDX 213
#define BLE_AUDIO_SYNC2_P_IDX 214
#define ANT_SEL0_IDX 215
#define ANT_SEL1_IDX 216
#define ANT_SEL2_IDX 217
#define ANT_SEL3_IDX 218
#define ANT_SEL4_IDX 219
#define ANT_SEL5_IDX 220
#define ANT_SEL6_IDX 221
#define ANT_SEL7_IDX 222
#define SIG_IN_FUNC_223_IDX 223
#define SIG_IN_FUNC223_IDX 223
#define SIG_IN_FUNC_224_IDX 224
#define SIG_IN_FUNC224_IDX 224
#define SIG_IN_FUNC_225_IDX 225
#define SIG_IN_FUNC225_IDX 225
#define SIG_IN_FUNC_226_IDX 226
#define SIG_IN_FUNC226_IDX 226
#define SIG_IN_FUNC_227_IDX 227
#define SIG_IN_FUNC227_IDX 227
#define PRO_ALONEGPIO_IN0_IDX 235
#define PRO_ALONEGPIO_OUT0_IDX 235
#define PRO_ALONEGPIO_IN1_IDX 236
#define PRO_ALONEGPIO_OUT1_IDX 236
#define PRO_ALONEGPIO_IN2_IDX 237
#define PRO_ALONEGPIO_OUT2_IDX 237
#define PRO_ALONEGPIO_IN3_IDX 238
#define PRO_ALONEGPIO_OUT3_IDX 238
#define PRO_ALONEGPIO_IN4_IDX 239
#define PRO_ALONEGPIO_OUT4_IDX 239
#define PRO_ALONEGPIO_IN5_IDX 240
#define PRO_ALONEGPIO_OUT5_IDX 240
#define PRO_ALONEGPIO_IN6_IDX 241
#define PRO_ALONEGPIO_OUT6_IDX 241
#define PRO_ALONEGPIO_IN7_IDX 242
#define PRO_ALONEGPIO_OUT7_IDX 242
#define CLK_I2S_MUX_IDX 251
#define SIG_GPIO_OUT_IDX 256
#define GPIO_MAP_DATE_IDX 0x1904100
#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_SIGMAP_H */

191
arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h Normal file

@ -0,0 +1,191 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H
#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H
/**
* Register definitions for digital PLL (BBPLL)
*
* This file lists register fields of BBPLL, located on an internal
* configuration bus. These definitions are used via macros defined in
* regi2c_ctrl.h, by rtc_clk_cpu_freq_set function in rtc_clk.c.
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 1
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
#define I2C_BBPLL_IR_CAL_CK_DIV 0
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3
#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
#define I2C_BBPLL_IR_CAL_ENX_CAP 1
#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4
#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4
#define I2C_BBPLL_IR_CAL_RSTB 1
#define I2C_BBPLL_IR_CAL_RSTB_MSB 5
#define I2C_BBPLL_IR_CAL_RSTB_LSB 5
#define I2C_BBPLL_IR_CAL_START 1
#define I2C_BBPLL_IR_CAL_START_MSB 6
#define I2C_BBPLL_IR_CAL_START_LSB 6
#define I2C_BBPLL_IR_CAL_UNSTOP 1
#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7
#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7
#define I2C_BBPLL_OC_REF_DIV 2
#define I2C_BBPLL_OC_REF_DIV_MSB 3
#define I2C_BBPLL_OC_REF_DIV_LSB 0
#define I2C_BBPLL_OC_DCHGP 2
#define I2C_BBPLL_OC_DCHGP_MSB 6
#define I2C_BBPLL_OC_DCHGP_LSB 4
#define I2C_BBPLL_OC_ENB_FCAL 2
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
#define I2C_BBPLL_OC_DIV_7_0 3
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
#define I2C_BBPLL_RSTB_DIV_ADC 4
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
#define I2C_BBPLL_MODE_HF 4
#define I2C_BBPLL_MODE_HF_MSB 1
#define I2C_BBPLL_MODE_HF_LSB 1
#define I2C_BBPLL_DIV_ADC 4
#define I2C_BBPLL_DIV_ADC_MSB 3
#define I2C_BBPLL_DIV_ADC_LSB 2
#define I2C_BBPLL_DIV_DAC 4
#define I2C_BBPLL_DIV_DAC_MSB 4
#define I2C_BBPLL_DIV_DAC_LSB 4
#define I2C_BBPLL_DIV_CPU 4
#define I2C_BBPLL_DIV_CPU_MSB 5
#define I2C_BBPLL_DIV_CPU_LSB 5
#define I2C_BBPLL_OC_ENB_VCON 4
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
#define I2C_BBPLL_OC_TSCHGP 4
#define I2C_BBPLL_OC_TSCHGP_MSB 7
#define I2C_BBPLL_OC_TSCHGP_LSB 7
#define I2C_BBPLL_OC_DR1 5
#define I2C_BBPLL_OC_DR1_MSB 2
#define I2C_BBPLL_OC_DR1_LSB 0
#define I2C_BBPLL_OC_DR3 5
#define I2C_BBPLL_OC_DR3_MSB 6
#define I2C_BBPLL_OC_DR3_LSB 4
#define I2C_BBPLL_EN_USB 5
#define I2C_BBPLL_EN_USB_MSB 7
#define I2C_BBPLL_EN_USB_LSB 7
#define I2C_BBPLL_OC_DCUR 6
#define I2C_BBPLL_OC_DCUR_MSB 2
#define I2C_BBPLL_OC_DCUR_LSB 0
#define I2C_BBPLL_INC_CUR 6
#define I2C_BBPLL_INC_CUR_MSB 3
#define I2C_BBPLL_INC_CUR_LSB 3
#define I2C_BBPLL_OC_DHREF_SEL 6
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
#define I2C_BBPLL_OC_DLREF_SEL 6
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
#define I2C_BBPLL_OR_CAL_CAP 8
#define I2C_BBPLL_OR_CAL_CAP_MSB 3
#define I2C_BBPLL_OR_CAL_CAP_LSB 0
#define I2C_BBPLL_OR_CAL_UDF 8
#define I2C_BBPLL_OR_CAL_UDF_MSB 4
#define I2C_BBPLL_OR_CAL_UDF_LSB 4
#define I2C_BBPLL_OR_CAL_OVF 8
#define I2C_BBPLL_OR_CAL_OVF_MSB 5
#define I2C_BBPLL_OR_CAL_OVF_LSB 5
#define I2C_BBPLL_OR_CAL_END 8
#define I2C_BBPLL_OR_CAL_END_MSB 6
#define I2C_BBPLL_OR_CAL_END_LSB 6
#define I2C_BBPLL_OR_LOCK 8
#define I2C_BBPLL_OR_LOCK_MSB 7
#define I2C_BBPLL_OR_LOCK_LSB 7
#define I2C_BBPLL_BBADC_DELAY1 9
#define I2C_BBPLL_BBADC_DELAY1_MSB 1
#define I2C_BBPLL_BBADC_DELAY1_LSB 0
#define I2C_BBPLL_BBADC_DELAY2 9
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
#define I2C_BBPLL_BBADC_DVDD 9
#define I2C_BBPLL_BBADC_DVDD_MSB 5
#define I2C_BBPLL_BBADC_DVDD_LSB 4
#define I2C_BBPLL_BBADC_DREF 9
#define I2C_BBPLL_BBADC_DREF_MSB 7
#define I2C_BBPLL_BBADC_DREF_LSB 6
#define I2C_BBPLL_BBADC_DCUR 10
#define I2C_BBPLL_BBADC_DCUR_MSB 1
#define I2C_BBPLL_BBADC_DCUR_LSB 0
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
#define I2C_BBPLL_ENT_PLL 10
#define I2C_BBPLL_ENT_PLL_MSB 3
#define I2C_BBPLL_ENT_PLL_LSB 3
#define I2C_BBPLL_DTEST 10
#define I2C_BBPLL_DTEST_MSB 5
#define I2C_BBPLL_DTEST_LSB 4
#define I2C_BBPLL_ENT_ADC 10
#define I2C_BBPLL_ENT_ADC_MSB 7
#define I2C_BBPLL_ENT_ADC_LSB 6
#endif

2229
arch/xtensa/src/esp32s2/hardware/esp32s2_i2s.h Normal file

File diff suppressed because it is too large Load Diff

1647
arch/xtensa/src/esp32s2/hardware/esp32s2_interrupt.h Normal file

File diff suppressed because it is too large Load Diff

460
arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h Normal file

@ -0,0 +1,460 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_IOMUM_H
#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_IOMUM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32s2_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers
* Output enable in sleep mode
*/
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1))
#define SLP_SEL_V 1
#define SLP_SEL_S 1
/* Pulldown enable in sleep mode */
#define SLP_PD (BIT(2))
#define SLP_PD_M (BIT(2))
#define SLP_PD_V 1
#define SLP_PD_S 2
/* Pullup enable in sleep mode */
#define SLP_PU (BIT(3))
#define SLP_PU_M (BIT(3))
#define SLP_PU_V 1
#define SLP_PU_S 3
/* Input enable in sleep mode */
#define SLP_IE (BIT(4))
#define SLP_IE_M (BIT(4))
#define SLP_IE_V 1
#define SLP_IE_S 4
/* Drive strength in sleep mode */
#define SLP_DRV 0x3
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
#define SLP_DRV_V 0x3
#define SLP_DRV_S 5
/* Pulldown enable */
#define FUN_PD (BIT(7))
#define FUN_PD_M (BIT(7))
#define FUN_PD_V 1
#define FUN_PD_S 7
/* Pullup enable */
#define FUN_PU (BIT(8))
#define FUN_PU_M (BIT(8))
#define FUN_PU_V 1
#define FUN_PU_S 8
/* Input enable */
#define FUN_IE (BIT(9))
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
#define FUN_IE_V 1
#define FUN_IE_S 9
/* Drive strength */
#define FUN_DRV 0x3
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
#define FUN_DRV_V 0x3
#define FUN_DRV_S 10
/* Function select (possible values are defined for each pin as
* FUNC_pinname_function below)
*/
#define MCU_SEL 0x7
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_GPIO4_U
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_GPIO5_U
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_XTAL_32K_P_U
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_XTAL_32K_N_U
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_DAC_1_U
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_DAC_2_U
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_GPIO21_U
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPICS1_U
#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SPIHD_U
#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIWP_U
#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICS0_U
#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPICLK_U
#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_SPIQ_U
#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_SPID_U
#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U
#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U
#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U
#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U
#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U
#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U
#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_MTCK_U
#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_MTDO_U
#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_MTDI_U
#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_MTMS_U
#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U0TXD_U
#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U0RXD_U
#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U
#define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_GPIO46_U
#define FUNC_GPIO_GPIO 1
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define U1RXD_GPIO_NUM 18
#define U1TXD_GPIO_NUM 17
#define U0RXD_GPIO_NUM 44
#define U0TXD_GPIO_NUM 43
#define SPI_CS1_GPIO_NUM 26
#define SPI_HD_GPIO_NUM 27
#define SPI_WP_GPIO_NUM 28
#define SPI_CS0_GPIO_NUM 29
#define SPI_CLK_GPIO_NUM 30
#define SPI_Q_GPIO_NUM 31
#define SPI_D_GPIO_NUM 32
#define SPI_D4_GPIO_NUM 33
#define SPI_D5_GPIO_NUM 34
#define SPI_D6_GPIO_NUM 35
#define SPI_D7_GPIO_NUM 36
#define SPI_DQS_GPIO_NUM 37
#define MAX_RTC_GPIO_NUM 21
#define MAX_PAD_GPIO_NUM 46
#define MAX_GPIO_NUM 53
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
#define PAD_POWER_SEL_S 15
#define PAD_POWER_SWITCH_DELAY 0x7
#define PAD_POWER_SWITCH_DELAY_V 0x7
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
#define PAD_POWER_SWITCH_DELAY_S 12
#define CLK_OUT3 0xf
#define CLK_OUT3_V CLK_OUT3
#define CLK_OUT3_S 8
#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
#define CLK_OUT2 0xf
#define CLK_OUT2_V CLK_OUT2
#define CLK_OUT2_S 4
#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
#define CLK_OUT1 0xf
#define CLK_OUT1_V CLK_OUT1
#define CLK_OUT1_S 0
#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE +0x04)
#define FUNC_GPIO0_GPIO0 1
#define FUNC_GPIO0_GPIO0_0 0
#define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE +0x08)
#define FUNC_GPIO1_GPIO1 1
#define FUNC_GPIO1_GPIO1_0 0
#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE +0x0c)
#define FUNC_GPIO2_GPIO2 1
#define FUNC_GPIO2_GPIO2_0 0
#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE +0x10)
#define FUNC_GPIO3_GPIO3 1
#define FUNC_GPIO3_GPIO3_0 0
#define PERIPHS_IO_MUX_GPIO4_U (REG_IO_MUX_BASE +0x14)
#define FUNC_GPIO4_GPIO4 1
#define FUNC_GPIO4_GPIO4_0 0
#define PERIPHS_IO_MUX_GPIO5_U (REG_IO_MUX_BASE +0x18)
#define FUNC_GPIO5_GPIO5 1
#define FUNC_GPIO5_GPIO5_0 0
#define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE +0x1c)
#define FUNC_GPIO6_GPIO6 1
#define FUNC_GPIO6_GPIO6_0 0
#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE +0x20)
#define FUNC_GPIO7_GPIO7 1
#define FUNC_GPIO7_GPIO7_0 0
#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE +0x24)
#define FUNC_GPIO8_SUBSPICS1 3
#define FUNC_GPIO8_GPIO8 1
#define FUNC_GPIO8_GPIO8_0 0
#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE +0x28)
#define FUNC_GPIO9_FSPIHD 4
#define FUNC_GPIO9_SUBSPIHD 3
#define FUNC_GPIO9_GPIO9 1
#define FUNC_GPIO9_GPIO9_0 0
#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE +0x2c)
#define FUNC_GPIO10_FSPICS0 4
#define FUNC_GPIO10_SUBSPICS0 3
#define FUNC_GPIO10_FSPIIO4 2
#define FUNC_GPIO10_GPIO10 1
#define FUNC_GPIO10_GPIO10_0 0
#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE +0x30)
#define FUNC_GPIO11_FSPID 4
#define FUNC_GPIO11_SUBSPID 3
#define FUNC_GPIO11_FSPIIO5 2
#define FUNC_GPIO11_GPIO11 1
#define FUNC_GPIO11_GPIO11_0 0
#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE +0x34)
#define FUNC_GPIO12_FSPICLK 4
#define FUNC_GPIO12_SUBSPICLK 3
#define FUNC_GPIO12_FSPIIO6 2
#define FUNC_GPIO12_GPIO12 1
#define FUNC_GPIO12_GPIO12_0 0
#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE +0x38)
#define FUNC_GPIO13_FSPIQ 4
#define FUNC_GPIO13_SUBSPIQ 3
#define FUNC_GPIO13_FSPIIO7 2
#define FUNC_GPIO13_GPIO13 1
#define FUNC_GPIO13_GPIO13_0 0
#define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE +0x3c)
#define FUNC_GPIO14_FSPIWP 4
#define FUNC_GPIO14_SUBSPIWP 3
#define FUNC_GPIO14_FSPIDQS 2
#define FUNC_GPIO14_GPIO14 1
#define FUNC_GPIO14_GPIO14_0 0
#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE +0x40)
#define FUNC_XTAL_32K_P_U0RTS 2
#define FUNC_XTAL_32K_P_GPIO15 1
#define FUNC_XTAL_32K_P_GPIO15_0 0
#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE +0x44)
#define FUNC_XTAL_32K_N_U0CTS 2
#define FUNC_XTAL_32K_N_GPIO16 1
#define FUNC_XTAL_32K_N_GPIO16_0 0
#define PERIPHS_IO_MUX_DAC_1_U (REG_IO_MUX_BASE +0x48)
#define FUNC_DAC_1_U1TXD 2
#define FUNC_DAC_1_GPIO17 1
#define FUNC_DAC_1_GPIO17_0 0
#define PERIPHS_IO_MUX_DAC_2_U (REG_IO_MUX_BASE +0x4c)
#define FUNC_DAC_2_CLK_OUT3 3
#define FUNC_DAC_2_U1RXD 2
#define FUNC_DAC_2_GPIO18 1
#define FUNC_DAC_2_GPIO18_0 0
#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE +0x50)
#define FUNC_GPIO19_CLK_OUT2 3
#define FUNC_GPIO19_U1RTS 2
#define FUNC_GPIO19_GPIO19 1
#define FUNC_GPIO19_GPIO19_0 0
#define PERIPHS_IO_MUX_GPIO20_U (REG_IO_MUX_BASE +0x54)
#define FUNC_GPIO20_CLK_OUT1 3
#define FUNC_GPIO20_U1CTS 2
#define FUNC_GPIO20_GPIO20 1
#define FUNC_GPIO20_GPIO20_0 0
#define PERIPHS_IO_MUX_GPIO21_U (REG_IO_MUX_BASE +0x58)
#define FUNC_GPIO21_GPIO21 1
#define FUNC_GPIO21_GPIO21_0 0
#define PERIPHS_IO_MUX_SPICS1_U (REG_IO_MUX_BASE +0x6c)
#define FUNC_SPICS1_GPIO26 1
#define FUNC_SPICS1_SPICS1 0
#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE +0x70)
#define FUNC_SPIHD_GPIO27 1
#define FUNC_SPIHD_SPIHD 0
#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE +0x74)
#define FUNC_SPIWP_GPIO28 1
#define FUNC_SPIWP_SPIWP 0
#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE +0x78)
#define FUNC_SPICS0_GPIO29 1
#define FUNC_SPICS0_SPICS0 0
#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE +0x7c)
#define FUNC_SPICLK_GPIO30 1
#define FUNC_SPICLK_SPICLK 0
#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE +0x80)
#define FUNC_SPIQ_GPIO31 1
#define FUNC_SPIQ_SPIQ 0
#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE +0x84)
#define FUNC_SPID_GPIO32 1
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88)
#define FUNC_GPIO33_SPIIO4 4
#define FUNC_GPIO33_SUBSPIHD 3
#define FUNC_GPIO33_FSPIHD 2
#define FUNC_GPIO33_GPIO33 1
#define FUNC_GPIO33_GPIO33_0 0
#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c)
#define FUNC_GPIO34_SPIIO5 4
#define FUNC_GPIO34_SUBSPICS0 3
#define FUNC_GPIO34_FSPICS0 2
#define FUNC_GPIO34_GPIO34 1
#define FUNC_GPIO34_GPIO34_0 0
#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90)
#define FUNC_GPIO35_SPIIO6 4
#define FUNC_GPIO35_SUBSPID 3
#define FUNC_GPIO35_FSPID 2
#define FUNC_GPIO35_GPIO35 1
#define FUNC_GPIO35_GPIO35_0 0
#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94)
#define FUNC_GPIO36_SPIIO7 4
#define FUNC_GPIO36_SUBSPICLK 3
#define FUNC_GPIO36_FSPICLK 2
#define FUNC_GPIO36_GPIO36 1
#define FUNC_GPIO36_GPIO36_0 0
#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98)
#define FUNC_GPIO37_SPIDQS 4
#define FUNC_GPIO37_SUBSPIQ 3
#define FUNC_GPIO37_FSPIQ 2
#define FUNC_GPIO37_GPIO37 1
#define FUNC_GPIO37_GPIO37_0 0
#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c)
#define FUNC_GPIO38_SUBSPIWP 3
#define FUNC_GPIO38_FSPIWP 2
#define FUNC_GPIO38_GPIO38 1
#define FUNC_GPIO38_GPIO38_0 0
#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE +0xa0)
#define FUNC_MTCK_SUBSPICS1 3
#define FUNC_MTCK_CLK_OUT3 2
#define FUNC_MTCK_GPIO39 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE +0xa4)
#define FUNC_MTDO_CLK_OUT2 2
#define FUNC_MTDO_GPIO40 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE +0xa8)
#define FUNC_MTDI_CLK_OUT1 2
#define FUNC_MTDI_GPIO41 1
#define FUNC_MTDI_MTDI 0
#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE +0xac)
#define FUNC_MTMS_GPIO42 1
#define FUNC_MTMS_MTMS 0
#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE +0xb0)
#define FUNC_U0TXD_CLK_OUT1 2
#define FUNC_U0TXD_GPIO43 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE +0xb4)
#define FUNC_U0RXD_CLK_OUT2 2
#define FUNC_U0RXD_GPIO44 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_GPIO45_U (REG_IO_MUX_BASE +0xb8)
#define FUNC_GPIO45_GPIO45 1
#define FUNC_GPIO45_GPIO45_0 0
#define PERIPHS_IO_MUX_GPIO46_U (REG_IO_MUX_BASE +0xbc)
#define FUNC_GPIO46_GPIO46 1
#define FUNC_GPIO46_GPIO46_0 0
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
#define IO_MUX_DATE 0xFFFFFFFF
#define IO_MUX_DATE_S 0
#define IO_MUX_DATE_VERSION 0x1907160
#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H */

233
arch/xtensa/src/esp32s2/hardware/esp32s2_rsa.h Normal file

@ -0,0 +1,233 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/hardware/esp32s2_rsa.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RSA_H
#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RSA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "esp32s2_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* RSA_M_PRIME_REG register
* Register to store M'
*/
#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800)
/* RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0;
* Stores M'
*/
#define RSA_M_PRIME 0xFFFFFFFF
#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S)
#define RSA_M_PRIME_V 0xFFFFFFFF
#define RSA_M_PRIME_S 0
/* RSA_MODE_REG register
* RSA length mode
*/
#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804)
/* RSA_MODE : R/W; bitpos: [6:0]; default: 0;
* Stores the mode of modular exponentiation.
*/
#define RSA_MODE 0x0000007F
#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S)
#define RSA_MODE_V 0x0000007F
#define RSA_MODE_S 0
/* RSA_CLEAN_REG register
* RSA clean register
*/
#define RSA_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
/* RSA_CLEAN : RO; bitpos: [0]; default: 0;
* The content of this bit is 1 when memories complete initialization.
*/
#define RSA_CLEAN (BIT(0))
#define RSA_CLEAN_M (RSA_CLEAN_V << RSA_CLEAN_S)
#define RSA_CLEAN_V 0x00000001
#define RSA_CLEAN_S 0
/* RSA_MODEXP_START_REG register
* Modular exponentiation starting bit
*/
#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c)
/* RSA_MODEXP_START : WO; bitpos: [0]; default: 0;
* Set this bit to 1 to start the modular exponentiation.
*/
#define RSA_MODEXP_START (BIT(0))
#define RSA_MODEXP_START_M (RSA_MODEXP_START_V << RSA_MODEXP_START_S)
#define RSA_MODEXP_START_V 0x00000001
#define RSA_MODEXP_START_S 0
/* RSA_MODMULT_START_REG register
* Modular multiplication starting bit
*/
#define RSA_MODMULT_START_REG (DR_REG_RSA_BASE + 0x810)
/* RSA_MODMULT_START : WO; bitpos: [0]; default: 0;
* Set this bit to 1 to start the modular multiplication.
*/
#define RSA_MODMULT_START (BIT(0))
#define RSA_MODMULT_START_M (RSA_MODMULT_START_V << RSA_MODMULT_START_S)
#define RSA_MODMULT_START_V 0x00000001
#define RSA_MODMULT_START_S 0
/* RSA_MULT_START_REG register
* Normal multiplicaiton starting bit
*/
#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814)
/* RSA_MULT_START : WO; bitpos: [0]; default: 0;
* Set this bit to 1 to start the multiplication.
*/
#define RSA_MULT_START (BIT(0))
#define RSA_MULT_START_M (RSA_MULT_START_V << RSA_MULT_START_S)
#define RSA_MULT_START_V 0x00000001
#define RSA_MULT_START_S 0
/* RSA_IDLE_REG register
* RSA idle register
*/
#define RSA_IDLE_REG (DR_REG_RSA_BASE + 0x818)
/* RSA_IDLE : RO; bitpos: [0]; default: 0;
* The content of this bit is 1 when the RSA accelerator is idle.
*/
#define RSA_IDLE (BIT(0))
#define RSA_IDLE_M (RSA_IDLE_V << RSA_IDLE_S)
#define RSA_IDLE_V 0x00000001
#define RSA_IDLE_S 0
/* RSA_CLEAR_INTERRUPT_REG register
* RSA clear interrupt register
*/
#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81c)
/* RSA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
* Set this bit to 1 to clear the RSA interrupts.
*/
#define RSA_CLEAR_INTERRUPT (BIT(0))
#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S)
#define RSA_CLEAR_INTERRUPT_V 0x00000001
#define RSA_CLEAR_INTERRUPT_S 0
/* RSA_CONSTANT_TIME_REG register
* The constant_time option
*/
#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
/* RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1;
* Set this bit to 0 to enable the acceleration option of constant_time for
* modular exponentiation. Set to 1 to disable the acceleration (by default).
*/
#define RSA_CONSTANT_TIME (BIT(0))
#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S)
#define RSA_CONSTANT_TIME_V 0x00000001
#define RSA_CONSTANT_TIME_S 0
/* RSA_SEARCH_ENABLE_REG register
* The search option
*/
#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824)
/* RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0;
* Set this bit to 1 to enable the acceleration option of search for modular
* exponentiation. Set to 0 to disable the acceleration (by default).
*/
#define RSA_SEARCH_ENABLE (BIT(0))
#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S)
#define RSA_SEARCH_ENABLE_V 0x00000001
#define RSA_SEARCH_ENABLE_S 0
/* RSA_SEARCH_POS_REG register
* The search position
*/
#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
/* RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0;
* Is used to configure the starting address when the acceleration option of
* search is used.
*/
#define RSA_SEARCH_POS 0x00000FFF
#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S)
#define RSA_SEARCH_POS_V 0x00000FFF
#define RSA_SEARCH_POS_S 0
/* RSA_INTERRUPT_ENA_REG register
* RSA interrupt enable register
*/
#define RSA_INTERRUPT_ENA_REG (DR_REG_RSA_BASE + 0x82c)
/* RSA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
* Set this bit to 1 to enable the RSA interrupt. This option is enabled by
* default.
*/
#define RSA_INTERRUPT_ENA (BIT(0))
#define RSA_INTERRUPT_ENA_M (RSA_INTERRUPT_ENA_V << RSA_INTERRUPT_ENA_S)
#define RSA_INTERRUPT_ENA_V 0x00000001
#define RSA_INTERRUPT_ENA_S 0
/* RSA_DATE_REG register
* Version control register
*/
#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830)
/* RSA_DATE : R/W; bitpos: [29:0]; default: 538510373;
* Version control register
*/
#define RSA_DATE 0x3FFFFFFF
#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S)
#define RSA_DATE_V 0x3FFFFFFF
#define RSA_DATE_S 0
#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RSA_H */

3704
arch/xtensa/src/esp32s2/hardware/esp32s2_rtc_io.h Normal file

File diff suppressed because it is too large Load Diff

4419
arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h Normal file

File diff suppressed because it is too large Load Diff

786
arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h Normal file

@ -0,0 +1,786 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H
#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include "xtensa_attr.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Bits */
#define BIT31 0x80000000
#define BIT30 0x40000000
#define BIT29 0x20000000
#define BIT28 0x10000000
#define BIT27 0x08000000
#define BIT26 0x04000000
#define BIT25 0x02000000
#define BIT24 0x01000000
#define BIT23 0x00800000
#define BIT22 0x00400000
#define BIT21 0x00200000
#define BIT20 0x00100000
#define BIT19 0x00080000
#define BIT18 0x00040000
#define BIT17 0x00020000
#define BIT16 0x00010000
#define BIT15 0x00008000
#define BIT14 0x00004000
#define BIT13 0x00002000
#define BIT12 0x00001000
#define BIT11 0x00000800
#define BIT10 0x00000400
#define BIT9 0x00000200
#define BIT8 0x00000100
#define BIT7 0x00000080
#define BIT6 0x00000040
#define BIT5 0x00000020
#define BIT4 0x00000010
#define BIT3 0x00000008
#define BIT2 0x00000004
#define BIT1 0x00000002
#define BIT0 0x00000001
#define PRO_CPU_NUM (0)
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) /* Largest span of contiguous memory (DRAM or IRAM) in the address space */
/* Registers Operation */
#define ETS_UNCACHED_ADDR(addr) (addr)
#define ETS_CACHED_ADDR(addr) (addr)
#define BIT(nr) (1UL << (nr))
/* Write value to register */
#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
/* Read value from register */
#define REG_READ(_r) (*(volatile uint32_t *)(_r))
/* Get bit or get bits from register */
#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b))
/* Set bit or set bits to register */
#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b))
/* Clear bit or clear bits of register */
#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b))
/* Set bits of register controlled by mask */
#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)))
/* Get field from register,
* used when _f is not left shifted by _f##_S
*/
#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V))
/* Set field to register,
* used when _f is not left shifted by _f##_S
*/
#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))))
/* Set field value from a variable,
* used when _f is not left shifted by _f##_S
*/
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
/* Get field value from a variable,
* used when _f is left shifted by _f##_S
*/
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
/* Set field value to a variable,
* used when _f is not left shifted by _f##_S
*/
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
/* Set field value to a variable,
* used when _f is left shifted by _f##_S
*/
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
/* Generate a value from a field value,
* used when _f is not left shifted by _f##_S
*/
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
/* Generate a value from a field value,
* used when _f is left shifted by _f##_S
*/
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
/* Read value from register */
#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
/* Write value to register */
#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
/* Clear bits of register controlled by mask */
#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
/* Set bits of register controlled by mask */
#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
/* Get bits of register controlled by mask */
#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask))
/* Get bits of register controlled by highest bit and lowest bit */
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
/* Set bits of register controlled by mask and shift */
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ))
/* Get field of register */
#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask))
/* Extract the field from the register and shift it to avoid wrong reading */
#define REG_MASK(_reg, _field) ((_reg & (_field##_M)) >> (_field##_S))
/* Helper to place a value in a field */
#define VALUE_TO_FIELD(_value, _field) ((_value << (_field##_S)) & (_field##_M))
/* Periheral Clock */
#define APB_CLK_FREQ_ROM 40 * 1000000
#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define UART_CLK_FREQ_ROM APB_CLK_FREQ_ROM
#define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ 80 * 1000000 /* Unit: Hz */
#define REF_CLK_FREQ (1000000)
#define UART_CLK_FREQ APB_CLK_FREQ
#define MWDT_CLK_FREQ APB_CLK_FREQ
#define TIMER_CLK_FREQ (80000000 >> 4) /* 80MHz divided by 16 */
#define SPI_CLK_DIV 4
#define TICKS_PER_US_ROM 40 /* CPU is 80MHz */
#define DR_REG_SYSTEM_BASE 0x3f4c0000
#define DR_REG_SENSITIVE_BASE 0x3f4c1000
#define DR_REG_INTERRUPT_BASE 0x3f4c2000
#define DR_REG_DMA_COPY_BASE 0x3f4c3000
#define DR_REG_EXTMEM_BASE 0x61800000
#define DR_REG_MMU_TABLE 0x61801000
#define DR_REG_ITAG_TABLE 0x61802000
#define DR_REG_DTAG_TABLE 0x61803000
#define DR_REG_AES_BASE 0x6003a000
#define DR_REG_SHA_BASE 0x6003b000
#define DR_REG_RSA_BASE 0x6003c000
#define DR_REG_HMAC_BASE 0x6003e000
#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000
#define DR_REG_CRYPTO_DMA_BASE 0x6003f000
#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000
#define DR_REG_INTRUSION_BASE 0x3f4d0000
#define DR_REG_DPORT_END 0x3f4d3FFC
#define DR_REG_UART_BASE 0x3f400000
#define DR_REG_SPI1_BASE 0x3f402000
#define DR_REG_SPI0_BASE 0x3f403000
#define DR_REG_GPIO_BASE 0x3f404000
#define DR_REG_GPIO_SD_BASE 0x3f404f00
#define DR_REG_FE2_BASE 0x3f405000
#define DR_REG_FE_BASE 0x3f406000
#define DR_REG_FRC_TIMER_BASE 0x3f407000
#define DR_REG_RTCCNTL_BASE 0x3f408000
#define DR_REG_RTCIO_BASE 0x3f408400
#define DR_REG_SENS_BASE 0x3f408800
#define DR_REG_RTC_I2C_BASE 0x3f408C00
#define DR_REG_IO_MUX_BASE 0x3f409000
#define DR_REG_HINF_BASE 0x3f40B000
#define DR_REG_I2S_BASE 0x3f40F000
#define DR_REG_UART1_BASE 0x3f410000
#define DR_REG_I2C_EXT_BASE 0x3f413000
#define DR_REG_UHCI0_BASE 0x3f414000
#define DR_REG_SLCHOST_BASE 0x3f415000
#define DR_REG_RMT_BASE 0x3f416000
#define DR_REG_PCNT_BASE 0x3f417000
#define DR_REG_SLC_BASE 0x3f418000
#define DR_REG_LEDC_BASE 0x3f419000
#define DR_REG_CP_BASE 0x3f4c3000
#define DR_REG_EFUSE_BASE 0x3f41A000
#define DR_REG_NRX_BASE 0x3f41CC00
#define DR_REG_BB_BASE 0x3f41D000
#define DR_REG_TIMERGROUP0_BASE 0x3f41F000
#define DR_REG_TIMERGROUP1_BASE 0x3f420000
#define DR_REG_RTC_SLOWMEM_BASE 0x3f421000
#define DR_REG_SYSTIMER_BASE 0x3f423000
#define DR_REG_SPI2_BASE 0x3f424000
#define DR_REG_SPI3_BASE 0x3f425000
#define DR_REG_SYSCON_BASE 0x3f426000
#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */
#define DR_REG_I2C1_EXT_BASE 0x3f427000
#define DR_REG_SPI4_BASE 0x3f437000
#define DR_REG_USB_WRAP_BASE 0x3f439000
#define DR_REG_APB_SARADC_BASE 0x3f440000
#define DR_REG_USB_BASE 0x60080000
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE)
#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000 )
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 )
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
/* Registers Operation */
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 )
/* Overall memory map */
#define SOC_DROM_LOW 0x3f000000 /* drom0 low address for icache */
#define SOC_DROM_HIGH 0x3ff80000 /* dram0 high address for dcache */
#define SOC_IROM_LOW 0x40080000
#define SOC_IROM_HIGH 0x40800000
#define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x40020000
#define SOC_IRAM_LOW 0x40020000
#define SOC_IRAM_HIGH 0x40070000
#define SOC_DRAM_LOW 0x3ffb0000
#define SOC_DRAM_HIGH 0x40000000
#define SOC_RTC_IRAM_LOW 0x40070000
#define SOC_RTC_IRAM_HIGH 0x40072000
#define SOC_RTC_DRAM_LOW 0x3ff9e000
#define SOC_RTC_DRAM_HIGH 0x3ffa0000
#define SOC_RTC_DATA_LOW 0x50000000
#define SOC_RTC_DATA_HIGH 0x50002000
#define SOC_EXTRAM_DATA_LOW 0x3f500000
#define SOC_EXTRAM_DATA_HIGH 0x3ff80000
/* Virtual address 0 */
#define VADDR0_START_ADDR SOC_DROM_LOW
#define VADDR0_END_ADDR (SOC_DROM_HIGH - 1)
/* Interrupt hardware source table
* This table is decided by hardware, don't touch this.
*/
#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010)
#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c)
#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038)
/* Interrupt cpu using table */
/****************************************************************************
*Intr num Level Type PRO CPU usage APP CPU uasge
* 0 1 extern level WMAC Reserved
* 1 1 extern level BT/BLE Host VHCI Reserved
* 2 1 extern level FROM_CPU FROM_CPU
* 3 1 extern level TG0_WDT Reserved
* 4 1 extern level WBB
* 5 1 extern level BT Controller
* 6 1 timer RTOS Tick RTOS Tick
* 7 1 software Reserved Reserved
* 8 1 extern level BLE Controller
* 9 1 extern level
* 10 1 extern edge Internal Timer
* 11 3 profiling
* 12 1 extern level
* 13 1 extern level
* 14 7 nmi Reserved Reserved
* 15 3 timer Internal Timer
* 16 5 timer
* 17 1 extern level
* 18 1 extern level
* 19 2 extern level
* 20 2 extern level
* 21 2 extern level
* 22 3 extern edge
* 23 3 extern level
* 24 4 extern level
* 25 4 extern level Reserved Reserved
* 26 5 extern level Reserved Reserved
* 27 3 extern level Reserved Reserved
* 28 4 extern edge
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 31 5 extern level Reserved Reserved
****************************************************************************/
/* CPU0 Interrupt number reserved, not touch this. */
#define ETS_WMAC_INUM 0
#define ETS_BT_HOST_INUM 1
#define ETS_FROM_CPU_INUM 2
#define ETS_T0_WDT_INUM 3
#define ETS_WBB_INUM 4
#define ETS_TG0_T1_INUM 10 /* Use edge interrupt */
/* CPU0 Interrupt number used in ROM, should be cancelled in SDK */
#define ETS_SLC_INUM 1
#define ETS_UART0_INUM 5
#define ETS_UART1_INUM 5
/* Other interrupt numbers should be managed by the user */
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0)
#define APB_CTRL_XTAL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4)
/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
#define APB_CTRL_PRE_DIV_CNT 0x000003ff
#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V) << \
(APB_CTRL_PRE_DIV_CNT_S))
#define APB_CTRL_PRE_DIV_CNT_V 0x3ff
#define APB_CTRL_PRE_DIV_CNT_S 0
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
#define I2C_BBPLL_OC_ENB_FCAL 4
#define I2C_BBPLL_OC_ENB_VCON 10
#define I2C_BBPLL_BBADC_CAL_7_0 12
#define I2C_BBPLL_OC_LREF 2
#define I2C_BBPLL_OC_LREF_MSB 7
#define I2C_BBPLL_OC_LREF_LSB 7
#define I2C_BBPLL_OC_DIV_7_0 3
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
#define I2C_BBPLL_BBADC_DSMP 9
#define I2C_BBPLL_BBADC_DSMP_MSB 7
#define I2C_BBPLL_BBADC_DSMP_LSB 4
#define I2C_BBPLL_OC_DCUR 5
#define I2C_BBPLL_OC_DCUR_MSB 2
#define I2C_BBPLL_OC_DCUR_LSB 0
#define I2C_BBPLL_ENDIV5 11
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 4
extern int rom_i2c_writereg(int block, int block_id, int reg_add,
int indata);
#define I2C_WRITEREG_RTC(block, reg_add, indata) \
rom_i2c_writereg(block, block##_HOSTID, reg_add, indata)
#define I2C_READREG_RTC(block, reg_add) \
rom_i2c_readreg(block, block##_HOSTID, reg_add)
#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \
rom_i2c_writereg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
#define I2C_READREG_MASK_RTC(block, reg_add) \
rom_i2c_readreg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
/* BBPLL configuration values */
#define BBPLL_ENDIV5_VAL_320M 0x43
#define BBPLL_BBADC_DSMP_VAL_320M 0x84
#define BBPLL_ENDIV5_VAL_480M 0xc3
#define BBPLL_BBADC_DSMP_VAL_480M 0x74
#define BBPLL_IR_CAL_DELAY_VAL 0x18
#define BBPLL_IR_CAL_EXT_CAP_VAL 0x20
#define BBPLL_OC_ENB_FCAL_VAL 0x9a
#define BBPLL_OC_ENB_VCON_VAL 0x00
#define BBPLL_BBADC_CAL_7_0_VAL 0x00
#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014)
/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */
/* description: This field stores the voltage level for
* CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.
* 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)
*/
#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03
#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V) << (EFUSE_RD_VOL_LEVEL_HP_INV_S))
#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03
#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22
/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */
/* description: read for sdio_force */
#define EFUSE_RD_SDIO_FORCE (BIT(16))
#define EFUSE_RD_SDIO_FORCE_M (BIT(16))
#define EFUSE_RD_SDIO_FORCE_V 0x1
#define EFUSE_RD_SDIO_FORCE_S 16
/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */
/* description: read for XPD_SDIO_REG */
#define EFUSE_RD_XPD_SDIO_REG (BIT(14))
#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14))
#define EFUSE_RD_XPD_SDIO_REG_V 0x1
#define EFUSE_RD_XPD_SDIO_REG_S 14
/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */
/* description: read for SDIO_TIEH */
#define EFUSE_RD_SDIO_TIEH (BIT(15))
#define EFUSE_RD_SDIO_TIEH_M (BIT(15))
#define EFUSE_RD_SDIO_TIEH_V 0x1
#define EFUSE_RD_SDIO_TIEH_S 15
/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */
/* description: If set, this bit indicates that
* BLOCK3[143:96] is reserved for internal use
*/
#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14))
#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V) << (EFUSE_RD_BLK3_PART_RESERVE_S))
#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1
#define EFUSE_RD_BLK3_PART_RESERVE_S 14
/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */
#define EFUSE_RD_SDIO_DREFH 0x00000003
#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V) << (EFUSE_RD_SDIO_DREFH_S))
#define EFUSE_RD_SDIO_DREFH_V 0x3
#define EFUSE_RD_SDIO_DREFH_S 8
/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */
#define EFUSE_RD_SDIO_DREFM 0x00000003
#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V) << (EFUSE_RD_SDIO_DREFM_S))
#define EFUSE_RD_SDIO_DREFM_V 0x3
#define EFUSE_RD_SDIO_DREFM_S 10
/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space.
* Newer versions of ESP32 come with EFUSE_ADC_VREF already burned,
* therefore SDIO_DREFH/M/L is only available in older versions of ESP32
*/
/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */
#define EFUSE_RD_SDIO_DREFL 0x00000003
#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V) << (EFUSE_RD_SDIO_DREFL_S))
#define EFUSE_RD_SDIO_DREFL_V 0x3
#define EFUSE_RD_SDIO_DREFL_S 12
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)
#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
* Valid if RTC_CNTL_DBG_ATTEN is 0.
*/
#define RTC_CNTL_DBIAS_1V00 2
#define RTC_CNTL_DBIAS_1V10 4
#define RTC_CNTL_DBIAS_1V25 7
/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ;
* description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL
*/
#define RTC_CNTL_SOC_CLK_SEL 0x00000003
#define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V) << (RTC_CNTL_SOC_CLK_SEL_S))
#define RTC_CNTL_SOC_CLK_SEL_V 0x3
#define RTC_CNTL_SOC_CLK_SEL_S 27
#define RTC_CNTL_SOC_CLK_SEL_XTL 0
#define RTC_CNTL_SOC_CLK_SEL_PLL 1
#define RTC_CNTL_SOC_CLK_SEL_8M 2
#define RTC_CNTL_SOC_CLK_SEL_APLL 3
/* Core voltage needs to be increased in two cases:
* 1. running at 240 MHz
* 2. running with 80MHz Flash frequency
* There is a record in efuse which indicates the
* proper voltage for these two cases.
*/
#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - \
(REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, \
EFUSE_RD_VOL_LEVEL_HP_INV)))
#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT
#else
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
#endif
#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
#define DELAY_PLL_DBIAS_RAISE 3
#define DELAY_PLL_ENABLE_WITH_150K 80
#define DELAY_PLL_ENABLE_WITH_32K 160
/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ;
* description: BB_I2C force power down
*/
#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6))
/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ;
* description: BB_PLL force power down
*/
#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10))
/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ;
* description: BB_PLL _I2C force power down
*/
#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8))
/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ;
* description: PLLA force power down
*/
#define RTC_CNTL_PLLA_FORCE_PD (BIT(23))
#define RTC_CNTL_PLLA_FORCE_PD_S 23
/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ;
* description: BIAS_I2C force power down
*/
#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18))
#define MHZ (1000000)
#define RTC_PLL_FREQ_320M 320
#define RTC_PLL_FREQ_480M 480
/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
#define TIMG_RTC_CALI_CLK_SEL 0x00000003
#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V) << (TIMG_RTC_CALI_CLK_SEL_S))
#define TIMG_RTC_CALI_CLK_SEL_V 0x3
#define TIMG_RTC_CALI_CLK_SEL_S 13
/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_V 0x1
#define TIMG_RTC_CALI_START_CYCLING_S 12
/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (BIT(31))
#define TIMG_RTC_CALI_START_V 0x1
#define TIMG_RTC_CALI_START_S 31
/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */
#define TIMG_RTC_CALI_MAX 0x00007fff
#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V) << (TIMG_RTC_CALI_MAX_S))
#define TIMG_RTC_CALI_MAX_V 0x7fff
#define TIMG_RTC_CALI_MAX_S 16
/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */
#define TIMG_RTC_CALI_VALUE 0x01ffffff
#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V) << (TIMG_RTC_CALI_VALUE_S))
#define TIMG_RTC_CALI_VALUE_V 0x1ffffff
#define TIMG_RTC_CALI_VALUE_S 7
/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (BIT(15))
#define TIMG_RTC_CALI_RDY_V 0x1
#define TIMG_RTC_CALI_RDY_S 15
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c)
/* Some of the baseband control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
#define BB_FFT_FORCE_PU (BIT(3))
#define BB_FFT_FORCE_PU_M (BIT(3))
#define BB_FFT_FORCE_PU_V 1
#define BB_FFT_FORCE_PU_S 3
#define BB_FFT_FORCE_PD (BIT(2))
#define BB_FFT_FORCE_PD_M (BIT(2))
#define BB_FFT_FORCE_PD_V 1
#define BB_FFT_FORCE_PD_S 2
#define BB_DC_EST_FORCE_PU (BIT(1))
#define BB_DC_EST_FORCE_PU_M (BIT(1))
#define BB_DC_EST_FORCE_PU_V 1
#define BB_DC_EST_FORCE_PU_S 1
#define BB_DC_EST_FORCE_PD (BIT(0))
#define BB_DC_EST_FORCE_PD_M (BIT(0))
#define BB_DC_EST_FORCE_PD_V 1
#define BB_DC_EST_FORCE_PD_S 0
/* Some of the WiFi RX control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
#define NRX_RX_ROT_FORCE_PU (BIT(5))
#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
#define NRX_RX_ROT_FORCE_PU_V 1
#define NRX_RX_ROT_FORCE_PU_S 5
#define NRX_RX_ROT_FORCE_PD (BIT(4))
#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
#define NRX_RX_ROT_FORCE_PD_V 1
#define NRX_RX_ROT_FORCE_PD_S 4
#define NRX_VIT_FORCE_PU (BIT(3))
#define NRX_VIT_FORCE_PU_M (BIT(3))
#define NRX_VIT_FORCE_PU_V 1
#define NRX_VIT_FORCE_PU_S 3
#define NRX_VIT_FORCE_PD (BIT(2))
#define NRX_VIT_FORCE_PD_M (BIT(2))
#define NRX_VIT_FORCE_PD_V 1
#define NRX_VIT_FORCE_PD_S 2
#define NRX_DEMAP_FORCE_PU (BIT(1))
#define NRX_DEMAP_FORCE_PU_M (BIT(1))
#define NRX_DEMAP_FORCE_PU_V 1
#define NRX_DEMAP_FORCE_PU_S 1
#define NRX_DEMAP_FORCE_PD (BIT(0))
#define NRX_DEMAP_FORCE_PD_M (BIT(0))
#define NRX_DEMAP_FORCE_PD_V 1
#define NRX_DEMAP_FORCE_PD_S 0
/* Some of the RF frontend control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
#define FE_IQ_EST_FORCE_PU (BIT(5))
#define FE_IQ_EST_FORCE_PU_M (BIT(5))
#define FE_IQ_EST_FORCE_PU_V 1
#define FE_IQ_EST_FORCE_PU_S 5
#define FE_IQ_EST_FORCE_PD (BIT(4))
#define FE_IQ_EST_FORCE_PD_M (BIT(4))
#define FE_IQ_EST_FORCE_PD_V 1
#define FE_IQ_EST_FORCE_PD_S 4
#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
#define FE2_TX_INF_FORCE_PU (BIT(10))
#define FE2_TX_INF_FORCE_PU_M (BIT(10))
#define FE2_TX_INF_FORCE_PU_V 1
#define FE2_TX_INF_FORCE_PU_S 10
#define FE2_TX_INF_FORCE_PD (BIT(9))
#define FE2_TX_INF_FORCE_PD_M (BIT(9))
#define FE2_TX_INF_FORCE_PD_V 1
#define FE2_TX_INF_FORCE_PD_S 9
/* RO data page in MMU index */
#define DROM0_PAGES_START 0
#define DROM0_PAGES_END 64
#define IROM0_PAGES_START 64
#define IROM0_PAGES_END 256
/* MMU invalid value */
#define INVALID_MMU_VAL 0x100
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s2_sp_dram
*
* Description:
* Check if the stack pointer is in DRAM.
*
****************************************************************************/
static inline bool IRAM_ATTR esp32s2_sp_dram(uint32_t sp)
{
return (sp >= SOC_DRAM_LOW + 0x10 && sp < SOC_DRAM_HIGH - 0x10);
}
/****************************************************************************
* Name: esp32s2_ptr_extram
*
* Description:
* Check if the buffer comes from the external RAM
*
****************************************************************************/
static inline bool IRAM_ATTR esp32s2_ptr_extram(const void *p)
{
return ((intptr_t)p >= SOC_EXTRAM_DATA_LOW &&
(intptr_t)p < SOC_EXTRAM_DATA_HIGH);
}
/****************************************************************************
* Name: esp32s2_ptr_exec
*
* Description:
* Check if the pointer is within an executable range.
*
****************************************************************************/
static inline bool IRAM_ATTR esp32s2_ptr_exec(const void *p)
{
intptr_t ip = (intptr_t)p;
return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH)
|| (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH)
|| (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH)
#if defined(SOC_CACHE_APP_LOW) && !defined(CONFIG_SMP)
|| (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH)
#endif
|| (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH);
}
#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H */

3139
arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h Normal file

File diff suppressed because it is too large Load Diff

1465
arch/xtensa/src/esp32s2/hardware/esp32s2_system.h Normal file

File diff suppressed because it is too large Load Diff

1265
arch/xtensa/src/esp32s2/hardware/esp32s2_tim.h Normal file

File diff suppressed because it is too large Load Diff

1846
arch/xtensa/src/esp32s2/hardware/esp32s2_uart.h Normal file

File diff suppressed because it is too large Load Diff

8
arch/xtensa/src/lx7/Kconfig Normal file

@ -0,0 +1,8 @@
#
# For a description of the syntax of this configuration file,
# see the file kconfig-language.txt in the NuttX tools repository.
#
if ARCH_CHIP_LX7
endif # ARCH_CHIP_LX7

67
arch/xtensa/src/lx7/Toolchain.defs Normal file

@ -0,0 +1,67 @@
############################################################################
# arch/xtensa/src/lx7/Toolchain.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
# Supported toolchains
#
# Each toolchain definition should set:
#
# CROSSDEV The GNU toolchain triple (command prefix)
# ARCHCPUFLAGS CPU-specific flags selecting the instruction set
# FPU options, etc.
# MAXOPTIMIZATION The maximum optimization level that results in
# reliable code generation.
#
CROSSDEV = xtensa-esp32s2-elf-
ARCHCPUFLAGS =
ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y)
MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL)
else
MAXOPTIMIZATION := -Os
endif
# Default toolchain
CC = $(CROSSDEV)gcc
CXX = $(CROSSDEV)g++
CPP = $(CROSSDEV)gcc -E -P -x c
LD = $(CROSSDEV)ld
STRIP = $(CROSSDEV)strip --strip-unneeded
AR = $(CROSSDEV)ar rcs
NM = $(CROSSDEV)nm
OBJCOPY = $(CROSSDEV)objcopy
OBJDUMP = $(CROSSDEV)objdump
# Add the builtin library
EXTRA_LIBS += -lgcc
EXTRA_LIBPATHS += -L "${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name`"}"
ifneq ($(CONFIG_LIBM),y)
EXTRA_LIBS += -lm
EXTRA_LIBPATHS += -L "${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a`"}"
endif
ifeq ($(CONFIG_CXX_LIBSUPCXX),y)
EXTRA_LIBS += -lsupc++
EXTRA_LIBPATHS += -L "${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a`"}"
endif