diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index d6267035a1..34776ba7ac 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -37,6 +37,32 @@ config ARCH_CHIP_ESP32 "application"), however for most purposes the two CPUs are interchangeable. +config ARCH_CHIP_ESP32S2 + bool "Espressif ESP32-S2" + select ARCH_FAMILY_LX7 + select XTENSA_HAVE_INTERRUPTS + select ARCH_HAVE_MODULE_TEXT + select ARCH_HAVE_SDRAM + select ARCH_HAVE_RESET + select ARCH_TOOLCHAIN_GNU + select ARCH_VECNOTIRQ + select LIBC_ARCH_MEMCPY + select LIBC_ARCH_MEMCHR + select LIBC_ARCH_MEMCMP + select LIBC_ARCH_MEMCCMP + select LIBC_ARCH_MEMMOVE + select LIBC_ARCH_MEMSET + select LIBC_ARCH_STRCHR + select LIBC_ARCH_STRCMP + select LIBC_ARCH_STRCPY + select LIBC_ARCH_STRLCPY + select LIBC_ARCH_STRNCPY + select LIBC_ARCH_STRLEN + select LIBC_ARCH_STRNLEN + ---help--- + The ESP32-S2 is a dual-core system from Espressif with a + Harvard architecture Xtensa LX7 CPU. + config ARCH_CHIP_XTENSA_CUSTOM bool "Custom XTENSA chip" select ARCH_CHIP_CUSTOM @@ -53,9 +79,17 @@ config ARCH_FAMILY_LX6 Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU). The LX6 is a configurable and extensible processor core. +config ARCH_FAMILY_LX7 + bool + default n + ---help--- + Cadence® Tensilica® Xtensa® LX7 data plane processing unit (DPU). + The LX7 is a configurable and extensible processor core. + config ARCH_CHIP string default "esp32" if ARCH_CHIP_ESP32 + default "esp32s2" if ARCH_CHIP_ESP32S2 config XTENSA_CP_LAZY bool "Lazy co-processor state restoration" @@ -143,4 +177,9 @@ if ARCH_CHIP_ESP32 source arch/xtensa/src/esp32/Kconfig endif +source arch/xtensa/src/lx7/Kconfig +if ARCH_CHIP_ESP32S2 +source arch/xtensa/src/esp32s2/Kconfig +endif + endif # ARCH_XTENSA diff --git a/arch/xtensa/include/esp32s2/chip.h b/arch/xtensa/include/esp32s2/chip.h new file mode 100644 index 0000000000..e03c5cc7e3 --- /dev/null +++ b/arch/xtensa/include/esp32s2/chip.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * arch/xtensa/include/esp32s2/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_CHIP_H +#define __ARCH_XTENSA_INCLUDE_ESP32S2_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Characterize each supported ESP32S2 part */ + +#define ESP32S2_NDAC 2 /* DAC0-1 */ +#define ESP32S2_NI2C 1 /* I2C0 */ +#define ESP32S2_NI2S 1 /* I2S0 */ +#define ESP32S2_NLCD 1 /* LCD0 */ +#define ESP32S2_NSPI 4 /* SPI0-3 */ +#define ESP32S2_NUARTS 2 /* UART0-1 */ +#define ESP32S2_NUSBOTG 1 /* USB OTG */ + +#define ESP32S2_NGPIOS 46 /* GPIO0-45 */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_CHIP_H */ diff --git a/arch/xtensa/include/esp32s2/core-isa.h b/arch/xtensa/include/esp32s2/core-isa.h new file mode 100644 index 0000000000..0348c10673 --- /dev/null +++ b/arch/xtensa/include/esp32s2/core-isa.h @@ -0,0 +1,738 @@ +/**************************************************************************** + * arch/xtensa/include/esp32s2/core-isa.h + * Xtensa processor CORE configuration + * + * Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_CORE_ISA_H +#define __ARCH_XTENSA_INCLUDE_ESP32S2_CORE_ISA_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option + * is configured, and a value of 0 otherwise. These macros are always + * defined. + */ + +/**************************************************************************** + * ISA + ****************************************************************************/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 0 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ + +/* #define XCHAL_HAVE_POPC 0 */ /* POPC instruction */ + +/* #define XCHAL_HAVE_CRC 0 */ /* CRC instruction */ + +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 0 /* MAC16 package */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BB 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ +#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */ +#define XCHAL_HAVE_FP 0 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ + +#define XCHAL_HAVE_FUSIONG 0 /* FusionG */ +#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */ +#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */ +#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */ +#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */ +#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */ + +#define XCHAL_HAVE_PDX 0 /* PDX */ +#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */ +#define XCHAL_HAVE_PDX4 0 /* PDX4 */ +#define XCHAL_HAVE_PDX8 0 /* PDX8 */ +#define XCHAL_HAVE_PDX16 0 /* PDX16 */ + +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + +#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */ +#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */ +#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */ +#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */ +#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */ +#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */ + +#define XCHAL_HAVE_VISIONC 0 /* Vision C */ + +/**************************************************************************** + * MISC + ****************************************************************************/ + +#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay + * (1 = 5-stage, 2 = 7-stage) + */ + +#define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */ + +/* In T1050, applies to selected core load and store instr. (see ISA): */ + +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc. */ +#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw */ + +#define XCHAL_SW_VERSION 1200008 /* sw version of this header */ + +#define XCHAL_CORE_ID "test_0731_1_TIE_GPIO_f" /* alphanum core name + * (CoreID) set in the Xtensa + * Processor Generator + */ + +#define XCHAL_BUILD_UNIQUE_ID 0x00075F76 /* 22-bit sw build ID */ + +/* These definitions describe the hardware targeted by this software. */ + +#define XCHAL_HW_CONFIGID0 0xC2ECFAFE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x22075F76 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX7.0.8" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 8 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 270008 /* major*100+minor */ +#define XCHAL_HW_REL_LX7 1 +#define XCHAL_HW_REL_LX7_0 1 +#define XCHAL_HW_REL_LX7_0_8 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 + +/* If software targets a range of hardware versions, these are the bounds: */ + +#define XCHAL_HW_MIN_VERSION_MAJOR 2700 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 8 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 270008 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2700 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 8 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 270008 /* latest targeted hw */ + +/**************************************************************************** + * CACHE + ****************************************************************************/ + +#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 4 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 2 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ + +/**************************************************************************** + * Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/**************************************************************************** + * CACHE + ****************************************************************************/ + +#define XCHAL_HAVE_PIF 1 /* any outbound bus present */ + +#define XCHAL_HAVE_AXI 0 /* AXI bus */ +#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */ +#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ + +#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */ +#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ + +#define XCHAL_ICACHE_SETWIDTH 0 +#define XCHAL_DCACHE_SETWIDTH 0 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 1 +#define XCHAL_DCACHE_WAYS 1 + +/* Cache features: */ + +#define XCHAL_ICACHE_LINE_LOCKABLE 0 +#define XCHAL_DCACHE_LINE_LOCKABLE 0 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Cache access size in bytes (affects operation of SICW instruction): */ + +#define XCHAL_ICACHE_ACCESS_SIZE 1 +#define XCHAL_DCACHE_ACCESS_SIZE 1 + +#define XCHAL_DCACHE_BANKS 0 /* number of banks */ + +/* Number of encoded cache attr bits (see for decoded bits): */ + +#define XCHAL_CA_BITS 4 + +/**************************************************************************** + * INTERNAL I/D RAM/ROMs and XLMI + ****************************************************************************/ + +#define XCHAL_NUM_INSTROM 1 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 1 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ + +/* Instruction ROM 0: */ + +#define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */ +#define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */ +#define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Instruction RAM 0: */ + +#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM0 1 +#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Instruction RAM 1: */ + +#define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */ +#define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */ +#define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */ +#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_HAVE_INSTRAM1 1 +#define XCHAL_INSTRAM1_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data ROM 0: */ + +#define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */ +#define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */ +#define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */ +#define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATAROM0_BANKS 1 /* number of banks */ + +/* Data RAM 0: */ + +#define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 1 /* number of banks */ +#define XCHAL_HAVE_DATARAM0 1 +#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* Data RAM 1: */ +#define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */ +#define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */ +#define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */ +#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM1_BANKS 1 /* number of banks */ +#define XCHAL_HAVE_DATARAM1 1 +#define XCHAL_DATARAM1_HAVE_IDMA 0 /* idma supported by this local memory */ + +/* XLMI Port 0: */ + +#define XCHAL_XLMI0_VADDR 0x3FE00000 /* virtual address */ +#define XCHAL_XLMI0_PADDR 0x3FE00000 /* physical address */ +#define XCHAL_XLMI0_SIZE 1048576 /* size in bytes */ +#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +#define XCHAL_HAVE_IDMA 0 +#define XCHAL_HAVE_IDMA_TRANSPOSE 0 + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM */ + +/**************************************************************************** + * INTERRUPTS and TIMERS + ****************************************************************************/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels + * (not including level zero) + */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + +/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ + +#define XCHAL_INTLEVEL1_MASK 0x000637FF +#define XCHAL_INTLEVEL2_MASK 0x00380000 +#define XCHAL_INTLEVEL3_MASK 0x28C08800 +#define XCHAL_INTLEVEL4_MASK 0x53000000 +#define XCHAL_INTLEVEL5_MASK 0x84010000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00004000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ + +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF + +/* Level of each interrupt: */ + +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 1 +#define XCHAL_INT9_LEVEL 1 +#define XCHAL_INT10_LEVEL 1 +#define XCHAL_INT11_LEVEL 3 +#define XCHAL_INT12_LEVEL 1 +#define XCHAL_INT13_LEVEL 1 +#define XCHAL_INT14_LEVEL 7 +#define XCHAL_INT15_LEVEL 3 +#define XCHAL_INT16_LEVEL 5 +#define XCHAL_INT17_LEVEL 1 +#define XCHAL_INT18_LEVEL 1 +#define XCHAL_INT19_LEVEL 2 +#define XCHAL_INT20_LEVEL 2 +#define XCHAL_INT21_LEVEL 2 +#define XCHAL_INT22_LEVEL 3 +#define XCHAL_INT23_LEVEL 3 +#define XCHAL_INT24_LEVEL 4 +#define XCHAL_INT25_LEVEL 4 +#define XCHAL_INT26_LEVEL 5 +#define XCHAL_INT27_LEVEL 3 +#define XCHAL_INT28_LEVEL 4 +#define XCHAL_INT29_LEVEL 3 +#define XCHAL_INT30_LEVEL 4 +#define XCHAL_INT31_LEVEL 5 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + * EXCSAVE/EPS/EPC_n, RFI n) + */ + +/* Type of each interrupt: */ + +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL + +/* Masks of interrupts for each type of interrupt: */ + +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F +#define XCHAL_INTTYPE_MASK_TIMER 0x00018040 +#define XCHAL_INTTYPE_MASK_NMI 0x00004000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800 +#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 +#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 +#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ + +#define XTHAL_TIMER_UNCONFIGURED -1 /* REVISIT: should be in hal.h */ +#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ +#define XCHAL_PROFILING_INTERRUPT 11 + +/* Interrupt numbers for levels at which only one interrupt is configured: */ + +#define XCHAL_INTLEVEL7_NUM 14 + +/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */ + +/* External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ + +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */ +#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */ +#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */ +#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */ +#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ +#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */ +#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */ +#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */ +#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */ +#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */ +#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */ +#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */ +#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */ +#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */ +#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */ +#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */ +#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */ + +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ + +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */ +#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */ +#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */ +#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */ +#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */ +#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */ +#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ +#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ +#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */ +#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */ +#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */ +#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */ +#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */ +#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */ +#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */ +#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */ +#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */ +#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */ +#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */ +#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */ + +/**************************************************************************** + * EXCEPTIONS and VECTORS + ****************************************************************************/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + * number: 1 == XEA1 (old) + * 2 == XEA2 (new) + * 0 == XEAX (extern) or TX + */ + +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x40000000 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0x50000000 +#define XCHAL_RESET_VECTOR0_PADDR 0x50000000 +#define XCHAL_RESET_VECTOR1_VADDR 0x40000400 +#define XCHAL_RESET_VECTOR1_PADDR 0x40000400 +#define XCHAL_RESET_VECTOR_VADDR 0x40000400 +#define XCHAL_RESET_VECTOR_PADDR 0x40000400 +#define XCHAL_USER_VECOFS 0x00000340 +#define XCHAL_USER_VECTOR_VADDR 0x40000340 +#define XCHAL_USER_VECTOR_PADDR 0x40000340 +#define XCHAL_KERNEL_VECOFS 0x00000300 +#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300 +#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300 +#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000 +#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0 +#define XCHAL_INTLEVEL4_VECOFS 0x00000200 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200 +#define XCHAL_INTLEVEL5_VECOFS 0x00000240 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240 +#define XCHAL_INTLEVEL6_VECOFS 0x00000280 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000002C0 +#define XCHAL_NMI_VECTOR_VADDR 0x400002C0 +#define XCHAL_NMI_VECTOR_PADDR 0x400002C0 +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + +/**************************************************************************** + * DEBUG MODULE + ****************************************************************************/ + +/* Misc */ + +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ + +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ + +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ + +#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */ + +/**************************************************************************** + * MMU + ****************************************************************************/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + * [autorefill] and protection) + * usable for an MMU-based OS + */ + +/* If none of the above last 5 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +/**************************************************************************** + * MPU + ****************************************************************************/ + +#define XCHAL_HAVE_MPU 0 +#define XCHAL_MPU_ENTRIES 0 + +#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ +#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/ +#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */ + +#define XCHAL_MPU_ALIGN_BITS 0 +#define XCHAL_MPU_ALIGN 0 + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + +#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_CORE_ISA_H */ diff --git a/arch/xtensa/include/esp32s2/irq.h b/arch/xtensa/include/esp32s2/irq.h new file mode 100644 index 0000000000..20c95b420c --- /dev/null +++ b/arch/xtensa/include/esp32s2/irq.h @@ -0,0 +1,495 @@ +/**************************************************************************** + * arch/xtensa/include/esp32s2/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H +#define __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Interrupt Matrix + * + * Features + * - Accepts 95 peripheral interrupt sources as input. + * - Generates 26 peripheral interrupt sources as output. + * - CPU NMI Interrupt Mask. + * - Queries current interrupt status of peripheral interrupt sources. + * + * Peripheral Interrupt Source + * + * ESP32S2 has 95 peripheral interrupt sources in total. 67 of 71 ESP32S2 + * peripheral interrupt sources can be allocated to either CPU. The four + * remaining peripheral interrupt sources are CPU-specific, two per CPU. + * + * - GPIO_INTERRUPT_PRO and GPIO_INTERRUPT_PRO_NMI can only be allocated to + * PRO_CPU. + * - GPIO_INTERRUPT_APP and GPIO_INTERRUPT_APP_NMI can only be allocated to + * APP_CPU. + * + * As a result, PRO_CPU and APP_CPU each have 69 peripheral interrupt + * sources. + */ + +/* PRO_INTR_STATUS_REG_0 */ + +#define ESP32S2_PERI_MAC 0 /* INTR_STATUS_REG_0, bit 0 */ +#define ESP32S2_PERI_MAC_NMI 1 /* INTR_STATUS_REG_0, bit 1 */ +#define ESP32S2_PERI_PWR 2 /* INTR_STATUS_REG_0, bit 2 */ +#define ESP32S2_PERI_BB 3 /* INTR_STATUS_REG_0, bit 3 */ +#define ESP32S2_PERI_BT_MAC 4 /* INTR_STATUS_REG_0, bit 4 */ +#define ESP32S2_PERI_BT_BB 5 /* INTR_STATUS_REG_0, bit 5 */ +#define ESP32S2_PERI_BT_BB_NMI 6 /* INTR_STATUS_REG_0, bit 6 */ +#define ESP32S2_PERI_RWBT 7 /* INTR_STATUS_REG_0, bit 7 */ +#define ESP32S2_PERI_RWBLE 8 /* INTR_STATUS_REG_0, bit 8 */ +#define ESP32S2_PERI_RWBT_NMI 9 /* INTR_STATUS_REG_0, bit 9 */ + +#define ESP32S2_PERI_RWBLE_NMI 10 /* INTR_STATUS_REG_0, bit 10 */ +#define ESP32S2_PERI_SLC0 11 /* INTR_STATUS_REG_0, bit 11 */ +#define ESP32S2_PERI_SLC1 12 /* INTR_STATUS_REG_0, bit 12 */ +#define ESP32S2_PERI_UHCI0 13 /* INTR_STATUS_REG_0, bit 13 */ +#define ESP32S2_PERI_UHCI1 14 /* INTR_STATUS_REG_0, bit 14 */ +#define ESP32S2_PERI_TG_T0_LEVEL 15 /* INTR_STATUS_REG_0, bit 15 */ +#define ESP32S2_PERI_TG_T1_LEVEL 16 /* INTR_STATUS_REG_0, bit 16 */ +#define ESP32S2_PERI_TG_WDT_LEVEL 17 /* INTR_STATUS_REG_0, bit 17 */ +#define ESP32S2_PERI_TG_LACT_LEVEL 18 /* INTR_STATUS_REG_0, bit 18 */ +#define ESP32S2_PERI_TG1_T0_LEVEL 19 /* INTR_STATUS_REG_0, bit 19 */ + +#define ESP32S2_PERI_TG1_T1_LEVEL 20 /* INTR_STATUS_REG_0, bit 20 */ +#define ESP32S2_PERI_TG1_WDT_LEVEL 21 /* INTR_STATUS_REG_0, bit 21 */ +#define ESP32S2_PERI_TG1_LACT_LEVEL 22 /* INTR_STATUS_REG_0, bit 22 */ +#define ESP32S2_PERI_GPIO_INT_PRO 23 /* INTR_STATUS_REG_0, bit 23 */ +#define ESP32S2_PERI_GPIO_INT_PRO_NMI 24 /* INTR_STATUS_REG_0, bit 24 */ +#define ESP32S2_PERI_GPIO_INT_APP 25 /* INTR_STATUS_REG_0, bit 25 */ +#define ESP32S2_PERI_GPIO_INT_APP_NMI 26 /* INTR_STATUS_REG_0, bit 26 */ +#define ESP32S2_PERI_DEDICATED_GPIO_IN 27 /* INTR_STATUS_REG_0, bit 27 */ +#define ESP32S2_PERI_INT_FROM_CPU0 28 /* INTR_STATUS_REG_0, bit 28 */ +#define ESP32S2_PERI_INT_FROM_CPU1 29 /* INTR_STATUS_REG_0, bit 29 */ + +#define ESP32S2_PERI_INT_FROM_CPU2 30 /* INTR_STATUS_REG_0, bit 30 */ +#define ESP32S2_PERI_INT_FROM_CPU3 31 /* INTR_STATUS_REG_0, bit 31 */ + +/* PRO_INTR_STATUS_REG_1 */ + +#define ESP32S2_PERI_SPI1 32 /* INTR_STATUS_REG_1, bit 0 */ +#define ESP32S2_PERI_SPI2 33 /* INTR_STATUS_REG_1, bit 1 */ +#define ESP32S2_PERI_SPI3 34 /* INTR_STATUS_REG_1, bit 2 */ +#define ESP32S2_PERI_I2S0 35 /* INTR_STATUS_REG_1, bit 3 */ +#define ESP32S2_PERI_I2S1 36 /* INTR_STATUS_REG_1, bit 4 */ +#define ESP32S2_PERI_UART 37 /* INTR_STATUS_REG_1, bit 5 */ +#define ESP32S2_PERI_UART1 38 /* INTR_STATUS_REG_1, bit 6 */ +#define ESP32S2_PERI_UART2 39 /* INTR_STATUS_REG_1, bit 7 */ +#define ESP32S2_PERI_SDIO_HOST 40 /* INTR_STATUS_REG_1, bit 8 */ +#define ESP32S2_PERI_PWM0 41 /* INTR_STATUS_REG_1, bit 9 */ + +#define ESP32S2_PERI_PWM1 42 /* INTR_STATUS_REG_1, bit 10 */ +#define ESP32S2_PERI_PWM2 43 /* INTR_STATUS_REG_1, bit 11 */ +#define ESP32S2_PERI_PWM3 44 /* INTR_STATUS_REG_1, bit 12 */ +#define ESP32S2_PERI_LEDC 45 /* INTR_STATUS_REG_1, bit 13 */ +#define ESP32S2_PERI_EFUSE 46 /* INTR_STATUS_REG_1, bit 14 */ +#define ESP32S2_PERI_CAN 47 /* INTR_STATUS_REG_1, bit 15 */ +#define ESP32S2_PERI_USB 48 /* INTR_STATUS_REG_1, bit 16 */ +#define ESP32S2_PERI_RTC_CORE 49 /* INTR_STATUS_REG_1, bit 17 */ +#define ESP32S2_PERI_RMT 50 /* INTR_STATUS_REG_1, bit 18 */ +#define ESP32S2_PERI_PCNT 51 /* INTR_STATUS_REG_1, bit 19 */ + +#define ESP32S2_PERI_I2C_EXT0 52 /* INTR_STATUS_REG_1, bit 20 */ +#define ESP32S2_PERI_I2C_EXT1 53 /* INTR_STATUS_REG_1, bit 21 */ +#define ESP32S2_PERI_RSA 54 /* INTR_STATUS_REG_1, bit 22 */ +#define ESP32S2_PERI_SHA 55 /* INTR_STATUS_REG_1, bit 23 */ +#define ESP32S2_PERI_AES 56 /* INTR_STATUS_REG_1, bit 24 */ +#define ESP32S2_PERI_SPI2_DMA 57 /* INTR_STATUS_REG_1, bit 25 */ +#define ESP32S2_PERI_SPI3_DMA 58 /* INTR_STATUS_REG_1, bit 26 */ +#define ESP32S2_PERI_WDG 59 /* INTR_STATUS_REG_1, bit 27 */ +#define ESP32S2_PERI_TIMER 60 /* INTR_STATUS_REG_1, bit 28 */ +#define ESP32S2_PERI_TIMER_INT2 61 /* INTR_STATUS_REG_1, bit 29 */ + +#define ESP32S2_PERI_TG_T0_EDGE 62 /* INTR_STATUS_REG_1, bit 30 */ +#define ESP32S2_PERI_TG_T1_EDGE 63 /* INTR_STATUS_REG_1, bit 31 */ + +/* PRO_INTR_STATUS_REG_2 */ + +#define ESP32S2_PERI_TG_WDT_EDGE 64 /* INTR_STATUS_REG_2, bit 0 */ +#define ESP32S2_PERI_TG_LACT_EDGE 65 /* INTR_STATUS_REG_2, bit 1 */ +#define ESP32S2_PERI_TG1_T0_EDGE 66 /* INTR_STATUS_REG_2, bit 2 */ +#define ESP32S2_PERI_TG1_T1_EDGE 67 /* INTR_STATUS_REG_2, bit 3 */ +#define ESP32S2_PERI_TG1_WDT_EDGE 68 /* INTR_STATUS_REG_2, bit 4 */ +#define ESP32S2_PERI_TG1_LACT_EDGE 69 /* INTR_STATUS_REG_2, bit 5 */ +#define ESP32S2_PERI_CACHE_IA 70 /* INTR_STATUS_REG_2, bit 6 */ +#define ESP32S2_PERI_SYSTIMER_TARGET0 71 /* INTR_STATUS_REG_2, bit 7 */ +#define ESP32S2_PERI_SYSTIMER_TARGET1 72 /* INTR_STATUS_REG_2, bit 8 */ +#define ESP32S2_PERI_SYSTIMER_TARGET2 73 /* INTR_STATUS_REG_2, bit 9 */ + +#define ESP32S2_PERI_ASSIST_DEBUG 74 /* INTR_STATUS_REG_2, bit 10 */ +#define ESP32S2_PERI_PMS_PRO_IRAM0_ILG 75 /* INTR_STATUS_REG_2, bit 11 */ +#define ESP32S2_PERI_PMS_PRO_DRAM0_ILG 76 /* INTR_STATUS_REG_2, bit 12 */ +#define ESP32S2_PERI_PMS_PRO_DPORT_ILG 77 /* INTR_STATUS_REG_2, bit 13 */ +#define ESP32S2_PERI_PMS_PRO_AHB_ILG 78 /* INTR_STATUS_REG_2, bit 14 */ +#define ESP32S2_PERI_PMS_PRO_CACHE_ILG 79 /* INTR_STATUS_REG_2, bit 15 */ +#define ESP32S2_PERI_PMS_DMA_APB_I_ILG 80 /* INTR_STATUS_REG_2, bit 16 */ +#define ESP32S2_PERI_PMS_DMA_RX_I_ILG 81 /* INTR_STATUS_REG_2, bit 17 */ +#define ESP32S2_PERI_PMS_DMA_TX_I_ILG 82 /* INTR_STATUS_REG_2, bit 18 */ +#define ESP32S2_PERI_SPI_MEM_REJECT 83 /* INTR_STATUS_REG_2, bit 19 */ + +#define ESP32S2_PERI_DMA_COPY 84 /* INTR_STATUS_REG_2, bit 20 */ +#define ESP32S2_PERI_SPI4_DMA 85 /* INTR_STATUS_REG_2, bit 21 */ +#define ESP32S2_PERI_SPI4 86 /* INTR_STATUS_REG_2, bit 22 */ +#define ESP32S2_PERI_DCACHE_PRELOAD 87 /* INTR_STATUS_REG_2, bit 23 */ +#define ESP32S2_PERI_ICACHE_PRELOAD 88 /* INTR_STATUS_REG_2, bit 24 */ +#define ESP32S2_PERI_APB_ADC 89 /* INTR_STATUS_REG_2, bit 25 */ +#define ESP32S2_PERI_CRYPTO_DMA 90 /* INTR_STATUS_REG_2, bit 26 */ +#define ESP32S2_PERI_CPU_PERI_ERR 91 /* INTR_STATUS_REG_2, bit 27 */ +#define ESP32S2_PERI_APB_PERI_ERR 92 /* INTR_STATUS_REG_2, bit 28 */ +#define ESP32S2_PERI_DCACHE_SYNC 93 /* INTR_STATUS_REG_2, bit 29 */ +#define ESP32S2_PERI_ICACHE_SYNC 94 /* INTR_STATUS_REG_2, bit 29 */ + +/* Total number of peripherals */ + +#define ESP32S2_NPERIPHERALS 95 + +/* Exceptions + * + * IRAM Offset Description + * 0x0000 Windows + * 0x0180 Level 2 interrupt + * 0x01c0 Level 3 interrupt + * 0x0200 Level 4 interrupt + * 0x0240 Level 5 interrupt + * 0x0280 Debug exception + * 0x02c0 NMI exception + * 0x0300 Kernel exception + * 0x0340 User exception + * 0x03c0 Double exception + * + * REVISIT: In more architectures supported by NuttX, exception errors + * tie into the normal interrupt handling via special IRQ numbers. + * It is still to be determined what will be done for the ESP32S2. + * + */ + +/* IRQ numbers for internal interrupts that are dispatched like peripheral + * interrupts + */ + +#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */ +#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */ +#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */ +#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */ + +#define XTENSA_NIRQ_INTERNAL 4 /* Number of dispatch internal interrupts */ +#define XTENSA_IRQ_FIRSTPERI 4 /* First peripheral IRQ number */ + +/* IRQ numbers for peripheral interrupts coming through the Interrupt + * Matrix. + */ + +#define ESP32S2_IRQ2PERIPH(irq) ((irq)-XTENSA_IRQ_FIRSTPERI) + +/* PRO_INTR_STATUS_REG_0 */ + +#define ESP32S2_IRQ_MAC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_MAC) +#define ESP32S2_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_MAC_NMI) +#define ESP32S2_IRQ_PWR (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWR) +#define ESP32S2_IRQ_BB (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BB) +#define ESP32S2_IRQ_BT_MAC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BT_MAC) +#define ESP32S2_IRQ_BT_BB (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BB) +#define ESP32S2_IRQ_BT_BB_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_BB_NMI) +#define ESP32S2_IRQ_RWBT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBT) +#define ESP32S2_IRQ_RWBLE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBLE) +#define ESP32S2_IRQ_RWBT_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBT_NMI) + +#define ESP32S2_IRQ_RWBLE_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RWBLE_NMI) +#define ESP32S2_IRQ_SLC0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SLC0) +#define ESP32S2_IRQ_SLC1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SLC1) +#define ESP32S2_IRQ_UHCI0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UHCI0) +#define ESP32S2_IRQ_UHCI1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UHCI1) +#define ESP32S2_IRQ_TG_T0_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T0_LEVEL) +#define ESP32S2_IRQ_TG_T1_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T1_LEVEL) +#define ESP32S2_IRQ_TG_WDT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_WDT_LEVEL) +#define ESP32S2_IRQ_TG_LACT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_LACT_LEVEL) +#define ESP32S2_IRQ_TG1_T0_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T0_LEVEL) + +#define ESP32S2_IRQ_TG1_T1_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T1_LEVEL) +#define ESP32S2_IRQ_TG1_WDT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_WDT_LEVEL) +#define ESP32S2_IRQ_TG1_LACT_LEVEL (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_LACT_LEVEL) +#define ESP32S2_IRQ_GPIO_INT_PRO (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_PRO) +#define ESP32S2_IRQ_GPIO_INT_PRO_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_PRO_NMI) +#define ESP32S2_IRQ_GPIO_INT_APP (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_APP) +#define ESP32S2_IRQ_GPIO_INT_APP_NMI (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_GPIO_INT_APP_NMI) +#define ESP32S2_IRQ_DEDICATED_GPIO_IN (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DEDICATED_GPIO_IN) +#define ESP32S2_IRQ_INT_FROM_CPU0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU0 +#define ESP32S2_IRQ_INT_FROM_CPU1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU1) + +#define ESP32S2_IRQ_INT_FROM_CPU2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU2) +#define ESP32S2_IRQ_INT_FROM_CPU3 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_INT_FROM_CPU3) + +#define ESP32_IRQ_SREG0 ESP32S2_IRQ_MAC +#define ESP32_NIRQS_SREG0 32 + +/* PRO_INTR_STATUS_REG_1 */ + +#define ESP32S2_IRQ_SPI1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI1) +#define ESP32S2_IRQ_SPI2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI2) +#define ESP32S2_IRQ_SPI3 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI3) +#define ESP32S2_IRQ_I2S0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2S0) +#define ESP32S2_IRQ_I2S1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2S1) +#define ESP32S2_IRQ_UART (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UART) +#define ESP32S2_IRQ_UART1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UART1) +#define ESP32S2_IRQ_UART2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_UART2) +#define ESP32S2_IRQ_SDIO_HOST (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SDIO_HOST) +#define ESP32S2_IRQ_PWM0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM0) + +#define ESP32S2_IRQ_PWM1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM1) +#define ESP32S2_IRQ_PWM2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM2) +#define ESP32S2_IRQ_PWM3 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PWM3) +#define ESP32S2_IRQ_LEDC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_LEDC) +#define ESP32S2_IRQ_EFUSE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_EFUSE) +#define ESP32S2_IRQ_CAN (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CAN) +#define ESP32S2_IRQ_USB (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_USB) +#define ESP32S2_IRQ_RTC_CORE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RTC_CORE) +#define ESP32S2_IRQ_RMT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RMT) +#define ESP32S2_IRQ_PCNT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PCNT) + +#define ESP32S2_IRQ_I2C_EXT0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2C_EXT0) +#define ESP32S2_IRQ_I2C_EXT1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_I2C_EXT1) +#define ESP32S2_IRQ_RSA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_RSA) +#define ESP32S2_IRQ_SHA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SHA) +#define ESP32S2_IRQ_AES (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_AES) +#define ESP32S2_IRQ_SPI2_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI2_DMA) +#define ESP32S2_IRQ_SPI3_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI3_DMA) +#define ESP32S2_IRQ_WDG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_WDG) +#define ESP32S2_IRQ_TIMER (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TIMER) +#define ESP32S2_IRQ_TIMER_INT2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TIMER_INT2) + +#define ESP32S2_IRQ_TG_T0_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T0_EDGE) +#define ESP32S2_IRQ_TG_T1_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_T1_EDGE) + +#define ESP32S2_IRQ_SREG1 ESP32S2_IRQ_SPI1 +#define ESP32S2_NIRQS_SREG1 32 + +/* PRO_INTR_STATUS_REG_2 */ + +#define ESP32S2_IRQ_TG_WDT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_WDT_EDGE) +#define ESP32S2_IRQ_TG_LACT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG_LACT_EDGE) +#define ESP32S2_IRQ_TG1_T0_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T0_EDGE) +#define ESP32S2_IRQ_TG1_T1_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_T1_EDGE) +#define ESP32S2_IRQ_TG1_WDT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_WDT_EDGE) +#define ESP32S2_IRQ_TG1_LACT_EDGE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_TG1_LACT_EDGE) +#define ESP32S2_IRQ_CACHE_IA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CACHE_IA) +#define ESP32S2_IRQ_SYSTIMER_TARGET0 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SYSTIMER_TARGET0) +#define ESP32S2_IRQ_SYSTIMER_TARGET1 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SYSTIMER_TARGET1) +#define ESP32S2_IRQ_SYSTIMER_TARGET2 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SYSTIMER_TARGET2) + +#define ESP32S2_IRQ_ASSIST_DEBUG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_ASSIST_DEBUG) +#define ESP32S2_IRQ_PMS_PRO_IRAM0_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_IRAM0_ILG) +#define ESP32S2_IRQ_PMS_PRO_DRAM0_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_DRAM0_ILG) +#define ESP32S2_IRQ_PMS_PRO_DPORT_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_DPORT_ILG) +#define ESP32S2_IRQ_PMS_PRO_AHB_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_AHB_ILG) +#define ESP32S2_IRQ_PMS_PRO_CACHE_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_PRO_CACHE_ILG) +#define ESP32S2_IRQ_PMS_DMA_APB_I_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_DMA_APB_I_ILG) +#define ESP32S2_IRQ_PMS_DMA_RX_I_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_DMA_RX_I_ILG) +#define ESP32S2_IRQ_PMS_DMA_TX_I_ILG (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_PMS_DMA_TX_I_ILG) +#define ESP32S2_IRQ_SPI_MEM_REJECT (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI_MEM_REJECT) + +#define ESP32S2_IRQ_DMA_COPY (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DMA_COPY) +#define ESP32S2_IRQ_SPI4_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI4_DMA) +#define ESP32S2_IRQ_SPI4 (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_SPI4) +#define ESP32S2_IRQ_DCACHE_PRELOAD (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DCACHE_PRELOAD) +#define ESP32S2_IRQ_ICACHE_PRELOAD (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_ICACHE_PRELOAD) +#define ESP32S2_IRQ_APB_ADC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_APB_ADC) +#define ESP32S2_IRQ_CRYPTO_DMA (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CRYPTO_DMA) +#define ESP32S2_IRQ_CPU_PERI_ERR (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_CPU_PERI_ERR) +#define ESP32S2_IRQ_APB_PERI_ERE (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_APB_PERI_ERR) +#define ESP32S2_IRQ_DCACHE_SYNC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_DCACHE_SYNC) +#define ESP32S2_IRQ_ICACHE_SYNC (XTENSA_IRQ_FIRSTPERI + ESP32S2_PERI_ICACHE_SYNC) + +#define ESP32S2_IRQ_SREG2 ESP32S2_IRQ_TG_WDT_EDGE +#define ESP32S2_NIRQS_SREG2 32 + +/* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */ + +#define ESP32S2_IRQ_SREG2 ESP32S2_IRQ_TG1_WDT_EDGE +#define ESP32S2_NIRQS_SREG2 5 + +#define ESP32S2_NIRQ_PERIPH ESP32S2_NPERIPHERALS + +/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched + * as a second level of decoding: The first level dispatches to the GPIO + * interrupt handler. The second to the decoded GPIO interrupt handler. + */ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +# define ESP32S2_NIRQ_GPIO 40 +# define ESP32S2_FIRST_GPIOIRQ (XTENSA_NIRQ_INTERNAL+ESP32S2_NIRQ_PERIPH) +# define ESP32S2_LAST_GPIOIRQ (ESP32S2_FIRST_GPIOIRQ+ESP32S2_NIRQ_GPIO-1) +# define ESP32S2_PIN2IRQ(p) ((p) + ESP32S2_FIRST_GPIOIRQ) +# define ESP32S2_IRQ2PIN(i) ((i) - ESP32S2_FIRST_GPIOIRQ) +#else +# define ESP32S2_NIRQ_GPIO 0 +#endif + +/* Total number of interrupts */ + +#define NR_IRQS (XTENSA_NIRQ_INTERNAL+ESP32S2_NIRQ_PERIPH+ESP32S2_NIRQ_GPIO) + +/* Xtensa CPU Interrupts. + * + * Each of the two CPUs (PRO and APP) have 32 interrupts each, of which + * 26 can be mapped to peripheral interrupts: + * + * Level triggered peripherals (21 total): + * 0-5, 8-9, 12-13, 17-18 - Priority 1 + * 19-21 - Priority 2 + * 23, 27 - Priority 3 + * 24-25 - Priority 4 + * 26, 31 - Priority 5 + * Edge triggered peripherals (4 total): + * 10 - Priority 1 + * 22 - Priority 3 + * 28, 30 - Priority 4 + * NMI (1 total): + * 14 - NMI + * + * CPU peripheral interrupts can be a assigned to a CPU interrupt using the + * PRO_*_MAP_REG or APP_*_MAP_REG. There are a pair of these registers for + * each peripheral source. Multiple peripheral interrupt sources can be + * mapped to the same CPU interrupt. + * + * The remaining, six, internal CPU interrupts are: + * + * 6 Timer0 - Priority 1 + * 7 Software - Priority 1 + * 11 Profiling - Priority 3 + * 15 Timer1 - Priority 3 + * 16 Timer2 - Priority 5 + * 29 Software - Priority 3 + * + * A peripheral interrupt can be disabled + */ + +#define ESP32S2_CPUINT_LEVELPERIPH_0 0 +#define ESP32S2_CPUINT_LEVELPERIPH_1 1 +#define ESP32S2_CPUINT_LEVELPERIPH_2 2 +#define ESP32S2_CPUINT_LEVELPERIPH_3 3 +#define ESP32S2_CPUINT_LEVELPERIPH_4 4 +#define ESP32S2_CPUINT_LEVELPERIPH_5 5 +#define ESP32S2_CPUINT_LEVELPERIPH_6 8 +#define ESP32S2_CPUINT_LEVELPERIPH_7 9 +#define ESP32S2_CPUINT_LEVELPERIPH_8 12 +#define ESP32S2_CPUINT_LEVELPERIPH_9 13 +#define ESP32S2_CPUINT_LEVELPERIPH_10 17 +#define ESP32S2_CPUINT_LEVELPERIPH_11 18 +#define ESP32S2_CPUINT_LEVELPERIPH_12 19 +#define ESP32S2_CPUINT_LEVELPERIPH_13 20 +#define ESP32S2_CPUINT_LEVELPERIPH_14 21 +#define ESP32S2_CPUINT_LEVELPERIPH_15 23 +#define ESP32S2_CPUINT_LEVELPERIPH_16 24 +#define ESP32S2_CPUINT_LEVELPERIPH_17 25 +#define ESP32S2_CPUINT_LEVELPERIPH_18 26 +#define ESP32S2_CPUINT_LEVELPERIPH_19 27 +#define ESP32S2_CPUINT_LEVELPERIPH_20 31 + +#define ESP32S2_CPUINT_NLEVELPERIPHS 21 +#define EPS32_CPUINT_LEVELSET 0x8fbe333f + +#define ESP32S2_CPUINT_EDGEPERIPH_0 10 +#define ESP32S2_CPUINT_EDGEPERIPH_1 22 +#define ESP32S2_CPUINT_EDGEPERIPH_2 28 +#define ESP32S2_CPUINT_EDGEPERIPH_3 30 + +#define ESP32S2_CPUINT_NEDGEPERIPHS 4 +#define EPS32_CPUINT_EDGESET 0x50400400 + +#define ESP32S2_CPUINT_NNMIPERIPHS 1 +#define EPS32_CPUINT_NMISET 0x00004000 + +#define ESP32S2_CPUINT_MAC 0 +#define ESP32S2_CPUINT_TIMER0 6 +#define ESP32S2_CPUINT_SOFTWARE0 7 +#define ESP32S2_CPUINT_PROFILING 11 +#define ESP32S2_CPUINT_TIMER1 15 +#define ESP32S2_CPUINT_TIMER2 16 +#define ESP32S2_CPUINT_SOFTWARE1 29 + +#define ESP32S2_CPUINT_NINTERNAL 6 + +#define ESP32S2_NCPUINTS 32 +#define ESP32S2_CPUINT_MAX (ESP32S2_NCPUINTS - 1) +#define ESP32_CPUINT_PERIPHSET 0xdffe773f +#define EPS32_CPUINT_INTERNALSET 0x200188c0 + +/* Priority 1: 0-10, 12-13, 17-18 (15) + * Priority 2: 19-21 (3) + * Priority 3: 11, 15, 22-23, 27, 29 (6) + * Priority 4: 24-25, 28, 30 (4) + * Priority 5: 16, 26, 31 (3) + * Priority NMI: 14 (1) + */ + +#define ESP32S2_INTPRI1_MASK 0x000637ff +#define ESP32S2_INTPRI2_MASK 0x00380000 +#define ESP32S2_INTPRI3_MASK 0x28c08800 +#define ESP32S2_INTPRI4_MASK 0x53000000 +#define ESP32S2_INTPRI5_MASK 0x84010000 +#define ESP32S2_INTNMI_MASK 0x00004000 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_IRQ_H */ diff --git a/arch/xtensa/include/esp32s2/memory_layout.h b/arch/xtensa/include/esp32s2/memory_layout.h new file mode 100644 index 0000000000..69a130f632 --- /dev/null +++ b/arch/xtensa/include/esp32s2/memory_layout.h @@ -0,0 +1,139 @@ +/**************************************************************************** + * arch/xtensa/include/esp32s2/memory_layout.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The heap overview: + * + * CONFIG_HEAP2_BASE eg. 3f80 0000 + * : + * : g_mmheap (CONFIG_ESP32_SPIRAM) + * : + * CONFIG_HEAP2_BASE + CONFIG_HEAP2_SIZE eg. 3fc0 0000 + * + * HEAP_REGION0_START 3ffa e6f0 + * : + * : g_mmheap region0 + * : + * HEAP_REGION0_END 3ffa fff0 + * : + * _sheap eg. 3ffc 8c6c + * : + * : g_mmheap region1 + * : + * HEAP_REGION1_END 3ffd fff0 + * : + * : ROM data + * : + *--------------------------------------------------------------------- + * + * HEAP_REGION2_START 3ffe 0450 + * : + * : g_iheap (CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP) + * : + * HEAP_REGION2_START + CONFIG_XTENSA_IMEM_REGION_SIZE + * : + * : g_mmheap region2 + * : + *--------------------------------------------------------------------- + * _eheap 4000 0000 + */ + +/* This region is supposed to be part of the ROM data. However, the ROM + * isn't using the last 6KB, so we get it as heap. It's called REGION0 + * because it starts before _sheap. + * Although this region is adjacent to 0x3ffb0000 (start of static memory) + * we don't add it to static memory but we add it as heap. The reason is the + * Bluetooth controller uses a fixed 64KB region at the start of 0x3ffb0000. + * It's cleaner, from a source code perspective, to start static memory at + * 0x3ffb0000 and get what's before that as heap. + */ + +#define HEAP_REGION0_START 0x3ffae6f0 +#define HEAP_REGION0_END 0x3ffafff0 + +/* Region 1 of the heap is the area from the end of the .data section to the + * beginning of the ROM data. The start address is defined from the linker + * script as "_sheap". The end is defined here, as follows: + */ + +#define HEAP_REGION1_END 0x3ffdfff0 + +/* Region 2 of the heap is the area from the end of the ROM data to the end + * of DRAM. The linker script has already set "_eheap" as the end of DRAM, + * the following defines the start of region2. + * N.B: That ROM data consists of 2 regions, one per CPU. If SMP is not + * enabled include APP's region with the heap. + * + * When an internal heap is enabled this region starts at an offset equal to + * the size of the internal heap. + * + * The QEMU bootloader image is slightly different than the chip's one. + * The ROM on PRO and APP CPUs uses different regions for static data. + * In QEMU, however, we load only one ROM binary, taken from the PRO CPU, + * and it is used by both CPUs. So, in QEMU, if we allocate PRO CPUs region + * early, it will be clobbered once the APP CPU starts. + * We can delay the allocation to when everything has started through the + * board_late_initiliaze hook, as is done for the APP data, however this + * should be fixed from QEMU side. The following macros, then, just skip + * PRO CPU's regions when a QEMU image generation is enabled with SMP. + */ + +#if defined(CONFIG_ESP32_QEMU_IMAGE) && defined(CONFIG_SMP) +# define HEAP_REGION2_START 0x3ffe7e40 +#else +# define HEAP_REGION2_START 0x3ffe0450 +#endif + +#ifdef CONFIG_SMP +# define HEAP_REGION2_END 0x3ffe3f10 +# define HEAP_REGION3_START 0x3ffe5240 +#endif + +#ifdef CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP +# define XTENSA_IMEM_REGION_SIZE CONFIG_XTENSA_IMEM_REGION_SIZE +#else +# define XTENSA_IMEM_REGION_SIZE 0 +#endif + +/* Internal heap starts at the end of the ROM data. + * This is either the start of region2 if SMP is disabled or start of region3 + * if SMP is enabled. + */ + +#ifndef CONFIG_SMP +# define ESP32_IMEM_START HEAP_REGION2_START +#else +# define ESP32_IMEM_START HEAP_REGION3_START +#endif + +/* Region of unused ROM App data */ + +#define HEAP_REGION_ROMAPP_START 0x3ffe4360 +#define HEAP_REGION_ROMAPP_END 0x3ffe5230 + diff --git a/arch/xtensa/include/esp32s2/tie-asm.h b/arch/xtensa/include/esp32s2/tie-asm.h new file mode 100644 index 0000000000..bc2ebb565d --- /dev/null +++ b/arch/xtensa/include/esp32s2/tie-asm.h @@ -0,0 +1,150 @@ +/**************************************************************************** + * arch/xtensa/include/esp32s2/tie-asm.h + * Compile-time assembler definitions dependent on CORE & TIE + * + * This header file contains assembly-language definitions (assembly + * macros, etc.) for this specific Xtensa processor's TIE extensions + * and options. It is customized to this Xtensa processor configuration. + * + * Customer ID=11657; Build=0x5fe96; + * Copyright (c) 1999-2016 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H +#define __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Selection parameter values for save-area save/restore macros: */ + +#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ +#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ +#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ + +/* Whether used automatically by compiler: */ + +#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ +#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ +#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ + +/* ABI handling across function calls: */ + +#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ +#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ +#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ +#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ + +/* Misc */ + +#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ +#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ + | ((ccuse) & XTHAL_SAS_ANYCC) \ + | ((abi) & XTHAL_SAS_ANYABI) ) + +/* Macro to store all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first + * XCHAL_NCP_NUM_ATMPS registers are clobbered, the + * remaining are unused). + * Optional parameters: + * continue If macro invoked as part of a larger store sequence, + * set to 1 if this is not the first in the sequence. + * Defaults to 0. + * ofs Offset from start of larger sequence (from value of first + * ptr in sequence) at which to store. Defaults to next + * available space (or 0 if is 0). + * select Select what category(ies) of registers to store, as a + * bitmask (see XTHAL_SAS_xxx constants). Defaults to all + * registers. + * alloc Select what category(ies) of registers to allocate; if + * any category is selected here that is not in , + * space for the corresponding registers is skipped without + * doing any load. + */ + +.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + + /* Optional global registers used by default by the compiler: */ + + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.THREADPTR \at1 /* threadptr option */ + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif +.endm /* xchal_ncp_load */ + +#define XCHAL_NCP_NUM_ATMPS 1 + +#define XCHAL_SA_NUM_ATMPS 1 + +#endif /* __ARCH_XTENSA_INCLUDE_ESP32S2_TIE_ASM_H */ diff --git a/arch/xtensa/include/esp32s2/tie.h b/arch/xtensa/include/esp32s2/tie.h new file mode 100644 index 0000000000..92208ee5c2 --- /dev/null +++ b/arch/xtensa/include/esp32s2/tie.h @@ -0,0 +1,194 @@ +/**************************************************************************** + * arch/xtensa/include/esp32s2/tie.h + * Compile-time HAL definitions dependent on CORE & TIE configuration + * + * NOTE: This header file is not meant to be included directly. + * + * This header file describes this specific Xtensa processor's TIE extensions + * that extend basic Xtensa core functionality. It is customized to this + * Xtensa processor configuration. + * + * Customer ID=11657; Build=0x5fe96; + * Copyright (c) 1999-2016 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************/ + +#ifndef _ARCH_XTENSA_INCLUDE_ESP32S2_TIE_H +#define _ARCH_XTENSA_INCLUDE_ESP32S2_TIE_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define XCHAL_CP_NUM 1 /* number of coprocessors */ +#define XCHAL_CP_MAX 1 /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK 0x01 /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ + +/* Basic parameters of each coprocessor: */ + +#define XCHAL_CP0_NAME "FPU" +#define XCHAL_CP0_IDENT FPU +#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */ +#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */ +#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */ + +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ + +#define XCHAL_CP1_SA_SIZE 0 +#define XCHAL_CP1_SA_ALIGN 1 +#define XCHAL_CP2_SA_SIZE 0 +#define XCHAL_CP2_SA_ALIGN 1 +#define XCHAL_CP3_SA_SIZE 0 +#define XCHAL_CP3_SA_ALIGN 1 +#define XCHAL_CP4_SA_SIZE 0 +#define XCHAL_CP4_SA_ALIGN 1 +#define XCHAL_CP5_SA_SIZE 0 +#define XCHAL_CP5_SA_ALIGN 1 +#define XCHAL_CP6_SA_SIZE 0 +#define XCHAL_CP6_SA_ALIGN 1 +#define XCHAL_CP7_SA_SIZE 0 +#define XCHAL_CP7_SA_ALIGN 1 + +/* Save area for non-coprocessor optional and custom (TIE) state: */ + +#define XCHAL_NCP_SA_SIZE 48 +#define XCHAL_NCP_SA_ALIGN 4 + +/* Total save area for optional and custom state (NCP + CPn): */ + +#define XCHAL_TOTAL_SA_SIZE 128 /* With 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 4 /* Actual minimum alignment */ + +/* Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) + * before expanding the XCHAL_xxx_SA_LIST() macros. + * + * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, + * dbnum,base,regnum,bitsz,gapsz,reset,x...) + * + * s = passed from XCHAL_*_LIST(s), eg. to select how to expand + * ccused = set if used by compiler without special options or code + * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) + * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) + * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) + * name = lowercase reg name (no quotes) + * galign = group byte alignment (power of 2) (galign >= align) + * align = register byte alignment (power of 2) + * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) + * (not including any pad bytes required to galign this or next reg) + * dbnum = unique target number f/debug (see ) + * base = reg shortname w/o index (or sr=special, ur=TIE user reg) + * regnum = reg index in regfile, or special/TIE-user reg number + * bitsz = number of significant bits (regfile width, or ur/sr mask bits) + * gapsz = intervening bits, if bitsz bits not stored contiguously + * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) + * reset = register reset value (or 0 if undefined at reset) + * x = reserved for future use (0 until then) + * + * To filter out certain registers, e.g. to expand only the non-global + * registers used by the compiler, you can do something like this: + * + * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) + * #define SELCC0(p...) + * #define SELCC1(abikind,p...) SELAK##abikind(p) + * #define SELAK0(p...) REG(p) + * #define SELAK1(p...) REG(p) + * #define SELAK2(p...) + * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ + * ...what you want to expand... + */ + +#define XCHAL_NCP_SA_NUM 12 +#define XCHAL_NCP_SA_LIST(s) \ + XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ + XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ + XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, f64r_lo, 4, 4, 4,0x03EA, ur,234, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, f64r_hi, 4, 4, 4,0x03EB, ur,235, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, f64s, 4, 4, 4,0x03EC, ur,236, 32,0,0,0) + +#define XCHAL_CP0_SA_NUM 18 +#define XCHAL_CP0_SA_LIST(s) \ + XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0) + +#define XCHAL_CP1_SA_NUM 0 +#define XCHAL_CP1_SA_LIST(s) /* empty */ + +#define XCHAL_CP2_SA_NUM 0 +#define XCHAL_CP2_SA_LIST(s) /* empty */ + +#define XCHAL_CP3_SA_NUM 0 +#define XCHAL_CP3_SA_LIST(s) /* empty */ + +#define XCHAL_CP4_SA_NUM 0 +#define XCHAL_CP4_SA_LIST(s) /* empty */ + +#define XCHAL_CP5_SA_NUM 0 +#define XCHAL_CP5_SA_LIST(s) /* empty */ + +#define XCHAL_CP6_SA_NUM 0 +#define XCHAL_CP6_SA_LIST(s) /* empty */ + +#define XCHAL_CP7_SA_NUM 0 +#define XCHAL_CP7_SA_LIST(s) /* empty */ + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ + +#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + +/* Byte length of instruction from its first byte, per FLIX. */ + +#define XCHAL_BYTE0_FORMAT_LENGTHS \ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + +#endif /* _ARCH_XTENSA_INCLUDE_ESP32S2_TIE_H */ diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index 54cb0ecfe0..9f20eb349f 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -55,6 +55,17 @@ # error Unknown LX6 implementation # endif +#elif CONFIG_ARCH_FAMILY_LX7 +# include + +/* Include implementation-specific IRQ definitions (including IRQ numbers) */ + +# ifdef CONFIG_ARCH_CHIP_ESP32S2 +# include +# else +# error Unknown LX7 implementation +# endif + #else # error Unknown XTENSA architecture #endif diff --git a/arch/xtensa/include/lx7/irq.h b/arch/xtensa/include/lx7/irq.h new file mode 100644 index 0000000000..222aebd46c --- /dev/null +++ b/arch/xtensa/include/lx7/irq.h @@ -0,0 +1,68 @@ +/**************************************************************************** + * arch/xtensa/include/lx7/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_XTENSA_INCLUDE_LX7_IRQ_H +#define __ARCH_XTENSA_INCLUDE_LX7_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_INCLUDE_LX7_IRQ_H */ diff --git a/arch/xtensa/include/xtensa/xtensa_coproc.h b/arch/xtensa/include/xtensa/xtensa_coproc.h index ecce93b2f2..0855b0cb50 100644 --- a/arch/xtensa/include/xtensa/xtensa_coproc.h +++ b/arch/xtensa/include/xtensa/xtensa_coproc.h @@ -38,7 +38,7 @@ * Included Files ****************************************************************************/ -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/Makefile b/arch/xtensa/src/Makefile index bdb5651709..b8e950e920 100644 --- a/arch/xtensa/src/Makefile +++ b/arch/xtensa/src/Makefile @@ -25,6 +25,10 @@ ifeq ($(CONFIG_ARCH_FAMILY_LX6),y) ARCH_SUBDIR = lx6 endif +ifeq ($(CONFIG_ARCH_FAMILY_LX7),y) +ARCH_SUBDIR = lx7 +endif + ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip} diff --git a/arch/xtensa/src/common/xtensa_coproc.S b/arch/xtensa/src/common/xtensa_coproc.S index 3b2b6bfe24..686f6c281c 100644 --- a/arch/xtensa/src/common/xtensa_coproc.S +++ b/arch/xtensa/src/common/xtensa_coproc.S @@ -128,7 +128,7 @@ _xtensa_coproc_savestate: bbci.l a2, 0, 2f /* CP 0 not enabled */ l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */ add a3, a14, a15 /* a3 = save area for CP 0 */ - xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL + xchal_ncp_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: #endif @@ -327,7 +327,7 @@ _xtensa_coproc_restorestate: bbci.l a2, 0, 2f /* CP 0 not enabled */ l32i a14, a13, 0 /* a14 = _xtensa_coproc_saoffsets[0] */ add a3, a14, a15 /* a3 = save area for CP 0 */ - xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL + xchal_ncp_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL 2: #endif diff --git a/arch/xtensa/src/esp32s2/Kconfig b/arch/xtensa/src/esp32s2/Kconfig new file mode 100644 index 0000000000..4ab9ce31ea --- /dev/null +++ b/arch/xtensa/src/esp32s2/Kconfig @@ -0,0 +1,911 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_ESP32S2 + +comment "ESP32S2 Configuration Options" + +choice + prompt "ESP32S2 Chip Selection" + default ARCH_CHIP_ESP32S2WROVER + depends on ARCH_CHIP_ESP32S2 + +config ARCH_CHIP_ESP32S2WROVER + bool "ESP32S2-WROVER" + select ESP32S2_ESP32S2DXWDXX + select ESP32S2_FLASH_4M + select ESP32S2_PSRAM_8M + ---help--- + Generic module with an embedded ESP32S2 + +endchoice # ESP32S2 Chip Selection + +choice + prompt "Instruction CACHE Size" + default ESP32S2_INSTRUCTION_CACHE_8KB + depends on ARCH_CHIP_ESP32S2 + +config ESP32S2_INSTRUCTION_CACHE_8KB + bool "8KB" + ---help--- + Use 8KB of SRAM as Instruction Cache + +config ESP32S2_INSTRUCTION_CACHE_16KB + bool "16KB" + ---help--- + Use 16KB of SRAM as Instruction Cache + +endchoice # ESP32S2 Instruction CACHE size + +choice + prompt "Instruction CACHE Size" + default ESP32S2_INSTRUCTION_CACHE_8KB + depends on ARCH_CHIP_ESP32S2 + +config ESP32S2_DATA_CACHE_0KB + bool "No DATA CACHE" + ---help--- + Use 8KB of SRAM as Data Cache + +config ESP32S2_DATA_CACHE_8KB + bool "8KB" + ---help--- + Use 8KB of SRAM as Data Cache + +config ESP32S2_DATA_CACHE_16KB + bool "16KB" + ---help--- + Use 16KB of SRAM as Data Cache + +endchoice # ESP32S2 Data CACHE size + +config ESP32S2_SINGLE_CPU + bool + default y + +config ESP32S2_FLASH_2M + bool + default n + +config ESP32S2_FLASH_4M + bool + default n + +config ESP32S2_FLASH_8M + bool + default n + +config ESP32S2_FLASH_16M + bool + default n + +config ESP32S2_FLASH_DETECT + bool "Auto-detect FLASH size" + default y + help + Auto detect flash size when flashing. + +config ESP32S2_PSRAM_8M + bool + default n + +config ESP32S2_ESP32S2SXWDXX + bool + default n + select ESP32S2_SINGLE_CPU + select ARCH_HAVE_I2CRESET + +choice ESP32S2_FLASH_MODE + prompt "SPI FLASH mode" + default ESP32S2_FLASH_MODE_DIO + help + These options control how many I/O pins are used for communication + with the attached SPI flash chip. + The option selected here is then used by esptool when flashing. + + config ESP32S2_FLASH_MODE_DIO + bool "Dual IO (DIO)" + + config ESP32S2_FLASH_MODE_DOUT + bool "Dual Output (DOUT)" + + config ESP32S2_FLASH_MODE_QIO + bool "Quad IO (QIO)" + + config ESP32S2_FLASH_MODE_QOUT + bool "Quad Output (QOUT)" + +endchoice # ESP32S2_FLASH_MODE + +choice ESP32S2_FLASH_FREQ + prompt "SPI FLASH frequency" + default ESP32S2_FLASH_FREQ_40M + help + SPI FLASH frequency + + config ESP32S2_FLASH_FREQ_80M + bool "80 MHz" + + config ESP32S2_FLASH_FREQ_40M + bool "40 MHz" + + config ESP32S2_FLASH_FREQ_26M + bool "26 MHz" + + config ESP32S2_FLASH_FREQ_20M + bool "20 MHz" + +endchoice # ESP32S2_FLASH_FREQ + +choice ESP32S2_DEFAULT_CPU_FREQ + prompt "CPU frequency" + default ESP32S2_DEFAULT_CPU_FREQ_240 + help + CPU frequency to be set on application startup. + + config ESP32S2_DEFAULT_CPU_FREQ_80 + bool "80 MHz" + config ESP32S2_DEFAULT_CPU_FREQ_160 + bool "160 MHz" + config ESP32S2_DEFAULT_CPU_FREQ_240 + bool "240 MHz" +endchoice # CPU frequency + +config ESP32S2_DEFAULT_CPU_FREQ_MHZ + int + default 80 if ESP32S2_DEFAULT_CPU_FREQ_80 + default 160 if ESP32S2_DEFAULT_CPU_FREQ_160 + default 240 if ESP32S2_DEFAULT_CPU_FREQ_240 + +choice + prompt "On-board Crystal Frequency" + default ESP32S2_XTAL_40MZ + +config ESP32S2_XTAL_40MZ + bool "40MHz" + +config ESP32S2_XTAL_26MHz + bool "26MHz" + +endchoice # On-board Crystal Frequency + +config ESP32S2_RT_TIMER + bool "Real-time Timer" + default n + +config ESP32S2_PARTITION + bool "ESP32S2 Partition" + default n + select ESP32S2_SPIFLASH + ---help--- + Decode esp-idf's partition file and initialize + partition by nuttx MTD. + +config ESP32S2_RUN_IRAM + bool "Run from IRAM" + default n + ---help--- + This loads all of NuttX inside IRAM. Used to test somewhat small + images that can fit entirely in IRAM. + +menu "ESP32S2 Peripheral Selection" + +config ESP32S2_UART + bool + default n + +config ESP32S2_TIMER + bool + default n + +config ESP32S2_WDT + bool + default n + +config ESP32S2_BT + bool "Bluetooth" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32S2_EFUSE + bool "EFUSE support" + default n + ---help--- + Enable ESP32S2 efuse support. + +config ESP32S2_I2C + bool + default n + +config ESP32S2_I2S0 + bool "I2S 0" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32S2_LEDC + bool "LED PWM (LEDC)" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32S2_PCNT + bool "Pulse Count Module (PCNT)" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32S2_RMT + bool "Remote Control Module (RMT)" + default n + depends on EXPERIMENTAL + ---help--- + No yet implemented + +config ESP32S2_RNG + bool "Random Number Generator (RNG)" + default n + select ARCH_HAVE_RNG + ---help--- + ESP32S2 supports a RNG that passed on Dieharder test suite. + +config ESP32S2_SPI + bool + default n + +config ESP32S2_SPIFLASH + bool "SPI Flash" + default n + select MTD + select MTD_BYTE_WRITE + select MTD_PARTITION + +config ESP32S2_SPI2 + bool "SPI 2" + default n + select ESP32S2_SPI + select ESP32S2_GPIO_IRQ + select SPI + +config ESP32S2_SPI3 + bool "SPI 3" + default n + select ESP32S2_SPI + select ESP32S2_GPIO_IRQ + select SPI + +config ESP32S2_SPIRAM + bool "SPI RAM Support" + default n + select ARCH_HAVE_HEAP2 + select XTENSA_IMEM_USE_SEPARATE_HEAP + +if ESP32S2_SPIRAM && SMP + +choice + prompt "How does SPIRAM share cache?" + default ESP32S2_MEMMAP_SPIRAM_CACHE_EVENODD + help + Selects the cache mode to CPU access the external memory. + + config ESP32S2_MEMMAP_SPIRAM_CACHE_EVENODD + bool "Pro CPU uses even 32 byte ranges, App uses odd ones" + config ESP32S2_MEMMAP_SPIRAM_CACHE_LOWHIGH + bool "Pro CPU uses low 2MB ranges, App uses high ones" +endchoice # CPU frequency + +endif + +config XTENSA_TIMER1 + bool "Xtensa Timer 1" + default n + +config XTENSA_TIMER2 + bool "Xtensa Timer 2" + default n + +config ESP32S2_TIMER0 + bool "64-bit Timer 0 (Group 0 Timer 0)" + default n + select ESP32S2_TIMER + ---help--- + Enables Timer + +config ESP32S2_TIMER1 + bool "64-bit Timer 1 (Group 0 Timer 1)" + default n + select ESP32S2_TIMER + ---help--- + Enables Timer + +config ESP32S2_TIMER2 + bool "64-bit Timer 2 (Group 1 Timer 0)" + default n + select ESP32S2_TIMER + ---help--- + Enables Timer + +config ESP32S2_TIMER3 + bool "64-bit Timer 3 (Group 1 Timer 1)" + default n + select ESP32S2_TIMER + ---help--- + Enables Timer + +config ESP32S2_MWDT0 + bool "Main System Watchdog Timer (Group 0)" + default n + select ESP32S2_WDT + ---help--- + Includes MWDT0. This watchdog timer is part of the Group 0 + timer submodule. + +config ESP32S2_MWDT1 + bool "Main System Watchdog Timer (Group 1)" + default n + select ESP32S2_WDT + ---help--- + Includes MWDT1. This watchdog timer is part of the Group 0 + timer submodule. + +config ESP32S2_RWDT + bool "RTC Watchdog Timer" + default n + select ESP32S2_WDT + ---help--- + Includes RWDT. This watchdog timer is from the RTC module. + When it is selected, if the developer sets it to reset on expiration + it will reset Main System and the RTC module. If you don't want + to have the RTC module reset, please, use the Timers' Module WDTs. + They will only reset Main System. + +config ESP32S2_UART0 + bool "UART 0" + default n + select ESP32S2_UART + select UART0_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config ESP32S2_UART1 + bool "UART 1" + default n + select ESP32S2_UART + select UART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config ESP32S2_UART2 + bool "UART 2" + default n + select ESP32S2_UART + select UART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config ESP32S2_WIRELESS + bool "Wireless" + default n + select NET + select ARCH_PHY_INTERRUPT + select ESP32S2_RNG + select ESP32S2_RT_TIMER + select ESP32S2_TIMER0 + ---help--- + Enable Wireless support + +config ESP32S2_I2C0 + bool "I2C 0" + default n + select ESP32S2_I2C + +config ESP32S2_I2C1 + bool "I2C 1" + default n + select ESP32S2_I2C + +config ESP32S2_AES_ACCELERATOR + bool "AES Accelerator" + default n + +endmenu # ESP32S2 Peripheral Selection + +menu "Memory Configuration" + +config ESP32S2_BT_RESERVE_DRAM + int "Reserved BT DRAM" + default 0 + +config ESP32S2_TRACEMEM_RESERVE_DRAM + int "Reserved trace memory DRAM" + default 0 + +config ESP32S2_ULP_COPROC_RESERVE_MEM + int "Reserved ULP co-processor DRAM" + default 0 + +endmenu # Memory Configuration + +config ESP32S2_GPIO_IRQ + bool "GPIO pin interrupts" + ---help--- + Enable support for interrupting GPIO pins + +menu "UART configuration" + depends on ESP32S2_UART + +if ESP32S2_UART0 + +config ESP32S2_UART0_TXPIN + int "UART0 Tx Pin" + default 43 + range 0 46 + +config ESP32S2_UART0_RXPIN + int "UART0 Rx Pin" + default 44 + range 0 46 + +if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +config ESP32S2_UART0_RTSPIN + int "UART0 RTS Pin" + default 22 + range 0 39 + +config ESP32S2_UART0_CTSPIN + int "UART0 CTS Pin" + default 19 + range 0 39 + +endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +endif # ESP32S2_UART0 + +if ESP32S2_UART1 + +config ESP32S2_UART1_TXPIN + int "UART1 Tx Pin" + default 10 + range 0 39 + +config ESP32S2_UART1_RXPIN + int "UART1 Rx Pin" + default 9 + range 0 39 + +if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +config ESP32S2_UART1_RTSPIN + int "UART1 RTS Pin" + default 11 + range 0 39 + +config ESP32S2_UART1_CTSPIN + int "UART1 CTS Pin" + default 6 + range 0 39 + +endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +endif # ESP32S2_UART1 + +if ESP32S2_UART2 + +config ESP32S2_UART2_TXPIN + int "UART2 Tx Pin" + default 17 + range 0 39 + +config ESP32S2_UART2_RXPIN + int "UART2 Rx Pin" + default 16 + range 0 39 + +if SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +config ESP32S2_UART2_RTSPIN + int "UART2 RTS Pin" + default 7 + range 0 39 + +config ESP32S2_UART2_CTSPIN + int "UART2 CTS Pin" + default 8 + range 0 39 + +endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL +endif # ESP32S2_UART2 + +endmenu # UART configuration + +menu "I2C configuration" + depends on ESP32S2_I2C + +if ESP32S2_I2C0 + +config ESP32S2_I2C0_SCLPIN + int "I2C0 SCL Pin" + default 22 + range 0 39 + +config ESP32S2_I2C0_SDAPIN + int "I2C0 SDA Pin" + default 23 + range 0 39 + +endif # ESP32S2_I2C0 + +if ESP32S2_I2C1 + +config ESP32S2_I2C1_SCLPIN + int "I2C1 SCL Pin" + default 26 + range 0 39 + +config ESP32S2_I2C1_SDAPIN + int "I2C1 SDA Pin" + default 25 + range 0 39 + +endif # ESP32S2_I2C1 + +endmenu # I2C configuration + +menu "SPI configuration" + depends on ESP32S2_SPI + +config ESP32S2_SPI_SWCS + bool "SPI software CS" + default y + ---help--- + Use SPI software CS. + +config ESP32S2_SPI_UDCS + bool "User defined CS" + default n + depends on ESP32S2_SPI_SWCS + ---help--- + Use user defined CS. + +config ESP32S2_SPI2_DMA + bool "SPI2 use DMA" + default y + depends on ESP32S2_SPI2 + +config ESP32S2_SPI3_DMA + bool "SPI3 use DMA" + default y + depends on ESP32S2_SPI3 + +config SPI_DMADESC_NUM + int "SPI master DMA description number" + default 2 + +config SPI_SLAVE_BUFSIZE + int "SPI slave buffer size" + default 2048 + depends on SPI_SLAVE + +config ESP32S2_SPI_DMATHRESHOLD + int "SPI DMA threshold" + default 64 + depends on ESP32S2_SPI2_DMA || ESP32S2_SPI3_DMA + ---help--- + When SPI DMA is enabled, DMA transfers whose size are below the + defined threshold will be performed by polling logic. + +if ESP32S2_SPI2 + +config ESP32S2_SPI2_CSPIN + int "SPI2 CS Pin" + default 15 + range 0 39 + +config ESP32S2_SPI2_CLKPIN + int "SPI2 CLK Pin" + default 14 + range 0 39 + +config ESP32S2_SPI2_MOSIPIN + int "SPI2 MOSI Pin" + default 13 + range 0 39 + +config ESP32S2_SPI2_MISOPIN + int "SPI2 MISO Pin" + default 12 + range 0 39 + +endif # ESP32S2_SPI2 + +if ESP32S2_SPI3 + +config ESP32S2_SPI3_CSPIN + int "SPI3 CS Pin" + default 5 + range 0 39 + +config ESP32S2_SPI3_CLKPIN + int "SPI3 CLK Pin" + default 18 + range 0 39 + +config ESP32S2_SPI3_MOSIPIN + int "SPI3 MOSI Pin" + default 23 + range 0 39 + +config ESP32S2_SPI3_MISOPIN + int "SPI3 MISO Pin" + default 19 + range 0 39 + +endif # ESP32S2_SPI3 + +endmenu # ESP32S2_SPI + +menu "SPI Flash configuration" + depends on ESP32S2_SPIFLASH + +config ESP32S2_MTD_OFFSET + hex "MTD base address in SPI Flash" + default 0x180000 + help + MTD base address in SPI Flash. + +config ESP32S2_MTD_SIZE + hex "MTD size in SPI Flash" + default 0x100000 + help + MTD size in SPI Flash. + +config ESP32S2_SPIFLASH_DEBUG + bool "Debug SPI Flash" + default n + depends on DEBUG_FS_INFO + help + Enable this option, read and write of SPI Flash + will show input arguments and result. + +endmenu # ESP32S2_SPIFLASH + +menu "SPI RAM Config" + depends on ESP32S2_SPIRAM + +choice ESP32S2_SPIRAM_TYPE + prompt "Type of SPI RAM chip in use" + default ESP32S2_SPIRAM_TYPE_AUTO + +config ESP32S2_SPIRAM_TYPE_AUTO + bool "Auto-detect" + +config ESP32S2_SPIRAM_TYPE_ESPPSRAM32 + bool "ESP-PSRAM32 or IS25WP032" + +config ESP32S2_SPIRAM_TYPE_ESPPSRAM64 + bool "ESP-PSRAM64 or LY68L6400" +endchoice #ESP32S2_SPIRAM_TYPE + +config ESP32S2_SPIRAM_SIZE + int + default -1 if ESP32S2_SPIRAM_TYPE_AUTO + default 4194304 if ESP32S2_SPIRAM_TYPE_ESPPSRAM32 + default 8388608 if ESP32S2_SPIRAM_TYPE_ESPPSRAM64 + default 0 + +choice ESP32S2_SPIRAM_SPEED + prompt "Set RAM clock speed" + default ESP32S2_SPIRAM_SPEED_40M + help + Select the speed for the SPI RAM chip. + +config ESP32S2_SPIRAM_SPEED_40M + bool "40MHz clock speed" + +config ESP32S2_SPIRAM_SPEED_80M + bool "80MHz clock speed" + +endchoice # ESP32S2_SPIRAM_SPEED + +config ESP32S2_SPIRAM_BOOT_INIT + bool "Initialize SPI RAM during startup" + depends on ESP32S2_SPIRAM + default "y" + help + If this is enabled, the SPI RAM will be enabled during initial + boot. Unless you have specific requirements, you'll want to leave + this enabled so memory allocated during boot-up can also be + placed in SPI RAM. + +config ESP32S2_SPIRAM_IGNORE_NOTFOUND + bool "Ignore PSRAM when not found" + default "n" + depends on ESP32S2_SPIRAM_BOOT_INIT && !BOOT_SDRAM_DATA + help + Normally, if psram initialization is enabled during compile time + but not found at runtime, it is seen as an error making the CPU + panic. If this is enabled, booting will complete but no PSRAM + will be available. + +config ESP32S2_SPIRAM_2T_MODE + bool "Enable SPI PSRAM 2T mode" + depends on ESP32S2_SPIRAM + default "n" + help + Enable this option to fix single bit errors inside 64Mbit PSRAM. + Some 64Mbit PSRAM chips have a hardware issue in the RAM which + causes bit errors at multiple fixed bit positions. + Note: If this option is enabled, the 64Mbit PSRAM chip will appear + to be 32Mbit in size. + Applications will not be affected unless the use the esp_himem + APIs, which are not supported in 2T mode. + +config ESP32S2_SPIRAM_BANKSWITCH_ENABLE + bool "Enable bank switching for >4MiB external RAM" + default y + help + The ESP32S2 only supports 4MiB of external RAM in its address + space. The hardware does support larger memories, but these + have to be bank-switched in and out of this address space. + Enabling this allows you to reserve some MMU pages for this, + which allows the use of the esp_himem api to manage these + banks. + #Note that this is limited to 62 banks, as + #esp_spiram_writeback_cache needs some kind of mapping of + #some banks below that mark to work. We cannot at this + #moment guarantee this to exist when himem is enabled. + If spiram 2T mode is enabled, the size of 64Mbit psram will + be changed as 32Mbit, so himem will be unusable. + +config SPIRAM_BANKSWITCH_RESERVE + int "Amount of 32K pages to reserve for bank switching" + depends on ESP32S2_SPIRAM_BANKSWITCH_ENABLE + default 8 + range 1 62 + help + Select the amount of banks reserved for bank switching. Note + that the amount of RAM allocatable with malloc will decrease + by 32K for each page reserved here. + Note that this reservation is only actually done if your + program actually uses the himem API. Without any himem + calls, the reservation is not done and the original amount + of memory will be available. + +endmenu #SPI RAM Config + +menu "WiFi configuration" + depends on ESP32S2_WIRELESS + +choice + prompt "ESP32S2 WiFi mode" + default ESP32S2_WIFI_STATION + +config ESP32S2_WIFI_STATION + bool "Station mode" + +config ESP32S2_WIFI_SOFTAP + bool "SoftAP mode" + +config ESP32S2_WIFI_STATION_SOFTAP_COEXISTENCE + bool "Station + SoftAP coexistence" + +endchoice # ESP32S2 WiFi mode + +config ESP32S2_WIFI_STATIC_RXBUF_NUM + int "WiFi static RX buffer number" + default 10 + +config ESP32S2_WIFI_DYNAMIC_RXBUF_NUM + int "WiFi dynamic RX buffer number" + default 32 + +config ESP32S2_WIFI_DYNAMIC_TXBUF_NUM + int "WiFi dynamic TX buffer number" + default 32 + +config ESP32S2_WIFI_TX_AMPDU + bool "WiFi TX AMPDU" + default y + +config ESP32S2_WIFI_RX_AMPDU + bool "WiFi RX AMPDU" + default y + +config ESP32S2_WIFI_RXBA_AMPDU_WZ + int "WiFi RX BA AMPDU windown size" + default 6 + +config ESP32S2_WLAN_PKTBUF_NUM + int "WLAN netcard packet buffer number per netcard" + default 16 + +config ESP32S2_WIFI_CONNECT_TIMEOUT + int "Connect timeout by second" + default 10 + help + Max waiting time of connecting to AP. + +config ESP32S2_WIFI_SCAN_RESULT_SIZE + int "Scan result buffer" + default 4096 + help + Maximum scan result buffer size. + +config ESP32S2_WIFI_SAVE_PARAM + bool "Save WiFi Parameters" + default n + help + If you enable this option, WiFi adapter parameters will be saved + into the file system instead of computing them each time. + + These parameters mainly contains: + - SSID + - Password + - BSSID + - PMK(compute when connecting) + - Author mode + - MAC address + - WiFi hardware configuration parameters + +config ESP32S2_WIFI_FS_MOUNTPT + string "Save WiFi Parameters" + default "/mnt/esp/wifi" + depends on ESP32S2_WIFI_SAVE_PARAM + help + Mount point of WiFi storage file system. + +endmenu # ESP32S2_WIRELESS + +menu "Real-Time Timer" + depends on ESP32S2_RT_TIMER + +config ESP32S2_RT_TIMER_TASK_NAME + string "Timer task name" + default "rt_timer" + +config ESP32S2_RT_TIMER_TASK_PRIORITY + int "Timer task priority" + default 223 # Lower than high priority workqueue + +config ESP32S2_RT_TIMER_TASK_STACK_SIZE + int "Timer task stack size" + default 2048 + +endmenu # Real-Time Timer + +if ESP32S2_TIMER +menu "Timer/counter Configuration" + +config ESP32S2_ONESHOT + bool "One-shot wrapper" + default n + ---help--- + Enable a wrapper around the low level timer/counter functions to + support one-shot timer. + +endmenu # Timer/counter Configuration +endif # ESP32S2_TIMER + +menu "Partition Configuration" + depends on ESP32S2_PARTITION + +config ESP32S2_PARTITION_OFFSET + hex "Partition offset" + default "0x8000" + +config ESP32S2_PARTITION_MOUNT + string "Partition mount point" + default "/dev/esp/partition/" + +endmenu # ESP32S2_PARTITION + +menu "AES accelerate" + depends on ESP32S2_AES_ACCELERATOR + +config ESP32S2_AES_ACCELERATOR_TEST + bool "AES driver test" + default n + +endmenu # ESP32S2_AES_ACCELERATOR + +endif # ARCH_CHIP_ESP32S2 diff --git a/arch/xtensa/src/esp32s2/Make.defs b/arch/xtensa/src/esp32s2/Make.defs new file mode 100644 index 0000000000..539b421444 --- /dev/null +++ b/arch/xtensa/src/esp32s2/Make.defs @@ -0,0 +1,87 @@ +############################################################################ +# arch/xtensa/src/esp32s2/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# The start-up, "head", file. May be either a .S or a .c file. + +HEAD_ASRC = xtensa_vectors.S xtensa_window_vector.S xtensa_windowspill.S +HEAD_ASRC += xtensa_int_handlers.S xtensa_user_handler.S +HEAD_CSRC = esp32s2_start.c + +# Common XTENSA files (arch/xtensa/src/common) + +CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S xtensa_panic.S +CMN_ASRCS += xtensa_sigtramp.S + +CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c +CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c +CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c +CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c +CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c +CMN_CSRCS += xtensa_puts.c xtensa_releasepending.c xtensa_releasestack.c +CMN_CSRCS += xtensa_reprioritizertr.c xtensa_schedsigaction.c +CMN_CSRCS += xtensa_sigdeliver.c xtensa_stackframe.c xtensa_udelay.c +CMN_CSRCS += xtensa_unblocktask.c xtensa_usestack.c +CMN_CSRCS += esp32s2_systemreset.c + +# Configuration-dependent common XTENSA files + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) + CMN_CSRCS += esp32s2_idle.c +endif + +ifeq ($(CONFIG_DEBUG_ALERT),y) + CMN_CSRCS += xtensa_dumpstate.c +endif + +ifeq ($(CONFIG_XTENSA_DUMPBT_ON_ASSERT),y) + CMN_ASRCS += xtensa_backtrace.S +endif + +ifeq ($(CONFIG_SPINLOCK),y) + CMN_CSRCS += xtensa_testset.c +endif + +ifeq ($(CONFIG_STACK_COLORATION),y) + CMN_CSRCS += xtensa_checkstack.c +endif + +ifeq ($(CONFIG_FS_HOSTFS),y) + CMN_ASRCS += xtensa_simcall.S + CMN_CSRCS += xtensa_hostfs.c +endif + +# Required ESP32S2 files (arch/xtensa/src/lx7) + +CHIP_CSRCS = esp32s2_allocateheap.c esp32s2_clockconfig.c esp32s2_cpuint.c +CHIP_CSRCS += esp32s2_gpio.c esp32s2_intdecode.c esp32s2_irq.c esp32s2_region.c +CHIP_CSRCS += esp32s2_timerisr.c esp32s2_user.c esp32s2_rtc.c +CHIP_CSRCS += esp32s2_lowputc.c + +# Configuration-dependent ESP32S2 files + +ifeq ($(CONFIG_ESP32S2_UART),y) +CMN_CSRCS += esp32s2_serial.c +endif + +ifeq ($(CONFIG_ARCH_USE_MODULE_TEXT),y) +CHIP_CSRCS += esp32s2_modtext.c +CMN_ASRCS += xtensa_loadstore.S +endif + diff --git a/arch/xtensa/src/esp32s2/chip_macros.h b/arch/xtensa/src/esp32s2/chip_macros.h new file mode 100644 index 0000000000..5684e7a5a7 --- /dev/null +++ b/arch/xtensa/src/esp32s2/chip_macros.h @@ -0,0 +1,107 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/chip_macros.h + * + * Adapted from use in NuttX by: + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Derives from logic originally provided by Cadence Design Systems Inc. + * + * Copyright (c) 2006-2015 Cadence Design Systems Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_CHIP_MACROS_H +#define __ARCH_XTENSA_SRC_ESP32S2_CHIP_MACROS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* This is the name of the section containing the Xtensa low level handlers + * that is used by the board linker scripts. + */ + +#define HANDLER_SECTION .iram1 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __ASSEMBLY__ + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Assembly Language Macros + ****************************************************************************/ + +#ifdef __ASSEMBLY__ + +/* Macro to get the current core ID. Only uses the reg given as an argument. + * Reading PRID on the ESP108 architecture gives us 0xcdcd on the PRO + * processor and 0xabab on the APP CPU. We distinguish between the two by + * simply checking bit 1: it's 1 on the APP and 0 on the PRO processor. + */ + + .macro getcoreid reg + rsr.prid \reg + bbci \reg, 1, 1f + movi \reg, 1 + j 2f +1: + movi \reg, 0 +2: + .endm + +#endif /* __ASSEMBLY */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_ESP32S2_CHIP_MACROS_H */ diff --git a/arch/xtensa/src/esp32s2/chip_memory.h b/arch/xtensa/src/esp32s2/chip_memory.h new file mode 100644 index 0000000000..f418427b7e --- /dev/null +++ b/arch/xtensa/src/esp32s2/chip_memory.h @@ -0,0 +1,68 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/chip_memory.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_CHIP_MEMORY_H +#define __ARCH_XTENSA_SRC_ESP32S2_CHIP_MEMORY_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/esp32s2_soc.h" + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: xtensa_sp_sane + ****************************************************************************/ + +static inline bool xtensa_sp_sane(uint32_t sp) +{ + return (esp32s2_sp_dram(sp) && ((sp & 0x0f) == 0)); +} + +/**************************************************************************** + * Name: xtensa_ptr_extram + ****************************************************************************/ + +static inline bool xtensa_ptr_exec(const void *p) +{ + return esp32s2_ptr_exec(p); +} + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_ESP32S2_CHIP_MEMORY_H */ + diff --git a/arch/xtensa/src/esp32s2/esp32s2_allocateheap.c b/arch/xtensa/src/esp32s2/esp32s2_allocateheap.c new file mode 100644 index 0000000000..6922588007 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_allocateheap.c @@ -0,0 +1,83 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_allocateheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + ****************************************************************************/ + +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +{ + board_autoled_on(LED_HEAPALLOCATE); + + *heap_start = (FAR void *)&_sheap; + DEBUGASSERT(HEAP_REGION1_END > (uintptr_t)*heap_start); + *heap_size = (size_t)(HEAP_REGION1_END - (uintptr_t)*heap_start); +} + +/**************************************************************************** + * Name: xtensa_add_region + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void xtensa_add_region(void) +{ +} +#endif diff --git a/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c new file mode 100644 index 0000000000..f2f0be57eb --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c @@ -0,0 +1,325 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_clockconfig.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "xtensa.h" +#include "xtensa_attr.h" +#include "hardware/esp32s2_soc.h" +#include "hardware/esp32s2_uart.h" +#include "hardware/esp32s2_rtccntl.h" +#include "hardware/esp32s2_system.h" +#include "esp32s2_rtc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef CONFIG_ESP_CONSOLE_UART_NUM +#define CONFIG_ESP_CONSOLE_UART_NUM 0 +#endif + +#define DEFAULT_CPU_FREQ 80 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +enum cpu_freq_e +{ + CPU_80M = 0, + CPU_160M = 1, + CPU_240M = 2, +}; + +enum cpu_clksrc_e +{ + XTAL_CLK, + PLL_CLK, + RTC8M_CLK, + APLL_CLK +}; + +enum pll_freq_e +{ + PLL_320, + PLL_480 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_cpuclksrc + * + * Description: + * Select a clock source for CPU clock. + * + * Input Parameters: + * src - Any source from cpu_clksrc_e. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void esp32s2_cpuclksrc(enum cpu_clksrc_e src) +{ + uint32_t value; + value = VALUE_TO_FIELD(src, SYSTEM_SOC_CLK_SEL); + modifyreg32(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL_M, value); +} + +/**************************************************************************** + * Name: esp32s2_cpudiv + * + * Description: + * Select a divider for the CPU clk. + * NOTE: The divider is not necessarily the real divisor. See TRM for the + * equivalences. + * + * Input Parameters: + * divider - A value between 0 to 2. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void esp32s2_cpudiv(uint8_t divider) +{ + uint32_t value; + value = VALUE_TO_FIELD(divider, SYSTEM_CPUPERIOD_SEL); + modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL_M, value); +} + +/**************************************************************************** + * Name: esp32s2_pllfreqsel + * + * Description: + * Select the PLL frequency. + * + * Input Parameters: + * freq - Any clock from enum pll_freq_e + * + * Returned Value: + * None + ****************************************************************************/ + +static inline void esp32s2_pllfreqsel(enum pll_freq_e freq) +{ + uint32_t value; + value = VALUE_TO_FIELD(freq, SYSTEM_PLL_FREQ_SEL); + modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL_M, value); +} + +/**************************************************************************** + * Name: esp32s2_uart_tx_wait_idle + * + * Description: + * Wait until uart tx full empty and the last char send ok. + * + * Input Parameters: + * uart_no - 0 for UART0, 1 for UART1, 2 for UART2 + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void esp32s2_uart_tx_wait_idle(uint8_t uart_no) +{ + uint32_t status; + do + { + status = getreg32(UART_STATUS_REG(uart_no)); + + /* tx count is non-zero */ + } + while ((status & UART_TXFIFO_CNT_M) != 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +extern uint32_t g_ticks_per_us; + +/**************************************************************************** + * Name: esp32s2_update_cpu_freq + * + * Description: + * Set the real CPU ticks per us to the ets, so that ets_delay_us + * will be accurate. Call this function when CPU frequency is changed. + * + * Input Parameters: + * ticks_per_us - CPU ticks per us + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_update_cpu_freq(uint32_t ticks_per_us) +{ + /* Update scale factors used by esp_rom_delay_us */ + + g_ticks_per_us = ticks_per_us; +} + +/**************************************************************************** + * Name: esp32s2_set_cpu_freq + * + * Description: + * Switch to one of PLL-based frequencies. + * + * Input Parameters: + * cpu_freq_mhz - Target CPU frequency + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_set_cpu_freq(int cpu_freq_mhz) +{ + uint32_t dbias; + uint32_t value; + switch (cpu_freq_mhz) + { + case 80: + /* 80 MHz is obtained from the 480 MHz PLL. + * In this case CPU_CLK = PLL_CLK / 6. Config the PLL as 480 MHz + * with a 6 divider and set the source clock as PLL_CLK. + */ + + dbias = DIG_DBIAS_80M_160M; + esp32s2_cpudiv(0); + break; + + case 160: + /* 160 MHz is obtained from the 480 MHz PLL. + * In this case CPU_CLK = PLL_CLK / 3. Config the PLL as 480 MHz + * with a 3 divider and set the source clock as PLL_CLK. + */ + + dbias = DIG_DBIAS_80M_160M; + esp32s2_cpudiv(1); + break; + + case 240: + /* 160 MHz is obtained from the 480 MHz PLL. + * In this case CPU_CLK = PLL_CLK / 2. Config the PLL as 480 MHz + * with a 2 divider and set the source clock as PLL_CLK. + */ + + dbias = DIG_DBIAS_240M; + esp32s2_cpudiv(2); + break; + + default: + + /* Unsupported clock config. */ + + return; + } + + value = (((80 * MHZ) >> 12) & UINT16_MAX) | + ((((80 * MHZ) >> 12) & UINT16_MAX) << 16); + esp32s2_pllfreqsel(PLL_480); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias); + esp32s2_cpuclksrc(PLL_CLK); + putreg32(value, RTC_APB_FREQ_REG); + esp32s2_update_cpu_freq(cpu_freq_mhz); +} + +/**************************************************************************** + * Name: esp32s2_clockconfig + * + * Description: + * Called to initialize the ESP32S2. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void esp32s2_clockconfig(void) +{ + /* Wait for the TX FIFO to unload data */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) + esp32s2_uart_tx_wait_idle(0); +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) + esp32s2_uart_tx_wait_idle(1); +#endif + + /* Configure the CPU frequency */ + + esp32s2_set_cpu_freq(CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ); +} + +/**************************************************************************** + * Name: esp_clk_cpu_freq + * + * Description: + * Get CPU frequency + * + * Input Parameters: + * None + * + * Returned Value: + * CPU frequency + * + ****************************************************************************/ + +int IRAM_ATTR esp_clk_cpu_freq(void) +{ + return g_ticks_per_us * MHZ; +} + +/**************************************************************************** + * Name: esp_clk_apb_freq + * + * Description: + * Return current APB clock frequency. + * + * Input Parameters: + * None + * + * Returned Value: + * APB clock frequency, in Hz + * + ****************************************************************************/ + +int IRAM_ATTR esp_clk_apb_freq(void) +{ + return MIN(g_ticks_per_us, 80) * MHZ; +} + diff --git a/arch/xtensa/src/esp32s2/esp32s2_clockconfig.h b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.h new file mode 100644 index 0000000000..a0f05b109b --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.h @@ -0,0 +1,112 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_clockconfig.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_update_cpu_freq + * + * Description: + * Set the real CPU ticks per us to the ets, so that ets_delay_us + * will be accurate. Call this function when CPU frequency is changed. + * + * Input Parameters: + * ticks_per_us - CPU ticks per us + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_update_cpu_freq(uint32_t ticks_per_us); + +/**************************************************************************** + * Name: esp32s2_set_cpu_freq + * + * Description: + * Switch to one of PLL-based frequencies. + * Current frequency can be XTAL or PLL. + * + * Input Parameters: + * cpu_freq_mhz - new CPU frequency + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_set_cpu_freq(int cpu_freq_mhz); + +/**************************************************************************** + * Name: esp32s2_clockconfig + * + * Description: + * Called to initialize the ESP32S2. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void esp32s2_clockconfig(void); + +/**************************************************************************** + * Name: esp_clk_cpu_freq + * + * Description: + * Get CPU frequency + * + * Input Parameters: + * None + * + * Returned Value: + * CPU frequency + * + ****************************************************************************/ + +int esp_clk_cpu_freq(void); + +/**************************************************************************** + * Name: esp_clk_apb_freq + * + * Description: + * Return current APB clock frequency. + * + * Input Parameters: + * None + * + * Returned Value: + * APB clock frequency, in Hz + * + ****************************************************************************/ + +int esp_clk_apb_freq(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_config.h b/arch/xtensa/src/esp32s2/esp32s2_config.h new file mode 100644 index 0000000000..c8097017b5 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_config.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_config.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CONFIG_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* UARTs ********************************************************************/ + +/* Are any UARTs enabled? */ + +#undef HAVE_UART_DEVICE +#ifdef CONFIG_ESP32S2_UART +# define HAVE_UART_DEVICE 1 +#endif + +/* Serial Console ***********************************************************/ + +/* Is there a serial console? There should be no more than one defined. It + * could be on any UARTn. n E {0,1} + */ + +#undef HAVE_SERIAL_CONSOLE +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESP32S2_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESP32S2_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# define HAVE_SERIAL_CONSOLE 1 +#else +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +#endif + +/* SPI **********************************************************************/ + +/* Don't enable SPI peripherals not supported by the chip. */ + +#if ESP32S2_NSPI < 1 +# undef CONFIG_ESP32S2_SPI0 +# undef CONFIG_ESP32S2_SPI1 +# undef CONFIG_ESP32S2_SPI2 +# undef CONFIG_ESP32S2_SPI3 +#elif ESP32S2_NSPI < 2 +# undef CONFIG_ESP32S2_SPI1 +# undef CONFIG_ESP32S2_SPI2 +# undef CONFIG_ESP32S2_SPI3 +#elif ESP32S2_NSPI < 3 +# undef CONFIG_ESP32S2_SPI2 +# undef CONFIG_ESP32S2_SPI3 +#elif ESP32S2_NSPI < 4 +# undef CONFIG_ESP32S2_SPI3 +#endif + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CONFIG_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_cpuint.c b/arch/xtensa/src/esp32s2/esp32s2_cpuint.c new file mode 100644 index 0000000000..18ca072bed --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_cpuint.c @@ -0,0 +1,587 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_cpuint.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "esp32s2_cpuint.h" +#include "hardware/esp32s2_interrupt.h" +#include "xtensa.h" + +#include "sched/sched.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Mapping Peripheral IDs to map register addresses + * + * PERIPHERAL ID INTERRUPT_PRO_X_MAP + * MNEMONIC REGISTER OFFSET + * ESP32S2_PERIPH_MAC_INTR 0x0000 + * ESP32S2_PERIPH_MAC_NMI 0x0004 + * ESP32S2_PERIPH_PWR_INTR 0x0008 + * ESP32S2_PERIPH_BB_INT 0x000C + * ESP32S2_PERIPH_BT_MAC_INT 0x0010 + * ESP32S2_PERIPH_BT_BB_INT 0x0014 + * ESP32S2_PERIPH_BT_BB_NMI 0x0018 + * ESP32S2_PERIPH_RWBT_IRQ 0x001C + * ESP32S2_PERIPH_RWBLE_IRQ 0x0020 + * ESP32S2_PERIPH_RWBT_NMI 0x0024 + * ESP32S2_PERIPH_RWBLE_NMI 0x0028 + * ESP32S2_PERIPH_SLC0_INTR 0x002C + * ESP32S2_PERIPH_SLC1_INTR 0x0030 + * ESP32S2_PERIPH_UHCI0_INTR 0x0034 + * ESP32S2_PERIPH_UHCI1_INTR 0x0038 + * ESP32S2_PERIPH_TG_T0_LEVEL_INT 0x003C + * ESP32S2_PERIPH_TG_T1_LEVEL_INT 0x0040 + * ESP32S2_PERIPH_TG_WDT_LEVEL_INT 0x0044 + * ESP32S2_PERIPH_TG_LACT_LEVEL_INT 0x0048 + * ESP32S2_PERIPH_TG1_T0_LEVEL_INT 0x004C + * ESP32S2_PERIPH_TG1_T1_LEVEL_INT 0x0050 + * ESP32S2_PERIPH_TG1_WDT_LEVEL_INT 0x0054 + * ESP32S2_PERIPH_TG1_LACT_LEVEL_INT 0x0058 + * ESP32S2_PERIPH_GPIO_INTERRUPT_PRO 0x005C + * ESP32S2_PERIPH_GPIO_INTERRUPT_PRO_NMI 0x0060 + * ESP32S2_PERIPH_GPIO_INTERRUPT_APP 0x0064 + * ESP32S2_PERIPH_GPIO_INTERRUPT_APP_NMI 0x0068 + * ESP32S2_PERIPH_DEDICATED_GPIO_IN_INTR 0x006C + * ESP32S2_PERIPH_CPU_INTR_FROM_CPU_0 0x0070 + * ESP32S2_PERIPH_CPU_INTR_FROM_CPU_1 0x0074 + * ESP32S2_PERIPH_CPU_INTR_FROM_CPU_2 0x0078 + * ESP32S2_PERIPH_CPU_INTR_FROM_CPU_3 0x007C + * ESP32S2_PERIPH_SPI_INTR_1 0x0080 + * ESP32S2_PERIPH_SPI_INTR_2 0x0084 + * ESP32S2_PERIPH_SPI_INTR_3 0x0088 + * ESP32S2_PERIPH_I2S0_INT 0x008C + * ESP32S2_PERIPH_I2S1_INT 0x0090 + * ESP32S2_PERIPH_UART_INT 0x0094 + * ESP32S2_PERIPH_UART1_INT 0x0098 + * ESP32S2_PERIPH_UART2_INT 0x009C + * ESP32S2_PERIPH_SDIO_HOST_INTERRUPT 0x00A0 + * ESP32S2_PERIPH_PWM0_INTR 0x00A4 + * ESP32S2_PERIPH_PWM1_INTR 0x00A8 + * ESP32S2_PERIPH_PWM2_INTR 0x00AC + * ESP32S2_PERIPH_PWM3_INTR 0x00B0 + * ESP32S2_PERIPH_LEDC_INTR 0x00B4 + * ESP32S2_PERIPH_EFUSE_INT 0x00B8 + * ESP32S2_PERIPH_CAN_INT 0x00BC + * ESP32S2_PERIPH_USB_INT 0x00C0 + * ESP32S2_PERIPH_RTC_CORE_INTR 0x00C4 + * ESP32S2_PERIPH_RMT_INTR 0x00C8 + * ESP32S2_PERIPH_PCNT_INTR 0x00CC + * ESP32S2_PERIPH_I2C_EXT0_INTR 0x00D0 + * ESP32S2_PERIPH_I2C_EXT1_INTR 0x00D4 + * ESP32S2_PERIPH_RSA_INTR 0x00D8 + * ESP32S2_PERIPH_SHA_INTR 0x00DC + * ESP32S2_PERIPH_AES_INTR 0x00E0 + * ESP32S2_PERIPH_SPI2_DMA_INT 0x00E4 + * ESP32S2_PERIPH_SPI3_DMA_INT 0x00E8 + * ESP32S2_PERIPH_WDG_INT 0x00EC + * ESP32S2_PERIPH_TIMER_INT1 0x00F0 + * ESP32S2_PERIPH_TIMER_INT2 0x00F4 + * ESP32S2_PERIPH_TG_T0_EDGE_INT 0x00F8 + * ESP32S2_PERIPH_TG_T1_EDGE_INT 0x00FC + * ESP32S2_PERIPH_TG_WDT_EDGE_INT 0x0100 + * ESP32S2_PERIPH_TG_LACT_EDGE_INT 0x0104 + * ESP32S2_PERIPH_TG1_T0_EDGE_INT 0x0108 + * ESP32S2_PERIPH_TG1_T1_EDGE_INT 0x010C + * ESP32S2_PERIPH_TG1_WDT_EDGE_INT 0x0110 + * ESP32S2_PERIPH_TG1_LACT_EDGE_INT 0x0114 + * ESP32S2_PERIPH_CACHE_IA_INT 0x0118 + * ESP32S2_PERIPH_SYSTIMER_TARGET0_INT 0x011C + * ESP32S2_PERIPH_SYSTIMER_TARGET1_INT 0x0120 + * ESP32S2_PERIPH_SYSTIMER_TARGET2 0x0124 + * ESP32S2_PERIPH_ASSIST_DEBUG_INTR 0x0128 + * ESP32S2_PERIPH_PMS_PRO_IRAM0_ILG 0x012C + * ESP32S2_PERIPH_PMS_PRO_DRAM0_ILG 0x0130 + * ESP32S2_PERIPH_PMS_PRO_DPORT_ILG 0x0134 + * ESP32S2_PERIPH_PMS_PRO_AHB_ILG 0x0138 + * ESP32S2_PERIPH_PMS_PRO_CACHE_ILG 0x013C + * ESP32S2_PERIPH_PMS_DMA_APB_I_ILG 0x0140 + * ESP32S2_PERIPH_PMS_DMA_RX_I_ILG 0x0144 + * ESP32S2_PERIPH_PMS_DMA_TX_I_ILG 0x0148 + * ESP32S2_PERIPH_SPI_MEM_REJECT_INTR 0x014C + * ESP32S2_PERIPH_DMA_COPY_INTR 0x0150 + * ESP32S2_PERIPH_SPI4_DMA_INT 0x0154 + * ESP32S2_PERIPH_SPI_INTR_4 0x0158 + * ESP32S2_PERIPH_DCACHE_PRELOAD_INT 0x015C + * ESP32S2_PERIPH_ICACHE_PRELOAD_INT 0x0160 + * ESP32S2_PERIPH_APB_ADC_INT 0x0164 + * ESP32S2_PERIPH_CRYPTO_DMA_INT 0x0168 + * ESP32S2_PERIPH_CPU_PERI_ERROR_INT 0x016C + * ESP32S2_PERIPH_APB_PERI_ERROR_INT 0x0170 + * ESP32S2_PERIPH_DCACHE_SYNC_INT 0x0174 + * ESP32S2_PERIPH_ICACHE_SYNC_INT 0x0178 + * ESP32S2_PERIPH_NMI 0x0188 + */ + +#define INTERRUPT_PRO_X_MAP_REG(n) (DR_REG_INTERRUPT_BASE + ((n) << 2)) + +/* CPU interrupts can be detached from any peripheral source by setting the + * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29). + */ + +#define NO_CPUINT ESP32S2_CPUINT_TIMER0 + +/* Priority range is 1-5 */ + +#define ESP32S2_MIN_PRIORITY 1 +#define ESP32S2_MAX_PRIORITY 5 +#define ESP32S2_PRIO_INDEX(p) ((p) - ESP32S2_MIN_PRIORITY) + +#ifdef CONFIG_ESP32S2_WIRELESS +# define ESP32S2_WIRELESS_RESERVE_INT (1 << ESP32S2_CPUINT_MAC) +#else +# define ESP32S2_WIRELESS_RESERVE_INT 0 +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ + +uint8_t g_cpu0_intmap[ESP32S2_NCPUINTS]; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* g_intenable[] is a shadow copy of the CPU INTENABLE register + * content. + */ + +static uint32_t g_intenable[1]; + +/* Bitsets for free, unallocated CPU interrupts available to peripheral + * devices. + */ + +static uint32_t g_cpu0_freeints = ESP32_CPUINT_PERIPHSET & + (~ESP32S2_WIRELESS_RESERVE_INT); + +/* Bitsets for each interrupt priority 1-5 */ + +static const uint32_t g_priority[5] = +{ + ESP32S2_INTPRI1_MASK, + ESP32S2_INTPRI2_MASK, + ESP32S2_INTPRI3_MASK, + ESP32S2_INTPRI4_MASK, + ESP32S2_INTPRI5_MASK +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_disable_all + * + * Description: + * Disable all CPU interrupts. + ****************************************************************************/ + +static inline void xtensa_disable_all(void) +{ + __asm__ __volatile__ + ( + "movi a2, 0\n" + "xsr a2, INTENABLE\n" + : : : "a2" + ); +} + +/**************************************************************************** + * Name: esp32s2_alloc_cpuint + * + * Description: + * Allocate a CPU interrupt for a peripheral device. This function will + * not allocate any of the pre-allocated CPU interrupts for internal + * devices. This current implementation is not supporting multiple + * peripheral interrupts maped to a single CPU interrupt. + * + * Input Parameters: + * intmask - Mask of candidate CPU interrupts. The CPU interrupt will be + * be allocated from free interrupts within this set. + * + * Returned Value: + * On success, the first available CPU interrupt accordingly to the passed + * intmask. If no one is available return -ENOMEM. + * + ****************************************************************************/ + +static int esp32s2_alloc_cpuint(uint32_t intmask) +{ + irqstate_t flags; + uint32_t *freeints; + uint32_t bitmask; + uint32_t intset; + int cpuint; + int ret = -ENOMEM; + + /* Check if there are CPU interrupts with the requested properties + * available. + */ + + flags = enter_critical_section(); + + freeints = &g_cpu0_freeints; + + intset = *freeints & intmask; + if (intset != 0) + { + /* Skip over initial unavailable CPU interrupts quickly in groups + * of 8 interrupt until find the first slot with the required + * CPU interrupt set. + */ + + for (cpuint = 0, bitmask = 0xff; + cpuint <= ESP32S2_CPUINT_MAX && (intset & bitmask) == 0; + cpuint += 8, bitmask <<= 8); + + /* Search for an unallocated CPU interrupt number in the remaining + * intset. + */ + + for (; cpuint <= ESP32S2_CPUINT_MAX; cpuint++) + { + /* If the bit corresponding to the CPU interrupt is '1', then + * that CPU interrupt is available. + */ + + bitmask = (1ul << cpuint); + if ((intset & bitmask) != 0) + { + /* Got it! + * Update the available CPU interrupts mask + * and return the cpuint. + */ + + *freeints &= ~bitmask; + ret = cpuint; + break; + } + } + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_cpuint_initialize + * + * Description: + * Initialize CPU interrupts. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp32s2_cpuint_initialize(void) +{ + uintptr_t regaddr; + uint8_t *intmap; + int i; + + /* Disable all CPU interrupts on this CPU */ + + xtensa_disable_all(); + + /* Detach all peripheral sources PRO CPU interrupts */ + + for (i = 0; i < ESP32S2_NPERIPHERALS; i++) + { + regaddr = INTERRUPT_PRO_X_MAP_REG(i); + + putreg32(NO_CPUINT, regaddr); + } + + /* Initialize CPU interrupt-to-IRQ mapping table */ + + intmap = g_cpu0_intmap; + + /* Indicate that no peripheral interrupts are assigned to CPU interrupts */ + + memset(intmap, CPUINT_UNASSIGNED, ESP32S2_NCPUINTS); + + /* Special case the 6 internal interrupts. + * + * CPU interrupt bit IRQ number + * --------------------------- --------------------- + * ESP32S2_CPUINT_MAC 0 ESP32S2_IRQ_MAC 4 + * ESP32S2_CPUINT_TIMER0 6 XTENSA_IRQ_TIMER0 0 + * ESP32S2_CPUINT_SOFTWARE0 7 Not yet defined + * ESP32S2_CPUINT_PROFILING 11 Not yet defined + * ESP32S2_CPUINT_TIMER1 15 XTENSA_IRQ_TIMER1 1 + * ESP32S2_CPUINT_TIMER2 16 XTENSA_IRQ_TIMER2 2 + * ESP32S2_CPUINT_SOFTWARE1 29 Not yet defined + */ + + intmap[ESP32S2_CPUINT_TIMER0] = XTENSA_IRQ_TIMER0; + intmap[ESP32S2_CPUINT_TIMER1] = XTENSA_IRQ_TIMER1; + intmap[ESP32S2_CPUINT_TIMER2] = XTENSA_IRQ_TIMER2; + + /* Reserve CPU interrupt for some special drivers */ + +#ifdef CONFIG_ESP32S2_WIRELESS + intmap[ESP32S2_CPUINT_MAC] = ESP32S2_IRQ_MAC; +#endif + + return OK; +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the CPU interrupt specified by 'cpuint'. + * + * Input Parameters: + * cpuint - The CPU interrupt to disable. + * + ****************************************************************************/ + +void up_disable_irq(int cpuint) +{ + DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX); + + xtensa_disable_cpuint(&g_intenable[0], (1ul << cpuint)); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the CPU interrupt specified by 'cpuint'. + * + * Input Parameters: + * cpuint - The CPU interrupt to disable. + * + ****************************************************************************/ + +void up_enable_irq(int cpuint) +{ + DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX); + + xtensa_enable_cpuint(&g_intenable[0], (1ul << cpuint)); +} + +/**************************************************************************** + * Name: esp32s2_alloc_levelint + * + * Description: + * Allocate a level CPU interrupt + * + * Input Parameters: + * priority - Priority of the CPU interrupt (1-5) + * + * Returned Value: + * On success, the allocated level-sensitive, CPU interrupt number is + * returned. A negated errno is returned on failure. The only possible + * failure is that all level-sensitive CPU interrupts have already been + * allocated. + * + ****************************************************************************/ + +int esp32s2_alloc_levelint(int priority) +{ + uint32_t intmask; + + DEBUGASSERT(priority >= ESP32S2_MIN_PRIORITY && + priority <= ESP32S2_MAX_PRIORITY); + + /* Check if there are any level CPU interrupts available at the requested + * interrupt priority. + */ + + intmask = g_priority[ESP32S2_PRIO_INDEX(priority)] & EPS32_CPUINT_LEVELSET; + return esp32s2_alloc_cpuint(intmask); +} + +/**************************************************************************** + * Name: esp32s2_alloc_edgeint + * + * Description: + * Allocate an edge CPU interrupt + * + * Input Parameters: + * priority - Priority of the CPU interrupt (1-5) + * + * Returned Value: + * On success, the allocated edge-sensitive, CPU interrupt number is + * returned. A negated errno is returned on failure. The only possible + * failure is that all edge-sensitive CPU interrupts have already been + * allocated. + * + ****************************************************************************/ + +int esp32s2_alloc_edgeint(int priority) +{ + uint32_t intmask; + + DEBUGASSERT(priority >= ESP32S2_MIN_PRIORITY && + priority <= ESP32S2_MAX_PRIORITY); + + /* Check if there are any edge CPU interrupts available at the requested + * interrupt priority. + */ + + intmask = g_priority[ESP32S2_PRIO_INDEX(priority)] & EPS32_CPUINT_EDGESET; + return esp32s2_alloc_cpuint(intmask); +} + +/**************************************************************************** + * Name: esp32s2_free_cpuint + * + * Description: + * Free a previously allocated CPU interrupt by making it available in the + * g_cpu0_freeints. + * + * Input Parameters: + * cpuint - The CPU interrupt number to be freed. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_free_cpuint(int cpuint) +{ + irqstate_t flags; + uint32_t *freeints; + uint32_t bitmask; + + DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX); + + /* Mark the CPU interrupt as available */ + + bitmask = (1ul << cpuint); + flags = enter_critical_section(); + + freeints = &g_cpu0_freeints; + + DEBUGASSERT((*freeints & bitmask) == 0); + *freeints |= bitmask; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp32s2_attach_peripheral + * + * Description: + * Attach a peripheral interrupt to a CPU interrupt. + * This function may be called after esp32s2_alloc_edgeint or + * esp32s2_alloc_levelint + * + * Input Parameters: + * periphid - The peripheral number from irq.h to be assigned to + * a CPU interrupt. + * cpuint - The CPU interrupt to receive the peripheral interrupt + * assignment. This value is returned by + * esp32s2_alloc_edgeint or esp32s2_alloc_levelint. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_attach_peripheral(int periphid, int cpuint) +{ + uintptr_t regaddr; + + /* Get the map for CPU interrupts and IRQs */ + + uint8_t *intmap = g_cpu0_intmap; + + DEBUGASSERT(periphid >= 0 && periphid < ESP32S2_NPERIPHERALS); + DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX); + DEBUGASSERT(intmap[cpuint] == CPUINT_UNASSIGNED); + + /* Get the INTERRUPT_PRO_X_MAP_REG for that specific peripheral. + * X stands for the peripheral source. + * Fill the interruption map with the IRQ for the new CPU interrupt. + * Allocate one peripheral interrupt to the CPU interrupt. + */ + + regaddr = INTERRUPT_PRO_X_MAP_REG(periphid); + intmap[cpuint] = periphid + XTENSA_IRQ_FIRSTPERI; + putreg32(cpuint, regaddr); +} + +/**************************************************************************** + * Name: esp32s2_detach_peripheral + * + * Description: + * Detach a peripheral interrupt from a CPU interrupt. + * + * Input Parameters: + * periphid - The peripheral number from irq.h to be detached from the + * CPU interrupt. + * cpuint - The CPU interrupt from which the peripheral interrupt will + * be detached. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_detach_peripheral(int periphid, int cpuint) +{ + uintptr_t regaddr; + uint8_t *intmap = g_cpu0_intmap; + + DEBUGASSERT(periphid >= 0 && periphid < ESP32S2_NPERIPHERALS); + DEBUGASSERT(intmap[cpuint] != CPUINT_UNASSIGNED); + + /* Get the INTERRUPT_PRO_X_MAP_REG for that specific peripheral. + * X stands for the peripheral source. + * Unassign the IRQ from the CPU interrupt. + * Deallocate the peripheral interrupt from the CPU interrupt. + */ + + regaddr = INTERRUPT_PRO_X_MAP_REG(periphid); + intmap[cpuint] = CPUINT_UNASSIGNED; + putreg32(NO_CPUINT, regaddr); +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_cpuint.h b/arch/xtensa/src/esp32s2/esp32s2_cpuint.h new file mode 100644 index 0000000000..4f6dd2e1c7 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_cpuint.h @@ -0,0 +1,169 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_cpuint.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CPUINT_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CPUINT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* No peripheral assigned to this CPU interrupt */ + +#define CPUINT_UNASSIGNED 0xff + +/* A low priority definition to be used by drivers */ + +#define ESP32S2_INT_PRIO_DEF 1 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ + +extern uint8_t g_cpu0_intmap[ESP32S2_NCPUINTS]; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_cpuint_initialize + * + * Description: + * Initialize CPU interrupts. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp32s2_cpuint_initialize(void); + +/**************************************************************************** + * Name: esp32s2_alloc_levelint + * + * Description: + * Allocate a level CPU interrupt + * + * Input Parameters: + * priority - Priority of the CPU interrupt (1-5) + * + * Returned Value: + * On success, the allocated level-sensitive, CPU interrupt number is + * returned. A negated errno is returned on failure. The only possible + * failure is that all level-sensitive CPU interrupts have already been + * allocated. + * + ****************************************************************************/ + +int esp32s2_alloc_levelint(int priority); + +/**************************************************************************** + * Name: esp32s2_alloc_edgeint + * + * Description: + * Allocate an edge CPU interrupt + * + * Input Parameters: + * priority - Priority of the CPU interrupt (1-5) + * + * Returned Value: + * On success, the allocated edge-sensitive, CPU interrupt number is + * returned. A negated errno is returned on failure. The only possible + * failure is that all edge-sensitive CPU interrupts have already been + * allocated. + * + ****************************************************************************/ + +int esp32s2_alloc_edgeint(int priority); + +/**************************************************************************** + * Name: esp32s2_free_cpuint + * + * Description: + * Free a previously allocated CPU interrupt by making it available in the + * g_cpu0_freeints. + * + * Input Parameters: + * cpuint - The CPU interrupt number to be freed. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_free_cpuint(int cpuint); + +/**************************************************************************** + * Name: esp32s2_attach_peripheral + * + * Description: + * Attach a peripheral interrupt to a CPU interrupt. + * This function may be called after esp32s2_alloc_edgeint or + * esp32s2_alloc_levelint + * + * Input Parameters: + * periphid - The peripheral number from irq.h to be assigned to + * a CPU interrupt. + * cpuint - The CPU interrupt to receive the peripheral interrupt + * assignment. This value is returned by + * esp32s2_alloc_edgeint or esp32s2_alloc_levelint. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_attach_peripheral(int periphid, int cpuint); + +/**************************************************************************** + * Name: esp32s2_detach_peripheral + * + * Description: + * Detach a peripheral interrupt from a CPU interrupt. + * + * Input Parameters: + * periphid - The peripheral number from irq.h to be detached from the + * CPU interrupt. + * cpuint - The CPU interrupt from which the peripheral interrupt will + * be detached. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_detach_peripheral(int periphid, int cpuint); + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CPUINT_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_gpio.c b/arch/xtensa/src/esp32s2/esp32s2_gpio.c new file mode 100644 index 0000000000..265160c74c --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_gpio.c @@ -0,0 +1,474 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "xtensa.h" +#include "hardware/esp32s2_iomux.h" +#include "hardware/esp32s2_gpio.h" +#include "esp32s2_cpuint.h" +#include "esp32s2_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NGPIO_HPINS (ESP32S2_NIRQ_GPIO - 32) +#define NGPIO_HMASK ((1ul << NGPIO_HPINS) - 1) +#define _NA_ 0xff + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +static int g_gpio_cpuint; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpio_dispatch + * + * Description: + * Second level dispatch for GPIO interrupt handling. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs) +{ + uint32_t mask; + int i; + + /* Check each bit in the status register */ + + for (i = 0; i < 32 && status != 0; i++) + { + /* Check if there is an interrupt pending for this pin */ + + mask = (1ul << i); + if ((status & mask) != 0) + { + /* Yes... perform the second level dispatch */ + + irq_dispatch(irq + i, regs); + + /* Clear the bit in the status so that we might execute this loop + * sooner. + */ + + status &= ~mask; + } + } +} +#endif + +/**************************************************************************** + * Name: gpio_interrupt + * + * Description: + * GPIO interrupt handler. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +static int gpio_interrupt(int irq, FAR void *context, FAR void *arg) +{ + uint32_t status; + + /* Read and clear the lower GPIO interrupt status */ + + status = getreg32(GPIO_STATUS_REG); + putreg32(status, GPIO_STATUS_W1TC_REG); + + /* Dispatch pending interrupts in the lower GPIO status register */ + + gpio_dispatch(ESP32S2_FIRST_GPIOIRQ, status, (uint32_t *)context); + + /* Read and clear the upper GPIO interrupt status */ + + status = getreg32(GPIO_STATUS1_REG) & NGPIO_HMASK; + putreg32(status, GPIO_STATUS1_W1TC_REG); + + /* Dispatch pending interrupts in the lower GPIO status register */ + + gpio_dispatch(ESP32S2_FIRST_GPIOIRQ + 32, status, (uint32_t *)context); + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_configgpio + * + * Description: + * Configure a GPIO pin based on encoded pin attributes. + * + ****************************************************************************/ + +int esp32s2_configgpio(int pin, gpio_pinattr_t attr) +{ + uintptr_t regaddr; + uint32_t func; + uint32_t cntrl; + uint32_t pin2func; + + DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS); + + /* Handle input pins */ + + func = 0; + cntrl = 0; + + if ((attr & INPUT) != 0) + { + if (pin < 32) + { + putreg32((1ul << pin), GPIO_ENABLE_W1TC_REG); + } + else + { + putreg32((1ul << (pin - 32)), GPIO_ENABLE1_W1TC_REG); + } + + /* Input enable */ + + func |= FUN_IE; + + if ((attr & PULLUP) != 0) + { + func |= FUN_PU; + } + else if (attr & PULLDOWN) + { + func |= FUN_PD; + } + } + + /* Handle output pins */ + + if ((attr & OUTPUT) != 0) + { + if (pin < 32) + { + putreg32((1ul << pin), GPIO_ENABLE_W1TS_REG); + } + else + { + putreg32((1ul << (pin - 32)), GPIO_ENABLE1_W1TS_REG); + } + } + + /* Add drivers */ + + func |= (uint32_t)(2ul << FUN_DRV_S); + + /* Select the pad's function. If no function was given, consider it a + * normal input or output (i.e. function3). + */ + + if ((attr & FUNCTION_MASK) != 0) + { + func |= (uint32_t)(((attr >> FUNCTION_SHIFT) - 1) << MCU_SEL_S); + } + else + { + func |= (uint32_t)(PIN_FUNC_GPIO << MCU_SEL_S); + } + + if ((attr & OPEN_DRAIN) != 0) + { + cntrl |= (1 << GPIO_PIN_PAD_DRIVER_S); + } + + pin2func = (pin + 1) * 4; + regaddr = DR_REG_IO_MUX_BASE + pin2func; + putreg32(func, regaddr); + + regaddr = GPIO_REG(pin); + putreg32(cntrl, regaddr); + return OK; +} + +/**************************************************************************** + * Name: esp32s2_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void esp32s2_gpiowrite(int pin, bool value) +{ + DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS); + + if (value) + { + if (pin < 32) + { + putreg32((uint32_t)(1ul << pin), GPIO_OUT_W1TS_REG); + } + else + { + putreg32((uint32_t)(1ul << (pin - 32)), GPIO_OUT1_W1TS_REG); + } + } + else + { + if (pin < 32) + { + putreg32((uint32_t)(1ul << pin), GPIO_OUT_W1TC_REG); + } + else + { + putreg32((uint32_t)(1ul << (pin - 32)), GPIO_OUT1_W1TC_REG); + } + } +} + +/**************************************************************************** + * Name: esp32s2_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool esp32s2_gpioread(int pin) +{ + uint32_t regval; + + DEBUGASSERT(pin >= 0 && pin <= ESP32S2_NGPIOS); + + if (pin < 32) + { + regval = getreg32(GPIO_IN_REG); + return ((regval >> pin) & 1) != 0; + } + else + { + regval = getreg32(GPIO_IN1_REG); + return ((regval >> (pin - 32)) & 1) != 0; + } +} + +/**************************************************************************** + * Name: esp32s2_gpioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +void esp32s2_gpioirqinitialize(void) +{ + /* Allocate a level-sensitive, priority 1 CPU interrupt */ + + g_gpio_cpuint = esp32s2_alloc_levelint(1); + DEBUGASSERT(g_gpio_cpuint >= 0); + + /* Attach the GPIO peripheral to the allocated CPU interrupt */ + + up_disable_irq(g_gpio_cpuint); + esp32s2_attach_peripheral(ESP32S2_PERI_GPIO_INT_PRO, g_gpio_cpuint); + + /* Attach and enable the interrupt handler */ + + DEBUGVERIFY(irq_attach(ESP32S2_PERI_GPIO_INT_PRO, gpio_interrupt, NULL)); + up_enable_irq(g_gpio_cpuint); +} +#endif + +/**************************************************************************** + * Name: esp32s2_gpioirqenable + * + * Description: + * Enable the COPY interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +void esp32s2_gpioirqenable(int irq, gpio_intrtype_t intrtype) +{ + uintptr_t regaddr; + uint32_t regval; + int pin; + + DEBUGASSERT(irq >= ESP32S2_FIRST_GPIOIRQ && irq <= ESP32S2_LAST_GPIOIRQ); + + /* Convert the IRQ number to a pin number */ + + pin = ESP32S2_IRQ2PIN(irq); + + /* Get the address of the GPIO PIN register for this pin */ + + up_disable_irq(g_gpio_cpuint); + + regaddr = GPIO_REG(pin); + regval = getreg32(regaddr); + regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); + + /* Set the pin ENA field: + * + * Bit 0: APP CPU interrupt enable + * Bit 1: APP CPU non-maskable interrupt enable + * Bit 3: PRO CPU interrupt enable + * Bit 4: PRO CPU non-maskable interrupt enable + * Bit 5: SDIO's extent interrupt enable. + */ + + /* PRO_CPU */ + + regval |= ((1 << 2) << GPIO_PIN_INT_ENA_S); + + regval |= (intrtype << GPIO_PIN_INT_TYPE_S); + putreg32(regval, regaddr); + + up_enable_irq(g_gpio_cpuint); +} +#endif + +/**************************************************************************** + * Name: esp32s2_gpioirqdisable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +void esp32s2_gpioirqdisable(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + int pin; + + DEBUGASSERT(irq >= ESP32S2_FIRST_GPIOIRQ && irq <= ESP32S2_LAST_GPIOIRQ); + + /* Convert the IRQ number to a pin number */ + + pin = ESP32S2_IRQ2PIN(irq); + + /* Get the address of the GPIO PIN register for this pin */ + + up_disable_irq(g_gpio_cpuint); + + regaddr = GPIO_REG(pin); + regval = getreg32(regaddr); + regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); + putreg32(regval, regaddr); + + up_enable_irq(g_gpio_cpuint); +} +#endif + +/**************************************************************************** + * Name: esp32s2_gpio_matrix_in + * + * Description: + * Set gpio input to a signal + * NOTE: one gpio can input to several signals + * If gpio == 0x30, cancel input to the signal, input 0 to signal + * If gpio == 0x38, cancel input to the signal, input 1 to signal, + * for I2C pad + * + ****************************************************************************/ + +void esp32s2_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv) +{ + uint32_t regaddr = GPIO_FUNC0_IN_SEL_CFG_REG + (signal_idx * 4); + uint32_t regval = (gpio << GPIO_FUNC0_IN_SEL_S); + + if (inv) + { + regval |= GPIO_FUNC0_IN_INV_SEL; + } + + if (gpio != 0x34) + { + regval |= GPIO_SIG0_IN_SEL; + } + + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: esp32s2_gpio_matrix_out + * + * Description: + * Set signal output to gpio + * NOTE: one signal can output to several gpios + * If signal_idx == 0x100, cancel output put to the gpio + * + ****************************************************************************/ + +void esp32s2_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, + bool out_inv, bool oen_inv) +{ + uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio * 4); + uint32_t regval = signal_idx << GPIO_FUNC0_OUT_SEL_S; + + if (gpio >= GPIO_PIN_COUNT) + { + return; + } + + if (gpio < 32) + { + putreg32((1ul << gpio), GPIO_ENABLE_W1TS_REG); + } + else + { + putreg32((1ul << (gpio - 32)), GPIO_ENABLE1_W1TS_REG); + } + + if (out_inv) + { + regval |= GPIO_FUNC0_OUT_INV_SEL; + } + + if (oen_inv) + { + regval |= GPIO_FUNC0_OEN_INV_SEL; + } + + putreg32(regval, regaddr); +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_gpio.h b/arch/xtensa/src/esp32s2/esp32s2_gpio.h new file mode 100644 index 0000000000..b83f0214a0 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_gpio.h @@ -0,0 +1,235 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */ +#define MATRIX_DETACH_IN_LOW_PIN 0x30 /* Detach non-inverted INPUT sig */ +#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */ + +/* Bit-encoded input to esp32s2_configgpio() ********************************/ + +/* Encoded pin attributes used with esp32s2_configgpio() + * + * 8 7 6 5 4 3 2 1 0 + * -- -- -- -- -- -- -- -- -- + * FN FN FN OD PD PU F O I + */ + +#define PINMODE_SHIFT 0 +#define PINMODE_MASK (7 << PINMODE_SHIFT) +# define INPUT (1 << 0) +# define OUTPUT (1 << 1) +# define FUNCTION (1 << 2) + +#define PULLUP (1 << 3) +#define PULLDOWN (1 << 4) +#define OPEN_DRAIN (1 << 5) +#define FUNCTION_SHIFT 6 +#define FUNCTION_MASK (7 << FUNCTION_SHIFT) +# define FUNCTION_1 (1 << FUNCTION_SHIFT) +# define FUNCTION_2 (2 << FUNCTION_SHIFT) +# define FUNCTION_3 (3 << FUNCTION_SHIFT) +# define FUNCTION_4 (4 << FUNCTION_SHIFT) +# define FUNCTION_5 (5 << FUNCTION_SHIFT) +# define FUNCTION_6 (6 << FUNCTION_SHIFT) + +#define INPUT_PULLUP (INPUT | PULLUP) +#define INPUT_PULLDOWN (INPUT | PULLDOWN) +#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN) +#define INPUT_FUNCTION (INPUT | FUNCTION) +# define INPUT_FUNCTION_1 (INPUT_FUNCTION | FUNCTION_1) +# define INPUT_FUNCTION_2 (INPUT_FUNCTION | FUNCTION_2) +# define INPUT_FUNCTION_3 (INPUT_FUNCTION | FUNCTION_3) +# define INPUT_FUNCTION_4 (INPUT_FUNCTION | FUNCTION_4) +# define INPUT_FUNCTION_5 (INPUT_FUNCTION | FUNCTION_5) +# define INPUT_FUNCTION_6 (INPUT_FUNCTION | FUNCTION_6) +#define OUTPUT_FUNCTION (OUTPUT | FUNCTION) +# define OUTPUT_FUNCTION_1 (OUTPUT_FUNCTION | FUNCTION_1) +# define OUTPUT_FUNCTION_2 (OUTPUT_FUNCTION | FUNCTION_2) +# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3) +# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4) +# define OUTPUT_FUNCTION_5 (OUTPUT_FUNCTION | FUNCTION_5) +# define OUTPUT_FUNCTION_6 (OUTPUT_FUNCTION | FUNCTION_6) + +/* Interrupt type used with esp32s2_gpioirqenable() */ + +#define DISABLED 0x00 +#define RISING 0x01 +#define FALLING 0x02 +#define CHANGE 0x03 +#define ONLOW 0x04 +#define ONHIGH 0x05 +#define ONLOW_WE 0x0c +#define ONHIGH_WE 0x0d + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Must be big enough to hold the above encodings */ + +typedef uint16_t gpio_pinattr_t; +typedef uint8_t gpio_intrtype_t; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_gpioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +void esp32s2_gpioirqinitialize(void); +#else +# define esp32s2_gpioirqinitialize() +#endif + +/**************************************************************************** + * Name: esp32s2_configgpio + * + * Description: + * Configure a GPIO pin based on encoded pin attributes. + * + ****************************************************************************/ + +int esp32s2_configgpio(int pin, gpio_pinattr_t attr); + +/**************************************************************************** + * Name: esp32s2_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void esp32s2_gpiowrite(int pin, bool value); + +/**************************************************************************** + * Name: esp32s2_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool esp32s2_gpioread(int pin); + +/**************************************************************************** + * Name: esp32s2_gpioirqenable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +void esp32s2_gpioirqenable(int irq, gpio_intrtype_t intrtype); +#else +# define esp32s2_gpioirqenable(irq,intrtype) +#endif + +/**************************************************************************** + * Name: esp32s2_gpioirqdisable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_GPIO_IRQ +void esp32s2_gpioirqdisable(int irq); +#else +# define esp32s2_gpioirqdisable(irq) +#endif + +/**************************************************************************** + * Name: esp32s2_gpio_matrix_in + * + * Description: + * Set gpio input to a signal + * NOTE: one gpio can input to several signals + * If gpio == 0x30, cancel input to the signal, input 0 to signal + * If gpio == 0x38, cancel input to the signal, input 1 to signal, + * for I2C pad + * + ****************************************************************************/ + +void esp32s2_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); + +/**************************************************************************** + * Name: esp32s2_gpio_matrix_out + * + * Description: + * Set signal output to gpio + * NOTE: one signal can output to several gpios + * If signal_idx == 0x100, cancel output put to the gpio + * + ****************************************************************************/ + +void esp32s2_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, + bool out_inv, bool oen_inv); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_idle.c b/arch/xtensa/src/esp32s2/esp32s2_idle.c new file mode 100644 index 0000000000..71dd02b4c8 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_idle.c @@ -0,0 +1,206 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_idle.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "esp32s2_pm.h" +#include "xtensa.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Values for the RTC Alarm to wake up from the PM_STANDBY mode + * (which corresponds to ESP32S2 stop mode). If this alarm expires, + * the logic in this file will wakeup from PM_STANDBY mode and + * transition to PM_SLEEP mode (ESP32S2 standby mode). + */ + +#ifdef CONFIG_PM +#ifndef CONFIG_PM_ALARM_SEC +# define CONFIG_PM_ALARM_SEC 15 +#endif + +#ifndef CONFIG_PM_ALARM_NSEC +# define CONFIG_PM_ALARM_NSEC 0 +#endif + +#ifndef CONFIG_PM_SLEEP_WAKEUP_SEC +# define CONFIG_PM_SLEEP_WAKEUP_SEC 20 +#endif + +#ifndef CONFIG_PM_SLEEP_WAKEUP_NSEC +# define CONFIG_PM_SLEEP_WAKEUP_NSEC 0 +#endif + +#define PM_IDLE_DOMAIN 0 /* Revisit */ +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_idlepm(void) +{ + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + flags = spin_lock_irqsave(NULL); + + /* Perform board-specific, state-dependent logic here */ + + _info("newstate= %d oldstate=%d\n", newstate, oldstate); + + /* Then force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + } + else + { + /* Save the new state */ + + oldstate = newstate; + } + + spin_unlock_irqrestore(NULL, flags); + + /* MCU-specific power management logic */ + + switch (newstate) + { + case PM_NORMAL: + break; + + case PM_IDLE: + break; + + case PM_STANDBY: + { + /* Enter Force-sleep mode */ + + esp32s2_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 + + CONFIG_PM_ALARM_NSEC / 1000); + } + break; + + case PM_SLEEP: + { + /* Enter Deep-sleep mode */ + + esp32s2_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 + + CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000); + } + break; + + default: + break; + } + } + else + { + if (oldstate == PM_NORMAL) + { + /* Relax normal operation */ + + pm_relax(PM_IDLE_DOMAIN, PM_NORMAL); + } + +#ifdef CONFIG_WATCHDOG + /* Announce the power management state change to feed watchdog */ + + pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); +#endif + } +} +#else +# define up_idlepm() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + up_idlepm(); + + /* This would be an appropriate place to put some MCU-specific logic to + * sleep in a reduced power mode until an interrupt occurs to save power + */ + +#if XCHAL_HAVE_INTERRUPTS + __asm__ __volatile__ ("waiti 0"); +#endif +#endif +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_intdecode.c b/arch/xtensa/src/esp32s2/esp32s2_intdecode.c new file mode 100644 index 0000000000..5f6ac7e05b --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_intdecode.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_intdecode.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "xtensa.h" +#include "esp32s2_cpuint.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_intclear + ****************************************************************************/ + +static inline void xtensa_intclear(uint32_t mask) +{ + __asm__ __volatile__ + ( + "wsr %0, INTCLEAR\n" + : "=r"(mask) : : + ); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_int_decode + * + * Description: + * Determine the peripheral that generated the interrupt and dispatch + * handling to the registered interrupt handler via xtensa_irq_dispatch(). + * + * Input Parameters: + * cpuints - Set of pending interrupts valid for this level + * regs - Saves processor state on the stack + * + * Returned Value: + * Normally the same value as regs is returned. But, in the event of an + * interrupt level context switch, the returned value will, instead point + * to the saved processor state in the TCB of the newly started task. + * + ****************************************************************************/ + +uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs) +{ + uint8_t *intmap; + uint32_t mask; + int bit; + + intmap = g_cpu0_intmap; + + /* Skip over zero bits, eight at a time */ + + for (bit = 0, mask = 0xff; + bit < ESP32S2_NCPUINTS && (cpuints & mask) == 0; + bit += 8, mask <<= 8); + + /* Process each pending CPU interrupt */ + + for (; bit < ESP32S2_NCPUINTS && cpuints != 0; bit++) + { + mask = (1 << bit); + if ((cpuints & mask) != 0) + { + /* Extract the IRQ number from the mapping table */ + + uint8_t irq = intmap[bit]; + DEBUGASSERT(irq != CPUINT_UNASSIGNED); + + /* Clear software or edge-triggered interrupt */ + + xtensa_intclear(mask); + + /* Dispatch the CPU interrupt. + * + * NOTE that regs may be altered in the case of an interrupt + * level context switch. + */ + + regs = xtensa_irq_dispatch((int)irq, regs); + + /* Clear the bit in the pending interrupt so that perhaps + * we can exit the look early. + */ + + cpuints &= ~mask; + } + } + + return regs; +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_irq.c b/arch/xtensa/src/esp32s2/esp32s2_irq.c new file mode 100644 index 0000000000..c470dba7e4 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_irq.c @@ -0,0 +1,109 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "xtensa.h" +#include "esp32s2_cpuint.h" +#include "esp32s2_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a reference to the current interrupt level + * register storage structure. It is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +volatile uint32_t *g_current_regs[1]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_irq_dump + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void esp32s2_irq_dump(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); +#warning Missing logic + leave_critical_section(flags); +} +#else +# define esp32s2_irq_dump(msg, irq) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + /* Initialize CPU interrupts */ + + esp32s2_cpuint_initialize(); + + /* Attach and enable internal interrupts */ + + esp32s2_irq_dump("initial", NR_IRQS); + +#ifdef CONFIG_ESP32S2_GPIO_IRQ + /* Initialize GPIO interrupt support */ + + esp32s2_gpioirqinitialize(); +#endif + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* And finally, enable interrupts. Also clears PS.EXCM */ + + up_irq_enable(); +#endif +} + diff --git a/arch/xtensa/src/esp32s2/esp32s2_lowputc.c b/arch/xtensa/src/esp32s2/esp32s2_lowputc.c new file mode 100644 index 0000000000..105eb808b4 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_lowputc.c @@ -0,0 +1,656 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_lowputc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "xtensa.h" + +#include "hardware/esp32s2_system.h" +#include "hardware/esp32s2_uart.h" +#include "hardware/esp32s2_soc.h" + +#include "esp32s2_clockconfig.h" +#include "esp32s2_config.h" +#include "esp32s2_gpio.h" + +#include "esp32s2_lowputc.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE + +#ifdef CONFIG_ESP32S2_UART0 + +struct esp32s2_uart_s g_uart0_config = +{ + .periph = ESP32S2_PERI_UART, + .id = 0, + .cpuint = -ENOMEM, + .irq = ESP32S2_IRQ_UART, + .baud = CONFIG_UART0_BAUD, + .bits = CONFIG_UART0_BITS, + .parity = CONFIG_UART0_PARITY, + .stop_b2 = CONFIG_UART0_2STOP, + .int_pri = ESP32S2_INT_PRIO_DEF, + .txpin = CONFIG_ESP32S2_UART0_TXPIN, + .txsig = U0TXD_OUT_IDX, + .rxpin = CONFIG_ESP32S2_UART0_RXPIN, + .rxsig = U0RXD_IN_IDX, +}; + +#endif /* CONFIG_ESP32S2_UART0 */ + +#ifdef CONFIG_ESP32S2_UART1 + +struct esp32s2_uart_s g_uart1_config = +{ + .periph = ESP32S2_PERI_UART1, + .id = 1, + .cpuint = -ENOMEM, + .irq = ESP32S2_IRQ_UART1, + .baud = CONFIG_UART1_BAUD, + .bits = CONFIG_UART1_BITS, + .parity = CONFIG_UART1_PARITY, + .stop_b2 = CONFIG_UART1_2STOP, + .int_pri = ESP32S2_INT_PRIO_DEF, + .txpin = CONFIG_ESP32S2_UART1_TXPIN, + .txsig = U1TXD_OUT_IDX, + .rxpin = CONFIG_ESP32S2_UART1_RXPIN, + .rxsig = U1RXD_IN_IDX, +}; + +#endif /* CONFIG_ESP32S2_UART1 */ +#endif /* HAVE_UART_DEVICE */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_lowputc_enable_sysclk + * + * Description: + * Enable clock for the UART using the System register. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_enable_sysclk(const struct esp32s2_uart_s *priv) +{ + if (priv->id == 0) + { + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, + SYSTEM_UART_CLK_EN_M); + } + else + { + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, + SYSTEM_UART1_CLK_EN_M); + } +} + +/**************************************************************************** + * Name: esp32s2_lowputc_enable_memclk + * + * Description: + * Enable memory clock gate enable signal. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_enable_memclk(const struct esp32s2_uart_s *priv) +{ + modifyreg32(UART_CONF0_REG(priv->id), 0, UART_MEM_CLK_EN_M); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_disable_sysclk + * + * Description: + * Disable clock for the UART using the System register. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_disable_sysclk(const struct esp32s2_uart_s *priv) +{ + if (priv->id == 0) + { + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_UART_CLK_EN_M, 0); + } + else + { + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, SYSTEM_UART1_CLK_EN_M, 0); + } +} + +/**************************************************************************** + * Name: esp32s2_lowputc_disable_memclk + * + * Description: + * Disable memory clock gate enable signal. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_disable_memclk(const struct esp32s2_uart_s *priv) +{ + modifyreg32(UART_CONF0_REG(priv->id), UART_MEM_CLK_EN_M, 0); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_set_sclk + * + * Description: + * Set a source clock for UART. + * + * Parameters: + * priv - Pointer to the private driver struct. + * source - REF_TICK = 0 + * APB_CLK = 1 80 MHz + * + ****************************************************************************/ + +void esp32s2_lowputc_set_sclk(const struct esp32s2_uart_s *priv, + enum uart_sclk source) +{ + modifyreg32(UART_CONF0_REG(priv->id), UART_TICK_REF_ALWAYS_ON_M, source); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_get_sclk + * + * Description: + * Get the source clock for UART. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + * Returned Value: + * The frequency of the clock in Hz. + * + ****************************************************************************/ + +uint32_t esp32s2_lowputc_get_sclk(const struct esp32s2_uart_s * priv) +{ + uint32_t clk_conf_reg; + uint32_t ret = -ENODATA; + uint32_t clk; + clk_conf_reg = getreg32(UART_CONF0_REG(priv->id)); + clk = REG_MASK(clk_conf_reg, UART_TICK_REF_ALWAYS_ON); + if (clk == 1) + { + ret = esp_clk_apb_freq(); + } + else + { + /* TODO in esp32s2_clockconfig.c + * ret = esp32s2_clk_ref_freq(); + */ + } + + return ret; +} + +/**************************************************************************** + * Name: esp32s2_lowputc_baud + * + * Description: + * Set the baud rate according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_baud(const struct esp32s2_uart_s * priv) +{ + uint32_t sclk_freq; + uint32_t clk_div; + uint32_t int_part; + uint32_t frag_part; + + /* Get serial clock */ + + sclk_freq = esp32s2_lowputc_get_sclk(priv); + + /* Calculate the clock divisor to achieve the baud rate. + * baud = sclk/clk_div + * clk_div = int_part + (frag_part/16) + * 16*clk_div = 16*int_part + frag + * 16*clk_div = (sclk*16)/baud + */ + + clk_div = ((sclk_freq << 4) / (priv->baud)); + + /* Get the integer part of it. */ + + int_part = clk_div >> 4; + + /* Get the frag part of it. */ + + frag_part = clk_div & 0xf; + + /* Set integer part of the clock divisor for baud rate. */ + + int_part = VALUE_TO_FIELD(int_part, UART_CLKDIV); + modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_M, int_part); + + /* Set decimal part of the clock divisor for baud rate. */ + + frag_part = VALUE_TO_FIELD(frag_part, UART_CLKDIV_FRAG); + modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_FRAG_M, frag_part); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_normal_mode + * + * Description: + * Set the UART to operate in normal mode, i.e., disable the RS485 mode and + * IRDA mode. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_normal_mode(const struct esp32s2_uart_s * priv) +{ + /* Disable RS485 mode */ + + modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485_EN_M, 0); + modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485TX_RX_EN_M, 0); + modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485RXBY_TX_EN_M, 0); + + /* Disable IRDA mode */ + + modifyreg32(UART_CONF0_REG(priv->id), UART_IRDA_EN_M, 0); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_parity + * + * Description: + * Set the parity, according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_parity(const struct esp32s2_uart_s * priv) +{ + if (priv->parity == UART_PARITY_DISABLE) + { + modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M, 0); + } + else + { + modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_M, + ((priv->parity & BIT(0)) << UART_PARITY_S)); + modifyreg32(UART_CONF0_REG(priv->id), 0, UART_PARITY_EN_M); + } +} + +/**************************************************************************** + * Name: esp32s2_lowputc_data_length + * + * Description: + * Set the data bits length, according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +int esp32s2_lowputc_data_length(const struct esp32s2_uart_s * priv) +{ + int ret = OK; + uint32_t length = (priv->bits - 5); + + /* If it is the allowed range */ + + if (length >= UART_DATA_5_BITS && length <= UART_DATA_8_BITS) + { + modifyreg32(UART_CONF0_REG(priv->id), UART_BIT_NUM_M, + length << UART_BIT_NUM_S); + } + else + { + ret = -EINVAL; + } + + return ret; +} + +/**************************************************************************** + * Name: esp32s2_lowputc_stop_length + * + * Description: + * Set the stop bits length, according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_stop_length(const struct esp32s2_uart_s *priv) +{ + if (priv->stop_b2 == 0) + { + modifyreg32(UART_CONF0_REG(priv->id), UART_STOP_BIT_NUM_M, + UART_STOP_BITS_1 << UART_STOP_BIT_NUM_S); + } + else + { + modifyreg32(UART_CONF0_REG(priv->id), UART_STOP_BIT_NUM_M, + UART_STOP_BITS_2 << UART_STOP_BIT_NUM_S); + } +} + +/**************************************************************************** + * Name: esp32s2_lowputc_send_byte + * + * Description: + * Send one byte. + * + * Parameters: + * priv - Pointer to the private driver struct. + * byte - Byte to be sent. + * + ****************************************************************************/ + +void esp32s2_lowputc_send_byte(const struct esp32s2_uart_s * priv, + char byte) +{ + putreg32((uint32_t) byte, UART_FIFO_REG(priv->id)); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_is_tx_fifo_full + * + * Description: + * Verify if TX FIFO is full. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + * Returned Value: + * True if it is full, otherwise false. + * + ****************************************************************************/ + +bool esp32s2_lowputc_is_tx_fifo_full(const struct esp32s2_uart_s *priv) +{ + uint32_t reg; + uint32_t val; + reg = getreg32(UART_STATUS_REG(priv->id)); + val = REG_MASK(reg, UART_TXFIFO_CNT); + if (val < (UART_TX_FIFO_SIZE -1)) + { + return false; + } + else + { + return true; + } +} + +/**************************************************************************** + * Name: esp32s2_lowputc_rst_peripheral + * + * Description: + * Reset the UART peripheral by using System reg. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_rst_peripheral(const struct esp32s2_uart_s *priv) +{ + if (priv->id == 0) + { + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, SYSTEM_UART_RST_M); + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART_RST_M, 0); + } + else + { + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, SYSTEM_UART1_RST_M); + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART1_RST_M, 0); + } +} + +/**************************************************************************** + * Name: esp32s2_lowputc_rst_txfifo + * + * Description: + * Reset TX FIFO. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_rst_txfifo(const struct esp32s2_uart_s *priv) +{ + modifyreg32(UART_CONF0_REG(priv->id), 0, UART_TXFIFO_RST_M); + modifyreg32(UART_CONF0_REG(priv->id), UART_TXFIFO_RST_M, 0); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_rst_rxfifo + * + * Description: + * Reset RX FIFO. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_rst_rxfifo(const struct esp32s2_uart_s *priv) +{ + modifyreg32(UART_CONF0_REG(priv->id), 0, UART_RXFIFO_RST_M); + modifyreg32(UART_CONF0_REG(priv->id), UART_RXFIFO_RST_M, 0); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_disable_all_uart_int + * + * Description: + * Disable all UART interrupts. + * + * Parameters: + * priv - Pointer to the private driver struct. + * current_status - Pointer to a variable to store the current status of + * the interrupt enable register before disabling + * UART interrupts. + * + ****************************************************************************/ + +void esp32s2_lowputc_disable_all_uart_int(const struct esp32s2_uart_s *priv, + uint32_t *current_status) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + if (current_status != NULL) + { + /* Save current status */ + + *current_status = getreg32(UART_INT_ENA_REG(priv->id)); + } + + /* Disable all UART int */ + + putreg32(0, UART_INT_ENA_REG(priv->id)); + + /* Clear all ints */ + + putreg32(UINT32_MAX, UART_INT_CLR_REG(priv->id)); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_restore_all_uart_int + * + * Description: + * Restore all UART interrupts. + * + * Parameters: + * priv - Pointer to the private driver struct. + * last_status - Pointer to a variable that stored the last state of the + * interrupt enable register. + * + ****************************************************************************/ + +void esp32s2_lowputc_restore_all_uart_int(const struct esp32s2_uart_s *priv, + uint32_t *last_status) +{ + /* Restore the previous behaviour */ + + putreg32(*last_status, UART_INT_ENA_REG(priv->id)); +} + +/**************************************************************************** + * Name: esp32s2_lowputc_config_pins + * + * Description: + * Configure TX and RX UART pins. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_config_pins(const struct esp32s2_uart_s *priv) +{ + /* Configure the pins */ + + /* Route UART TX signal to the selected TX pin */ + + esp32s2_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0); + + /* Select the GPIO function to the TX pin and configure as output. */ + + esp32s2_configgpio(priv->txpin, OUTPUT_FUNCTION_1); + + /* Select the GPIO function to the RX pin and configure as input. */ + + esp32s2_configgpio(priv->rxpin, INPUT_FUNCTION_1); + + /* Route UART RX signal to the selected RX pin */ + + esp32s2_gpio_matrix_in(priv->rxpin, priv->rxsig, 0); +} + +/**************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console. + * + * Parameters: + * ch - Byte to be sent. + * + ****************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + +# if defined(CONFIG_UART0_SERIAL_CONSOLE) + struct esp32s2_uart_s *priv = &g_uart0_config; +#elif defined (CONFIG_UART1_SERIAL_CONSOLE) + struct esp32s2_uart_s *priv = &g_uart1_config; +#endif + + /* Wait until the TX FIFO has space to insert new char */ + + while (esp32s2_lowputc_is_tx_fifo_full(priv)); + + /* Then send the character */ + + esp32s2_lowputc_send_byte(priv, ch); + +#endif /* HAVE_CONSOLE */ +} + +/**************************************************************************** + * Name: esp32s2_lowsetup + * + * Description: + * This performs only the basic configuration for UART pins. + * + ****************************************************************************/ + +void esp32s2_lowsetup(void) +{ +#ifndef CONFIG_SUPPRESS_UART_CONFIG + +#ifdef CONFIG_ESP32S2_UART0 + + esp32s2_lowputc_config_pins(&g_uart0_config); + +#endif + +#ifdef CONFIG_ESP32S2_UART1 + + esp32s2_lowputc_config_pins(&g_uart1_config); + +#endif + +#endif /* !CONFIG_SUPPRESS_UART_CONFIG */ +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_lowputc.h b/arch/xtensa/src/esp32s2/esp32s2_lowputc.h new file mode 100644 index 0000000000..1bf123d510 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_lowputc.h @@ -0,0 +1,391 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_lowputc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_LOWPUTC_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "hardware/esp32s2_uart.h" +#include "hardware/esp32s2_gpio_sigmap.h" + +#include "esp32s2_cpuint.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum uart_sclk +{ + REF_TICK, + APB_CLK = 1, /* 80 MHz */ +}; + +enum uart_parity +{ + UART_PARITY_DISABLE, + UART_PARITY_ODD, + UART_PARITY_EVEN +}; + +enum uart_data_length +{ + UART_DATA_5_BITS, + UART_DATA_6_BITS, + UART_DATA_7_BITS, + UART_DATA_8_BITS +}; + +enum uart_stop_length +{ + UART_STOP_BITS_1 = 0x1, /* Stop bit: 1 bit */ + UART_STOP_BITS_2 = 0x3, /* Stop bit: 2 bits */ +}; + +/* Default FIFOs size */ + +#define UART_TX_FIFO_SIZE 128 +#define UART_RX_FIFO_SIZE 128 + +/* Struct used to store uart driver information and to + * manipulate uart driver + */ + +struct esp32s2_uart_s +{ + uint8_t periph; /* UART peripheral ID */ + int cpuint; /* CPU interrupt assigned to this UART */ + uint8_t id; /* UART ID */ + uint8_t irq; /* IRQ associated with this UART */ + uint32_t baud; /* Configured baud rate */ + uint8_t bits; /* Data length (5 to 8 bits). */ + uint8_t parity; /* 0=no parity, 1=odd parity, 2=even parity */ + uint8_t stop_b2; /* Use 2 stop bits? 0 = no (use 1) 1 = yes (use 2) */ + uint8_t int_pri; /* UART Interrupt Priority */ + uint8_t txpin; /* TX pin */ + uint8_t txsig; /* TX signal */ + uint8_t rxpin; /* RX pin */ + uint8_t rxsig; /* RX signal */ +}; + +extern struct esp32s2_uart_s g_uart0_config; +extern struct esp32s2_uart_s g_uart1_config; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_lowputc_enable_sysclk + * + * Description: + * Enable clock for the UART using the System register. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_enable_sysclk(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_enable_memclk + * + * Description: + * Enable memory clock gate enable signal. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_enable_memclk(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_disable_sysclk + * + * Description: + * Disable clock for the UART using the System register. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_disable_sysclk(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_disable_memclk + * + * Description: + * Disable memory clock gate enable signal. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_disable_memclk(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_set_sclk + * + * Description: + * Set a source clock for UART. + * + * Parameters: + * priv - Pointer to the private driver struct. + * source - REF_TICK = 0 + * APB_CLK = 1 80 MHz + * + ****************************************************************************/ + +void esp32s2_lowputc_set_sclk(const struct esp32s2_uart_s *priv, + enum uart_sclk source); + +/**************************************************************************** + * Name: esp32s2_lowputc_get_sclk + * + * Description: + * Get the source clock for UART. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + * Returned Value: + * The frequency of the clock in Hz. + * + ****************************************************************************/ + +uint32_t esp32s2_lowputc_get_sclk(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_baud + * + * Description: + * Set the baud rate according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_baud(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_normal_mode + * + * Description: + * Set the UART to operate in normal mode, i.e., disable the RS485 mode and + * IRDA mode. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_normal_mode(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_parity + * + * Description: + * Set the parity, according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_parity(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_data_length + * + * Description: + * Set the data bits length, according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +int esp32s2_lowputc_data_length(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_stop_length + * + * Description: + * Set the stop bits length, according to the value in the private driver + * struct. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_stop_length(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_send_byte + * + * Description: + * Send one byte. + * + * Parameters: + * priv - Pointer to the private driver struct. + * byte - Byte to be sent. + * + ****************************************************************************/ + +void esp32s2_lowputc_send_byte(const struct esp32s2_uart_s *priv, + char byte); + +/**************************************************************************** + * Name: esp32s2_lowputc_is_tx_fifo_full + * + * Description: + * Verify if TX FIFO is full. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + * Returned Value: + * True if it is full, otherwise false. + * + ****************************************************************************/ + +bool esp32s2_lowputc_is_tx_fifo_full(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_rst_peripheral + * + * Description: + * Reset the UART peripheral by using System reg. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_rst_peripheral(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_rst_txfifo + * + * Description: + * Reset TX FIFO. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_rst_txfifo(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_rst_rxfifo + * + * Description: + * Reset RX FIFO. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_rst_rxfifo(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowputc_disable_all_uart_int + * + * Description: + * Disable all UART interrupts. + * + * Parameters: + * priv - Pointer to the private driver struct. + * current_status - Pointer to a variable to store the current status of + * the interrupt enable register before disabling + * UART interrupts. + * + ****************************************************************************/ + +void esp32s2_lowputc_disable_all_uart_int(const struct esp32s2_uart_s *priv, + uint32_t *current_status); + +/**************************************************************************** + * Name: esp32s2_lowputc_restore_all_uart_int + * + * Description: + * Restore all UART interrupts. + * + * Parameters: + * priv - Pointer to the private driver struct. + * last_status - Pointer to a variable that stored the last state of the + * interrupt enable register. + * + ****************************************************************************/ + +void esp32s2_lowputc_restore_all_uart_int(const struct esp32s2_uart_s *priv, + uint32_t * last_status); + +/**************************************************************************** + * Name: esp32s2_lowputc_config_pins + * + * Description: + * Configure TX and RX UART pins. + * + * Parameters: + * priv - Pointer to the private driver struct. + * + ****************************************************************************/ + +void esp32s2_lowputc_config_pins(const struct esp32s2_uart_s *priv); + +/**************************************************************************** + * Name: esp32s2_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void esp32s2_lowsetup(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_LOWPUTC_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_pm.h b/arch/xtensa/src/esp32s2/esp32s2_pm.h new file mode 100644 index 0000000000..6e9f50cdc5 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_pm.h @@ -0,0 +1,218 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_pm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PMSLEEP_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PMSLEEP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Sleep wakeup cause */ + +enum esp32s2_sleep_source_e +{ +/* In case of deep sleep, reset was not caused by exit from deep sleep */ + + ESP_SLEEP_WAKEUP_UNDEFINED, + +/* Not a wakeup cause, used to disable all wakeup sources with + * esp_sleep_disable_wakeup_source + */ + + ESP_SLEEP_WAKEUP_ALL, + +/* Wakeup caused by external signal using RTC_IO */ + + ESP_SLEEP_WAKEUP_EXT0, + +/* Wakeup caused by external signal using RTC_CNTL */ + + ESP_SLEEP_WAKEUP_EXT1, + +/* Wakeup caused by timer */ + + ESP_SLEEP_WAKEUP_TIMER, + +/* Wakeup caused by touchpad */ + + ESP_SLEEP_WAKEUP_TOUCHPAD, + +/* Wakeup caused by ULP program */ + + ESP_SLEEP_WAKEUP_ULP, + +/* Wakeup caused by GPIO (light sleep only) */ + + ESP_SLEEP_WAKEUP_GPIO, + +/* Wakeup caused by UART (light sleep only) */ + + ESP_SLEEP_WAKEUP_UART, +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_sleep_enable_timer_wakeup + * + * Description: + * Configure wake-up interval + * + * Input Parameters: + * time_in_us - Configure wake-up time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_sleep_enable_timer_wakeup(uint64_t time_in_us); + +/**************************************************************************** + * Name: esp32s2_light_sleep_start + * + * Description: + * Enter sleep mode + * + * Input Parameters: + * None + * + * Returned Value: + * 0 is returned on success or a negated errno value is returned + * + ****************************************************************************/ + +int esp32s2_light_sleep_start(void); + +/**************************************************************************** + * Name: esp32s2_pminit + * + * Description: + * Initialize force sleep parameters. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_pminit(void); + +/**************************************************************************** + * Name: esp32s2_pmstandby + * + * Description: + * Enter force sleep time interval. + * + * Input Parameters: + * time_in_us - force sleep time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_pmstandby(uint64_t time_in_us); + +/**************************************************************************** + * Name: esp32s2_sleep_get_wakeup_cause + * + * Description: + * Get the wakeup source which caused wakeup from sleep. + * + * Input Parameters: + * None + * + * Returned Value: + * enum esp32s2_sleep_source_e - Cause of wake up from last sleep. + * + ****************************************************************************/ + +enum esp32s2_sleep_source_e esp32s2_sleep_get_wakeup_cause(void); + +/**************************************************************************** + * Name: esp32s2_deep_sleep_start + * + * Description: + * Enter deep sleep mode + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_deep_sleep_start(void); + +/**************************************************************************** + * Name: esp32s2_pmsleep + * + * Description: + * Enter deep sleep. + * + * Input Parameters: + * time_in_us - deep sleep time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_pmsleep(uint64_t time_in_us); + +#endif /* CONFIG_PM */ + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PMSLEEP_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_region.c b/arch/xtensa/src/esp32s2/esp32s2_region.c new file mode 100644 index 0000000000..a9d7595591 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_region.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_region.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint32_t g_protected_pages[] = +{ + 0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000 +}; + +#define NPROTECTED_PAGES (sizeof(g_protected_pages)/sizeof(uint32_t)) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_write_dtlb and xtensa_write_itlb + * + * Description: + * Functions to set page attributes for Region Protection option in the + * CPU. See Xtensa ISA Reference manual for explanation of arguments + * (section 4.6.3.2). + * + ****************************************************************************/ + +static inline void xtensa_write_dtlb(uint32_t vpn, unsigned int attr) +{ + __asm__ __volatile__ + ( + "wdtlb %1, %0\n" + "dsync\n" + : : "r" (vpn), "r" (attr) + ); +} + +static inline void xtensa_write_itlb(unsigned vpn, unsigned int attr) +{ + __asm__ __volatile__ + ( + "witlb %1, %0\n" + "isync\n" + : : "r" (vpn), "r" (attr) + ); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_region_protection + * + * Description: + * Make page 0 access raise an exception. Also protect some other unused + * pages so we can catch weirdness. + * + * Useful attribute values: + * 0 — cached, RW + * 2 — bypass cache, RWX (default value after CPU reset) + * 15 — no access, raise exception + * + ****************************************************************************/ + +void esp32s2_region_protection(void) +{ + int i; + + for (i = 0; i < NPROTECTED_PAGES; ++i) + { + xtensa_write_dtlb(g_protected_pages[i], 0xf); + xtensa_write_itlb(g_protected_pages[i], 0xf); + } + + xtensa_write_dtlb(0x20000000, 0); + xtensa_write_itlb(0x20000000, 0); +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_region.h b/arch/xtensa/src/esp32s2/esp32s2_region.h new file mode 100644 index 0000000000..67d20cf279 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_region.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_region.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_REGION_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_REGION_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_region_protection + * + * Description: + * Make page 0 access raise an exception. Also protect some other unused + * pages so we can catch weirdness. + * + * Useful attribute values: + * 0 — cached, RW + * 2 — bypass cache, RWX (default value after CPU reset) + * 15 — no access, raise exception + * + ****************************************************************************/ + +void esp32s2_region_protection(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_REGION_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc.c b/arch/xtensa/src/esp32s2/esp32s2_rtc.c new file mode 100644 index 0000000000..9ce3ae630b --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_rtc.c @@ -0,0 +1,562 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_rtc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "esp32s2_rtc.h" +#include "esp32s2_clockconfig.h" +#include "hardware/esp32s2_i2s.h" +#include "hardware/esp32s2_rtccntl.h" +#include "hardware/esp32s2_i2cbbpll.h" +#include "hardware/esp32s2_system.h" +#include "esp32s2_rtc.h" +#include "xtensa.h" +#include "xtensa_attr.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Various delays to be programmed into power control state machines */ + +#define RTC_CNTL_XTL_BUF_WAIT_SLP 2 +#define RTC_CNTL_CK8M_WAIT_SLP 4 +#define OTHER_BLOCKS_POWERUP 1 +#define OTHER_BLOCKS_WAIT 1 + +#define ROM_RAM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP +#define ROM_RAM_WAIT_CYCLES OTHER_BLOCKS_WAIT + +#define WIFI_POWERUP_CYCLES OTHER_BLOCKS_POWERUP +#define WIFI_WAIT_CYCLES OTHER_BLOCKS_WAIT + +#define RTC_POWERUP_CYCLES OTHER_BLOCKS_POWERUP +#define RTC_WAIT_CYCLES OTHER_BLOCKS_WAIT + +#define DG_WRAP_POWERUP_CYCLES OTHER_BLOCKS_POWERUP +#define DG_WRAP_WAIT_CYCLES OTHER_BLOCKS_WAIT + +#define RTC_MEM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP +#define RTC_MEM_WAIT_CYCLES OTHER_BLOCKS_WAIT + +#define RTC_CNTL_PLL_BUF_WAIT_SLP 2 + +#define DELAY_FAST_CLK_SWITCH 3 + +#define XTAL_32K_DAC_VAL 3 +#define XTAL_32K_DRES_VAL 3 +#define XTAL_32K_DBIAS_VAL 0 + +#define DELAY_SLOW_CLK_SWITCH 300 + +/* Number of fractional bits in values returned by rtc_clk_cal */ + +#define RTC_CLK_CAL_FRACT 19 + +/* With the default value of CK8M_DFREQ, + * 8M clock frequency is 8.5 MHz +/- 7% + */ + +#define RTC_FAST_CLK_FREQ_APPROX 8500000 + +/* Disable logging from the ROM code. */ + +#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) + +/* Default initializer for esp32s2_rtc_sleep_config_t + * This initializer sets all fields to "reasonable" values + * (e.g. suggested for production use) based on a combination + * of RTC_SLEEP_PD_x flags. + */ + +#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ + .lslp_mem_inf_fpu = 0, \ + .rtc_mem_inf_fpu = 0, \ + .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ + .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ + .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ + .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ + .wifi_pd_en = 0, \ + .rom_mem_pd_en = 0, \ + .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ + .wdt_flashboot_mod_en = 0, \ + .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \ + .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \ + .lslp_meminf_pd = 1, \ + .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ + .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1 \ +} + +/* Initializer for rtc_sleep_pd_config_t which + * sets all flags to the same value + */ + +#define RTC_SLEEP_PD_CONFIG_ALL(val) {\ + .dig_pd = (val), \ + .rtc_pd = (val), \ + .cpu_pd = (val), \ + .i2s_pd = (val), \ + .bb_pd = (val), \ + .nrx_pd = (val), \ + .fe_pd = (val), \ +} + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* RTC power and clock control initialization settings */ + +struct esp32s2_rtc_priv_s +{ + uint32_t ck8m_wait : 8; /* Number of rtc_fast_clk cycles to wait for 8M clock to be ready */ + uint32_t xtal_wait : 8; /* Number of rtc_fast_clk cycles to wait for XTAL clock to be ready */ + uint32_t pll_wait : 8; /* Number of rtc_fast_clk cycles to wait for PLL to be ready */ + uint32_t clkctl_init : 1; /* Perform clock control related initialization */ + uint32_t pwrctl_init : 1; /* Perform power control related initialization */ + uint32_t rtc_dboost_fpd : 1; /* Force power down RTC_DBOOST */ +}; + +/* sleep configuration for rtc_sleep_init function */ + +struct esp32s2_rtc_sleep_config_s +{ + uint32_t lslp_mem_inf_fpu : 1; /* force normal voltage in sleep mode (digital domain memory) */ + uint32_t rtc_mem_inf_fpu : 1; /* force normal voltage in sleep mode (RTC memory) */ + uint32_t rtc_mem_inf_follow_cpu : 1; /* keep low voltage in sleep mode (even if ULP/touch is used) */ + uint32_t rtc_fastmem_pd_en : 1; /* power down RTC fast memory */ + uint32_t rtc_slowmem_pd_en : 1; /* power down RTC slow memory */ + uint32_t rtc_peri_pd_en : 1; /* power down RTC peripherals */ + uint32_t wifi_pd_en : 1; /* power down WiFi */ + uint32_t rom_mem_pd_en : 1; /* power down main RAM and ROM */ + uint32_t deep_slp : 1; /* power down digital domain */ + uint32_t wdt_flashboot_mod_en : 1; /* enable WDT flashboot mode */ + uint32_t dig_dbias_wak : 3; /* set bias for digital domain, in active mode */ + uint32_t dig_dbias_slp : 3; /* set bias for digital domain, in sleep mode */ + uint32_t rtc_dbias_wak : 3; /* set bias for RTC domain, in active mode */ + uint32_t rtc_dbias_slp : 3; /* set bias for RTC domain, in sleep mode */ + uint32_t lslp_meminf_pd : 1; /* remove all peripheral force power up flags */ + uint32_t vddsdio_pd_en : 1; /* power down VDDSDIO regulator */ + uint32_t xtal_fpu : 1; /* keep main XTAL powered up in sleep */ +}; + +/* Power down flags for rtc_sleep_pd function */ + +struct esp32s2_rtc_sleep_pd_config_s +{ + uint32_t dig_pd : 1; /* Set to 1 to power down digital part in sleep */ + uint32_t rtc_pd : 1; /* Set to 1 to power down RTC memories in sleep */ + uint32_t cpu_pd : 1; /* Set to 1 to power down digital memories and CPU in sleep */ + uint32_t i2s_pd : 1; /* Set to 1 to power down I2S in sleep */ + uint32_t bb_pd : 1; /* Set to 1 to power down WiFi in sleep */ + uint32_t nrx_pd : 1; /* Set to 1 to power down WiFi in sleep */ + uint32_t fe_pd : 1; /* Set to 1 to power down WiFi in sleep */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void IRAM_ATTR esp32s2_rtc_sleep_pd( + struct esp32s2_rtc_sleep_pd_config_s cfg); +static inline bool esp32s2_clk_val_is_valid(uint32_t val); +static void IRAM_ATTR esp32s2_rtc_clk_fast_freq_set( + enum esp32s2_rtc_fast_freq_e fast_freq); +static uint32_t IRAM_ATTR esp32s2_rtc_clk_cal_internal( + enum esp32s2_rtc_cal_sel_e cal_clk, uint32_t slowclk_cycles); +static void IRAM_ATTR esp32s2_rtc_clk_slow_freq_set( + enum esp32s2_rtc_slow_freq_e slow_freq); +static void esp32s2_select_rtc_slow_clk(enum esp32s2_slow_clk_sel_e + slow_clk); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct esp32s2_rtc_priv_s esp32s2_rtc_priv = +{ + .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, + .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, + .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, + .clkctl_init = 1, + .pwrctl_init = 1, + .rtc_dboost_fpd = 1 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +extern void ets_delay_us(uint32_t us); + +/**************************************************************************** + * Name: esp32s2_clk_val_is_valid + * + * Description: + * Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are + * stored as two copies in lower and upper 16-bit halves. + * These are the routines to work with such a representation. + * + * Input Parameters: + * val - register value + * + * Returned Value: + * true: Valid register value. + * false: Invalid register value. + * + ****************************************************************************/ + +static inline bool esp32s2_clk_val_is_valid(uint32_t val) +{ + return (val & 0xffff) == ((val >> 16) & 0xffff) + && val != 0 && val != UINT32_MAX; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +enum esp32s2_rtc_xtal_freq_e rtc_get_xtal(void) + __attribute__((alias("esp32s2_rtc_clk_xtal_freq_get"))); + +/**************************************************************************** + * Name: esp32s2_rtc_clk_xtal_freq_get + * + * Description: + * Get main XTAL frequency + * + * Input Parameters: + * None + * + * Returned Value: + * XTAL frequency (one of enum esp32s2_rtc_xtal_freq_e values) + * + ****************************************************************************/ + +enum esp32s2_rtc_xtal_freq_e IRAM_ATTR esp32s2_rtc_clk_xtal_freq_get(void) +{ + /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */ + + uint32_t xtal_freq_reg = getreg32(RTC_XTAL_FREQ_REG); + + if (!esp32s2_clk_val_is_valid(xtal_freq_reg)) + { + return RTC_XTAL_FREQ_AUTO; + } + + return (xtal_freq_reg & ~RTC_DISABLE_ROM_LOG) & UINT16_MAX; +} + +/**************************************************************************** + * Name: esp32s2_rtc_update_to_xtal + * + * Description: + * Switch to XTAL frequency, does not disable the PLL + * + * Input Parameters: + * freq - XTAL frequency + * div - REF_TICK divider + * + * Returned Value: + * none + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_rtc_update_to_xtal(int freq, int div) +{ + uint32_t value = (((freq * MHZ) >> 12) & UINT16_MAX) + | ((((freq * MHZ) >> 12) & UINT16_MAX) << 16); + esp32s2_update_cpu_freq(freq); + + /* set divider from XTAL to APB clock */ + + REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, div - 1); + + /* adjust ref_tick */ + + modifyreg32(APB_CTRL_XTAL_TICK_CONF_REG, 0, + (freq * MHZ) / REF_CLK_FREQ - 1); + + /* switch clock source */ + + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, + RTC_CNTL_SOC_CLK_SEL_XTL); + putreg32(value, RTC_APB_FREQ_REG); + + /* lower the voltage */ + + if (freq <= 2) + { + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M); + } + else + { + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); + } +} + +/**************************************************************************** + * Name: esp32s2_rtc_bbpll_enable + * + * Description: + * Reset BBPLL configuration. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_rtc_bbpll_enable(void) +{ + modifyreg32(RTC_CNTL_OPTIONS0_REG, + RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD | + RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD, 0); + + /* reset BBPLL configuration */ + + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, + BBPLL_IR_CAL_DELAY_VAL); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, + BBPLL_IR_CAL_EXT_CAP_VAL); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, + BBPLL_OC_ENB_FCAL_VAL); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, + BBPLL_OC_ENB_VCON_VAL); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, + BBPLL_BBADC_CAL_7_0_VAL); +} + +/**************************************************************************** + * Name: esp32s2_rtc_bbpll_configure + * + * Description: + * Configure main XTAL frequency values according to pll_freq. + * + * Input Parameters: + * xtal_freq - XTAL frequency values + * pll_freq - PLL frequency values + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_rtc_bbpll_configure( + enum esp32s2_rtc_xtal_freq_e xtal_freq, int pll_freq) +{ + static uint8_t div_ref = 0; + static uint8_t div7_0 = 0; + static uint8_t dr1 = 0; + static uint8_t dr3 = 0; + static uint8_t dchgp = 0; + static uint8_t dcur = 0; + uint8_t i2c_bbpll_lref = 0; + uint8_t i2c_bbpll_div_7_0 = 0; + uint8_t i2c_bbpll_dcur = 0; + + if (pll_freq == RTC_PLL_FREQ_480M) + { + /* Clear this register to let the digital part know 480M PLL is used */ + + SET_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL); + + /* Configure 480M PLL */ + + div_ref = 0; + div7_0 = 8; + dr1 = 0; + dr3 = 0; + dchgp = 5; + dcur = 4; + + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6b); + } + else + { + /* Clear this register to let the digital part know 320M PLL is used */ + + CLEAR_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL); + + /* Configure 320M PLL */ + + div_ref = 0; + div7_0 = 4; + dr1 = 0; + dr3 = 0; + dchgp = 5; + dcur = 5; + + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69); + } + + i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref); + i2c_bbpll_div_7_0 = div7_0; + i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB) | + (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur; + + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0); + I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1); + I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3); + I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur); + + /* Enable calibration by software */ + + I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_ENX_CAP, 1); + + for (int ext_cap = 0; ext_cap < 16; ext_cap++) + { + uint8_t cal_result; + + I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, ext_cap); + cal_result = I2C_READREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OR_CAL_CAP); + if (cal_result == 0) + { + break; + } + + if (ext_cap == 15) + { + ets_printf("BBPLL SOFTWARE CAL FAIL\n"); + abort(); + } + } +} + +/**************************************************************************** + * Name: esp32s2_rtc_wait_for_slow_cycle + * + * Description: + * Busy loop until next RTC_SLOW_CLK cycle. + * + * Input Parameters: + * None + * + * Returned Value: + * none + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_rtc_wait_for_slow_cycle(void) +{ + modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING | + TIMG_RTC_CALI_START, 0); + modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY, 0); + REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, + RTC_CAL_RTC_MUX); + + /* Request to run calibration for 0 slow clock cycles. + * RDY bit will be set on the nearest slow clock cycle. + */ + + REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, 0); + modifyreg32(TIMG_RTCCALICFG_REG(0), 0, TIMG_RTC_CALI_START); + + /* RDY needs some time to go low */ + + ets_delay_us(1); + + while (!(getreg32(TIMG_RTCCALICFG_REG(0)) & TIMG_RTC_CALI_RDY)) + { + ets_delay_us(1); + } +} + +/**************************************************************************** + * Name: esp_rtc_clk_get_cpu_freq + * + * Description: + * Get the currently used CPU frequency configuration. + * + * Input Parameters: + * None + * + * Returned Value: + * CPU frequency + * + ****************************************************************************/ + +int IRAM_ATTR esp_rtc_clk_get_cpu_freq(void) +{ + uint32_t source_freq_mhz; + uint32_t div; + uint32_t soc_clk_sel; + uint32_t cpuperiod_sel; + int freq_mhz = 0; + + soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); + switch (soc_clk_sel) + { + case RTC_CNTL_SOC_CLK_SEL_XTL: + { + div = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG, + APB_CTRL_PRE_DIV_CNT) + 1; + source_freq_mhz = (uint32_t) esp32s2_rtc_clk_xtal_freq_get(); + freq_mhz = source_freq_mhz / div; + } + break; + + case RTC_CNTL_SOC_CLK_SEL_PLL: + { + cpuperiod_sel = REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, + SYSTEM_CPUPERIOD_SEL); + if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) + { + freq_mhz = 80; + } + else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) + { + freq_mhz = 160; + } + else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) + { + freq_mhz = 240; + } + else + { + DEBUGASSERT(0); + } + } + break; + + case RTC_CNTL_SOC_CLK_SEL_8M: + { + freq_mhz = 8; + } + break; + + case RTC_CNTL_SOC_CLK_SEL_APLL: + default: + DEBUGASSERT(0); + } + + return freq_mhz; +} + diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc.h b/arch/xtensa/src/esp32s2/esp32s2_rtc.h new file mode 100644 index 0000000000..be7cc151cd --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_rtc.h @@ -0,0 +1,358 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_rtc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/esp32s2_soc.h" + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of cycles to wait from the 32k XTAL oscillator to + * consider it running. Larger values increase startup delay. + * Smaller values may cause false positive detection + * (i.e. oscillator runs for a few cycles and then stops). + */ + +#define SLOW_CLK_CAL_CYCLES 1024 + +/* Indicates that 32k oscillator gets input from external oscillator + * instead of a crystal. + */ + +#define EXT_OSC_FLAG BIT(3) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Possible main XTAL frequency values. + * Enum values should be equal to frequency in MHz. + */ + +enum esp32s2_rtc_xtal_freq_e +{ + RTC_XTAL_FREQ_AUTO = 0, /* Automatic XTAL frequency detection */ + RTC_XTAL_FREQ_40M = 40, /* 40 MHz XTAL */ + RTC_XTAL_FREQ_26M = 26, /* 26 MHz XTAL */ + RTC_XTAL_FREQ_24M = 24, /* 24 MHz XTAL */ +}; + +/* RTC SLOW_CLK frequency values */ + +enum esp32s2_rtc_slow_freq_e +{ + RTC_SLOW_FREQ_RTC = 0, /* Internal 150 kHz RC oscillator */ + RTC_SLOW_FREQ_32K_XTAL = 1, /* External 32 kHz XTAL */ + RTC_SLOW_FREQ_8MD256 = 2, /* Internal 8 MHz RC oscillator, divided by 256 */ +}; + +/* RTC FAST_CLK frequency values */ + +enum esp32s2_rtc_fast_freq_e +{ + RTC_FAST_FREQ_XTALD4 = 0, /* Main XTAL, divided by 4 */ + RTC_FAST_FREQ_8M = 1, /* Internal 8 MHz RC oscillator */ +}; + +/* This is almost the same as esp32s2_rtc_slow_freq_e, except that we define + * an extra enum member for the external 32k oscillator. For convenience, + * lower 2 bits should correspond to esp32s2_rtc_slow_freq_e values. + */ + +enum esp32s2_slow_clk_sel_e +{ + /* Internal 150 kHz RC oscillator */ + + SLOW_CLK_150K = RTC_SLOW_FREQ_RTC, + + /* External 32 kHz XTAL */ + + SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, + + /* Internal 8 MHz RC oscillator, divided by 256 */ + + SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, + + /* External 32k oscillator connected to 32K_XP pin */ + + SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG +}; + +/* Clock source to be calibrated using rtc_clk_cal function */ + +enum esp32s2_rtc_cal_sel_e +{ + RTC_CAL_RTC_MUX = 0, /* Currently selected RTC SLOW_CLK */ + RTC_CAL_8MD256 = 1, /* Internal 8 MHz RC oscillator, divided by 256 */ + RTC_CAL_32K_XTAL = 2 /* External 32 kHz XTAL */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_rtc_get_slow_clk_rtc + * + * Description: + * Get slow_clk_rtc source. + * + * Input Parameters: + * None + * + * Returned Value: + * The clock source: + * - SLOW_CK + * - CK_XTAL_32K + * - CK8M_D256_OUT + * + ****************************************************************************/ + +enum esp32s2_rtc_slow_freq_e esp32s2_rtc_get_slow_clk(void); + +/**************************************************************************** + * Name: esp32s2_rtc_clk_cal + * + * Description: + * Measure RTC slow clock's period, based on main XTAL frequency + * + * Input Parameters: + * cal_clk - clock to be measured + * slowclk_cycles - number of slow clock cycles to average + * + * Returned Value: + * Average slow clock period in microseconds, Q13.19 fixed point format + * or 0 if calibration has timed out + * + ****************************************************************************/ + +uint32_t esp32s2_rtc_clk_cal(enum esp32s2_rtc_cal_sel_e cal_clk, + uint32_t slowclk_cycles); + +/**************************************************************************** + * Name: esp32s2_rtc_clk_xtal_freq_get + * + * Description: + * Get main XTAL frequency + * + * Input Parameters: + * None + * + * Returned Value: + * XTAL frequency (one of enum esp32s2_rtc_xtal_freq_e values) + * + ****************************************************************************/ + +enum esp32s2_rtc_xtal_freq_e esp32s2_rtc_clk_xtal_freq_get(void); + +/**************************************************************************** + * Name: esp32s2_rtc_update_to_xtal + * + * Description: + * Switch to XTAL frequency, does not disable the PLL + * + * Input Parameters: + * freq - XTAL frequency + * div - REF_TICK divider + * + * Returned Value: + * none + * + ****************************************************************************/ + +void esp32s2_rtc_update_to_xtal(int freq, int div); + +/**************************************************************************** + * Name: esp32s2_rtc_bbpll_enable + * + * Description: + * Reset BBPLL configuration. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_bbpll_enable(void); + +/**************************************************************************** + * Name: esp32s2_rtc_bbpll_configure + * + * Description: + * Configure main XTAL frequency values according to pll_freq. + * + * Input Parameters: + * xtal_freq - XTAL frequency values + * pll_freq - PLL frequency values + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_bbpll_configure( + enum esp32s2_rtc_xtal_freq_e xtal_freq, int pll_freq); + +/**************************************************************************** + * Name: esp32s2_rtc_clk_set + * + * Description: + * Set RTC CLK frequency. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_clk_set(void); + +/**************************************************************************** + * Name: esp32s2_rtc_init + * + * Description: + * Initialize RTC clock and power control related functions. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_init(void); + +/**************************************************************************** + * Name: esp32s2_rtc_time_get + * + * Description: + * Get current value of RTC counter. + * + * Input Parameters: + * None + * + * Returned Value: + * current value of RTC counter + * + ****************************************************************************/ + +uint64_t esp32s2_rtc_time_get(void); + +/**************************************************************************** + * Name: esp32s2_rtc_wait_for_slow_cycle + * + * Description: + * Busy loop until next RTC_SLOW_CLK cycle. + * + * Input Parameters: + * None + * + * Returned Value: + * none + * + ****************************************************************************/ + +void esp32s2_rtc_wait_for_slow_cycle(void); + +/**************************************************************************** + * Name: esp_rtc_clk_get_cpu_freq + * + * Description: + * Get the currently used CPU frequency configuration. + * + * Input Parameters: + * None + * + * Returned Value: + * CPU frequency + * + ****************************************************************************/ + +int esp_rtc_clk_get_cpu_freq(void); + +/**************************************************************************** + * Name: esp32s2_rtc_sleep_init + * + * Description: + * Prepare the chip to enter sleep mode + * + * Input Parameters: + * flags - sleep mode configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_sleep_init(uint32_t flags); + +/**************************************************************************** + * Name: esp32s2_rtc_sleep_start + * + * Description: + * Enter force sleep mode. + * + * Input Parameters: + * wakeup_opt - bit mask wake up reasons to enable + * reject_opt - bit mask of sleep reject reasons. + * + * Returned Value: + * non-zero if sleep was rejected by hardware + * + ****************************************************************************/ + +int esp32s2_rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_serial.c b/arch/xtensa/src/esp32s2/esp32s2_serial.c new file mode 100644 index 0000000000..c401f7bfbb --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_serial.c @@ -0,0 +1,1031 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include "xtensa.h" + +#include "hardware/esp32s2_uart.h" +#include "hardware/esp32s2_system.h" + +#include "esp32s2_config.h" +#include "esp32s2_cpuint.h" +#include "esp32s2_lowputc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The console is enabled, and it's not the syslog device, + * so, it should be a serial device. + */ + +#ifdef USE_SERIALDRIVER + +/* Which UART will be tty0/console and which tty1? */ + +/* First pick the console and ttys0. + * Console can be UART0 or UART1, but will always be ttys0. + */ + +/* In case a UART was assigned to be + * the console and the corresponding peripheral was also selected. + */ + +#ifdef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0_dev /* UART0 is console */ +# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1_dev /* UART1 is console */ +# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# endif /* CONFIG_UART0_SERIAL_CONSOLE */ +#else /* No console */ +# undef CONSOLE_DEV +# if defined(CONFIG_ESP32S2_UART0) +# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */ +# define UART0_ASSIGNED 1 +# elif defined(CONFIG_ESP32S2_UART1) +# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */ +# define UART1_ASSIGNED 1 +# endif +#endif /* HAVE_SERIAL_CONSOLE */ + +/* Pick ttys1 */ + +#if defined(CONFIG_ESP32S2_UART0) && !defined(UART0_ASSIGNED) +# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */ +# define UART0_ASSIGNED 1 +#elif defined(CONFIG_ESP32S2_UART1) && !defined(UART1_ASSIGNED) +# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */ +# define UART1_ASSIGNED 1 +#endif + +#ifdef HAVE_UART_DEVICE + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Serial driver methods */ + +static int esp32s2_setup(struct uart_dev_s *dev); +static void esp32s2_shutdown(struct uart_dev_s *dev); +static int esp32s2_attach(struct uart_dev_s *dev); +static void esp32s2_detach(struct uart_dev_s *dev); +static void esp32s2_txint(struct uart_dev_s *dev, bool enable); +static void esp32s2_rxint(struct uart_dev_s *dev, bool enable); +static bool esp32s2_rxavailable(struct uart_dev_s *dev); +static bool esp32s2_txready(struct uart_dev_s *dev); +static bool esp32s2_txempty(struct uart_dev_s *dev); +static void esp32s2_send(struct uart_dev_s *dev, int ch); +static int esp32s2_receive(struct uart_dev_s *dev, unsigned int *status); +static int esp32s2_ioctl(struct file *filep, int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Operations */ + +static struct uart_ops_s g_uart_ops = +{ + .setup = esp32s2_setup, + .shutdown = esp32s2_shutdown, + .attach = esp32s2_attach, + .detach = esp32s2_detach, + .txint = esp32s2_txint, + .rxint = esp32s2_rxint, + .rxavailable = esp32s2_rxavailable, + .txready = esp32s2_txready, + .txempty = esp32s2_txempty, + .send = esp32s2_send, + .receive = esp32s2_receive, + .ioctl = esp32s2_ioctl, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif +}; + +/* UART 0 */ + +#ifdef CONFIG_ESP32S2_UART0 + +static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE]; + +/* Fill only the requested fields */ + +static uart_dev_t g_uart0_dev = +{ +#ifdef CONFIG_UART0_SERIAL_CONSOLE + .isconsole = true, +#else + .isconsole = false, +#endif + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0_txbuffer, + }, + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0_rxbuffer, + }, + + .ops = &g_uart_ops, + .priv = &g_uart0_config +}; + +#endif + +/* UART 1 */ + +#ifdef CONFIG_ESP32S2_UART1 + +static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE]; + +/* Fill only the requested fields */ + +static uart_dev_t g_uart1_dev = +{ +#ifdef CONFIG_UART1_SERIAL_CONSOLE + .isconsole = true, +#else + .isconsole = false, +#endif + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1_txbuffer, + }, + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1_rxbuffer, + }, + + .ops = &g_uart_ops, + .priv = &g_uart1_config +}; + +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: uart_handler + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt is received on the 'irq' It should call uart_xmitchars or + * uart_recvchars to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int uart_handler(int irq, FAR void *context, FAR void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct esp32s2_uart_s *priv = dev->priv; + uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M; + uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M; + uint32_t int_status; + + int_status = getreg32(UART_INT_ST_REG(priv->id)); + + /* TX FIFO empty interrupt or UART TX done int */ + + if (int_status & tx_mask) + { + /* Unload the SW TX FIFO into the HW TX FIFO and clear interrupts */ + + uart_xmitchars(dev); + modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask); + } + + /* Rx fifo timeout interrupt or rx fifo full interrupt */ + + if (int_status & rx_mask) + { + /* Load the SW RX FIFO with the HW RX FIFO content and clear + * interrupts. + */ + + uart_recvchars(dev); + modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask); + } + + return OK; +} + +/**************************************************************************** + * Name: esp32s2_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This method is + * called the first time that the serial port is opened. + * For the serial console, this will occur very early in initialization, + * for other serial ports this will occur when the port is first opened. + * This setup does not include attaching or enabling interrupts. + * That portion of the UART setup is performed when the attach() method + * is called. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * + * Returned Values: + * Zero (OK) is returned. + * + ****************************************************************************/ + +static int esp32s2_setup(struct uart_dev_s *dev) +{ + struct esp32s2_uart_s *priv = dev->priv; + + /* Initialize UART module */ + + /* Discard corrupt RX data */ + + modifyreg32(UART_CONF0_REG(priv->id), 0, UART_ERR_WR_MASK_M); + + /* Define 0 as the threshold that means TX FIFO buffer is empty. */ + + modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0); + + /* Define a threshold to trigger an RX FIFO FULL interrupt. + * Define just one byte to read data immediately. + */ + + modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M, + 1 << UART_RXFIFO_FULL_THRHD_S); + + /* Define the maximum FIFO size for RX and TX FIFO. + * 1 block = 128 bytes. + * As a consequence, software serial FIFO can unload the bytes and + * not wait too much on polling activity. + */ + + modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M, + (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S)); + + /* Configure the UART Baud Rate */ + + esp32s2_lowputc_baud(priv); + + /* Set a mode */ + + esp32s2_lowputc_normal_mode(priv); + + /* Parity */ + + esp32s2_lowputc_parity(priv); + + /* Data Frame size */ + + esp32s2_lowputc_data_length(priv); + + /* Stop bit */ + + esp32s2_lowputc_stop_length(priv); + + /* Reset FIFOs */ + + esp32s2_lowputc_rst_txfifo(priv); + esp32s2_lowputc_rst_rxfifo(priv); + + return OK; +} + +/**************************************************************************** + * Name: esp32s2_shutdown + * + * Description: + * Disable the UART. This method is called when the serial port is closed. + * This method reverses the operation the setup method. NOTE that the serial + * console is never shutdown. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * + ****************************************************************************/ + +static void esp32s2_shutdown(struct uart_dev_s *dev) +{ + struct esp32s2_uart_s *priv = dev->priv; + + /* Disable ints */ + + esp32s2_lowputc_disable_all_uart_int(priv, NULL); + + /* Disable clk */ + + esp32s2_lowputc_disable_sysclk(priv); + + /* Disable memory clock */ + + esp32s2_lowputc_disable_memclk(priv); +} + +/**************************************************************************** + * Name: esp32s2_attach + * + * Description: + * Configure the UART to operate in interrupt driven mode. This method + * is called when the serial port is opened. Normally, this is just after + * the the setup() method is called, however, the serial console may + * operate in a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * + * Returned Values: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +static int esp32s2_attach(struct uart_dev_s *dev) +{ + struct esp32s2_uart_s *priv = dev->priv; + int ret; + + DEBUGASSERT(priv->cpuint == -ENOMEM); + + /* Alloc a level CPU interrupt */ + + priv->cpuint = esp32s2_alloc_levelint(priv->int_pri); + if (priv->cpuint < 0) + { + return priv->cpuint; + } + else + { + /* Disable the allocated CPU interrupt */ + + up_disable_irq(priv->cpuint); + + /* Attach a peripheral interrupt to a CPU interrupt */ + + esp32s2_attach_peripheral(priv->periph, priv->cpuint); + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, uart_handler, dev); + if (ret == OK) + { + up_enable_irq(priv->cpuint); + } + } + + return ret; +} + +/**************************************************************************** + * Name: esp32s2_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * + ****************************************************************************/ + +static void esp32s2_detach(struct uart_dev_s *dev) +{ + struct esp32s2_uart_s *priv = dev->priv; + + DEBUGASSERT(priv->cpuint != -ENOMEM); + + /* Disable the CPU interrupt and detach the IRQ */ + + up_disable_irq(priv->cpuint); + irq_detach(priv->irq); + + /* Disassociate the peripheral interrupt from the CPU interrupt */ + + esp32s2_detach_peripheral(priv->periph, priv->cpuint); + + /* Release the CPU interrupt */ + + esp32s2_free_cpuint(priv->periph); + + /* Reset cpuint */ + + priv->cpuint = -ENOMEM; +} + +/**************************************************************************** + * Name: esp32s2_txint + * + * Description: + * Enable or disable TX interrupts. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * enable - If true enables the TX interrupt, if false disables it. + * + ****************************************************************************/ + +static void esp32s2_txint(struct uart_dev_s *dev, bool enable) +{ + struct esp32s2_uart_s *priv = dev->priv; + uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M; + + if (enable) + { + /* Set to receive an interrupt when the TX holding FIFO is empty or + * a transmission is done. + */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + modifyreg32(UART_INT_ENA_REG(priv->id), 0, ints_mask); +#endif + } + else + { + /* Disable the TX interrupts */ + + modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0); + } +} + +/**************************************************************************** + * Name: esp32s2_rxint + * + * Description: + * Enable or disable RX interrupts. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * enable - If true enables the RX interrupt, if false disables it. + * + ****************************************************************************/ + +static void esp32s2_rxint(struct uart_dev_s *dev, bool enable) +{ + struct esp32s2_uart_s *priv = dev->priv; + uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M | + UART_RXFIFO_FULL_INT_ENA_M; + + if (enable) + { + /* Receive an interrupt when there is anything in the RX FIFO + * (or when a RX timeout occurs). + * NOTE: RX timeout feature needs to be enabled. + */ +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + modifyreg32(UART_CONF1_REG(priv->id), 0, UART_RX_TOUT_EN_M); + modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask); +#endif + } + else + { + modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0); + + /* Disable the RX interrupts */ + + modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0); + } +} + +/**************************************************************************** + * Name: esp32s2_rxavailable + * + * Description: + * Check if there is any data available to be read. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * + * Returned Values: + * Return true if the RX FIFO is not empty and false if RX FIFO is empty. + * + ****************************************************************************/ + +static bool esp32s2_rxavailable(struct uart_dev_s *dev) +{ + struct esp32s2_uart_s *priv = dev->priv; + uint32_t status_reg; + uint32_t bytes; + + status_reg = getreg32(UART_STATUS_REG(priv->id)); + + bytes = REG_MASK(status_reg, UART_RXFIFO_CNT); + + return (bytes > 0) ? true : false; +} + +/**************************************************************************** + * Name: esp32s2_txready + * + * Description: + * Check if the transmit hardware is ready to send another byte. + * This is used to determine if send() method can be called. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * + * Returned Values: + * Return true if the transmit hardware is ready to send another byte, + * false otherwise. + * + ****************************************************************************/ + +static bool esp32s2_txready(struct uart_dev_s *dev) +{ + return (esp32s2_lowputc_is_tx_fifo_full(dev->priv)) ? false : true; +} + +/**************************************************************************** + * Name: esp32s2_txempty + * + * Description: + * Verify if all characters have been sent. If for example, the UART + * hardware implements FIFOs, then this would mean the transmit FIFO is + * empty. This method is called when the driver needs to make sure that + * all characters are "drained" from the TX hardware. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * + * Returned Values: + * Return true if the TX FIFO is empty, false if it is not. + * + ****************************************************************************/ + +static bool esp32s2_txempty(struct uart_dev_s *dev) +{ + uint32_t reg; + struct esp32s2_uart_s *priv = dev->priv; + + reg = getreg32(UART_INT_RAW_REG(priv->id)); + + reg = REG_MASK(reg, UART_TXFIFO_EMPTY_INT_RAW); + + return (reg > 0) ? true : false; +} + +/**************************************************************************** + * Name: esp32s2_send + * + * Description: + * Send a unique character + * + * Parameters: + * dev - Pointer to the serial driver struct. + * ch - Byte to be sent. + * + ****************************************************************************/ + +static void esp32s2_send(struct uart_dev_s *dev, int ch) +{ + esp32s2_lowputc_send_byte(dev->priv, ch); +} + +/**************************************************************************** + * Name: esp32s2_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + * Parameters: + * dev - Pointer to the serial driver struct. + * status - Pointer to a variable to store eventual error bits. + * + * Returned Values: + * Return the byte read from the RX FIFO. + * + ****************************************************************************/ + +static int esp32s2_receive(struct uart_dev_s *dev, unsigned int *status) +{ + uint32_t rx_fifo; + struct esp32s2_uart_s *priv = dev->priv; + + rx_fifo = getreg32(UART_FIFO_REG(priv->id)); + rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M; + + /* Since we don't have error bits associated with receipt, we set zero */ + + *status = 0; + + return (int)rx_fifo; +} + +/**************************************************************************** + * Name: esp32s2_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * Here it's employed to implement the TERMIOS ioctls and TIOCSERGSTRUCT. + * + * Parameters: + * filep Pointer to a file structure instance. + * cmd The ioctl command. + * arg The argument of the ioctl cmd. + * + * Returned Value: + * Returns a non-negative number on success; A negated errno value is + * returned on any failure (see comments ioctl() for a list of appropriate + * errno values). + * + ****************************************************************************/ + +static int esp32s2_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + /* Get access to the internal instance of the driver through the file + * pointer. + */ + +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; +#endif + int ret = OK; + + /* Run the requested ioctl command. */ + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + + /* Get the internal driver data structure for debug purposes. */ + + case TIOCSERGSTRUCT: + { + struct esp32s2_uart_s *user = (struct esp32s2_uart_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev->priv, sizeof(struct esp32s2_uart_s)); + } + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + + /* Fill a termios structure with the required information. */ + + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + struct esp32s2_uart_s *priv = (struct esp32s2_uart_s *)dev->priv; + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Return parity (0 = no parity, 1 = odd parity, 2 = even parity). */ + + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0); + + /* Return stop bits */ + + termiosp->c_cflag |= (priv->stop_b2) ? CSTOPB : 0; + + /* Set the baud rate in the termiosp using the + * cfsetispeed interface. + */ + + cfsetispeed(termiosp, priv->baud); + + /* Return number of bits. */ + + switch (priv->bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + + case 6: + termiosp->c_cflag |= CS6; + break; + + case 7: + termiosp->c_cflag |= CS7; + break; + + default: + case 8: + termiosp->c_cflag |= CS8; + break; + } + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + struct esp32s2_uart_s *priv = (struct esp32s2_uart_s *)dev->priv; + uint32_t baud; + uint32_t current_int_sts; + uint8_t parity; + uint8_t bits; + uint8_t stop2; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Get the target baud rate to change. */ + + baud = cfgetispeed(termiosp); + + /* Decode number of bits. */ + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + bits = 5; + break; + + case CS6: + bits = 6; + break; + + case CS7: + bits = 7; + break; + + case CS8: + bits = 8; + break; + + default: + ret = -EINVAL; + break; + } + + /* Decode parity. */ + + if ((termiosp->c_cflag & PARENB) != 0) + { + parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + parity = 0; + } + + /* Decode stop bits. */ + + stop2 = (termiosp->c_cflag & CSTOPB) ? 1 : 0; + + /* Verify that all settings are valid before + * performing the changes. + */ + + if (ret == OK) + { + /* Fill the private struct fields. */ + + priv->baud = baud; + priv->parity = parity; + priv->bits = bits; + priv->stop_b2 = stop2; + + /* Effect the changes immediately - note that we do not + * implement TCSADRAIN or TCSAFLUSH, only TCSANOW option. + * See nuttx/libs/libc/termios/lib_tcsetattr.c + */ + + esp32s2_lowputc_disable_all_uart_int(priv, ¤t_int_sts); + ret = esp32s2_setup(dev); + + /* Restore the interrupt state */ + + esp32s2_lowputc_restore_all_uart_int(priv, ¤t_int_sts); + } + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT + +/**************************************************************************** + * Name: xtensa_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before xtensa_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in esp32s2_lowsetup. + * + ****************************************************************************/ + +void xtensa_earlyserialinit(void) +{ + /* NOTE: All GPIO configuration for the UARTs was performed in + * esp32s2_lowsetup + */ + + /* Disable all UARTS interrupts */ + + esp32s2_lowputc_disable_all_uart_int(TTYS0_DEV.priv, NULL); +#ifdef TTYS1_DEV + esp32s2_lowputc_disable_all_uart_int(TTYS1_DEV.priv, NULL); +#endif + + /* Configure console in early step. + * Setup for other serials will be perfomed when the serial driver is + * open. + */ + +#ifdef HAVE_SERIAL_CONSOLE + esp32s2_setup(&CONSOLE_DEV); +#endif +} + +#endif /* USE_EARLYSERIALINIT */ + +/**************************************************************************** + * Name: xtensa_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that xtensa_earlyserialinit was called previously. + * + ****************************************************************************/ + +void xtensa_serialinit(void) +{ +#ifdef HAVE_SERIAL_CONSOLE + uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* At least one UART char driver will logically be registered */ + + uart_register("/dev/ttyS0", &TTYS0_DEV); + +#ifdef TTYS1_DEV + uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + uint32_t int_status; + + esp32s2_lowputc_disable_all_uart_int(CONSOLE_DEV.priv, &int_status); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + esp32s2_lowputc_restore_all_uart_int(CONSOLE_DEV.priv, &int_status); +#endif + return ch; +} + +#else /* HAVE_UART_DEVICE */ + +/**************************************************************************** + * Name: xtensa_earlyserialinit, xtensa_serialinit, and up_putc + * + * Description: + * Stubs that may be needed. These stubs will be used if all UARTs are + * disabled. In that case, the logic in common/up_initialize() is not + * smart enough to know that there are not UARTs and will still expect + * these interfaces to be provided. + * This may be a special case where the upper and lower half serial layers + * are added but other device is used as console. + * For more details, take a look at: nuttx/arch/xtensa/src/common/xtensa.h + * + ****************************************************************************/ + +void xtensa_earlyserialinit(void) +{ +} + +void xtensa_serialinit(void) +{ +} + +int up_putc(int ch) +{ + return ch; +} + +#endif /* HAVE_UART_DEVICE */ +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * This up_putc is a utility when the serial driver is not ready yet but + * UART is selected and we have a basic lowsetup. + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + uint32_t int_status; + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + xtensa_lowputc('\r'); + } + + xtensa_lowputc(ch); +#endif + return ch; +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_start.c b/arch/xtensa/src/esp32s2/esp32s2_start.c new file mode 100644 index 0000000000..a272c81a6d --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_start.c @@ -0,0 +1,169 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_start.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "xtensa.h" +#include "xtensa_attr.h" + +#include "hardware/esp32s2_rtccntl.h" +#include "esp32s2_clockconfig.h" +#include "esp32s2_region.h" +#include "esp32s2_start.h" +#include "esp32s2_lowputc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) up_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Address of the CPU0 IDLE thread */ + +uint32_t g_idlestack[IDLETHREAD_STACKWORDS] + __attribute__((aligned(16), section(".noinit"))); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __start + * + * Description: + * We arrive here after the bootloader finished loading the program from + * flash. The hardware is mostly uninitialized, and the app CPU is in + * reset. We do have a stack, so we can do the initialization in C. + * + ****************************************************************************/ + +void IRAM_ATTR __start(void) +{ + uint32_t *dest; + uint32_t regval; + uint32_t sp; + + /* Kill the watchdog timer */ + + regval = getreg32(RTC_CNTL_WDTCONFIG0_REG); + regval &= ~RTC_CNTL_WDT_FLASHBOOT_MOD_EN; + putreg32(regval, RTC_CNTL_WDTCONFIG0_REG); + + regval = getreg32(DR_REG_BB_BASE + 0x48); /* DR_REG_BB_BASE+48 */ + regval &= ~(1 << 14); + putreg32(regval, DR_REG_BB_BASE + 0x48); + + /* Make sure that normal interrupts are disabled. This is really only an + * issue when we are started in un-usual ways (such as from IRAM). In this + * case, we can at least defer some unexpected interrupts left over from + * the last program execution. + */ + + up_irq_disable(); + + /* Set CPU frequency configured in board.h */ + + esp32s2_clockconfig(); + + esp32s2_lowsetup(); + +#ifdef USE_EARLYSERIALINIT + /* Perform early serial initialization */ + + xtensa_earlyserialinit(); +#endif + +#ifdef CONFIG_STACK_COLORATION + { + register uint32_t *ptr; + register int i; + + /* If stack debug is enabled, then fill the stack with a recognizable + * value that we can use later to test for high water marks. + */ + + for (i = 0, ptr = g_idlestack; i < IDLETHREAD_STACKWORDS; i++) + { + *ptr++ = STACK_COLOR; + } + } +#endif + + /* Move the stack to a known location. Although we were given a stack + * pointer at start-up, we don't know where that stack pointer is + * positioned with respect to our memory map. The only safe option is to + * switch to a well-known IDLE thread stack. + */ + + sp = (uint32_t)g_idlestack + IDLETHREAD_STACKSIZE; + __asm__ __volatile__("mov sp, %0\n" : : "r"(sp)); + + /* Make page 0 access raise an exception */ + + esp32s2_region_protection(); + + /* Move CPU0 exception vectors to IRAM */ + + __asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (&_init_start)); + + showprogress('A'); + + /* Set .bss to zero */ + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; dest++) + { + *dest = 0; + } + + showprogress('B'); + + /* Initialize onboard resources */ + + esp32s2_board_initialize(); + + showprogress('C'); + + /* Bring up NuttX */ + + nx_start(); + for (; ; ); /* Should not return */ +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_start.h b/arch/xtensa/src/esp32s2/esp32s2_start.h new file mode 100644 index 0000000000..42628243da --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_start.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_start.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_START_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_START_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_board_initialize + * + * Description: + * Board-specific logic is initialized by calling this function. This + * entry point is called early in the initialization -- after all memory + * has been configured but before any devices have been initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_board_initialize(void); + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_START_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_systemreset.c b/arch/xtensa/src/esp32s2/esp32s2_systemreset.c new file mode 100644 index 0000000000..9b26e597d7 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_systemreset.c @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_systemreset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "xtensa.h" +#include "hardware/esp32s2_rtccntl.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_systemreset + * + * Description: + * Internal reset logic. + * + ****************************************************************************/ + +void up_systemreset(void) +{ + putreg32(RTC_CNTL_SW_SYS_RST, RTC_CNTL_OPTIONS0_REG); + + /* Wait for the reset */ + + for (; ; ); +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_timerisr.c b/arch/xtensa/src/esp32s2/esp32s2_timerisr.c new file mode 100644 index 0000000000..fd61e42595 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_timerisr.c @@ -0,0 +1,185 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_timerisr.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "clock/clock.h" +#include "xtensa_timer.h" +#include "xtensa.h" + +/**************************************************************************** + * Private data + ****************************************************************************/ + +static uint32_t g_tick_divisor; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: xtensa_getcount, xtensa_getcompare, and xtensa_setcompare + * + * Description: + * Lower level operations on Xtensa special registers. + * + ****************************************************************************/ + +/* Return the current value of the cycle count register */ + +static inline uint32_t xtensa_getcount(void) +{ + uint32_t count; + + __asm__ __volatile__ + ( + "rsr %0, CCOUNT" : "=r"(count) + ); + + return count; +} + +/* Return the old value of the compare register */ + +static inline uint32_t xtensa_getcompare(void) +{ + uint32_t compare; + + __asm__ __volatile__ + ( + "rsr %0, %1" : "=r"(compare) : "I"(XT_CCOMPARE) + ); + + return compare; +} + +/* Set the value of the compare register */ + +static inline void xtensa_setcompare(uint32_t compare) +{ + __asm__ __volatile__ + ( + "wsr %0, %1" : : "r"(compare), "I"(XT_CCOMPARE) + ); +} + +/**************************************************************************** + * Function: esp32s2_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + * Xtensa timers work by comparing a cycle counter with a preset value. + * Once the match occurs an interrupt is generated, and the handler has to + * set a new cycle count into the comparator. To avoid clock drift due to + * interrupt latency, the new cycle count is computed from the old, not the + * time the interrupt was serviced. However if a timer interrupt is ever + * serviced more than one tick late, it is necessary to process multiple + * ticks until the new cycle count is in the future, otherwise the next + * timer interrupt would not occur until after the cycle counter had + * wrapped (2^32 cycles later). + * + ****************************************************************************/ + +static int esp32s2_timerisr(int irq, uint32_t *regs, FAR void *arg) +{ + uint32_t divisor; + uint32_t compare; + uint32_t diff; + + divisor = g_tick_divisor; + do + { + /* Increment the compare register for the next tick */ + + compare = xtensa_getcompare(); + xtensa_setcompare(compare + divisor); + + /* Process one timer tick */ + + nxsched_process_timer(); + + /* Check if we are falling behind and need to process multiple timer + * interrupts. + */ + + diff = xtensa_getcount() - compare; + } + while (diff >= divisor); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t divisor; + uint32_t count; + + /* Configured the timer0 as the system timer. + * + * divisor = BOARD_CLOCK_FREQUENCY / ticks_per_sec + */ + + divisor = BOARD_CLOCK_FREQUENCY / CLOCKS_PER_SEC; + g_tick_divisor = divisor; + + /* Set up periodic timer */ + + count = xtensa_getcount(); + xtensa_setcompare(count + divisor); + + /* NOTE: Timer 0 is an internal interrupt source so we do not need to + * attach any peripheral ID to the dedicated CPU interrupt. + */ + + /* Attach the timer interrupt */ + + irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32s2_timerisr, NULL); + + /* Enable the timer 0 CPU interrupt. */ + + up_enable_irq(ESP32S2_CPUINT_TIMER0); +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_user.c b/arch/xtensa/src/esp32s2/esp32s2_user.c new file mode 100644 index 0000000000..338a4efc26 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_user.c @@ -0,0 +1,395 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_user.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include +#include + +#include "xtensa.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef CONFIG_ARCH_USE_MODULE_TEXT +extern uint32_t _smodtext; +extern uint32_t _emodtext; +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_ARCH_USE_MODULE_TEXT +#ifdef CONFIG_ENDIAN_BIG +#error not implemented +#endif +#ifndef CONFIG_BUILD_FLAT +#error permission check not implemented +#endif + +/**************************************************************************** + * Name: load_uint8 + * + * Description: + * Fetch a byte using 32-bit aligned access. + * + ****************************************************************************/ + +static uint8_t load_uint8(const uint8_t *p) +{ + const uint32_t *aligned; + uint32_t value; + unsigned int offset; + + aligned = (const uint32_t *)(((uintptr_t)p) & ~3); + value = l32i(aligned); + offset = ((uintptr_t)p) & 3; + switch (offset) + { + case 0: + return value & 0xff; + case 1: + return (value >> 8) & 0xff; + case 2: + return (value >> 16) & 0xff; + case 3: + return (value >> 24) & 0xff; + } + + /* not reached */ + + PANIC(); +} + +/**************************************************************************** + * Name: store_uint8 + * + * Description: + * Store a byte using 32-bit aligned access. + * + ****************************************************************************/ + +static void store_uint8(uint8_t *p, uint8_t v) +{ + uint32_t *aligned; + uint32_t value; + unsigned int offset; + + aligned = (uint32_t *)(((uintptr_t)p) & ~3); + value = l32i(aligned); + offset = ((uintptr_t)p) & 3; + switch (offset) + { + case 0: + value = (value & 0xffffff00) | v; + break; + case 1: + value = (value & 0xffff00ff) | (v << 8); + break; + case 2: + value = (value & 0xff00ffff) | (v << 16); + break; + case 3: + value = (value & 0x00ffffff) | (v << 24); + break; + } + + s32i(aligned, value); +} + +/**************************************************************************** + * Name: decode_s8i + * + * Description: + * Decode S8I instruction using 32-bit aligned access. + * Return non-zero on successful decoding. + * + ****************************************************************************/ + +static int decode_s8i(const uint8_t *p, uint8_t *imm8, uint8_t *s, + uint8_t *t) +{ + /* 23 16 15 12 11 8 7 4 3 0 + * | imm8 |0 1 0 0| s | t |0 0 1 0| + */ + + uint8_t b0 = load_uint8(p); + uint8_t b1 = load_uint8(p + 1); + + if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0x40) + { + *t = b0 >> 4; + *s = b1 & 0xf; + *imm8 = load_uint8(p + 2); + return 1; + } + + return 0; +} + +/**************************************************************************** + * Name: decode_s16i + * + * Description: + * Decode S16I instruction using 32-bit aligned access. + * Return non-zero on successful decoding. + * + ****************************************************************************/ + +static int decode_s16i(const uint8_t *p, uint8_t *imm8, uint8_t *s, + uint8_t *t) +{ + /* 23 16 15 12 11 8 7 4 3 0 + * | imm8 |0 1 0 1| s | t |0 0 1 0| + */ + + uint8_t b0 = load_uint8(p); + uint8_t b1 = load_uint8(p + 1); + + if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0x50) + { + *t = b0 >> 4; + *s = b1 & 0xf; + *imm8 = load_uint8(p + 2); + return 1; + } + + return 0; +} + +/**************************************************************************** + * Name: decode_l8ui + * + * Description: + * Decode L8UI instruction using 32-bit aligned access. + * Return non-zero on successful decoding. + * + ****************************************************************************/ + +static int decode_l8ui(const uint8_t *p, uint8_t *imm8, uint8_t *s, + uint8_t *t) +{ + /* 23 16 15 12 11 8 7 4 3 0 + * | imm8 |0 0 0 0| s | t |0 0 1 0| + */ + + uint8_t b0 = load_uint8(p); + uint8_t b1 = load_uint8(p + 1); + + if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0) + { + *t = b0 >> 4; + *s = b1 & 0xf; + *imm8 = load_uint8(p + 2); + return 1; + } + + return 0; +} + +/**************************************************************************** + * Name: decode_l16ui + * + * Description: + * Decode L16UI instruction using 32-bit aligned access. + * Return non-zero on successful decoding. + * + ****************************************************************************/ + +static int decode_l16ui(const uint8_t *p, uint8_t *imm8, uint8_t *s, + uint8_t *t) +{ + /* 23 16 15 12 11 8 7 4 3 0 + * | imm8 |0 0 0 1| s | t |0 0 1 0| + */ + + uint8_t b0 = load_uint8(p); + uint8_t b1 = load_uint8(p + 1); + + if ((b0 & 0xf) == 2 && (b1 & 0xf0) == 0x10) + { + *t = b0 >> 4; + *s = b1 & 0xf; + *imm8 = load_uint8(p + 2); + return 1; + } + + return 0; +} + +/**************************************************************************** + * Name: advance_pc + * + * Description: + * Advance PC register by the given value. + * + ****************************************************************************/ + +static void advance_pc(uint32_t *regs, int diff) +{ + uint32_t nextpc; + + /* Advance to the next instruction. */ + + nextpc = regs[REG_PC] + diff; +#if XCHAL_HAVE_LOOPS + /* See Xtensa ISA 4.3.2.4 Loopback Semantics */ + + if (regs[REG_LCOUNT] != 0 && nextpc == regs[REG_LEND]) + { + regs[REG_LCOUNT]--; + nextpc = regs[REG_LBEG]; + } + +#endif + regs[REG_PC] = nextpc; +} + +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_user + * + * Description: + * ESP32S2-specific user exception handler. + * + ****************************************************************************/ + +uint32_t *xtensa_user(int exccause, uint32_t *regs) +{ +#ifdef CONFIG_ARCH_USE_MODULE_TEXT + /* Emulate byte access for module text. + * + * ESP32S2 only allows word-aligned accesses to the instruction memory + * regions. A non-aligned access raises a LoadStoreErrorCause exception. + * We catch those exception and emulate byte access here because it's + * necessary in a few places during dynamic code loading: + * + * - memcpy as a part of read(2) when loading code from a file system. + * - relocation needs to inspect and modify text. + * + * (thus binfo() is used below) + */ + + if (exccause == XCHAL_EXCCAUSE_LOAD_STORE_ERROR && + (uintptr_t)&_smodtext <= regs[REG_EXCVADDR] && + (uintptr_t)&_emodtext > regs[REG_EXCVADDR]) + { + uint8_t *pc = (uint8_t *)regs[REG_PC]; + uint8_t imm8; + uint8_t s; + uint8_t t; + + binfo("XCHAL_EXCCAUSE_LOAD_STORE_ERROR at %p, pc=%p\n", + (FAR void *)regs[REG_EXCVADDR], + pc); + + if (decode_s8i(pc, &imm8, &s, &t)) + { + binfo("Emulating S8I imm8=%u, s=%u (%p), t=%u (%p)\n", + (unsigned int)imm8, + (unsigned int)s, + (void *)regs[REG_A0 + s], + (unsigned int)t, + (void *)regs[REG_A0 + t]); + + DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]); + store_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8, + regs[REG_A0 + t]); + advance_pc(regs, 3); + return regs; + } + else if (decode_s16i(pc, &imm8, &s, &t)) + { + binfo("Emulating S16I imm8=%u, s=%u (%p), t=%u (%p)\n", + (unsigned int)imm8, + (unsigned int)s, + (void *)regs[REG_A0 + s], + (unsigned int)t, + (void *)regs[REG_A0 + t]); + + DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]); + store_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8, + regs[REG_A0 + t]); + store_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8 + 1, + regs[REG_A0 + t] >> 8); + advance_pc(regs, 3); + return regs; + } + else if (decode_l8ui(pc, &imm8, &s, &t)) + { + binfo("Emulating L8UI imm8=%u, s=%u (%p), t=%u (%p)\n", + (unsigned int)imm8, + (unsigned int)s, + (void *)regs[REG_A0 + s], + (unsigned int)t, + (void *)regs[REG_A0 + t]); + + DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]); + regs[REG_A0 + t] = load_uint8(((uint8_t *)regs[REG_A0 + s]) + + imm8); + advance_pc(regs, 3); + return regs; + } + else if (decode_l16ui(pc, &imm8, &s, &t)) + { + binfo("Emulating L16UI imm8=%u, s=%u (%p), t=%u (%p)\n", + (unsigned int)imm8, + (unsigned int)s, + (void *)regs[REG_A0 + s], + (unsigned int)t, + (void *)regs[REG_A0 + t]); + + DEBUGASSERT(regs[REG_A0 + s] + imm8 == regs[REG_EXCVADDR]); + uint8_t lo = load_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8); + uint8_t hi = load_uint8(((uint8_t *)regs[REG_A0 + s]) + imm8 + 1); + regs[REG_A0 + t] = (hi << 8) | lo; + advance_pc(regs, 3); + return regs; + } + } + +#endif + /* xtensa_user_panic never returns. */ + + xtensa_user_panic(exccause, regs); + + while (1) + { + } +} diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h new file mode 100644 index 0000000000..68dd21450c --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h @@ -0,0 +1,780 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_aes.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_AES_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_AES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* AES_KEY_0_REG register + * AES key register 0 + */ + +#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0) + +/* AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_0 0xFFFFFFFF +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFF +#define AES_KEY_0_S 0 + +/* AES_KEY_1_REG register + * AES key register 1 + */ + +#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4) + +/* AES_KEY_1 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_1 0xFFFFFFFF +#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S) +#define AES_KEY_1_V 0xFFFFFFFF +#define AES_KEY_1_S 0 + +/* AES_KEY_2_REG register + * AES key register 2 + */ + +#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8) + +/* AES_KEY_2 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_2 0xFFFFFFFF +#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S) +#define AES_KEY_2_V 0xFFFFFFFF +#define AES_KEY_2_S 0 + +/* AES_KEY_3_REG register + * AES key register 3 + */ + +#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc) + +/* AES_KEY_3 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_3 0xFFFFFFFF +#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S) +#define AES_KEY_3_V 0xFFFFFFFF +#define AES_KEY_3_S 0 + +/* AES_KEY_4_REG register + * AES key register 4 + */ + +#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10) + +/* AES_KEY_4 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_4 0xFFFFFFFF +#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S) +#define AES_KEY_4_V 0xFFFFFFFF +#define AES_KEY_4_S 0 + +/* AES_KEY_5_REG register + * AES key register 5 + */ + +#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14) + +/* AES_KEY_5 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_5 0xFFFFFFFF +#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S) +#define AES_KEY_5_V 0xFFFFFFFF +#define AES_KEY_5_S 0 + +/* AES_KEY_6_REG register + * AES key register 6 + */ + +#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18) + +/* AES_KEY_6 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_6 0xFFFFFFFF +#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S) +#define AES_KEY_6_V 0xFFFFFFFF +#define AES_KEY_6_S 0 + +/* AES_KEY_7_REG register + * AES key register 7 + */ + +#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c) + +/* AES_KEY_7 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_7 0xFFFFFFFF +#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S) +#define AES_KEY_7_V 0xFFFFFFFF +#define AES_KEY_7_S 0 + +/* AES_TEXT_IN_0_REG register + * Source data register 0 + */ + +#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20) + +/* AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_0 0xFFFFFFFF +#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) +#define AES_TEXT_IN_0_V 0xFFFFFFFF +#define AES_TEXT_IN_0_S 0 + +/* AES_TEXT_IN_1_REG register + * Source data register 1 + */ + +#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24) + +/* AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_1 0xFFFFFFFF +#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S) +#define AES_TEXT_IN_1_V 0xFFFFFFFF +#define AES_TEXT_IN_1_S 0 + +/* AES_TEXT_IN_2_REG register + * Source data register 2 + */ + +#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28) + +/* AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_2 0xFFFFFFFF +#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S) +#define AES_TEXT_IN_2_V 0xFFFFFFFF +#define AES_TEXT_IN_2_S 0 + +/* AES_TEXT_IN_3_REG register + * Source data register 3 + */ + +#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c) + +/* AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_3 0xFFFFFFFF +#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S) +#define AES_TEXT_IN_3_V 0xFFFFFFFF +#define AES_TEXT_IN_3_S 0 + +/* AES_TEXT_OUT_0_REG register + * Result data register 0 + */ + +#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30) + +/* AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_0 0xFFFFFFFF +#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) +#define AES_TEXT_OUT_0_V 0xFFFFFFFF +#define AES_TEXT_OUT_0_S 0 + +/* AES_TEXT_OUT_1_REG register + * Result data register 1 + */ + +#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34) + +/* AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_1 0xFFFFFFFF +#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S) +#define AES_TEXT_OUT_1_V 0xFFFFFFFF +#define AES_TEXT_OUT_1_S 0 + +/* AES_TEXT_OUT_2_REG register + * Result data register 2 + */ + +#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38) + +/* AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_2 0xFFFFFFFF +#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S) +#define AES_TEXT_OUT_2_V 0xFFFFFFFF +#define AES_TEXT_OUT_2_S 0 + +/* AES_TEXT_OUT_3_REG register + * Result data register 3 + */ + +#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c) + +/* AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_3 0xFFFFFFFF +#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S) +#define AES_TEXT_OUT_3_V 0xFFFFFFFF +#define AES_TEXT_OUT_3_S 0 + +/* AES_MODE_REG register + * AES working mode configuration register + */ + +#define AES_MODE_REG (DR_REG_AES_BASE + 0x40) + +/* AES_MODE : R/W; bitpos: [2:0]; default: 0; + * Defines the operation type of the AES Accelerator operating under the + * Typical AES working mode. + * & + * 0x0(AES_EN_128): AES-EN-128 # + * 0x1(AES_EN_192): AES-EN-192 # + * 0x2(AES_EN_256): AES-EN-256 # + * 0x4(AES_DE_128): AES-DE-128 # + * 0x5(AES_DE_192): AES-DE-192 # + * 0x6(AES_DE_256): AES-DE-256 + * & + */ + +#define AES_MODE 0x00000007 +#define AES_MODE_M (AES_MODE_V << AES_MODE_S) +#define AES_MODE_V 0x00000007 +#define AES_MODE_S 0 + +/* AES_ENDIAN_REG register + * Endian configuration register + */ + +#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44) + +/* AES_ENDIAN : R/W; bitpos: [5:0]; default: 0; + * Defines the endianness of input and output texts. + * & + * [1:0] key endian # + * [3:2] text_in endian or in_stream endian # + * [5:4] text_out endian or out_stream endian # + * & + */ + +#define AES_ENDIAN 0x0000003F +#define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S) +#define AES_ENDIAN_V 0x0000003F +#define AES_ENDIAN_S 0 + +/* AES_TRIGGER_REG register + * Operation start controlling register + */ + +#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48) + +/* AES_TRIGGER : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start AES operation. + */ + +#define AES_TRIGGER (BIT(0)) +#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S) +#define AES_TRIGGER_V 0x00000001 +#define AES_TRIGGER_S 0 + +/* AES_STATE_REG register + * Operation status register + */ + +#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c) + +/* AES_STATE : RO; bitpos: [1:0]; default: 0; + * Stores the working status of the AES Accelerator. For details, see Table + * 3 for Typical AES working mode and Table 9 for DMA AES working mode. + * For typical AES; 0 = idle; 1 = busy. + * For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done. + */ + +#define AES_STATE 0x00000003 +#define AES_STATE_M (AES_STATE_V << AES_STATE_S) +#define AES_STATE_V 0x00000003 +#define AES_STATE_S 0 + +/* AES_IV_0_REG register + * initialization vector + */ + +#define AES_IV_0_REG (DR_REG_AES_BASE + 0x50) + +/* AES_IV_0 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_0 0xFFFFFFFF +#define AES_IV_0_M (AES_IV_0_V << AES_IV_0_S) +#define AES_IV_0_V 0xFFFFFFFF +#define AES_IV_0_S 0 + +/* AES_IV_1_REG register + * initialization vector + */ + +#define AES_IV_1_REG (DR_REG_AES_BASE + 0x54) + +/* AES_IV_1 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_1 0xFFFFFFFF +#define AES_IV_1_M (AES_IV_1_V << AES_IV_1_S) +#define AES_IV_1_V 0xFFFFFFFF +#define AES_IV_1_S 0 + +/* AES_IV_2_REG register + * initialization vector + */ + +#define AES_IV_2_REG (DR_REG_AES_BASE + 0x58) + +/* AES_IV_2 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_2 0xFFFFFFFF +#define AES_IV_2_M (AES_IV_2_V << AES_IV_2_S) +#define AES_IV_2_V 0xFFFFFFFF +#define AES_IV_2_S 0 + +/* AES_IV_3_REG register + * initialization vector + */ + +#define AES_IV_3_REG (DR_REG_AES_BASE + 0x5c) + +/* AES_IV_3 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_3 0xFFFFFFFF +#define AES_IV_3_M (AES_IV_3_V << AES_IV_3_S) +#define AES_IV_3_V 0xFFFFFFFF +#define AES_IV_3_S 0 + +/* AES_H_0_REG register + * GCM hash subkey + */ + +#define AES_H_0_REG (DR_REG_AES_BASE + 0x60) + +/* AES_H_0 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_0 0xFFFFFFFF +#define AES_H_0_M (AES_H_0_V << AES_H_0_S) +#define AES_H_0_V 0xFFFFFFFF +#define AES_H_0_S 0 + +/* AES_H_1_REG register + * GCM hash subkey + */ + +#define AES_H_1_REG (DR_REG_AES_BASE + 0x64) + +/* AES_H_1 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_1 0xFFFFFFFF +#define AES_H_1_M (AES_H_1_V << AES_H_1_S) +#define AES_H_1_V 0xFFFFFFFF +#define AES_H_1_S 0 + +/* AES_H_2_REG register + * GCM hash subkey + */ + +#define AES_H_2_REG (DR_REG_AES_BASE + 0x68) + +/* AES_H_2 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_2 0xFFFFFFFF +#define AES_H_2_M (AES_H_2_V << AES_H_2_S) +#define AES_H_2_V 0xFFFFFFFF +#define AES_H_2_S 0 + +/* AES_H_3_REG register + * GCM hash subkey + */ + +#define AES_H_3_REG (DR_REG_AES_BASE + 0x6c) + +/* AES_H_3 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_3 0xFFFFFFFF +#define AES_H_3_M (AES_H_3_V << AES_H_3_S) +#define AES_H_3_V 0xFFFFFFFF +#define AES_H_3_S 0 + +/* AES_J0_0_REG register + * J0 + */ + +#define AES_J0_0_REG (DR_REG_AES_BASE + 0x70) + +/* AES_J0_0 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_0 0xFFFFFFFF +#define AES_J0_0_M (AES_J0_0_V << AES_J0_0_S) +#define AES_J0_0_V 0xFFFFFFFF +#define AES_J0_0_S 0 + +/* AES_J0_1_REG register + * J0 + */ + +#define AES_J0_1_REG (DR_REG_AES_BASE + 0x74) + +/* AES_J0_1 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_1 0xFFFFFFFF +#define AES_J0_1_M (AES_J0_1_V << AES_J0_1_S) +#define AES_J0_1_V 0xFFFFFFFF +#define AES_J0_1_S 0 + +/* AES_J0_2_REG register + * J0 + */ + +#define AES_J0_2_REG (DR_REG_AES_BASE + 0x78) + +/* AES_J0_2 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_2 0xFFFFFFFF +#define AES_J0_2_M (AES_J0_2_V << AES_J0_2_S) +#define AES_J0_2_V 0xFFFFFFFF +#define AES_J0_2_S 0 + +/* AES_J0_3_REG register + * J0 + */ + +#define AES_J0_3_REG (DR_REG_AES_BASE + 0x7c) + +/* AES_J0_3 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_3 0xFFFFFFFF +#define AES_J0_3_M (AES_J0_3_V << AES_J0_3_S) +#define AES_J0_3_V 0xFFFFFFFF +#define AES_J0_3_S 0 + +/* AES_T0_0_REG register + * T0 + */ + +#define AES_T0_0_REG (DR_REG_AES_BASE + 0x80) + +/* AES_T0_0 : RO; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_0 0xFFFFFFFF +#define AES_T0_0_M (AES_T0_0_V << AES_T0_0_S) +#define AES_T0_0_V 0xFFFFFFFF +#define AES_T0_0_S 0 + +/* AES_T0_1_REG register + * T0 + */ + +#define AES_T0_1_REG (DR_REG_AES_BASE + 0x84) + +/* AES_T0_1 : RO; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_1 0xFFFFFFFF +#define AES_T0_1_M (AES_T0_1_V << AES_T0_1_S) +#define AES_T0_1_V 0xFFFFFFFF +#define AES_T0_1_S 0 + +/* AES_T0_2_REG register + * T0 + */ + +#define AES_T0_2_REG (DR_REG_AES_BASE + 0x88) + +/* AES_T0_2 : RO; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_2 0xFFFFFFFF +#define AES_T0_2_M (AES_T0_2_V << AES_T0_2_S) +#define AES_T0_2_V 0xFFFFFFFF +#define AES_T0_2_S 0 + +/* AES_T0_3_REG register + * T0 + */ + +#define AES_T0_3_REG (DR_REG_AES_BASE + 0x8c) + +/* AES_T0_3 : RO; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_3 0xFFFFFFFF +#define AES_T0_3_M (AES_T0_3_V << AES_T0_3_S) +#define AES_T0_3_V 0xFFFFFFFF +#define AES_T0_3_S 0 + +/* AES_DMA_ENABLE_REG register + * DMA enable register + */ + +#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90) + +/* AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0; + * Defines the working mode of the AES Accelerator. For details, see Table 1. + * 1'h0: typical AES operation + * 1'h1: DMA-AES operation + */ + +#define AES_DMA_ENABLE (BIT(0)) +#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S) +#define AES_DMA_ENABLE_V 0x00000001 +#define AES_DMA_ENABLE_S 0 + +/* AES_BLOCK_MODE_REG register + * Block operation type register + */ + +#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94) + +/* AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0; + * Defines the operation type of the AES Accelerator operating under the + * DMA-AES working mode. For details, see Table 8. + * & + * 3'h0(BLOCK_MODE_ECB): ECB # + * 3'h1(BLOCK_MODE_CBC): CBC # + * 3'h2(BLOCK_MODE_OFB): OFB # + * 3'h3(BLOCK_MODE_CTR): CTR # + * 3'h4(BLOCK_MODE_CFB8): CFB-8 # + * 3'h5(BLOCK_MODE_CFB128): CFB-128 # + * 3'h6(BLOCK_MODE_GCM): GCM + * & + */ + +#define AES_BLOCK_MODE 0x00000007 +#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S) +#define AES_BLOCK_MODE_V 0x00000007 +#define AES_BLOCK_MODE_S 0 + +/* AES_BLOCK_NUM_REG register + * Block number configuration register + */ + +#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) + +/* AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Stores the Block Number of plaintext or cipertext when the AES + * Accelerator operates under the DMA-AES working mode. For details, see + * Section 1.5.4. + */ + +#define AES_BLOCK_NUM 0xFFFFFFFF +#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S) +#define AES_BLOCK_NUM_V 0xFFFFFFFF +#define AES_BLOCK_NUM_S 0 + +/* AES_INC_SEL_REG register + * Standard incrementing function register + */ + +#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c) + +/* AES_INC_SEL : R/W; bitpos: [0]; default: 0; + * Defines the Standard Incrementing Function for CTR block operation. Set + * this bit to 0 or 1 to choose INC 32 or INC 128 . + */ + +#define AES_INC_SEL (BIT(0)) +#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S) +#define AES_INC_SEL_V 0x00000001 +#define AES_INC_SEL_S 0 + +/* AES_AAD_BLOCK_NUM_REG register + * AAD block number configuration register + */ + +#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0) + +/* AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Stores the ADD Block Number for the GCM operation. + */ + +#define AES_AAD_BLOCK_NUM 0xFFFFFFFF +#define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S) +#define AES_AAD_BLOCK_NUM_V 0xFFFFFFFF +#define AES_AAD_BLOCK_NUM_S 0 + +/* AES_REMAINDER_BIT_NUM_REG register + * Remainder bit number of plaintext/ciphertext + */ + +#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4) + +/* AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0; + * Stores the Remainder Bit Number for the GCM operation. + */ + +#define AES_REMAINDER_BIT_NUM 0x0000007F +#define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S) +#define AES_REMAINDER_BIT_NUM_V 0x0000007F +#define AES_REMAINDER_BIT_NUM_S 0 + +/* AES_CONTINUE_REG register + * Operation continue controlling register + */ + +#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8) + +/* AES_CONTINUE : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to continue AES operation. + */ + +#define AES_CONTINUE (BIT(0)) +#define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S) +#define AES_CONTINUE_V 0x00000001 +#define AES_CONTINUE_S 0 + +/* AES_INT_CLR_REG register + * DMA-AES interrupt clear register + */ + +#define AES_INT_CLR_REG (DR_REG_AES_BASE + 0xac) + +/* AES_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to clear AES interrupt. + */ + +#define AES_INT_CLR (BIT(0)) +#define AES_INT_CLR_M (AES_INT_CLR_V << AES_INT_CLR_S) +#define AES_INT_CLR_V 0x00000001 +#define AES_INT_CLR_S 0 + +/* AES_INT_ENA_REG register + * DMA-AES interrupt enable register + */ + +#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0) + +/* AES_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. + */ + +#define AES_INT_ENA (BIT(0)) +#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S) +#define AES_INT_ENA_V 0x00000001 +#define AES_INT_ENA_S 0 + +/* AES_DATE_REG register + * Version control register + */ + +#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4) + +/* AES_DATE : R/W; bitpos: [29:0]; default: 538510612; + * Version control register + */ + +#define AES_DATE 0x3FFFFFFF +#define AES_DATE_M (AES_DATE_V << AES_DATE_S) +#define AES_DATE_V 0x3FFFFFFF +#define AES_DATE_S 0 + +/* AES_DMA_EXIT_REG register + * Operation exit controlling register + */ + +#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8) + +/* AES_DMA_EXIT : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to exit AES operation. This register is only effective + * for DMA-AES operation. + */ + +#define AES_DMA_EXIT (BIT(0)) +#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S) +#define AES_DMA_EXIT_V 0x00000001 +#define AES_DMA_EXIT_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_AES_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h new file mode 100644 index 0000000000..0cc076b5d2 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h @@ -0,0 +1,3282 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EFUSE_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EFUSE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) + +/* EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_0 0xFFFFFFFF +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_0_S 0 + +/* EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) + +/* EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_1 0xFFFFFFFF +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_1_S 0 + +/* EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) + +/* EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_2 0xFFFFFFFF +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_2_S 0 + +/* EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) + +/* EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_3 0xFFFFFFFF +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_3_S 0 + +/* EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) + +/* EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_4 0xFFFFFFFF +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_4_S 0 + +/* EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) + +/* EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_5 0xFFFFFFFF +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_5_S 0 + +/* EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) + +/* EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_6 0xFFFFFFFF +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_6_S 0 + +/* EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) + +/* EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_7 0xFFFFFFFF +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_7_S 0 + +/* EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ + +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) + +/* EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ + +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_0_S 0 + +/* EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ + +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) + +/* EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit RS code to be programmed. + */ + +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_1_S 0 + +/* EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ + +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) + +/* EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit RS code to be programmed. + */ + +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_2_S 0 + +/* EFUSE_RD_WR_DIS_REG register + * Register 0 of BLOCK0. + */ + +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) + +/* EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Disables programming of individual eFuses. + */ + +#define EFUSE_WR_DIS 0xFFFFFFFF +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFF +#define EFUSE_WR_DIS_S 0 + +/* EFUSE_RD_REPEAT_DATA0_REG register + * Register 1 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) + +/* EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0; + * SPI regulator high voltage reference. + */ + +#define EFUSE_VDD_SPI_DREFH 0x00000003 +#define EFUSE_VDD_SPI_DREFH_M (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S) +#define EFUSE_VDD_SPI_DREFH_V 0x00000003 +#define EFUSE_VDD_SPI_DREFH_S 30 + +/* EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0; + * SPI regulator switches current limit mode. + */ + +#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_M (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S) +#define EFUSE_VDD_SPI_MODECURLIM_V 0x00000001 +#define EFUSE_VDD_SPI_MODECURLIM_S 29 + +/* EFUSE_RPT4_RESERVED0 : RO; bitpos: [28:27]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED0 0x00000003 +#define EFUSE_RPT4_RESERVED0_M (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S) +#define EFUSE_RPT4_RESERVED0_V 0x00000003 +#define EFUSE_RPT4_RESERVED0_S 27 + +/* EFUSE_USB_FORCE_NOPERSIST : RO; bitpos: [26]; default: 0; + * If set, forces USB BVALID to 1. + */ + +#define EFUSE_USB_FORCE_NOPERSIST (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_M (EFUSE_USB_FORCE_NOPERSIST_V << EFUSE_USB_FORCE_NOPERSIST_S) +#define EFUSE_USB_FORCE_NOPERSIST_V 0x00000001 +#define EFUSE_USB_FORCE_NOPERSIST_S 26 + +/* EFUSE_EXT_PHY_ENABLE : RO; bitpos: [25]; default: 0; + * Set this bit to enable external USB PHY. + */ + +#define EFUSE_EXT_PHY_ENABLE (BIT(25)) +#define EFUSE_EXT_PHY_ENABLE_M (EFUSE_EXT_PHY_ENABLE_V << EFUSE_EXT_PHY_ENABLE_S) +#define EFUSE_EXT_PHY_ENABLE_V 0x00000001 +#define EFUSE_EXT_PHY_ENABLE_S 25 + +/* EFUSE_USB_EXCHG_PINS : RO; bitpos: [24]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ + +#define EFUSE_USB_EXCHG_PINS (BIT(24)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001 +#define EFUSE_USB_EXCHG_PINS_S 24 + +/* EFUSE_USB_DREFL : RO; bitpos: [23:22]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of + * 80 mV, stored in eFuse. + */ + +#define EFUSE_USB_DREFL 0x00000003 +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003 +#define EFUSE_USB_DREFL_S 22 + +/* EFUSE_USB_DREFH : RO; bitpos: [21:20]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 + * mV, stored in eFuse. + */ + +#define EFUSE_USB_DREFH 0x00000003 +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003 +#define EFUSE_USB_DREFH_S 20 + +/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [19]; default: 0; + * Disables flash encryption when in download boot modes. + */ + +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(19)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 19 + +/* EFUSE_HARD_DIS_JTAG : RO; bitpos: [18]; default: 0; + * Hardware disables JTAG permanently. + */ + +#define EFUSE_HARD_DIS_JTAG (BIT(18)) +#define EFUSE_HARD_DIS_JTAG_M (EFUSE_HARD_DIS_JTAG_V << EFUSE_HARD_DIS_JTAG_S) +#define EFUSE_HARD_DIS_JTAG_V 0x00000001 +#define EFUSE_HARD_DIS_JTAG_S 18 + +/* EFUSE_SOFT_DIS_JTAG : RO; bitpos: [17]; default: 0; + * Software disables JTAG. When software disabled, JTAG can be activated + * temporarily by HMAC peripheral. + */ + +#define EFUSE_SOFT_DIS_JTAG (BIT(17)) +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000001 +#define EFUSE_SOFT_DIS_JTAG_S 17 + +/* EFUSE_DIS_EFUSE_ATE_WR : RO; bitpos: [16]; default: 0; */ + +#define EFUSE_DIS_EFUSE_ATE_WR (BIT(16)) +#define EFUSE_DIS_EFUSE_ATE_WR_M (EFUSE_DIS_EFUSE_ATE_WR_V << EFUSE_DIS_EFUSE_ATE_WR_S) +#define EFUSE_DIS_EFUSE_ATE_WR_V 0x00000001 +#define EFUSE_DIS_EFUSE_ATE_WR_S 16 + +/* EFUSE_DIS_BOOT_REMAP : RO; bitpos: [15]; default: 0; + * Disables capability to Remap RAM to ROM address space. + */ + +#define EFUSE_DIS_BOOT_REMAP (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_M (EFUSE_DIS_BOOT_REMAP_V << EFUSE_DIS_BOOT_REMAP_S) +#define EFUSE_DIS_BOOT_REMAP_V 0x00000001 +#define EFUSE_DIS_BOOT_REMAP_S 15 + +/* EFUSE_DIS_CAN : RO; bitpos: [14]; default: 0; + * Set this bit to disable CAN function. + */ + +#define EFUSE_DIS_CAN (BIT(14)) +#define EFUSE_DIS_CAN_M (EFUSE_DIS_CAN_V << EFUSE_DIS_CAN_S) +#define EFUSE_DIS_CAN_V 0x00000001 +#define EFUSE_DIS_CAN_S 14 + +/* EFUSE_DIS_USB : RO; bitpos: [13]; default: 0; + * Set this bit to disable USB function. + */ + +#define EFUSE_DIS_USB (BIT(13)) +#define EFUSE_DIS_USB_M (EFUSE_DIS_USB_V << EFUSE_DIS_USB_S) +#define EFUSE_DIS_USB_V 0x00000001 +#define EFUSE_DIS_USB_S 13 + +/* EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ + +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001 +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 + +/* EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0; + * Disables Dcache when SoC is in Download mode. + */ + +#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_M (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 + +/* EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; + * Disables Icache when SoC is in Download mode. + */ + +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 + +/* EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0; + * Set this bit to disable Dcache. + */ + +#define EFUSE_DIS_DCACHE (BIT(9)) +#define EFUSE_DIS_DCACHE_M (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S) +#define EFUSE_DIS_DCACHE_V 0x00000001 +#define EFUSE_DIS_DCACHE_S 9 + +/* EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ + +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001 +#define EFUSE_DIS_ICACHE_S 8 + +/* EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0; + * Set this bit to disable boot from RTC RAM. + */ + +#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S) +#define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001 +#define EFUSE_DIS_RTC_RAM_BOOT_S 7 + +/* EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Disables software reading from individual eFuse blocks (BLOCK4-10). + */ + +#define EFUSE_RD_DIS 0x0000007F +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007F +#define EFUSE_RD_DIS_S 0 + +/* EFUSE_RD_REPEAT_DATA1_REG register + * Register 2 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) + +/* EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of KEY1. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_1 0x0000000F +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000F +#define EFUSE_KEY_PURPOSE_1_S 28 + +/* EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of KEY0. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_0 0x0000000F +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000F +#define EFUSE_KEY_PURPOSE_0_S 24 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * If set, revokes use of secure boot key digest 2. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * If set, revokes use of secure boot key digest 1. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * If set, revokes use of secure boot key digest 0. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 + +/* EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Enables encryption and decryption, when an SPI boot mode is set. Feature + * is enabled 1 or 3 bits are set in the eFuse, disabled otherwise. + */ + +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 + +/* EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock + * cycles; 1: 80,000 slow clock cycles; 2: 160,000 slow clock cycles; 3: + * 320,000 slow clock cycles. + */ + +#define EFUSE_WDT_DELAY_SEL 0x00000003 +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003 +#define EFUSE_WDT_DELAY_SEL_S 16 + +/* EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0; + * Prevents SPI regulator from overshoot. + */ + +#define EFUSE_VDD_SPI_DCAP 0x00000003 +#define EFUSE_VDD_SPI_DCAP_M (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S) +#define EFUSE_VDD_SPI_DCAP_V 0x00000003 +#define EFUSE_VDD_SPI_DCAP_S 14 + +/* EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0; + * Adds resistor from LDO output to ground. 0: no resistance; 1: 6 K; 2: 4 + * K; 3: 2 K. + */ + +#define EFUSE_VDD_SPI_INIT 0x00000003 +#define EFUSE_VDD_SPI_INIT_M (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S) +#define EFUSE_VDD_SPI_INIT_V 0x00000003 +#define EFUSE_VDD_SPI_INIT_S 12 + +/* EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0; + * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 + * mA/(8+d). + */ + +#define EFUSE_VDD_SPI_DCURLIM 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_M (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S) +#define EFUSE_VDD_SPI_DCURLIM_V 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_S 9 + +/* EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0; + * Set SPI regulator to 1 to enable output current limit. + */ + +#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_M (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S) +#define EFUSE_VDD_SPI_ENCURLIM_V 0x00000001 +#define EFUSE_VDD_SPI_ENCURLIM_S 8 + +/* EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0; + * Set SPI regulator to 0 to configure init[1:0]=0. + */ + +#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_M (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S) +#define EFUSE_VDD_SPI_EN_INIT_V 0x00000001 +#define EFUSE_VDD_SPI_EN_INIT_S 7 + +/* EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0; + * Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI + * LDO. + */ + +#define EFUSE_VDD_SPI_FORCE (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_M (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S) +#define EFUSE_VDD_SPI_FORCE_V 0x00000001 +#define EFUSE_VDD_SPI_FORCE_S 6 + +/* EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0; + * If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to + * 1.8 V LDO; 1: VDD_SPI connects to VDD_RTC_IO. + */ + +#define EFUSE_VDD_SPI_TIEH (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_M (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S) +#define EFUSE_VDD_SPI_TIEH_V 0x00000001 +#define EFUSE_VDD_SPI_TIEH_S 5 + +/* EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0; + * If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is + * powered on. + */ + +#define EFUSE_VDD_SPI_XPD (BIT(4)) +#define EFUSE_VDD_SPI_XPD_M (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S) +#define EFUSE_VDD_SPI_XPD_V 0x00000001 +#define EFUSE_VDD_SPI_XPD_S 4 + +/* EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0; + * SPI regulator low voltage reference. + */ + +#define EFUSE_VDD_SPI_DREFL 0x00000003 +#define EFUSE_VDD_SPI_DREFL_M (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S) +#define EFUSE_VDD_SPI_DREFL_V 0x00000003 +#define EFUSE_VDD_SPI_DREFL_S 2 + +/* EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0; + * SPI regulator medium voltage reference. + */ + +#define EFUSE_VDD_SPI_DREFM 0x00000003 +#define EFUSE_VDD_SPI_DREFM_M (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S) +#define EFUSE_VDD_SPI_DREFM_V 0x00000003 +#define EFUSE_VDD_SPI_DREFM_S 0 + +/* EFUSE_RD_REPEAT_DATA2_REG register + * Register 3 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) + +/* EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Configures flash startup delay after SoC power-up, in unit of (ms/2). + * When the value is 15, delay is 7.5 ms. + */ + +#define EFUSE_FLASH_TPUW 0x0000000F +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000F +#define EFUSE_FLASH_TPUW_S 28 + +/* EFUSE_RPT4_RESERVED1 : RO; bitpos: [27:22]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED1 0x0000003F +#define EFUSE_RPT4_RESERVED1_M (EFUSE_RPT4_RESERVED1_V << EFUSE_RPT4_RESERVED1_S) +#define EFUSE_RPT4_RESERVED1_V 0x0000003F +#define EFUSE_RPT4_RESERVED1_S 22 + +/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Set this bit to enable aggressive secure boot key revocation mode. + */ + +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001 +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 + +/* EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ + +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001 +#define EFUSE_SECURE_BOOT_EN_S 20 + +/* EFUSE_KEY_PURPOSE_6 : RO; bitpos: [19:16]; default: 0; + * Purpose of KEY6. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_6 0x0000000F +#define EFUSE_KEY_PURPOSE_6_M (EFUSE_KEY_PURPOSE_6_V << EFUSE_KEY_PURPOSE_6_S) +#define EFUSE_KEY_PURPOSE_6_V 0x0000000F +#define EFUSE_KEY_PURPOSE_6_S 16 + +/* EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of KEY5. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_5 0x0000000F +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000F +#define EFUSE_KEY_PURPOSE_5_S 12 + +/* EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of KEY4. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_4 0x0000000F +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000F +#define EFUSE_KEY_PURPOSE_4_S 8 + +/* EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of KEY3. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_3 0x0000000F +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000F +#define EFUSE_KEY_PURPOSE_3_S 4 + +/* EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of KEY2. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_2 0x0000000F +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000F +#define EFUSE_KEY_PURPOSE_2_S 0 + +/* EFUSE_RD_REPEAT_DATA3_REG register + * Register 4 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) + +/* EFUSE_RPT4_RESERVED2 : RO; bitpos: [31:27]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED2 0x0000001F +#define EFUSE_RPT4_RESERVED2_M (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S) +#define EFUSE_RPT4_RESERVED2_V 0x0000001F +#define EFUSE_RPT4_RESERVED2_S 27 + +/* EFUSE_SECURE_VERSION : RO; bitpos: [26:11]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ + +#define EFUSE_SECURE_VERSION 0x0000FFFF +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFF +#define EFUSE_SECURE_VERSION_S 11 + +/* EFUSE_FORCE_SEND_RESUME : RO; bitpos: [10]; default: 0; + * If set, forces ROM code to send an SPI flash resume command during SPI + * boot. + */ + +#define EFUSE_FORCE_SEND_RESUME (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001 +#define EFUSE_FORCE_SEND_RESUME_S 10 + +/* EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0; + * SPI flash type. 0: maximum four data lines, 1: eight data lines. + */ + +#define EFUSE_FLASH_TYPE (BIT(9)) +#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) +#define EFUSE_FLASH_TYPE_V 0x00000001 +#define EFUSE_FLASH_TYPE_S 9 + +/* EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0; + * Set default power supply for GPIO33-GPIO37, set when SPI flash is + * initialized. 0: VDD3P3_CPU; 1: VDD_SPI. + */ + +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S) +#define EFUSE_PIN_POWER_SELECTION_V 0x00000001 +#define EFUSE_PIN_POWER_SELECTION_S 8 + +/* EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Set the default UART boot message output mode. + * & + * 00: Enabled.# + * 01: Enable when GPIO46 is low at reset.# + * 10: Enable when GPIO46 is high at reset.# + * 11: Disabled. + * & + */ + +#define EFUSE_UART_PRINT_CONTROL 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_S 6 + +/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode (read/write flash only). + */ + +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001 +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 + +/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Set this bit to disable use of USB in UART download boot mode. + */ + +#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (EFUSE_DIS_USB_DOWNLOAD_MODE_V << EFUSE_DIS_USB_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x00000001 +#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 + +/* EFUSE_RPT4_RESERVED3 : RO; bitpos: [3]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED3 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_M (EFUSE_RPT4_RESERVED3_V << EFUSE_RPT4_RESERVED3_S) +#define EFUSE_RPT4_RESERVED3_V 0x00000001 +#define EFUSE_RPT4_RESERVED3_S 3 + +/* EFUSE_UART_PRINT_CHANNEL : RO; bitpos: [2]; default: 0; + * Selects the default UART for printing boot messages. 0: UART0; 1: UART1. + */ + +#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_M (EFUSE_UART_PRINT_CHANNEL_V << EFUSE_UART_PRINT_CHANNEL_S) +#define EFUSE_UART_PRINT_CHANNEL_V 0x00000001 +#define EFUSE_UART_PRINT_CHANNEL_S 2 + +/* EFUSE_DIS_LEGACY_SPI_BOOT : RO; bitpos: [1]; default: 0; + * Set this bit to disable Legacy SPI boot mode. + */ + +#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_M (EFUSE_DIS_LEGACY_SPI_BOOT_V << EFUSE_DIS_LEGACY_SPI_BOOT_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x00000001 +#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 + +/* EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Set this bit to disable all download boot modes. + */ + +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MODE_S 0 + +/* EFUSE_RD_REPEAT_DATA4_REG register + * Register 5 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) + +/* EFUSE_RPT4_RESERVED4 : RO; bitpos: [23:0]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED4 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_M (EFUSE_RPT4_RESERVED4_V << EFUSE_RPT4_RESERVED4_S) +#define EFUSE_RPT4_RESERVED4_V 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_0_REG register + * Register 0 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) + +/* EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + +#define EFUSE_MAC_0 0xFFFFFFFF +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFF +#define EFUSE_MAC_0_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_1_REG register + * Register 1 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) + +/* EFUSE_SPI_PAD_CONF_0 : RO; bitpos: [31:16]; default: 0; + * Stores the zeroth part of SPI_PAD_CONF. + */ + +#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF +#define EFUSE_SPI_PAD_CONF_0_M (EFUSE_SPI_PAD_CONF_0_V << EFUSE_SPI_PAD_CONF_0_S) +#define EFUSE_SPI_PAD_CONF_0_V 0x0000FFFF +#define EFUSE_SPI_PAD_CONF_0_S 16 + +/* EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + +#define EFUSE_MAC_1 0x0000FFFF +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFF +#define EFUSE_MAC_1_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_2_REG register + * Register 2 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) + +/* EFUSE_SPI_PAD_CONF_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first part of SPI_PAD_CONF. + */ + +#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF +#define EFUSE_SPI_PAD_CONF_1_M (EFUSE_SPI_PAD_CONF_1_V << EFUSE_SPI_PAD_CONF_1_S) +#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF +#define EFUSE_SPI_PAD_CONF_1_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_3_REG register + * Register 3 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) + +/* EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; + * Stores the zeroth part of the zeroth part of system data. + */ + +#define EFUSE_SYS_DATA_PART0_0 0x00003FFF +#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) +#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFF +#define EFUSE_SYS_DATA_PART0_0_S 18 + +/* EFUSE_SPI_PAD_CONF_2 : RO; bitpos: [17:0]; default: 0; + * Stores the second part of SPI_PAD_CONF. + */ + +#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF +#define EFUSE_SPI_PAD_CONF_2_M (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S) +#define EFUSE_SPI_PAD_CONF_2_V 0x0003FFFF +#define EFUSE_SPI_PAD_CONF_2_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_4_REG register + * Register 4 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) + +/* EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; + * Stores the fist part of the zeroth part of system data. + */ + +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) +#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_1_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_5_REG register + * Register 5 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) + +/* EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second part of the zeroth part of system data. + */ + +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_2_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_0_REG register + * Register 0 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_0_REG (DR_REG_EFUSE_BASE + 0x5c) + +/* EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_0_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_1_REG register + * Register 1 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_1_REG (DR_REG_EFUSE_BASE + 0x60) + +/* EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_1_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_2_REG register + * Register 2 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_2_REG (DR_REG_EFUSE_BASE + 0x64) + +/* EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_2_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_3_REG register + * Register 3 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_3_REG (DR_REG_EFUSE_BASE + 0x68) + +/* EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_3_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_4_REG register + * Register 4 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_4_REG (DR_REG_EFUSE_BASE + 0x6c) + +/* EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_4_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_5_REG register + * Register 5 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_5_REG (DR_REG_EFUSE_BASE + 0x70) + +/* EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_5_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_6_REG register + * Register 6 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_6_REG (DR_REG_EFUSE_BASE + 0x74) + +/* EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_6_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_7_REG register + * Register 7 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_7_REG (DR_REG_EFUSE_BASE + 0x78) + +/* EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_7_S 0 + +/* EFUSE_RD_USR_DATA0_REG register + * Register 0 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) + +/* EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA0 0xFFFFFFFF +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFF +#define EFUSE_USR_DATA0_S 0 + +/* EFUSE_RD_USR_DATA1_REG register + * Register 1 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) + +/* EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA1 0xFFFFFFFF +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFF +#define EFUSE_USR_DATA1_S 0 + +/* EFUSE_RD_USR_DATA2_REG register + * Register 2 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) + +/* EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA2 0xFFFFFFFF +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFF +#define EFUSE_USR_DATA2_S 0 + +/* EFUSE_RD_USR_DATA3_REG register + * Register 3 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) + +/* EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA3 0xFFFFFFFF +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFF +#define EFUSE_USR_DATA3_S 0 + +/* EFUSE_RD_USR_DATA4_REG register + * Register 4 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) + +/* EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA4 0xFFFFFFFF +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFF +#define EFUSE_USR_DATA4_S 0 + +/* EFUSE_RD_USR_DATA5_REG register + * Register 5 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) + +/* EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA5 0xFFFFFFFF +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFF +#define EFUSE_USR_DATA5_S 0 + +/* EFUSE_RD_USR_DATA6_REG register + * Register 6 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) + +/* EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA6 0xFFFFFFFF +#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) +#define EFUSE_USR_DATA6_V 0xFFFFFFFF +#define EFUSE_USR_DATA6_S 0 + +/* EFUSE_RD_USR_DATA7_REG register + * Register 7 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) + +/* EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA7 0xFFFFFFFF +#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) +#define EFUSE_USR_DATA7_V 0xFFFFFFFF +#define EFUSE_USR_DATA7_S 0 + +/* EFUSE_RD_KEY0_DATA0_REG register + * Register 0 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) + +/* EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA0 0xFFFFFFFF +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA0_S 0 + +/* EFUSE_RD_KEY0_DATA1_REG register + * Register 1 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) + +/* EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA1 0xFFFFFFFF +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA1_S 0 + +/* EFUSE_RD_KEY0_DATA2_REG register + * Register 2 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) + +/* EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA2 0xFFFFFFFF +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA2_S 0 + +/* EFUSE_RD_KEY0_DATA3_REG register + * Register 3 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) + +/* EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA3 0xFFFFFFFF +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA3_S 0 + +/* EFUSE_RD_KEY0_DATA4_REG register + * Register 4 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) + +/* EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA4 0xFFFFFFFF +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA4_S 0 + +/* EFUSE_RD_KEY0_DATA5_REG register + * Register 5 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) + +/* EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA5 0xFFFFFFFF +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA5_S 0 + +/* EFUSE_RD_KEY0_DATA6_REG register + * Register 6 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) + +/* EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA6 0xFFFFFFFF +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA6_S 0 + +/* EFUSE_RD_KEY0_DATA7_REG register + * Register 7 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) + +/* EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA7 0xFFFFFFFF +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA7_S 0 + +/* EFUSE_RD_KEY1_DATA0_REG register + * Register 0 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) + +/* EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA0 0xFFFFFFFF +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA0_S 0 + +/* EFUSE_RD_KEY1_DATA1_REG register + * Register 1 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) + +/* EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA1 0xFFFFFFFF +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA1_S 0 + +/* EFUSE_RD_KEY1_DATA2_REG register + * Register 2 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) + +/* EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA2 0xFFFFFFFF +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA2_S 0 + +/* EFUSE_RD_KEY1_DATA3_REG register + * Register 3 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) + +/* EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA3 0xFFFFFFFF +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA3_S 0 + +/* EFUSE_RD_KEY1_DATA4_REG register + * Register 4 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) + +/* EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA4 0xFFFFFFFF +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA4_S 0 + +/* EFUSE_RD_KEY1_DATA5_REG register + * Register 5 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) + +/* EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA5 0xFFFFFFFF +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA5_S 0 + +/* EFUSE_RD_KEY1_DATA6_REG register + * Register 6 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) + +/* EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA6 0xFFFFFFFF +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA6_S 0 + +/* EFUSE_RD_KEY1_DATA7_REG register + * Register 7 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) + +/* EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA7 0xFFFFFFFF +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA7_S 0 + +/* EFUSE_RD_KEY2_DATA0_REG register + * Register 0 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) + +/* EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA0 0xFFFFFFFF +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA0_S 0 + +/* EFUSE_RD_KEY2_DATA1_REG register + * Register 1 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) + +/* EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA1 0xFFFFFFFF +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA1_S 0 + +/* EFUSE_RD_KEY2_DATA2_REG register + * Register 2 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) + +/* EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA2 0xFFFFFFFF +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA2_S 0 + +/* EFUSE_RD_KEY2_DATA3_REG register + * Register 3 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) + +/* EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA3 0xFFFFFFFF +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA3_S 0 + +/* EFUSE_RD_KEY2_DATA4_REG register + * Register 4 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) + +/* EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA4 0xFFFFFFFF +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA4_S 0 + +/* EFUSE_RD_KEY2_DATA5_REG register + * Register 5 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) + +/* EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA5 0xFFFFFFFF +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA5_S 0 + +/* EFUSE_RD_KEY2_DATA6_REG register + * Register 6 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) + +/* EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA6 0xFFFFFFFF +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA6_S 0 + +/* EFUSE_RD_KEY2_DATA7_REG register + * Register 7 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) + +/* EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA7 0xFFFFFFFF +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA7_S 0 + +/* EFUSE_RD_KEY3_DATA0_REG register + * Register 0 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) + +/* EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA0 0xFFFFFFFF +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA0_S 0 + +/* EFUSE_RD_KEY3_DATA1_REG register + * Register 1 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) + +/* EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA1 0xFFFFFFFF +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA1_S 0 + +/* EFUSE_RD_KEY3_DATA2_REG register + * Register 2 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) + +/* EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA2 0xFFFFFFFF +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA2_S 0 + +/* EFUSE_RD_KEY3_DATA3_REG register + * Register 3 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) + +/* EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA3 0xFFFFFFFF +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA3_S 0 + +/* EFUSE_RD_KEY3_DATA4_REG register + * Register 4 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) + +/* EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA4 0xFFFFFFFF +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA4_S 0 + +/* EFUSE_RD_KEY3_DATA5_REG register + * Register 5 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) + +/* EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA5 0xFFFFFFFF +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA5_S 0 + +/* EFUSE_RD_KEY3_DATA6_REG register + * Register 6 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) + +/* EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA6 0xFFFFFFFF +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA6_S 0 + +/* EFUSE_RD_KEY3_DATA7_REG register + * Register 7 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) + +/* EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA7 0xFFFFFFFF +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA7_S 0 + +/* EFUSE_RD_KEY4_DATA0_REG register + * Register 0 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) + +/* EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA0 0xFFFFFFFF +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA0_S 0 + +/* EFUSE_RD_KEY4_DATA1_REG register + * Register 1 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) + +/* EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA1 0xFFFFFFFF +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA1_S 0 + +/* EFUSE_RD_KEY4_DATA2_REG register + * Register 2 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) + +/* EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA2 0xFFFFFFFF +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA2_S 0 + +/* EFUSE_RD_KEY4_DATA3_REG register + * Register 3 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) + +/* EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA3 0xFFFFFFFF +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA3_S 0 + +/* EFUSE_RD_KEY4_DATA4_REG register + * Register 4 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) + +/* EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA4 0xFFFFFFFF +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA4_S 0 + +/* EFUSE_RD_KEY4_DATA5_REG register + * Register 5 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) + +/* EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA5 0xFFFFFFFF +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA5_S 0 + +/* EFUSE_RD_KEY4_DATA6_REG register + * Register 6 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) + +/* EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA6 0xFFFFFFFF +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA6_S 0 + +/* EFUSE_RD_KEY4_DATA7_REG register + * Register 7 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) + +/* EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA7 0xFFFFFFFF +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA7_S 0 + +/* EFUSE_RD_KEY5_DATA0_REG register + * Register 0 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) + +/* EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA0 0xFFFFFFFF +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA0_S 0 + +/* EFUSE_RD_KEY5_DATA1_REG register + * Register 1 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) + +/* EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA1 0xFFFFFFFF +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA1_S 0 + +/* EFUSE_RD_KEY5_DATA2_REG register + * Register 2 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) + +/* EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA2 0xFFFFFFFF +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA2_S 0 + +/* EFUSE_RD_KEY5_DATA3_REG register + * Register 3 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) + +/* EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA3 0xFFFFFFFF +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA3_S 0 + +/* EFUSE_RD_KEY5_DATA4_REG register + * Register 4 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) + +/* EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA4 0xFFFFFFFF +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA4_S 0 + +/* EFUSE_RD_KEY5_DATA5_REG register + * Register 5 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) + +/* EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA5 0xFFFFFFFF +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA5_S 0 + +/* EFUSE_RD_KEY5_DATA6_REG register + * Register 6 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) + +/* EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA6 0xFFFFFFFF +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA6_S 0 + +/* EFUSE_RD_KEY5_DATA7_REG register + * Register 7 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) + +/* EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA7 0xFFFFFFFF +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA7_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_0_REG register + * Register 0 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_0_REG (DR_REG_EFUSE_BASE + 0x15c) + +/* EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_0_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_1_REG register + * Register 1 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_1_REG (DR_REG_EFUSE_BASE + 0x160) + +/* EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_1_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_2_REG register + * Register 2 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_2_REG (DR_REG_EFUSE_BASE + 0x164) + +/* EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_2_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_3_REG register + * Register 3 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_3_REG (DR_REG_EFUSE_BASE + 0x168) + +/* EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_3_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_4_REG register + * Register 4 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_4_REG (DR_REG_EFUSE_BASE + 0x16c) + +/* EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_4_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_5_REG register + * Register 5 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_5_REG (DR_REG_EFUSE_BASE + 0x170) + +/* EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_5_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_6_REG register + * Register 6 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_6_REG (DR_REG_EFUSE_BASE + 0x174) + +/* EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_6_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_7_REG register + * Register 7 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_7_REG (DR_REG_EFUSE_BASE + 0x178) + +/* EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_7_S 0 + +/* EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) + +/* EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DREFH. + */ + +#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFH_ERR_M (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S) +#define EFUSE_VDD_SPI_DREFH_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DREFH_ERR_S 30 + +/* EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_MODECURLIM. + */ + +#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 + +/* EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [28:27]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED0. + */ + +#define EFUSE_RPT4_RESERVED0_ERR 0x00000003 +#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) +#define EFUSE_RPT4_RESERVED0_ERR_V 0x00000003 +#define EFUSE_RPT4_RESERVED0_ERR_S 27 + +/* EFUSE_USB_FORCE_NOPERSIST_ERR : RO; bitpos: [26]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_FORCE_NOPERSIST. + */ + +#define EFUSE_USB_FORCE_NOPERSIST_ERR (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_ERR_M (EFUSE_USB_FORCE_NOPERSIST_ERR_V << EFUSE_USB_FORCE_NOPERSIST_ERR_S) +#define EFUSE_USB_FORCE_NOPERSIST_ERR_V 0x00000001 +#define EFUSE_USB_FORCE_NOPERSIST_ERR_S 26 + +/* EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [25]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_EXT_PHY_ENABLE. + */ + +#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(25)) +#define EFUSE_EXT_PHY_ENABLE_ERR_M (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S) +#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x00000001 +#define EFUSE_EXT_PHY_ENABLE_ERR_S 25 + +/* EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [24]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_EXCHG_PINS. + */ + +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(24)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001 +#define EFUSE_USB_EXCHG_PINS_ERR_S 24 + +/* EFUSE_USB_DREFL_ERR : RO; bitpos: [23:22]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_DREFL. + */ + +#define EFUSE_USB_DREFL_ERR 0x00000003 +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003 +#define EFUSE_USB_DREFL_ERR_S 22 + +/* EFUSE_USB_DREFH_ERR : RO; bitpos: [21:20]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_DREFH. + */ + +#define EFUSE_USB_DREFH_ERR 0x00000003 +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003 +#define EFUSE_USB_DREFH_ERR_S 20 + +/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [19]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ + +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(19)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 19 + +/* EFUSE_HARD_DIS_JTAG_ERR : RO; bitpos: [18]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_HARD_DIS_JTAG. + */ + +#define EFUSE_HARD_DIS_JTAG_ERR (BIT(18)) +#define EFUSE_HARD_DIS_JTAG_ERR_M (EFUSE_HARD_DIS_JTAG_ERR_V << EFUSE_HARD_DIS_JTAG_ERR_S) +#define EFUSE_HARD_DIS_JTAG_ERR_V 0x00000001 +#define EFUSE_HARD_DIS_JTAG_ERR_S 18 + +/* EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [17]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SOFT_DIS_JTAG. + */ + +#define EFUSE_SOFT_DIS_JTAG_ERR (BIT(17)) +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000001 +#define EFUSE_SOFT_DIS_JTAG_ERR_S 17 + +/* EFUSE_DIS_EFUSE_ATE_WR_ERR : RO; bitpos: [16]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_EFUSE_ATE_WR. + */ + +#define EFUSE_DIS_EFUSE_ATE_WR_ERR (BIT(16)) +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_M (EFUSE_DIS_EFUSE_ATE_WR_ERR_V << EFUSE_DIS_EFUSE_ATE_WR_ERR_S) +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_V 0x00000001 +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_S 16 + +/* EFUSE_DIS_BOOT_REMAP_ERR : RO; bitpos: [15]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_BOOT_REMAP. + */ + +#define EFUSE_DIS_BOOT_REMAP_ERR (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_ERR_M (EFUSE_DIS_BOOT_REMAP_ERR_V << EFUSE_DIS_BOOT_REMAP_ERR_S) +#define EFUSE_DIS_BOOT_REMAP_ERR_V 0x00000001 +#define EFUSE_DIS_BOOT_REMAP_ERR_S 15 + +/* EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_CAN. + */ + +#define EFUSE_DIS_CAN_ERR (BIT(14)) +#define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S) +#define EFUSE_DIS_CAN_ERR_V 0x00000001 +#define EFUSE_DIS_CAN_ERR_S 14 + +/* EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_USB. + */ + +#define EFUSE_DIS_USB_ERR (BIT(13)) +#define EFUSE_DIS_USB_ERR_M (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S) +#define EFUSE_DIS_USB_ERR_V 0x00000001 +#define EFUSE_DIS_USB_ERR_S 13 + +/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_FORCE_DOWNLOAD. + */ + +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001 +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 + +/* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_DCACHE. + */ + +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 + +/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_ICACHE. + */ + +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 + +/* EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DCACHE. + */ + +#define EFUSE_DIS_DCACHE_ERR (BIT(9)) +#define EFUSE_DIS_DCACHE_ERR_M (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S) +#define EFUSE_DIS_DCACHE_ERR_V 0x00000001 +#define EFUSE_DIS_DCACHE_ERR_S 9 + +/* EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_ICACHE. + */ + +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001 +#define EFUSE_DIS_ICACHE_ERR_S 8 + +/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_RTC_RAM_BOOT. + */ + +#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001 +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 + +/* EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RD_DIS. + */ + +#define EFUSE_RD_DIS_ERR 0x0000007F +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007F +#define EFUSE_RD_DIS_ERR_S 0 + +/* EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) + +/* EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_1. + */ + +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 + +/* EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_0. + */ + +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_KEY_REVOKE2. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_KEY_REVOKE1. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_KEY_REVOKE0. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 + +/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SPI_BOOT_CRYPT_CNT. + */ + +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 + +/* EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_WDT_DELAY_SEL. + */ + +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003 +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 + +/* EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DCAP. + */ + +#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003 +#define EFUSE_VDD_SPI_DCAP_ERR_M (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S) +#define EFUSE_VDD_SPI_DCAP_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DCAP_ERR_S 14 + +/* EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_INIT. + */ + +#define EFUSE_VDD_SPI_INIT_ERR 0x00000003 +#define EFUSE_VDD_SPI_INIT_ERR_M (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S) +#define EFUSE_VDD_SPI_INIT_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_INIT_ERR_S 12 + +/* EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DCURLIM. + */ + +#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_ERR_M (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S) +#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 + +/* EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_ENCURLIM. + */ + +#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 + +/* EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_EN_INIT. + */ + +#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_ERR_M (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S) +#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 + +/* EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_FORCE. + */ + +#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_ERR_M (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S) +#define EFUSE_VDD_SPI_FORCE_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_FORCE_ERR_S 6 + +/* EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_TIEH. + */ + +#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_ERR_M (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S) +#define EFUSE_VDD_SPI_TIEH_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_TIEH_ERR_S 5 + +/* EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_XPD. + */ + +#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) +#define EFUSE_VDD_SPI_XPD_ERR_M (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S) +#define EFUSE_VDD_SPI_XPD_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_XPD_ERR_S 4 + +/* EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DREFL. + */ + +#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFL_ERR_M (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S) +#define EFUSE_VDD_SPI_DREFL_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DREFL_ERR_S 2 + +/* EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DREFM. + */ + +#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFM_ERR_M (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S) +#define EFUSE_VDD_SPI_DREFM_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DREFM_ERR_S 0 + +/* EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) + +/* EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_FLASH_TPUW. + */ + +#define EFUSE_FLASH_TPUW_ERR 0x0000000F +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000F +#define EFUSE_FLASH_TPUW_ERR_S 28 + +/* EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [27:22]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED1. + */ + +#define EFUSE_RPT4_RESERVED1_ERR 0x0000003F +#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) +#define EFUSE_RPT4_RESERVED1_ERR_V 0x0000003F +#define EFUSE_RPT4_RESERVED1_ERR_S 22 + +/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. + */ + +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 + +/* EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_EN. + */ + +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 + +/* EFUSE_KEY_PURPOSE_6_ERR : RO; bitpos: [19:16]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_6. + */ + +#define EFUSE_KEY_PURPOSE_6_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_6_ERR_M (EFUSE_KEY_PURPOSE_6_ERR_V << EFUSE_KEY_PURPOSE_6_ERR_S) +#define EFUSE_KEY_PURPOSE_6_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_6_ERR_S 16 + +/* EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_5. + */ + +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 + +/* EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_4. + */ + +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 + +/* EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_3. + */ + +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 + +/* EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_2. + */ + +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_2_ERR_S 0 + +/* EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) + +/* EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [31:27]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED2. + */ + +#define EFUSE_RPT4_RESERVED2_ERR 0x0000001F +#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) +#define EFUSE_RPT4_RESERVED2_ERR_V 0x0000001F +#define EFUSE_RPT4_RESERVED2_ERR_S 27 + +/* EFUSE_SECURE_VERSION_ERR : RO; bitpos: [26:11]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_VERSION. + */ + +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFF +#define EFUSE_SECURE_VERSION_ERR_S 11 + +/* EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [10]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_FORCE_SEND_RESUME. + */ + +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001 +#define EFUSE_FORCE_SEND_RESUME_ERR_S 10 + +/* EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_FLASH_TYPE. + */ + +#define EFUSE_FLASH_TYPE_ERR (BIT(9)) +#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) +#define EFUSE_FLASH_TYPE_ERR_V 0x00000001 +#define EFUSE_FLASH_TYPE_ERR_S 9 + +/* EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_PIN_POWER_SELECTION. + */ + +#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S) +#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001 +#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 + +/* EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_UART_PRINT_CONTROL. + */ + +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 + +/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_ENABLE_SECURITY_DOWNLOAD. + */ + +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001 +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 + +/* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_USB_DOWNLOAD_MODE. + */ + +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001 +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 + +/* EFUSE_RPT4_RESERVED3_ERR : RO; bitpos: [3]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED3. + */ + +#define EFUSE_RPT4_RESERVED3_ERR (BIT(3)) +#define EFUSE_RPT4_RESERVED3_ERR_M (EFUSE_RPT4_RESERVED3_ERR_V << EFUSE_RPT4_RESERVED3_ERR_S) +#define EFUSE_RPT4_RESERVED3_ERR_V 0x00000001 +#define EFUSE_RPT4_RESERVED3_ERR_S 3 + +/* EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_UART_PRINT_CHANNEL. + */ + +#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S) +#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001 +#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 + +/* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_LEGACY_SPI_BOOT. + */ + +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001 +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 + +/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_MODE. + */ + +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 + +/* EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) + +/* EFUSE_RPT4_RESERVED4_ERR : RO; bitpos: [23:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED4. + */ + +#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_ERR_M (EFUSE_RPT4_RESERVED4_ERR_V << EFUSE_RPT4_RESERVED4_ERR_S) +#define EFUSE_RPT4_RESERVED4_ERR_V 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_ERR_S 0 + +/* EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ + +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) + +/* EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of KEY4 is reliable; 1: Means that + * programming KEY4 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001 +#define EFUSE_KEY4_FAIL_S 31 + +/* EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes in KEY4. + */ + +#define EFUSE_KEY4_ERR_NUM 0x00000007 +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007 +#define EFUSE_KEY4_ERR_NUM_S 28 + +/* EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of KEY3 is reliable; 1: Means that + * programming KEY3 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001 +#define EFUSE_KEY3_FAIL_S 27 + +/* EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes in KEY3. + */ + +#define EFUSE_KEY3_ERR_NUM 0x00000007 +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007 +#define EFUSE_KEY3_ERR_NUM_S 24 + +/* EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of KEY2 is reliable; 1: Means that + * programming KEY2 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001 +#define EFUSE_KEY2_FAIL_S 23 + +/* EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes in KEY2. + */ + +#define EFUSE_KEY2_ERR_NUM 0x00000007 +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007 +#define EFUSE_KEY2_ERR_NUM_S 20 + +/* EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of KEY1 is reliable; 1: Means that + * programming KEY1 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001 +#define EFUSE_KEY1_FAIL_S 19 + +/* EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes in KEY1. + */ + +#define EFUSE_KEY1_ERR_NUM 0x00000007 +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007 +#define EFUSE_KEY1_ERR_NUM_S 16 + +/* EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of KEY0 is reliable; 1: Means that + * programming KEY0 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001 +#define EFUSE_KEY0_FAIL_S 15 + +/* EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes in KEY0. + */ + +#define EFUSE_KEY0_ERR_NUM 0x00000007 +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007 +#define EFUSE_KEY0_ERR_NUM_S 12 + +/* EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the data of BLOCK3 is reliable; 1: Means + * that programming BLOCK3 data failed and the number of error bytes is over + * 5. + */ + +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001 +#define EFUSE_USR_DATA_FAIL_S 11 + +/* EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes in BLOCK3. + */ + +#define EFUSE_USR_DATA_ERR_NUM 0x00000007 +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007 +#define EFUSE_USR_DATA_ERR_NUM_S 8 + +/* EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK2 is reliable; 1: Means + * that programming BLOCK2 data failed and the number of error bytes is over + * 5. + */ + +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001 +#define EFUSE_SYS_PART1_FAIL_S 7 + +/* EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK2. + */ + +#define EFUSE_SYS_PART1_NUM 0x00000007 +#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) +#define EFUSE_SYS_PART1_NUM_V 0x00000007 +#define EFUSE_SYS_PART1_NUM_S 4 + +/* EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of BLOCK1 is reliable; 1: Means + * that programming BLOCK1 data failed and the number of error bytes is over + * 5. + */ + +#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001 +#define EFUSE_MAC_SPI_8M_FAIL_S 3 + +/* EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in BLOCK1. + */ + +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 +#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007 +#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 + +/* EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ + +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) + +/* EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK10 is reliable; 1: Means + * that programming BLOCK10 data failed and the number of error bytes is + * over 5. + */ + +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001 +#define EFUSE_SYS_PART2_FAIL_S 7 + +/* EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK10. + */ + +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007 +#define EFUSE_SYS_PART2_ERR_NUM_S 4 + +/* EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable; 1: Means that + * programming user data failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001 +#define EFUSE_KEY5_FAIL_S 3 + +/* EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in KEY5. + */ + +#define EFUSE_KEY5_ERR_NUM 0x00000007 +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007 +#define EFUSE_KEY5_ERR_NUM_S 0 + +/* EFUSE_CLK_REG register + * eFuse clock configuration register. + */ + +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) + +/* EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * If set, forces to enable clock signal of eFuse memory. + */ + +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001 +#define EFUSE_CLK_EN_S 16 + +/* EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * If set, forces eFuse SRAM into working mode. + */ + +#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) +#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001 +#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 + +/* EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * If set, forces to activate clock signal of eFuse SRAM. + */ + +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001 +#define EFUSE_MEM_CLK_FORCE_ON_S 1 + +/* EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * If set, forces eFuse SRAM into power-saving mode. + */ + +#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) +#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001 +#define EFUSE_EFUSE_MEM_FORCE_PD_S 0 + +/* EFUSE_CONF_REG register + * eFuse operation mode configuration register. + */ + +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) + +/* EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command; 0x5AA5: Operate read command. + */ + +#define EFUSE_OP_CODE 0x0000FFFF +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFF +#define EFUSE_OP_CODE_S 0 + +/* EFUSE_STATUS_REG register + * eFuse status register. + */ + +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) + +/* EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ + +#define EFUSE_REPEAT_ERR_CNT 0x000000FF +#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) +#define EFUSE_REPEAT_ERR_CNT_V 0x000000FF +#define EFUSE_REPEAT_ERR_CNT_S 10 + +/* EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001 +#define EFUSE_OTP_VDDQ_IS_SW_S 9 + +/* EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001 +#define EFUSE_OTP_PGENB_SW_S 8 + +/* EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001 +#define EFUSE_OTP_CSB_SW_S 7 + +/* EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001 +#define EFUSE_OTP_STROBE_SW_S 6 + +/* EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001 +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 + +/* EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001 +#define EFUSE_OTP_LOAD_SW_S 4 + +/* EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + +#define EFUSE_STATE 0x0000000F +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000F +#define EFUSE_STATE_S 0 + +/* EFUSE_CMD_REG register + * eFuse command register. + */ + +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) + +/* EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds + * to block number 0-10, respectively. + */ + +#define EFUSE_BLK_NUM 0x0000000F +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000F +#define EFUSE_BLK_NUM_S 2 + +/* EFUSE_PGM_CMD : R/W; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001 +#define EFUSE_PGM_CMD_S 1 + +/* EFUSE_READ_CMD : R/W; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001 +#define EFUSE_READ_CMD_S 0 + +/* EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ + +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) + +/* EFUSE_PGM_DONE_INT_RAW : RO; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001 +#define EFUSE_PGM_DONE_INT_RAW_S 1 + +/* EFUSE_READ_DONE_INT_RAW : RO; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001 +#define EFUSE_READ_DONE_INT_RAW_S 0 + +/* EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ + +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) + +/* EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001 +#define EFUSE_PGM_DONE_INT_ST_S 1 + +/* EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001 +#define EFUSE_READ_DONE_INT_ST_S 0 + +/* EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ + +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) + +/* EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001 +#define EFUSE_PGM_DONE_INT_ENA_S 1 + +/* EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001 +#define EFUSE_READ_DONE_INT_ENA_S 0 + +/* EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ + +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) + +/* EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001 +#define EFUSE_PGM_DONE_INT_CLR_S 1 + +/* EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001 +#define EFUSE_READ_DONE_INT_CLR_S 0 + +/* EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ + +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) + +/* EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001 +#define EFUSE_OE_CLR_S 17 + +/* EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + +#define EFUSE_DAC_NUM 0x000000FF +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FF +#define EFUSE_DAC_NUM_S 9 + +/* EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001 +#define EFUSE_DAC_CLK_PAD_SEL_S 8 + +/* EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming + * voltage. + */ + +#define EFUSE_DAC_CLK_DIV 0x000000FF +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FF +#define EFUSE_DAC_CLK_DIV_S 0 + +/* EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ + +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) + +/* EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ + +#define EFUSE_READ_INIT_NUM 0x000000FF +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FF +#define EFUSE_READ_INIT_NUM_S 24 + +/* EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; + * Configures the setup time of read operation. + */ + +#define EFUSE_TSUR_A 0x000000FF +#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) +#define EFUSE_TSUR_A_V 0x000000FF +#define EFUSE_TSUR_A_S 16 + +/* EFUSE_TRD : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse of read operation. + */ + +#define EFUSE_TRD 0x000000FF +#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) +#define EFUSE_TRD_V 0x000000FF +#define EFUSE_TRD_S 8 + +/* EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of read operation. + */ + +#define EFUSE_THR_A 0x000000FF +#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) +#define EFUSE_THR_A_V 0x000000FF +#define EFUSE_THR_A_S 0 + +/* EFUSE_WR_TIM_CONF0_REG register + * Configuration register 0 of eFuse programming timing parameters. + */ + +#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1f0) + +/* EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200; + * Configures the length of pulse during programming 1 to eFuse. + */ + +#define EFUSE_TPGM 0x0000FFFF +#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) +#define EFUSE_TPGM_V 0x0000FFFF +#define EFUSE_TPGM_S 16 + +/* EFUSE_TPGM_INACTIVE : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse during programming 0 to eFuse. + */ + +#define EFUSE_TPGM_INACTIVE 0x000000FF +#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) +#define EFUSE_TPGM_INACTIVE_V 0x000000FF +#define EFUSE_TPGM_INACTIVE_S 8 + +/* EFUSE_THP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of programming operation. + */ + +#define EFUSE_THP_A 0x000000FF +#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) +#define EFUSE_THP_A_V 0x000000FF +#define EFUSE_THP_A_S 0 + +/* EFUSE_WR_TIM_CONF1_REG register + * Configuration register 1 of eFuse programming timing parameters. + */ + +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4) + +/* EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ + +#define EFUSE_PWR_ON_NUM 0x0000FFFF +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFF +#define EFUSE_PWR_ON_NUM_S 8 + +/* EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the setup time of programming operation. + */ + +#define EFUSE_TSUP_A 0x000000FF +#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) +#define EFUSE_TSUP_A_V 0x000000FF +#define EFUSE_TSUP_A_S 0 + +/* EFUSE_WR_TIM_CONF2_REG register + * Configuration register 2 of eFuse programming timing parameters. + */ + +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8) + +/* EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + +#define EFUSE_PWR_OFF_NUM 0x0000FFFF +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFF +#define EFUSE_PWR_OFF_NUM_S 0 + +/* EFUSE_DATE_REG register + * eFuse version register. + */ + +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) + +/* EFUSE_EFUSE_DATE : R/W; bitpos: [31:0]; default: 419959040; + * Stores eFuse version. + */ + +#define EFUSE_EFUSE_DATE 0xFFFFFFFF +#define EFUSE_EFUSE_DATE_M (EFUSE_EFUSE_DATE_V << EFUSE_EFUSE_DATE_S) +#define EFUSE_EFUSE_DATE_V 0xFFFFFFFF +#define EFUSE_EFUSE_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EFUSE_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio.h new file mode 100644 index 0000000000..0c36a00fe1 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio.h @@ -0,0 +1,16494 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define GPIO_PIN_COUNT 53 + +/* GPIO_BT_SELECT_REG register + * GPIO bit select register + */ + +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) + +/* GPIO_BT_SEL : R/W; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define GPIO_BT_SEL 0xFFFFFFFF +#define GPIO_BT_SEL_M (GPIO_BT_SEL_V << GPIO_BT_SEL_S) +#define GPIO_BT_SEL_V 0xFFFFFFFF +#define GPIO_BT_SEL_S 0 + +/* GPIO_OUT_REG register + * GPIO0 ~ 31 output register + */ + +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) + +/* GPIO_OUT_DATA_ORIG : R/W; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 output value in simple GPIO output mode. The values of bit0 ~ + * bit31 correspond to the output value of GPIO0 ~ GPIO31 respectively. + * Bit22 ~ bit25 are invalid. + */ + +#define GPIO_OUT_DATA_ORIG 0xFFFFFFFF +#define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) +#define GPIO_OUT_DATA_ORIG_V 0xFFFFFFFF +#define GPIO_OUT_DATA_ORIG_S 0 + +/* GPIO_OUT_W1TS_REG register + * GPIO0 ~ 31 output bit set register + */ + +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) + +/* GPIO_OUT_W1TS : WO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 output set register. If the value 1 is written to a bit here, + * the corre- sponding bit in GPIO_OUT_REG will be set to 1. Recommended + * operation: use this register to set GPIO_OUT_REG. + */ + +#define GPIO_OUT_W1TS 0xFFFFFFFF +#define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) +#define GPIO_OUT_W1TS_V 0xFFFFFFFF +#define GPIO_OUT_W1TS_S 0 + +/* GPIO_OUT_W1TC_REG register + * GPIO0 ~ 31 output bit clear register + */ + +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) + +/* GPIO_OUT_W1TC : WO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 output clear register. If the value 1 is written to a bit + * here, the cor- responding bit in GPIO_OUT_REG will be cleared. + * Recommended operation: use this register to clear GPIO_OUT_REG. + */ + +#define GPIO_OUT_W1TC 0xFFFFFFFF +#define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) +#define GPIO_OUT_W1TC_V 0xFFFFFFFF +#define GPIO_OUT_W1TC_S 0 + +/* GPIO_OUT1_REG register + * GPIO32 ~ 53 output register + */ + +#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10) + +/* GPIO_OUT1_DATA_ORIG : R/W; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 output value in simple GPIO output mode. The values of bit0 ~ + * bit13 correspond to GPIO32 ~ GPIO45. Bit14 ~ bit21 are invalid. + */ + +#define GPIO_OUT1_DATA_ORIG 0x003FFFFF +#define GPIO_OUT1_DATA_ORIG_M (GPIO_OUT1_DATA_ORIG_V << GPIO_OUT1_DATA_ORIG_S) +#define GPIO_OUT1_DATA_ORIG_V 0x003FFFFF +#define GPIO_OUT1_DATA_ORIG_S 0 + +/* GPIO_OUT1_W1TS_REG register + * GPIO32 ~ 53 output bit set register + */ + +#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14) + +/* GPIO_OUT1_W1TS : WO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 output value set register. If the value 1 is written to a bit + * here, the corresponding bit in GPIO_OUT1_REG will be set to 1. + * Recommended operation: use this register to set GPIO_OUT1_REG. + */ + +#define GPIO_OUT1_W1TS 0x003FFFFF +#define GPIO_OUT1_W1TS_M (GPIO_OUT1_W1TS_V << GPIO_OUT1_W1TS_S) +#define GPIO_OUT1_W1TS_V 0x003FFFFF +#define GPIO_OUT1_W1TS_S 0 + +/* GPIO_OUT1_W1TC_REG register + * GPIO32 ~ 53 output bit clear register + */ + +#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18) + +/* GPIO_OUT1_W1TC : WO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 output value clear register. If the value 1 is written to a + * bit here, the corresponding bit in GPIO_OUT1_REG will be cleared. + * Recommended operation: use this register to clear GPIO_OUT1_REG. + */ + +#define GPIO_OUT1_W1TC 0x003FFFFF +#define GPIO_OUT1_W1TC_M (GPIO_OUT1_W1TC_V << GPIO_OUT1_W1TC_S) +#define GPIO_OUT1_W1TC_V 0x003FFFFF +#define GPIO_OUT1_W1TC_S 0 + +/* GPIO_SDIO_SELECT_REG register + * GPIO SDIO selection register + */ + +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c) + +/* GPIO_SDIO_SEL : R/W; bitpos: [7:0]; default: 0; + * Reserved + */ + +#define GPIO_SDIO_SEL 0x000000FF +#define GPIO_SDIO_SEL_M (GPIO_SDIO_SEL_V << GPIO_SDIO_SEL_S) +#define GPIO_SDIO_SEL_V 0x000000FF +#define GPIO_SDIO_SEL_S 0 + +/* GPIO_ENABLE_REG register + * GPIO0 ~ 31 output enable register + */ + +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) + +/* GPIO_ENABLE_DATA : R/W; bitpos: [31:0]; default: 0; + * GPIO0~31 output enable register. + */ + +#define GPIO_ENABLE_DATA 0xFFFFFFFF +#define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) +#define GPIO_ENABLE_DATA_V 0xFFFFFFFF +#define GPIO_ENABLE_DATA_S 0 + +/* GPIO_ENABLE_W1TS_REG register + * GPIO0 ~ 31 output enable bit set register + */ + +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) + +/* GPIO_ENABLE_W1TS : WO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 output enable set register. If the value 1 is written to a bit + * here, the corresponding bit in GPIO_ENABLE_REG will be set to 1. + * Recommended operation: use this register to set GPIO_ENABLE_REG. + */ + +#define GPIO_ENABLE_W1TS 0xFFFFFFFF +#define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) +#define GPIO_ENABLE_W1TS_V 0xFFFFFFFF +#define GPIO_ENABLE_W1TS_S 0 + +/* GPIO_ENABLE_W1TC_REG register + * GPIO0 ~ 31 output enable bit clear register + */ + +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) + +/* GPIO_ENABLE_W1TC : WO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 output enable clear register. If the value 1 is written to a + * bit here, the corresponding bit in GPIO_ENABLE_REG will be cleared. + * Recommended operation: use this register to clear GPIO_ENABLE_REG. + */ + +#define GPIO_ENABLE_W1TC 0xFFFFFFFF +#define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) +#define GPIO_ENABLE_W1TC_V 0xFFFFFFFF +#define GPIO_ENABLE_W1TC_S 0 + +/* GPIO_ENABLE1_REG register + * GPIO32 ~ 53 output enable register + */ + +#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x2c) + +/* GPIO_ENABLE1_DATA : R/W; bitpos: [21:0]; default: 0; + * GPIO32~53 output enable register. + */ + +#define GPIO_ENABLE1_DATA 0x003FFFFF +#define GPIO_ENABLE1_DATA_M (GPIO_ENABLE1_DATA_V << GPIO_ENABLE1_DATA_S) +#define GPIO_ENABLE1_DATA_V 0x003FFFFF +#define GPIO_ENABLE1_DATA_S 0 + +/* GPIO_ENABLE1_W1TS_REG register + * GPIO32 ~ 53 output enable bit set register + */ + +#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x30) + +/* GPIO_ENABLE1_W1TS : WO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 output enable set register. If the value 1 is written to a + * bit here, the corresponding bit in GPIO_ENABLE1_REG will be set to 1. + * Recommended operation: use this register to set GPIO_ENABLE1_REG. + */ + +#define GPIO_ENABLE1_W1TS 0x003FFFFF +#define GPIO_ENABLE1_W1TS_M (GPIO_ENABLE1_W1TS_V << GPIO_ENABLE1_W1TS_S) +#define GPIO_ENABLE1_W1TS_V 0x003FFFFF +#define GPIO_ENABLE1_W1TS_S 0 + +/* GPIO_ENABLE1_W1TC_REG register + * GPIO32 ~ 53 output enable bit clear register + */ + +#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x34) + +/* GPIO_ENABLE1_W1TC : WO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 output enable clear register. If the value 1 is written to a + * bit here, the corresponding bit in GPIO_ENABLE1_REG will be cleared. + * Recommended operation: use this register to clear GPIO_ENABLE1_REG. + */ + +#define GPIO_ENABLE1_W1TC 0x003FFFFF +#define GPIO_ENABLE1_W1TC_M (GPIO_ENABLE1_W1TC_V << GPIO_ENABLE1_W1TC_S) +#define GPIO_ENABLE1_W1TC_V 0x003FFFFF +#define GPIO_ENABLE1_W1TC_S 0 + +/* GPIO_STRAP_REG register + * Bootstrap pin value register + */ + +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038) + +/* GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; + * GPIO strapping values: bit4 ~ bit2 correspond to stripping pins GPIO45, + * GPIO0, and GPIO46 respectively. + */ + +#define GPIO_STRAPPING 0x0000FFFF +#define GPIO_STRAPPING_M (GPIO_STRAPPING_V << GPIO_STRAPPING_S) +#define GPIO_STRAPPING_V 0x0000FFFF +#define GPIO_STRAPPING_S 0 + +/* GPIO_IN_REG register + * GPIO0 ~ 31 input register + */ + +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c) + +/* GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 input value. Each bit represents a pad input value, 1 for high + * level and 0 for low level. + */ + +#define GPIO_IN_DATA_NEXT 0xFFFFFFFF +#define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) +#define GPIO_IN_DATA_NEXT_V 0xFFFFFFFF +#define GPIO_IN_DATA_NEXT_S 0 + +/* GPIO_IN1_REG register + * GPIO32 ~ 53 input register + */ + +#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x40) + +/* GPIO_IN_DATA1_NEXT : RO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 input value. Each bit represents a pad input value. + */ + +#define GPIO_IN_DATA1_NEXT 0x003FFFFF +#define GPIO_IN_DATA1_NEXT_M (GPIO_IN_DATA1_NEXT_V << GPIO_IN_DATA1_NEXT_S) +#define GPIO_IN_DATA1_NEXT_V 0x003FFFFF +#define GPIO_IN_DATA1_NEXT_S 0 + +/* GPIO_STATUS_REG register + * GPIO0 ~ 31 interrupt status register + */ + +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) + +/* GPIO_STATUS_INTERRUPT : R/W; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 interrupt status register. + */ + +#define GPIO_STATUS_INTERRUPT 0xFFFFFFFF +#define GPIO_STATUS_INTERRUPT_M (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S) +#define GPIO_STATUS_INTERRUPT_V 0xFFFFFFFF +#define GPIO_STATUS_INTERRUPT_S 0 + +/* GPIO_STATUS_W1TS_REG register + * GPIO0 ~ 31 interrupt status bit set register + */ + +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) + +/* GPIO_STATUS_W1TS : WO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 interrupt status set register. If the value 1 is written to a + * bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be set to + * 1. Recommended operation: use this register to set GPIO_STATUS_INTERRUPT. + */ + +#define GPIO_STATUS_W1TS 0xFFFFFFFF +#define GPIO_STATUS_W1TS_M (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S) +#define GPIO_STATUS_W1TS_V 0xFFFFFFFF +#define GPIO_STATUS_W1TS_S 0 + +/* GPIO_STATUS_W1TC_REG register + * GPIO0 ~ 31 interrupt status bit clear register + */ + +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c) + +/* GPIO_STATUS_W1TC : WO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 interrupt status clear register. If the value 1 is written to + * a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be + * cleared. Recommended operation: use this register to clear + * GPIO_STATUS_INTERRUPT. + */ + +#define GPIO_STATUS_W1TC 0xFFFFFFFF +#define GPIO_STATUS_W1TC_M (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S) +#define GPIO_STATUS_W1TC_V 0xFFFFFFFF +#define GPIO_STATUS_W1TC_S 0 + +/* GPIO_STATUS1_REG register + * GPIO32 ~ 53 interrupt status register + */ + +#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x50) + +/* GPIO_STATUS1_INTERRUPT : R/W; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 interrupt status register. + */ + +#define GPIO_STATUS1_INTERRUPT 0x003FFFFF +#define GPIO_STATUS1_INTERRUPT_M (GPIO_STATUS1_INTERRUPT_V << GPIO_STATUS1_INTERRUPT_S) +#define GPIO_STATUS1_INTERRUPT_V 0x003FFFFF +#define GPIO_STATUS1_INTERRUPT_S 0 + +/* GPIO_STATUS1_W1TS_REG register + * GPIO32 ~ 53 interrupt status bit set register + */ + +#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x54) + +/* GPIO_STATUS1_W1TS : WO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 interrupt status set register. If the value 1 is written to a + * bit here, the corresponding bit in GPIO_STATUS1_REG will be set to 1. + * Recommended operation: use this register to set GPIO_STATUS1_REG. + */ + +#define GPIO_STATUS1_W1TS 0x003FFFFF +#define GPIO_STATUS1_W1TS_M (GPIO_STATUS1_W1TS_V << GPIO_STATUS1_W1TS_S) +#define GPIO_STATUS1_W1TS_V 0x003FFFFF +#define GPIO_STATUS1_W1TS_S 0 + +/* GPIO_STATUS1_W1TC_REG register + * GPIO32 ~ 53 interrupt status bit clear register + */ + +#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x58) + +/* GPIO_STATUS1_W1TC : WO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 interrupt status clear register. If the value 1 is written to + * a bit here, the corresponding bit in GPIO_STATUS1_REG will be cleared. + * Recommended operation: use this register to clear GPIO_STATUS1_REG. + */ + +#define GPIO_STATUS1_W1TC 0x003FFFFF +#define GPIO_STATUS1_W1TC_M (GPIO_STATUS1_W1TC_V << GPIO_STATUS1_W1TC_S) +#define GPIO_STATUS1_W1TC_V 0x003FFFFF +#define GPIO_STATUS1_W1TC_S 0 + +/* GPIO_PCPU_INT_REG register + * GPIO0 ~ 31 PRO_CPU interrupt status register + */ + +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c) + +/* GPIO_PROCPU_INT : RO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 PRO_CPU interrupt status. This interrupt status is + * corresponding to the bit in GPIO_STATUS_REG when assert (high) enable + * signal (bit13 of GPIO_PINn_REG). + */ + +#define GPIO_PROCPU_INT 0xFFFFFFFF +#define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) +#define GPIO_PROCPU_INT_V 0xFFFFFFFF +#define GPIO_PROCPU_INT_S 0 + +/* GPIO_PCPU_NMI_INT_REG register + * GPIO0 ~ 31 PRO_CPU non-maskable interrupt status register + */ + +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) + +/* GPIO_PROCPU_NMI_INT : RO; bitpos: [31:0]; default: 0; + * GPIO0 ~ 31 PRO_CPU non-maskable interrupt status. This interrupt sta- tus + * is corresponding to the bit in GPIO_STATUS_REG when assert (high) enable + * signal (bit 14 of GPIO_PINn_REG). + */ + +#define GPIO_PROCPU_NMI_INT 0xFFFFFFFF +#define GPIO_PROCPU_NMI_INT_M (GPIO_PROCPU_NMI_INT_V << GPIO_PROCPU_NMI_INT_S) +#define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFF +#define GPIO_PROCPU_NMI_INT_S 0 + +/* GPIO_CPUSDIO_INT_REG register + * GPIO0 ~ 31 CPU SDIO interrupt status register + */ + +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) + +/* GPIO_SDIO_INT : RO; bitpos: [31:0]; default: 0; + * GPIO0~31 CPU SDIO interrupt status. + */ + +#define GPIO_SDIO_INT 0xFFFFFFFF +#define GPIO_SDIO_INT_M (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S) +#define GPIO_SDIO_INT_V 0xFFFFFFFF +#define GPIO_SDIO_INT_S 0 + +/* GPIO_PCPU_INT1_REG register + * GPIO32 ~ 53 PRO_CPU interrupt status register + */ + +#define GPIO_PCPU_INT1_REG (DR_REG_GPIO_BASE + 0x68) + +/* GPIO_PROCPU1_INT : RO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 PRO_CPU interrupt status. This interrupt status is + * corresponding to the bit in GPIO_STATUS1_REG when assert (high) enable + * signal (bit 13 of GPIO_PINn_REG). + */ + +#define GPIO_PROCPU1_INT 0x003FFFFF +#define GPIO_PROCPU1_INT_M (GPIO_PROCPU1_INT_V << GPIO_PROCPU1_INT_S) +#define GPIO_PROCPU1_INT_V 0x003FFFFF +#define GPIO_PROCPU1_INT_S 0 + +/* GPIO_PCPU_NMI_INT1_REG register + * GPIO32 ~ 53 PRO_CPU non-maskable interrupt status register + */ + +#define GPIO_PCPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x6c) + +/* GPIO_PROCPU_NMI1_INT : RO; bitpos: [21:0]; default: 0; + * GPIO32 ~ 53 PRO_CPU non-maskable interrupt status. This interrupt status + * is corresponding to bit in GPIO_STATUS1_REG when assert (high) enable + * signal (bit 14 of GPIO_PINn_REG). + */ + +#define GPIO_PROCPU_NMI1_INT 0x003FFFFF +#define GPIO_PROCPU_NMI1_INT_M (GPIO_PROCPU_NMI1_INT_V << GPIO_PROCPU_NMI1_INT_S) +#define GPIO_PROCPU_NMI1_INT_V 0x003FFFFF +#define GPIO_PROCPU_NMI1_INT_S 0 + +/* GPIO_CPUSDIO_INT1_REG register + * GPIO32 ~ 53 CPU SDIO interrupt status register + */ + +#define GPIO_CPUSDIO_INT1_REG (DR_REG_GPIO_BASE + 0x70) + +/* GPIO_SDIO1_INT : RO; bitpos: [21:0]; default: 0; + * GPIO32~53 CPU SDIO interrupt status. + */ + +#define GPIO_SDIO1_INT 0x003FFFFF +#define GPIO_SDIO1_INT_M (GPIO_SDIO1_INT_V << GPIO_SDIO1_INT_S) +#define GPIO_SDIO1_INT_V 0x003FFFFF +#define GPIO_SDIO1_INT_S 0 + +/* GPIO_PIN0_REG register + * Configuration for GPIO pin 0 + */ + +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) +#define GPIO_REG(io_num) (GPIO_PIN0_REG + (io_num)*0x4) +#define GPIO_PIN_PAD_DRIVER_S 2 + +/* GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN0_INT_ENA 0x0000001F +#define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) +#define GPIO_PIN0_INT_ENA_V 0x0000001F +#define GPIO_PIN0_INT_ENA_S 13 + +/* GPIO_PIN0_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN0_CONFIG 0x00000003 +#define GPIO_PIN0_CONFIG_M (GPIO_PIN0_CONFIG_V << GPIO_PIN0_CONFIG_S) +#define GPIO_PIN0_CONFIG_V 0x00000003 +#define GPIO_PIN0_CONFIG_S 11 + +/* GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 + +#define GPIO_PIN_INT_TYPE 0x00000007 +#define GPIO_PIN_INT_TYPE_M (GPIO_PIN_INT_TYPE_V << GPIO_PIN_INT_TYPE_S) +#define GPIO_PIN_INT_TYPE_V 0x00000007 +#define GPIO_PIN_INT_TYPE_S 7 + +#define GPIO_PIN_INT_ENA 0x0000001F +#define GPIO_PIN_INT_ENA_M (GPIO_PIN_INT_ENA_V << GPIO_PIN_INT_ENA_S) +#define GPIO_PIN_INT_ENA_V 0x0000001F +#define GPIO_PIN_INT_ENA_S 13 + +/* GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN0_INT_TYPE 0x00000007 +#define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) +#define GPIO_PIN0_INT_TYPE_V 0x00000007 +#define GPIO_PIN0_INT_TYPE_S 7 + +/* GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN0_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) +#define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN0_SYNC1_BYPASS_S 3 + +/* GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) +#define GPIO_PIN0_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN0_PAD_DRIVER_S 2 + +/* GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN0_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) +#define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN0_SYNC2_BYPASS_S 0 + +/* GPIO_PIN1_REG register + * Configuration for GPIO pin 1 + */ + +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) + +/* GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN1_INT_ENA 0x0000001F +#define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) +#define GPIO_PIN1_INT_ENA_V 0x0000001F +#define GPIO_PIN1_INT_ENA_S 13 + +/* GPIO_PIN1_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN1_CONFIG 0x00000003 +#define GPIO_PIN1_CONFIG_M (GPIO_PIN1_CONFIG_V << GPIO_PIN1_CONFIG_S) +#define GPIO_PIN1_CONFIG_V 0x00000003 +#define GPIO_PIN1_CONFIG_S 11 + +/* GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN1_INT_TYPE 0x00000007 +#define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) +#define GPIO_PIN1_INT_TYPE_V 0x00000007 +#define GPIO_PIN1_INT_TYPE_S 7 + +/* GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN1_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) +#define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN1_SYNC1_BYPASS_S 3 + +/* GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) +#define GPIO_PIN1_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN1_PAD_DRIVER_S 2 + +/* GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN1_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) +#define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN1_SYNC2_BYPASS_S 0 + +/* GPIO_PIN2_REG register + * Configuration for GPIO pin 2 + */ + +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c) + +/* GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN2_INT_ENA 0x0000001F +#define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) +#define GPIO_PIN2_INT_ENA_V 0x0000001F +#define GPIO_PIN2_INT_ENA_S 13 + +/* GPIO_PIN2_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN2_CONFIG 0x00000003 +#define GPIO_PIN2_CONFIG_M (GPIO_PIN2_CONFIG_V << GPIO_PIN2_CONFIG_S) +#define GPIO_PIN2_CONFIG_V 0x00000003 +#define GPIO_PIN2_CONFIG_S 11 + +/* GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN2_INT_TYPE 0x00000007 +#define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) +#define GPIO_PIN2_INT_TYPE_V 0x00000007 +#define GPIO_PIN2_INT_TYPE_S 7 + +/* GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN2_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) +#define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN2_SYNC1_BYPASS_S 3 + +/* GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) +#define GPIO_PIN2_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN2_PAD_DRIVER_S 2 + +/* GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN2_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) +#define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN2_SYNC2_BYPASS_S 0 + +/* GPIO_PIN3_REG register + * Configuration for GPIO pin 3 + */ + +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) + +/* GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN3_INT_ENA 0x0000001F +#define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) +#define GPIO_PIN3_INT_ENA_V 0x0000001F +#define GPIO_PIN3_INT_ENA_S 13 + +/* GPIO_PIN3_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN3_CONFIG 0x00000003 +#define GPIO_PIN3_CONFIG_M (GPIO_PIN3_CONFIG_V << GPIO_PIN3_CONFIG_S) +#define GPIO_PIN3_CONFIG_V 0x00000003 +#define GPIO_PIN3_CONFIG_S 11 + +/* GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN3_INT_TYPE 0x00000007 +#define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) +#define GPIO_PIN3_INT_TYPE_V 0x00000007 +#define GPIO_PIN3_INT_TYPE_S 7 + +/* GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN3_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) +#define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN3_SYNC1_BYPASS_S 3 + +/* GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) +#define GPIO_PIN3_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN3_PAD_DRIVER_S 2 + +/* GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN3_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) +#define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN3_SYNC2_BYPASS_S 0 + +/* GPIO_PIN4_REG register + * Configuration for GPIO pin 4 + */ + +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) + +/* GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN4_INT_ENA 0x0000001F +#define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) +#define GPIO_PIN4_INT_ENA_V 0x0000001F +#define GPIO_PIN4_INT_ENA_S 13 + +/* GPIO_PIN4_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN4_CONFIG 0x00000003 +#define GPIO_PIN4_CONFIG_M (GPIO_PIN4_CONFIG_V << GPIO_PIN4_CONFIG_S) +#define GPIO_PIN4_CONFIG_V 0x00000003 +#define GPIO_PIN4_CONFIG_S 11 + +/* GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN4_INT_TYPE 0x00000007 +#define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) +#define GPIO_PIN4_INT_TYPE_V 0x00000007 +#define GPIO_PIN4_INT_TYPE_S 7 + +/* GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN4_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) +#define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN4_SYNC1_BYPASS_S 3 + +/* GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) +#define GPIO_PIN4_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN4_PAD_DRIVER_S 2 + +/* GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN4_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) +#define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN4_SYNC2_BYPASS_S 0 + +/* GPIO_PIN5_REG register + * Configuration for GPIO pin 5 + */ + +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) + +/* GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN5_INT_ENA 0x0000001F +#define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) +#define GPIO_PIN5_INT_ENA_V 0x0000001F +#define GPIO_PIN5_INT_ENA_S 13 + +/* GPIO_PIN5_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN5_CONFIG 0x00000003 +#define GPIO_PIN5_CONFIG_M (GPIO_PIN5_CONFIG_V << GPIO_PIN5_CONFIG_S) +#define GPIO_PIN5_CONFIG_V 0x00000003 +#define GPIO_PIN5_CONFIG_S 11 + +/* GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN5_INT_TYPE 0x00000007 +#define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) +#define GPIO_PIN5_INT_TYPE_V 0x00000007 +#define GPIO_PIN5_INT_TYPE_S 7 + +/* GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN5_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) +#define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN5_SYNC1_BYPASS_S 3 + +/* GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) +#define GPIO_PIN5_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN5_PAD_DRIVER_S 2 + +/* GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN5_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) +#define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN5_SYNC2_BYPASS_S 0 + +/* GPIO_PIN6_REG register + * Configuration for GPIO pin 6 + */ + +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c) + +/* GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN6_INT_ENA 0x0000001F +#define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) +#define GPIO_PIN6_INT_ENA_V 0x0000001F +#define GPIO_PIN6_INT_ENA_S 13 + +/* GPIO_PIN6_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN6_CONFIG 0x00000003 +#define GPIO_PIN6_CONFIG_M (GPIO_PIN6_CONFIG_V << GPIO_PIN6_CONFIG_S) +#define GPIO_PIN6_CONFIG_V 0x00000003 +#define GPIO_PIN6_CONFIG_S 11 + +/* GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN6_INT_TYPE 0x00000007 +#define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) +#define GPIO_PIN6_INT_TYPE_V 0x00000007 +#define GPIO_PIN6_INT_TYPE_S 7 + +/* GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN6_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) +#define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN6_SYNC1_BYPASS_S 3 + +/* GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) +#define GPIO_PIN6_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN6_PAD_DRIVER_S 2 + +/* GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN6_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) +#define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN6_SYNC2_BYPASS_S 0 + +/* GPIO_PIN7_REG register + * Configuration for GPIO pin 7 + */ + +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) + +/* GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN7_INT_ENA 0x0000001F +#define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) +#define GPIO_PIN7_INT_ENA_V 0x0000001F +#define GPIO_PIN7_INT_ENA_S 13 + +/* GPIO_PIN7_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN7_CONFIG 0x00000003 +#define GPIO_PIN7_CONFIG_M (GPIO_PIN7_CONFIG_V << GPIO_PIN7_CONFIG_S) +#define GPIO_PIN7_CONFIG_V 0x00000003 +#define GPIO_PIN7_CONFIG_S 11 + +/* GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN7_INT_TYPE 0x00000007 +#define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) +#define GPIO_PIN7_INT_TYPE_V 0x00000007 +#define GPIO_PIN7_INT_TYPE_S 7 + +/* GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN7_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) +#define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN7_SYNC1_BYPASS_S 3 + +/* GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) +#define GPIO_PIN7_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN7_PAD_DRIVER_S 2 + +/* GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN7_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) +#define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN7_SYNC2_BYPASS_S 0 + +/* GPIO_PIN8_REG register + * Configuration for GPIO pin 8 + */ + +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) + +/* GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN8_INT_ENA 0x0000001F +#define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) +#define GPIO_PIN8_INT_ENA_V 0x0000001F +#define GPIO_PIN8_INT_ENA_S 13 + +/* GPIO_PIN8_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN8_CONFIG 0x00000003 +#define GPIO_PIN8_CONFIG_M (GPIO_PIN8_CONFIG_V << GPIO_PIN8_CONFIG_S) +#define GPIO_PIN8_CONFIG_V 0x00000003 +#define GPIO_PIN8_CONFIG_S 11 + +/* GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN8_INT_TYPE 0x00000007 +#define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) +#define GPIO_PIN8_INT_TYPE_V 0x00000007 +#define GPIO_PIN8_INT_TYPE_S 7 + +/* GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN8_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) +#define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN8_SYNC1_BYPASS_S 3 + +/* GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) +#define GPIO_PIN8_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN8_PAD_DRIVER_S 2 + +/* GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN8_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) +#define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN8_SYNC2_BYPASS_S 0 + +/* GPIO_PIN9_REG register + * Configuration for GPIO pin 9 + */ + +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) + +/* GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN9_INT_ENA 0x0000001F +#define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) +#define GPIO_PIN9_INT_ENA_V 0x0000001F +#define GPIO_PIN9_INT_ENA_S 13 + +/* GPIO_PIN9_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN9_CONFIG 0x00000003 +#define GPIO_PIN9_CONFIG_M (GPIO_PIN9_CONFIG_V << GPIO_PIN9_CONFIG_S) +#define GPIO_PIN9_CONFIG_V 0x00000003 +#define GPIO_PIN9_CONFIG_S 11 + +/* GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN9_INT_TYPE 0x00000007 +#define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) +#define GPIO_PIN9_INT_TYPE_V 0x00000007 +#define GPIO_PIN9_INT_TYPE_S 7 + +/* GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN9_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) +#define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN9_SYNC1_BYPASS_S 3 + +/* GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) +#define GPIO_PIN9_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN9_PAD_DRIVER_S 2 + +/* GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN9_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) +#define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN9_SYNC2_BYPASS_S 0 + +/* GPIO_PIN10_REG register + * Configuration for GPIO pin 10 + */ + +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c) + +/* GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN10_INT_ENA 0x0000001F +#define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) +#define GPIO_PIN10_INT_ENA_V 0x0000001F +#define GPIO_PIN10_INT_ENA_S 13 + +/* GPIO_PIN10_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN10_CONFIG 0x00000003 +#define GPIO_PIN10_CONFIG_M (GPIO_PIN10_CONFIG_V << GPIO_PIN10_CONFIG_S) +#define GPIO_PIN10_CONFIG_V 0x00000003 +#define GPIO_PIN10_CONFIG_S 11 + +/* GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN10_INT_TYPE 0x00000007 +#define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) +#define GPIO_PIN10_INT_TYPE_V 0x00000007 +#define GPIO_PIN10_INT_TYPE_S 7 + +/* GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN10_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) +#define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN10_SYNC1_BYPASS_S 3 + +/* GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) +#define GPIO_PIN10_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN10_PAD_DRIVER_S 2 + +/* GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN10_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) +#define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN10_SYNC2_BYPASS_S 0 + +/* GPIO_PIN11_REG register + * Configuration for GPIO pin 11 + */ + +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0) + +/* GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN11_INT_ENA 0x0000001F +#define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) +#define GPIO_PIN11_INT_ENA_V 0x0000001F +#define GPIO_PIN11_INT_ENA_S 13 + +/* GPIO_PIN11_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN11_CONFIG 0x00000003 +#define GPIO_PIN11_CONFIG_M (GPIO_PIN11_CONFIG_V << GPIO_PIN11_CONFIG_S) +#define GPIO_PIN11_CONFIG_V 0x00000003 +#define GPIO_PIN11_CONFIG_S 11 + +/* GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN11_INT_TYPE 0x00000007 +#define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) +#define GPIO_PIN11_INT_TYPE_V 0x00000007 +#define GPIO_PIN11_INT_TYPE_S 7 + +/* GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN11_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) +#define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN11_SYNC1_BYPASS_S 3 + +/* GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) +#define GPIO_PIN11_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN11_PAD_DRIVER_S 2 + +/* GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN11_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) +#define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN11_SYNC2_BYPASS_S 0 + +/* GPIO_PIN12_REG register + * Configuration for GPIO pin 12 + */ + +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4) + +/* GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN12_INT_ENA 0x0000001F +#define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) +#define GPIO_PIN12_INT_ENA_V 0x0000001F +#define GPIO_PIN12_INT_ENA_S 13 + +/* GPIO_PIN12_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN12_CONFIG 0x00000003 +#define GPIO_PIN12_CONFIG_M (GPIO_PIN12_CONFIG_V << GPIO_PIN12_CONFIG_S) +#define GPIO_PIN12_CONFIG_V 0x00000003 +#define GPIO_PIN12_CONFIG_S 11 + +/* GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN12_INT_TYPE 0x00000007 +#define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) +#define GPIO_PIN12_INT_TYPE_V 0x00000007 +#define GPIO_PIN12_INT_TYPE_S 7 + +/* GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN12_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) +#define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN12_SYNC1_BYPASS_S 3 + +/* GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) +#define GPIO_PIN12_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN12_PAD_DRIVER_S 2 + +/* GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN12_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) +#define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN12_SYNC2_BYPASS_S 0 + +/* GPIO_PIN13_REG register + * Configuration for GPIO pin 13 + */ + +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8) + +/* GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN13_INT_ENA 0x0000001F +#define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) +#define GPIO_PIN13_INT_ENA_V 0x0000001F +#define GPIO_PIN13_INT_ENA_S 13 + +/* GPIO_PIN13_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN13_CONFIG 0x00000003 +#define GPIO_PIN13_CONFIG_M (GPIO_PIN13_CONFIG_V << GPIO_PIN13_CONFIG_S) +#define GPIO_PIN13_CONFIG_V 0x00000003 +#define GPIO_PIN13_CONFIG_S 11 + +/* GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN13_INT_TYPE 0x00000007 +#define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) +#define GPIO_PIN13_INT_TYPE_V 0x00000007 +#define GPIO_PIN13_INT_TYPE_S 7 + +/* GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN13_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) +#define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN13_SYNC1_BYPASS_S 3 + +/* GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) +#define GPIO_PIN13_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN13_PAD_DRIVER_S 2 + +/* GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN13_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) +#define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN13_SYNC2_BYPASS_S 0 + +/* GPIO_PIN14_REG register + * Configuration for GPIO pin 14 + */ + +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac) + +/* GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN14_INT_ENA 0x0000001F +#define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) +#define GPIO_PIN14_INT_ENA_V 0x0000001F +#define GPIO_PIN14_INT_ENA_S 13 + +/* GPIO_PIN14_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN14_CONFIG 0x00000003 +#define GPIO_PIN14_CONFIG_M (GPIO_PIN14_CONFIG_V << GPIO_PIN14_CONFIG_S) +#define GPIO_PIN14_CONFIG_V 0x00000003 +#define GPIO_PIN14_CONFIG_S 11 + +/* GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN14_INT_TYPE 0x00000007 +#define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) +#define GPIO_PIN14_INT_TYPE_V 0x00000007 +#define GPIO_PIN14_INT_TYPE_S 7 + +/* GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN14_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) +#define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN14_SYNC1_BYPASS_S 3 + +/* GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) +#define GPIO_PIN14_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN14_PAD_DRIVER_S 2 + +/* GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN14_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) +#define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN14_SYNC2_BYPASS_S 0 + +/* GPIO_PIN15_REG register + * Configuration for GPIO pin 15 + */ + +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0) + +/* GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN15_INT_ENA 0x0000001F +#define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) +#define GPIO_PIN15_INT_ENA_V 0x0000001F +#define GPIO_PIN15_INT_ENA_S 13 + +/* GPIO_PIN15_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN15_CONFIG 0x00000003 +#define GPIO_PIN15_CONFIG_M (GPIO_PIN15_CONFIG_V << GPIO_PIN15_CONFIG_S) +#define GPIO_PIN15_CONFIG_V 0x00000003 +#define GPIO_PIN15_CONFIG_S 11 + +/* GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN15_INT_TYPE 0x00000007 +#define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) +#define GPIO_PIN15_INT_TYPE_V 0x00000007 +#define GPIO_PIN15_INT_TYPE_S 7 + +/* GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN15_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) +#define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN15_SYNC1_BYPASS_S 3 + +/* GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) +#define GPIO_PIN15_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN15_PAD_DRIVER_S 2 + +/* GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN15_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) +#define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN15_SYNC2_BYPASS_S 0 + +/* GPIO_PIN16_REG register + * Configuration for GPIO pin 16 + */ + +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4) + +/* GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN16_INT_ENA 0x0000001F +#define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) +#define GPIO_PIN16_INT_ENA_V 0x0000001F +#define GPIO_PIN16_INT_ENA_S 13 + +/* GPIO_PIN16_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN16_CONFIG 0x00000003 +#define GPIO_PIN16_CONFIG_M (GPIO_PIN16_CONFIG_V << GPIO_PIN16_CONFIG_S) +#define GPIO_PIN16_CONFIG_V 0x00000003 +#define GPIO_PIN16_CONFIG_S 11 + +/* GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN16_INT_TYPE 0x00000007 +#define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) +#define GPIO_PIN16_INT_TYPE_V 0x00000007 +#define GPIO_PIN16_INT_TYPE_S 7 + +/* GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN16_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) +#define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN16_SYNC1_BYPASS_S 3 + +/* GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) +#define GPIO_PIN16_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN16_PAD_DRIVER_S 2 + +/* GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN16_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) +#define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN16_SYNC2_BYPASS_S 0 + +/* GPIO_PIN17_REG register + * Configuration for GPIO pin 17 + */ + +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8) + +/* GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN17_INT_ENA 0x0000001F +#define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) +#define GPIO_PIN17_INT_ENA_V 0x0000001F +#define GPIO_PIN17_INT_ENA_S 13 + +/* GPIO_PIN17_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN17_CONFIG 0x00000003 +#define GPIO_PIN17_CONFIG_M (GPIO_PIN17_CONFIG_V << GPIO_PIN17_CONFIG_S) +#define GPIO_PIN17_CONFIG_V 0x00000003 +#define GPIO_PIN17_CONFIG_S 11 + +/* GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN17_INT_TYPE 0x00000007 +#define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) +#define GPIO_PIN17_INT_TYPE_V 0x00000007 +#define GPIO_PIN17_INT_TYPE_S 7 + +/* GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN17_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) +#define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN17_SYNC1_BYPASS_S 3 + +/* GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) +#define GPIO_PIN17_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN17_PAD_DRIVER_S 2 + +/* GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN17_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) +#define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN17_SYNC2_BYPASS_S 0 + +/* GPIO_PIN18_REG register + * Configuration for GPIO pin 18 + */ + +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc) + +/* GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN18_INT_ENA 0x0000001F +#define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) +#define GPIO_PIN18_INT_ENA_V 0x0000001F +#define GPIO_PIN18_INT_ENA_S 13 + +/* GPIO_PIN18_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN18_CONFIG 0x00000003 +#define GPIO_PIN18_CONFIG_M (GPIO_PIN18_CONFIG_V << GPIO_PIN18_CONFIG_S) +#define GPIO_PIN18_CONFIG_V 0x00000003 +#define GPIO_PIN18_CONFIG_S 11 + +/* GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN18_INT_TYPE 0x00000007 +#define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) +#define GPIO_PIN18_INT_TYPE_V 0x00000007 +#define GPIO_PIN18_INT_TYPE_S 7 + +/* GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN18_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) +#define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN18_SYNC1_BYPASS_S 3 + +/* GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) +#define GPIO_PIN18_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN18_PAD_DRIVER_S 2 + +/* GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN18_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) +#define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN18_SYNC2_BYPASS_S 0 + +/* GPIO_PIN19_REG register + * Configuration for GPIO pin 19 + */ + +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0) + +/* GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN19_INT_ENA 0x0000001F +#define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) +#define GPIO_PIN19_INT_ENA_V 0x0000001F +#define GPIO_PIN19_INT_ENA_S 13 + +/* GPIO_PIN19_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN19_CONFIG 0x00000003 +#define GPIO_PIN19_CONFIG_M (GPIO_PIN19_CONFIG_V << GPIO_PIN19_CONFIG_S) +#define GPIO_PIN19_CONFIG_V 0x00000003 +#define GPIO_PIN19_CONFIG_S 11 + +/* GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN19_INT_TYPE 0x00000007 +#define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) +#define GPIO_PIN19_INT_TYPE_V 0x00000007 +#define GPIO_PIN19_INT_TYPE_S 7 + +/* GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN19_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) +#define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN19_SYNC1_BYPASS_S 3 + +/* GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) +#define GPIO_PIN19_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN19_PAD_DRIVER_S 2 + +/* GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN19_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) +#define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN19_SYNC2_BYPASS_S 0 + +/* GPIO_PIN20_REG register + * Configuration for GPIO pin 20 + */ + +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4) + +/* GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN20_INT_ENA 0x0000001F +#define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) +#define GPIO_PIN20_INT_ENA_V 0x0000001F +#define GPIO_PIN20_INT_ENA_S 13 + +/* GPIO_PIN20_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN20_CONFIG 0x00000003 +#define GPIO_PIN20_CONFIG_M (GPIO_PIN20_CONFIG_V << GPIO_PIN20_CONFIG_S) +#define GPIO_PIN20_CONFIG_V 0x00000003 +#define GPIO_PIN20_CONFIG_S 11 + +/* GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN20_INT_TYPE 0x00000007 +#define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) +#define GPIO_PIN20_INT_TYPE_V 0x00000007 +#define GPIO_PIN20_INT_TYPE_S 7 + +/* GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN20_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) +#define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN20_SYNC1_BYPASS_S 3 + +/* GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) +#define GPIO_PIN20_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN20_PAD_DRIVER_S 2 + +/* GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN20_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) +#define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN20_SYNC2_BYPASS_S 0 + +/* GPIO_PIN21_REG register + * Configuration for GPIO pin 21 + */ + +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8) + +/* GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN21_INT_ENA 0x0000001F +#define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) +#define GPIO_PIN21_INT_ENA_V 0x0000001F +#define GPIO_PIN21_INT_ENA_S 13 + +/* GPIO_PIN21_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN21_CONFIG 0x00000003 +#define GPIO_PIN21_CONFIG_M (GPIO_PIN21_CONFIG_V << GPIO_PIN21_CONFIG_S) +#define GPIO_PIN21_CONFIG_V 0x00000003 +#define GPIO_PIN21_CONFIG_S 11 + +/* GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN21_INT_TYPE 0x00000007 +#define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) +#define GPIO_PIN21_INT_TYPE_V 0x00000007 +#define GPIO_PIN21_INT_TYPE_S 7 + +/* GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN21_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) +#define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN21_SYNC1_BYPASS_S 3 + +/* GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) +#define GPIO_PIN21_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN21_PAD_DRIVER_S 2 + +/* GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN21_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) +#define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN21_SYNC2_BYPASS_S 0 + +/* GPIO_PIN22_REG register + * Configuration for GPIO pin 22 + */ + +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc) + +/* GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN22_INT_ENA 0x0000001F +#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) +#define GPIO_PIN22_INT_ENA_V 0x0000001F +#define GPIO_PIN22_INT_ENA_S 13 + +/* GPIO_PIN22_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN22_CONFIG 0x00000003 +#define GPIO_PIN22_CONFIG_M (GPIO_PIN22_CONFIG_V << GPIO_PIN22_CONFIG_S) +#define GPIO_PIN22_CONFIG_V 0x00000003 +#define GPIO_PIN22_CONFIG_S 11 + +/* GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN22_INT_TYPE 0x00000007 +#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) +#define GPIO_PIN22_INT_TYPE_V 0x00000007 +#define GPIO_PIN22_INT_TYPE_S 7 + +/* GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN22_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) +#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN22_SYNC1_BYPASS_S 3 + +/* GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) +#define GPIO_PIN22_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN22_PAD_DRIVER_S 2 + +/* GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN22_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) +#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN22_SYNC2_BYPASS_S 0 + +/* GPIO_PIN23_REG register + * Configuration for GPIO pin 23 + */ + +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0) + +/* GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN23_INT_ENA 0x0000001F +#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) +#define GPIO_PIN23_INT_ENA_V 0x0000001F +#define GPIO_PIN23_INT_ENA_S 13 + +/* GPIO_PIN23_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN23_CONFIG 0x00000003 +#define GPIO_PIN23_CONFIG_M (GPIO_PIN23_CONFIG_V << GPIO_PIN23_CONFIG_S) +#define GPIO_PIN23_CONFIG_V 0x00000003 +#define GPIO_PIN23_CONFIG_S 11 + +/* GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN23_INT_TYPE 0x00000007 +#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) +#define GPIO_PIN23_INT_TYPE_V 0x00000007 +#define GPIO_PIN23_INT_TYPE_S 7 + +/* GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN23_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) +#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN23_SYNC1_BYPASS_S 3 + +/* GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) +#define GPIO_PIN23_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN23_PAD_DRIVER_S 2 + +/* GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN23_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) +#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN23_SYNC2_BYPASS_S 0 + +/* GPIO_PIN24_REG register + * Configuration for GPIO pin 24 + */ + +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4) + +/* GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN24_INT_ENA 0x0000001F +#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) +#define GPIO_PIN24_INT_ENA_V 0x0000001F +#define GPIO_PIN24_INT_ENA_S 13 + +/* GPIO_PIN24_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN24_CONFIG 0x00000003 +#define GPIO_PIN24_CONFIG_M (GPIO_PIN24_CONFIG_V << GPIO_PIN24_CONFIG_S) +#define GPIO_PIN24_CONFIG_V 0x00000003 +#define GPIO_PIN24_CONFIG_S 11 + +/* GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN24_INT_TYPE 0x00000007 +#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) +#define GPIO_PIN24_INT_TYPE_V 0x00000007 +#define GPIO_PIN24_INT_TYPE_S 7 + +/* GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN24_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) +#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN24_SYNC1_BYPASS_S 3 + +/* GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) +#define GPIO_PIN24_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN24_PAD_DRIVER_S 2 + +/* GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN24_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) +#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN24_SYNC2_BYPASS_S 0 + +/* GPIO_PIN25_REG register + * Configuration for GPIO pin 25 + */ + +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8) + +/* GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN25_INT_ENA 0x0000001F +#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) +#define GPIO_PIN25_INT_ENA_V 0x0000001F +#define GPIO_PIN25_INT_ENA_S 13 + +/* GPIO_PIN25_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN25_CONFIG 0x00000003 +#define GPIO_PIN25_CONFIG_M (GPIO_PIN25_CONFIG_V << GPIO_PIN25_CONFIG_S) +#define GPIO_PIN25_CONFIG_V 0x00000003 +#define GPIO_PIN25_CONFIG_S 11 + +/* GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN25_INT_TYPE 0x00000007 +#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) +#define GPIO_PIN25_INT_TYPE_V 0x00000007 +#define GPIO_PIN25_INT_TYPE_S 7 + +/* GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN25_SYNC1_BYPASS_S 3 + +/* GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) +#define GPIO_PIN25_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN25_PAD_DRIVER_S 2 + +/* GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN25_SYNC2_BYPASS_S 0 + +/* GPIO_PIN26_REG register + * Configuration for GPIO pin 26 + */ + +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xdc) + +/* GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN26_INT_ENA 0x0000001F +#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) +#define GPIO_PIN26_INT_ENA_V 0x0000001F +#define GPIO_PIN26_INT_ENA_S 13 + +/* GPIO_PIN26_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN26_CONFIG 0x00000003 +#define GPIO_PIN26_CONFIG_M (GPIO_PIN26_CONFIG_V << GPIO_PIN26_CONFIG_S) +#define GPIO_PIN26_CONFIG_V 0x00000003 +#define GPIO_PIN26_CONFIG_S 11 + +/* GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN26_INT_TYPE 0x00000007 +#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) +#define GPIO_PIN26_INT_TYPE_V 0x00000007 +#define GPIO_PIN26_INT_TYPE_S 7 + +/* GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN26_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) +#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN26_SYNC1_BYPASS_S 3 + +/* GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) +#define GPIO_PIN26_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN26_PAD_DRIVER_S 2 + +/* GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN26_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) +#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN26_SYNC2_BYPASS_S 0 + +/* GPIO_PIN27_REG register + * Configuration for GPIO pin 27 + */ + +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xe0) + +/* GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN27_INT_ENA 0x0000001F +#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) +#define GPIO_PIN27_INT_ENA_V 0x0000001F +#define GPIO_PIN27_INT_ENA_S 13 + +/* GPIO_PIN27_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN27_CONFIG 0x00000003 +#define GPIO_PIN27_CONFIG_M (GPIO_PIN27_CONFIG_V << GPIO_PIN27_CONFIG_S) +#define GPIO_PIN27_CONFIG_V 0x00000003 +#define GPIO_PIN27_CONFIG_S 11 + +/* GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN27_INT_TYPE 0x00000007 +#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) +#define GPIO_PIN27_INT_TYPE_V 0x00000007 +#define GPIO_PIN27_INT_TYPE_S 7 + +/* GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN27_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) +#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN27_SYNC1_BYPASS_S 3 + +/* GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) +#define GPIO_PIN27_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN27_PAD_DRIVER_S 2 + +/* GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN27_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) +#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN27_SYNC2_BYPASS_S 0 + +/* GPIO_PIN28_REG register + * Configuration for GPIO pin 28 + */ + +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xe4) + +/* GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN28_INT_ENA 0x0000001F +#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) +#define GPIO_PIN28_INT_ENA_V 0x0000001F +#define GPIO_PIN28_INT_ENA_S 13 + +/* GPIO_PIN28_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN28_CONFIG 0x00000003 +#define GPIO_PIN28_CONFIG_M (GPIO_PIN28_CONFIG_V << GPIO_PIN28_CONFIG_S) +#define GPIO_PIN28_CONFIG_V 0x00000003 +#define GPIO_PIN28_CONFIG_S 11 + +/* GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN28_INT_TYPE 0x00000007 +#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) +#define GPIO_PIN28_INT_TYPE_V 0x00000007 +#define GPIO_PIN28_INT_TYPE_S 7 + +/* GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN28_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) +#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN28_SYNC1_BYPASS_S 3 + +/* GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) +#define GPIO_PIN28_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN28_PAD_DRIVER_S 2 + +/* GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN28_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) +#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN28_SYNC2_BYPASS_S 0 + +/* GPIO_PIN29_REG register + * Configuration for GPIO pin 29 + */ + +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xe8) + +/* GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN29_INT_ENA 0x0000001F +#define GPIO_PIN29_INT_ENA_M (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S) +#define GPIO_PIN29_INT_ENA_V 0x0000001F +#define GPIO_PIN29_INT_ENA_S 13 + +/* GPIO_PIN29_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN29_CONFIG 0x00000003 +#define GPIO_PIN29_CONFIG_M (GPIO_PIN29_CONFIG_V << GPIO_PIN29_CONFIG_S) +#define GPIO_PIN29_CONFIG_V 0x00000003 +#define GPIO_PIN29_CONFIG_S 11 + +/* GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN29_INT_TYPE 0x00000007 +#define GPIO_PIN29_INT_TYPE_M (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S) +#define GPIO_PIN29_INT_TYPE_V 0x00000007 +#define GPIO_PIN29_INT_TYPE_S 7 + +/* GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN29_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN29_SYNC1_BYPASS_M (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S) +#define GPIO_PIN29_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN29_SYNC1_BYPASS_S 3 + +/* GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S) +#define GPIO_PIN29_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN29_PAD_DRIVER_S 2 + +/* GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN29_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN29_SYNC2_BYPASS_M (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S) +#define GPIO_PIN29_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN29_SYNC2_BYPASS_S 0 + +/* GPIO_PIN30_REG register + * Configuration for GPIO pin 30 + */ + +#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xec) + +/* GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN30_INT_ENA 0x0000001F +#define GPIO_PIN30_INT_ENA_M (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S) +#define GPIO_PIN30_INT_ENA_V 0x0000001F +#define GPIO_PIN30_INT_ENA_S 13 + +/* GPIO_PIN30_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN30_CONFIG 0x00000003 +#define GPIO_PIN30_CONFIG_M (GPIO_PIN30_CONFIG_V << GPIO_PIN30_CONFIG_S) +#define GPIO_PIN30_CONFIG_V 0x00000003 +#define GPIO_PIN30_CONFIG_S 11 + +/* GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_M (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S) +#define GPIO_PIN30_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN30_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN30_INT_TYPE 0x00000007 +#define GPIO_PIN30_INT_TYPE_M (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S) +#define GPIO_PIN30_INT_TYPE_V 0x00000007 +#define GPIO_PIN30_INT_TYPE_S 7 + +/* GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN30_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN30_SYNC1_BYPASS_M (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S) +#define GPIO_PIN30_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN30_SYNC1_BYPASS_S 3 + +/* GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_M (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S) +#define GPIO_PIN30_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN30_PAD_DRIVER_S 2 + +/* GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN30_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN30_SYNC2_BYPASS_M (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S) +#define GPIO_PIN30_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN30_SYNC2_BYPASS_S 0 + +/* GPIO_PIN31_REG register + * Configuration for GPIO pin 31 + */ + +#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xf0) + +/* GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN31_INT_ENA 0x0000001F +#define GPIO_PIN31_INT_ENA_M (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S) +#define GPIO_PIN31_INT_ENA_V 0x0000001F +#define GPIO_PIN31_INT_ENA_S 13 + +/* GPIO_PIN31_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN31_CONFIG 0x00000003 +#define GPIO_PIN31_CONFIG_M (GPIO_PIN31_CONFIG_V << GPIO_PIN31_CONFIG_S) +#define GPIO_PIN31_CONFIG_V 0x00000003 +#define GPIO_PIN31_CONFIG_S 11 + +/* GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_M (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S) +#define GPIO_PIN31_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN31_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN31_INT_TYPE 0x00000007 +#define GPIO_PIN31_INT_TYPE_M (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S) +#define GPIO_PIN31_INT_TYPE_V 0x00000007 +#define GPIO_PIN31_INT_TYPE_S 7 + +/* GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN31_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN31_SYNC1_BYPASS_M (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S) +#define GPIO_PIN31_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN31_SYNC1_BYPASS_S 3 + +/* GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN31_PAD_DRIVER (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_M (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S) +#define GPIO_PIN31_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN31_PAD_DRIVER_S 2 + +/* GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN31_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN31_SYNC2_BYPASS_M (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S) +#define GPIO_PIN31_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN31_SYNC2_BYPASS_S 0 + +/* GPIO_PIN32_REG register + * Configuration for GPIO pin 32 + */ + +#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0xf4) + +/* GPIO_PIN32_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN32_INT_ENA 0x0000001F +#define GPIO_PIN32_INT_ENA_M (GPIO_PIN32_INT_ENA_V << GPIO_PIN32_INT_ENA_S) +#define GPIO_PIN32_INT_ENA_V 0x0000001F +#define GPIO_PIN32_INT_ENA_S 13 + +/* GPIO_PIN32_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN32_CONFIG 0x00000003 +#define GPIO_PIN32_CONFIG_M (GPIO_PIN32_CONFIG_V << GPIO_PIN32_CONFIG_S) +#define GPIO_PIN32_CONFIG_V 0x00000003 +#define GPIO_PIN32_CONFIG_S 11 + +/* GPIO_PIN32_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_M (GPIO_PIN32_WAKEUP_ENABLE_V << GPIO_PIN32_WAKEUP_ENABLE_S) +#define GPIO_PIN32_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN32_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN32_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN32_INT_TYPE 0x00000007 +#define GPIO_PIN32_INT_TYPE_M (GPIO_PIN32_INT_TYPE_V << GPIO_PIN32_INT_TYPE_S) +#define GPIO_PIN32_INT_TYPE_V 0x00000007 +#define GPIO_PIN32_INT_TYPE_S 7 + +/* GPIO_PIN32_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN32_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN32_SYNC1_BYPASS_M (GPIO_PIN32_SYNC1_BYPASS_V << GPIO_PIN32_SYNC1_BYPASS_S) +#define GPIO_PIN32_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN32_SYNC1_BYPASS_S 3 + +/* GPIO_PIN32_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN32_PAD_DRIVER (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_M (GPIO_PIN32_PAD_DRIVER_V << GPIO_PIN32_PAD_DRIVER_S) +#define GPIO_PIN32_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN32_PAD_DRIVER_S 2 + +/* GPIO_PIN32_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN32_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN32_SYNC2_BYPASS_M (GPIO_PIN32_SYNC2_BYPASS_V << GPIO_PIN32_SYNC2_BYPASS_S) +#define GPIO_PIN32_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN32_SYNC2_BYPASS_S 0 + +/* GPIO_PIN33_REG register + * Configuration for GPIO pin 33 + */ + +#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0xf8) + +/* GPIO_PIN33_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN33_INT_ENA 0x0000001F +#define GPIO_PIN33_INT_ENA_M (GPIO_PIN33_INT_ENA_V << GPIO_PIN33_INT_ENA_S) +#define GPIO_PIN33_INT_ENA_V 0x0000001F +#define GPIO_PIN33_INT_ENA_S 13 + +/* GPIO_PIN33_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN33_CONFIG 0x00000003 +#define GPIO_PIN33_CONFIG_M (GPIO_PIN33_CONFIG_V << GPIO_PIN33_CONFIG_S) +#define GPIO_PIN33_CONFIG_V 0x00000003 +#define GPIO_PIN33_CONFIG_S 11 + +/* GPIO_PIN33_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_M (GPIO_PIN33_WAKEUP_ENABLE_V << GPIO_PIN33_WAKEUP_ENABLE_S) +#define GPIO_PIN33_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN33_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN33_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN33_INT_TYPE 0x00000007 +#define GPIO_PIN33_INT_TYPE_M (GPIO_PIN33_INT_TYPE_V << GPIO_PIN33_INT_TYPE_S) +#define GPIO_PIN33_INT_TYPE_V 0x00000007 +#define GPIO_PIN33_INT_TYPE_S 7 + +/* GPIO_PIN33_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN33_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN33_SYNC1_BYPASS_M (GPIO_PIN33_SYNC1_BYPASS_V << GPIO_PIN33_SYNC1_BYPASS_S) +#define GPIO_PIN33_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN33_SYNC1_BYPASS_S 3 + +/* GPIO_PIN33_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN33_PAD_DRIVER (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_M (GPIO_PIN33_PAD_DRIVER_V << GPIO_PIN33_PAD_DRIVER_S) +#define GPIO_PIN33_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN33_PAD_DRIVER_S 2 + +/* GPIO_PIN33_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN33_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN33_SYNC2_BYPASS_M (GPIO_PIN33_SYNC2_BYPASS_V << GPIO_PIN33_SYNC2_BYPASS_S) +#define GPIO_PIN33_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN33_SYNC2_BYPASS_S 0 + +/* GPIO_PIN34_REG register + * Configuration for GPIO pin 34 + */ + +#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0xfc) + +/* GPIO_PIN34_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN34_INT_ENA 0x0000001F +#define GPIO_PIN34_INT_ENA_M (GPIO_PIN34_INT_ENA_V << GPIO_PIN34_INT_ENA_S) +#define GPIO_PIN34_INT_ENA_V 0x0000001F +#define GPIO_PIN34_INT_ENA_S 13 + +/* GPIO_PIN34_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN34_CONFIG 0x00000003 +#define GPIO_PIN34_CONFIG_M (GPIO_PIN34_CONFIG_V << GPIO_PIN34_CONFIG_S) +#define GPIO_PIN34_CONFIG_V 0x00000003 +#define GPIO_PIN34_CONFIG_S 11 + +/* GPIO_PIN34_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE_M (GPIO_PIN34_WAKEUP_ENABLE_V << GPIO_PIN34_WAKEUP_ENABLE_S) +#define GPIO_PIN34_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN34_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN34_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN34_INT_TYPE 0x00000007 +#define GPIO_PIN34_INT_TYPE_M (GPIO_PIN34_INT_TYPE_V << GPIO_PIN34_INT_TYPE_S) +#define GPIO_PIN34_INT_TYPE_V 0x00000007 +#define GPIO_PIN34_INT_TYPE_S 7 + +/* GPIO_PIN34_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN34_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN34_SYNC1_BYPASS_M (GPIO_PIN34_SYNC1_BYPASS_V << GPIO_PIN34_SYNC1_BYPASS_S) +#define GPIO_PIN34_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN34_SYNC1_BYPASS_S 3 + +/* GPIO_PIN34_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN34_PAD_DRIVER (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER_M (GPIO_PIN34_PAD_DRIVER_V << GPIO_PIN34_PAD_DRIVER_S) +#define GPIO_PIN34_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN34_PAD_DRIVER_S 2 + +/* GPIO_PIN34_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN34_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN34_SYNC2_BYPASS_M (GPIO_PIN34_SYNC2_BYPASS_V << GPIO_PIN34_SYNC2_BYPASS_S) +#define GPIO_PIN34_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN34_SYNC2_BYPASS_S 0 + +/* GPIO_PIN35_REG register + * Configuration for GPIO pin 35 + */ + +#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x100) + +/* GPIO_PIN35_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN35_INT_ENA 0x0000001F +#define GPIO_PIN35_INT_ENA_M (GPIO_PIN35_INT_ENA_V << GPIO_PIN35_INT_ENA_S) +#define GPIO_PIN35_INT_ENA_V 0x0000001F +#define GPIO_PIN35_INT_ENA_S 13 + +/* GPIO_PIN35_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN35_CONFIG 0x00000003 +#define GPIO_PIN35_CONFIG_M (GPIO_PIN35_CONFIG_V << GPIO_PIN35_CONFIG_S) +#define GPIO_PIN35_CONFIG_V 0x00000003 +#define GPIO_PIN35_CONFIG_S 11 + +/* GPIO_PIN35_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN35_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN35_WAKEUP_ENABLE_M (GPIO_PIN35_WAKEUP_ENABLE_V << GPIO_PIN35_WAKEUP_ENABLE_S) +#define GPIO_PIN35_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN35_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN35_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN35_INT_TYPE 0x00000007 +#define GPIO_PIN35_INT_TYPE_M (GPIO_PIN35_INT_TYPE_V << GPIO_PIN35_INT_TYPE_S) +#define GPIO_PIN35_INT_TYPE_V 0x00000007 +#define GPIO_PIN35_INT_TYPE_S 7 + +/* GPIO_PIN35_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN35_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN35_SYNC1_BYPASS_M (GPIO_PIN35_SYNC1_BYPASS_V << GPIO_PIN35_SYNC1_BYPASS_S) +#define GPIO_PIN35_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN35_SYNC1_BYPASS_S 3 + +/* GPIO_PIN35_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN35_PAD_DRIVER (BIT(2)) +#define GPIO_PIN35_PAD_DRIVER_M (GPIO_PIN35_PAD_DRIVER_V << GPIO_PIN35_PAD_DRIVER_S) +#define GPIO_PIN35_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN35_PAD_DRIVER_S 2 + +/* GPIO_PIN35_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN35_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN35_SYNC2_BYPASS_M (GPIO_PIN35_SYNC2_BYPASS_V << GPIO_PIN35_SYNC2_BYPASS_S) +#define GPIO_PIN35_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN35_SYNC2_BYPASS_S 0 + +/* GPIO_PIN36_REG register + * Configuration for GPIO pin 36 + */ + +#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x104) + +/* GPIO_PIN36_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN36_INT_ENA 0x0000001F +#define GPIO_PIN36_INT_ENA_M (GPIO_PIN36_INT_ENA_V << GPIO_PIN36_INT_ENA_S) +#define GPIO_PIN36_INT_ENA_V 0x0000001F +#define GPIO_PIN36_INT_ENA_S 13 + +/* GPIO_PIN36_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN36_CONFIG 0x00000003 +#define GPIO_PIN36_CONFIG_M (GPIO_PIN36_CONFIG_V << GPIO_PIN36_CONFIG_S) +#define GPIO_PIN36_CONFIG_V 0x00000003 +#define GPIO_PIN36_CONFIG_S 11 + +/* GPIO_PIN36_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN36_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN36_WAKEUP_ENABLE_M (GPIO_PIN36_WAKEUP_ENABLE_V << GPIO_PIN36_WAKEUP_ENABLE_S) +#define GPIO_PIN36_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN36_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN36_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN36_INT_TYPE 0x00000007 +#define GPIO_PIN36_INT_TYPE_M (GPIO_PIN36_INT_TYPE_V << GPIO_PIN36_INT_TYPE_S) +#define GPIO_PIN36_INT_TYPE_V 0x00000007 +#define GPIO_PIN36_INT_TYPE_S 7 + +/* GPIO_PIN36_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN36_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN36_SYNC1_BYPASS_M (GPIO_PIN36_SYNC1_BYPASS_V << GPIO_PIN36_SYNC1_BYPASS_S) +#define GPIO_PIN36_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN36_SYNC1_BYPASS_S 3 + +/* GPIO_PIN36_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN36_PAD_DRIVER (BIT(2)) +#define GPIO_PIN36_PAD_DRIVER_M (GPIO_PIN36_PAD_DRIVER_V << GPIO_PIN36_PAD_DRIVER_S) +#define GPIO_PIN36_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN36_PAD_DRIVER_S 2 + +/* GPIO_PIN36_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN36_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN36_SYNC2_BYPASS_M (GPIO_PIN36_SYNC2_BYPASS_V << GPIO_PIN36_SYNC2_BYPASS_S) +#define GPIO_PIN36_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN36_SYNC2_BYPASS_S 0 + +/* GPIO_PIN37_REG register + * Configuration for GPIO pin 37 + */ + +#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x108) + +/* GPIO_PIN37_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN37_INT_ENA 0x0000001F +#define GPIO_PIN37_INT_ENA_M (GPIO_PIN37_INT_ENA_V << GPIO_PIN37_INT_ENA_S) +#define GPIO_PIN37_INT_ENA_V 0x0000001F +#define GPIO_PIN37_INT_ENA_S 13 + +/* GPIO_PIN37_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN37_CONFIG 0x00000003 +#define GPIO_PIN37_CONFIG_M (GPIO_PIN37_CONFIG_V << GPIO_PIN37_CONFIG_S) +#define GPIO_PIN37_CONFIG_V 0x00000003 +#define GPIO_PIN37_CONFIG_S 11 + +/* GPIO_PIN37_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN37_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN37_WAKEUP_ENABLE_M (GPIO_PIN37_WAKEUP_ENABLE_V << GPIO_PIN37_WAKEUP_ENABLE_S) +#define GPIO_PIN37_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN37_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN37_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN37_INT_TYPE 0x00000007 +#define GPIO_PIN37_INT_TYPE_M (GPIO_PIN37_INT_TYPE_V << GPIO_PIN37_INT_TYPE_S) +#define GPIO_PIN37_INT_TYPE_V 0x00000007 +#define GPIO_PIN37_INT_TYPE_S 7 + +/* GPIO_PIN37_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN37_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN37_SYNC1_BYPASS_M (GPIO_PIN37_SYNC1_BYPASS_V << GPIO_PIN37_SYNC1_BYPASS_S) +#define GPIO_PIN37_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN37_SYNC1_BYPASS_S 3 + +/* GPIO_PIN37_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN37_PAD_DRIVER (BIT(2)) +#define GPIO_PIN37_PAD_DRIVER_M (GPIO_PIN37_PAD_DRIVER_V << GPIO_PIN37_PAD_DRIVER_S) +#define GPIO_PIN37_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN37_PAD_DRIVER_S 2 + +/* GPIO_PIN37_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN37_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN37_SYNC2_BYPASS_M (GPIO_PIN37_SYNC2_BYPASS_V << GPIO_PIN37_SYNC2_BYPASS_S) +#define GPIO_PIN37_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN37_SYNC2_BYPASS_S 0 + +/* GPIO_PIN38_REG register + * Configuration for GPIO pin 38 + */ + +#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x10c) + +/* GPIO_PIN38_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN38_INT_ENA 0x0000001F +#define GPIO_PIN38_INT_ENA_M (GPIO_PIN38_INT_ENA_V << GPIO_PIN38_INT_ENA_S) +#define GPIO_PIN38_INT_ENA_V 0x0000001F +#define GPIO_PIN38_INT_ENA_S 13 + +/* GPIO_PIN38_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN38_CONFIG 0x00000003 +#define GPIO_PIN38_CONFIG_M (GPIO_PIN38_CONFIG_V << GPIO_PIN38_CONFIG_S) +#define GPIO_PIN38_CONFIG_V 0x00000003 +#define GPIO_PIN38_CONFIG_S 11 + +/* GPIO_PIN38_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN38_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN38_WAKEUP_ENABLE_M (GPIO_PIN38_WAKEUP_ENABLE_V << GPIO_PIN38_WAKEUP_ENABLE_S) +#define GPIO_PIN38_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN38_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN38_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN38_INT_TYPE 0x00000007 +#define GPIO_PIN38_INT_TYPE_M (GPIO_PIN38_INT_TYPE_V << GPIO_PIN38_INT_TYPE_S) +#define GPIO_PIN38_INT_TYPE_V 0x00000007 +#define GPIO_PIN38_INT_TYPE_S 7 + +/* GPIO_PIN38_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN38_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN38_SYNC1_BYPASS_M (GPIO_PIN38_SYNC1_BYPASS_V << GPIO_PIN38_SYNC1_BYPASS_S) +#define GPIO_PIN38_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN38_SYNC1_BYPASS_S 3 + +/* GPIO_PIN38_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN38_PAD_DRIVER (BIT(2)) +#define GPIO_PIN38_PAD_DRIVER_M (GPIO_PIN38_PAD_DRIVER_V << GPIO_PIN38_PAD_DRIVER_S) +#define GPIO_PIN38_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN38_PAD_DRIVER_S 2 + +/* GPIO_PIN38_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN38_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN38_SYNC2_BYPASS_M (GPIO_PIN38_SYNC2_BYPASS_V << GPIO_PIN38_SYNC2_BYPASS_S) +#define GPIO_PIN38_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN38_SYNC2_BYPASS_S 0 + +/* GPIO_PIN39_REG register + * Configuration for GPIO pin 39 + */ + +#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x110) + +/* GPIO_PIN39_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN39_INT_ENA 0x0000001F +#define GPIO_PIN39_INT_ENA_M (GPIO_PIN39_INT_ENA_V << GPIO_PIN39_INT_ENA_S) +#define GPIO_PIN39_INT_ENA_V 0x0000001F +#define GPIO_PIN39_INT_ENA_S 13 + +/* GPIO_PIN39_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN39_CONFIG 0x00000003 +#define GPIO_PIN39_CONFIG_M (GPIO_PIN39_CONFIG_V << GPIO_PIN39_CONFIG_S) +#define GPIO_PIN39_CONFIG_V 0x00000003 +#define GPIO_PIN39_CONFIG_S 11 + +/* GPIO_PIN39_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN39_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN39_WAKEUP_ENABLE_M (GPIO_PIN39_WAKEUP_ENABLE_V << GPIO_PIN39_WAKEUP_ENABLE_S) +#define GPIO_PIN39_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN39_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN39_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN39_INT_TYPE 0x00000007 +#define GPIO_PIN39_INT_TYPE_M (GPIO_PIN39_INT_TYPE_V << GPIO_PIN39_INT_TYPE_S) +#define GPIO_PIN39_INT_TYPE_V 0x00000007 +#define GPIO_PIN39_INT_TYPE_S 7 + +/* GPIO_PIN39_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN39_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN39_SYNC1_BYPASS_M (GPIO_PIN39_SYNC1_BYPASS_V << GPIO_PIN39_SYNC1_BYPASS_S) +#define GPIO_PIN39_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN39_SYNC1_BYPASS_S 3 + +/* GPIO_PIN39_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN39_PAD_DRIVER (BIT(2)) +#define GPIO_PIN39_PAD_DRIVER_M (GPIO_PIN39_PAD_DRIVER_V << GPIO_PIN39_PAD_DRIVER_S) +#define GPIO_PIN39_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN39_PAD_DRIVER_S 2 + +/* GPIO_PIN39_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN39_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN39_SYNC2_BYPASS_M (GPIO_PIN39_SYNC2_BYPASS_V << GPIO_PIN39_SYNC2_BYPASS_S) +#define GPIO_PIN39_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN39_SYNC2_BYPASS_S 0 + +/* GPIO_PIN40_REG register + * Configuration for GPIO pin 40 + */ + +#define GPIO_PIN40_REG (DR_REG_GPIO_BASE + 0x114) + +/* GPIO_PIN40_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN40_INT_ENA 0x0000001F +#define GPIO_PIN40_INT_ENA_M (GPIO_PIN40_INT_ENA_V << GPIO_PIN40_INT_ENA_S) +#define GPIO_PIN40_INT_ENA_V 0x0000001F +#define GPIO_PIN40_INT_ENA_S 13 + +/* GPIO_PIN40_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN40_CONFIG 0x00000003 +#define GPIO_PIN40_CONFIG_M (GPIO_PIN40_CONFIG_V << GPIO_PIN40_CONFIG_S) +#define GPIO_PIN40_CONFIG_V 0x00000003 +#define GPIO_PIN40_CONFIG_S 11 + +/* GPIO_PIN40_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN40_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN40_WAKEUP_ENABLE_M (GPIO_PIN40_WAKEUP_ENABLE_V << GPIO_PIN40_WAKEUP_ENABLE_S) +#define GPIO_PIN40_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN40_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN40_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN40_INT_TYPE 0x00000007 +#define GPIO_PIN40_INT_TYPE_M (GPIO_PIN40_INT_TYPE_V << GPIO_PIN40_INT_TYPE_S) +#define GPIO_PIN40_INT_TYPE_V 0x00000007 +#define GPIO_PIN40_INT_TYPE_S 7 + +/* GPIO_PIN40_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN40_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN40_SYNC1_BYPASS_M (GPIO_PIN40_SYNC1_BYPASS_V << GPIO_PIN40_SYNC1_BYPASS_S) +#define GPIO_PIN40_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN40_SYNC1_BYPASS_S 3 + +/* GPIO_PIN40_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN40_PAD_DRIVER (BIT(2)) +#define GPIO_PIN40_PAD_DRIVER_M (GPIO_PIN40_PAD_DRIVER_V << GPIO_PIN40_PAD_DRIVER_S) +#define GPIO_PIN40_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN40_PAD_DRIVER_S 2 + +/* GPIO_PIN40_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN40_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN40_SYNC2_BYPASS_M (GPIO_PIN40_SYNC2_BYPASS_V << GPIO_PIN40_SYNC2_BYPASS_S) +#define GPIO_PIN40_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN40_SYNC2_BYPASS_S 0 + +/* GPIO_PIN41_REG register + * Configuration for GPIO pin 41 + */ + +#define GPIO_PIN41_REG (DR_REG_GPIO_BASE + 0x118) + +/* GPIO_PIN41_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN41_INT_ENA 0x0000001F +#define GPIO_PIN41_INT_ENA_M (GPIO_PIN41_INT_ENA_V << GPIO_PIN41_INT_ENA_S) +#define GPIO_PIN41_INT_ENA_V 0x0000001F +#define GPIO_PIN41_INT_ENA_S 13 + +/* GPIO_PIN41_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN41_CONFIG 0x00000003 +#define GPIO_PIN41_CONFIG_M (GPIO_PIN41_CONFIG_V << GPIO_PIN41_CONFIG_S) +#define GPIO_PIN41_CONFIG_V 0x00000003 +#define GPIO_PIN41_CONFIG_S 11 + +/* GPIO_PIN41_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN41_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN41_WAKEUP_ENABLE_M (GPIO_PIN41_WAKEUP_ENABLE_V << GPIO_PIN41_WAKEUP_ENABLE_S) +#define GPIO_PIN41_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN41_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN41_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN41_INT_TYPE 0x00000007 +#define GPIO_PIN41_INT_TYPE_M (GPIO_PIN41_INT_TYPE_V << GPIO_PIN41_INT_TYPE_S) +#define GPIO_PIN41_INT_TYPE_V 0x00000007 +#define GPIO_PIN41_INT_TYPE_S 7 + +/* GPIO_PIN41_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN41_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN41_SYNC1_BYPASS_M (GPIO_PIN41_SYNC1_BYPASS_V << GPIO_PIN41_SYNC1_BYPASS_S) +#define GPIO_PIN41_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN41_SYNC1_BYPASS_S 3 + +/* GPIO_PIN41_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN41_PAD_DRIVER (BIT(2)) +#define GPIO_PIN41_PAD_DRIVER_M (GPIO_PIN41_PAD_DRIVER_V << GPIO_PIN41_PAD_DRIVER_S) +#define GPIO_PIN41_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN41_PAD_DRIVER_S 2 + +/* GPIO_PIN41_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN41_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN41_SYNC2_BYPASS_M (GPIO_PIN41_SYNC2_BYPASS_V << GPIO_PIN41_SYNC2_BYPASS_S) +#define GPIO_PIN41_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN41_SYNC2_BYPASS_S 0 + +/* GPIO_PIN42_REG register + * Configuration for GPIO pin 42 + */ + +#define GPIO_PIN42_REG (DR_REG_GPIO_BASE + 0x11c) + +/* GPIO_PIN42_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN42_INT_ENA 0x0000001F +#define GPIO_PIN42_INT_ENA_M (GPIO_PIN42_INT_ENA_V << GPIO_PIN42_INT_ENA_S) +#define GPIO_PIN42_INT_ENA_V 0x0000001F +#define GPIO_PIN42_INT_ENA_S 13 + +/* GPIO_PIN42_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN42_CONFIG 0x00000003 +#define GPIO_PIN42_CONFIG_M (GPIO_PIN42_CONFIG_V << GPIO_PIN42_CONFIG_S) +#define GPIO_PIN42_CONFIG_V 0x00000003 +#define GPIO_PIN42_CONFIG_S 11 + +/* GPIO_PIN42_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN42_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN42_WAKEUP_ENABLE_M (GPIO_PIN42_WAKEUP_ENABLE_V << GPIO_PIN42_WAKEUP_ENABLE_S) +#define GPIO_PIN42_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN42_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN42_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN42_INT_TYPE 0x00000007 +#define GPIO_PIN42_INT_TYPE_M (GPIO_PIN42_INT_TYPE_V << GPIO_PIN42_INT_TYPE_S) +#define GPIO_PIN42_INT_TYPE_V 0x00000007 +#define GPIO_PIN42_INT_TYPE_S 7 + +/* GPIO_PIN42_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN42_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN42_SYNC1_BYPASS_M (GPIO_PIN42_SYNC1_BYPASS_V << GPIO_PIN42_SYNC1_BYPASS_S) +#define GPIO_PIN42_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN42_SYNC1_BYPASS_S 3 + +/* GPIO_PIN42_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN42_PAD_DRIVER (BIT(2)) +#define GPIO_PIN42_PAD_DRIVER_M (GPIO_PIN42_PAD_DRIVER_V << GPIO_PIN42_PAD_DRIVER_S) +#define GPIO_PIN42_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN42_PAD_DRIVER_S 2 + +/* GPIO_PIN42_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN42_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN42_SYNC2_BYPASS_M (GPIO_PIN42_SYNC2_BYPASS_V << GPIO_PIN42_SYNC2_BYPASS_S) +#define GPIO_PIN42_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN42_SYNC2_BYPASS_S 0 + +/* GPIO_PIN43_REG register + * Configuration for GPIO pin 43 + */ + +#define GPIO_PIN43_REG (DR_REG_GPIO_BASE + 0x120) + +/* GPIO_PIN43_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN43_INT_ENA 0x0000001F +#define GPIO_PIN43_INT_ENA_M (GPIO_PIN43_INT_ENA_V << GPIO_PIN43_INT_ENA_S) +#define GPIO_PIN43_INT_ENA_V 0x0000001F +#define GPIO_PIN43_INT_ENA_S 13 + +/* GPIO_PIN43_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN43_CONFIG 0x00000003 +#define GPIO_PIN43_CONFIG_M (GPIO_PIN43_CONFIG_V << GPIO_PIN43_CONFIG_S) +#define GPIO_PIN43_CONFIG_V 0x00000003 +#define GPIO_PIN43_CONFIG_S 11 + +/* GPIO_PIN43_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN43_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN43_WAKEUP_ENABLE_M (GPIO_PIN43_WAKEUP_ENABLE_V << GPIO_PIN43_WAKEUP_ENABLE_S) +#define GPIO_PIN43_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN43_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN43_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN43_INT_TYPE 0x00000007 +#define GPIO_PIN43_INT_TYPE_M (GPIO_PIN43_INT_TYPE_V << GPIO_PIN43_INT_TYPE_S) +#define GPIO_PIN43_INT_TYPE_V 0x00000007 +#define GPIO_PIN43_INT_TYPE_S 7 + +/* GPIO_PIN43_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN43_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN43_SYNC1_BYPASS_M (GPIO_PIN43_SYNC1_BYPASS_V << GPIO_PIN43_SYNC1_BYPASS_S) +#define GPIO_PIN43_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN43_SYNC1_BYPASS_S 3 + +/* GPIO_PIN43_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN43_PAD_DRIVER (BIT(2)) +#define GPIO_PIN43_PAD_DRIVER_M (GPIO_PIN43_PAD_DRIVER_V << GPIO_PIN43_PAD_DRIVER_S) +#define GPIO_PIN43_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN43_PAD_DRIVER_S 2 + +/* GPIO_PIN43_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN43_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN43_SYNC2_BYPASS_M (GPIO_PIN43_SYNC2_BYPASS_V << GPIO_PIN43_SYNC2_BYPASS_S) +#define GPIO_PIN43_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN43_SYNC2_BYPASS_S 0 + +/* GPIO_PIN44_REG register + * Configuration for GPIO pin 44 + */ + +#define GPIO_PIN44_REG (DR_REG_GPIO_BASE + 0x124) + +/* GPIO_PIN44_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN44_INT_ENA 0x0000001F +#define GPIO_PIN44_INT_ENA_M (GPIO_PIN44_INT_ENA_V << GPIO_PIN44_INT_ENA_S) +#define GPIO_PIN44_INT_ENA_V 0x0000001F +#define GPIO_PIN44_INT_ENA_S 13 + +/* GPIO_PIN44_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN44_CONFIG 0x00000003 +#define GPIO_PIN44_CONFIG_M (GPIO_PIN44_CONFIG_V << GPIO_PIN44_CONFIG_S) +#define GPIO_PIN44_CONFIG_V 0x00000003 +#define GPIO_PIN44_CONFIG_S 11 + +/* GPIO_PIN44_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN44_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN44_WAKEUP_ENABLE_M (GPIO_PIN44_WAKEUP_ENABLE_V << GPIO_PIN44_WAKEUP_ENABLE_S) +#define GPIO_PIN44_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN44_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN44_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN44_INT_TYPE 0x00000007 +#define GPIO_PIN44_INT_TYPE_M (GPIO_PIN44_INT_TYPE_V << GPIO_PIN44_INT_TYPE_S) +#define GPIO_PIN44_INT_TYPE_V 0x00000007 +#define GPIO_PIN44_INT_TYPE_S 7 + +/* GPIO_PIN44_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN44_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN44_SYNC1_BYPASS_M (GPIO_PIN44_SYNC1_BYPASS_V << GPIO_PIN44_SYNC1_BYPASS_S) +#define GPIO_PIN44_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN44_SYNC1_BYPASS_S 3 + +/* GPIO_PIN44_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN44_PAD_DRIVER (BIT(2)) +#define GPIO_PIN44_PAD_DRIVER_M (GPIO_PIN44_PAD_DRIVER_V << GPIO_PIN44_PAD_DRIVER_S) +#define GPIO_PIN44_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN44_PAD_DRIVER_S 2 + +/* GPIO_PIN44_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN44_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN44_SYNC2_BYPASS_M (GPIO_PIN44_SYNC2_BYPASS_V << GPIO_PIN44_SYNC2_BYPASS_S) +#define GPIO_PIN44_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN44_SYNC2_BYPASS_S 0 + +/* GPIO_PIN45_REG register + * Configuration for GPIO pin 45 + */ + +#define GPIO_PIN45_REG (DR_REG_GPIO_BASE + 0x128) + +/* GPIO_PIN45_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN45_INT_ENA 0x0000001F +#define GPIO_PIN45_INT_ENA_M (GPIO_PIN45_INT_ENA_V << GPIO_PIN45_INT_ENA_S) +#define GPIO_PIN45_INT_ENA_V 0x0000001F +#define GPIO_PIN45_INT_ENA_S 13 + +/* GPIO_PIN45_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN45_CONFIG 0x00000003 +#define GPIO_PIN45_CONFIG_M (GPIO_PIN45_CONFIG_V << GPIO_PIN45_CONFIG_S) +#define GPIO_PIN45_CONFIG_V 0x00000003 +#define GPIO_PIN45_CONFIG_S 11 + +/* GPIO_PIN45_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN45_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN45_WAKEUP_ENABLE_M (GPIO_PIN45_WAKEUP_ENABLE_V << GPIO_PIN45_WAKEUP_ENABLE_S) +#define GPIO_PIN45_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN45_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN45_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN45_INT_TYPE 0x00000007 +#define GPIO_PIN45_INT_TYPE_M (GPIO_PIN45_INT_TYPE_V << GPIO_PIN45_INT_TYPE_S) +#define GPIO_PIN45_INT_TYPE_V 0x00000007 +#define GPIO_PIN45_INT_TYPE_S 7 + +/* GPIO_PIN45_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN45_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN45_SYNC1_BYPASS_M (GPIO_PIN45_SYNC1_BYPASS_V << GPIO_PIN45_SYNC1_BYPASS_S) +#define GPIO_PIN45_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN45_SYNC1_BYPASS_S 3 + +/* GPIO_PIN45_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN45_PAD_DRIVER (BIT(2)) +#define GPIO_PIN45_PAD_DRIVER_M (GPIO_PIN45_PAD_DRIVER_V << GPIO_PIN45_PAD_DRIVER_S) +#define GPIO_PIN45_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN45_PAD_DRIVER_S 2 + +/* GPIO_PIN45_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN45_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN45_SYNC2_BYPASS_M (GPIO_PIN45_SYNC2_BYPASS_V << GPIO_PIN45_SYNC2_BYPASS_S) +#define GPIO_PIN45_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN45_SYNC2_BYPASS_S 0 + +/* GPIO_PIN46_REG register + * Configuration for GPIO pin 46 + */ + +#define GPIO_PIN46_REG (DR_REG_GPIO_BASE + 0x12c) + +/* GPIO_PIN46_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN46_INT_ENA 0x0000001F +#define GPIO_PIN46_INT_ENA_M (GPIO_PIN46_INT_ENA_V << GPIO_PIN46_INT_ENA_S) +#define GPIO_PIN46_INT_ENA_V 0x0000001F +#define GPIO_PIN46_INT_ENA_S 13 + +/* GPIO_PIN46_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN46_CONFIG 0x00000003 +#define GPIO_PIN46_CONFIG_M (GPIO_PIN46_CONFIG_V << GPIO_PIN46_CONFIG_S) +#define GPIO_PIN46_CONFIG_V 0x00000003 +#define GPIO_PIN46_CONFIG_S 11 + +/* GPIO_PIN46_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN46_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN46_WAKEUP_ENABLE_M (GPIO_PIN46_WAKEUP_ENABLE_V << GPIO_PIN46_WAKEUP_ENABLE_S) +#define GPIO_PIN46_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN46_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN46_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN46_INT_TYPE 0x00000007 +#define GPIO_PIN46_INT_TYPE_M (GPIO_PIN46_INT_TYPE_V << GPIO_PIN46_INT_TYPE_S) +#define GPIO_PIN46_INT_TYPE_V 0x00000007 +#define GPIO_PIN46_INT_TYPE_S 7 + +/* GPIO_PIN46_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN46_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN46_SYNC1_BYPASS_M (GPIO_PIN46_SYNC1_BYPASS_V << GPIO_PIN46_SYNC1_BYPASS_S) +#define GPIO_PIN46_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN46_SYNC1_BYPASS_S 3 + +/* GPIO_PIN46_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN46_PAD_DRIVER (BIT(2)) +#define GPIO_PIN46_PAD_DRIVER_M (GPIO_PIN46_PAD_DRIVER_V << GPIO_PIN46_PAD_DRIVER_S) +#define GPIO_PIN46_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN46_PAD_DRIVER_S 2 + +/* GPIO_PIN46_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN46_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN46_SYNC2_BYPASS_M (GPIO_PIN46_SYNC2_BYPASS_V << GPIO_PIN46_SYNC2_BYPASS_S) +#define GPIO_PIN46_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN46_SYNC2_BYPASS_S 0 + +/* GPIO_PIN47_REG register + * Configuration for GPIO pin 47 + */ + +#define GPIO_PIN47_REG (DR_REG_GPIO_BASE + 0x130) + +/* GPIO_PIN47_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN47_INT_ENA 0x0000001F +#define GPIO_PIN47_INT_ENA_M (GPIO_PIN47_INT_ENA_V << GPIO_PIN47_INT_ENA_S) +#define GPIO_PIN47_INT_ENA_V 0x0000001F +#define GPIO_PIN47_INT_ENA_S 13 + +/* GPIO_PIN47_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN47_CONFIG 0x00000003 +#define GPIO_PIN47_CONFIG_M (GPIO_PIN47_CONFIG_V << GPIO_PIN47_CONFIG_S) +#define GPIO_PIN47_CONFIG_V 0x00000003 +#define GPIO_PIN47_CONFIG_S 11 + +/* GPIO_PIN47_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN47_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN47_WAKEUP_ENABLE_M (GPIO_PIN47_WAKEUP_ENABLE_V << GPIO_PIN47_WAKEUP_ENABLE_S) +#define GPIO_PIN47_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN47_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN47_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN47_INT_TYPE 0x00000007 +#define GPIO_PIN47_INT_TYPE_M (GPIO_PIN47_INT_TYPE_V << GPIO_PIN47_INT_TYPE_S) +#define GPIO_PIN47_INT_TYPE_V 0x00000007 +#define GPIO_PIN47_INT_TYPE_S 7 + +/* GPIO_PIN47_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN47_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN47_SYNC1_BYPASS_M (GPIO_PIN47_SYNC1_BYPASS_V << GPIO_PIN47_SYNC1_BYPASS_S) +#define GPIO_PIN47_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN47_SYNC1_BYPASS_S 3 + +/* GPIO_PIN47_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN47_PAD_DRIVER (BIT(2)) +#define GPIO_PIN47_PAD_DRIVER_M (GPIO_PIN47_PAD_DRIVER_V << GPIO_PIN47_PAD_DRIVER_S) +#define GPIO_PIN47_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN47_PAD_DRIVER_S 2 + +/* GPIO_PIN47_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN47_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN47_SYNC2_BYPASS_M (GPIO_PIN47_SYNC2_BYPASS_V << GPIO_PIN47_SYNC2_BYPASS_S) +#define GPIO_PIN47_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN47_SYNC2_BYPASS_S 0 + +/* GPIO_PIN48_REG register + * Configuration for GPIO pin 48 + */ + +#define GPIO_PIN48_REG (DR_REG_GPIO_BASE + 0x134) + +/* GPIO_PIN48_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN48_INT_ENA 0x0000001F +#define GPIO_PIN48_INT_ENA_M (GPIO_PIN48_INT_ENA_V << GPIO_PIN48_INT_ENA_S) +#define GPIO_PIN48_INT_ENA_V 0x0000001F +#define GPIO_PIN48_INT_ENA_S 13 + +/* GPIO_PIN48_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN48_CONFIG 0x00000003 +#define GPIO_PIN48_CONFIG_M (GPIO_PIN48_CONFIG_V << GPIO_PIN48_CONFIG_S) +#define GPIO_PIN48_CONFIG_V 0x00000003 +#define GPIO_PIN48_CONFIG_S 11 + +/* GPIO_PIN48_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN48_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN48_WAKEUP_ENABLE_M (GPIO_PIN48_WAKEUP_ENABLE_V << GPIO_PIN48_WAKEUP_ENABLE_S) +#define GPIO_PIN48_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN48_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN48_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN48_INT_TYPE 0x00000007 +#define GPIO_PIN48_INT_TYPE_M (GPIO_PIN48_INT_TYPE_V << GPIO_PIN48_INT_TYPE_S) +#define GPIO_PIN48_INT_TYPE_V 0x00000007 +#define GPIO_PIN48_INT_TYPE_S 7 + +/* GPIO_PIN48_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN48_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN48_SYNC1_BYPASS_M (GPIO_PIN48_SYNC1_BYPASS_V << GPIO_PIN48_SYNC1_BYPASS_S) +#define GPIO_PIN48_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN48_SYNC1_BYPASS_S 3 + +/* GPIO_PIN48_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN48_PAD_DRIVER (BIT(2)) +#define GPIO_PIN48_PAD_DRIVER_M (GPIO_PIN48_PAD_DRIVER_V << GPIO_PIN48_PAD_DRIVER_S) +#define GPIO_PIN48_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN48_PAD_DRIVER_S 2 + +/* GPIO_PIN48_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN48_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN48_SYNC2_BYPASS_M (GPIO_PIN48_SYNC2_BYPASS_V << GPIO_PIN48_SYNC2_BYPASS_S) +#define GPIO_PIN48_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN48_SYNC2_BYPASS_S 0 + +/* GPIO_PIN49_REG register + * Configuration for GPIO pin 49 + */ + +#define GPIO_PIN49_REG (DR_REG_GPIO_BASE + 0x138) + +/* GPIO_PIN49_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN49_INT_ENA 0x0000001F +#define GPIO_PIN49_INT_ENA_M (GPIO_PIN49_INT_ENA_V << GPIO_PIN49_INT_ENA_S) +#define GPIO_PIN49_INT_ENA_V 0x0000001F +#define GPIO_PIN49_INT_ENA_S 13 + +/* GPIO_PIN49_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN49_CONFIG 0x00000003 +#define GPIO_PIN49_CONFIG_M (GPIO_PIN49_CONFIG_V << GPIO_PIN49_CONFIG_S) +#define GPIO_PIN49_CONFIG_V 0x00000003 +#define GPIO_PIN49_CONFIG_S 11 + +/* GPIO_PIN49_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN49_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN49_WAKEUP_ENABLE_M (GPIO_PIN49_WAKEUP_ENABLE_V << GPIO_PIN49_WAKEUP_ENABLE_S) +#define GPIO_PIN49_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN49_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN49_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN49_INT_TYPE 0x00000007 +#define GPIO_PIN49_INT_TYPE_M (GPIO_PIN49_INT_TYPE_V << GPIO_PIN49_INT_TYPE_S) +#define GPIO_PIN49_INT_TYPE_V 0x00000007 +#define GPIO_PIN49_INT_TYPE_S 7 + +/* GPIO_PIN49_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN49_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN49_SYNC1_BYPASS_M (GPIO_PIN49_SYNC1_BYPASS_V << GPIO_PIN49_SYNC1_BYPASS_S) +#define GPIO_PIN49_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN49_SYNC1_BYPASS_S 3 + +/* GPIO_PIN49_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN49_PAD_DRIVER (BIT(2)) +#define GPIO_PIN49_PAD_DRIVER_M (GPIO_PIN49_PAD_DRIVER_V << GPIO_PIN49_PAD_DRIVER_S) +#define GPIO_PIN49_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN49_PAD_DRIVER_S 2 + +/* GPIO_PIN49_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN49_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN49_SYNC2_BYPASS_M (GPIO_PIN49_SYNC2_BYPASS_V << GPIO_PIN49_SYNC2_BYPASS_S) +#define GPIO_PIN49_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN49_SYNC2_BYPASS_S 0 + +/* GPIO_PIN50_REG register + * Configuration for GPIO pin 50 + */ + +#define GPIO_PIN50_REG (DR_REG_GPIO_BASE + 0x13c) + +/* GPIO_PIN50_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN50_INT_ENA 0x0000001F +#define GPIO_PIN50_INT_ENA_M (GPIO_PIN50_INT_ENA_V << GPIO_PIN50_INT_ENA_S) +#define GPIO_PIN50_INT_ENA_V 0x0000001F +#define GPIO_PIN50_INT_ENA_S 13 + +/* GPIO_PIN50_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN50_CONFIG 0x00000003 +#define GPIO_PIN50_CONFIG_M (GPIO_PIN50_CONFIG_V << GPIO_PIN50_CONFIG_S) +#define GPIO_PIN50_CONFIG_V 0x00000003 +#define GPIO_PIN50_CONFIG_S 11 + +/* GPIO_PIN50_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN50_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN50_WAKEUP_ENABLE_M (GPIO_PIN50_WAKEUP_ENABLE_V << GPIO_PIN50_WAKEUP_ENABLE_S) +#define GPIO_PIN50_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN50_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN50_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN50_INT_TYPE 0x00000007 +#define GPIO_PIN50_INT_TYPE_M (GPIO_PIN50_INT_TYPE_V << GPIO_PIN50_INT_TYPE_S) +#define GPIO_PIN50_INT_TYPE_V 0x00000007 +#define GPIO_PIN50_INT_TYPE_S 7 + +/* GPIO_PIN50_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN50_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN50_SYNC1_BYPASS_M (GPIO_PIN50_SYNC1_BYPASS_V << GPIO_PIN50_SYNC1_BYPASS_S) +#define GPIO_PIN50_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN50_SYNC1_BYPASS_S 3 + +/* GPIO_PIN50_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN50_PAD_DRIVER (BIT(2)) +#define GPIO_PIN50_PAD_DRIVER_M (GPIO_PIN50_PAD_DRIVER_V << GPIO_PIN50_PAD_DRIVER_S) +#define GPIO_PIN50_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN50_PAD_DRIVER_S 2 + +/* GPIO_PIN50_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN50_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN50_SYNC2_BYPASS_M (GPIO_PIN50_SYNC2_BYPASS_V << GPIO_PIN50_SYNC2_BYPASS_S) +#define GPIO_PIN50_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN50_SYNC2_BYPASS_S 0 + +/* GPIO_PIN51_REG register + * Configuration for GPIO pin 51 + */ + +#define GPIO_PIN51_REG (DR_REG_GPIO_BASE + 0x140) + +/* GPIO_PIN51_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN51_INT_ENA 0x0000001F +#define GPIO_PIN51_INT_ENA_M (GPIO_PIN51_INT_ENA_V << GPIO_PIN51_INT_ENA_S) +#define GPIO_PIN51_INT_ENA_V 0x0000001F +#define GPIO_PIN51_INT_ENA_S 13 + +/* GPIO_PIN51_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN51_CONFIG 0x00000003 +#define GPIO_PIN51_CONFIG_M (GPIO_PIN51_CONFIG_V << GPIO_PIN51_CONFIG_S) +#define GPIO_PIN51_CONFIG_V 0x00000003 +#define GPIO_PIN51_CONFIG_S 11 + +/* GPIO_PIN51_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN51_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN51_WAKEUP_ENABLE_M (GPIO_PIN51_WAKEUP_ENABLE_V << GPIO_PIN51_WAKEUP_ENABLE_S) +#define GPIO_PIN51_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN51_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN51_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN51_INT_TYPE 0x00000007 +#define GPIO_PIN51_INT_TYPE_M (GPIO_PIN51_INT_TYPE_V << GPIO_PIN51_INT_TYPE_S) +#define GPIO_PIN51_INT_TYPE_V 0x00000007 +#define GPIO_PIN51_INT_TYPE_S 7 + +/* GPIO_PIN51_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN51_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN51_SYNC1_BYPASS_M (GPIO_PIN51_SYNC1_BYPASS_V << GPIO_PIN51_SYNC1_BYPASS_S) +#define GPIO_PIN51_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN51_SYNC1_BYPASS_S 3 + +/* GPIO_PIN51_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN51_PAD_DRIVER (BIT(2)) +#define GPIO_PIN51_PAD_DRIVER_M (GPIO_PIN51_PAD_DRIVER_V << GPIO_PIN51_PAD_DRIVER_S) +#define GPIO_PIN51_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN51_PAD_DRIVER_S 2 + +/* GPIO_PIN51_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN51_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN51_SYNC2_BYPASS_M (GPIO_PIN51_SYNC2_BYPASS_V << GPIO_PIN51_SYNC2_BYPASS_S) +#define GPIO_PIN51_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN51_SYNC2_BYPASS_S 0 + +/* GPIO_PIN52_REG register + * Configuration for GPIO pin 52 + */ + +#define GPIO_PIN52_REG (DR_REG_GPIO_BASE + 0x144) + +/* GPIO_PIN52_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN52_INT_ENA 0x0000001F +#define GPIO_PIN52_INT_ENA_M (GPIO_PIN52_INT_ENA_V << GPIO_PIN52_INT_ENA_S) +#define GPIO_PIN52_INT_ENA_V 0x0000001F +#define GPIO_PIN52_INT_ENA_S 13 + +/* GPIO_PIN52_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN52_CONFIG 0x00000003 +#define GPIO_PIN52_CONFIG_M (GPIO_PIN52_CONFIG_V << GPIO_PIN52_CONFIG_S) +#define GPIO_PIN52_CONFIG_V 0x00000003 +#define GPIO_PIN52_CONFIG_S 11 + +/* GPIO_PIN52_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN52_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN52_WAKEUP_ENABLE_M (GPIO_PIN52_WAKEUP_ENABLE_V << GPIO_PIN52_WAKEUP_ENABLE_S) +#define GPIO_PIN52_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN52_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN52_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN52_INT_TYPE 0x00000007 +#define GPIO_PIN52_INT_TYPE_M (GPIO_PIN52_INT_TYPE_V << GPIO_PIN52_INT_TYPE_S) +#define GPIO_PIN52_INT_TYPE_V 0x00000007 +#define GPIO_PIN52_INT_TYPE_S 7 + +/* GPIO_PIN52_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN52_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN52_SYNC1_BYPASS_M (GPIO_PIN52_SYNC1_BYPASS_V << GPIO_PIN52_SYNC1_BYPASS_S) +#define GPIO_PIN52_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN52_SYNC1_BYPASS_S 3 + +/* GPIO_PIN52_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN52_PAD_DRIVER (BIT(2)) +#define GPIO_PIN52_PAD_DRIVER_M (GPIO_PIN52_PAD_DRIVER_V << GPIO_PIN52_PAD_DRIVER_S) +#define GPIO_PIN52_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN52_PAD_DRIVER_S 2 + +/* GPIO_PIN52_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN52_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN52_SYNC2_BYPASS_M (GPIO_PIN52_SYNC2_BYPASS_V << GPIO_PIN52_SYNC2_BYPASS_S) +#define GPIO_PIN52_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN52_SYNC2_BYPASS_S 0 + +/* GPIO_PIN53_REG register + * Configuration for GPIO pin 53 + */ + +#define GPIO_PIN53_REG (DR_REG_GPIO_BASE + 0x148) + +/* GPIO_PIN53_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU + * non-maskable interrupt enabled. + */ + +#define GPIO_PIN53_INT_ENA 0x0000001F +#define GPIO_PIN53_INT_ENA_M (GPIO_PIN53_INT_ENA_V << GPIO_PIN53_INT_ENA_S) +#define GPIO_PIN53_INT_ENA_V 0x0000001F +#define GPIO_PIN53_INT_ENA_S 13 + +/* GPIO_PIN53_CONFIG : R/W; bitpos: [12:11]; default: 0; + * Reserved + */ + +#define GPIO_PIN53_CONFIG 0x00000003 +#define GPIO_PIN53_CONFIG_M (GPIO_PIN53_CONFIG_V << GPIO_PIN53_CONFIG_S) +#define GPIO_PIN53_CONFIG_V 0x00000003 +#define GPIO_PIN53_CONFIG_S 11 + +/* GPIO_PIN53_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable bit, only wakes up the CPU from Light-sleep. + */ + +#define GPIO_PIN53_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN53_WAKEUP_ENABLE_M (GPIO_PIN53_WAKEUP_ENABLE_V << GPIO_PIN53_WAKEUP_ENABLE_S) +#define GPIO_PIN53_WAKEUP_ENABLE_V 0x00000001 +#define GPIO_PIN53_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN53_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. (R/W) + */ + +#define GPIO_PIN53_INT_TYPE 0x00000007 +#define GPIO_PIN53_INT_TYPE_M (GPIO_PIN53_INT_TYPE_V << GPIO_PIN53_INT_TYPE_S) +#define GPIO_PIN53_INT_TYPE_V 0x00000007 +#define GPIO_PIN53_INT_TYPE_S 7 + +/* GPIO_PIN53_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * For the first stage synchronization, GPIO input data can be synchro- + * nized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN53_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN53_SYNC1_BYPASS_M (GPIO_PIN53_SYNC1_BYPASS_V << GPIO_PIN53_SYNC1_BYPASS_S) +#define GPIO_PIN53_SYNC1_BYPASS_V 0x00000003 +#define GPIO_PIN53_SYNC1_BYPASS_S 3 + +/* GPIO_PIN53_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain output.. + */ + +#define GPIO_PIN53_PAD_DRIVER (BIT(2)) +#define GPIO_PIN53_PAD_DRIVER_M (GPIO_PIN53_PAD_DRIVER_V << GPIO_PIN53_PAD_DRIVER_S) +#define GPIO_PIN53_PAD_DRIVER_V 0x00000001 +#define GPIO_PIN53_PAD_DRIVER_S 2 + +/* GPIO_PIN53_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * For the second stage synchronization, GPIO input data can be syn- + * chronized on either edge of the APB clock. 0: no synchronization; 1: + * synchronized on falling edge; 2 and 3: synchronized on rising edge. + */ + +#define GPIO_PIN53_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN53_SYNC2_BYPASS_M (GPIO_PIN53_SYNC2_BYPASS_V << GPIO_PIN53_SYNC2_BYPASS_S) +#define GPIO_PIN53_SYNC2_BYPASS_V 0x00000003 +#define GPIO_PIN53_SYNC2_BYPASS_S 0 + +/* GPIO_STATUS_NEXT_REG register + * GPIO0 ~ 31 interrupt source register + */ + +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c) + +/* GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0; + * Interrupt source signal of GPIO0 ~ 31, could be rising edge interrupt, + * falling edge interrupt, level sensitive interrupt and any edge interrupt. + */ + +#define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFF +#define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) +#define GPIO_STATUS_INTERRUPT_NEXT_V 0xFFFFFFFF +#define GPIO_STATUS_INTERRUPT_NEXT_S 0 + +/* GPIO_STATUS_NEXT1_REG register + * GPIO32 ~ 53 interrupt source register + */ + +#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x150) + +/* GPIO_STATUS1_INTERRUPT_NEXT : RO; bitpos: [21:0]; default: 0; + * Interrupt source signal of GPIO32 ~ 53. + */ + +#define GPIO_STATUS1_INTERRUPT_NEXT 0x003FFFFF +#define GPIO_STATUS1_INTERRUPT_NEXT_M (GPIO_STATUS1_INTERRUPT_NEXT_V << GPIO_STATUS1_INTERRUPT_NEXT_S) +#define GPIO_STATUS1_INTERRUPT_NEXT_V 0x003FFFFF +#define GPIO_STATUS1_INTERRUPT_NEXT_S 0 + +/* GPIO_FUNC0_IN_SEL_CFG_REG register + * Peripheral function 0 input selection register + */ + +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) + +/* GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) +#define GPIO_SIG0_IN_SEL_V 0x00000001 +#define GPIO_SIG0_IN_SEL_S 7 + +/* GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) +#define GPIO_FUNC0_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC0_IN_INV_SEL_S 6 + +/* GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC0_IN_SEL 0x0000003F +#define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) +#define GPIO_FUNC0_IN_SEL_V 0x0000003F +#define GPIO_FUNC0_IN_SEL_S 0 + +/* GPIO_FUNC1_IN_SEL_CFG_REG register + * Peripheral function 1 input selection register + */ + +#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158) + +/* GPIO_SIG1_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG1_IN_SEL (BIT(7)) +#define GPIO_SIG1_IN_SEL_M (GPIO_SIG1_IN_SEL_V << GPIO_SIG1_IN_SEL_S) +#define GPIO_SIG1_IN_SEL_V 0x00000001 +#define GPIO_SIG1_IN_SEL_S 7 + +/* GPIO_FUNC1_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC1_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC1_IN_INV_SEL_M (GPIO_FUNC1_IN_INV_SEL_V << GPIO_FUNC1_IN_INV_SEL_S) +#define GPIO_FUNC1_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC1_IN_INV_SEL_S 6 + +/* GPIO_FUNC1_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC1_IN_SEL 0x0000003F +#define GPIO_FUNC1_IN_SEL_M (GPIO_FUNC1_IN_SEL_V << GPIO_FUNC1_IN_SEL_S) +#define GPIO_FUNC1_IN_SEL_V 0x0000003F +#define GPIO_FUNC1_IN_SEL_S 0 + +/* GPIO_FUNC2_IN_SEL_CFG_REG register + * Peripheral function 2 input selection register + */ + +#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c) + +/* GPIO_SIG2_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG2_IN_SEL (BIT(7)) +#define GPIO_SIG2_IN_SEL_M (GPIO_SIG2_IN_SEL_V << GPIO_SIG2_IN_SEL_S) +#define GPIO_SIG2_IN_SEL_V 0x00000001 +#define GPIO_SIG2_IN_SEL_S 7 + +/* GPIO_FUNC2_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC2_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC2_IN_INV_SEL_M (GPIO_FUNC2_IN_INV_SEL_V << GPIO_FUNC2_IN_INV_SEL_S) +#define GPIO_FUNC2_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC2_IN_INV_SEL_S 6 + +/* GPIO_FUNC2_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC2_IN_SEL 0x0000003F +#define GPIO_FUNC2_IN_SEL_M (GPIO_FUNC2_IN_SEL_V << GPIO_FUNC2_IN_SEL_S) +#define GPIO_FUNC2_IN_SEL_V 0x0000003F +#define GPIO_FUNC2_IN_SEL_S 0 + +/* GPIO_FUNC3_IN_SEL_CFG_REG register + * Peripheral function 3 input selection register + */ + +#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160) + +/* GPIO_SIG3_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG3_IN_SEL (BIT(7)) +#define GPIO_SIG3_IN_SEL_M (GPIO_SIG3_IN_SEL_V << GPIO_SIG3_IN_SEL_S) +#define GPIO_SIG3_IN_SEL_V 0x00000001 +#define GPIO_SIG3_IN_SEL_S 7 + +/* GPIO_FUNC3_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC3_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC3_IN_INV_SEL_M (GPIO_FUNC3_IN_INV_SEL_V << GPIO_FUNC3_IN_INV_SEL_S) +#define GPIO_FUNC3_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC3_IN_INV_SEL_S 6 + +/* GPIO_FUNC3_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC3_IN_SEL 0x0000003F +#define GPIO_FUNC3_IN_SEL_M (GPIO_FUNC3_IN_SEL_V << GPIO_FUNC3_IN_SEL_S) +#define GPIO_FUNC3_IN_SEL_V 0x0000003F +#define GPIO_FUNC3_IN_SEL_S 0 + +/* GPIO_FUNC4_IN_SEL_CFG_REG register + * Peripheral function 4 input selection register + */ + +#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164) + +/* GPIO_SIG4_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG4_IN_SEL (BIT(7)) +#define GPIO_SIG4_IN_SEL_M (GPIO_SIG4_IN_SEL_V << GPIO_SIG4_IN_SEL_S) +#define GPIO_SIG4_IN_SEL_V 0x00000001 +#define GPIO_SIG4_IN_SEL_S 7 + +/* GPIO_FUNC4_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC4_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC4_IN_INV_SEL_M (GPIO_FUNC4_IN_INV_SEL_V << GPIO_FUNC4_IN_INV_SEL_S) +#define GPIO_FUNC4_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC4_IN_INV_SEL_S 6 + +/* GPIO_FUNC4_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC4_IN_SEL 0x0000003F +#define GPIO_FUNC4_IN_SEL_M (GPIO_FUNC4_IN_SEL_V << GPIO_FUNC4_IN_SEL_S) +#define GPIO_FUNC4_IN_SEL_V 0x0000003F +#define GPIO_FUNC4_IN_SEL_S 0 + +/* GPIO_FUNC5_IN_SEL_CFG_REG register + * Peripheral function 5 input selection register + */ + +#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168) + +/* GPIO_SIG5_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG5_IN_SEL (BIT(7)) +#define GPIO_SIG5_IN_SEL_M (GPIO_SIG5_IN_SEL_V << GPIO_SIG5_IN_SEL_S) +#define GPIO_SIG5_IN_SEL_V 0x00000001 +#define GPIO_SIG5_IN_SEL_S 7 + +/* GPIO_FUNC5_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC5_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC5_IN_INV_SEL_M (GPIO_FUNC5_IN_INV_SEL_V << GPIO_FUNC5_IN_INV_SEL_S) +#define GPIO_FUNC5_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC5_IN_INV_SEL_S 6 + +/* GPIO_FUNC5_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC5_IN_SEL 0x0000003F +#define GPIO_FUNC5_IN_SEL_M (GPIO_FUNC5_IN_SEL_V << GPIO_FUNC5_IN_SEL_S) +#define GPIO_FUNC5_IN_SEL_V 0x0000003F +#define GPIO_FUNC5_IN_SEL_S 0 + +/* GPIO_FUNC6_IN_SEL_CFG_REG register + * Peripheral function 6 input selection register + */ + +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c) + +/* GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) +#define GPIO_SIG6_IN_SEL_V 0x00000001 +#define GPIO_SIG6_IN_SEL_S 7 + +/* GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) +#define GPIO_FUNC6_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC6_IN_INV_SEL_S 6 + +/* GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC6_IN_SEL 0x0000003F +#define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) +#define GPIO_FUNC6_IN_SEL_V 0x0000003F +#define GPIO_FUNC6_IN_SEL_S 0 + +/* GPIO_FUNC7_IN_SEL_CFG_REG register + * Peripheral function 7 input selection register + */ + +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) + +/* GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) +#define GPIO_SIG7_IN_SEL_V 0x00000001 +#define GPIO_SIG7_IN_SEL_S 7 + +/* GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) +#define GPIO_FUNC7_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC7_IN_INV_SEL_S 6 + +/* GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC7_IN_SEL 0x0000003F +#define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) +#define GPIO_FUNC7_IN_SEL_V 0x0000003F +#define GPIO_FUNC7_IN_SEL_S 0 + +/* GPIO_FUNC8_IN_SEL_CFG_REG register + * Peripheral function 8 input selection register + */ + +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) + +/* GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) +#define GPIO_SIG8_IN_SEL_V 0x00000001 +#define GPIO_SIG8_IN_SEL_S 7 + +/* GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) +#define GPIO_FUNC8_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC8_IN_INV_SEL_S 6 + +/* GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC8_IN_SEL 0x0000003F +#define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) +#define GPIO_FUNC8_IN_SEL_V 0x0000003F +#define GPIO_FUNC8_IN_SEL_S 0 + +/* GPIO_FUNC9_IN_SEL_CFG_REG register + * Peripheral function 9 input selection register + */ + +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) + +/* GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) +#define GPIO_SIG9_IN_SEL_V 0x00000001 +#define GPIO_SIG9_IN_SEL_S 7 + +/* GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) +#define GPIO_FUNC9_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC9_IN_INV_SEL_S 6 + +/* GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC9_IN_SEL 0x0000003F +#define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) +#define GPIO_FUNC9_IN_SEL_V 0x0000003F +#define GPIO_FUNC9_IN_SEL_S 0 + +/* GPIO_FUNC10_IN_SEL_CFG_REG register + * Peripheral function 10 input selection register + */ + +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c) + +/* GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) +#define GPIO_SIG10_IN_SEL_V 0x00000001 +#define GPIO_SIG10_IN_SEL_S 7 + +/* GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) +#define GPIO_FUNC10_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC10_IN_INV_SEL_S 6 + +/* GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC10_IN_SEL 0x0000003F +#define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) +#define GPIO_FUNC10_IN_SEL_V 0x0000003F +#define GPIO_FUNC10_IN_SEL_S 0 + +/* GPIO_FUNC11_IN_SEL_CFG_REG register + * Peripheral function 11 input selection register + */ + +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) + +/* GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) +#define GPIO_SIG11_IN_SEL_V 0x00000001 +#define GPIO_SIG11_IN_SEL_S 7 + +/* GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) +#define GPIO_FUNC11_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC11_IN_INV_SEL_S 6 + +/* GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC11_IN_SEL 0x0000003F +#define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) +#define GPIO_FUNC11_IN_SEL_V 0x0000003F +#define GPIO_FUNC11_IN_SEL_S 0 + +/* GPIO_FUNC12_IN_SEL_CFG_REG register + * Peripheral function 12 input selection register + */ + +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) + +/* GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) +#define GPIO_SIG12_IN_SEL_V 0x00000001 +#define GPIO_SIG12_IN_SEL_S 7 + +/* GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) +#define GPIO_FUNC12_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC12_IN_INV_SEL_S 6 + +/* GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC12_IN_SEL 0x0000003F +#define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) +#define GPIO_FUNC12_IN_SEL_V 0x0000003F +#define GPIO_FUNC12_IN_SEL_S 0 + +/* GPIO_FUNC13_IN_SEL_CFG_REG register + * Peripheral function 13 input selection register + */ + +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) + +/* GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) +#define GPIO_SIG13_IN_SEL_V 0x00000001 +#define GPIO_SIG13_IN_SEL_S 7 + +/* GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) +#define GPIO_FUNC13_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC13_IN_INV_SEL_S 6 + +/* GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC13_IN_SEL 0x0000003F +#define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) +#define GPIO_FUNC13_IN_SEL_V 0x0000003F +#define GPIO_FUNC13_IN_SEL_S 0 + +/* GPIO_FUNC14_IN_SEL_CFG_REG register + * Peripheral function 14 input selection register + */ + +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c) + +/* GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) +#define GPIO_SIG14_IN_SEL_V 0x00000001 +#define GPIO_SIG14_IN_SEL_S 7 + +/* GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) +#define GPIO_FUNC14_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC14_IN_INV_SEL_S 6 + +/* GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC14_IN_SEL 0x0000003F +#define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) +#define GPIO_FUNC14_IN_SEL_V 0x0000003F +#define GPIO_FUNC14_IN_SEL_S 0 + +/* GPIO_FUNC15_IN_SEL_CFG_REG register + * Peripheral function 15 input selection register + */ + +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) + +/* GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) +#define GPIO_SIG15_IN_SEL_V 0x00000001 +#define GPIO_SIG15_IN_SEL_S 7 + +/* GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) +#define GPIO_FUNC15_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC15_IN_INV_SEL_S 6 + +/* GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC15_IN_SEL 0x0000003F +#define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) +#define GPIO_FUNC15_IN_SEL_V 0x0000003F +#define GPIO_FUNC15_IN_SEL_S 0 + +/* GPIO_FUNC16_IN_SEL_CFG_REG register + * Peripheral function 16 input selection register + */ + +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) + +/* GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) +#define GPIO_SIG16_IN_SEL_V 0x00000001 +#define GPIO_SIG16_IN_SEL_S 7 + +/* GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) +#define GPIO_FUNC16_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC16_IN_INV_SEL_S 6 + +/* GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC16_IN_SEL 0x0000003F +#define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) +#define GPIO_FUNC16_IN_SEL_V 0x0000003F +#define GPIO_FUNC16_IN_SEL_S 0 + +/* GPIO_FUNC17_IN_SEL_CFG_REG register + * Peripheral function 17 input selection register + */ + +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) + +/* GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) +#define GPIO_SIG17_IN_SEL_V 0x00000001 +#define GPIO_SIG17_IN_SEL_S 7 + +/* GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) +#define GPIO_FUNC17_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC17_IN_INV_SEL_S 6 + +/* GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC17_IN_SEL 0x0000003F +#define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) +#define GPIO_FUNC17_IN_SEL_V 0x0000003F +#define GPIO_FUNC17_IN_SEL_S 0 + +/* GPIO_FUNC18_IN_SEL_CFG_REG register + * Peripheral function 18 input selection register + */ + +#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19c) + +/* GPIO_SIG18_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG18_IN_SEL (BIT(7)) +#define GPIO_SIG18_IN_SEL_M (GPIO_SIG18_IN_SEL_V << GPIO_SIG18_IN_SEL_S) +#define GPIO_SIG18_IN_SEL_V 0x00000001 +#define GPIO_SIG18_IN_SEL_S 7 + +/* GPIO_FUNC18_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC18_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC18_IN_INV_SEL_M (GPIO_FUNC18_IN_INV_SEL_V << GPIO_FUNC18_IN_INV_SEL_S) +#define GPIO_FUNC18_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC18_IN_INV_SEL_S 6 + +/* GPIO_FUNC18_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC18_IN_SEL 0x0000003F +#define GPIO_FUNC18_IN_SEL_M (GPIO_FUNC18_IN_SEL_V << GPIO_FUNC18_IN_SEL_S) +#define GPIO_FUNC18_IN_SEL_V 0x0000003F +#define GPIO_FUNC18_IN_SEL_S 0 + +/* GPIO_FUNC19_IN_SEL_CFG_REG register + * Peripheral function 19 input selection register + */ + +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0) + +/* GPIO_SIG19_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG19_IN_SEL (BIT(7)) +#define GPIO_SIG19_IN_SEL_M (GPIO_SIG19_IN_SEL_V << GPIO_SIG19_IN_SEL_S) +#define GPIO_SIG19_IN_SEL_V 0x00000001 +#define GPIO_SIG19_IN_SEL_S 7 + +/* GPIO_FUNC19_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_M (GPIO_FUNC19_IN_INV_SEL_V << GPIO_FUNC19_IN_INV_SEL_S) +#define GPIO_FUNC19_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC19_IN_INV_SEL_S 6 + +/* GPIO_FUNC19_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC19_IN_SEL 0x0000003F +#define GPIO_FUNC19_IN_SEL_M (GPIO_FUNC19_IN_SEL_V << GPIO_FUNC19_IN_SEL_S) +#define GPIO_FUNC19_IN_SEL_V 0x0000003F +#define GPIO_FUNC19_IN_SEL_S 0 + +/* GPIO_FUNC20_IN_SEL_CFG_REG register + * Peripheral function 20 input selection register + */ + +#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a4) + +/* GPIO_SIG20_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG20_IN_SEL (BIT(7)) +#define GPIO_SIG20_IN_SEL_M (GPIO_SIG20_IN_SEL_V << GPIO_SIG20_IN_SEL_S) +#define GPIO_SIG20_IN_SEL_V 0x00000001 +#define GPIO_SIG20_IN_SEL_S 7 + +/* GPIO_FUNC20_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC20_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC20_IN_INV_SEL_M (GPIO_FUNC20_IN_INV_SEL_V << GPIO_FUNC20_IN_INV_SEL_S) +#define GPIO_FUNC20_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC20_IN_INV_SEL_S 6 + +/* GPIO_FUNC20_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC20_IN_SEL 0x0000003F +#define GPIO_FUNC20_IN_SEL_M (GPIO_FUNC20_IN_SEL_V << GPIO_FUNC20_IN_SEL_S) +#define GPIO_FUNC20_IN_SEL_V 0x0000003F +#define GPIO_FUNC20_IN_SEL_S 0 + +/* GPIO_FUNC21_IN_SEL_CFG_REG register + * Peripheral function 21 input selection register + */ + +#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8) + +/* GPIO_SIG21_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG21_IN_SEL (BIT(7)) +#define GPIO_SIG21_IN_SEL_M (GPIO_SIG21_IN_SEL_V << GPIO_SIG21_IN_SEL_S) +#define GPIO_SIG21_IN_SEL_V 0x00000001 +#define GPIO_SIG21_IN_SEL_S 7 + +/* GPIO_FUNC21_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC21_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL_M (GPIO_FUNC21_IN_INV_SEL_V << GPIO_FUNC21_IN_INV_SEL_S) +#define GPIO_FUNC21_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC21_IN_INV_SEL_S 6 + +/* GPIO_FUNC21_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC21_IN_SEL 0x0000003F +#define GPIO_FUNC21_IN_SEL_M (GPIO_FUNC21_IN_SEL_V << GPIO_FUNC21_IN_SEL_S) +#define GPIO_FUNC21_IN_SEL_V 0x0000003F +#define GPIO_FUNC21_IN_SEL_S 0 + +/* GPIO_FUNC22_IN_SEL_CFG_REG register + * Peripheral function 22 input selection register + */ + +#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac) + +/* GPIO_SIG22_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG22_IN_SEL (BIT(7)) +#define GPIO_SIG22_IN_SEL_M (GPIO_SIG22_IN_SEL_V << GPIO_SIG22_IN_SEL_S) +#define GPIO_SIG22_IN_SEL_V 0x00000001 +#define GPIO_SIG22_IN_SEL_S 7 + +/* GPIO_FUNC22_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC22_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL_M (GPIO_FUNC22_IN_INV_SEL_V << GPIO_FUNC22_IN_INV_SEL_S) +#define GPIO_FUNC22_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC22_IN_INV_SEL_S 6 + +/* GPIO_FUNC22_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC22_IN_SEL 0x0000003F +#define GPIO_FUNC22_IN_SEL_M (GPIO_FUNC22_IN_SEL_V << GPIO_FUNC22_IN_SEL_S) +#define GPIO_FUNC22_IN_SEL_V 0x0000003F +#define GPIO_FUNC22_IN_SEL_S 0 + +/* GPIO_FUNC23_IN_SEL_CFG_REG register + * Peripheral function 23 input selection register + */ + +#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0) + +/* GPIO_SIG23_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG23_IN_SEL (BIT(7)) +#define GPIO_SIG23_IN_SEL_M (GPIO_SIG23_IN_SEL_V << GPIO_SIG23_IN_SEL_S) +#define GPIO_SIG23_IN_SEL_V 0x00000001 +#define GPIO_SIG23_IN_SEL_S 7 + +/* GPIO_FUNC23_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC23_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL_M (GPIO_FUNC23_IN_INV_SEL_V << GPIO_FUNC23_IN_INV_SEL_S) +#define GPIO_FUNC23_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC23_IN_INV_SEL_S 6 + +/* GPIO_FUNC23_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC23_IN_SEL 0x0000003F +#define GPIO_FUNC23_IN_SEL_M (GPIO_FUNC23_IN_SEL_V << GPIO_FUNC23_IN_SEL_S) +#define GPIO_FUNC23_IN_SEL_V 0x0000003F +#define GPIO_FUNC23_IN_SEL_S 0 + +/* GPIO_FUNC24_IN_SEL_CFG_REG register + * Peripheral function 24 input selection register + */ + +#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4) + +/* GPIO_SIG24_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG24_IN_SEL (BIT(7)) +#define GPIO_SIG24_IN_SEL_M (GPIO_SIG24_IN_SEL_V << GPIO_SIG24_IN_SEL_S) +#define GPIO_SIG24_IN_SEL_V 0x00000001 +#define GPIO_SIG24_IN_SEL_S 7 + +/* GPIO_FUNC24_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC24_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL_M (GPIO_FUNC24_IN_INV_SEL_V << GPIO_FUNC24_IN_INV_SEL_S) +#define GPIO_FUNC24_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC24_IN_INV_SEL_S 6 + +/* GPIO_FUNC24_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC24_IN_SEL 0x0000003F +#define GPIO_FUNC24_IN_SEL_M (GPIO_FUNC24_IN_SEL_V << GPIO_FUNC24_IN_SEL_S) +#define GPIO_FUNC24_IN_SEL_V 0x0000003F +#define GPIO_FUNC24_IN_SEL_S 0 + +/* GPIO_FUNC25_IN_SEL_CFG_REG register + * Peripheral function 25 input selection register + */ + +#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b8) + +/* GPIO_SIG25_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG25_IN_SEL (BIT(7)) +#define GPIO_SIG25_IN_SEL_M (GPIO_SIG25_IN_SEL_V << GPIO_SIG25_IN_SEL_S) +#define GPIO_SIG25_IN_SEL_V 0x00000001 +#define GPIO_SIG25_IN_SEL_S 7 + +/* GPIO_FUNC25_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC25_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC25_IN_INV_SEL_M (GPIO_FUNC25_IN_INV_SEL_V << GPIO_FUNC25_IN_INV_SEL_S) +#define GPIO_FUNC25_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC25_IN_INV_SEL_S 6 + +/* GPIO_FUNC25_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC25_IN_SEL 0x0000003F +#define GPIO_FUNC25_IN_SEL_M (GPIO_FUNC25_IN_SEL_V << GPIO_FUNC25_IN_SEL_S) +#define GPIO_FUNC25_IN_SEL_V 0x0000003F +#define GPIO_FUNC25_IN_SEL_S 0 + +/* GPIO_FUNC26_IN_SEL_CFG_REG register + * Peripheral function 26 input selection register + */ + +#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1bc) + +/* GPIO_SIG26_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG26_IN_SEL (BIT(7)) +#define GPIO_SIG26_IN_SEL_M (GPIO_SIG26_IN_SEL_V << GPIO_SIG26_IN_SEL_S) +#define GPIO_SIG26_IN_SEL_V 0x00000001 +#define GPIO_SIG26_IN_SEL_S 7 + +/* GPIO_FUNC26_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC26_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC26_IN_INV_SEL_M (GPIO_FUNC26_IN_INV_SEL_V << GPIO_FUNC26_IN_INV_SEL_S) +#define GPIO_FUNC26_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC26_IN_INV_SEL_S 6 + +/* GPIO_FUNC26_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC26_IN_SEL 0x0000003F +#define GPIO_FUNC26_IN_SEL_M (GPIO_FUNC26_IN_SEL_V << GPIO_FUNC26_IN_SEL_S) +#define GPIO_FUNC26_IN_SEL_V 0x0000003F +#define GPIO_FUNC26_IN_SEL_S 0 + +/* GPIO_FUNC27_IN_SEL_CFG_REG register + * Peripheral function 27 input selection register + */ + +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c0) + +/* GPIO_SIG27_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG27_IN_SEL (BIT(7)) +#define GPIO_SIG27_IN_SEL_M (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S) +#define GPIO_SIG27_IN_SEL_V 0x00000001 +#define GPIO_SIG27_IN_SEL_S 7 + +/* GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL_M (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S) +#define GPIO_FUNC27_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC27_IN_INV_SEL_S 6 + +/* GPIO_FUNC27_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC27_IN_SEL 0x0000003F +#define GPIO_FUNC27_IN_SEL_M (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S) +#define GPIO_FUNC27_IN_SEL_V 0x0000003F +#define GPIO_FUNC27_IN_SEL_S 0 + +/* GPIO_FUNC28_IN_SEL_CFG_REG register + * Peripheral function 28 input selection register + */ + +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4) + +/* GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) +#define GPIO_SIG28_IN_SEL_V 0x00000001 +#define GPIO_SIG28_IN_SEL_S 7 + +/* GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) +#define GPIO_FUNC28_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC28_IN_INV_SEL_S 6 + +/* GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC28_IN_SEL 0x0000003F +#define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) +#define GPIO_FUNC28_IN_SEL_V 0x0000003F +#define GPIO_FUNC28_IN_SEL_S 0 + +/* GPIO_FUNC29_IN_SEL_CFG_REG register + * Peripheral function 29 input selection register + */ + +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8) + +/* GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) +#define GPIO_SIG29_IN_SEL_V 0x00000001 +#define GPIO_SIG29_IN_SEL_S 7 + +/* GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) +#define GPIO_FUNC29_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC29_IN_INV_SEL_S 6 + +/* GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC29_IN_SEL 0x0000003F +#define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) +#define GPIO_FUNC29_IN_SEL_V 0x0000003F +#define GPIO_FUNC29_IN_SEL_S 0 + +/* GPIO_FUNC30_IN_SEL_CFG_REG register + * Peripheral function 30 input selection register + */ + +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc) + +/* GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) +#define GPIO_SIG30_IN_SEL_V 0x00000001 +#define GPIO_SIG30_IN_SEL_S 7 + +/* GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) +#define GPIO_FUNC30_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC30_IN_INV_SEL_S 6 + +/* GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC30_IN_SEL 0x0000003F +#define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) +#define GPIO_FUNC30_IN_SEL_V 0x0000003F +#define GPIO_FUNC30_IN_SEL_S 0 + +/* GPIO_FUNC31_IN_SEL_CFG_REG register + * Peripheral function 31 input selection register + */ + +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0) + +/* GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) +#define GPIO_SIG31_IN_SEL_V 0x00000001 +#define GPIO_SIG31_IN_SEL_S 7 + +/* GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) +#define GPIO_FUNC31_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC31_IN_INV_SEL_S 6 + +/* GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC31_IN_SEL 0x0000003F +#define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) +#define GPIO_FUNC31_IN_SEL_V 0x0000003F +#define GPIO_FUNC31_IN_SEL_S 0 + +/* GPIO_FUNC32_IN_SEL_CFG_REG register + * Peripheral function 32 input selection register + */ + +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4) + +/* GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) +#define GPIO_SIG32_IN_SEL_V 0x00000001 +#define GPIO_SIG32_IN_SEL_S 7 + +/* GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) +#define GPIO_FUNC32_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC32_IN_INV_SEL_S 6 + +/* GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC32_IN_SEL 0x0000003F +#define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) +#define GPIO_FUNC32_IN_SEL_V 0x0000003F +#define GPIO_FUNC32_IN_SEL_S 0 + +/* GPIO_FUNC33_IN_SEL_CFG_REG register + * Peripheral function 33 input selection register + */ + +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8) + +/* GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) +#define GPIO_SIG33_IN_SEL_V 0x00000001 +#define GPIO_SIG33_IN_SEL_S 7 + +/* GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) +#define GPIO_FUNC33_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC33_IN_INV_SEL_S 6 + +/* GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC33_IN_SEL 0x0000003F +#define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) +#define GPIO_FUNC33_IN_SEL_V 0x0000003F +#define GPIO_FUNC33_IN_SEL_S 0 + +/* GPIO_FUNC34_IN_SEL_CFG_REG register + * Peripheral function 34 input selection register + */ + +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc) + +/* GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) +#define GPIO_SIG34_IN_SEL_V 0x00000001 +#define GPIO_SIG34_IN_SEL_S 7 + +/* GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) +#define GPIO_FUNC34_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC34_IN_INV_SEL_S 6 + +/* GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC34_IN_SEL 0x0000003F +#define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) +#define GPIO_FUNC34_IN_SEL_V 0x0000003F +#define GPIO_FUNC34_IN_SEL_S 0 + +/* GPIO_FUNC35_IN_SEL_CFG_REG register + * Peripheral function 35 input selection register + */ + +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0) + +/* GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) +#define GPIO_SIG35_IN_SEL_V 0x00000001 +#define GPIO_SIG35_IN_SEL_S 7 + +/* GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) +#define GPIO_FUNC35_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC35_IN_INV_SEL_S 6 + +/* GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC35_IN_SEL 0x0000003F +#define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) +#define GPIO_FUNC35_IN_SEL_V 0x0000003F +#define GPIO_FUNC35_IN_SEL_S 0 + +/* GPIO_FUNC36_IN_SEL_CFG_REG register + * Peripheral function 36 input selection register + */ + +#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e4) + +/* GPIO_SIG36_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG36_IN_SEL (BIT(7)) +#define GPIO_SIG36_IN_SEL_M (GPIO_SIG36_IN_SEL_V << GPIO_SIG36_IN_SEL_S) +#define GPIO_SIG36_IN_SEL_V 0x00000001 +#define GPIO_SIG36_IN_SEL_S 7 + +/* GPIO_FUNC36_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC36_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC36_IN_INV_SEL_M (GPIO_FUNC36_IN_INV_SEL_V << GPIO_FUNC36_IN_INV_SEL_S) +#define GPIO_FUNC36_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC36_IN_INV_SEL_S 6 + +/* GPIO_FUNC36_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC36_IN_SEL 0x0000003F +#define GPIO_FUNC36_IN_SEL_M (GPIO_FUNC36_IN_SEL_V << GPIO_FUNC36_IN_SEL_S) +#define GPIO_FUNC36_IN_SEL_V 0x0000003F +#define GPIO_FUNC36_IN_SEL_S 0 + +/* GPIO_FUNC37_IN_SEL_CFG_REG register + * Peripheral function 37 input selection register + */ + +#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e8) + +/* GPIO_SIG37_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG37_IN_SEL (BIT(7)) +#define GPIO_SIG37_IN_SEL_M (GPIO_SIG37_IN_SEL_V << GPIO_SIG37_IN_SEL_S) +#define GPIO_SIG37_IN_SEL_V 0x00000001 +#define GPIO_SIG37_IN_SEL_S 7 + +/* GPIO_FUNC37_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC37_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC37_IN_INV_SEL_M (GPIO_FUNC37_IN_INV_SEL_V << GPIO_FUNC37_IN_INV_SEL_S) +#define GPIO_FUNC37_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC37_IN_INV_SEL_S 6 + +/* GPIO_FUNC37_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC37_IN_SEL 0x0000003F +#define GPIO_FUNC37_IN_SEL_M (GPIO_FUNC37_IN_SEL_V << GPIO_FUNC37_IN_SEL_S) +#define GPIO_FUNC37_IN_SEL_V 0x0000003F +#define GPIO_FUNC37_IN_SEL_S 0 + +/* GPIO_FUNC38_IN_SEL_CFG_REG register + * Peripheral function 38 input selection register + */ + +#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ec) + +/* GPIO_SIG38_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG38_IN_SEL (BIT(7)) +#define GPIO_SIG38_IN_SEL_M (GPIO_SIG38_IN_SEL_V << GPIO_SIG38_IN_SEL_S) +#define GPIO_SIG38_IN_SEL_V 0x00000001 +#define GPIO_SIG38_IN_SEL_S 7 + +/* GPIO_FUNC38_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC38_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC38_IN_INV_SEL_M (GPIO_FUNC38_IN_INV_SEL_V << GPIO_FUNC38_IN_INV_SEL_S) +#define GPIO_FUNC38_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC38_IN_INV_SEL_S 6 + +/* GPIO_FUNC38_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC38_IN_SEL 0x0000003F +#define GPIO_FUNC38_IN_SEL_M (GPIO_FUNC38_IN_SEL_V << GPIO_FUNC38_IN_SEL_S) +#define GPIO_FUNC38_IN_SEL_V 0x0000003F +#define GPIO_FUNC38_IN_SEL_S 0 + +/* GPIO_FUNC39_IN_SEL_CFG_REG register + * Peripheral function 39 input selection register + */ + +#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f0) + +/* GPIO_SIG39_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG39_IN_SEL (BIT(7)) +#define GPIO_SIG39_IN_SEL_M (GPIO_SIG39_IN_SEL_V << GPIO_SIG39_IN_SEL_S) +#define GPIO_SIG39_IN_SEL_V 0x00000001 +#define GPIO_SIG39_IN_SEL_S 7 + +/* GPIO_FUNC39_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC39_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC39_IN_INV_SEL_M (GPIO_FUNC39_IN_INV_SEL_V << GPIO_FUNC39_IN_INV_SEL_S) +#define GPIO_FUNC39_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC39_IN_INV_SEL_S 6 + +/* GPIO_FUNC39_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC39_IN_SEL 0x0000003F +#define GPIO_FUNC39_IN_SEL_M (GPIO_FUNC39_IN_SEL_V << GPIO_FUNC39_IN_SEL_S) +#define GPIO_FUNC39_IN_SEL_V 0x0000003F +#define GPIO_FUNC39_IN_SEL_S 0 + +/* GPIO_FUNC40_IN_SEL_CFG_REG register + * Peripheral function 40 input selection register + */ + +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4) + +/* GPIO_SIG40_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG40_IN_SEL (BIT(7)) +#define GPIO_SIG40_IN_SEL_M (GPIO_SIG40_IN_SEL_V << GPIO_SIG40_IN_SEL_S) +#define GPIO_SIG40_IN_SEL_V 0x00000001 +#define GPIO_SIG40_IN_SEL_S 7 + +/* GPIO_FUNC40_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_M (GPIO_FUNC40_IN_INV_SEL_V << GPIO_FUNC40_IN_INV_SEL_S) +#define GPIO_FUNC40_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC40_IN_INV_SEL_S 6 + +/* GPIO_FUNC40_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC40_IN_SEL 0x0000003F +#define GPIO_FUNC40_IN_SEL_M (GPIO_FUNC40_IN_SEL_V << GPIO_FUNC40_IN_SEL_S) +#define GPIO_FUNC40_IN_SEL_V 0x0000003F +#define GPIO_FUNC40_IN_SEL_S 0 + +/* GPIO_FUNC41_IN_SEL_CFG_REG register + * Peripheral function 41 input selection register + */ + +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8) + +/* GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) +#define GPIO_SIG41_IN_SEL_V 0x00000001 +#define GPIO_SIG41_IN_SEL_S 7 + +/* GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) +#define GPIO_FUNC41_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC41_IN_INV_SEL_S 6 + +/* GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC41_IN_SEL 0x0000003F +#define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) +#define GPIO_FUNC41_IN_SEL_V 0x0000003F +#define GPIO_FUNC41_IN_SEL_S 0 + +/* GPIO_FUNC42_IN_SEL_CFG_REG register + * Peripheral function 42 input selection register + */ + +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc) + +/* GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) +#define GPIO_SIG42_IN_SEL_V 0x00000001 +#define GPIO_SIG42_IN_SEL_S 7 + +/* GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) +#define GPIO_FUNC42_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC42_IN_INV_SEL_S 6 + +/* GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC42_IN_SEL 0x0000003F +#define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) +#define GPIO_FUNC42_IN_SEL_V 0x0000003F +#define GPIO_FUNC42_IN_SEL_S 0 + +/* GPIO_FUNC43_IN_SEL_CFG_REG register + * Peripheral function 43 input selection register + */ + +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200) + +/* GPIO_SIG43_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG43_IN_SEL (BIT(7)) +#define GPIO_SIG43_IN_SEL_M (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S) +#define GPIO_SIG43_IN_SEL_V 0x00000001 +#define GPIO_SIG43_IN_SEL_S 7 + +/* GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL_M (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S) +#define GPIO_FUNC43_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC43_IN_INV_SEL_S 6 + +/* GPIO_FUNC43_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC43_IN_SEL 0x0000003F +#define GPIO_FUNC43_IN_SEL_M (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S) +#define GPIO_FUNC43_IN_SEL_V 0x0000003F +#define GPIO_FUNC43_IN_SEL_S 0 + +/* GPIO_FUNC44_IN_SEL_CFG_REG register + * Peripheral function 44 input selection register + */ + +#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204) + +/* GPIO_SIG44_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG44_IN_SEL (BIT(7)) +#define GPIO_SIG44_IN_SEL_M (GPIO_SIG44_IN_SEL_V << GPIO_SIG44_IN_SEL_S) +#define GPIO_SIG44_IN_SEL_V 0x00000001 +#define GPIO_SIG44_IN_SEL_S 7 + +/* GPIO_FUNC44_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC44_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC44_IN_INV_SEL_M (GPIO_FUNC44_IN_INV_SEL_V << GPIO_FUNC44_IN_INV_SEL_S) +#define GPIO_FUNC44_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC44_IN_INV_SEL_S 6 + +/* GPIO_FUNC44_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC44_IN_SEL 0x0000003F +#define GPIO_FUNC44_IN_SEL_M (GPIO_FUNC44_IN_SEL_V << GPIO_FUNC44_IN_SEL_S) +#define GPIO_FUNC44_IN_SEL_V 0x0000003F +#define GPIO_FUNC44_IN_SEL_S 0 + +/* GPIO_FUNC45_IN_SEL_CFG_REG register + * Peripheral function 45 input selection register + */ + +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) + +/* GPIO_SIG45_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG45_IN_SEL (BIT(7)) +#define GPIO_SIG45_IN_SEL_M (GPIO_SIG45_IN_SEL_V << GPIO_SIG45_IN_SEL_S) +#define GPIO_SIG45_IN_SEL_V 0x00000001 +#define GPIO_SIG45_IN_SEL_S 7 + +/* GPIO_FUNC45_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_M (GPIO_FUNC45_IN_INV_SEL_V << GPIO_FUNC45_IN_INV_SEL_S) +#define GPIO_FUNC45_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC45_IN_INV_SEL_S 6 + +/* GPIO_FUNC45_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC45_IN_SEL 0x0000003F +#define GPIO_FUNC45_IN_SEL_M (GPIO_FUNC45_IN_SEL_V << GPIO_FUNC45_IN_SEL_S) +#define GPIO_FUNC45_IN_SEL_V 0x0000003F +#define GPIO_FUNC45_IN_SEL_S 0 + +/* GPIO_FUNC46_IN_SEL_CFG_REG register + * Peripheral function 46 input selection register + */ + +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c) + +/* GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) +#define GPIO_SIG46_IN_SEL_V 0x00000001 +#define GPIO_SIG46_IN_SEL_S 7 + +/* GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) +#define GPIO_FUNC46_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC46_IN_INV_SEL_S 6 + +/* GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC46_IN_SEL 0x0000003F +#define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) +#define GPIO_FUNC46_IN_SEL_V 0x0000003F +#define GPIO_FUNC46_IN_SEL_S 0 + +/* GPIO_FUNC47_IN_SEL_CFG_REG register + * Peripheral function 47 input selection register + */ + +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) + +/* GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) +#define GPIO_SIG47_IN_SEL_V 0x00000001 +#define GPIO_SIG47_IN_SEL_S 7 + +/* GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) +#define GPIO_FUNC47_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC47_IN_INV_SEL_S 6 + +/* GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC47_IN_SEL 0x0000003F +#define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) +#define GPIO_FUNC47_IN_SEL_V 0x0000003F +#define GPIO_FUNC47_IN_SEL_S 0 + +/* GPIO_FUNC48_IN_SEL_CFG_REG register + * Peripheral function 48 input selection register + */ + +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) + +/* GPIO_SIG48_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG48_IN_SEL (BIT(7)) +#define GPIO_SIG48_IN_SEL_M (GPIO_SIG48_IN_SEL_V << GPIO_SIG48_IN_SEL_S) +#define GPIO_SIG48_IN_SEL_V 0x00000001 +#define GPIO_SIG48_IN_SEL_S 7 + +/* GPIO_FUNC48_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_M (GPIO_FUNC48_IN_INV_SEL_V << GPIO_FUNC48_IN_INV_SEL_S) +#define GPIO_FUNC48_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC48_IN_INV_SEL_S 6 + +/* GPIO_FUNC48_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC48_IN_SEL 0x0000003F +#define GPIO_FUNC48_IN_SEL_M (GPIO_FUNC48_IN_SEL_V << GPIO_FUNC48_IN_SEL_S) +#define GPIO_FUNC48_IN_SEL_V 0x0000003F +#define GPIO_FUNC48_IN_SEL_S 0 + +/* GPIO_FUNC49_IN_SEL_CFG_REG register + * Peripheral function 49 input selection register + */ + +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) + +/* GPIO_SIG49_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG49_IN_SEL (BIT(7)) +#define GPIO_SIG49_IN_SEL_M (GPIO_SIG49_IN_SEL_V << GPIO_SIG49_IN_SEL_S) +#define GPIO_SIG49_IN_SEL_V 0x00000001 +#define GPIO_SIG49_IN_SEL_S 7 + +/* GPIO_FUNC49_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_M (GPIO_FUNC49_IN_INV_SEL_V << GPIO_FUNC49_IN_INV_SEL_S) +#define GPIO_FUNC49_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC49_IN_INV_SEL_S 6 + +/* GPIO_FUNC49_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC49_IN_SEL 0x0000003F +#define GPIO_FUNC49_IN_SEL_M (GPIO_FUNC49_IN_SEL_V << GPIO_FUNC49_IN_SEL_S) +#define GPIO_FUNC49_IN_SEL_V 0x0000003F +#define GPIO_FUNC49_IN_SEL_S 0 + +/* GPIO_FUNC50_IN_SEL_CFG_REG register + * Peripheral function 50 input selection register + */ + +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c) + +/* GPIO_SIG50_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG50_IN_SEL (BIT(7)) +#define GPIO_SIG50_IN_SEL_M (GPIO_SIG50_IN_SEL_V << GPIO_SIG50_IN_SEL_S) +#define GPIO_SIG50_IN_SEL_V 0x00000001 +#define GPIO_SIG50_IN_SEL_S 7 + +/* GPIO_FUNC50_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_M (GPIO_FUNC50_IN_INV_SEL_V << GPIO_FUNC50_IN_INV_SEL_S) +#define GPIO_FUNC50_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC50_IN_INV_SEL_S 6 + +/* GPIO_FUNC50_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC50_IN_SEL 0x0000003F +#define GPIO_FUNC50_IN_SEL_M (GPIO_FUNC50_IN_SEL_V << GPIO_FUNC50_IN_SEL_S) +#define GPIO_FUNC50_IN_SEL_V 0x0000003F +#define GPIO_FUNC50_IN_SEL_S 0 + +/* GPIO_FUNC51_IN_SEL_CFG_REG register + * Peripheral function 51 input selection register + */ + +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) + +/* GPIO_SIG51_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG51_IN_SEL (BIT(7)) +#define GPIO_SIG51_IN_SEL_M (GPIO_SIG51_IN_SEL_V << GPIO_SIG51_IN_SEL_S) +#define GPIO_SIG51_IN_SEL_V 0x00000001 +#define GPIO_SIG51_IN_SEL_S 7 + +/* GPIO_FUNC51_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_M (GPIO_FUNC51_IN_INV_SEL_V << GPIO_FUNC51_IN_INV_SEL_S) +#define GPIO_FUNC51_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC51_IN_INV_SEL_S 6 + +/* GPIO_FUNC51_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC51_IN_SEL 0x0000003F +#define GPIO_FUNC51_IN_SEL_M (GPIO_FUNC51_IN_SEL_V << GPIO_FUNC51_IN_SEL_S) +#define GPIO_FUNC51_IN_SEL_V 0x0000003F +#define GPIO_FUNC51_IN_SEL_S 0 + +/* GPIO_FUNC52_IN_SEL_CFG_REG register + * Peripheral function 52 input selection register + */ + +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) + +/* GPIO_SIG52_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG52_IN_SEL (BIT(7)) +#define GPIO_SIG52_IN_SEL_M (GPIO_SIG52_IN_SEL_V << GPIO_SIG52_IN_SEL_S) +#define GPIO_SIG52_IN_SEL_V 0x00000001 +#define GPIO_SIG52_IN_SEL_S 7 + +/* GPIO_FUNC52_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_M (GPIO_FUNC52_IN_INV_SEL_V << GPIO_FUNC52_IN_INV_SEL_S) +#define GPIO_FUNC52_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC52_IN_INV_SEL_S 6 + +/* GPIO_FUNC52_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC52_IN_SEL 0x0000003F +#define GPIO_FUNC52_IN_SEL_M (GPIO_FUNC52_IN_SEL_V << GPIO_FUNC52_IN_SEL_S) +#define GPIO_FUNC52_IN_SEL_V 0x0000003F +#define GPIO_FUNC52_IN_SEL_S 0 + +/* GPIO_FUNC53_IN_SEL_CFG_REG register + * Peripheral function 53 input selection register + */ + +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) + +/* GPIO_SIG53_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG53_IN_SEL (BIT(7)) +#define GPIO_SIG53_IN_SEL_M (GPIO_SIG53_IN_SEL_V << GPIO_SIG53_IN_SEL_S) +#define GPIO_SIG53_IN_SEL_V 0x00000001 +#define GPIO_SIG53_IN_SEL_S 7 + +/* GPIO_FUNC53_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_M (GPIO_FUNC53_IN_INV_SEL_V << GPIO_FUNC53_IN_INV_SEL_S) +#define GPIO_FUNC53_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC53_IN_INV_SEL_S 6 + +/* GPIO_FUNC53_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC53_IN_SEL 0x0000003F +#define GPIO_FUNC53_IN_SEL_M (GPIO_FUNC53_IN_SEL_V << GPIO_FUNC53_IN_SEL_S) +#define GPIO_FUNC53_IN_SEL_V 0x0000003F +#define GPIO_FUNC53_IN_SEL_S 0 + +/* GPIO_FUNC54_IN_SEL_CFG_REG register + * Peripheral function 54 input selection register + */ + +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c) + +/* GPIO_SIG54_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG54_IN_SEL (BIT(7)) +#define GPIO_SIG54_IN_SEL_M (GPIO_SIG54_IN_SEL_V << GPIO_SIG54_IN_SEL_S) +#define GPIO_SIG54_IN_SEL_V 0x00000001 +#define GPIO_SIG54_IN_SEL_S 7 + +/* GPIO_FUNC54_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_M (GPIO_FUNC54_IN_INV_SEL_V << GPIO_FUNC54_IN_INV_SEL_S) +#define GPIO_FUNC54_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC54_IN_INV_SEL_S 6 + +/* GPIO_FUNC54_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC54_IN_SEL 0x0000003F +#define GPIO_FUNC54_IN_SEL_M (GPIO_FUNC54_IN_SEL_V << GPIO_FUNC54_IN_SEL_S) +#define GPIO_FUNC54_IN_SEL_V 0x0000003F +#define GPIO_FUNC54_IN_SEL_S 0 + +/* GPIO_FUNC55_IN_SEL_CFG_REG register + * Peripheral function 55 input selection register + */ + +#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) + +/* GPIO_SIG55_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG55_IN_SEL (BIT(7)) +#define GPIO_SIG55_IN_SEL_M (GPIO_SIG55_IN_SEL_V << GPIO_SIG55_IN_SEL_S) +#define GPIO_SIG55_IN_SEL_V 0x00000001 +#define GPIO_SIG55_IN_SEL_S 7 + +/* GPIO_FUNC55_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC55_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL_M (GPIO_FUNC55_IN_INV_SEL_V << GPIO_FUNC55_IN_INV_SEL_S) +#define GPIO_FUNC55_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC55_IN_INV_SEL_S 6 + +/* GPIO_FUNC55_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC55_IN_SEL 0x0000003F +#define GPIO_FUNC55_IN_SEL_M (GPIO_FUNC55_IN_SEL_V << GPIO_FUNC55_IN_SEL_S) +#define GPIO_FUNC55_IN_SEL_V 0x0000003F +#define GPIO_FUNC55_IN_SEL_S 0 + +/* GPIO_FUNC56_IN_SEL_CFG_REG register + * Peripheral function 56 input selection register + */ + +#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) + +/* GPIO_SIG56_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG56_IN_SEL (BIT(7)) +#define GPIO_SIG56_IN_SEL_M (GPIO_SIG56_IN_SEL_V << GPIO_SIG56_IN_SEL_S) +#define GPIO_SIG56_IN_SEL_V 0x00000001 +#define GPIO_SIG56_IN_SEL_S 7 + +/* GPIO_FUNC56_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC56_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL_M (GPIO_FUNC56_IN_INV_SEL_V << GPIO_FUNC56_IN_INV_SEL_S) +#define GPIO_FUNC56_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC56_IN_INV_SEL_S 6 + +/* GPIO_FUNC56_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC56_IN_SEL 0x0000003F +#define GPIO_FUNC56_IN_SEL_M (GPIO_FUNC56_IN_SEL_V << GPIO_FUNC56_IN_SEL_S) +#define GPIO_FUNC56_IN_SEL_V 0x0000003F +#define GPIO_FUNC56_IN_SEL_S 0 + +/* GPIO_FUNC57_IN_SEL_CFG_REG register + * Peripheral function 57 input selection register + */ + +#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) + +/* GPIO_SIG57_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG57_IN_SEL (BIT(7)) +#define GPIO_SIG57_IN_SEL_M (GPIO_SIG57_IN_SEL_V << GPIO_SIG57_IN_SEL_S) +#define GPIO_SIG57_IN_SEL_V 0x00000001 +#define GPIO_SIG57_IN_SEL_S 7 + +/* GPIO_FUNC57_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC57_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC57_IN_INV_SEL_M (GPIO_FUNC57_IN_INV_SEL_V << GPIO_FUNC57_IN_INV_SEL_S) +#define GPIO_FUNC57_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC57_IN_INV_SEL_S 6 + +/* GPIO_FUNC57_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC57_IN_SEL 0x0000003F +#define GPIO_FUNC57_IN_SEL_M (GPIO_FUNC57_IN_SEL_V << GPIO_FUNC57_IN_SEL_S) +#define GPIO_FUNC57_IN_SEL_V 0x0000003F +#define GPIO_FUNC57_IN_SEL_S 0 + +/* GPIO_FUNC58_IN_SEL_CFG_REG register + * Peripheral function 58 input selection register + */ + +#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c) + +/* GPIO_SIG58_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG58_IN_SEL (BIT(7)) +#define GPIO_SIG58_IN_SEL_M (GPIO_SIG58_IN_SEL_V << GPIO_SIG58_IN_SEL_S) +#define GPIO_SIG58_IN_SEL_V 0x00000001 +#define GPIO_SIG58_IN_SEL_S 7 + +/* GPIO_FUNC58_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC58_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC58_IN_INV_SEL_M (GPIO_FUNC58_IN_INV_SEL_V << GPIO_FUNC58_IN_INV_SEL_S) +#define GPIO_FUNC58_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC58_IN_INV_SEL_S 6 + +/* GPIO_FUNC58_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC58_IN_SEL 0x0000003F +#define GPIO_FUNC58_IN_SEL_M (GPIO_FUNC58_IN_SEL_V << GPIO_FUNC58_IN_SEL_S) +#define GPIO_FUNC58_IN_SEL_V 0x0000003F +#define GPIO_FUNC58_IN_SEL_S 0 + +/* GPIO_FUNC59_IN_SEL_CFG_REG register + * Peripheral function 59 input selection register + */ + +#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) + +/* GPIO_SIG59_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG59_IN_SEL (BIT(7)) +#define GPIO_SIG59_IN_SEL_M (GPIO_SIG59_IN_SEL_V << GPIO_SIG59_IN_SEL_S) +#define GPIO_SIG59_IN_SEL_V 0x00000001 +#define GPIO_SIG59_IN_SEL_S 7 + +/* GPIO_FUNC59_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC59_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC59_IN_INV_SEL_M (GPIO_FUNC59_IN_INV_SEL_V << GPIO_FUNC59_IN_INV_SEL_S) +#define GPIO_FUNC59_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC59_IN_INV_SEL_S 6 + +/* GPIO_FUNC59_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC59_IN_SEL 0x0000003F +#define GPIO_FUNC59_IN_SEL_M (GPIO_FUNC59_IN_SEL_V << GPIO_FUNC59_IN_SEL_S) +#define GPIO_FUNC59_IN_SEL_V 0x0000003F +#define GPIO_FUNC59_IN_SEL_S 0 + +/* GPIO_FUNC60_IN_SEL_CFG_REG register + * Peripheral function 60 input selection register + */ + +#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) + +/* GPIO_SIG60_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG60_IN_SEL (BIT(7)) +#define GPIO_SIG60_IN_SEL_M (GPIO_SIG60_IN_SEL_V << GPIO_SIG60_IN_SEL_S) +#define GPIO_SIG60_IN_SEL_V 0x00000001 +#define GPIO_SIG60_IN_SEL_S 7 + +/* GPIO_FUNC60_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC60_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC60_IN_INV_SEL_M (GPIO_FUNC60_IN_INV_SEL_V << GPIO_FUNC60_IN_INV_SEL_S) +#define GPIO_FUNC60_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC60_IN_INV_SEL_S 6 + +/* GPIO_FUNC60_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC60_IN_SEL 0x0000003F +#define GPIO_FUNC60_IN_SEL_M (GPIO_FUNC60_IN_SEL_V << GPIO_FUNC60_IN_SEL_S) +#define GPIO_FUNC60_IN_SEL_V 0x0000003F +#define GPIO_FUNC60_IN_SEL_S 0 + +/* GPIO_FUNC61_IN_SEL_CFG_REG register + * Peripheral function 61 input selection register + */ + +#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) + +/* GPIO_SIG61_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG61_IN_SEL (BIT(7)) +#define GPIO_SIG61_IN_SEL_M (GPIO_SIG61_IN_SEL_V << GPIO_SIG61_IN_SEL_S) +#define GPIO_SIG61_IN_SEL_V 0x00000001 +#define GPIO_SIG61_IN_SEL_S 7 + +/* GPIO_FUNC61_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC61_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC61_IN_INV_SEL_M (GPIO_FUNC61_IN_INV_SEL_V << GPIO_FUNC61_IN_INV_SEL_S) +#define GPIO_FUNC61_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC61_IN_INV_SEL_S 6 + +/* GPIO_FUNC61_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC61_IN_SEL 0x0000003F +#define GPIO_FUNC61_IN_SEL_M (GPIO_FUNC61_IN_SEL_V << GPIO_FUNC61_IN_SEL_S) +#define GPIO_FUNC61_IN_SEL_V 0x0000003F +#define GPIO_FUNC61_IN_SEL_S 0 + +/* GPIO_FUNC62_IN_SEL_CFG_REG register + * Peripheral function 62 input selection register + */ + +#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c) + +/* GPIO_SIG62_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG62_IN_SEL (BIT(7)) +#define GPIO_SIG62_IN_SEL_M (GPIO_SIG62_IN_SEL_V << GPIO_SIG62_IN_SEL_S) +#define GPIO_SIG62_IN_SEL_V 0x00000001 +#define GPIO_SIG62_IN_SEL_S 7 + +/* GPIO_FUNC62_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC62_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC62_IN_INV_SEL_M (GPIO_FUNC62_IN_INV_SEL_V << GPIO_FUNC62_IN_INV_SEL_S) +#define GPIO_FUNC62_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC62_IN_INV_SEL_S 6 + +/* GPIO_FUNC62_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC62_IN_SEL 0x0000003F +#define GPIO_FUNC62_IN_SEL_M (GPIO_FUNC62_IN_SEL_V << GPIO_FUNC62_IN_SEL_S) +#define GPIO_FUNC62_IN_SEL_V 0x0000003F +#define GPIO_FUNC62_IN_SEL_S 0 + +/* GPIO_FUNC63_IN_SEL_CFG_REG register + * Peripheral function 63 input selection register + */ + +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) + +/* GPIO_SIG63_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG63_IN_SEL (BIT(7)) +#define GPIO_SIG63_IN_SEL_M (GPIO_SIG63_IN_SEL_V << GPIO_SIG63_IN_SEL_S) +#define GPIO_SIG63_IN_SEL_V 0x00000001 +#define GPIO_SIG63_IN_SEL_S 7 + +/* GPIO_FUNC63_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_M (GPIO_FUNC63_IN_INV_SEL_V << GPIO_FUNC63_IN_INV_SEL_S) +#define GPIO_FUNC63_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC63_IN_INV_SEL_S 6 + +/* GPIO_FUNC63_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC63_IN_SEL 0x0000003F +#define GPIO_FUNC63_IN_SEL_M (GPIO_FUNC63_IN_SEL_V << GPIO_FUNC63_IN_SEL_S) +#define GPIO_FUNC63_IN_SEL_V 0x0000003F +#define GPIO_FUNC63_IN_SEL_S 0 + +/* GPIO_FUNC64_IN_SEL_CFG_REG register + * Peripheral function 64 input selection register + */ + +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) + +/* GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) +#define GPIO_SIG64_IN_SEL_V 0x00000001 +#define GPIO_SIG64_IN_SEL_S 7 + +/* GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) +#define GPIO_FUNC64_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC64_IN_INV_SEL_S 6 + +/* GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC64_IN_SEL 0x0000003F +#define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) +#define GPIO_FUNC64_IN_SEL_V 0x0000003F +#define GPIO_FUNC64_IN_SEL_S 0 + +/* GPIO_FUNC65_IN_SEL_CFG_REG register + * Peripheral function 65 input selection register + */ + +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) + +/* GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) +#define GPIO_SIG65_IN_SEL_V 0x00000001 +#define GPIO_SIG65_IN_SEL_S 7 + +/* GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) +#define GPIO_FUNC65_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC65_IN_INV_SEL_S 6 + +/* GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC65_IN_SEL 0x0000003F +#define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) +#define GPIO_FUNC65_IN_SEL_V 0x0000003F +#define GPIO_FUNC65_IN_SEL_S 0 + +/* GPIO_FUNC66_IN_SEL_CFG_REG register + * Peripheral function 66 input selection register + */ + +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c) + +/* GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) +#define GPIO_SIG66_IN_SEL_V 0x00000001 +#define GPIO_SIG66_IN_SEL_S 7 + +/* GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) +#define GPIO_FUNC66_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC66_IN_INV_SEL_S 6 + +/* GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC66_IN_SEL 0x0000003F +#define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) +#define GPIO_FUNC66_IN_SEL_V 0x0000003F +#define GPIO_FUNC66_IN_SEL_S 0 + +/* GPIO_FUNC67_IN_SEL_CFG_REG register + * Peripheral function 67 input selection register + */ + +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) + +/* GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL_M (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S) +#define GPIO_SIG67_IN_SEL_V 0x00000001 +#define GPIO_SIG67_IN_SEL_S 7 + +/* GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_M (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S) +#define GPIO_FUNC67_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC67_IN_INV_SEL_S 6 + +/* GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC67_IN_SEL 0x0000003F +#define GPIO_FUNC67_IN_SEL_M (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S) +#define GPIO_FUNC67_IN_SEL_V 0x0000003F +#define GPIO_FUNC67_IN_SEL_S 0 + +/* GPIO_FUNC68_IN_SEL_CFG_REG register + * Peripheral function 68 input selection register + */ + +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) + +/* GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL_M (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S) +#define GPIO_SIG68_IN_SEL_V 0x00000001 +#define GPIO_SIG68_IN_SEL_S 7 + +/* GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_M (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S) +#define GPIO_FUNC68_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC68_IN_INV_SEL_S 6 + +/* GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC68_IN_SEL 0x0000003F +#define GPIO_FUNC68_IN_SEL_M (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S) +#define GPIO_FUNC68_IN_SEL_V 0x0000003F +#define GPIO_FUNC68_IN_SEL_S 0 + +/* GPIO_FUNC69_IN_SEL_CFG_REG register + * Peripheral function 69 input selection register + */ + +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) + +/* GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL_M (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S) +#define GPIO_SIG69_IN_SEL_V 0x00000001 +#define GPIO_SIG69_IN_SEL_S 7 + +/* GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_M (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S) +#define GPIO_FUNC69_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC69_IN_INV_SEL_S 6 + +/* GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC69_IN_SEL 0x0000003F +#define GPIO_FUNC69_IN_SEL_M (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S) +#define GPIO_FUNC69_IN_SEL_V 0x0000003F +#define GPIO_FUNC69_IN_SEL_S 0 + +/* GPIO_FUNC70_IN_SEL_CFG_REG register + * Peripheral function 70 input selection register + */ + +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c) + +/* GPIO_SIG70_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG70_IN_SEL (BIT(7)) +#define GPIO_SIG70_IN_SEL_M (GPIO_SIG70_IN_SEL_V << GPIO_SIG70_IN_SEL_S) +#define GPIO_SIG70_IN_SEL_V 0x00000001 +#define GPIO_SIG70_IN_SEL_S 7 + +/* GPIO_FUNC70_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_M (GPIO_FUNC70_IN_INV_SEL_V << GPIO_FUNC70_IN_INV_SEL_S) +#define GPIO_FUNC70_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC70_IN_INV_SEL_S 6 + +/* GPIO_FUNC70_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC70_IN_SEL 0x0000003F +#define GPIO_FUNC70_IN_SEL_M (GPIO_FUNC70_IN_SEL_V << GPIO_FUNC70_IN_SEL_S) +#define GPIO_FUNC70_IN_SEL_V 0x0000003F +#define GPIO_FUNC70_IN_SEL_S 0 + +/* GPIO_FUNC71_IN_SEL_CFG_REG register + * Peripheral function 71 input selection register + */ + +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) + +/* GPIO_SIG71_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG71_IN_SEL (BIT(7)) +#define GPIO_SIG71_IN_SEL_M (GPIO_SIG71_IN_SEL_V << GPIO_SIG71_IN_SEL_S) +#define GPIO_SIG71_IN_SEL_V 0x00000001 +#define GPIO_SIG71_IN_SEL_S 7 + +/* GPIO_FUNC71_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_M (GPIO_FUNC71_IN_INV_SEL_V << GPIO_FUNC71_IN_INV_SEL_S) +#define GPIO_FUNC71_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC71_IN_INV_SEL_S 6 + +/* GPIO_FUNC71_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC71_IN_SEL 0x0000003F +#define GPIO_FUNC71_IN_SEL_M (GPIO_FUNC71_IN_SEL_V << GPIO_FUNC71_IN_SEL_S) +#define GPIO_FUNC71_IN_SEL_V 0x0000003F +#define GPIO_FUNC71_IN_SEL_S 0 + +/* GPIO_FUNC72_IN_SEL_CFG_REG register + * Peripheral function 72 input selection register + */ + +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) + +/* GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL_M (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S) +#define GPIO_SIG72_IN_SEL_V 0x00000001 +#define GPIO_SIG72_IN_SEL_S 7 + +/* GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_M (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S) +#define GPIO_FUNC72_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC72_IN_INV_SEL_S 6 + +/* GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC72_IN_SEL 0x0000003F +#define GPIO_FUNC72_IN_SEL_M (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S) +#define GPIO_FUNC72_IN_SEL_V 0x0000003F +#define GPIO_FUNC72_IN_SEL_S 0 + +/* GPIO_FUNC73_IN_SEL_CFG_REG register + * Peripheral function 73 input selection register + */ + +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) + +/* GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL_M (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S) +#define GPIO_SIG73_IN_SEL_V 0x00000001 +#define GPIO_SIG73_IN_SEL_S 7 + +/* GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_M (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S) +#define GPIO_FUNC73_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC73_IN_INV_SEL_S 6 + +/* GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC73_IN_SEL 0x0000003F +#define GPIO_FUNC73_IN_SEL_M (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S) +#define GPIO_FUNC73_IN_SEL_V 0x0000003F +#define GPIO_FUNC73_IN_SEL_S 0 + +/* GPIO_FUNC74_IN_SEL_CFG_REG register + * Peripheral function 74 input selection register + */ + +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27c) + +/* GPIO_SIG74_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG74_IN_SEL (BIT(7)) +#define GPIO_SIG74_IN_SEL_M (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S) +#define GPIO_SIG74_IN_SEL_V 0x00000001 +#define GPIO_SIG74_IN_SEL_S 7 + +/* GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL_M (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S) +#define GPIO_FUNC74_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC74_IN_INV_SEL_S 6 + +/* GPIO_FUNC74_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC74_IN_SEL 0x0000003F +#define GPIO_FUNC74_IN_SEL_M (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S) +#define GPIO_FUNC74_IN_SEL_V 0x0000003F +#define GPIO_FUNC74_IN_SEL_S 0 + +/* GPIO_FUNC75_IN_SEL_CFG_REG register + * Peripheral function 75 input selection register + */ + +#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280) + +/* GPIO_SIG75_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG75_IN_SEL (BIT(7)) +#define GPIO_SIG75_IN_SEL_M (GPIO_SIG75_IN_SEL_V << GPIO_SIG75_IN_SEL_S) +#define GPIO_SIG75_IN_SEL_V 0x00000001 +#define GPIO_SIG75_IN_SEL_S 7 + +/* GPIO_FUNC75_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC75_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC75_IN_INV_SEL_M (GPIO_FUNC75_IN_INV_SEL_V << GPIO_FUNC75_IN_INV_SEL_S) +#define GPIO_FUNC75_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC75_IN_INV_SEL_S 6 + +/* GPIO_FUNC75_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC75_IN_SEL 0x0000003F +#define GPIO_FUNC75_IN_SEL_M (GPIO_FUNC75_IN_SEL_V << GPIO_FUNC75_IN_SEL_S) +#define GPIO_FUNC75_IN_SEL_V 0x0000003F +#define GPIO_FUNC75_IN_SEL_S 0 + +/* GPIO_FUNC76_IN_SEL_CFG_REG register + * Peripheral function 76 input selection register + */ + +#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284) + +/* GPIO_SIG76_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG76_IN_SEL (BIT(7)) +#define GPIO_SIG76_IN_SEL_M (GPIO_SIG76_IN_SEL_V << GPIO_SIG76_IN_SEL_S) +#define GPIO_SIG76_IN_SEL_V 0x00000001 +#define GPIO_SIG76_IN_SEL_S 7 + +/* GPIO_FUNC76_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC76_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC76_IN_INV_SEL_M (GPIO_FUNC76_IN_INV_SEL_V << GPIO_FUNC76_IN_INV_SEL_S) +#define GPIO_FUNC76_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC76_IN_INV_SEL_S 6 + +/* GPIO_FUNC76_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC76_IN_SEL 0x0000003F +#define GPIO_FUNC76_IN_SEL_M (GPIO_FUNC76_IN_SEL_V << GPIO_FUNC76_IN_SEL_S) +#define GPIO_FUNC76_IN_SEL_V 0x0000003F +#define GPIO_FUNC76_IN_SEL_S 0 + +/* GPIO_FUNC77_IN_SEL_CFG_REG register + * Peripheral function 77 input selection register + */ + +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) + +/* GPIO_SIG77_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG77_IN_SEL (BIT(7)) +#define GPIO_SIG77_IN_SEL_M (GPIO_SIG77_IN_SEL_V << GPIO_SIG77_IN_SEL_S) +#define GPIO_SIG77_IN_SEL_V 0x00000001 +#define GPIO_SIG77_IN_SEL_S 7 + +/* GPIO_FUNC77_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_M (GPIO_FUNC77_IN_INV_SEL_V << GPIO_FUNC77_IN_INV_SEL_S) +#define GPIO_FUNC77_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC77_IN_INV_SEL_S 6 + +/* GPIO_FUNC77_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC77_IN_SEL 0x0000003F +#define GPIO_FUNC77_IN_SEL_M (GPIO_FUNC77_IN_SEL_V << GPIO_FUNC77_IN_SEL_S) +#define GPIO_FUNC77_IN_SEL_V 0x0000003F +#define GPIO_FUNC77_IN_SEL_S 0 + +/* GPIO_FUNC78_IN_SEL_CFG_REG register + * Peripheral function 78 input selection register + */ + +#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28c) + +/* GPIO_SIG78_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG78_IN_SEL (BIT(7)) +#define GPIO_SIG78_IN_SEL_M (GPIO_SIG78_IN_SEL_V << GPIO_SIG78_IN_SEL_S) +#define GPIO_SIG78_IN_SEL_V 0x00000001 +#define GPIO_SIG78_IN_SEL_S 7 + +/* GPIO_FUNC78_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC78_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC78_IN_INV_SEL_M (GPIO_FUNC78_IN_INV_SEL_V << GPIO_FUNC78_IN_INV_SEL_S) +#define GPIO_FUNC78_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC78_IN_INV_SEL_S 6 + +/* GPIO_FUNC78_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC78_IN_SEL 0x0000003F +#define GPIO_FUNC78_IN_SEL_M (GPIO_FUNC78_IN_SEL_V << GPIO_FUNC78_IN_SEL_S) +#define GPIO_FUNC78_IN_SEL_V 0x0000003F +#define GPIO_FUNC78_IN_SEL_S 0 + +/* GPIO_FUNC79_IN_SEL_CFG_REG register + * Peripheral function 79 input selection register + */ + +#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290) + +/* GPIO_SIG79_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG79_IN_SEL (BIT(7)) +#define GPIO_SIG79_IN_SEL_M (GPIO_SIG79_IN_SEL_V << GPIO_SIG79_IN_SEL_S) +#define GPIO_SIG79_IN_SEL_V 0x00000001 +#define GPIO_SIG79_IN_SEL_S 7 + +/* GPIO_FUNC79_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC79_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC79_IN_INV_SEL_M (GPIO_FUNC79_IN_INV_SEL_V << GPIO_FUNC79_IN_INV_SEL_S) +#define GPIO_FUNC79_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC79_IN_INV_SEL_S 6 + +/* GPIO_FUNC79_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC79_IN_SEL 0x0000003F +#define GPIO_FUNC79_IN_SEL_M (GPIO_FUNC79_IN_SEL_V << GPIO_FUNC79_IN_SEL_S) +#define GPIO_FUNC79_IN_SEL_V 0x0000003F +#define GPIO_FUNC79_IN_SEL_S 0 + +/* GPIO_FUNC80_IN_SEL_CFG_REG register + * Peripheral function 80 input selection register + */ + +#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294) + +/* GPIO_SIG80_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG80_IN_SEL (BIT(7)) +#define GPIO_SIG80_IN_SEL_M (GPIO_SIG80_IN_SEL_V << GPIO_SIG80_IN_SEL_S) +#define GPIO_SIG80_IN_SEL_V 0x00000001 +#define GPIO_SIG80_IN_SEL_S 7 + +/* GPIO_FUNC80_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC80_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC80_IN_INV_SEL_M (GPIO_FUNC80_IN_INV_SEL_V << GPIO_FUNC80_IN_INV_SEL_S) +#define GPIO_FUNC80_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC80_IN_INV_SEL_S 6 + +/* GPIO_FUNC80_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC80_IN_SEL 0x0000003F +#define GPIO_FUNC80_IN_SEL_M (GPIO_FUNC80_IN_SEL_V << GPIO_FUNC80_IN_SEL_S) +#define GPIO_FUNC80_IN_SEL_V 0x0000003F +#define GPIO_FUNC80_IN_SEL_S 0 + +/* GPIO_FUNC81_IN_SEL_CFG_REG register + * Peripheral function 81 input selection register + */ + +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) + +/* GPIO_SIG81_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG81_IN_SEL (BIT(7)) +#define GPIO_SIG81_IN_SEL_M (GPIO_SIG81_IN_SEL_V << GPIO_SIG81_IN_SEL_S) +#define GPIO_SIG81_IN_SEL_V 0x00000001 +#define GPIO_SIG81_IN_SEL_S 7 + +/* GPIO_FUNC81_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_M (GPIO_FUNC81_IN_INV_SEL_V << GPIO_FUNC81_IN_INV_SEL_S) +#define GPIO_FUNC81_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC81_IN_INV_SEL_S 6 + +/* GPIO_FUNC81_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC81_IN_SEL 0x0000003F +#define GPIO_FUNC81_IN_SEL_M (GPIO_FUNC81_IN_SEL_V << GPIO_FUNC81_IN_SEL_S) +#define GPIO_FUNC81_IN_SEL_V 0x0000003F +#define GPIO_FUNC81_IN_SEL_S 0 + +/* GPIO_FUNC82_IN_SEL_CFG_REG register + * Peripheral function 82 input selection register + */ + +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c) + +/* GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) +#define GPIO_SIG82_IN_SEL_V 0x00000001 +#define GPIO_SIG82_IN_SEL_S 7 + +/* GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) +#define GPIO_FUNC82_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC82_IN_INV_SEL_S 6 + +/* GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC82_IN_SEL 0x0000003F +#define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) +#define GPIO_FUNC82_IN_SEL_V 0x0000003F +#define GPIO_FUNC82_IN_SEL_S 0 + +/* GPIO_FUNC83_IN_SEL_CFG_REG register + * Peripheral function 83 input selection register + */ + +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a0) + +/* GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG83_IN_SEL (BIT(7)) +#define GPIO_SIG83_IN_SEL_M (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S) +#define GPIO_SIG83_IN_SEL_V 0x00000001 +#define GPIO_SIG83_IN_SEL_S 7 + +/* GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_M (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S) +#define GPIO_FUNC83_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC83_IN_INV_SEL_S 6 + +/* GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC83_IN_SEL 0x0000003F +#define GPIO_FUNC83_IN_SEL_M (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S) +#define GPIO_FUNC83_IN_SEL_V 0x0000003F +#define GPIO_FUNC83_IN_SEL_S 0 + +/* GPIO_FUNC84_IN_SEL_CFG_REG register + * Peripheral function 84 input selection register + */ + +#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4) + +/* GPIO_SIG84_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG84_IN_SEL (BIT(7)) +#define GPIO_SIG84_IN_SEL_M (GPIO_SIG84_IN_SEL_V << GPIO_SIG84_IN_SEL_S) +#define GPIO_SIG84_IN_SEL_V 0x00000001 +#define GPIO_SIG84_IN_SEL_S 7 + +/* GPIO_FUNC84_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC84_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL_M (GPIO_FUNC84_IN_INV_SEL_V << GPIO_FUNC84_IN_INV_SEL_S) +#define GPIO_FUNC84_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC84_IN_INV_SEL_S 6 + +/* GPIO_FUNC84_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC84_IN_SEL 0x0000003F +#define GPIO_FUNC84_IN_SEL_M (GPIO_FUNC84_IN_SEL_V << GPIO_FUNC84_IN_SEL_S) +#define GPIO_FUNC84_IN_SEL_V 0x0000003F +#define GPIO_FUNC84_IN_SEL_S 0 + +/* GPIO_FUNC85_IN_SEL_CFG_REG register + * Peripheral function 85 input selection register + */ + +#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a8) + +/* GPIO_SIG85_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG85_IN_SEL (BIT(7)) +#define GPIO_SIG85_IN_SEL_M (GPIO_SIG85_IN_SEL_V << GPIO_SIG85_IN_SEL_S) +#define GPIO_SIG85_IN_SEL_V 0x00000001 +#define GPIO_SIG85_IN_SEL_S 7 + +/* GPIO_FUNC85_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC85_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL_M (GPIO_FUNC85_IN_INV_SEL_V << GPIO_FUNC85_IN_INV_SEL_S) +#define GPIO_FUNC85_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC85_IN_INV_SEL_S 6 + +/* GPIO_FUNC85_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC85_IN_SEL 0x0000003F +#define GPIO_FUNC85_IN_SEL_M (GPIO_FUNC85_IN_SEL_V << GPIO_FUNC85_IN_SEL_S) +#define GPIO_FUNC85_IN_SEL_V 0x0000003F +#define GPIO_FUNC85_IN_SEL_S 0 + +/* GPIO_FUNC86_IN_SEL_CFG_REG register + * Peripheral function 86 input selection register + */ + +#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ac) + +/* GPIO_SIG86_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG86_IN_SEL (BIT(7)) +#define GPIO_SIG86_IN_SEL_M (GPIO_SIG86_IN_SEL_V << GPIO_SIG86_IN_SEL_S) +#define GPIO_SIG86_IN_SEL_V 0x00000001 +#define GPIO_SIG86_IN_SEL_S 7 + +/* GPIO_FUNC86_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC86_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL_M (GPIO_FUNC86_IN_INV_SEL_V << GPIO_FUNC86_IN_INV_SEL_S) +#define GPIO_FUNC86_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC86_IN_INV_SEL_S 6 + +/* GPIO_FUNC86_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC86_IN_SEL 0x0000003F +#define GPIO_FUNC86_IN_SEL_M (GPIO_FUNC86_IN_SEL_V << GPIO_FUNC86_IN_SEL_S) +#define GPIO_FUNC86_IN_SEL_V 0x0000003F +#define GPIO_FUNC86_IN_SEL_S 0 + +/* GPIO_FUNC87_IN_SEL_CFG_REG register + * Peripheral function 87 input selection register + */ + +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0) + +/* GPIO_SIG87_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG87_IN_SEL (BIT(7)) +#define GPIO_SIG87_IN_SEL_M (GPIO_SIG87_IN_SEL_V << GPIO_SIG87_IN_SEL_S) +#define GPIO_SIG87_IN_SEL_V 0x00000001 +#define GPIO_SIG87_IN_SEL_S 7 + +/* GPIO_FUNC87_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_M (GPIO_FUNC87_IN_INV_SEL_V << GPIO_FUNC87_IN_INV_SEL_S) +#define GPIO_FUNC87_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC87_IN_INV_SEL_S 6 + +/* GPIO_FUNC87_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC87_IN_SEL 0x0000003F +#define GPIO_FUNC87_IN_SEL_M (GPIO_FUNC87_IN_SEL_V << GPIO_FUNC87_IN_SEL_S) +#define GPIO_FUNC87_IN_SEL_V 0x0000003F +#define GPIO_FUNC87_IN_SEL_S 0 + +/* GPIO_FUNC88_IN_SEL_CFG_REG register + * Peripheral function 88 input selection register + */ + +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4) + +/* GPIO_SIG88_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG88_IN_SEL (BIT(7)) +#define GPIO_SIG88_IN_SEL_M (GPIO_SIG88_IN_SEL_V << GPIO_SIG88_IN_SEL_S) +#define GPIO_SIG88_IN_SEL_V 0x00000001 +#define GPIO_SIG88_IN_SEL_S 7 + +/* GPIO_FUNC88_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_M (GPIO_FUNC88_IN_INV_SEL_V << GPIO_FUNC88_IN_INV_SEL_S) +#define GPIO_FUNC88_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC88_IN_INV_SEL_S 6 + +/* GPIO_FUNC88_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC88_IN_SEL 0x0000003F +#define GPIO_FUNC88_IN_SEL_M (GPIO_FUNC88_IN_SEL_V << GPIO_FUNC88_IN_SEL_S) +#define GPIO_FUNC88_IN_SEL_V 0x0000003F +#define GPIO_FUNC88_IN_SEL_S 0 + +/* GPIO_FUNC89_IN_SEL_CFG_REG register + * Peripheral function 89 input selection register + */ + +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8) + +/* GPIO_SIG89_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG89_IN_SEL (BIT(7)) +#define GPIO_SIG89_IN_SEL_M (GPIO_SIG89_IN_SEL_V << GPIO_SIG89_IN_SEL_S) +#define GPIO_SIG89_IN_SEL_V 0x00000001 +#define GPIO_SIG89_IN_SEL_S 7 + +/* GPIO_FUNC89_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_M (GPIO_FUNC89_IN_INV_SEL_V << GPIO_FUNC89_IN_INV_SEL_S) +#define GPIO_FUNC89_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC89_IN_INV_SEL_S 6 + +/* GPIO_FUNC89_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC89_IN_SEL 0x0000003F +#define GPIO_FUNC89_IN_SEL_M (GPIO_FUNC89_IN_SEL_V << GPIO_FUNC89_IN_SEL_S) +#define GPIO_FUNC89_IN_SEL_V 0x0000003F +#define GPIO_FUNC89_IN_SEL_S 0 + +/* GPIO_FUNC90_IN_SEL_CFG_REG register + * Peripheral function 90 input selection register + */ + +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc) + +/* GPIO_SIG90_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG90_IN_SEL (BIT(7)) +#define GPIO_SIG90_IN_SEL_M (GPIO_SIG90_IN_SEL_V << GPIO_SIG90_IN_SEL_S) +#define GPIO_SIG90_IN_SEL_V 0x00000001 +#define GPIO_SIG90_IN_SEL_S 7 + +/* GPIO_FUNC90_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_M (GPIO_FUNC90_IN_INV_SEL_V << GPIO_FUNC90_IN_INV_SEL_S) +#define GPIO_FUNC90_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC90_IN_INV_SEL_S 6 + +/* GPIO_FUNC90_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC90_IN_SEL 0x0000003F +#define GPIO_FUNC90_IN_SEL_M (GPIO_FUNC90_IN_SEL_V << GPIO_FUNC90_IN_SEL_S) +#define GPIO_FUNC90_IN_SEL_V 0x0000003F +#define GPIO_FUNC90_IN_SEL_S 0 + +/* GPIO_FUNC91_IN_SEL_CFG_REG register + * Peripheral function 91 input selection register + */ + +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0) + +/* GPIO_SIG91_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG91_IN_SEL (BIT(7)) +#define GPIO_SIG91_IN_SEL_M (GPIO_SIG91_IN_SEL_V << GPIO_SIG91_IN_SEL_S) +#define GPIO_SIG91_IN_SEL_V 0x00000001 +#define GPIO_SIG91_IN_SEL_S 7 + +/* GPIO_FUNC91_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_M (GPIO_FUNC91_IN_INV_SEL_V << GPIO_FUNC91_IN_INV_SEL_S) +#define GPIO_FUNC91_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC91_IN_INV_SEL_S 6 + +/* GPIO_FUNC91_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC91_IN_SEL 0x0000003F +#define GPIO_FUNC91_IN_SEL_M (GPIO_FUNC91_IN_SEL_V << GPIO_FUNC91_IN_SEL_S) +#define GPIO_FUNC91_IN_SEL_V 0x0000003F +#define GPIO_FUNC91_IN_SEL_S 0 + +/* GPIO_FUNC92_IN_SEL_CFG_REG register + * Peripheral function 92 input selection register + */ + +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) + +/* GPIO_SIG92_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG92_IN_SEL (BIT(7)) +#define GPIO_SIG92_IN_SEL_M (GPIO_SIG92_IN_SEL_V << GPIO_SIG92_IN_SEL_S) +#define GPIO_SIG92_IN_SEL_V 0x00000001 +#define GPIO_SIG92_IN_SEL_S 7 + +/* GPIO_FUNC92_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_M (GPIO_FUNC92_IN_INV_SEL_V << GPIO_FUNC92_IN_INV_SEL_S) +#define GPIO_FUNC92_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC92_IN_INV_SEL_S 6 + +/* GPIO_FUNC92_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC92_IN_SEL 0x0000003F +#define GPIO_FUNC92_IN_SEL_M (GPIO_FUNC92_IN_SEL_V << GPIO_FUNC92_IN_SEL_S) +#define GPIO_FUNC92_IN_SEL_V 0x0000003F +#define GPIO_FUNC92_IN_SEL_S 0 + +/* GPIO_FUNC93_IN_SEL_CFG_REG register + * Peripheral function 93 input selection register + */ + +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8) + +/* GPIO_SIG93_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG93_IN_SEL (BIT(7)) +#define GPIO_SIG93_IN_SEL_M (GPIO_SIG93_IN_SEL_V << GPIO_SIG93_IN_SEL_S) +#define GPIO_SIG93_IN_SEL_V 0x00000001 +#define GPIO_SIG93_IN_SEL_S 7 + +/* GPIO_FUNC93_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_M (GPIO_FUNC93_IN_INV_SEL_V << GPIO_FUNC93_IN_INV_SEL_S) +#define GPIO_FUNC93_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC93_IN_INV_SEL_S 6 + +/* GPIO_FUNC93_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC93_IN_SEL 0x0000003F +#define GPIO_FUNC93_IN_SEL_M (GPIO_FUNC93_IN_SEL_V << GPIO_FUNC93_IN_SEL_S) +#define GPIO_FUNC93_IN_SEL_V 0x0000003F +#define GPIO_FUNC93_IN_SEL_S 0 + +/* GPIO_FUNC94_IN_SEL_CFG_REG register + * Peripheral function 94 input selection register + */ + +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc) + +/* GPIO_SIG94_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG94_IN_SEL (BIT(7)) +#define GPIO_SIG94_IN_SEL_M (GPIO_SIG94_IN_SEL_V << GPIO_SIG94_IN_SEL_S) +#define GPIO_SIG94_IN_SEL_V 0x00000001 +#define GPIO_SIG94_IN_SEL_S 7 + +/* GPIO_FUNC94_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_M (GPIO_FUNC94_IN_INV_SEL_V << GPIO_FUNC94_IN_INV_SEL_S) +#define GPIO_FUNC94_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC94_IN_INV_SEL_S 6 + +/* GPIO_FUNC94_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC94_IN_SEL 0x0000003F +#define GPIO_FUNC94_IN_SEL_M (GPIO_FUNC94_IN_SEL_V << GPIO_FUNC94_IN_SEL_S) +#define GPIO_FUNC94_IN_SEL_V 0x0000003F +#define GPIO_FUNC94_IN_SEL_S 0 + +/* GPIO_FUNC95_IN_SEL_CFG_REG register + * Peripheral function 95 input selection register + */ + +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0) + +/* GPIO_SIG95_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG95_IN_SEL (BIT(7)) +#define GPIO_SIG95_IN_SEL_M (GPIO_SIG95_IN_SEL_V << GPIO_SIG95_IN_SEL_S) +#define GPIO_SIG95_IN_SEL_V 0x00000001 +#define GPIO_SIG95_IN_SEL_S 7 + +/* GPIO_FUNC95_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_M (GPIO_FUNC95_IN_INV_SEL_V << GPIO_FUNC95_IN_INV_SEL_S) +#define GPIO_FUNC95_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC95_IN_INV_SEL_S 6 + +/* GPIO_FUNC95_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC95_IN_SEL 0x0000003F +#define GPIO_FUNC95_IN_SEL_M (GPIO_FUNC95_IN_SEL_V << GPIO_FUNC95_IN_SEL_S) +#define GPIO_FUNC95_IN_SEL_V 0x0000003F +#define GPIO_FUNC95_IN_SEL_S 0 + +/* GPIO_FUNC96_IN_SEL_CFG_REG register + * Peripheral function 96 input selection register + */ + +#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4) + +/* GPIO_SIG96_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG96_IN_SEL (BIT(7)) +#define GPIO_SIG96_IN_SEL_M (GPIO_SIG96_IN_SEL_V << GPIO_SIG96_IN_SEL_S) +#define GPIO_SIG96_IN_SEL_V 0x00000001 +#define GPIO_SIG96_IN_SEL_S 7 + +/* GPIO_FUNC96_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC96_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC96_IN_INV_SEL_M (GPIO_FUNC96_IN_INV_SEL_V << GPIO_FUNC96_IN_INV_SEL_S) +#define GPIO_FUNC96_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC96_IN_INV_SEL_S 6 + +/* GPIO_FUNC96_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC96_IN_SEL 0x0000003F +#define GPIO_FUNC96_IN_SEL_M (GPIO_FUNC96_IN_SEL_V << GPIO_FUNC96_IN_SEL_S) +#define GPIO_FUNC96_IN_SEL_V 0x0000003F +#define GPIO_FUNC96_IN_SEL_S 0 + +/* GPIO_FUNC97_IN_SEL_CFG_REG register + * Peripheral function 97 input selection register + */ + +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8) + +/* GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) +#define GPIO_SIG97_IN_SEL_V 0x00000001 +#define GPIO_SIG97_IN_SEL_S 7 + +/* GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) +#define GPIO_FUNC97_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC97_IN_INV_SEL_S 6 + +/* GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC97_IN_SEL 0x0000003F +#define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) +#define GPIO_FUNC97_IN_SEL_V 0x0000003F +#define GPIO_FUNC97_IN_SEL_S 0 + +/* GPIO_FUNC98_IN_SEL_CFG_REG register + * Peripheral function 98 input selection register + */ + +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) + +/* GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) +#define GPIO_SIG98_IN_SEL_V 0x00000001 +#define GPIO_SIG98_IN_SEL_S 7 + +/* GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) +#define GPIO_FUNC98_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC98_IN_INV_SEL_S 6 + +/* GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC98_IN_SEL 0x0000003F +#define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) +#define GPIO_FUNC98_IN_SEL_V 0x0000003F +#define GPIO_FUNC98_IN_SEL_S 0 + +/* GPIO_FUNC99_IN_SEL_CFG_REG register + * Peripheral function 99 input selection register + */ + +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) + +/* GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) +#define GPIO_SIG99_IN_SEL_V 0x00000001 +#define GPIO_SIG99_IN_SEL_S 7 + +/* GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) +#define GPIO_FUNC99_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC99_IN_INV_SEL_S 6 + +/* GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC99_IN_SEL 0x0000003F +#define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) +#define GPIO_FUNC99_IN_SEL_V 0x0000003F +#define GPIO_FUNC99_IN_SEL_S 0 + +/* GPIO_FUNC100_IN_SEL_CFG_REG register + * Peripheral function 100 input selection register + */ + +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) + +/* GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) +#define GPIO_SIG100_IN_SEL_V 0x00000001 +#define GPIO_SIG100_IN_SEL_S 7 + +/* GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) +#define GPIO_FUNC100_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC100_IN_INV_SEL_S 6 + +/* GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC100_IN_SEL 0x0000003F +#define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) +#define GPIO_FUNC100_IN_SEL_V 0x0000003F +#define GPIO_FUNC100_IN_SEL_S 0 + +/* GPIO_FUNC101_IN_SEL_CFG_REG register + * Peripheral function 101 input selection register + */ + +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) + +/* GPIO_SIG101_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG101_IN_SEL (BIT(7)) +#define GPIO_SIG101_IN_SEL_M (GPIO_SIG101_IN_SEL_V << GPIO_SIG101_IN_SEL_S) +#define GPIO_SIG101_IN_SEL_V 0x00000001 +#define GPIO_SIG101_IN_SEL_S 7 + +/* GPIO_FUNC101_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_M (GPIO_FUNC101_IN_INV_SEL_V << GPIO_FUNC101_IN_INV_SEL_S) +#define GPIO_FUNC101_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC101_IN_INV_SEL_S 6 + +/* GPIO_FUNC101_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC101_IN_SEL 0x0000003F +#define GPIO_FUNC101_IN_SEL_M (GPIO_FUNC101_IN_SEL_V << GPIO_FUNC101_IN_SEL_S) +#define GPIO_FUNC101_IN_SEL_V 0x0000003F +#define GPIO_FUNC101_IN_SEL_S 0 + +/* GPIO_FUNC102_IN_SEL_CFG_REG register + * Peripheral function 102 input selection register + */ + +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) + +/* GPIO_SIG102_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG102_IN_SEL (BIT(7)) +#define GPIO_SIG102_IN_SEL_M (GPIO_SIG102_IN_SEL_V << GPIO_SIG102_IN_SEL_S) +#define GPIO_SIG102_IN_SEL_V 0x00000001 +#define GPIO_SIG102_IN_SEL_S 7 + +/* GPIO_FUNC102_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_M (GPIO_FUNC102_IN_INV_SEL_V << GPIO_FUNC102_IN_INV_SEL_S) +#define GPIO_FUNC102_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC102_IN_INV_SEL_S 6 + +/* GPIO_FUNC102_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC102_IN_SEL 0x0000003F +#define GPIO_FUNC102_IN_SEL_M (GPIO_FUNC102_IN_SEL_V << GPIO_FUNC102_IN_SEL_S) +#define GPIO_FUNC102_IN_SEL_V 0x0000003F +#define GPIO_FUNC102_IN_SEL_S 0 + +/* GPIO_FUNC103_IN_SEL_CFG_REG register + * Peripheral function 103 input selection register + */ + +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) + +/* GPIO_SIG103_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG103_IN_SEL (BIT(7)) +#define GPIO_SIG103_IN_SEL_M (GPIO_SIG103_IN_SEL_V << GPIO_SIG103_IN_SEL_S) +#define GPIO_SIG103_IN_SEL_V 0x00000001 +#define GPIO_SIG103_IN_SEL_S 7 + +/* GPIO_FUNC103_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_M (GPIO_FUNC103_IN_INV_SEL_V << GPIO_FUNC103_IN_INV_SEL_S) +#define GPIO_FUNC103_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC103_IN_INV_SEL_S 6 + +/* GPIO_FUNC103_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC103_IN_SEL 0x0000003F +#define GPIO_FUNC103_IN_SEL_M (GPIO_FUNC103_IN_SEL_V << GPIO_FUNC103_IN_SEL_S) +#define GPIO_FUNC103_IN_SEL_V 0x0000003F +#define GPIO_FUNC103_IN_SEL_S 0 + +/* GPIO_FUNC104_IN_SEL_CFG_REG register + * Peripheral function 104 input selection register + */ + +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) + +/* GPIO_SIG104_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG104_IN_SEL (BIT(7)) +#define GPIO_SIG104_IN_SEL_M (GPIO_SIG104_IN_SEL_V << GPIO_SIG104_IN_SEL_S) +#define GPIO_SIG104_IN_SEL_V 0x00000001 +#define GPIO_SIG104_IN_SEL_S 7 + +/* GPIO_FUNC104_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_M (GPIO_FUNC104_IN_INV_SEL_V << GPIO_FUNC104_IN_INV_SEL_S) +#define GPIO_FUNC104_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC104_IN_INV_SEL_S 6 + +/* GPIO_FUNC104_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC104_IN_SEL 0x0000003F +#define GPIO_FUNC104_IN_SEL_M (GPIO_FUNC104_IN_SEL_V << GPIO_FUNC104_IN_SEL_S) +#define GPIO_FUNC104_IN_SEL_V 0x0000003F +#define GPIO_FUNC104_IN_SEL_S 0 + +/* GPIO_FUNC105_IN_SEL_CFG_REG register + * Peripheral function 105 input selection register + */ + +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) + +/* GPIO_SIG105_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG105_IN_SEL (BIT(7)) +#define GPIO_SIG105_IN_SEL_M (GPIO_SIG105_IN_SEL_V << GPIO_SIG105_IN_SEL_S) +#define GPIO_SIG105_IN_SEL_V 0x00000001 +#define GPIO_SIG105_IN_SEL_S 7 + +/* GPIO_FUNC105_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_M (GPIO_FUNC105_IN_INV_SEL_V << GPIO_FUNC105_IN_INV_SEL_S) +#define GPIO_FUNC105_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC105_IN_INV_SEL_S 6 + +/* GPIO_FUNC105_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC105_IN_SEL 0x0000003F +#define GPIO_FUNC105_IN_SEL_M (GPIO_FUNC105_IN_SEL_V << GPIO_FUNC105_IN_SEL_S) +#define GPIO_FUNC105_IN_SEL_V 0x0000003F +#define GPIO_FUNC105_IN_SEL_S 0 + +/* GPIO_FUNC106_IN_SEL_CFG_REG register + * Peripheral function 106 input selection register + */ + +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) + +/* GPIO_SIG106_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG106_IN_SEL (BIT(7)) +#define GPIO_SIG106_IN_SEL_M (GPIO_SIG106_IN_SEL_V << GPIO_SIG106_IN_SEL_S) +#define GPIO_SIG106_IN_SEL_V 0x00000001 +#define GPIO_SIG106_IN_SEL_S 7 + +/* GPIO_FUNC106_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_M (GPIO_FUNC106_IN_INV_SEL_V << GPIO_FUNC106_IN_INV_SEL_S) +#define GPIO_FUNC106_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC106_IN_INV_SEL_S 6 + +/* GPIO_FUNC106_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC106_IN_SEL 0x0000003F +#define GPIO_FUNC106_IN_SEL_M (GPIO_FUNC106_IN_SEL_V << GPIO_FUNC106_IN_SEL_S) +#define GPIO_FUNC106_IN_SEL_V 0x0000003F +#define GPIO_FUNC106_IN_SEL_S 0 + +/* GPIO_FUNC107_IN_SEL_CFG_REG register + * Peripheral function 107 input selection register + */ + +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) + +/* GPIO_SIG107_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG107_IN_SEL (BIT(7)) +#define GPIO_SIG107_IN_SEL_M (GPIO_SIG107_IN_SEL_V << GPIO_SIG107_IN_SEL_S) +#define GPIO_SIG107_IN_SEL_V 0x00000001 +#define GPIO_SIG107_IN_SEL_S 7 + +/* GPIO_FUNC107_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_M (GPIO_FUNC107_IN_INV_SEL_V << GPIO_FUNC107_IN_INV_SEL_S) +#define GPIO_FUNC107_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC107_IN_INV_SEL_S 6 + +/* GPIO_FUNC107_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC107_IN_SEL 0x0000003F +#define GPIO_FUNC107_IN_SEL_M (GPIO_FUNC107_IN_SEL_V << GPIO_FUNC107_IN_SEL_S) +#define GPIO_FUNC107_IN_SEL_V 0x0000003F +#define GPIO_FUNC107_IN_SEL_S 0 + +/* GPIO_FUNC108_IN_SEL_CFG_REG register + * Peripheral function 108 input selection register + */ + +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) + +/* GPIO_SIG108_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG108_IN_SEL (BIT(7)) +#define GPIO_SIG108_IN_SEL_M (GPIO_SIG108_IN_SEL_V << GPIO_SIG108_IN_SEL_S) +#define GPIO_SIG108_IN_SEL_V 0x00000001 +#define GPIO_SIG108_IN_SEL_S 7 + +/* GPIO_FUNC108_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_M (GPIO_FUNC108_IN_INV_SEL_V << GPIO_FUNC108_IN_INV_SEL_S) +#define GPIO_FUNC108_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC108_IN_INV_SEL_S 6 + +/* GPIO_FUNC108_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC108_IN_SEL 0x0000003F +#define GPIO_FUNC108_IN_SEL_M (GPIO_FUNC108_IN_SEL_V << GPIO_FUNC108_IN_SEL_S) +#define GPIO_FUNC108_IN_SEL_V 0x0000003F +#define GPIO_FUNC108_IN_SEL_S 0 + +/* GPIO_FUNC109_IN_SEL_CFG_REG register + * Peripheral function 109 input selection register + */ + +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) + +/* GPIO_SIG109_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG109_IN_SEL (BIT(7)) +#define GPIO_SIG109_IN_SEL_M (GPIO_SIG109_IN_SEL_V << GPIO_SIG109_IN_SEL_S) +#define GPIO_SIG109_IN_SEL_V 0x00000001 +#define GPIO_SIG109_IN_SEL_S 7 + +/* GPIO_FUNC109_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_M (GPIO_FUNC109_IN_INV_SEL_V << GPIO_FUNC109_IN_INV_SEL_S) +#define GPIO_FUNC109_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC109_IN_INV_SEL_S 6 + +/* GPIO_FUNC109_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC109_IN_SEL 0x0000003F +#define GPIO_FUNC109_IN_SEL_M (GPIO_FUNC109_IN_SEL_V << GPIO_FUNC109_IN_SEL_S) +#define GPIO_FUNC109_IN_SEL_V 0x0000003F +#define GPIO_FUNC109_IN_SEL_S 0 + +/* GPIO_FUNC110_IN_SEL_CFG_REG register + * Peripheral function 110 input selection register + */ + +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) + +/* GPIO_SIG110_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG110_IN_SEL (BIT(7)) +#define GPIO_SIG110_IN_SEL_M (GPIO_SIG110_IN_SEL_V << GPIO_SIG110_IN_SEL_S) +#define GPIO_SIG110_IN_SEL_V 0x00000001 +#define GPIO_SIG110_IN_SEL_S 7 + +/* GPIO_FUNC110_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_M (GPIO_FUNC110_IN_INV_SEL_V << GPIO_FUNC110_IN_INV_SEL_S) +#define GPIO_FUNC110_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC110_IN_INV_SEL_S 6 + +/* GPIO_FUNC110_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC110_IN_SEL 0x0000003F +#define GPIO_FUNC110_IN_SEL_M (GPIO_FUNC110_IN_SEL_V << GPIO_FUNC110_IN_SEL_S) +#define GPIO_FUNC110_IN_SEL_V 0x0000003F +#define GPIO_FUNC110_IN_SEL_S 0 + +/* GPIO_FUNC111_IN_SEL_CFG_REG register + * Peripheral function 111 input selection register + */ + +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) + +/* GPIO_SIG111_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG111_IN_SEL (BIT(7)) +#define GPIO_SIG111_IN_SEL_M (GPIO_SIG111_IN_SEL_V << GPIO_SIG111_IN_SEL_S) +#define GPIO_SIG111_IN_SEL_V 0x00000001 +#define GPIO_SIG111_IN_SEL_S 7 + +/* GPIO_FUNC111_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_M (GPIO_FUNC111_IN_INV_SEL_V << GPIO_FUNC111_IN_INV_SEL_S) +#define GPIO_FUNC111_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC111_IN_INV_SEL_S 6 + +/* GPIO_FUNC111_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC111_IN_SEL 0x0000003F +#define GPIO_FUNC111_IN_SEL_M (GPIO_FUNC111_IN_SEL_V << GPIO_FUNC111_IN_SEL_S) +#define GPIO_FUNC111_IN_SEL_V 0x0000003F +#define GPIO_FUNC111_IN_SEL_S 0 + +/* GPIO_FUNC112_IN_SEL_CFG_REG register + * Peripheral function 112 input selection register + */ + +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) + +/* GPIO_SIG112_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG112_IN_SEL (BIT(7)) +#define GPIO_SIG112_IN_SEL_M (GPIO_SIG112_IN_SEL_V << GPIO_SIG112_IN_SEL_S) +#define GPIO_SIG112_IN_SEL_V 0x00000001 +#define GPIO_SIG112_IN_SEL_S 7 + +/* GPIO_FUNC112_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_M (GPIO_FUNC112_IN_INV_SEL_V << GPIO_FUNC112_IN_INV_SEL_S) +#define GPIO_FUNC112_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC112_IN_INV_SEL_S 6 + +/* GPIO_FUNC112_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC112_IN_SEL 0x0000003F +#define GPIO_FUNC112_IN_SEL_M (GPIO_FUNC112_IN_SEL_V << GPIO_FUNC112_IN_SEL_S) +#define GPIO_FUNC112_IN_SEL_V 0x0000003F +#define GPIO_FUNC112_IN_SEL_S 0 + +/* GPIO_FUNC113_IN_SEL_CFG_REG register + * Peripheral function 113 input selection register + */ + +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) + +/* GPIO_SIG113_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG113_IN_SEL (BIT(7)) +#define GPIO_SIG113_IN_SEL_M (GPIO_SIG113_IN_SEL_V << GPIO_SIG113_IN_SEL_S) +#define GPIO_SIG113_IN_SEL_V 0x00000001 +#define GPIO_SIG113_IN_SEL_S 7 + +/* GPIO_FUNC113_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_M (GPIO_FUNC113_IN_INV_SEL_V << GPIO_FUNC113_IN_INV_SEL_S) +#define GPIO_FUNC113_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC113_IN_INV_SEL_S 6 + +/* GPIO_FUNC113_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC113_IN_SEL 0x0000003F +#define GPIO_FUNC113_IN_SEL_M (GPIO_FUNC113_IN_SEL_V << GPIO_FUNC113_IN_SEL_S) +#define GPIO_FUNC113_IN_SEL_V 0x0000003F +#define GPIO_FUNC113_IN_SEL_S 0 + +/* GPIO_FUNC114_IN_SEL_CFG_REG register + * Peripheral function 114 input selection register + */ + +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c) + +/* GPIO_SIG114_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG114_IN_SEL (BIT(7)) +#define GPIO_SIG114_IN_SEL_M (GPIO_SIG114_IN_SEL_V << GPIO_SIG114_IN_SEL_S) +#define GPIO_SIG114_IN_SEL_V 0x00000001 +#define GPIO_SIG114_IN_SEL_S 7 + +/* GPIO_FUNC114_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_M (GPIO_FUNC114_IN_INV_SEL_V << GPIO_FUNC114_IN_INV_SEL_S) +#define GPIO_FUNC114_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC114_IN_INV_SEL_S 6 + +/* GPIO_FUNC114_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC114_IN_SEL 0x0000003F +#define GPIO_FUNC114_IN_SEL_M (GPIO_FUNC114_IN_SEL_V << GPIO_FUNC114_IN_SEL_S) +#define GPIO_FUNC114_IN_SEL_V 0x0000003F +#define GPIO_FUNC114_IN_SEL_S 0 + +/* GPIO_FUNC115_IN_SEL_CFG_REG register + * Peripheral function 115 input selection register + */ + +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) + +/* GPIO_SIG115_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG115_IN_SEL (BIT(7)) +#define GPIO_SIG115_IN_SEL_M (GPIO_SIG115_IN_SEL_V << GPIO_SIG115_IN_SEL_S) +#define GPIO_SIG115_IN_SEL_V 0x00000001 +#define GPIO_SIG115_IN_SEL_S 7 + +/* GPIO_FUNC115_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_M (GPIO_FUNC115_IN_INV_SEL_V << GPIO_FUNC115_IN_INV_SEL_S) +#define GPIO_FUNC115_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC115_IN_INV_SEL_S 6 + +/* GPIO_FUNC115_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC115_IN_SEL 0x0000003F +#define GPIO_FUNC115_IN_SEL_M (GPIO_FUNC115_IN_SEL_V << GPIO_FUNC115_IN_SEL_S) +#define GPIO_FUNC115_IN_SEL_V 0x0000003F +#define GPIO_FUNC115_IN_SEL_S 0 + +/* GPIO_FUNC116_IN_SEL_CFG_REG register + * Peripheral function 116 input selection register + */ + +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) + +/* GPIO_SIG116_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG116_IN_SEL (BIT(7)) +#define GPIO_SIG116_IN_SEL_M (GPIO_SIG116_IN_SEL_V << GPIO_SIG116_IN_SEL_S) +#define GPIO_SIG116_IN_SEL_V 0x00000001 +#define GPIO_SIG116_IN_SEL_S 7 + +/* GPIO_FUNC116_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_M (GPIO_FUNC116_IN_INV_SEL_V << GPIO_FUNC116_IN_INV_SEL_S) +#define GPIO_FUNC116_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC116_IN_INV_SEL_S 6 + +/* GPIO_FUNC116_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC116_IN_SEL 0x0000003F +#define GPIO_FUNC116_IN_SEL_M (GPIO_FUNC116_IN_SEL_V << GPIO_FUNC116_IN_SEL_S) +#define GPIO_FUNC116_IN_SEL_V 0x0000003F +#define GPIO_FUNC116_IN_SEL_S 0 + +/* GPIO_FUNC117_IN_SEL_CFG_REG register + * Peripheral function 117 input selection register + */ + +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) + +/* GPIO_SIG117_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG117_IN_SEL (BIT(7)) +#define GPIO_SIG117_IN_SEL_M (GPIO_SIG117_IN_SEL_V << GPIO_SIG117_IN_SEL_S) +#define GPIO_SIG117_IN_SEL_V 0x00000001 +#define GPIO_SIG117_IN_SEL_S 7 + +/* GPIO_FUNC117_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_M (GPIO_FUNC117_IN_INV_SEL_V << GPIO_FUNC117_IN_INV_SEL_S) +#define GPIO_FUNC117_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC117_IN_INV_SEL_S 6 + +/* GPIO_FUNC117_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC117_IN_SEL 0x0000003F +#define GPIO_FUNC117_IN_SEL_M (GPIO_FUNC117_IN_SEL_V << GPIO_FUNC117_IN_SEL_S) +#define GPIO_FUNC117_IN_SEL_V 0x0000003F +#define GPIO_FUNC117_IN_SEL_S 0 + +/* GPIO_FUNC118_IN_SEL_CFG_REG register + * Peripheral function 118 input selection register + */ + +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c) + +/* GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL_M (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S) +#define GPIO_SIG118_IN_SEL_V 0x00000001 +#define GPIO_SIG118_IN_SEL_S 7 + +/* GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_M (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S) +#define GPIO_FUNC118_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC118_IN_INV_SEL_S 6 + +/* GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC118_IN_SEL 0x0000003F +#define GPIO_FUNC118_IN_SEL_M (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S) +#define GPIO_FUNC118_IN_SEL_V 0x0000003F +#define GPIO_FUNC118_IN_SEL_S 0 + +/* GPIO_FUNC119_IN_SEL_CFG_REG register + * Peripheral function 119 input selection register + */ + +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) + +/* GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL_M (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S) +#define GPIO_SIG119_IN_SEL_V 0x00000001 +#define GPIO_SIG119_IN_SEL_S 7 + +/* GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_M (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S) +#define GPIO_FUNC119_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC119_IN_INV_SEL_S 6 + +/* GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC119_IN_SEL 0x0000003F +#define GPIO_FUNC119_IN_SEL_M (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S) +#define GPIO_FUNC119_IN_SEL_V 0x0000003F +#define GPIO_FUNC119_IN_SEL_S 0 + +/* GPIO_FUNC120_IN_SEL_CFG_REG register + * Peripheral function 120 input selection register + */ + +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) + +/* GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL_M (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S) +#define GPIO_SIG120_IN_SEL_V 0x00000001 +#define GPIO_SIG120_IN_SEL_S 7 + +/* GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_M (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S) +#define GPIO_FUNC120_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC120_IN_INV_SEL_S 6 + +/* GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC120_IN_SEL 0x0000003F +#define GPIO_FUNC120_IN_SEL_M (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S) +#define GPIO_FUNC120_IN_SEL_V 0x0000003F +#define GPIO_FUNC120_IN_SEL_S 0 + +/* GPIO_FUNC121_IN_SEL_CFG_REG register + * Peripheral function 121 input selection register + */ + +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) + +/* GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL_M (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S) +#define GPIO_SIG121_IN_SEL_V 0x00000001 +#define GPIO_SIG121_IN_SEL_S 7 + +/* GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_M (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S) +#define GPIO_FUNC121_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC121_IN_INV_SEL_S 6 + +/* GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC121_IN_SEL 0x0000003F +#define GPIO_FUNC121_IN_SEL_M (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S) +#define GPIO_FUNC121_IN_SEL_V 0x0000003F +#define GPIO_FUNC121_IN_SEL_S 0 + +/* GPIO_FUNC122_IN_SEL_CFG_REG register + * Peripheral function 122 input selection register + */ + +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) + +/* GPIO_SIG122_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG122_IN_SEL (BIT(7)) +#define GPIO_SIG122_IN_SEL_M (GPIO_SIG122_IN_SEL_V << GPIO_SIG122_IN_SEL_S) +#define GPIO_SIG122_IN_SEL_V 0x00000001 +#define GPIO_SIG122_IN_SEL_S 7 + +/* GPIO_FUNC122_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_M (GPIO_FUNC122_IN_INV_SEL_V << GPIO_FUNC122_IN_INV_SEL_S) +#define GPIO_FUNC122_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC122_IN_INV_SEL_S 6 + +/* GPIO_FUNC122_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC122_IN_SEL 0x0000003F +#define GPIO_FUNC122_IN_SEL_M (GPIO_FUNC122_IN_SEL_V << GPIO_FUNC122_IN_SEL_S) +#define GPIO_FUNC122_IN_SEL_V 0x0000003F +#define GPIO_FUNC122_IN_SEL_S 0 + +/* GPIO_FUNC123_IN_SEL_CFG_REG register + * Peripheral function 123 input selection register + */ + +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) + +/* GPIO_SIG123_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG123_IN_SEL (BIT(7)) +#define GPIO_SIG123_IN_SEL_M (GPIO_SIG123_IN_SEL_V << GPIO_SIG123_IN_SEL_S) +#define GPIO_SIG123_IN_SEL_V 0x00000001 +#define GPIO_SIG123_IN_SEL_S 7 + +/* GPIO_FUNC123_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_M (GPIO_FUNC123_IN_INV_SEL_V << GPIO_FUNC123_IN_INV_SEL_S) +#define GPIO_FUNC123_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC123_IN_INV_SEL_S 6 + +/* GPIO_FUNC123_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC123_IN_SEL 0x0000003F +#define GPIO_FUNC123_IN_SEL_M (GPIO_FUNC123_IN_SEL_V << GPIO_FUNC123_IN_SEL_S) +#define GPIO_FUNC123_IN_SEL_V 0x0000003F +#define GPIO_FUNC123_IN_SEL_S 0 + +/* GPIO_FUNC124_IN_SEL_CFG_REG register + * Peripheral function 124 input selection register + */ + +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) + +/* GPIO_SIG124_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG124_IN_SEL (BIT(7)) +#define GPIO_SIG124_IN_SEL_M (GPIO_SIG124_IN_SEL_V << GPIO_SIG124_IN_SEL_S) +#define GPIO_SIG124_IN_SEL_V 0x00000001 +#define GPIO_SIG124_IN_SEL_S 7 + +/* GPIO_FUNC124_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_M (GPIO_FUNC124_IN_INV_SEL_V << GPIO_FUNC124_IN_INV_SEL_S) +#define GPIO_FUNC124_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC124_IN_INV_SEL_S 6 + +/* GPIO_FUNC124_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC124_IN_SEL 0x0000003F +#define GPIO_FUNC124_IN_SEL_M (GPIO_FUNC124_IN_SEL_V << GPIO_FUNC124_IN_SEL_S) +#define GPIO_FUNC124_IN_SEL_V 0x0000003F +#define GPIO_FUNC124_IN_SEL_S 0 + +/* GPIO_FUNC125_IN_SEL_CFG_REG register + * Peripheral function 125 input selection register + */ + +#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) + +/* GPIO_SIG125_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG125_IN_SEL (BIT(7)) +#define GPIO_SIG125_IN_SEL_M (GPIO_SIG125_IN_SEL_V << GPIO_SIG125_IN_SEL_S) +#define GPIO_SIG125_IN_SEL_V 0x00000001 +#define GPIO_SIG125_IN_SEL_S 7 + +/* GPIO_FUNC125_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC125_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC125_IN_INV_SEL_M (GPIO_FUNC125_IN_INV_SEL_V << GPIO_FUNC125_IN_INV_SEL_S) +#define GPIO_FUNC125_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC125_IN_INV_SEL_S 6 + +/* GPIO_FUNC125_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC125_IN_SEL 0x0000003F +#define GPIO_FUNC125_IN_SEL_M (GPIO_FUNC125_IN_SEL_V << GPIO_FUNC125_IN_SEL_S) +#define GPIO_FUNC125_IN_SEL_V 0x0000003F +#define GPIO_FUNC125_IN_SEL_S 0 + +/* GPIO_FUNC126_IN_SEL_CFG_REG register + * Peripheral function 126 input selection register + */ + +#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) + +/* GPIO_SIG126_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG126_IN_SEL (BIT(7)) +#define GPIO_SIG126_IN_SEL_M (GPIO_SIG126_IN_SEL_V << GPIO_SIG126_IN_SEL_S) +#define GPIO_SIG126_IN_SEL_V 0x00000001 +#define GPIO_SIG126_IN_SEL_S 7 + +/* GPIO_FUNC126_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC126_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC126_IN_INV_SEL_M (GPIO_FUNC126_IN_INV_SEL_V << GPIO_FUNC126_IN_INV_SEL_S) +#define GPIO_FUNC126_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC126_IN_INV_SEL_S 6 + +/* GPIO_FUNC126_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC126_IN_SEL 0x0000003F +#define GPIO_FUNC126_IN_SEL_M (GPIO_FUNC126_IN_SEL_V << GPIO_FUNC126_IN_SEL_S) +#define GPIO_FUNC126_IN_SEL_V 0x0000003F +#define GPIO_FUNC126_IN_SEL_S 0 + +/* GPIO_FUNC127_IN_SEL_CFG_REG register + * Peripheral function 127 input selection register + */ + +#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) + +/* GPIO_SIG127_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG127_IN_SEL (BIT(7)) +#define GPIO_SIG127_IN_SEL_M (GPIO_SIG127_IN_SEL_V << GPIO_SIG127_IN_SEL_S) +#define GPIO_SIG127_IN_SEL_V 0x00000001 +#define GPIO_SIG127_IN_SEL_S 7 + +/* GPIO_FUNC127_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC127_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC127_IN_INV_SEL_M (GPIO_FUNC127_IN_INV_SEL_V << GPIO_FUNC127_IN_INV_SEL_S) +#define GPIO_FUNC127_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC127_IN_INV_SEL_S 6 + +/* GPIO_FUNC127_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC127_IN_SEL 0x0000003F +#define GPIO_FUNC127_IN_SEL_M (GPIO_FUNC127_IN_SEL_V << GPIO_FUNC127_IN_SEL_S) +#define GPIO_FUNC127_IN_SEL_V 0x0000003F +#define GPIO_FUNC127_IN_SEL_S 0 + +/* GPIO_FUNC128_IN_SEL_CFG_REG register + * Peripheral function 128 input selection register + */ + +#define GPIO_FUNC128_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x354) + +/* GPIO_SIG128_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG128_IN_SEL (BIT(7)) +#define GPIO_SIG128_IN_SEL_M (GPIO_SIG128_IN_SEL_V << GPIO_SIG128_IN_SEL_S) +#define GPIO_SIG128_IN_SEL_V 0x00000001 +#define GPIO_SIG128_IN_SEL_S 7 + +/* GPIO_FUNC128_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC128_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC128_IN_INV_SEL_M (GPIO_FUNC128_IN_INV_SEL_V << GPIO_FUNC128_IN_INV_SEL_S) +#define GPIO_FUNC128_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC128_IN_INV_SEL_S 6 + +/* GPIO_FUNC128_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC128_IN_SEL 0x0000003F +#define GPIO_FUNC128_IN_SEL_M (GPIO_FUNC128_IN_SEL_V << GPIO_FUNC128_IN_SEL_S) +#define GPIO_FUNC128_IN_SEL_V 0x0000003F +#define GPIO_FUNC128_IN_SEL_S 0 + +/* GPIO_FUNC129_IN_SEL_CFG_REG register + * Peripheral function 129 input selection register + */ + +#define GPIO_FUNC129_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x358) + +/* GPIO_SIG129_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG129_IN_SEL (BIT(7)) +#define GPIO_SIG129_IN_SEL_M (GPIO_SIG129_IN_SEL_V << GPIO_SIG129_IN_SEL_S) +#define GPIO_SIG129_IN_SEL_V 0x00000001 +#define GPIO_SIG129_IN_SEL_S 7 + +/* GPIO_FUNC129_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC129_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC129_IN_INV_SEL_M (GPIO_FUNC129_IN_INV_SEL_V << GPIO_FUNC129_IN_INV_SEL_S) +#define GPIO_FUNC129_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC129_IN_INV_SEL_S 6 + +/* GPIO_FUNC129_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC129_IN_SEL 0x0000003F +#define GPIO_FUNC129_IN_SEL_M (GPIO_FUNC129_IN_SEL_V << GPIO_FUNC129_IN_SEL_S) +#define GPIO_FUNC129_IN_SEL_V 0x0000003F +#define GPIO_FUNC129_IN_SEL_S 0 + +/* GPIO_FUNC130_IN_SEL_CFG_REG register + * Peripheral function 130 input selection register + */ + +#define GPIO_FUNC130_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x35c) + +/* GPIO_SIG130_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG130_IN_SEL (BIT(7)) +#define GPIO_SIG130_IN_SEL_M (GPIO_SIG130_IN_SEL_V << GPIO_SIG130_IN_SEL_S) +#define GPIO_SIG130_IN_SEL_V 0x00000001 +#define GPIO_SIG130_IN_SEL_S 7 + +/* GPIO_FUNC130_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC130_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC130_IN_INV_SEL_M (GPIO_FUNC130_IN_INV_SEL_V << GPIO_FUNC130_IN_INV_SEL_S) +#define GPIO_FUNC130_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC130_IN_INV_SEL_S 6 + +/* GPIO_FUNC130_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC130_IN_SEL 0x0000003F +#define GPIO_FUNC130_IN_SEL_M (GPIO_FUNC130_IN_SEL_V << GPIO_FUNC130_IN_SEL_S) +#define GPIO_FUNC130_IN_SEL_V 0x0000003F +#define GPIO_FUNC130_IN_SEL_S 0 + +/* GPIO_FUNC131_IN_SEL_CFG_REG register + * Peripheral function 131 input selection register + */ + +#define GPIO_FUNC131_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x360) + +/* GPIO_SIG131_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG131_IN_SEL (BIT(7)) +#define GPIO_SIG131_IN_SEL_M (GPIO_SIG131_IN_SEL_V << GPIO_SIG131_IN_SEL_S) +#define GPIO_SIG131_IN_SEL_V 0x00000001 +#define GPIO_SIG131_IN_SEL_S 7 + +/* GPIO_FUNC131_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC131_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC131_IN_INV_SEL_M (GPIO_FUNC131_IN_INV_SEL_V << GPIO_FUNC131_IN_INV_SEL_S) +#define GPIO_FUNC131_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC131_IN_INV_SEL_S 6 + +/* GPIO_FUNC131_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC131_IN_SEL 0x0000003F +#define GPIO_FUNC131_IN_SEL_M (GPIO_FUNC131_IN_SEL_V << GPIO_FUNC131_IN_SEL_S) +#define GPIO_FUNC131_IN_SEL_V 0x0000003F +#define GPIO_FUNC131_IN_SEL_S 0 + +/* GPIO_FUNC132_IN_SEL_CFG_REG register + * Peripheral function 132 input selection register + */ + +#define GPIO_FUNC132_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x364) + +/* GPIO_SIG132_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG132_IN_SEL (BIT(7)) +#define GPIO_SIG132_IN_SEL_M (GPIO_SIG132_IN_SEL_V << GPIO_SIG132_IN_SEL_S) +#define GPIO_SIG132_IN_SEL_V 0x00000001 +#define GPIO_SIG132_IN_SEL_S 7 + +/* GPIO_FUNC132_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC132_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC132_IN_INV_SEL_M (GPIO_FUNC132_IN_INV_SEL_V << GPIO_FUNC132_IN_INV_SEL_S) +#define GPIO_FUNC132_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC132_IN_INV_SEL_S 6 + +/* GPIO_FUNC132_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC132_IN_SEL 0x0000003F +#define GPIO_FUNC132_IN_SEL_M (GPIO_FUNC132_IN_SEL_V << GPIO_FUNC132_IN_SEL_S) +#define GPIO_FUNC132_IN_SEL_V 0x0000003F +#define GPIO_FUNC132_IN_SEL_S 0 + +/* GPIO_FUNC133_IN_SEL_CFG_REG register + * Peripheral function 133 input selection register + */ + +#define GPIO_FUNC133_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x368) + +/* GPIO_SIG133_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG133_IN_SEL (BIT(7)) +#define GPIO_SIG133_IN_SEL_M (GPIO_SIG133_IN_SEL_V << GPIO_SIG133_IN_SEL_S) +#define GPIO_SIG133_IN_SEL_V 0x00000001 +#define GPIO_SIG133_IN_SEL_S 7 + +/* GPIO_FUNC133_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC133_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC133_IN_INV_SEL_M (GPIO_FUNC133_IN_INV_SEL_V << GPIO_FUNC133_IN_INV_SEL_S) +#define GPIO_FUNC133_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC133_IN_INV_SEL_S 6 + +/* GPIO_FUNC133_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC133_IN_SEL 0x0000003F +#define GPIO_FUNC133_IN_SEL_M (GPIO_FUNC133_IN_SEL_V << GPIO_FUNC133_IN_SEL_S) +#define GPIO_FUNC133_IN_SEL_V 0x0000003F +#define GPIO_FUNC133_IN_SEL_S 0 + +/* GPIO_FUNC134_IN_SEL_CFG_REG register + * Peripheral function 134 input selection register + */ + +#define GPIO_FUNC134_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x36c) + +/* GPIO_SIG134_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG134_IN_SEL (BIT(7)) +#define GPIO_SIG134_IN_SEL_M (GPIO_SIG134_IN_SEL_V << GPIO_SIG134_IN_SEL_S) +#define GPIO_SIG134_IN_SEL_V 0x00000001 +#define GPIO_SIG134_IN_SEL_S 7 + +/* GPIO_FUNC134_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC134_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC134_IN_INV_SEL_M (GPIO_FUNC134_IN_INV_SEL_V << GPIO_FUNC134_IN_INV_SEL_S) +#define GPIO_FUNC134_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC134_IN_INV_SEL_S 6 + +/* GPIO_FUNC134_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC134_IN_SEL 0x0000003F +#define GPIO_FUNC134_IN_SEL_M (GPIO_FUNC134_IN_SEL_V << GPIO_FUNC134_IN_SEL_S) +#define GPIO_FUNC134_IN_SEL_V 0x0000003F +#define GPIO_FUNC134_IN_SEL_S 0 + +/* GPIO_FUNC135_IN_SEL_CFG_REG register + * Peripheral function 135 input selection register + */ + +#define GPIO_FUNC135_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x370) + +/* GPIO_SIG135_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG135_IN_SEL (BIT(7)) +#define GPIO_SIG135_IN_SEL_M (GPIO_SIG135_IN_SEL_V << GPIO_SIG135_IN_SEL_S) +#define GPIO_SIG135_IN_SEL_V 0x00000001 +#define GPIO_SIG135_IN_SEL_S 7 + +/* GPIO_FUNC135_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC135_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC135_IN_INV_SEL_M (GPIO_FUNC135_IN_INV_SEL_V << GPIO_FUNC135_IN_INV_SEL_S) +#define GPIO_FUNC135_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC135_IN_INV_SEL_S 6 + +/* GPIO_FUNC135_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC135_IN_SEL 0x0000003F +#define GPIO_FUNC135_IN_SEL_M (GPIO_FUNC135_IN_SEL_V << GPIO_FUNC135_IN_SEL_S) +#define GPIO_FUNC135_IN_SEL_V 0x0000003F +#define GPIO_FUNC135_IN_SEL_S 0 + +/* GPIO_FUNC136_IN_SEL_CFG_REG register + * Peripheral function 136 input selection register + */ + +#define GPIO_FUNC136_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x374) + +/* GPIO_SIG136_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG136_IN_SEL (BIT(7)) +#define GPIO_SIG136_IN_SEL_M (GPIO_SIG136_IN_SEL_V << GPIO_SIG136_IN_SEL_S) +#define GPIO_SIG136_IN_SEL_V 0x00000001 +#define GPIO_SIG136_IN_SEL_S 7 + +/* GPIO_FUNC136_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC136_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC136_IN_INV_SEL_M (GPIO_FUNC136_IN_INV_SEL_V << GPIO_FUNC136_IN_INV_SEL_S) +#define GPIO_FUNC136_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC136_IN_INV_SEL_S 6 + +/* GPIO_FUNC136_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC136_IN_SEL 0x0000003F +#define GPIO_FUNC136_IN_SEL_M (GPIO_FUNC136_IN_SEL_V << GPIO_FUNC136_IN_SEL_S) +#define GPIO_FUNC136_IN_SEL_V 0x0000003F +#define GPIO_FUNC136_IN_SEL_S 0 + +/* GPIO_FUNC137_IN_SEL_CFG_REG register + * Peripheral function 137 input selection register + */ + +#define GPIO_FUNC137_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x378) + +/* GPIO_SIG137_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG137_IN_SEL (BIT(7)) +#define GPIO_SIG137_IN_SEL_M (GPIO_SIG137_IN_SEL_V << GPIO_SIG137_IN_SEL_S) +#define GPIO_SIG137_IN_SEL_V 0x00000001 +#define GPIO_SIG137_IN_SEL_S 7 + +/* GPIO_FUNC137_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC137_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC137_IN_INV_SEL_M (GPIO_FUNC137_IN_INV_SEL_V << GPIO_FUNC137_IN_INV_SEL_S) +#define GPIO_FUNC137_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC137_IN_INV_SEL_S 6 + +/* GPIO_FUNC137_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC137_IN_SEL 0x0000003F +#define GPIO_FUNC137_IN_SEL_M (GPIO_FUNC137_IN_SEL_V << GPIO_FUNC137_IN_SEL_S) +#define GPIO_FUNC137_IN_SEL_V 0x0000003F +#define GPIO_FUNC137_IN_SEL_S 0 + +/* GPIO_FUNC138_IN_SEL_CFG_REG register + * Peripheral function 138 input selection register + */ + +#define GPIO_FUNC138_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c) + +/* GPIO_SIG138_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG138_IN_SEL (BIT(7)) +#define GPIO_SIG138_IN_SEL_M (GPIO_SIG138_IN_SEL_V << GPIO_SIG138_IN_SEL_S) +#define GPIO_SIG138_IN_SEL_V 0x00000001 +#define GPIO_SIG138_IN_SEL_S 7 + +/* GPIO_FUNC138_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC138_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC138_IN_INV_SEL_M (GPIO_FUNC138_IN_INV_SEL_V << GPIO_FUNC138_IN_INV_SEL_S) +#define GPIO_FUNC138_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC138_IN_INV_SEL_S 6 + +/* GPIO_FUNC138_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC138_IN_SEL 0x0000003F +#define GPIO_FUNC138_IN_SEL_M (GPIO_FUNC138_IN_SEL_V << GPIO_FUNC138_IN_SEL_S) +#define GPIO_FUNC138_IN_SEL_V 0x0000003F +#define GPIO_FUNC138_IN_SEL_S 0 + +/* GPIO_FUNC139_IN_SEL_CFG_REG register + * Peripheral function 139 input selection register + */ + +#define GPIO_FUNC139_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380) + +/* GPIO_SIG139_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG139_IN_SEL (BIT(7)) +#define GPIO_SIG139_IN_SEL_M (GPIO_SIG139_IN_SEL_V << GPIO_SIG139_IN_SEL_S) +#define GPIO_SIG139_IN_SEL_V 0x00000001 +#define GPIO_SIG139_IN_SEL_S 7 + +/* GPIO_FUNC139_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC139_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC139_IN_INV_SEL_M (GPIO_FUNC139_IN_INV_SEL_V << GPIO_FUNC139_IN_INV_SEL_S) +#define GPIO_FUNC139_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC139_IN_INV_SEL_S 6 + +/* GPIO_FUNC139_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC139_IN_SEL 0x0000003F +#define GPIO_FUNC139_IN_SEL_M (GPIO_FUNC139_IN_SEL_V << GPIO_FUNC139_IN_SEL_S) +#define GPIO_FUNC139_IN_SEL_V 0x0000003F +#define GPIO_FUNC139_IN_SEL_S 0 + +/* GPIO_FUNC140_IN_SEL_CFG_REG register + * Peripheral function 140 input selection register + */ + +#define GPIO_FUNC140_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x384) + +/* GPIO_SIG140_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG140_IN_SEL (BIT(7)) +#define GPIO_SIG140_IN_SEL_M (GPIO_SIG140_IN_SEL_V << GPIO_SIG140_IN_SEL_S) +#define GPIO_SIG140_IN_SEL_V 0x00000001 +#define GPIO_SIG140_IN_SEL_S 7 + +/* GPIO_FUNC140_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC140_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC140_IN_INV_SEL_M (GPIO_FUNC140_IN_INV_SEL_V << GPIO_FUNC140_IN_INV_SEL_S) +#define GPIO_FUNC140_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC140_IN_INV_SEL_S 6 + +/* GPIO_FUNC140_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC140_IN_SEL 0x0000003F +#define GPIO_FUNC140_IN_SEL_M (GPIO_FUNC140_IN_SEL_V << GPIO_FUNC140_IN_SEL_S) +#define GPIO_FUNC140_IN_SEL_V 0x0000003F +#define GPIO_FUNC140_IN_SEL_S 0 + +/* GPIO_FUNC141_IN_SEL_CFG_REG register + * Peripheral function 141 input selection register + */ + +#define GPIO_FUNC141_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x388) + +/* GPIO_SIG141_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG141_IN_SEL (BIT(7)) +#define GPIO_SIG141_IN_SEL_M (GPIO_SIG141_IN_SEL_V << GPIO_SIG141_IN_SEL_S) +#define GPIO_SIG141_IN_SEL_V 0x00000001 +#define GPIO_SIG141_IN_SEL_S 7 + +/* GPIO_FUNC141_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC141_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC141_IN_INV_SEL_M (GPIO_FUNC141_IN_INV_SEL_V << GPIO_FUNC141_IN_INV_SEL_S) +#define GPIO_FUNC141_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC141_IN_INV_SEL_S 6 + +/* GPIO_FUNC141_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC141_IN_SEL 0x0000003F +#define GPIO_FUNC141_IN_SEL_M (GPIO_FUNC141_IN_SEL_V << GPIO_FUNC141_IN_SEL_S) +#define GPIO_FUNC141_IN_SEL_V 0x0000003F +#define GPIO_FUNC141_IN_SEL_S 0 + +/* GPIO_FUNC142_IN_SEL_CFG_REG register + * Peripheral function 142 input selection register + */ + +#define GPIO_FUNC142_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x38c) + +/* GPIO_SIG142_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG142_IN_SEL (BIT(7)) +#define GPIO_SIG142_IN_SEL_M (GPIO_SIG142_IN_SEL_V << GPIO_SIG142_IN_SEL_S) +#define GPIO_SIG142_IN_SEL_V 0x00000001 +#define GPIO_SIG142_IN_SEL_S 7 + +/* GPIO_FUNC142_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC142_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC142_IN_INV_SEL_M (GPIO_FUNC142_IN_INV_SEL_V << GPIO_FUNC142_IN_INV_SEL_S) +#define GPIO_FUNC142_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC142_IN_INV_SEL_S 6 + +/* GPIO_FUNC142_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC142_IN_SEL 0x0000003F +#define GPIO_FUNC142_IN_SEL_M (GPIO_FUNC142_IN_SEL_V << GPIO_FUNC142_IN_SEL_S) +#define GPIO_FUNC142_IN_SEL_V 0x0000003F +#define GPIO_FUNC142_IN_SEL_S 0 + +/* GPIO_FUNC143_IN_SEL_CFG_REG register + * Peripheral function 143 input selection register + */ + +#define GPIO_FUNC143_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x390) + +/* GPIO_SIG143_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG143_IN_SEL (BIT(7)) +#define GPIO_SIG143_IN_SEL_M (GPIO_SIG143_IN_SEL_V << GPIO_SIG143_IN_SEL_S) +#define GPIO_SIG143_IN_SEL_V 0x00000001 +#define GPIO_SIG143_IN_SEL_S 7 + +/* GPIO_FUNC143_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC143_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC143_IN_INV_SEL_M (GPIO_FUNC143_IN_INV_SEL_V << GPIO_FUNC143_IN_INV_SEL_S) +#define GPIO_FUNC143_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC143_IN_INV_SEL_S 6 + +/* GPIO_FUNC143_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC143_IN_SEL 0x0000003F +#define GPIO_FUNC143_IN_SEL_M (GPIO_FUNC143_IN_SEL_V << GPIO_FUNC143_IN_SEL_S) +#define GPIO_FUNC143_IN_SEL_V 0x0000003F +#define GPIO_FUNC143_IN_SEL_S 0 + +/* GPIO_FUNC144_IN_SEL_CFG_REG register + * Peripheral function 144 input selection register + */ + +#define GPIO_FUNC144_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x394) + +/* GPIO_SIG144_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG144_IN_SEL (BIT(7)) +#define GPIO_SIG144_IN_SEL_M (GPIO_SIG144_IN_SEL_V << GPIO_SIG144_IN_SEL_S) +#define GPIO_SIG144_IN_SEL_V 0x00000001 +#define GPIO_SIG144_IN_SEL_S 7 + +/* GPIO_FUNC144_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC144_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC144_IN_INV_SEL_M (GPIO_FUNC144_IN_INV_SEL_V << GPIO_FUNC144_IN_INV_SEL_S) +#define GPIO_FUNC144_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC144_IN_INV_SEL_S 6 + +/* GPIO_FUNC144_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC144_IN_SEL 0x0000003F +#define GPIO_FUNC144_IN_SEL_M (GPIO_FUNC144_IN_SEL_V << GPIO_FUNC144_IN_SEL_S) +#define GPIO_FUNC144_IN_SEL_V 0x0000003F +#define GPIO_FUNC144_IN_SEL_S 0 + +/* GPIO_FUNC145_IN_SEL_CFG_REG register + * Peripheral function 145 input selection register + */ + +#define GPIO_FUNC145_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x398) + +/* GPIO_SIG145_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG145_IN_SEL (BIT(7)) +#define GPIO_SIG145_IN_SEL_M (GPIO_SIG145_IN_SEL_V << GPIO_SIG145_IN_SEL_S) +#define GPIO_SIG145_IN_SEL_V 0x00000001 +#define GPIO_SIG145_IN_SEL_S 7 + +/* GPIO_FUNC145_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC145_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC145_IN_INV_SEL_M (GPIO_FUNC145_IN_INV_SEL_V << GPIO_FUNC145_IN_INV_SEL_S) +#define GPIO_FUNC145_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC145_IN_INV_SEL_S 6 + +/* GPIO_FUNC145_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC145_IN_SEL 0x0000003F +#define GPIO_FUNC145_IN_SEL_M (GPIO_FUNC145_IN_SEL_V << GPIO_FUNC145_IN_SEL_S) +#define GPIO_FUNC145_IN_SEL_V 0x0000003F +#define GPIO_FUNC145_IN_SEL_S 0 + +/* GPIO_FUNC146_IN_SEL_CFG_REG register + * Peripheral function 146 input selection register + */ + +#define GPIO_FUNC146_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x39c) + +/* GPIO_SIG146_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG146_IN_SEL (BIT(7)) +#define GPIO_SIG146_IN_SEL_M (GPIO_SIG146_IN_SEL_V << GPIO_SIG146_IN_SEL_S) +#define GPIO_SIG146_IN_SEL_V 0x00000001 +#define GPIO_SIG146_IN_SEL_S 7 + +/* GPIO_FUNC146_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC146_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC146_IN_INV_SEL_M (GPIO_FUNC146_IN_INV_SEL_V << GPIO_FUNC146_IN_INV_SEL_S) +#define GPIO_FUNC146_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC146_IN_INV_SEL_S 6 + +/* GPIO_FUNC146_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC146_IN_SEL 0x0000003F +#define GPIO_FUNC146_IN_SEL_M (GPIO_FUNC146_IN_SEL_V << GPIO_FUNC146_IN_SEL_S) +#define GPIO_FUNC146_IN_SEL_V 0x0000003F +#define GPIO_FUNC146_IN_SEL_S 0 + +/* GPIO_FUNC147_IN_SEL_CFG_REG register + * Peripheral function 147 input selection register + */ + +#define GPIO_FUNC147_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a0) + +/* GPIO_SIG147_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG147_IN_SEL (BIT(7)) +#define GPIO_SIG147_IN_SEL_M (GPIO_SIG147_IN_SEL_V << GPIO_SIG147_IN_SEL_S) +#define GPIO_SIG147_IN_SEL_V 0x00000001 +#define GPIO_SIG147_IN_SEL_S 7 + +/* GPIO_FUNC147_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC147_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC147_IN_INV_SEL_M (GPIO_FUNC147_IN_INV_SEL_V << GPIO_FUNC147_IN_INV_SEL_S) +#define GPIO_FUNC147_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC147_IN_INV_SEL_S 6 + +/* GPIO_FUNC147_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC147_IN_SEL 0x0000003F +#define GPIO_FUNC147_IN_SEL_M (GPIO_FUNC147_IN_SEL_V << GPIO_FUNC147_IN_SEL_S) +#define GPIO_FUNC147_IN_SEL_V 0x0000003F +#define GPIO_FUNC147_IN_SEL_S 0 + +/* GPIO_FUNC148_IN_SEL_CFG_REG register + * Peripheral function 148 input selection register + */ + +#define GPIO_FUNC148_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a4) + +/* GPIO_SIG148_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG148_IN_SEL (BIT(7)) +#define GPIO_SIG148_IN_SEL_M (GPIO_SIG148_IN_SEL_V << GPIO_SIG148_IN_SEL_S) +#define GPIO_SIG148_IN_SEL_V 0x00000001 +#define GPIO_SIG148_IN_SEL_S 7 + +/* GPIO_FUNC148_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC148_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC148_IN_INV_SEL_M (GPIO_FUNC148_IN_INV_SEL_V << GPIO_FUNC148_IN_INV_SEL_S) +#define GPIO_FUNC148_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC148_IN_INV_SEL_S 6 + +/* GPIO_FUNC148_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC148_IN_SEL 0x0000003F +#define GPIO_FUNC148_IN_SEL_M (GPIO_FUNC148_IN_SEL_V << GPIO_FUNC148_IN_SEL_S) +#define GPIO_FUNC148_IN_SEL_V 0x0000003F +#define GPIO_FUNC148_IN_SEL_S 0 + +/* GPIO_FUNC149_IN_SEL_CFG_REG register + * Peripheral function 149 input selection register + */ + +#define GPIO_FUNC149_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3a8) + +/* GPIO_SIG149_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG149_IN_SEL (BIT(7)) +#define GPIO_SIG149_IN_SEL_M (GPIO_SIG149_IN_SEL_V << GPIO_SIG149_IN_SEL_S) +#define GPIO_SIG149_IN_SEL_V 0x00000001 +#define GPIO_SIG149_IN_SEL_S 7 + +/* GPIO_FUNC149_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC149_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC149_IN_INV_SEL_M (GPIO_FUNC149_IN_INV_SEL_V << GPIO_FUNC149_IN_INV_SEL_S) +#define GPIO_FUNC149_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC149_IN_INV_SEL_S 6 + +/* GPIO_FUNC149_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC149_IN_SEL 0x0000003F +#define GPIO_FUNC149_IN_SEL_M (GPIO_FUNC149_IN_SEL_V << GPIO_FUNC149_IN_SEL_S) +#define GPIO_FUNC149_IN_SEL_V 0x0000003F +#define GPIO_FUNC149_IN_SEL_S 0 + +/* GPIO_FUNC150_IN_SEL_CFG_REG register + * Peripheral function 150 input selection register + */ + +#define GPIO_FUNC150_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ac) + +/* GPIO_SIG150_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG150_IN_SEL (BIT(7)) +#define GPIO_SIG150_IN_SEL_M (GPIO_SIG150_IN_SEL_V << GPIO_SIG150_IN_SEL_S) +#define GPIO_SIG150_IN_SEL_V 0x00000001 +#define GPIO_SIG150_IN_SEL_S 7 + +/* GPIO_FUNC150_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC150_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC150_IN_INV_SEL_M (GPIO_FUNC150_IN_INV_SEL_V << GPIO_FUNC150_IN_INV_SEL_S) +#define GPIO_FUNC150_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC150_IN_INV_SEL_S 6 + +/* GPIO_FUNC150_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC150_IN_SEL 0x0000003F +#define GPIO_FUNC150_IN_SEL_M (GPIO_FUNC150_IN_SEL_V << GPIO_FUNC150_IN_SEL_S) +#define GPIO_FUNC150_IN_SEL_V 0x0000003F +#define GPIO_FUNC150_IN_SEL_S 0 + +/* GPIO_FUNC151_IN_SEL_CFG_REG register + * Peripheral function 151 input selection register + */ + +#define GPIO_FUNC151_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b0) + +/* GPIO_SIG151_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG151_IN_SEL (BIT(7)) +#define GPIO_SIG151_IN_SEL_M (GPIO_SIG151_IN_SEL_V << GPIO_SIG151_IN_SEL_S) +#define GPIO_SIG151_IN_SEL_V 0x00000001 +#define GPIO_SIG151_IN_SEL_S 7 + +/* GPIO_FUNC151_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC151_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC151_IN_INV_SEL_M (GPIO_FUNC151_IN_INV_SEL_V << GPIO_FUNC151_IN_INV_SEL_S) +#define GPIO_FUNC151_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC151_IN_INV_SEL_S 6 + +/* GPIO_FUNC151_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC151_IN_SEL 0x0000003F +#define GPIO_FUNC151_IN_SEL_M (GPIO_FUNC151_IN_SEL_V << GPIO_FUNC151_IN_SEL_S) +#define GPIO_FUNC151_IN_SEL_V 0x0000003F +#define GPIO_FUNC151_IN_SEL_S 0 + +/* GPIO_FUNC152_IN_SEL_CFG_REG register + * Peripheral function 152 input selection register + */ + +#define GPIO_FUNC152_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b4) + +/* GPIO_SIG152_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG152_IN_SEL (BIT(7)) +#define GPIO_SIG152_IN_SEL_M (GPIO_SIG152_IN_SEL_V << GPIO_SIG152_IN_SEL_S) +#define GPIO_SIG152_IN_SEL_V 0x00000001 +#define GPIO_SIG152_IN_SEL_S 7 + +/* GPIO_FUNC152_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC152_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC152_IN_INV_SEL_M (GPIO_FUNC152_IN_INV_SEL_V << GPIO_FUNC152_IN_INV_SEL_S) +#define GPIO_FUNC152_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC152_IN_INV_SEL_S 6 + +/* GPIO_FUNC152_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC152_IN_SEL 0x0000003F +#define GPIO_FUNC152_IN_SEL_M (GPIO_FUNC152_IN_SEL_V << GPIO_FUNC152_IN_SEL_S) +#define GPIO_FUNC152_IN_SEL_V 0x0000003F +#define GPIO_FUNC152_IN_SEL_S 0 + +/* GPIO_FUNC153_IN_SEL_CFG_REG register + * Peripheral function 153 input selection register + */ + +#define GPIO_FUNC153_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3b8) + +/* GPIO_SIG153_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG153_IN_SEL (BIT(7)) +#define GPIO_SIG153_IN_SEL_M (GPIO_SIG153_IN_SEL_V << GPIO_SIG153_IN_SEL_S) +#define GPIO_SIG153_IN_SEL_V 0x00000001 +#define GPIO_SIG153_IN_SEL_S 7 + +/* GPIO_FUNC153_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC153_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC153_IN_INV_SEL_M (GPIO_FUNC153_IN_INV_SEL_V << GPIO_FUNC153_IN_INV_SEL_S) +#define GPIO_FUNC153_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC153_IN_INV_SEL_S 6 + +/* GPIO_FUNC153_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC153_IN_SEL 0x0000003F +#define GPIO_FUNC153_IN_SEL_M (GPIO_FUNC153_IN_SEL_V << GPIO_FUNC153_IN_SEL_S) +#define GPIO_FUNC153_IN_SEL_V 0x0000003F +#define GPIO_FUNC153_IN_SEL_S 0 + +/* GPIO_FUNC154_IN_SEL_CFG_REG register + * Peripheral function 154 input selection register + */ + +#define GPIO_FUNC154_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3bc) + +/* GPIO_SIG154_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG154_IN_SEL (BIT(7)) +#define GPIO_SIG154_IN_SEL_M (GPIO_SIG154_IN_SEL_V << GPIO_SIG154_IN_SEL_S) +#define GPIO_SIG154_IN_SEL_V 0x00000001 +#define GPIO_SIG154_IN_SEL_S 7 + +/* GPIO_FUNC154_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC154_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC154_IN_INV_SEL_M (GPIO_FUNC154_IN_INV_SEL_V << GPIO_FUNC154_IN_INV_SEL_S) +#define GPIO_FUNC154_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC154_IN_INV_SEL_S 6 + +/* GPIO_FUNC154_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC154_IN_SEL 0x0000003F +#define GPIO_FUNC154_IN_SEL_M (GPIO_FUNC154_IN_SEL_V << GPIO_FUNC154_IN_SEL_S) +#define GPIO_FUNC154_IN_SEL_V 0x0000003F +#define GPIO_FUNC154_IN_SEL_S 0 + +/* GPIO_FUNC155_IN_SEL_CFG_REG register + * Peripheral function 155 input selection register + */ + +#define GPIO_FUNC155_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c0) + +/* GPIO_SIG155_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG155_IN_SEL (BIT(7)) +#define GPIO_SIG155_IN_SEL_M (GPIO_SIG155_IN_SEL_V << GPIO_SIG155_IN_SEL_S) +#define GPIO_SIG155_IN_SEL_V 0x00000001 +#define GPIO_SIG155_IN_SEL_S 7 + +/* GPIO_FUNC155_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC155_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC155_IN_INV_SEL_M (GPIO_FUNC155_IN_INV_SEL_V << GPIO_FUNC155_IN_INV_SEL_S) +#define GPIO_FUNC155_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC155_IN_INV_SEL_S 6 + +/* GPIO_FUNC155_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC155_IN_SEL 0x0000003F +#define GPIO_FUNC155_IN_SEL_M (GPIO_FUNC155_IN_SEL_V << GPIO_FUNC155_IN_SEL_S) +#define GPIO_FUNC155_IN_SEL_V 0x0000003F +#define GPIO_FUNC155_IN_SEL_S 0 + +/* GPIO_FUNC156_IN_SEL_CFG_REG register + * Peripheral function 156 input selection register + */ + +#define GPIO_FUNC156_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c4) + +/* GPIO_SIG156_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG156_IN_SEL (BIT(7)) +#define GPIO_SIG156_IN_SEL_M (GPIO_SIG156_IN_SEL_V << GPIO_SIG156_IN_SEL_S) +#define GPIO_SIG156_IN_SEL_V 0x00000001 +#define GPIO_SIG156_IN_SEL_S 7 + +/* GPIO_FUNC156_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC156_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC156_IN_INV_SEL_M (GPIO_FUNC156_IN_INV_SEL_V << GPIO_FUNC156_IN_INV_SEL_S) +#define GPIO_FUNC156_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC156_IN_INV_SEL_S 6 + +/* GPIO_FUNC156_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC156_IN_SEL 0x0000003F +#define GPIO_FUNC156_IN_SEL_M (GPIO_FUNC156_IN_SEL_V << GPIO_FUNC156_IN_SEL_S) +#define GPIO_FUNC156_IN_SEL_V 0x0000003F +#define GPIO_FUNC156_IN_SEL_S 0 + +/* GPIO_FUNC157_IN_SEL_CFG_REG register + * Peripheral function 157 input selection register + */ + +#define GPIO_FUNC157_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c8) + +/* GPIO_SIG157_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG157_IN_SEL (BIT(7)) +#define GPIO_SIG157_IN_SEL_M (GPIO_SIG157_IN_SEL_V << GPIO_SIG157_IN_SEL_S) +#define GPIO_SIG157_IN_SEL_V 0x00000001 +#define GPIO_SIG157_IN_SEL_S 7 + +/* GPIO_FUNC157_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC157_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC157_IN_INV_SEL_M (GPIO_FUNC157_IN_INV_SEL_V << GPIO_FUNC157_IN_INV_SEL_S) +#define GPIO_FUNC157_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC157_IN_INV_SEL_S 6 + +/* GPIO_FUNC157_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC157_IN_SEL 0x0000003F +#define GPIO_FUNC157_IN_SEL_M (GPIO_FUNC157_IN_SEL_V << GPIO_FUNC157_IN_SEL_S) +#define GPIO_FUNC157_IN_SEL_V 0x0000003F +#define GPIO_FUNC157_IN_SEL_S 0 + +/* GPIO_FUNC158_IN_SEL_CFG_REG register + * Peripheral function 158 input selection register + */ + +#define GPIO_FUNC158_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3cc) + +/* GPIO_SIG158_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG158_IN_SEL (BIT(7)) +#define GPIO_SIG158_IN_SEL_M (GPIO_SIG158_IN_SEL_V << GPIO_SIG158_IN_SEL_S) +#define GPIO_SIG158_IN_SEL_V 0x00000001 +#define GPIO_SIG158_IN_SEL_S 7 + +/* GPIO_FUNC158_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC158_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC158_IN_INV_SEL_M (GPIO_FUNC158_IN_INV_SEL_V << GPIO_FUNC158_IN_INV_SEL_S) +#define GPIO_FUNC158_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC158_IN_INV_SEL_S 6 + +/* GPIO_FUNC158_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC158_IN_SEL 0x0000003F +#define GPIO_FUNC158_IN_SEL_M (GPIO_FUNC158_IN_SEL_V << GPIO_FUNC158_IN_SEL_S) +#define GPIO_FUNC158_IN_SEL_V 0x0000003F +#define GPIO_FUNC158_IN_SEL_S 0 + +/* GPIO_FUNC159_IN_SEL_CFG_REG register + * Peripheral function 159 input selection register + */ + +#define GPIO_FUNC159_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d0) + +/* GPIO_SIG159_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG159_IN_SEL (BIT(7)) +#define GPIO_SIG159_IN_SEL_M (GPIO_SIG159_IN_SEL_V << GPIO_SIG159_IN_SEL_S) +#define GPIO_SIG159_IN_SEL_V 0x00000001 +#define GPIO_SIG159_IN_SEL_S 7 + +/* GPIO_FUNC159_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC159_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC159_IN_INV_SEL_M (GPIO_FUNC159_IN_INV_SEL_V << GPIO_FUNC159_IN_INV_SEL_S) +#define GPIO_FUNC159_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC159_IN_INV_SEL_S 6 + +/* GPIO_FUNC159_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC159_IN_SEL 0x0000003F +#define GPIO_FUNC159_IN_SEL_M (GPIO_FUNC159_IN_SEL_V << GPIO_FUNC159_IN_SEL_S) +#define GPIO_FUNC159_IN_SEL_V 0x0000003F +#define GPIO_FUNC159_IN_SEL_S 0 + +/* GPIO_FUNC160_IN_SEL_CFG_REG register + * Peripheral function 160 input selection register + */ + +#define GPIO_FUNC160_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4) + +/* GPIO_SIG160_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG160_IN_SEL (BIT(7)) +#define GPIO_SIG160_IN_SEL_M (GPIO_SIG160_IN_SEL_V << GPIO_SIG160_IN_SEL_S) +#define GPIO_SIG160_IN_SEL_V 0x00000001 +#define GPIO_SIG160_IN_SEL_S 7 + +/* GPIO_FUNC160_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC160_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC160_IN_INV_SEL_M (GPIO_FUNC160_IN_INV_SEL_V << GPIO_FUNC160_IN_INV_SEL_S) +#define GPIO_FUNC160_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC160_IN_INV_SEL_S 6 + +/* GPIO_FUNC160_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC160_IN_SEL 0x0000003F +#define GPIO_FUNC160_IN_SEL_M (GPIO_FUNC160_IN_SEL_V << GPIO_FUNC160_IN_SEL_S) +#define GPIO_FUNC160_IN_SEL_V 0x0000003F +#define GPIO_FUNC160_IN_SEL_S 0 + +/* GPIO_FUNC161_IN_SEL_CFG_REG register + * Peripheral function 161 input selection register + */ + +#define GPIO_FUNC161_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8) + +/* GPIO_SIG161_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG161_IN_SEL (BIT(7)) +#define GPIO_SIG161_IN_SEL_M (GPIO_SIG161_IN_SEL_V << GPIO_SIG161_IN_SEL_S) +#define GPIO_SIG161_IN_SEL_V 0x00000001 +#define GPIO_SIG161_IN_SEL_S 7 + +/* GPIO_FUNC161_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC161_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC161_IN_INV_SEL_M (GPIO_FUNC161_IN_INV_SEL_V << GPIO_FUNC161_IN_INV_SEL_S) +#define GPIO_FUNC161_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC161_IN_INV_SEL_S 6 + +/* GPIO_FUNC161_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC161_IN_SEL 0x0000003F +#define GPIO_FUNC161_IN_SEL_M (GPIO_FUNC161_IN_SEL_V << GPIO_FUNC161_IN_SEL_S) +#define GPIO_FUNC161_IN_SEL_V 0x0000003F +#define GPIO_FUNC161_IN_SEL_S 0 + +/* GPIO_FUNC162_IN_SEL_CFG_REG register + * Peripheral function 162 input selection register + */ + +#define GPIO_FUNC162_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3dc) + +/* GPIO_SIG162_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG162_IN_SEL (BIT(7)) +#define GPIO_SIG162_IN_SEL_M (GPIO_SIG162_IN_SEL_V << GPIO_SIG162_IN_SEL_S) +#define GPIO_SIG162_IN_SEL_V 0x00000001 +#define GPIO_SIG162_IN_SEL_S 7 + +/* GPIO_FUNC162_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC162_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC162_IN_INV_SEL_M (GPIO_FUNC162_IN_INV_SEL_V << GPIO_FUNC162_IN_INV_SEL_S) +#define GPIO_FUNC162_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC162_IN_INV_SEL_S 6 + +/* GPIO_FUNC162_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC162_IN_SEL 0x0000003F +#define GPIO_FUNC162_IN_SEL_M (GPIO_FUNC162_IN_SEL_V << GPIO_FUNC162_IN_SEL_S) +#define GPIO_FUNC162_IN_SEL_V 0x0000003F +#define GPIO_FUNC162_IN_SEL_S 0 + +/* GPIO_FUNC163_IN_SEL_CFG_REG register + * Peripheral function 163 input selection register + */ + +#define GPIO_FUNC163_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e0) + +/* GPIO_SIG163_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG163_IN_SEL (BIT(7)) +#define GPIO_SIG163_IN_SEL_M (GPIO_SIG163_IN_SEL_V << GPIO_SIG163_IN_SEL_S) +#define GPIO_SIG163_IN_SEL_V 0x00000001 +#define GPIO_SIG163_IN_SEL_S 7 + +/* GPIO_FUNC163_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC163_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC163_IN_INV_SEL_M (GPIO_FUNC163_IN_INV_SEL_V << GPIO_FUNC163_IN_INV_SEL_S) +#define GPIO_FUNC163_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC163_IN_INV_SEL_S 6 + +/* GPIO_FUNC163_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC163_IN_SEL 0x0000003F +#define GPIO_FUNC163_IN_SEL_M (GPIO_FUNC163_IN_SEL_V << GPIO_FUNC163_IN_SEL_S) +#define GPIO_FUNC163_IN_SEL_V 0x0000003F +#define GPIO_FUNC163_IN_SEL_S 0 + +/* GPIO_FUNC164_IN_SEL_CFG_REG register + * Peripheral function 164 input selection register + */ + +#define GPIO_FUNC164_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e4) + +/* GPIO_SIG164_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG164_IN_SEL (BIT(7)) +#define GPIO_SIG164_IN_SEL_M (GPIO_SIG164_IN_SEL_V << GPIO_SIG164_IN_SEL_S) +#define GPIO_SIG164_IN_SEL_V 0x00000001 +#define GPIO_SIG164_IN_SEL_S 7 + +/* GPIO_FUNC164_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC164_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC164_IN_INV_SEL_M (GPIO_FUNC164_IN_INV_SEL_V << GPIO_FUNC164_IN_INV_SEL_S) +#define GPIO_FUNC164_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC164_IN_INV_SEL_S 6 + +/* GPIO_FUNC164_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC164_IN_SEL 0x0000003F +#define GPIO_FUNC164_IN_SEL_M (GPIO_FUNC164_IN_SEL_V << GPIO_FUNC164_IN_SEL_S) +#define GPIO_FUNC164_IN_SEL_V 0x0000003F +#define GPIO_FUNC164_IN_SEL_S 0 + +/* GPIO_FUNC165_IN_SEL_CFG_REG register + * Peripheral function 165 input selection register + */ + +#define GPIO_FUNC165_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e8) + +/* GPIO_SIG165_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG165_IN_SEL (BIT(7)) +#define GPIO_SIG165_IN_SEL_M (GPIO_SIG165_IN_SEL_V << GPIO_SIG165_IN_SEL_S) +#define GPIO_SIG165_IN_SEL_V 0x00000001 +#define GPIO_SIG165_IN_SEL_S 7 + +/* GPIO_FUNC165_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC165_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC165_IN_INV_SEL_M (GPIO_FUNC165_IN_INV_SEL_V << GPIO_FUNC165_IN_INV_SEL_S) +#define GPIO_FUNC165_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC165_IN_INV_SEL_S 6 + +/* GPIO_FUNC165_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC165_IN_SEL 0x0000003F +#define GPIO_FUNC165_IN_SEL_M (GPIO_FUNC165_IN_SEL_V << GPIO_FUNC165_IN_SEL_S) +#define GPIO_FUNC165_IN_SEL_V 0x0000003F +#define GPIO_FUNC165_IN_SEL_S 0 + +/* GPIO_FUNC166_IN_SEL_CFG_REG register + * Peripheral function 166 input selection register + */ + +#define GPIO_FUNC166_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ec) + +/* GPIO_SIG166_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG166_IN_SEL (BIT(7)) +#define GPIO_SIG166_IN_SEL_M (GPIO_SIG166_IN_SEL_V << GPIO_SIG166_IN_SEL_S) +#define GPIO_SIG166_IN_SEL_V 0x00000001 +#define GPIO_SIG166_IN_SEL_S 7 + +/* GPIO_FUNC166_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC166_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC166_IN_INV_SEL_M (GPIO_FUNC166_IN_INV_SEL_V << GPIO_FUNC166_IN_INV_SEL_S) +#define GPIO_FUNC166_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC166_IN_INV_SEL_S 6 + +/* GPIO_FUNC166_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC166_IN_SEL 0x0000003F +#define GPIO_FUNC166_IN_SEL_M (GPIO_FUNC166_IN_SEL_V << GPIO_FUNC166_IN_SEL_S) +#define GPIO_FUNC166_IN_SEL_V 0x0000003F +#define GPIO_FUNC166_IN_SEL_S 0 + +/* GPIO_FUNC167_IN_SEL_CFG_REG register + * Peripheral function 167 input selection register + */ + +#define GPIO_FUNC167_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f0) + +/* GPIO_SIG167_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG167_IN_SEL (BIT(7)) +#define GPIO_SIG167_IN_SEL_M (GPIO_SIG167_IN_SEL_V << GPIO_SIG167_IN_SEL_S) +#define GPIO_SIG167_IN_SEL_V 0x00000001 +#define GPIO_SIG167_IN_SEL_S 7 + +/* GPIO_FUNC167_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC167_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC167_IN_INV_SEL_M (GPIO_FUNC167_IN_INV_SEL_V << GPIO_FUNC167_IN_INV_SEL_S) +#define GPIO_FUNC167_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC167_IN_INV_SEL_S 6 + +/* GPIO_FUNC167_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC167_IN_SEL 0x0000003F +#define GPIO_FUNC167_IN_SEL_M (GPIO_FUNC167_IN_SEL_V << GPIO_FUNC167_IN_SEL_S) +#define GPIO_FUNC167_IN_SEL_V 0x0000003F +#define GPIO_FUNC167_IN_SEL_S 0 + +/* GPIO_FUNC168_IN_SEL_CFG_REG register + * Peripheral function 168 input selection register + */ + +#define GPIO_FUNC168_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f4) + +/* GPIO_SIG168_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG168_IN_SEL (BIT(7)) +#define GPIO_SIG168_IN_SEL_M (GPIO_SIG168_IN_SEL_V << GPIO_SIG168_IN_SEL_S) +#define GPIO_SIG168_IN_SEL_V 0x00000001 +#define GPIO_SIG168_IN_SEL_S 7 + +/* GPIO_FUNC168_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC168_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC168_IN_INV_SEL_M (GPIO_FUNC168_IN_INV_SEL_V << GPIO_FUNC168_IN_INV_SEL_S) +#define GPIO_FUNC168_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC168_IN_INV_SEL_S 6 + +/* GPIO_FUNC168_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC168_IN_SEL 0x0000003F +#define GPIO_FUNC168_IN_SEL_M (GPIO_FUNC168_IN_SEL_V << GPIO_FUNC168_IN_SEL_S) +#define GPIO_FUNC168_IN_SEL_V 0x0000003F +#define GPIO_FUNC168_IN_SEL_S 0 + +/* GPIO_FUNC169_IN_SEL_CFG_REG register + * Peripheral function 169 input selection register + */ + +#define GPIO_FUNC169_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f8) + +/* GPIO_SIG169_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG169_IN_SEL (BIT(7)) +#define GPIO_SIG169_IN_SEL_M (GPIO_SIG169_IN_SEL_V << GPIO_SIG169_IN_SEL_S) +#define GPIO_SIG169_IN_SEL_V 0x00000001 +#define GPIO_SIG169_IN_SEL_S 7 + +/* GPIO_FUNC169_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC169_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC169_IN_INV_SEL_M (GPIO_FUNC169_IN_INV_SEL_V << GPIO_FUNC169_IN_INV_SEL_S) +#define GPIO_FUNC169_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC169_IN_INV_SEL_S 6 + +/* GPIO_FUNC169_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC169_IN_SEL 0x0000003F +#define GPIO_FUNC169_IN_SEL_M (GPIO_FUNC169_IN_SEL_V << GPIO_FUNC169_IN_SEL_S) +#define GPIO_FUNC169_IN_SEL_V 0x0000003F +#define GPIO_FUNC169_IN_SEL_S 0 + +/* GPIO_FUNC170_IN_SEL_CFG_REG register + * Peripheral function 170 input selection register + */ + +#define GPIO_FUNC170_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3fc) + +/* GPIO_SIG170_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG170_IN_SEL (BIT(7)) +#define GPIO_SIG170_IN_SEL_M (GPIO_SIG170_IN_SEL_V << GPIO_SIG170_IN_SEL_S) +#define GPIO_SIG170_IN_SEL_V 0x00000001 +#define GPIO_SIG170_IN_SEL_S 7 + +/* GPIO_FUNC170_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC170_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC170_IN_INV_SEL_M (GPIO_FUNC170_IN_INV_SEL_V << GPIO_FUNC170_IN_INV_SEL_S) +#define GPIO_FUNC170_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC170_IN_INV_SEL_S 6 + +/* GPIO_FUNC170_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC170_IN_SEL 0x0000003F +#define GPIO_FUNC170_IN_SEL_M (GPIO_FUNC170_IN_SEL_V << GPIO_FUNC170_IN_SEL_S) +#define GPIO_FUNC170_IN_SEL_V 0x0000003F +#define GPIO_FUNC170_IN_SEL_S 0 + +/* GPIO_FUNC171_IN_SEL_CFG_REG register + * Peripheral function 171 input selection register + */ + +#define GPIO_FUNC171_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x400) + +/* GPIO_SIG171_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG171_IN_SEL (BIT(7)) +#define GPIO_SIG171_IN_SEL_M (GPIO_SIG171_IN_SEL_V << GPIO_SIG171_IN_SEL_S) +#define GPIO_SIG171_IN_SEL_V 0x00000001 +#define GPIO_SIG171_IN_SEL_S 7 + +/* GPIO_FUNC171_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC171_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC171_IN_INV_SEL_M (GPIO_FUNC171_IN_INV_SEL_V << GPIO_FUNC171_IN_INV_SEL_S) +#define GPIO_FUNC171_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC171_IN_INV_SEL_S 6 + +/* GPIO_FUNC171_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC171_IN_SEL 0x0000003F +#define GPIO_FUNC171_IN_SEL_M (GPIO_FUNC171_IN_SEL_V << GPIO_FUNC171_IN_SEL_S) +#define GPIO_FUNC171_IN_SEL_V 0x0000003F +#define GPIO_FUNC171_IN_SEL_S 0 + +/* GPIO_FUNC172_IN_SEL_CFG_REG register + * Peripheral function 172 input selection register + */ + +#define GPIO_FUNC172_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x404) + +/* GPIO_SIG172_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG172_IN_SEL (BIT(7)) +#define GPIO_SIG172_IN_SEL_M (GPIO_SIG172_IN_SEL_V << GPIO_SIG172_IN_SEL_S) +#define GPIO_SIG172_IN_SEL_V 0x00000001 +#define GPIO_SIG172_IN_SEL_S 7 + +/* GPIO_FUNC172_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC172_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC172_IN_INV_SEL_M (GPIO_FUNC172_IN_INV_SEL_V << GPIO_FUNC172_IN_INV_SEL_S) +#define GPIO_FUNC172_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC172_IN_INV_SEL_S 6 + +/* GPIO_FUNC172_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC172_IN_SEL 0x0000003F +#define GPIO_FUNC172_IN_SEL_M (GPIO_FUNC172_IN_SEL_V << GPIO_FUNC172_IN_SEL_S) +#define GPIO_FUNC172_IN_SEL_V 0x0000003F +#define GPIO_FUNC172_IN_SEL_S 0 + +/* GPIO_FUNC173_IN_SEL_CFG_REG register + * Peripheral function 173 input selection register + */ + +#define GPIO_FUNC173_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x408) + +/* GPIO_SIG173_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG173_IN_SEL (BIT(7)) +#define GPIO_SIG173_IN_SEL_M (GPIO_SIG173_IN_SEL_V << GPIO_SIG173_IN_SEL_S) +#define GPIO_SIG173_IN_SEL_V 0x00000001 +#define GPIO_SIG173_IN_SEL_S 7 + +/* GPIO_FUNC173_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC173_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC173_IN_INV_SEL_M (GPIO_FUNC173_IN_INV_SEL_V << GPIO_FUNC173_IN_INV_SEL_S) +#define GPIO_FUNC173_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC173_IN_INV_SEL_S 6 + +/* GPIO_FUNC173_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC173_IN_SEL 0x0000003F +#define GPIO_FUNC173_IN_SEL_M (GPIO_FUNC173_IN_SEL_V << GPIO_FUNC173_IN_SEL_S) +#define GPIO_FUNC173_IN_SEL_V 0x0000003F +#define GPIO_FUNC173_IN_SEL_S 0 + +/* GPIO_FUNC174_IN_SEL_CFG_REG register + * Peripheral function 174 input selection register + */ + +#define GPIO_FUNC174_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40c) + +/* GPIO_SIG174_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG174_IN_SEL (BIT(7)) +#define GPIO_SIG174_IN_SEL_M (GPIO_SIG174_IN_SEL_V << GPIO_SIG174_IN_SEL_S) +#define GPIO_SIG174_IN_SEL_V 0x00000001 +#define GPIO_SIG174_IN_SEL_S 7 + +/* GPIO_FUNC174_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC174_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC174_IN_INV_SEL_M (GPIO_FUNC174_IN_INV_SEL_V << GPIO_FUNC174_IN_INV_SEL_S) +#define GPIO_FUNC174_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC174_IN_INV_SEL_S 6 + +/* GPIO_FUNC174_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC174_IN_SEL 0x0000003F +#define GPIO_FUNC174_IN_SEL_M (GPIO_FUNC174_IN_SEL_V << GPIO_FUNC174_IN_SEL_S) +#define GPIO_FUNC174_IN_SEL_V 0x0000003F +#define GPIO_FUNC174_IN_SEL_S 0 + +/* GPIO_FUNC175_IN_SEL_CFG_REG register + * Peripheral function 175 input selection register + */ + +#define GPIO_FUNC175_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410) + +/* GPIO_SIG175_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG175_IN_SEL (BIT(7)) +#define GPIO_SIG175_IN_SEL_M (GPIO_SIG175_IN_SEL_V << GPIO_SIG175_IN_SEL_S) +#define GPIO_SIG175_IN_SEL_V 0x00000001 +#define GPIO_SIG175_IN_SEL_S 7 + +/* GPIO_FUNC175_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC175_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC175_IN_INV_SEL_M (GPIO_FUNC175_IN_INV_SEL_V << GPIO_FUNC175_IN_INV_SEL_S) +#define GPIO_FUNC175_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC175_IN_INV_SEL_S 6 + +/* GPIO_FUNC175_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC175_IN_SEL 0x0000003F +#define GPIO_FUNC175_IN_SEL_M (GPIO_FUNC175_IN_SEL_V << GPIO_FUNC175_IN_SEL_S) +#define GPIO_FUNC175_IN_SEL_V 0x0000003F +#define GPIO_FUNC175_IN_SEL_S 0 + +/* GPIO_FUNC176_IN_SEL_CFG_REG register + * Peripheral function 176 input selection register + */ + +#define GPIO_FUNC176_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x414) + +/* GPIO_SIG176_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG176_IN_SEL (BIT(7)) +#define GPIO_SIG176_IN_SEL_M (GPIO_SIG176_IN_SEL_V << GPIO_SIG176_IN_SEL_S) +#define GPIO_SIG176_IN_SEL_V 0x00000001 +#define GPIO_SIG176_IN_SEL_S 7 + +/* GPIO_FUNC176_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC176_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC176_IN_INV_SEL_M (GPIO_FUNC176_IN_INV_SEL_V << GPIO_FUNC176_IN_INV_SEL_S) +#define GPIO_FUNC176_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC176_IN_INV_SEL_S 6 + +/* GPIO_FUNC176_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC176_IN_SEL 0x0000003F +#define GPIO_FUNC176_IN_SEL_M (GPIO_FUNC176_IN_SEL_V << GPIO_FUNC176_IN_SEL_S) +#define GPIO_FUNC176_IN_SEL_V 0x0000003F +#define GPIO_FUNC176_IN_SEL_S 0 + +/* GPIO_FUNC177_IN_SEL_CFG_REG register + * Peripheral function 177 input selection register + */ + +#define GPIO_FUNC177_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x418) + +/* GPIO_SIG177_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG177_IN_SEL (BIT(7)) +#define GPIO_SIG177_IN_SEL_M (GPIO_SIG177_IN_SEL_V << GPIO_SIG177_IN_SEL_S) +#define GPIO_SIG177_IN_SEL_V 0x00000001 +#define GPIO_SIG177_IN_SEL_S 7 + +/* GPIO_FUNC177_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC177_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC177_IN_INV_SEL_M (GPIO_FUNC177_IN_INV_SEL_V << GPIO_FUNC177_IN_INV_SEL_S) +#define GPIO_FUNC177_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC177_IN_INV_SEL_S 6 + +/* GPIO_FUNC177_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC177_IN_SEL 0x0000003F +#define GPIO_FUNC177_IN_SEL_M (GPIO_FUNC177_IN_SEL_V << GPIO_FUNC177_IN_SEL_S) +#define GPIO_FUNC177_IN_SEL_V 0x0000003F +#define GPIO_FUNC177_IN_SEL_S 0 + +/* GPIO_FUNC178_IN_SEL_CFG_REG register + * Peripheral function 178 input selection register + */ + +#define GPIO_FUNC178_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x41c) + +/* GPIO_SIG178_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG178_IN_SEL (BIT(7)) +#define GPIO_SIG178_IN_SEL_M (GPIO_SIG178_IN_SEL_V << GPIO_SIG178_IN_SEL_S) +#define GPIO_SIG178_IN_SEL_V 0x00000001 +#define GPIO_SIG178_IN_SEL_S 7 + +/* GPIO_FUNC178_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC178_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC178_IN_INV_SEL_M (GPIO_FUNC178_IN_INV_SEL_V << GPIO_FUNC178_IN_INV_SEL_S) +#define GPIO_FUNC178_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC178_IN_INV_SEL_S 6 + +/* GPIO_FUNC178_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC178_IN_SEL 0x0000003F +#define GPIO_FUNC178_IN_SEL_M (GPIO_FUNC178_IN_SEL_V << GPIO_FUNC178_IN_SEL_S) +#define GPIO_FUNC178_IN_SEL_V 0x0000003F +#define GPIO_FUNC178_IN_SEL_S 0 + +/* GPIO_FUNC179_IN_SEL_CFG_REG register + * Peripheral function 179 input selection register + */ + +#define GPIO_FUNC179_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x420) + +/* GPIO_SIG179_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG179_IN_SEL (BIT(7)) +#define GPIO_SIG179_IN_SEL_M (GPIO_SIG179_IN_SEL_V << GPIO_SIG179_IN_SEL_S) +#define GPIO_SIG179_IN_SEL_V 0x00000001 +#define GPIO_SIG179_IN_SEL_S 7 + +/* GPIO_FUNC179_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC179_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC179_IN_INV_SEL_M (GPIO_FUNC179_IN_INV_SEL_V << GPIO_FUNC179_IN_INV_SEL_S) +#define GPIO_FUNC179_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC179_IN_INV_SEL_S 6 + +/* GPIO_FUNC179_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC179_IN_SEL 0x0000003F +#define GPIO_FUNC179_IN_SEL_M (GPIO_FUNC179_IN_SEL_V << GPIO_FUNC179_IN_SEL_S) +#define GPIO_FUNC179_IN_SEL_V 0x0000003F +#define GPIO_FUNC179_IN_SEL_S 0 + +/* GPIO_FUNC180_IN_SEL_CFG_REG register + * Peripheral function 180 input selection register + */ + +#define GPIO_FUNC180_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x424) + +/* GPIO_SIG180_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG180_IN_SEL (BIT(7)) +#define GPIO_SIG180_IN_SEL_M (GPIO_SIG180_IN_SEL_V << GPIO_SIG180_IN_SEL_S) +#define GPIO_SIG180_IN_SEL_V 0x00000001 +#define GPIO_SIG180_IN_SEL_S 7 + +/* GPIO_FUNC180_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC180_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC180_IN_INV_SEL_M (GPIO_FUNC180_IN_INV_SEL_V << GPIO_FUNC180_IN_INV_SEL_S) +#define GPIO_FUNC180_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC180_IN_INV_SEL_S 6 + +/* GPIO_FUNC180_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC180_IN_SEL 0x0000003F +#define GPIO_FUNC180_IN_SEL_M (GPIO_FUNC180_IN_SEL_V << GPIO_FUNC180_IN_SEL_S) +#define GPIO_FUNC180_IN_SEL_V 0x0000003F +#define GPIO_FUNC180_IN_SEL_S 0 + +/* GPIO_FUNC181_IN_SEL_CFG_REG register + * Peripheral function 181 input selection register + */ + +#define GPIO_FUNC181_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x428) + +/* GPIO_SIG181_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG181_IN_SEL (BIT(7)) +#define GPIO_SIG181_IN_SEL_M (GPIO_SIG181_IN_SEL_V << GPIO_SIG181_IN_SEL_S) +#define GPIO_SIG181_IN_SEL_V 0x00000001 +#define GPIO_SIG181_IN_SEL_S 7 + +/* GPIO_FUNC181_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC181_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC181_IN_INV_SEL_M (GPIO_FUNC181_IN_INV_SEL_V << GPIO_FUNC181_IN_INV_SEL_S) +#define GPIO_FUNC181_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC181_IN_INV_SEL_S 6 + +/* GPIO_FUNC181_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC181_IN_SEL 0x0000003F +#define GPIO_FUNC181_IN_SEL_M (GPIO_FUNC181_IN_SEL_V << GPIO_FUNC181_IN_SEL_S) +#define GPIO_FUNC181_IN_SEL_V 0x0000003F +#define GPIO_FUNC181_IN_SEL_S 0 + +/* GPIO_FUNC182_IN_SEL_CFG_REG register + * Peripheral function 182 input selection register + */ + +#define GPIO_FUNC182_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x42c) + +/* GPIO_SIG182_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG182_IN_SEL (BIT(7)) +#define GPIO_SIG182_IN_SEL_M (GPIO_SIG182_IN_SEL_V << GPIO_SIG182_IN_SEL_S) +#define GPIO_SIG182_IN_SEL_V 0x00000001 +#define GPIO_SIG182_IN_SEL_S 7 + +/* GPIO_FUNC182_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC182_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC182_IN_INV_SEL_M (GPIO_FUNC182_IN_INV_SEL_V << GPIO_FUNC182_IN_INV_SEL_S) +#define GPIO_FUNC182_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC182_IN_INV_SEL_S 6 + +/* GPIO_FUNC182_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC182_IN_SEL 0x0000003F +#define GPIO_FUNC182_IN_SEL_M (GPIO_FUNC182_IN_SEL_V << GPIO_FUNC182_IN_SEL_S) +#define GPIO_FUNC182_IN_SEL_V 0x0000003F +#define GPIO_FUNC182_IN_SEL_S 0 + +/* GPIO_FUNC183_IN_SEL_CFG_REG register + * Peripheral function 183 input selection register + */ + +#define GPIO_FUNC183_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x430) + +/* GPIO_SIG183_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG183_IN_SEL (BIT(7)) +#define GPIO_SIG183_IN_SEL_M (GPIO_SIG183_IN_SEL_V << GPIO_SIG183_IN_SEL_S) +#define GPIO_SIG183_IN_SEL_V 0x00000001 +#define GPIO_SIG183_IN_SEL_S 7 + +/* GPIO_FUNC183_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC183_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC183_IN_INV_SEL_M (GPIO_FUNC183_IN_INV_SEL_V << GPIO_FUNC183_IN_INV_SEL_S) +#define GPIO_FUNC183_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC183_IN_INV_SEL_S 6 + +/* GPIO_FUNC183_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC183_IN_SEL 0x0000003F +#define GPIO_FUNC183_IN_SEL_M (GPIO_FUNC183_IN_SEL_V << GPIO_FUNC183_IN_SEL_S) +#define GPIO_FUNC183_IN_SEL_V 0x0000003F +#define GPIO_FUNC183_IN_SEL_S 0 + +/* GPIO_FUNC184_IN_SEL_CFG_REG register + * Peripheral function 184 input selection register + */ + +#define GPIO_FUNC184_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x434) + +/* GPIO_SIG184_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG184_IN_SEL (BIT(7)) +#define GPIO_SIG184_IN_SEL_M (GPIO_SIG184_IN_SEL_V << GPIO_SIG184_IN_SEL_S) +#define GPIO_SIG184_IN_SEL_V 0x00000001 +#define GPIO_SIG184_IN_SEL_S 7 + +/* GPIO_FUNC184_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC184_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC184_IN_INV_SEL_M (GPIO_FUNC184_IN_INV_SEL_V << GPIO_FUNC184_IN_INV_SEL_S) +#define GPIO_FUNC184_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC184_IN_INV_SEL_S 6 + +/* GPIO_FUNC184_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC184_IN_SEL 0x0000003F +#define GPIO_FUNC184_IN_SEL_M (GPIO_FUNC184_IN_SEL_V << GPIO_FUNC184_IN_SEL_S) +#define GPIO_FUNC184_IN_SEL_V 0x0000003F +#define GPIO_FUNC184_IN_SEL_S 0 + +/* GPIO_FUNC185_IN_SEL_CFG_REG register + * Peripheral function 185 input selection register + */ + +#define GPIO_FUNC185_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x438) + +/* GPIO_SIG185_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG185_IN_SEL (BIT(7)) +#define GPIO_SIG185_IN_SEL_M (GPIO_SIG185_IN_SEL_V << GPIO_SIG185_IN_SEL_S) +#define GPIO_SIG185_IN_SEL_V 0x00000001 +#define GPIO_SIG185_IN_SEL_S 7 + +/* GPIO_FUNC185_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC185_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC185_IN_INV_SEL_M (GPIO_FUNC185_IN_INV_SEL_V << GPIO_FUNC185_IN_INV_SEL_S) +#define GPIO_FUNC185_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC185_IN_INV_SEL_S 6 + +/* GPIO_FUNC185_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC185_IN_SEL 0x0000003F +#define GPIO_FUNC185_IN_SEL_M (GPIO_FUNC185_IN_SEL_V << GPIO_FUNC185_IN_SEL_S) +#define GPIO_FUNC185_IN_SEL_V 0x0000003F +#define GPIO_FUNC185_IN_SEL_S 0 + +/* GPIO_FUNC186_IN_SEL_CFG_REG register + * Peripheral function 186 input selection register + */ + +#define GPIO_FUNC186_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x43c) + +/* GPIO_SIG186_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG186_IN_SEL (BIT(7)) +#define GPIO_SIG186_IN_SEL_M (GPIO_SIG186_IN_SEL_V << GPIO_SIG186_IN_SEL_S) +#define GPIO_SIG186_IN_SEL_V 0x00000001 +#define GPIO_SIG186_IN_SEL_S 7 + +/* GPIO_FUNC186_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC186_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC186_IN_INV_SEL_M (GPIO_FUNC186_IN_INV_SEL_V << GPIO_FUNC186_IN_INV_SEL_S) +#define GPIO_FUNC186_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC186_IN_INV_SEL_S 6 + +/* GPIO_FUNC186_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC186_IN_SEL 0x0000003F +#define GPIO_FUNC186_IN_SEL_M (GPIO_FUNC186_IN_SEL_V << GPIO_FUNC186_IN_SEL_S) +#define GPIO_FUNC186_IN_SEL_V 0x0000003F +#define GPIO_FUNC186_IN_SEL_S 0 + +/* GPIO_FUNC187_IN_SEL_CFG_REG register + * Peripheral function 187 input selection register + */ + +#define GPIO_FUNC187_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x440) + +/* GPIO_SIG187_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG187_IN_SEL (BIT(7)) +#define GPIO_SIG187_IN_SEL_M (GPIO_SIG187_IN_SEL_V << GPIO_SIG187_IN_SEL_S) +#define GPIO_SIG187_IN_SEL_V 0x00000001 +#define GPIO_SIG187_IN_SEL_S 7 + +/* GPIO_FUNC187_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC187_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC187_IN_INV_SEL_M (GPIO_FUNC187_IN_INV_SEL_V << GPIO_FUNC187_IN_INV_SEL_S) +#define GPIO_FUNC187_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC187_IN_INV_SEL_S 6 + +/* GPIO_FUNC187_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC187_IN_SEL 0x0000003F +#define GPIO_FUNC187_IN_SEL_M (GPIO_FUNC187_IN_SEL_V << GPIO_FUNC187_IN_SEL_S) +#define GPIO_FUNC187_IN_SEL_V 0x0000003F +#define GPIO_FUNC187_IN_SEL_S 0 + +/* GPIO_FUNC188_IN_SEL_CFG_REG register + * Peripheral function 188 input selection register + */ + +#define GPIO_FUNC188_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x444) + +/* GPIO_SIG188_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG188_IN_SEL (BIT(7)) +#define GPIO_SIG188_IN_SEL_M (GPIO_SIG188_IN_SEL_V << GPIO_SIG188_IN_SEL_S) +#define GPIO_SIG188_IN_SEL_V 0x00000001 +#define GPIO_SIG188_IN_SEL_S 7 + +/* GPIO_FUNC188_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC188_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC188_IN_INV_SEL_M (GPIO_FUNC188_IN_INV_SEL_V << GPIO_FUNC188_IN_INV_SEL_S) +#define GPIO_FUNC188_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC188_IN_INV_SEL_S 6 + +/* GPIO_FUNC188_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC188_IN_SEL 0x0000003F +#define GPIO_FUNC188_IN_SEL_M (GPIO_FUNC188_IN_SEL_V << GPIO_FUNC188_IN_SEL_S) +#define GPIO_FUNC188_IN_SEL_V 0x0000003F +#define GPIO_FUNC188_IN_SEL_S 0 + +/* GPIO_FUNC189_IN_SEL_CFG_REG register + * Peripheral function 189 input selection register + */ + +#define GPIO_FUNC189_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x448) + +/* GPIO_SIG189_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG189_IN_SEL (BIT(7)) +#define GPIO_SIG189_IN_SEL_M (GPIO_SIG189_IN_SEL_V << GPIO_SIG189_IN_SEL_S) +#define GPIO_SIG189_IN_SEL_V 0x00000001 +#define GPIO_SIG189_IN_SEL_S 7 + +/* GPIO_FUNC189_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC189_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC189_IN_INV_SEL_M (GPIO_FUNC189_IN_INV_SEL_V << GPIO_FUNC189_IN_INV_SEL_S) +#define GPIO_FUNC189_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC189_IN_INV_SEL_S 6 + +/* GPIO_FUNC189_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC189_IN_SEL 0x0000003F +#define GPIO_FUNC189_IN_SEL_M (GPIO_FUNC189_IN_SEL_V << GPIO_FUNC189_IN_SEL_S) +#define GPIO_FUNC189_IN_SEL_V 0x0000003F +#define GPIO_FUNC189_IN_SEL_S 0 + +/* GPIO_FUNC190_IN_SEL_CFG_REG register + * Peripheral function 190 input selection register + */ + +#define GPIO_FUNC190_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x44c) + +/* GPIO_SIG190_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG190_IN_SEL (BIT(7)) +#define GPIO_SIG190_IN_SEL_M (GPIO_SIG190_IN_SEL_V << GPIO_SIG190_IN_SEL_S) +#define GPIO_SIG190_IN_SEL_V 0x00000001 +#define GPIO_SIG190_IN_SEL_S 7 + +/* GPIO_FUNC190_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC190_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC190_IN_INV_SEL_M (GPIO_FUNC190_IN_INV_SEL_V << GPIO_FUNC190_IN_INV_SEL_S) +#define GPIO_FUNC190_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC190_IN_INV_SEL_S 6 + +/* GPIO_FUNC190_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC190_IN_SEL 0x0000003F +#define GPIO_FUNC190_IN_SEL_M (GPIO_FUNC190_IN_SEL_V << GPIO_FUNC190_IN_SEL_S) +#define GPIO_FUNC190_IN_SEL_V 0x0000003F +#define GPIO_FUNC190_IN_SEL_S 0 + +/* GPIO_FUNC191_IN_SEL_CFG_REG register + * Peripheral function 191 input selection register + */ + +#define GPIO_FUNC191_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x450) + +/* GPIO_SIG191_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG191_IN_SEL (BIT(7)) +#define GPIO_SIG191_IN_SEL_M (GPIO_SIG191_IN_SEL_V << GPIO_SIG191_IN_SEL_S) +#define GPIO_SIG191_IN_SEL_V 0x00000001 +#define GPIO_SIG191_IN_SEL_S 7 + +/* GPIO_FUNC191_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC191_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC191_IN_INV_SEL_M (GPIO_FUNC191_IN_INV_SEL_V << GPIO_FUNC191_IN_INV_SEL_S) +#define GPIO_FUNC191_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC191_IN_INV_SEL_S 6 + +/* GPIO_FUNC191_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC191_IN_SEL 0x0000003F +#define GPIO_FUNC191_IN_SEL_M (GPIO_FUNC191_IN_SEL_V << GPIO_FUNC191_IN_SEL_S) +#define GPIO_FUNC191_IN_SEL_V 0x0000003F +#define GPIO_FUNC191_IN_SEL_S 0 + +/* GPIO_FUNC192_IN_SEL_CFG_REG register + * Peripheral function 192 input selection register + */ + +#define GPIO_FUNC192_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x454) + +/* GPIO_SIG192_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG192_IN_SEL (BIT(7)) +#define GPIO_SIG192_IN_SEL_M (GPIO_SIG192_IN_SEL_V << GPIO_SIG192_IN_SEL_S) +#define GPIO_SIG192_IN_SEL_V 0x00000001 +#define GPIO_SIG192_IN_SEL_S 7 + +/* GPIO_FUNC192_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC192_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC192_IN_INV_SEL_M (GPIO_FUNC192_IN_INV_SEL_V << GPIO_FUNC192_IN_INV_SEL_S) +#define GPIO_FUNC192_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC192_IN_INV_SEL_S 6 + +/* GPIO_FUNC192_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC192_IN_SEL 0x0000003F +#define GPIO_FUNC192_IN_SEL_M (GPIO_FUNC192_IN_SEL_V << GPIO_FUNC192_IN_SEL_S) +#define GPIO_FUNC192_IN_SEL_V 0x0000003F +#define GPIO_FUNC192_IN_SEL_S 0 + +/* GPIO_FUNC193_IN_SEL_CFG_REG register + * Peripheral function 193 input selection register + */ + +#define GPIO_FUNC193_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x458) + +/* GPIO_SIG193_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG193_IN_SEL (BIT(7)) +#define GPIO_SIG193_IN_SEL_M (GPIO_SIG193_IN_SEL_V << GPIO_SIG193_IN_SEL_S) +#define GPIO_SIG193_IN_SEL_V 0x00000001 +#define GPIO_SIG193_IN_SEL_S 7 + +/* GPIO_FUNC193_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC193_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC193_IN_INV_SEL_M (GPIO_FUNC193_IN_INV_SEL_V << GPIO_FUNC193_IN_INV_SEL_S) +#define GPIO_FUNC193_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC193_IN_INV_SEL_S 6 + +/* GPIO_FUNC193_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC193_IN_SEL 0x0000003F +#define GPIO_FUNC193_IN_SEL_M (GPIO_FUNC193_IN_SEL_V << GPIO_FUNC193_IN_SEL_S) +#define GPIO_FUNC193_IN_SEL_V 0x0000003F +#define GPIO_FUNC193_IN_SEL_S 0 + +/* GPIO_FUNC194_IN_SEL_CFG_REG register + * Peripheral function 194 input selection register + */ + +#define GPIO_FUNC194_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x45c) + +/* GPIO_SIG194_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG194_IN_SEL (BIT(7)) +#define GPIO_SIG194_IN_SEL_M (GPIO_SIG194_IN_SEL_V << GPIO_SIG194_IN_SEL_S) +#define GPIO_SIG194_IN_SEL_V 0x00000001 +#define GPIO_SIG194_IN_SEL_S 7 + +/* GPIO_FUNC194_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC194_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC194_IN_INV_SEL_M (GPIO_FUNC194_IN_INV_SEL_V << GPIO_FUNC194_IN_INV_SEL_S) +#define GPIO_FUNC194_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC194_IN_INV_SEL_S 6 + +/* GPIO_FUNC194_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC194_IN_SEL 0x0000003F +#define GPIO_FUNC194_IN_SEL_M (GPIO_FUNC194_IN_SEL_V << GPIO_FUNC194_IN_SEL_S) +#define GPIO_FUNC194_IN_SEL_V 0x0000003F +#define GPIO_FUNC194_IN_SEL_S 0 + +/* GPIO_FUNC195_IN_SEL_CFG_REG register + * Peripheral function 195 input selection register + */ + +#define GPIO_FUNC195_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x460) + +/* GPIO_SIG195_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG195_IN_SEL (BIT(7)) +#define GPIO_SIG195_IN_SEL_M (GPIO_SIG195_IN_SEL_V << GPIO_SIG195_IN_SEL_S) +#define GPIO_SIG195_IN_SEL_V 0x00000001 +#define GPIO_SIG195_IN_SEL_S 7 + +/* GPIO_FUNC195_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC195_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC195_IN_INV_SEL_M (GPIO_FUNC195_IN_INV_SEL_V << GPIO_FUNC195_IN_INV_SEL_S) +#define GPIO_FUNC195_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC195_IN_INV_SEL_S 6 + +/* GPIO_FUNC195_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC195_IN_SEL 0x0000003F +#define GPIO_FUNC195_IN_SEL_M (GPIO_FUNC195_IN_SEL_V << GPIO_FUNC195_IN_SEL_S) +#define GPIO_FUNC195_IN_SEL_V 0x0000003F +#define GPIO_FUNC195_IN_SEL_S 0 + +/* GPIO_FUNC196_IN_SEL_CFG_REG register + * Peripheral function 196 input selection register + */ + +#define GPIO_FUNC196_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x464) + +/* GPIO_SIG196_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG196_IN_SEL (BIT(7)) +#define GPIO_SIG196_IN_SEL_M (GPIO_SIG196_IN_SEL_V << GPIO_SIG196_IN_SEL_S) +#define GPIO_SIG196_IN_SEL_V 0x00000001 +#define GPIO_SIG196_IN_SEL_S 7 + +/* GPIO_FUNC196_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC196_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC196_IN_INV_SEL_M (GPIO_FUNC196_IN_INV_SEL_V << GPIO_FUNC196_IN_INV_SEL_S) +#define GPIO_FUNC196_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC196_IN_INV_SEL_S 6 + +/* GPIO_FUNC196_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC196_IN_SEL 0x0000003F +#define GPIO_FUNC196_IN_SEL_M (GPIO_FUNC196_IN_SEL_V << GPIO_FUNC196_IN_SEL_S) +#define GPIO_FUNC196_IN_SEL_V 0x0000003F +#define GPIO_FUNC196_IN_SEL_S 0 + +/* GPIO_FUNC197_IN_SEL_CFG_REG register + * Peripheral function 197 input selection register + */ + +#define GPIO_FUNC197_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x468) + +/* GPIO_SIG197_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG197_IN_SEL (BIT(7)) +#define GPIO_SIG197_IN_SEL_M (GPIO_SIG197_IN_SEL_V << GPIO_SIG197_IN_SEL_S) +#define GPIO_SIG197_IN_SEL_V 0x00000001 +#define GPIO_SIG197_IN_SEL_S 7 + +/* GPIO_FUNC197_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC197_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC197_IN_INV_SEL_M (GPIO_FUNC197_IN_INV_SEL_V << GPIO_FUNC197_IN_INV_SEL_S) +#define GPIO_FUNC197_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC197_IN_INV_SEL_S 6 + +/* GPIO_FUNC197_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC197_IN_SEL 0x0000003F +#define GPIO_FUNC197_IN_SEL_M (GPIO_FUNC197_IN_SEL_V << GPIO_FUNC197_IN_SEL_S) +#define GPIO_FUNC197_IN_SEL_V 0x0000003F +#define GPIO_FUNC197_IN_SEL_S 0 + +/* GPIO_FUNC198_IN_SEL_CFG_REG register + * Peripheral function 198 input selection register + */ + +#define GPIO_FUNC198_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x46c) + +/* GPIO_SIG198_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG198_IN_SEL (BIT(7)) +#define GPIO_SIG198_IN_SEL_M (GPIO_SIG198_IN_SEL_V << GPIO_SIG198_IN_SEL_S) +#define GPIO_SIG198_IN_SEL_V 0x00000001 +#define GPIO_SIG198_IN_SEL_S 7 + +/* GPIO_FUNC198_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC198_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC198_IN_INV_SEL_M (GPIO_FUNC198_IN_INV_SEL_V << GPIO_FUNC198_IN_INV_SEL_S) +#define GPIO_FUNC198_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC198_IN_INV_SEL_S 6 + +/* GPIO_FUNC198_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC198_IN_SEL 0x0000003F +#define GPIO_FUNC198_IN_SEL_M (GPIO_FUNC198_IN_SEL_V << GPIO_FUNC198_IN_SEL_S) +#define GPIO_FUNC198_IN_SEL_V 0x0000003F +#define GPIO_FUNC198_IN_SEL_S 0 + +/* GPIO_FUNC199_IN_SEL_CFG_REG register + * Peripheral function 199 input selection register + */ + +#define GPIO_FUNC199_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x470) + +/* GPIO_SIG199_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG199_IN_SEL (BIT(7)) +#define GPIO_SIG199_IN_SEL_M (GPIO_SIG199_IN_SEL_V << GPIO_SIG199_IN_SEL_S) +#define GPIO_SIG199_IN_SEL_V 0x00000001 +#define GPIO_SIG199_IN_SEL_S 7 + +/* GPIO_FUNC199_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC199_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC199_IN_INV_SEL_M (GPIO_FUNC199_IN_INV_SEL_V << GPIO_FUNC199_IN_INV_SEL_S) +#define GPIO_FUNC199_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC199_IN_INV_SEL_S 6 + +/* GPIO_FUNC199_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC199_IN_SEL 0x0000003F +#define GPIO_FUNC199_IN_SEL_M (GPIO_FUNC199_IN_SEL_V << GPIO_FUNC199_IN_SEL_S) +#define GPIO_FUNC199_IN_SEL_V 0x0000003F +#define GPIO_FUNC199_IN_SEL_S 0 + +/* GPIO_FUNC200_IN_SEL_CFG_REG register + * Peripheral function 200 input selection register + */ + +#define GPIO_FUNC200_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x474) + +/* GPIO_SIG200_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG200_IN_SEL (BIT(7)) +#define GPIO_SIG200_IN_SEL_M (GPIO_SIG200_IN_SEL_V << GPIO_SIG200_IN_SEL_S) +#define GPIO_SIG200_IN_SEL_V 0x00000001 +#define GPIO_SIG200_IN_SEL_S 7 + +/* GPIO_FUNC200_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC200_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC200_IN_INV_SEL_M (GPIO_FUNC200_IN_INV_SEL_V << GPIO_FUNC200_IN_INV_SEL_S) +#define GPIO_FUNC200_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC200_IN_INV_SEL_S 6 + +/* GPIO_FUNC200_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC200_IN_SEL 0x0000003F +#define GPIO_FUNC200_IN_SEL_M (GPIO_FUNC200_IN_SEL_V << GPIO_FUNC200_IN_SEL_S) +#define GPIO_FUNC200_IN_SEL_V 0x0000003F +#define GPIO_FUNC200_IN_SEL_S 0 + +/* GPIO_FUNC201_IN_SEL_CFG_REG register + * Peripheral function 201 input selection register + */ + +#define GPIO_FUNC201_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x478) + +/* GPIO_SIG201_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG201_IN_SEL (BIT(7)) +#define GPIO_SIG201_IN_SEL_M (GPIO_SIG201_IN_SEL_V << GPIO_SIG201_IN_SEL_S) +#define GPIO_SIG201_IN_SEL_V 0x00000001 +#define GPIO_SIG201_IN_SEL_S 7 + +/* GPIO_FUNC201_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC201_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC201_IN_INV_SEL_M (GPIO_FUNC201_IN_INV_SEL_V << GPIO_FUNC201_IN_INV_SEL_S) +#define GPIO_FUNC201_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC201_IN_INV_SEL_S 6 + +/* GPIO_FUNC201_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC201_IN_SEL 0x0000003F +#define GPIO_FUNC201_IN_SEL_M (GPIO_FUNC201_IN_SEL_V << GPIO_FUNC201_IN_SEL_S) +#define GPIO_FUNC201_IN_SEL_V 0x0000003F +#define GPIO_FUNC201_IN_SEL_S 0 + +/* GPIO_FUNC202_IN_SEL_CFG_REG register + * Peripheral function 202 input selection register + */ + +#define GPIO_FUNC202_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x47c) + +/* GPIO_SIG202_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG202_IN_SEL (BIT(7)) +#define GPIO_SIG202_IN_SEL_M (GPIO_SIG202_IN_SEL_V << GPIO_SIG202_IN_SEL_S) +#define GPIO_SIG202_IN_SEL_V 0x00000001 +#define GPIO_SIG202_IN_SEL_S 7 + +/* GPIO_FUNC202_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC202_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC202_IN_INV_SEL_M (GPIO_FUNC202_IN_INV_SEL_V << GPIO_FUNC202_IN_INV_SEL_S) +#define GPIO_FUNC202_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC202_IN_INV_SEL_S 6 + +/* GPIO_FUNC202_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC202_IN_SEL 0x0000003F +#define GPIO_FUNC202_IN_SEL_M (GPIO_FUNC202_IN_SEL_V << GPIO_FUNC202_IN_SEL_S) +#define GPIO_FUNC202_IN_SEL_V 0x0000003F +#define GPIO_FUNC202_IN_SEL_S 0 + +/* GPIO_FUNC203_IN_SEL_CFG_REG register + * Peripheral function 203 input selection register + */ + +#define GPIO_FUNC203_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x480) + +/* GPIO_SIG203_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG203_IN_SEL (BIT(7)) +#define GPIO_SIG203_IN_SEL_M (GPIO_SIG203_IN_SEL_V << GPIO_SIG203_IN_SEL_S) +#define GPIO_SIG203_IN_SEL_V 0x00000001 +#define GPIO_SIG203_IN_SEL_S 7 + +/* GPIO_FUNC203_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC203_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC203_IN_INV_SEL_M (GPIO_FUNC203_IN_INV_SEL_V << GPIO_FUNC203_IN_INV_SEL_S) +#define GPIO_FUNC203_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC203_IN_INV_SEL_S 6 + +/* GPIO_FUNC203_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC203_IN_SEL 0x0000003F +#define GPIO_FUNC203_IN_SEL_M (GPIO_FUNC203_IN_SEL_V << GPIO_FUNC203_IN_SEL_S) +#define GPIO_FUNC203_IN_SEL_V 0x0000003F +#define GPIO_FUNC203_IN_SEL_S 0 + +/* GPIO_FUNC204_IN_SEL_CFG_REG register + * Peripheral function 204 input selection register + */ + +#define GPIO_FUNC204_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x484) + +/* GPIO_SIG204_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG204_IN_SEL (BIT(7)) +#define GPIO_SIG204_IN_SEL_M (GPIO_SIG204_IN_SEL_V << GPIO_SIG204_IN_SEL_S) +#define GPIO_SIG204_IN_SEL_V 0x00000001 +#define GPIO_SIG204_IN_SEL_S 7 + +/* GPIO_FUNC204_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC204_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC204_IN_INV_SEL_M (GPIO_FUNC204_IN_INV_SEL_V << GPIO_FUNC204_IN_INV_SEL_S) +#define GPIO_FUNC204_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC204_IN_INV_SEL_S 6 + +/* GPIO_FUNC204_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC204_IN_SEL 0x0000003F +#define GPIO_FUNC204_IN_SEL_M (GPIO_FUNC204_IN_SEL_V << GPIO_FUNC204_IN_SEL_S) +#define GPIO_FUNC204_IN_SEL_V 0x0000003F +#define GPIO_FUNC204_IN_SEL_S 0 + +/* GPIO_FUNC205_IN_SEL_CFG_REG register + * Peripheral function 205 input selection register + */ + +#define GPIO_FUNC205_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x488) + +/* GPIO_SIG205_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG205_IN_SEL (BIT(7)) +#define GPIO_SIG205_IN_SEL_M (GPIO_SIG205_IN_SEL_V << GPIO_SIG205_IN_SEL_S) +#define GPIO_SIG205_IN_SEL_V 0x00000001 +#define GPIO_SIG205_IN_SEL_S 7 + +/* GPIO_FUNC205_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC205_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC205_IN_INV_SEL_M (GPIO_FUNC205_IN_INV_SEL_V << GPIO_FUNC205_IN_INV_SEL_S) +#define GPIO_FUNC205_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC205_IN_INV_SEL_S 6 + +/* GPIO_FUNC205_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC205_IN_SEL 0x0000003F +#define GPIO_FUNC205_IN_SEL_M (GPIO_FUNC205_IN_SEL_V << GPIO_FUNC205_IN_SEL_S) +#define GPIO_FUNC205_IN_SEL_V 0x0000003F +#define GPIO_FUNC205_IN_SEL_S 0 + +/* GPIO_FUNC206_IN_SEL_CFG_REG register + * Peripheral function 206 input selection register + */ + +#define GPIO_FUNC206_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x48c) + +/* GPIO_SIG206_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG206_IN_SEL (BIT(7)) +#define GPIO_SIG206_IN_SEL_M (GPIO_SIG206_IN_SEL_V << GPIO_SIG206_IN_SEL_S) +#define GPIO_SIG206_IN_SEL_V 0x00000001 +#define GPIO_SIG206_IN_SEL_S 7 + +/* GPIO_FUNC206_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC206_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC206_IN_INV_SEL_M (GPIO_FUNC206_IN_INV_SEL_V << GPIO_FUNC206_IN_INV_SEL_S) +#define GPIO_FUNC206_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC206_IN_INV_SEL_S 6 + +/* GPIO_FUNC206_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC206_IN_SEL 0x0000003F +#define GPIO_FUNC206_IN_SEL_M (GPIO_FUNC206_IN_SEL_V << GPIO_FUNC206_IN_SEL_S) +#define GPIO_FUNC206_IN_SEL_V 0x0000003F +#define GPIO_FUNC206_IN_SEL_S 0 + +/* GPIO_FUNC207_IN_SEL_CFG_REG register + * Peripheral function 207 input selection register + */ + +#define GPIO_FUNC207_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x490) + +/* GPIO_SIG207_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG207_IN_SEL (BIT(7)) +#define GPIO_SIG207_IN_SEL_M (GPIO_SIG207_IN_SEL_V << GPIO_SIG207_IN_SEL_S) +#define GPIO_SIG207_IN_SEL_V 0x00000001 +#define GPIO_SIG207_IN_SEL_S 7 + +/* GPIO_FUNC207_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC207_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC207_IN_INV_SEL_M (GPIO_FUNC207_IN_INV_SEL_V << GPIO_FUNC207_IN_INV_SEL_S) +#define GPIO_FUNC207_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC207_IN_INV_SEL_S 6 + +/* GPIO_FUNC207_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC207_IN_SEL 0x0000003F +#define GPIO_FUNC207_IN_SEL_M (GPIO_FUNC207_IN_SEL_V << GPIO_FUNC207_IN_SEL_S) +#define GPIO_FUNC207_IN_SEL_V 0x0000003F +#define GPIO_FUNC207_IN_SEL_S 0 + +/* GPIO_FUNC208_IN_SEL_CFG_REG register + * Peripheral function 208 input selection register + */ + +#define GPIO_FUNC208_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x494) + +/* GPIO_SIG208_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG208_IN_SEL (BIT(7)) +#define GPIO_SIG208_IN_SEL_M (GPIO_SIG208_IN_SEL_V << GPIO_SIG208_IN_SEL_S) +#define GPIO_SIG208_IN_SEL_V 0x00000001 +#define GPIO_SIG208_IN_SEL_S 7 + +/* GPIO_FUNC208_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC208_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC208_IN_INV_SEL_M (GPIO_FUNC208_IN_INV_SEL_V << GPIO_FUNC208_IN_INV_SEL_S) +#define GPIO_FUNC208_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC208_IN_INV_SEL_S 6 + +/* GPIO_FUNC208_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC208_IN_SEL 0x0000003F +#define GPIO_FUNC208_IN_SEL_M (GPIO_FUNC208_IN_SEL_V << GPIO_FUNC208_IN_SEL_S) +#define GPIO_FUNC208_IN_SEL_V 0x0000003F +#define GPIO_FUNC208_IN_SEL_S 0 + +/* GPIO_FUNC209_IN_SEL_CFG_REG register + * Peripheral function 209 input selection register + */ + +#define GPIO_FUNC209_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x498) + +/* GPIO_SIG209_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG209_IN_SEL (BIT(7)) +#define GPIO_SIG209_IN_SEL_M (GPIO_SIG209_IN_SEL_V << GPIO_SIG209_IN_SEL_S) +#define GPIO_SIG209_IN_SEL_V 0x00000001 +#define GPIO_SIG209_IN_SEL_S 7 + +/* GPIO_FUNC209_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC209_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC209_IN_INV_SEL_M (GPIO_FUNC209_IN_INV_SEL_V << GPIO_FUNC209_IN_INV_SEL_S) +#define GPIO_FUNC209_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC209_IN_INV_SEL_S 6 + +/* GPIO_FUNC209_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC209_IN_SEL 0x0000003F +#define GPIO_FUNC209_IN_SEL_M (GPIO_FUNC209_IN_SEL_V << GPIO_FUNC209_IN_SEL_S) +#define GPIO_FUNC209_IN_SEL_V 0x0000003F +#define GPIO_FUNC209_IN_SEL_S 0 + +/* GPIO_FUNC210_IN_SEL_CFG_REG register + * Peripheral function 210 input selection register + */ + +#define GPIO_FUNC210_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x49c) + +/* GPIO_SIG210_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG210_IN_SEL (BIT(7)) +#define GPIO_SIG210_IN_SEL_M (GPIO_SIG210_IN_SEL_V << GPIO_SIG210_IN_SEL_S) +#define GPIO_SIG210_IN_SEL_V 0x00000001 +#define GPIO_SIG210_IN_SEL_S 7 + +/* GPIO_FUNC210_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC210_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC210_IN_INV_SEL_M (GPIO_FUNC210_IN_INV_SEL_V << GPIO_FUNC210_IN_INV_SEL_S) +#define GPIO_FUNC210_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC210_IN_INV_SEL_S 6 + +/* GPIO_FUNC210_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC210_IN_SEL 0x0000003F +#define GPIO_FUNC210_IN_SEL_M (GPIO_FUNC210_IN_SEL_V << GPIO_FUNC210_IN_SEL_S) +#define GPIO_FUNC210_IN_SEL_V 0x0000003F +#define GPIO_FUNC210_IN_SEL_S 0 + +/* GPIO_FUNC211_IN_SEL_CFG_REG register + * Peripheral function 211 input selection register + */ + +#define GPIO_FUNC211_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a0) + +/* GPIO_SIG211_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG211_IN_SEL (BIT(7)) +#define GPIO_SIG211_IN_SEL_M (GPIO_SIG211_IN_SEL_V << GPIO_SIG211_IN_SEL_S) +#define GPIO_SIG211_IN_SEL_V 0x00000001 +#define GPIO_SIG211_IN_SEL_S 7 + +/* GPIO_FUNC211_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC211_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC211_IN_INV_SEL_M (GPIO_FUNC211_IN_INV_SEL_V << GPIO_FUNC211_IN_INV_SEL_S) +#define GPIO_FUNC211_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC211_IN_INV_SEL_S 6 + +/* GPIO_FUNC211_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC211_IN_SEL 0x0000003F +#define GPIO_FUNC211_IN_SEL_M (GPIO_FUNC211_IN_SEL_V << GPIO_FUNC211_IN_SEL_S) +#define GPIO_FUNC211_IN_SEL_V 0x0000003F +#define GPIO_FUNC211_IN_SEL_S 0 + +/* GPIO_FUNC212_IN_SEL_CFG_REG register + * Peripheral function 212 input selection register + */ + +#define GPIO_FUNC212_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a4) + +/* GPIO_SIG212_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG212_IN_SEL (BIT(7)) +#define GPIO_SIG212_IN_SEL_M (GPIO_SIG212_IN_SEL_V << GPIO_SIG212_IN_SEL_S) +#define GPIO_SIG212_IN_SEL_V 0x00000001 +#define GPIO_SIG212_IN_SEL_S 7 + +/* GPIO_FUNC212_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC212_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC212_IN_INV_SEL_M (GPIO_FUNC212_IN_INV_SEL_V << GPIO_FUNC212_IN_INV_SEL_S) +#define GPIO_FUNC212_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC212_IN_INV_SEL_S 6 + +/* GPIO_FUNC212_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC212_IN_SEL 0x0000003F +#define GPIO_FUNC212_IN_SEL_M (GPIO_FUNC212_IN_SEL_V << GPIO_FUNC212_IN_SEL_S) +#define GPIO_FUNC212_IN_SEL_V 0x0000003F +#define GPIO_FUNC212_IN_SEL_S 0 + +/* GPIO_FUNC213_IN_SEL_CFG_REG register + * Peripheral function 213 input selection register + */ + +#define GPIO_FUNC213_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a8) + +/* GPIO_SIG213_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG213_IN_SEL (BIT(7)) +#define GPIO_SIG213_IN_SEL_M (GPIO_SIG213_IN_SEL_V << GPIO_SIG213_IN_SEL_S) +#define GPIO_SIG213_IN_SEL_V 0x00000001 +#define GPIO_SIG213_IN_SEL_S 7 + +/* GPIO_FUNC213_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC213_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC213_IN_INV_SEL_M (GPIO_FUNC213_IN_INV_SEL_V << GPIO_FUNC213_IN_INV_SEL_S) +#define GPIO_FUNC213_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC213_IN_INV_SEL_S 6 + +/* GPIO_FUNC213_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC213_IN_SEL 0x0000003F +#define GPIO_FUNC213_IN_SEL_M (GPIO_FUNC213_IN_SEL_V << GPIO_FUNC213_IN_SEL_S) +#define GPIO_FUNC213_IN_SEL_V 0x0000003F +#define GPIO_FUNC213_IN_SEL_S 0 + +/* GPIO_FUNC214_IN_SEL_CFG_REG register + * Peripheral function 214 input selection register + */ + +#define GPIO_FUNC214_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4ac) + +/* GPIO_SIG214_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG214_IN_SEL (BIT(7)) +#define GPIO_SIG214_IN_SEL_M (GPIO_SIG214_IN_SEL_V << GPIO_SIG214_IN_SEL_S) +#define GPIO_SIG214_IN_SEL_V 0x00000001 +#define GPIO_SIG214_IN_SEL_S 7 + +/* GPIO_FUNC214_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC214_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC214_IN_INV_SEL_M (GPIO_FUNC214_IN_INV_SEL_V << GPIO_FUNC214_IN_INV_SEL_S) +#define GPIO_FUNC214_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC214_IN_INV_SEL_S 6 + +/* GPIO_FUNC214_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC214_IN_SEL 0x0000003F +#define GPIO_FUNC214_IN_SEL_M (GPIO_FUNC214_IN_SEL_V << GPIO_FUNC214_IN_SEL_S) +#define GPIO_FUNC214_IN_SEL_V 0x0000003F +#define GPIO_FUNC214_IN_SEL_S 0 + +/* GPIO_FUNC215_IN_SEL_CFG_REG register + * Peripheral function 215 input selection register + */ + +#define GPIO_FUNC215_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b0) + +/* GPIO_SIG215_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG215_IN_SEL (BIT(7)) +#define GPIO_SIG215_IN_SEL_M (GPIO_SIG215_IN_SEL_V << GPIO_SIG215_IN_SEL_S) +#define GPIO_SIG215_IN_SEL_V 0x00000001 +#define GPIO_SIG215_IN_SEL_S 7 + +/* GPIO_FUNC215_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC215_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC215_IN_INV_SEL_M (GPIO_FUNC215_IN_INV_SEL_V << GPIO_FUNC215_IN_INV_SEL_S) +#define GPIO_FUNC215_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC215_IN_INV_SEL_S 6 + +/* GPIO_FUNC215_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC215_IN_SEL 0x0000003F +#define GPIO_FUNC215_IN_SEL_M (GPIO_FUNC215_IN_SEL_V << GPIO_FUNC215_IN_SEL_S) +#define GPIO_FUNC215_IN_SEL_V 0x0000003F +#define GPIO_FUNC215_IN_SEL_S 0 + +/* GPIO_FUNC216_IN_SEL_CFG_REG register + * Peripheral function 216 input selection register + */ + +#define GPIO_FUNC216_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b4) + +/* GPIO_SIG216_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG216_IN_SEL (BIT(7)) +#define GPIO_SIG216_IN_SEL_M (GPIO_SIG216_IN_SEL_V << GPIO_SIG216_IN_SEL_S) +#define GPIO_SIG216_IN_SEL_V 0x00000001 +#define GPIO_SIG216_IN_SEL_S 7 + +/* GPIO_FUNC216_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC216_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC216_IN_INV_SEL_M (GPIO_FUNC216_IN_INV_SEL_V << GPIO_FUNC216_IN_INV_SEL_S) +#define GPIO_FUNC216_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC216_IN_INV_SEL_S 6 + +/* GPIO_FUNC216_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC216_IN_SEL 0x0000003F +#define GPIO_FUNC216_IN_SEL_M (GPIO_FUNC216_IN_SEL_V << GPIO_FUNC216_IN_SEL_S) +#define GPIO_FUNC216_IN_SEL_V 0x0000003F +#define GPIO_FUNC216_IN_SEL_S 0 + +/* GPIO_FUNC217_IN_SEL_CFG_REG register + * Peripheral function 217 input selection register + */ + +#define GPIO_FUNC217_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b8) + +/* GPIO_SIG217_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG217_IN_SEL (BIT(7)) +#define GPIO_SIG217_IN_SEL_M (GPIO_SIG217_IN_SEL_V << GPIO_SIG217_IN_SEL_S) +#define GPIO_SIG217_IN_SEL_V 0x00000001 +#define GPIO_SIG217_IN_SEL_S 7 + +/* GPIO_FUNC217_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC217_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC217_IN_INV_SEL_M (GPIO_FUNC217_IN_INV_SEL_V << GPIO_FUNC217_IN_INV_SEL_S) +#define GPIO_FUNC217_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC217_IN_INV_SEL_S 6 + +/* GPIO_FUNC217_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC217_IN_SEL 0x0000003F +#define GPIO_FUNC217_IN_SEL_M (GPIO_FUNC217_IN_SEL_V << GPIO_FUNC217_IN_SEL_S) +#define GPIO_FUNC217_IN_SEL_V 0x0000003F +#define GPIO_FUNC217_IN_SEL_S 0 + +/* GPIO_FUNC218_IN_SEL_CFG_REG register + * Peripheral function 218 input selection register + */ + +#define GPIO_FUNC218_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4bc) + +/* GPIO_SIG218_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG218_IN_SEL (BIT(7)) +#define GPIO_SIG218_IN_SEL_M (GPIO_SIG218_IN_SEL_V << GPIO_SIG218_IN_SEL_S) +#define GPIO_SIG218_IN_SEL_V 0x00000001 +#define GPIO_SIG218_IN_SEL_S 7 + +/* GPIO_FUNC218_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC218_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC218_IN_INV_SEL_M (GPIO_FUNC218_IN_INV_SEL_V << GPIO_FUNC218_IN_INV_SEL_S) +#define GPIO_FUNC218_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC218_IN_INV_SEL_S 6 + +/* GPIO_FUNC218_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC218_IN_SEL 0x0000003F +#define GPIO_FUNC218_IN_SEL_M (GPIO_FUNC218_IN_SEL_V << GPIO_FUNC218_IN_SEL_S) +#define GPIO_FUNC218_IN_SEL_V 0x0000003F +#define GPIO_FUNC218_IN_SEL_S 0 + +/* GPIO_FUNC219_IN_SEL_CFG_REG register + * Peripheral function 219 input selection register + */ + +#define GPIO_FUNC219_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c0) + +/* GPIO_SIG219_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG219_IN_SEL (BIT(7)) +#define GPIO_SIG219_IN_SEL_M (GPIO_SIG219_IN_SEL_V << GPIO_SIG219_IN_SEL_S) +#define GPIO_SIG219_IN_SEL_V 0x00000001 +#define GPIO_SIG219_IN_SEL_S 7 + +/* GPIO_FUNC219_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC219_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC219_IN_INV_SEL_M (GPIO_FUNC219_IN_INV_SEL_V << GPIO_FUNC219_IN_INV_SEL_S) +#define GPIO_FUNC219_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC219_IN_INV_SEL_S 6 + +/* GPIO_FUNC219_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC219_IN_SEL 0x0000003F +#define GPIO_FUNC219_IN_SEL_M (GPIO_FUNC219_IN_SEL_V << GPIO_FUNC219_IN_SEL_S) +#define GPIO_FUNC219_IN_SEL_V 0x0000003F +#define GPIO_FUNC219_IN_SEL_S 0 + +/* GPIO_FUNC220_IN_SEL_CFG_REG register + * Peripheral function 220 input selection register + */ + +#define GPIO_FUNC220_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c4) + +/* GPIO_SIG220_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG220_IN_SEL (BIT(7)) +#define GPIO_SIG220_IN_SEL_M (GPIO_SIG220_IN_SEL_V << GPIO_SIG220_IN_SEL_S) +#define GPIO_SIG220_IN_SEL_V 0x00000001 +#define GPIO_SIG220_IN_SEL_S 7 + +/* GPIO_FUNC220_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC220_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC220_IN_INV_SEL_M (GPIO_FUNC220_IN_INV_SEL_V << GPIO_FUNC220_IN_INV_SEL_S) +#define GPIO_FUNC220_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC220_IN_INV_SEL_S 6 + +/* GPIO_FUNC220_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC220_IN_SEL 0x0000003F +#define GPIO_FUNC220_IN_SEL_M (GPIO_FUNC220_IN_SEL_V << GPIO_FUNC220_IN_SEL_S) +#define GPIO_FUNC220_IN_SEL_V 0x0000003F +#define GPIO_FUNC220_IN_SEL_S 0 + +/* GPIO_FUNC221_IN_SEL_CFG_REG register + * Peripheral function 221 input selection register + */ + +#define GPIO_FUNC221_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4c8) + +/* GPIO_SIG221_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG221_IN_SEL (BIT(7)) +#define GPIO_SIG221_IN_SEL_M (GPIO_SIG221_IN_SEL_V << GPIO_SIG221_IN_SEL_S) +#define GPIO_SIG221_IN_SEL_V 0x00000001 +#define GPIO_SIG221_IN_SEL_S 7 + +/* GPIO_FUNC221_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC221_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC221_IN_INV_SEL_M (GPIO_FUNC221_IN_INV_SEL_V << GPIO_FUNC221_IN_INV_SEL_S) +#define GPIO_FUNC221_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC221_IN_INV_SEL_S 6 + +/* GPIO_FUNC221_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC221_IN_SEL 0x0000003F +#define GPIO_FUNC221_IN_SEL_M (GPIO_FUNC221_IN_SEL_V << GPIO_FUNC221_IN_SEL_S) +#define GPIO_FUNC221_IN_SEL_V 0x0000003F +#define GPIO_FUNC221_IN_SEL_S 0 + +/* GPIO_FUNC222_IN_SEL_CFG_REG register + * Peripheral function 222 input selection register + */ + +#define GPIO_FUNC222_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4cc) + +/* GPIO_SIG222_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG222_IN_SEL (BIT(7)) +#define GPIO_SIG222_IN_SEL_M (GPIO_SIG222_IN_SEL_V << GPIO_SIG222_IN_SEL_S) +#define GPIO_SIG222_IN_SEL_V 0x00000001 +#define GPIO_SIG222_IN_SEL_S 7 + +/* GPIO_FUNC222_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC222_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC222_IN_INV_SEL_M (GPIO_FUNC222_IN_INV_SEL_V << GPIO_FUNC222_IN_INV_SEL_S) +#define GPIO_FUNC222_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC222_IN_INV_SEL_S 6 + +/* GPIO_FUNC222_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC222_IN_SEL 0x0000003F +#define GPIO_FUNC222_IN_SEL_M (GPIO_FUNC222_IN_SEL_V << GPIO_FUNC222_IN_SEL_S) +#define GPIO_FUNC222_IN_SEL_V 0x0000003F +#define GPIO_FUNC222_IN_SEL_S 0 + +/* GPIO_FUNC223_IN_SEL_CFG_REG register + * Peripheral function 223 input selection register + */ + +#define GPIO_FUNC223_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d0) + +/* GPIO_SIG223_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG223_IN_SEL (BIT(7)) +#define GPIO_SIG223_IN_SEL_M (GPIO_SIG223_IN_SEL_V << GPIO_SIG223_IN_SEL_S) +#define GPIO_SIG223_IN_SEL_V 0x00000001 +#define GPIO_SIG223_IN_SEL_S 7 + +/* GPIO_FUNC223_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC223_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC223_IN_INV_SEL_M (GPIO_FUNC223_IN_INV_SEL_V << GPIO_FUNC223_IN_INV_SEL_S) +#define GPIO_FUNC223_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC223_IN_INV_SEL_S 6 + +/* GPIO_FUNC223_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC223_IN_SEL 0x0000003F +#define GPIO_FUNC223_IN_SEL_M (GPIO_FUNC223_IN_SEL_V << GPIO_FUNC223_IN_SEL_S) +#define GPIO_FUNC223_IN_SEL_V 0x0000003F +#define GPIO_FUNC223_IN_SEL_S 0 + +/* GPIO_FUNC224_IN_SEL_CFG_REG register + * Peripheral function 224 input selection register + */ + +#define GPIO_FUNC224_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d4) + +/* GPIO_SIG224_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG224_IN_SEL (BIT(7)) +#define GPIO_SIG224_IN_SEL_M (GPIO_SIG224_IN_SEL_V << GPIO_SIG224_IN_SEL_S) +#define GPIO_SIG224_IN_SEL_V 0x00000001 +#define GPIO_SIG224_IN_SEL_S 7 + +/* GPIO_FUNC224_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC224_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC224_IN_INV_SEL_M (GPIO_FUNC224_IN_INV_SEL_V << GPIO_FUNC224_IN_INV_SEL_S) +#define GPIO_FUNC224_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC224_IN_INV_SEL_S 6 + +/* GPIO_FUNC224_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC224_IN_SEL 0x0000003F +#define GPIO_FUNC224_IN_SEL_M (GPIO_FUNC224_IN_SEL_V << GPIO_FUNC224_IN_SEL_S) +#define GPIO_FUNC224_IN_SEL_V 0x0000003F +#define GPIO_FUNC224_IN_SEL_S 0 + +/* GPIO_FUNC225_IN_SEL_CFG_REG register + * Peripheral function 225 input selection register + */ + +#define GPIO_FUNC225_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4d8) + +/* GPIO_SIG225_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG225_IN_SEL (BIT(7)) +#define GPIO_SIG225_IN_SEL_M (GPIO_SIG225_IN_SEL_V << GPIO_SIG225_IN_SEL_S) +#define GPIO_SIG225_IN_SEL_V 0x00000001 +#define GPIO_SIG225_IN_SEL_S 7 + +/* GPIO_FUNC225_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC225_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC225_IN_INV_SEL_M (GPIO_FUNC225_IN_INV_SEL_V << GPIO_FUNC225_IN_INV_SEL_S) +#define GPIO_FUNC225_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC225_IN_INV_SEL_S 6 + +/* GPIO_FUNC225_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC225_IN_SEL 0x0000003F +#define GPIO_FUNC225_IN_SEL_M (GPIO_FUNC225_IN_SEL_V << GPIO_FUNC225_IN_SEL_S) +#define GPIO_FUNC225_IN_SEL_V 0x0000003F +#define GPIO_FUNC225_IN_SEL_S 0 + +/* GPIO_FUNC226_IN_SEL_CFG_REG register + * Peripheral function 226 input selection register + */ + +#define GPIO_FUNC226_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4dc) + +/* GPIO_SIG226_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG226_IN_SEL (BIT(7)) +#define GPIO_SIG226_IN_SEL_M (GPIO_SIG226_IN_SEL_V << GPIO_SIG226_IN_SEL_S) +#define GPIO_SIG226_IN_SEL_V 0x00000001 +#define GPIO_SIG226_IN_SEL_S 7 + +/* GPIO_FUNC226_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC226_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC226_IN_INV_SEL_M (GPIO_FUNC226_IN_INV_SEL_V << GPIO_FUNC226_IN_INV_SEL_S) +#define GPIO_FUNC226_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC226_IN_INV_SEL_S 6 + +/* GPIO_FUNC226_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC226_IN_SEL 0x0000003F +#define GPIO_FUNC226_IN_SEL_M (GPIO_FUNC226_IN_SEL_V << GPIO_FUNC226_IN_SEL_S) +#define GPIO_FUNC226_IN_SEL_V 0x0000003F +#define GPIO_FUNC226_IN_SEL_S 0 + +/* GPIO_FUNC227_IN_SEL_CFG_REG register + * Peripheral function 227 input selection register + */ + +#define GPIO_FUNC227_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e0) + +/* GPIO_SIG227_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG227_IN_SEL (BIT(7)) +#define GPIO_SIG227_IN_SEL_M (GPIO_SIG227_IN_SEL_V << GPIO_SIG227_IN_SEL_S) +#define GPIO_SIG227_IN_SEL_V 0x00000001 +#define GPIO_SIG227_IN_SEL_S 7 + +/* GPIO_FUNC227_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC227_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC227_IN_INV_SEL_M (GPIO_FUNC227_IN_INV_SEL_V << GPIO_FUNC227_IN_INV_SEL_S) +#define GPIO_FUNC227_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC227_IN_INV_SEL_S 6 + +/* GPIO_FUNC227_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC227_IN_SEL 0x0000003F +#define GPIO_FUNC227_IN_SEL_M (GPIO_FUNC227_IN_SEL_V << GPIO_FUNC227_IN_SEL_S) +#define GPIO_FUNC227_IN_SEL_V 0x0000003F +#define GPIO_FUNC227_IN_SEL_S 0 + +/* GPIO_FUNC228_IN_SEL_CFG_REG register + * Peripheral function 228 input selection register + */ + +#define GPIO_FUNC228_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e4) + +/* GPIO_SIG228_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG228_IN_SEL (BIT(7)) +#define GPIO_SIG228_IN_SEL_M (GPIO_SIG228_IN_SEL_V << GPIO_SIG228_IN_SEL_S) +#define GPIO_SIG228_IN_SEL_V 0x00000001 +#define GPIO_SIG228_IN_SEL_S 7 + +/* GPIO_FUNC228_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC228_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC228_IN_INV_SEL_M (GPIO_FUNC228_IN_INV_SEL_V << GPIO_FUNC228_IN_INV_SEL_S) +#define GPIO_FUNC228_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC228_IN_INV_SEL_S 6 + +/* GPIO_FUNC228_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC228_IN_SEL 0x0000003F +#define GPIO_FUNC228_IN_SEL_M (GPIO_FUNC228_IN_SEL_V << GPIO_FUNC228_IN_SEL_S) +#define GPIO_FUNC228_IN_SEL_V 0x0000003F +#define GPIO_FUNC228_IN_SEL_S 0 + +/* GPIO_FUNC229_IN_SEL_CFG_REG register + * Peripheral function 229 input selection register + */ + +#define GPIO_FUNC229_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4e8) + +/* GPIO_SIG229_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG229_IN_SEL (BIT(7)) +#define GPIO_SIG229_IN_SEL_M (GPIO_SIG229_IN_SEL_V << GPIO_SIG229_IN_SEL_S) +#define GPIO_SIG229_IN_SEL_V 0x00000001 +#define GPIO_SIG229_IN_SEL_S 7 + +/* GPIO_FUNC229_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC229_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC229_IN_INV_SEL_M (GPIO_FUNC229_IN_INV_SEL_V << GPIO_FUNC229_IN_INV_SEL_S) +#define GPIO_FUNC229_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC229_IN_INV_SEL_S 6 + +/* GPIO_FUNC229_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC229_IN_SEL 0x0000003F +#define GPIO_FUNC229_IN_SEL_M (GPIO_FUNC229_IN_SEL_V << GPIO_FUNC229_IN_SEL_S) +#define GPIO_FUNC229_IN_SEL_V 0x0000003F +#define GPIO_FUNC229_IN_SEL_S 0 + +/* GPIO_FUNC230_IN_SEL_CFG_REG register + * Peripheral function 230 input selection register + */ + +#define GPIO_FUNC230_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4ec) + +/* GPIO_SIG230_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG230_IN_SEL (BIT(7)) +#define GPIO_SIG230_IN_SEL_M (GPIO_SIG230_IN_SEL_V << GPIO_SIG230_IN_SEL_S) +#define GPIO_SIG230_IN_SEL_V 0x00000001 +#define GPIO_SIG230_IN_SEL_S 7 + +/* GPIO_FUNC230_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC230_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC230_IN_INV_SEL_M (GPIO_FUNC230_IN_INV_SEL_V << GPIO_FUNC230_IN_INV_SEL_S) +#define GPIO_FUNC230_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC230_IN_INV_SEL_S 6 + +/* GPIO_FUNC230_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC230_IN_SEL 0x0000003F +#define GPIO_FUNC230_IN_SEL_M (GPIO_FUNC230_IN_SEL_V << GPIO_FUNC230_IN_SEL_S) +#define GPIO_FUNC230_IN_SEL_V 0x0000003F +#define GPIO_FUNC230_IN_SEL_S 0 + +/* GPIO_FUNC231_IN_SEL_CFG_REG register + * Peripheral function 231 input selection register + */ + +#define GPIO_FUNC231_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f0) + +/* GPIO_SIG231_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG231_IN_SEL (BIT(7)) +#define GPIO_SIG231_IN_SEL_M (GPIO_SIG231_IN_SEL_V << GPIO_SIG231_IN_SEL_S) +#define GPIO_SIG231_IN_SEL_V 0x00000001 +#define GPIO_SIG231_IN_SEL_S 7 + +/* GPIO_FUNC231_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC231_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC231_IN_INV_SEL_M (GPIO_FUNC231_IN_INV_SEL_V << GPIO_FUNC231_IN_INV_SEL_S) +#define GPIO_FUNC231_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC231_IN_INV_SEL_S 6 + +/* GPIO_FUNC231_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC231_IN_SEL 0x0000003F +#define GPIO_FUNC231_IN_SEL_M (GPIO_FUNC231_IN_SEL_V << GPIO_FUNC231_IN_SEL_S) +#define GPIO_FUNC231_IN_SEL_V 0x0000003F +#define GPIO_FUNC231_IN_SEL_S 0 + +/* GPIO_FUNC232_IN_SEL_CFG_REG register + * Peripheral function 232 input selection register + */ + +#define GPIO_FUNC232_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f4) + +/* GPIO_SIG232_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG232_IN_SEL (BIT(7)) +#define GPIO_SIG232_IN_SEL_M (GPIO_SIG232_IN_SEL_V << GPIO_SIG232_IN_SEL_S) +#define GPIO_SIG232_IN_SEL_V 0x00000001 +#define GPIO_SIG232_IN_SEL_S 7 + +/* GPIO_FUNC232_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC232_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC232_IN_INV_SEL_M (GPIO_FUNC232_IN_INV_SEL_V << GPIO_FUNC232_IN_INV_SEL_S) +#define GPIO_FUNC232_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC232_IN_INV_SEL_S 6 + +/* GPIO_FUNC232_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC232_IN_SEL 0x0000003F +#define GPIO_FUNC232_IN_SEL_M (GPIO_FUNC232_IN_SEL_V << GPIO_FUNC232_IN_SEL_S) +#define GPIO_FUNC232_IN_SEL_V 0x0000003F +#define GPIO_FUNC232_IN_SEL_S 0 + +/* GPIO_FUNC233_IN_SEL_CFG_REG register + * Peripheral function 233 input selection register + */ + +#define GPIO_FUNC233_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4f8) + +/* GPIO_SIG233_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG233_IN_SEL (BIT(7)) +#define GPIO_SIG233_IN_SEL_M (GPIO_SIG233_IN_SEL_V << GPIO_SIG233_IN_SEL_S) +#define GPIO_SIG233_IN_SEL_V 0x00000001 +#define GPIO_SIG233_IN_SEL_S 7 + +/* GPIO_FUNC233_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC233_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC233_IN_INV_SEL_M (GPIO_FUNC233_IN_INV_SEL_V << GPIO_FUNC233_IN_INV_SEL_S) +#define GPIO_FUNC233_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC233_IN_INV_SEL_S 6 + +/* GPIO_FUNC233_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC233_IN_SEL 0x0000003F +#define GPIO_FUNC233_IN_SEL_M (GPIO_FUNC233_IN_SEL_V << GPIO_FUNC233_IN_SEL_S) +#define GPIO_FUNC233_IN_SEL_V 0x0000003F +#define GPIO_FUNC233_IN_SEL_S 0 + +/* GPIO_FUNC234_IN_SEL_CFG_REG register + * Peripheral function 234 input selection register + */ + +#define GPIO_FUNC234_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4fc) + +/* GPIO_SIG234_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG234_IN_SEL (BIT(7)) +#define GPIO_SIG234_IN_SEL_M (GPIO_SIG234_IN_SEL_V << GPIO_SIG234_IN_SEL_S) +#define GPIO_SIG234_IN_SEL_V 0x00000001 +#define GPIO_SIG234_IN_SEL_S 7 + +/* GPIO_FUNC234_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC234_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC234_IN_INV_SEL_M (GPIO_FUNC234_IN_INV_SEL_V << GPIO_FUNC234_IN_INV_SEL_S) +#define GPIO_FUNC234_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC234_IN_INV_SEL_S 6 + +/* GPIO_FUNC234_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC234_IN_SEL 0x0000003F +#define GPIO_FUNC234_IN_SEL_M (GPIO_FUNC234_IN_SEL_V << GPIO_FUNC234_IN_SEL_S) +#define GPIO_FUNC234_IN_SEL_V 0x0000003F +#define GPIO_FUNC234_IN_SEL_S 0 + +/* GPIO_FUNC235_IN_SEL_CFG_REG register + * Peripheral function 235 input selection register + */ + +#define GPIO_FUNC235_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x500) + +/* GPIO_SIG235_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG235_IN_SEL (BIT(7)) +#define GPIO_SIG235_IN_SEL_M (GPIO_SIG235_IN_SEL_V << GPIO_SIG235_IN_SEL_S) +#define GPIO_SIG235_IN_SEL_V 0x00000001 +#define GPIO_SIG235_IN_SEL_S 7 + +/* GPIO_FUNC235_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC235_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC235_IN_INV_SEL_M (GPIO_FUNC235_IN_INV_SEL_V << GPIO_FUNC235_IN_INV_SEL_S) +#define GPIO_FUNC235_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC235_IN_INV_SEL_S 6 + +/* GPIO_FUNC235_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC235_IN_SEL 0x0000003F +#define GPIO_FUNC235_IN_SEL_M (GPIO_FUNC235_IN_SEL_V << GPIO_FUNC235_IN_SEL_S) +#define GPIO_FUNC235_IN_SEL_V 0x0000003F +#define GPIO_FUNC235_IN_SEL_S 0 + +/* GPIO_FUNC236_IN_SEL_CFG_REG register + * Peripheral function 236 input selection register + */ + +#define GPIO_FUNC236_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x504) + +/* GPIO_SIG236_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG236_IN_SEL (BIT(7)) +#define GPIO_SIG236_IN_SEL_M (GPIO_SIG236_IN_SEL_V << GPIO_SIG236_IN_SEL_S) +#define GPIO_SIG236_IN_SEL_V 0x00000001 +#define GPIO_SIG236_IN_SEL_S 7 + +/* GPIO_FUNC236_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC236_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC236_IN_INV_SEL_M (GPIO_FUNC236_IN_INV_SEL_V << GPIO_FUNC236_IN_INV_SEL_S) +#define GPIO_FUNC236_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC236_IN_INV_SEL_S 6 + +/* GPIO_FUNC236_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC236_IN_SEL 0x0000003F +#define GPIO_FUNC236_IN_SEL_M (GPIO_FUNC236_IN_SEL_V << GPIO_FUNC236_IN_SEL_S) +#define GPIO_FUNC236_IN_SEL_V 0x0000003F +#define GPIO_FUNC236_IN_SEL_S 0 + +/* GPIO_FUNC237_IN_SEL_CFG_REG register + * Peripheral function 237 input selection register + */ + +#define GPIO_FUNC237_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x508) + +/* GPIO_SIG237_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG237_IN_SEL (BIT(7)) +#define GPIO_SIG237_IN_SEL_M (GPIO_SIG237_IN_SEL_V << GPIO_SIG237_IN_SEL_S) +#define GPIO_SIG237_IN_SEL_V 0x00000001 +#define GPIO_SIG237_IN_SEL_S 7 + +/* GPIO_FUNC237_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC237_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC237_IN_INV_SEL_M (GPIO_FUNC237_IN_INV_SEL_V << GPIO_FUNC237_IN_INV_SEL_S) +#define GPIO_FUNC237_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC237_IN_INV_SEL_S 6 + +/* GPIO_FUNC237_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC237_IN_SEL 0x0000003F +#define GPIO_FUNC237_IN_SEL_M (GPIO_FUNC237_IN_SEL_V << GPIO_FUNC237_IN_SEL_S) +#define GPIO_FUNC237_IN_SEL_V 0x0000003F +#define GPIO_FUNC237_IN_SEL_S 0 + +/* GPIO_FUNC238_IN_SEL_CFG_REG register + * Peripheral function 238 input selection register + */ + +#define GPIO_FUNC238_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x50c) + +/* GPIO_SIG238_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG238_IN_SEL (BIT(7)) +#define GPIO_SIG238_IN_SEL_M (GPIO_SIG238_IN_SEL_V << GPIO_SIG238_IN_SEL_S) +#define GPIO_SIG238_IN_SEL_V 0x00000001 +#define GPIO_SIG238_IN_SEL_S 7 + +/* GPIO_FUNC238_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC238_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC238_IN_INV_SEL_M (GPIO_FUNC238_IN_INV_SEL_V << GPIO_FUNC238_IN_INV_SEL_S) +#define GPIO_FUNC238_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC238_IN_INV_SEL_S 6 + +/* GPIO_FUNC238_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC238_IN_SEL 0x0000003F +#define GPIO_FUNC238_IN_SEL_M (GPIO_FUNC238_IN_SEL_V << GPIO_FUNC238_IN_SEL_S) +#define GPIO_FUNC238_IN_SEL_V 0x0000003F +#define GPIO_FUNC238_IN_SEL_S 0 + +/* GPIO_FUNC239_IN_SEL_CFG_REG register + * Peripheral function 239 input selection register + */ + +#define GPIO_FUNC239_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x510) + +/* GPIO_SIG239_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG239_IN_SEL (BIT(7)) +#define GPIO_SIG239_IN_SEL_M (GPIO_SIG239_IN_SEL_V << GPIO_SIG239_IN_SEL_S) +#define GPIO_SIG239_IN_SEL_V 0x00000001 +#define GPIO_SIG239_IN_SEL_S 7 + +/* GPIO_FUNC239_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC239_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC239_IN_INV_SEL_M (GPIO_FUNC239_IN_INV_SEL_V << GPIO_FUNC239_IN_INV_SEL_S) +#define GPIO_FUNC239_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC239_IN_INV_SEL_S 6 + +/* GPIO_FUNC239_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC239_IN_SEL 0x0000003F +#define GPIO_FUNC239_IN_SEL_M (GPIO_FUNC239_IN_SEL_V << GPIO_FUNC239_IN_SEL_S) +#define GPIO_FUNC239_IN_SEL_V 0x0000003F +#define GPIO_FUNC239_IN_SEL_S 0 + +/* GPIO_FUNC240_IN_SEL_CFG_REG register + * Peripheral function 240 input selection register + */ + +#define GPIO_FUNC240_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x514) + +/* GPIO_SIG240_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG240_IN_SEL (BIT(7)) +#define GPIO_SIG240_IN_SEL_M (GPIO_SIG240_IN_SEL_V << GPIO_SIG240_IN_SEL_S) +#define GPIO_SIG240_IN_SEL_V 0x00000001 +#define GPIO_SIG240_IN_SEL_S 7 + +/* GPIO_FUNC240_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC240_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC240_IN_INV_SEL_M (GPIO_FUNC240_IN_INV_SEL_V << GPIO_FUNC240_IN_INV_SEL_S) +#define GPIO_FUNC240_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC240_IN_INV_SEL_S 6 + +/* GPIO_FUNC240_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC240_IN_SEL 0x0000003F +#define GPIO_FUNC240_IN_SEL_M (GPIO_FUNC240_IN_SEL_V << GPIO_FUNC240_IN_SEL_S) +#define GPIO_FUNC240_IN_SEL_V 0x0000003F +#define GPIO_FUNC240_IN_SEL_S 0 + +/* GPIO_FUNC241_IN_SEL_CFG_REG register + * Peripheral function 241 input selection register + */ + +#define GPIO_FUNC241_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x518) + +/* GPIO_SIG241_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG241_IN_SEL (BIT(7)) +#define GPIO_SIG241_IN_SEL_M (GPIO_SIG241_IN_SEL_V << GPIO_SIG241_IN_SEL_S) +#define GPIO_SIG241_IN_SEL_V 0x00000001 +#define GPIO_SIG241_IN_SEL_S 7 + +/* GPIO_FUNC241_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC241_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC241_IN_INV_SEL_M (GPIO_FUNC241_IN_INV_SEL_V << GPIO_FUNC241_IN_INV_SEL_S) +#define GPIO_FUNC241_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC241_IN_INV_SEL_S 6 + +/* GPIO_FUNC241_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC241_IN_SEL 0x0000003F +#define GPIO_FUNC241_IN_SEL_M (GPIO_FUNC241_IN_SEL_V << GPIO_FUNC241_IN_SEL_S) +#define GPIO_FUNC241_IN_SEL_V 0x0000003F +#define GPIO_FUNC241_IN_SEL_S 0 + +/* GPIO_FUNC242_IN_SEL_CFG_REG register + * Peripheral function 242 input selection register + */ + +#define GPIO_FUNC242_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x51c) + +/* GPIO_SIG242_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG242_IN_SEL (BIT(7)) +#define GPIO_SIG242_IN_SEL_M (GPIO_SIG242_IN_SEL_V << GPIO_SIG242_IN_SEL_S) +#define GPIO_SIG242_IN_SEL_V 0x00000001 +#define GPIO_SIG242_IN_SEL_S 7 + +/* GPIO_FUNC242_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC242_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC242_IN_INV_SEL_M (GPIO_FUNC242_IN_INV_SEL_V << GPIO_FUNC242_IN_INV_SEL_S) +#define GPIO_FUNC242_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC242_IN_INV_SEL_S 6 + +/* GPIO_FUNC242_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC242_IN_SEL 0x0000003F +#define GPIO_FUNC242_IN_SEL_M (GPIO_FUNC242_IN_SEL_V << GPIO_FUNC242_IN_SEL_S) +#define GPIO_FUNC242_IN_SEL_V 0x0000003F +#define GPIO_FUNC242_IN_SEL_S 0 + +/* GPIO_FUNC243_IN_SEL_CFG_REG register + * Peripheral function 243 input selection register + */ + +#define GPIO_FUNC243_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x520) + +/* GPIO_SIG243_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG243_IN_SEL (BIT(7)) +#define GPIO_SIG243_IN_SEL_M (GPIO_SIG243_IN_SEL_V << GPIO_SIG243_IN_SEL_S) +#define GPIO_SIG243_IN_SEL_V 0x00000001 +#define GPIO_SIG243_IN_SEL_S 7 + +/* GPIO_FUNC243_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC243_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC243_IN_INV_SEL_M (GPIO_FUNC243_IN_INV_SEL_V << GPIO_FUNC243_IN_INV_SEL_S) +#define GPIO_FUNC243_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC243_IN_INV_SEL_S 6 + +/* GPIO_FUNC243_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC243_IN_SEL 0x0000003F +#define GPIO_FUNC243_IN_SEL_M (GPIO_FUNC243_IN_SEL_V << GPIO_FUNC243_IN_SEL_S) +#define GPIO_FUNC243_IN_SEL_V 0x0000003F +#define GPIO_FUNC243_IN_SEL_S 0 + +/* GPIO_FUNC244_IN_SEL_CFG_REG register + * Peripheral function 244 input selection register + */ + +#define GPIO_FUNC244_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x524) + +/* GPIO_SIG244_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG244_IN_SEL (BIT(7)) +#define GPIO_SIG244_IN_SEL_M (GPIO_SIG244_IN_SEL_V << GPIO_SIG244_IN_SEL_S) +#define GPIO_SIG244_IN_SEL_V 0x00000001 +#define GPIO_SIG244_IN_SEL_S 7 + +/* GPIO_FUNC244_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC244_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC244_IN_INV_SEL_M (GPIO_FUNC244_IN_INV_SEL_V << GPIO_FUNC244_IN_INV_SEL_S) +#define GPIO_FUNC244_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC244_IN_INV_SEL_S 6 + +/* GPIO_FUNC244_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC244_IN_SEL 0x0000003F +#define GPIO_FUNC244_IN_SEL_M (GPIO_FUNC244_IN_SEL_V << GPIO_FUNC244_IN_SEL_S) +#define GPIO_FUNC244_IN_SEL_V 0x0000003F +#define GPIO_FUNC244_IN_SEL_S 0 + +/* GPIO_FUNC245_IN_SEL_CFG_REG register + * Peripheral function 245 input selection register + */ + +#define GPIO_FUNC245_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x528) + +/* GPIO_SIG245_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG245_IN_SEL (BIT(7)) +#define GPIO_SIG245_IN_SEL_M (GPIO_SIG245_IN_SEL_V << GPIO_SIG245_IN_SEL_S) +#define GPIO_SIG245_IN_SEL_V 0x00000001 +#define GPIO_SIG245_IN_SEL_S 7 + +/* GPIO_FUNC245_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC245_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC245_IN_INV_SEL_M (GPIO_FUNC245_IN_INV_SEL_V << GPIO_FUNC245_IN_INV_SEL_S) +#define GPIO_FUNC245_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC245_IN_INV_SEL_S 6 + +/* GPIO_FUNC245_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC245_IN_SEL 0x0000003F +#define GPIO_FUNC245_IN_SEL_M (GPIO_FUNC245_IN_SEL_V << GPIO_FUNC245_IN_SEL_S) +#define GPIO_FUNC245_IN_SEL_V 0x0000003F +#define GPIO_FUNC245_IN_SEL_S 0 + +/* GPIO_FUNC246_IN_SEL_CFG_REG register + * Peripheral function 246 input selection register + */ + +#define GPIO_FUNC246_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x52c) + +/* GPIO_SIG246_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG246_IN_SEL (BIT(7)) +#define GPIO_SIG246_IN_SEL_M (GPIO_SIG246_IN_SEL_V << GPIO_SIG246_IN_SEL_S) +#define GPIO_SIG246_IN_SEL_V 0x00000001 +#define GPIO_SIG246_IN_SEL_S 7 + +/* GPIO_FUNC246_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC246_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC246_IN_INV_SEL_M (GPIO_FUNC246_IN_INV_SEL_V << GPIO_FUNC246_IN_INV_SEL_S) +#define GPIO_FUNC246_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC246_IN_INV_SEL_S 6 + +/* GPIO_FUNC246_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC246_IN_SEL 0x0000003F +#define GPIO_FUNC246_IN_SEL_M (GPIO_FUNC246_IN_SEL_V << GPIO_FUNC246_IN_SEL_S) +#define GPIO_FUNC246_IN_SEL_V 0x0000003F +#define GPIO_FUNC246_IN_SEL_S 0 + +/* GPIO_FUNC247_IN_SEL_CFG_REG register + * Peripheral function 247 input selection register + */ + +#define GPIO_FUNC247_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x530) + +/* GPIO_SIG247_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG247_IN_SEL (BIT(7)) +#define GPIO_SIG247_IN_SEL_M (GPIO_SIG247_IN_SEL_V << GPIO_SIG247_IN_SEL_S) +#define GPIO_SIG247_IN_SEL_V 0x00000001 +#define GPIO_SIG247_IN_SEL_S 7 + +/* GPIO_FUNC247_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC247_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC247_IN_INV_SEL_M (GPIO_FUNC247_IN_INV_SEL_V << GPIO_FUNC247_IN_INV_SEL_S) +#define GPIO_FUNC247_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC247_IN_INV_SEL_S 6 + +/* GPIO_FUNC247_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC247_IN_SEL 0x0000003F +#define GPIO_FUNC247_IN_SEL_M (GPIO_FUNC247_IN_SEL_V << GPIO_FUNC247_IN_SEL_S) +#define GPIO_FUNC247_IN_SEL_V 0x0000003F +#define GPIO_FUNC247_IN_SEL_S 0 + +/* GPIO_FUNC248_IN_SEL_CFG_REG register + * Peripheral function 248 input selection register + */ + +#define GPIO_FUNC248_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x534) + +/* GPIO_SIG248_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG248_IN_SEL (BIT(7)) +#define GPIO_SIG248_IN_SEL_M (GPIO_SIG248_IN_SEL_V << GPIO_SIG248_IN_SEL_S) +#define GPIO_SIG248_IN_SEL_V 0x00000001 +#define GPIO_SIG248_IN_SEL_S 7 + +/* GPIO_FUNC248_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC248_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC248_IN_INV_SEL_M (GPIO_FUNC248_IN_INV_SEL_V << GPIO_FUNC248_IN_INV_SEL_S) +#define GPIO_FUNC248_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC248_IN_INV_SEL_S 6 + +/* GPIO_FUNC248_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC248_IN_SEL 0x0000003F +#define GPIO_FUNC248_IN_SEL_M (GPIO_FUNC248_IN_SEL_V << GPIO_FUNC248_IN_SEL_S) +#define GPIO_FUNC248_IN_SEL_V 0x0000003F +#define GPIO_FUNC248_IN_SEL_S 0 + +/* GPIO_FUNC249_IN_SEL_CFG_REG register + * Peripheral function 249 input selection register + */ + +#define GPIO_FUNC249_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x538) + +/* GPIO_SIG249_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG249_IN_SEL (BIT(7)) +#define GPIO_SIG249_IN_SEL_M (GPIO_SIG249_IN_SEL_V << GPIO_SIG249_IN_SEL_S) +#define GPIO_SIG249_IN_SEL_V 0x00000001 +#define GPIO_SIG249_IN_SEL_S 7 + +/* GPIO_FUNC249_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC249_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC249_IN_INV_SEL_M (GPIO_FUNC249_IN_INV_SEL_V << GPIO_FUNC249_IN_INV_SEL_S) +#define GPIO_FUNC249_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC249_IN_INV_SEL_S 6 + +/* GPIO_FUNC249_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC249_IN_SEL 0x0000003F +#define GPIO_FUNC249_IN_SEL_M (GPIO_FUNC249_IN_SEL_V << GPIO_FUNC249_IN_SEL_S) +#define GPIO_FUNC249_IN_SEL_V 0x0000003F +#define GPIO_FUNC249_IN_SEL_S 0 + +/* GPIO_FUNC250_IN_SEL_CFG_REG register + * Peripheral function 250 input selection register + */ + +#define GPIO_FUNC250_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x53c) + +/* GPIO_SIG250_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG250_IN_SEL (BIT(7)) +#define GPIO_SIG250_IN_SEL_M (GPIO_SIG250_IN_SEL_V << GPIO_SIG250_IN_SEL_S) +#define GPIO_SIG250_IN_SEL_V 0x00000001 +#define GPIO_SIG250_IN_SEL_S 7 + +/* GPIO_FUNC250_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC250_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC250_IN_INV_SEL_M (GPIO_FUNC250_IN_INV_SEL_V << GPIO_FUNC250_IN_INV_SEL_S) +#define GPIO_FUNC250_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC250_IN_INV_SEL_S 6 + +/* GPIO_FUNC250_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC250_IN_SEL 0x0000003F +#define GPIO_FUNC250_IN_SEL_M (GPIO_FUNC250_IN_SEL_V << GPIO_FUNC250_IN_SEL_S) +#define GPIO_FUNC250_IN_SEL_V 0x0000003F +#define GPIO_FUNC250_IN_SEL_S 0 + +/* GPIO_FUNC251_IN_SEL_CFG_REG register + * Peripheral function 251 input selection register + */ + +#define GPIO_FUNC251_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x540) + +/* GPIO_SIG251_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG251_IN_SEL (BIT(7)) +#define GPIO_SIG251_IN_SEL_M (GPIO_SIG251_IN_SEL_V << GPIO_SIG251_IN_SEL_S) +#define GPIO_SIG251_IN_SEL_V 0x00000001 +#define GPIO_SIG251_IN_SEL_S 7 + +/* GPIO_FUNC251_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC251_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC251_IN_INV_SEL_M (GPIO_FUNC251_IN_INV_SEL_V << GPIO_FUNC251_IN_INV_SEL_S) +#define GPIO_FUNC251_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC251_IN_INV_SEL_S 6 + +/* GPIO_FUNC251_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC251_IN_SEL 0x0000003F +#define GPIO_FUNC251_IN_SEL_M (GPIO_FUNC251_IN_SEL_V << GPIO_FUNC251_IN_SEL_S) +#define GPIO_FUNC251_IN_SEL_V 0x0000003F +#define GPIO_FUNC251_IN_SEL_S 0 + +/* GPIO_FUNC252_IN_SEL_CFG_REG register + * Peripheral function 252 input selection register + */ + +#define GPIO_FUNC252_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x544) + +/* GPIO_SIG252_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG252_IN_SEL (BIT(7)) +#define GPIO_SIG252_IN_SEL_M (GPIO_SIG252_IN_SEL_V << GPIO_SIG252_IN_SEL_S) +#define GPIO_SIG252_IN_SEL_V 0x00000001 +#define GPIO_SIG252_IN_SEL_S 7 + +/* GPIO_FUNC252_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC252_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC252_IN_INV_SEL_M (GPIO_FUNC252_IN_INV_SEL_V << GPIO_FUNC252_IN_INV_SEL_S) +#define GPIO_FUNC252_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC252_IN_INV_SEL_S 6 + +/* GPIO_FUNC252_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC252_IN_SEL 0x0000003F +#define GPIO_FUNC252_IN_SEL_M (GPIO_FUNC252_IN_SEL_V << GPIO_FUNC252_IN_SEL_S) +#define GPIO_FUNC252_IN_SEL_V 0x0000003F +#define GPIO_FUNC252_IN_SEL_S 0 + +/* GPIO_FUNC253_IN_SEL_CFG_REG register + * Peripheral function 253 input selection register + */ + +#define GPIO_FUNC253_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x548) + +/* GPIO_SIG253_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG253_IN_SEL (BIT(7)) +#define GPIO_SIG253_IN_SEL_M (GPIO_SIG253_IN_SEL_V << GPIO_SIG253_IN_SEL_S) +#define GPIO_SIG253_IN_SEL_V 0x00000001 +#define GPIO_SIG253_IN_SEL_S 7 + +/* GPIO_FUNC253_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC253_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC253_IN_INV_SEL_M (GPIO_FUNC253_IN_INV_SEL_V << GPIO_FUNC253_IN_INV_SEL_S) +#define GPIO_FUNC253_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC253_IN_INV_SEL_S 6 + +/* GPIO_FUNC253_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC253_IN_SEL 0x0000003F +#define GPIO_FUNC253_IN_SEL_M (GPIO_FUNC253_IN_SEL_V << GPIO_FUNC253_IN_SEL_S) +#define GPIO_FUNC253_IN_SEL_V 0x0000003F +#define GPIO_FUNC253_IN_SEL_S 0 + +/* GPIO_FUNC254_IN_SEL_CFG_REG register + * Peripheral function 254 input selection register + */ + +#define GPIO_FUNC254_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x54c) + +/* GPIO_SIG254_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG254_IN_SEL (BIT(7)) +#define GPIO_SIG254_IN_SEL_M (GPIO_SIG254_IN_SEL_V << GPIO_SIG254_IN_SEL_S) +#define GPIO_SIG254_IN_SEL_V 0x00000001 +#define GPIO_SIG254_IN_SEL_S 7 + +/* GPIO_FUNC254_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC254_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC254_IN_INV_SEL_M (GPIO_FUNC254_IN_INV_SEL_V << GPIO_FUNC254_IN_INV_SEL_S) +#define GPIO_FUNC254_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC254_IN_INV_SEL_S 6 + +/* GPIO_FUNC254_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC254_IN_SEL 0x0000003F +#define GPIO_FUNC254_IN_SEL_M (GPIO_FUNC254_IN_SEL_V << GPIO_FUNC254_IN_SEL_S) +#define GPIO_FUNC254_IN_SEL_V 0x0000003F +#define GPIO_FUNC254_IN_SEL_S 0 + +/* GPIO_FUNC255_IN_SEL_CFG_REG register + * Peripheral function 255 input selection register + */ + +#define GPIO_FUNC255_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x550) + +/* GPIO_SIG255_IN_SEL : R/W; bitpos: [7]; default: 0; + * Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals + * directly to peripheral configured in IO_MUX. + */ + +#define GPIO_SIG255_IN_SEL (BIT(7)) +#define GPIO_SIG255_IN_SEL_M (GPIO_SIG255_IN_SEL_V << GPIO_SIG255_IN_SEL_S) +#define GPIO_SIG255_IN_SEL_V 0x00000001 +#define GPIO_SIG255_IN_SEL_S 7 + +/* GPIO_FUNC255_IN_INV_SEL : R/W; bitpos: [6]; default: 0; + * Invert the input value. 1: invert enabled; 0: invert disabled. + */ + +#define GPIO_FUNC255_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC255_IN_INV_SEL_M (GPIO_FUNC255_IN_INV_SEL_V << GPIO_FUNC255_IN_INV_SEL_S) +#define GPIO_FUNC255_IN_INV_SEL_V 0x00000001 +#define GPIO_FUNC255_IN_INV_SEL_S 6 + +/* GPIO_FUNC255_IN_SEL : R/W; bitpos: [5:0]; default: 0; + * Selection control for peripheral input signal m, selects a pad from the + * 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a + * constantly high input or 0x3C for a constantly low input. + */ + +#define GPIO_FUNC255_IN_SEL 0x0000003F +#define GPIO_FUNC255_IN_SEL_M (GPIO_FUNC255_IN_SEL_V << GPIO_FUNC255_IN_SEL_S) +#define GPIO_FUNC255_IN_SEL_V 0x0000003F +#define GPIO_FUNC255_IN_SEL_S 0 + +/* GPIO_FUNC0_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 0 + */ + +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) + +/* GPIO_FUNC0_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC0_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC0_OEN_INV_SEL_M (GPIO_FUNC0_OEN_INV_SEL_V << GPIO_FUNC0_OEN_INV_SEL_S) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC0_OEN_INV_SEL_S 11 + +/* GPIO_FUNC0_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC0_OEN_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_SEL_M (GPIO_FUNC0_OEN_SEL_V << GPIO_FUNC0_OEN_SEL_S) +#define GPIO_FUNC0_OEN_SEL_V 0x00000001 +#define GPIO_FUNC0_OEN_SEL_S 10 + +/* GPIO_FUNC0_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC0_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC0_OUT_INV_SEL_S 9 + +/* GPIO_FUNC0_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC0_OUT_SEL 0x000001FF +#define GPIO_FUNC0_OUT_SEL_M (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S) +#define GPIO_FUNC0_OUT_SEL_V 0x000001FF +#define GPIO_FUNC0_OUT_SEL_S 0 + +/* GPIO_FUNC1_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 1 + */ + +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) + +/* GPIO_FUNC1_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC1_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC1_OEN_INV_SEL_M (GPIO_FUNC1_OEN_INV_SEL_V << GPIO_FUNC1_OEN_INV_SEL_S) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC1_OEN_INV_SEL_S 11 + +/* GPIO_FUNC1_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC1_OEN_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_SEL_M (GPIO_FUNC1_OEN_SEL_V << GPIO_FUNC1_OEN_SEL_S) +#define GPIO_FUNC1_OEN_SEL_V 0x00000001 +#define GPIO_FUNC1_OEN_SEL_S 10 + +/* GPIO_FUNC1_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC1_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC1_OUT_INV_SEL_S 9 + +/* GPIO_FUNC1_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC1_OUT_SEL 0x000001FF +#define GPIO_FUNC1_OUT_SEL_M (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S) +#define GPIO_FUNC1_OUT_SEL_V 0x000001FF +#define GPIO_FUNC1_OUT_SEL_S 0 + +/* GPIO_FUNC2_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 2 + */ + +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c) + +/* GPIO_FUNC2_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC2_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC2_OEN_INV_SEL_M (GPIO_FUNC2_OEN_INV_SEL_V << GPIO_FUNC2_OEN_INV_SEL_S) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC2_OEN_INV_SEL_S 11 + +/* GPIO_FUNC2_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC2_OEN_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_SEL_M (GPIO_FUNC2_OEN_SEL_V << GPIO_FUNC2_OEN_SEL_S) +#define GPIO_FUNC2_OEN_SEL_V 0x00000001 +#define GPIO_FUNC2_OEN_SEL_S 10 + +/* GPIO_FUNC2_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC2_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC2_OUT_INV_SEL_S 9 + +/* GPIO_FUNC2_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC2_OUT_SEL 0x000001FF +#define GPIO_FUNC2_OUT_SEL_M (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S) +#define GPIO_FUNC2_OUT_SEL_V 0x000001FF +#define GPIO_FUNC2_OUT_SEL_S 0 + +/* GPIO_FUNC3_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 3 + */ + +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) + +/* GPIO_FUNC3_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC3_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC3_OEN_INV_SEL_M (GPIO_FUNC3_OEN_INV_SEL_V << GPIO_FUNC3_OEN_INV_SEL_S) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC3_OEN_INV_SEL_S 11 + +/* GPIO_FUNC3_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC3_OEN_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_SEL_M (GPIO_FUNC3_OEN_SEL_V << GPIO_FUNC3_OEN_SEL_S) +#define GPIO_FUNC3_OEN_SEL_V 0x00000001 +#define GPIO_FUNC3_OEN_SEL_S 10 + +/* GPIO_FUNC3_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC3_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC3_OUT_INV_SEL_S 9 + +/* GPIO_FUNC3_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC3_OUT_SEL 0x000001FF +#define GPIO_FUNC3_OUT_SEL_M (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S) +#define GPIO_FUNC3_OUT_SEL_V 0x000001FF +#define GPIO_FUNC3_OUT_SEL_S 0 + +/* GPIO_FUNC4_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 4 + */ + +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) + +/* GPIO_FUNC4_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC4_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC4_OEN_INV_SEL_M (GPIO_FUNC4_OEN_INV_SEL_V << GPIO_FUNC4_OEN_INV_SEL_S) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC4_OEN_INV_SEL_S 11 + +/* GPIO_FUNC4_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC4_OEN_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_SEL_M (GPIO_FUNC4_OEN_SEL_V << GPIO_FUNC4_OEN_SEL_S) +#define GPIO_FUNC4_OEN_SEL_V 0x00000001 +#define GPIO_FUNC4_OEN_SEL_S 10 + +/* GPIO_FUNC4_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC4_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC4_OUT_INV_SEL_S 9 + +/* GPIO_FUNC4_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC4_OUT_SEL 0x000001FF +#define GPIO_FUNC4_OUT_SEL_M (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S) +#define GPIO_FUNC4_OUT_SEL_V 0x000001FF +#define GPIO_FUNC4_OUT_SEL_S 0 + +/* GPIO_FUNC5_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 5 + */ + +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) + +/* GPIO_FUNC5_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC5_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC5_OEN_INV_SEL_M (GPIO_FUNC5_OEN_INV_SEL_V << GPIO_FUNC5_OEN_INV_SEL_S) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC5_OEN_INV_SEL_S 11 + +/* GPIO_FUNC5_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC5_OEN_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_SEL_M (GPIO_FUNC5_OEN_SEL_V << GPIO_FUNC5_OEN_SEL_S) +#define GPIO_FUNC5_OEN_SEL_V 0x00000001 +#define GPIO_FUNC5_OEN_SEL_S 10 + +/* GPIO_FUNC5_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC5_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC5_OUT_INV_SEL_S 9 + +/* GPIO_FUNC5_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC5_OUT_SEL 0x000001FF +#define GPIO_FUNC5_OUT_SEL_M (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S) +#define GPIO_FUNC5_OUT_SEL_V 0x000001FF +#define GPIO_FUNC5_OUT_SEL_S 0 + +/* GPIO_FUNC6_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 6 + */ + +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c) + +/* GPIO_FUNC6_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC6_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC6_OEN_INV_SEL_M (GPIO_FUNC6_OEN_INV_SEL_V << GPIO_FUNC6_OEN_INV_SEL_S) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC6_OEN_INV_SEL_S 11 + +/* GPIO_FUNC6_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC6_OEN_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_SEL_M (GPIO_FUNC6_OEN_SEL_V << GPIO_FUNC6_OEN_SEL_S) +#define GPIO_FUNC6_OEN_SEL_V 0x00000001 +#define GPIO_FUNC6_OEN_SEL_S 10 + +/* GPIO_FUNC6_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC6_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC6_OUT_INV_SEL_S 9 + +/* GPIO_FUNC6_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC6_OUT_SEL 0x000001FF +#define GPIO_FUNC6_OUT_SEL_M (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S) +#define GPIO_FUNC6_OUT_SEL_V 0x000001FF +#define GPIO_FUNC6_OUT_SEL_S 0 + +/* GPIO_FUNC7_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 7 + */ + +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) + +/* GPIO_FUNC7_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC7_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC7_OEN_INV_SEL_M (GPIO_FUNC7_OEN_INV_SEL_V << GPIO_FUNC7_OEN_INV_SEL_S) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC7_OEN_INV_SEL_S 11 + +/* GPIO_FUNC7_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC7_OEN_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_SEL_M (GPIO_FUNC7_OEN_SEL_V << GPIO_FUNC7_OEN_SEL_S) +#define GPIO_FUNC7_OEN_SEL_V 0x00000001 +#define GPIO_FUNC7_OEN_SEL_S 10 + +/* GPIO_FUNC7_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC7_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC7_OUT_INV_SEL_S 9 + +/* GPIO_FUNC7_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC7_OUT_SEL 0x000001FF +#define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S) +#define GPIO_FUNC7_OUT_SEL_V 0x000001FF +#define GPIO_FUNC7_OUT_SEL_S 0 + +/* GPIO_FUNC8_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 8 + */ + +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) + +/* GPIO_FUNC8_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC8_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC8_OEN_INV_SEL_M (GPIO_FUNC8_OEN_INV_SEL_V << GPIO_FUNC8_OEN_INV_SEL_S) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC8_OEN_INV_SEL_S 11 + +/* GPIO_FUNC8_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC8_OEN_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_SEL_M (GPIO_FUNC8_OEN_SEL_V << GPIO_FUNC8_OEN_SEL_S) +#define GPIO_FUNC8_OEN_SEL_V 0x00000001 +#define GPIO_FUNC8_OEN_SEL_S 10 + +/* GPIO_FUNC8_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC8_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC8_OUT_INV_SEL_S 9 + +/* GPIO_FUNC8_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC8_OUT_SEL 0x000001FF +#define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S) +#define GPIO_FUNC8_OUT_SEL_V 0x000001FF +#define GPIO_FUNC8_OUT_SEL_S 0 + +/* GPIO_FUNC9_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 9 + */ + +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) + +/* GPIO_FUNC9_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC9_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC9_OEN_INV_SEL_M (GPIO_FUNC9_OEN_INV_SEL_V << GPIO_FUNC9_OEN_INV_SEL_S) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC9_OEN_INV_SEL_S 11 + +/* GPIO_FUNC9_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC9_OEN_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_SEL_M (GPIO_FUNC9_OEN_SEL_V << GPIO_FUNC9_OEN_SEL_S) +#define GPIO_FUNC9_OEN_SEL_V 0x00000001 +#define GPIO_FUNC9_OEN_SEL_S 10 + +/* GPIO_FUNC9_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC9_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC9_OUT_INV_SEL_S 9 + +/* GPIO_FUNC9_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC9_OUT_SEL 0x000001FF +#define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S) +#define GPIO_FUNC9_OUT_SEL_V 0x000001FF +#define GPIO_FUNC9_OUT_SEL_S 0 + +/* GPIO_FUNC10_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 10 + */ + +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c) + +/* GPIO_FUNC10_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC10_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC10_OEN_INV_SEL_M (GPIO_FUNC10_OEN_INV_SEL_V << GPIO_FUNC10_OEN_INV_SEL_S) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC10_OEN_INV_SEL_S 11 + +/* GPIO_FUNC10_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC10_OEN_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_SEL_M (GPIO_FUNC10_OEN_SEL_V << GPIO_FUNC10_OEN_SEL_S) +#define GPIO_FUNC10_OEN_SEL_V 0x00000001 +#define GPIO_FUNC10_OEN_SEL_S 10 + +/* GPIO_FUNC10_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC10_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC10_OUT_INV_SEL_S 9 + +/* GPIO_FUNC10_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC10_OUT_SEL 0x000001FF +#define GPIO_FUNC10_OUT_SEL_M (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S) +#define GPIO_FUNC10_OUT_SEL_V 0x000001FF +#define GPIO_FUNC10_OUT_SEL_S 0 + +/* GPIO_FUNC11_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 11 + */ + +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) + +/* GPIO_FUNC11_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC11_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC11_OEN_INV_SEL_M (GPIO_FUNC11_OEN_INV_SEL_V << GPIO_FUNC11_OEN_INV_SEL_S) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC11_OEN_INV_SEL_S 11 + +/* GPIO_FUNC11_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC11_OEN_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_SEL_M (GPIO_FUNC11_OEN_SEL_V << GPIO_FUNC11_OEN_SEL_S) +#define GPIO_FUNC11_OEN_SEL_V 0x00000001 +#define GPIO_FUNC11_OEN_SEL_S 10 + +/* GPIO_FUNC11_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC11_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC11_OUT_INV_SEL_S 9 + +/* GPIO_FUNC11_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC11_OUT_SEL 0x000001FF +#define GPIO_FUNC11_OUT_SEL_M (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S) +#define GPIO_FUNC11_OUT_SEL_V 0x000001FF +#define GPIO_FUNC11_OUT_SEL_S 0 + +/* GPIO_FUNC12_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 12 + */ + +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) + +/* GPIO_FUNC12_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC12_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC12_OEN_INV_SEL_M (GPIO_FUNC12_OEN_INV_SEL_V << GPIO_FUNC12_OEN_INV_SEL_S) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC12_OEN_INV_SEL_S 11 + +/* GPIO_FUNC12_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC12_OEN_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_SEL_M (GPIO_FUNC12_OEN_SEL_V << GPIO_FUNC12_OEN_SEL_S) +#define GPIO_FUNC12_OEN_SEL_V 0x00000001 +#define GPIO_FUNC12_OEN_SEL_S 10 + +/* GPIO_FUNC12_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC12_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC12_OUT_INV_SEL_S 9 + +/* GPIO_FUNC12_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC12_OUT_SEL 0x000001FF +#define GPIO_FUNC12_OUT_SEL_M (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S) +#define GPIO_FUNC12_OUT_SEL_V 0x000001FF +#define GPIO_FUNC12_OUT_SEL_S 0 + +/* GPIO_FUNC13_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 13 + */ + +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) + +/* GPIO_FUNC13_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC13_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC13_OEN_INV_SEL_M (GPIO_FUNC13_OEN_INV_SEL_V << GPIO_FUNC13_OEN_INV_SEL_S) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC13_OEN_INV_SEL_S 11 + +/* GPIO_FUNC13_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC13_OEN_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_SEL_M (GPIO_FUNC13_OEN_SEL_V << GPIO_FUNC13_OEN_SEL_S) +#define GPIO_FUNC13_OEN_SEL_V 0x00000001 +#define GPIO_FUNC13_OEN_SEL_S 10 + +/* GPIO_FUNC13_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC13_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC13_OUT_INV_SEL_S 9 + +/* GPIO_FUNC13_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC13_OUT_SEL 0x000001FF +#define GPIO_FUNC13_OUT_SEL_M (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S) +#define GPIO_FUNC13_OUT_SEL_V 0x000001FF +#define GPIO_FUNC13_OUT_SEL_S 0 + +/* GPIO_FUNC14_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 14 + */ + +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c) + +/* GPIO_FUNC14_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC14_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC14_OEN_INV_SEL_M (GPIO_FUNC14_OEN_INV_SEL_V << GPIO_FUNC14_OEN_INV_SEL_S) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC14_OEN_INV_SEL_S 11 + +/* GPIO_FUNC14_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC14_OEN_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_SEL_M (GPIO_FUNC14_OEN_SEL_V << GPIO_FUNC14_OEN_SEL_S) +#define GPIO_FUNC14_OEN_SEL_V 0x00000001 +#define GPIO_FUNC14_OEN_SEL_S 10 + +/* GPIO_FUNC14_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC14_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC14_OUT_INV_SEL_S 9 + +/* GPIO_FUNC14_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC14_OUT_SEL 0x000001FF +#define GPIO_FUNC14_OUT_SEL_M (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S) +#define GPIO_FUNC14_OUT_SEL_V 0x000001FF +#define GPIO_FUNC14_OUT_SEL_S 0 + +/* GPIO_FUNC15_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 15 + */ + +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) + +/* GPIO_FUNC15_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC15_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC15_OEN_INV_SEL_M (GPIO_FUNC15_OEN_INV_SEL_V << GPIO_FUNC15_OEN_INV_SEL_S) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC15_OEN_INV_SEL_S 11 + +/* GPIO_FUNC15_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC15_OEN_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_SEL_M (GPIO_FUNC15_OEN_SEL_V << GPIO_FUNC15_OEN_SEL_S) +#define GPIO_FUNC15_OEN_SEL_V 0x00000001 +#define GPIO_FUNC15_OEN_SEL_S 10 + +/* GPIO_FUNC15_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC15_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC15_OUT_INV_SEL_S 9 + +/* GPIO_FUNC15_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC15_OUT_SEL 0x000001FF +#define GPIO_FUNC15_OUT_SEL_M (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S) +#define GPIO_FUNC15_OUT_SEL_V 0x000001FF +#define GPIO_FUNC15_OUT_SEL_S 0 + +/* GPIO_FUNC16_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 16 + */ + +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) + +/* GPIO_FUNC16_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC16_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC16_OEN_INV_SEL_M (GPIO_FUNC16_OEN_INV_SEL_V << GPIO_FUNC16_OEN_INV_SEL_S) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC16_OEN_INV_SEL_S 11 + +/* GPIO_FUNC16_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC16_OEN_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_SEL_M (GPIO_FUNC16_OEN_SEL_V << GPIO_FUNC16_OEN_SEL_S) +#define GPIO_FUNC16_OEN_SEL_V 0x00000001 +#define GPIO_FUNC16_OEN_SEL_S 10 + +/* GPIO_FUNC16_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC16_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC16_OUT_INV_SEL_S 9 + +/* GPIO_FUNC16_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC16_OUT_SEL 0x000001FF +#define GPIO_FUNC16_OUT_SEL_M (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S) +#define GPIO_FUNC16_OUT_SEL_V 0x000001FF +#define GPIO_FUNC16_OUT_SEL_S 0 + +/* GPIO_FUNC17_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 17 + */ + +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) + +/* GPIO_FUNC17_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC17_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC17_OEN_INV_SEL_M (GPIO_FUNC17_OEN_INV_SEL_V << GPIO_FUNC17_OEN_INV_SEL_S) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC17_OEN_INV_SEL_S 11 + +/* GPIO_FUNC17_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC17_OEN_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_SEL_M (GPIO_FUNC17_OEN_SEL_V << GPIO_FUNC17_OEN_SEL_S) +#define GPIO_FUNC17_OEN_SEL_V 0x00000001 +#define GPIO_FUNC17_OEN_SEL_S 10 + +/* GPIO_FUNC17_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC17_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC17_OUT_INV_SEL_S 9 + +/* GPIO_FUNC17_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC17_OUT_SEL 0x000001FF +#define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S) +#define GPIO_FUNC17_OUT_SEL_V 0x000001FF +#define GPIO_FUNC17_OUT_SEL_S 0 + +/* GPIO_FUNC18_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 18 + */ + +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c) + +/* GPIO_FUNC18_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC18_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC18_OEN_INV_SEL_M (GPIO_FUNC18_OEN_INV_SEL_V << GPIO_FUNC18_OEN_INV_SEL_S) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC18_OEN_INV_SEL_S 11 + +/* GPIO_FUNC18_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC18_OEN_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_SEL_M (GPIO_FUNC18_OEN_SEL_V << GPIO_FUNC18_OEN_SEL_S) +#define GPIO_FUNC18_OEN_SEL_V 0x00000001 +#define GPIO_FUNC18_OEN_SEL_S 10 + +/* GPIO_FUNC18_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC18_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC18_OUT_INV_SEL_S 9 + +/* GPIO_FUNC18_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC18_OUT_SEL 0x000001FF +#define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S) +#define GPIO_FUNC18_OUT_SEL_V 0x000001FF +#define GPIO_FUNC18_OUT_SEL_S 0 + +/* GPIO_FUNC19_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 19 + */ + +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0) + +/* GPIO_FUNC19_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC19_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC19_OEN_INV_SEL_M (GPIO_FUNC19_OEN_INV_SEL_V << GPIO_FUNC19_OEN_INV_SEL_S) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC19_OEN_INV_SEL_S 11 + +/* GPIO_FUNC19_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC19_OEN_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_SEL_M (GPIO_FUNC19_OEN_SEL_V << GPIO_FUNC19_OEN_SEL_S) +#define GPIO_FUNC19_OEN_SEL_V 0x00000001 +#define GPIO_FUNC19_OEN_SEL_S 10 + +/* GPIO_FUNC19_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC19_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC19_OUT_INV_SEL_S 9 + +/* GPIO_FUNC19_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC19_OUT_SEL 0x000001FF +#define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S) +#define GPIO_FUNC19_OUT_SEL_V 0x000001FF +#define GPIO_FUNC19_OUT_SEL_S 0 + +/* GPIO_FUNC20_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 20 + */ + +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4) + +/* GPIO_FUNC20_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC20_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC20_OEN_INV_SEL_M (GPIO_FUNC20_OEN_INV_SEL_V << GPIO_FUNC20_OEN_INV_SEL_S) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC20_OEN_INV_SEL_S 11 + +/* GPIO_FUNC20_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC20_OEN_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_SEL_M (GPIO_FUNC20_OEN_SEL_V << GPIO_FUNC20_OEN_SEL_S) +#define GPIO_FUNC20_OEN_SEL_V 0x00000001 +#define GPIO_FUNC20_OEN_SEL_S 10 + +/* GPIO_FUNC20_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC20_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC20_OUT_INV_SEL_S 9 + +/* GPIO_FUNC20_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC20_OUT_SEL 0x000001FF +#define GPIO_FUNC20_OUT_SEL_M (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S) +#define GPIO_FUNC20_OUT_SEL_V 0x000001FF +#define GPIO_FUNC20_OUT_SEL_S 0 + +/* GPIO_FUNC21_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 21 + */ + +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8) + +/* GPIO_FUNC21_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC21_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC21_OEN_INV_SEL_M (GPIO_FUNC21_OEN_INV_SEL_V << GPIO_FUNC21_OEN_INV_SEL_S) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC21_OEN_INV_SEL_S 11 + +/* GPIO_FUNC21_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC21_OEN_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_SEL_M (GPIO_FUNC21_OEN_SEL_V << GPIO_FUNC21_OEN_SEL_S) +#define GPIO_FUNC21_OEN_SEL_V 0x00000001 +#define GPIO_FUNC21_OEN_SEL_S 10 + +/* GPIO_FUNC21_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC21_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC21_OUT_INV_SEL_S 9 + +/* GPIO_FUNC21_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC21_OUT_SEL 0x000001FF +#define GPIO_FUNC21_OUT_SEL_M (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S) +#define GPIO_FUNC21_OUT_SEL_V 0x000001FF +#define GPIO_FUNC21_OUT_SEL_S 0 + +/* GPIO_FUNC22_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 22 + */ + +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac) + +/* GPIO_FUNC22_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC22_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC22_OEN_INV_SEL_M (GPIO_FUNC22_OEN_INV_SEL_V << GPIO_FUNC22_OEN_INV_SEL_S) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC22_OEN_INV_SEL_S 11 + +/* GPIO_FUNC22_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC22_OEN_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_SEL_M (GPIO_FUNC22_OEN_SEL_V << GPIO_FUNC22_OEN_SEL_S) +#define GPIO_FUNC22_OEN_SEL_V 0x00000001 +#define GPIO_FUNC22_OEN_SEL_S 10 + +/* GPIO_FUNC22_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC22_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC22_OUT_INV_SEL_S 9 + +/* GPIO_FUNC22_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC22_OUT_SEL 0x000001FF +#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S) +#define GPIO_FUNC22_OUT_SEL_V 0x000001FF +#define GPIO_FUNC22_OUT_SEL_S 0 + +/* GPIO_FUNC23_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 23 + */ + +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0) + +/* GPIO_FUNC23_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC23_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC23_OEN_INV_SEL_M (GPIO_FUNC23_OEN_INV_SEL_V << GPIO_FUNC23_OEN_INV_SEL_S) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC23_OEN_INV_SEL_S 11 + +/* GPIO_FUNC23_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC23_OEN_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_SEL_M (GPIO_FUNC23_OEN_SEL_V << GPIO_FUNC23_OEN_SEL_S) +#define GPIO_FUNC23_OEN_SEL_V 0x00000001 +#define GPIO_FUNC23_OEN_SEL_S 10 + +/* GPIO_FUNC23_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC23_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC23_OUT_INV_SEL_S 9 + +/* GPIO_FUNC23_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC23_OUT_SEL 0x000001FF +#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S) +#define GPIO_FUNC23_OUT_SEL_V 0x000001FF +#define GPIO_FUNC23_OUT_SEL_S 0 + +/* GPIO_FUNC24_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 24 + */ + +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4) + +/* GPIO_FUNC24_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC24_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC24_OEN_INV_SEL_M (GPIO_FUNC24_OEN_INV_SEL_V << GPIO_FUNC24_OEN_INV_SEL_S) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC24_OEN_INV_SEL_S 11 + +/* GPIO_FUNC24_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC24_OEN_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_SEL_M (GPIO_FUNC24_OEN_SEL_V << GPIO_FUNC24_OEN_SEL_S) +#define GPIO_FUNC24_OEN_SEL_V 0x00000001 +#define GPIO_FUNC24_OEN_SEL_S 10 + +/* GPIO_FUNC24_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC24_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC24_OUT_INV_SEL_S 9 + +/* GPIO_FUNC24_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC24_OUT_SEL 0x000001FF +#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S) +#define GPIO_FUNC24_OUT_SEL_V 0x000001FF +#define GPIO_FUNC24_OUT_SEL_S 0 + +/* GPIO_FUNC25_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 25 + */ + +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8) + +/* GPIO_FUNC25_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC25_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC25_OEN_INV_SEL_M (GPIO_FUNC25_OEN_INV_SEL_V << GPIO_FUNC25_OEN_INV_SEL_S) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC25_OEN_INV_SEL_S 11 + +/* GPIO_FUNC25_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC25_OEN_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_SEL_M (GPIO_FUNC25_OEN_SEL_V << GPIO_FUNC25_OEN_SEL_S) +#define GPIO_FUNC25_OEN_SEL_V 0x00000001 +#define GPIO_FUNC25_OEN_SEL_S 10 + +/* GPIO_FUNC25_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC25_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC25_OUT_INV_SEL_S 9 + +/* GPIO_FUNC25_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC25_OUT_SEL 0x000001FF +#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S) +#define GPIO_FUNC25_OUT_SEL_V 0x000001FF +#define GPIO_FUNC25_OUT_SEL_S 0 + +/* GPIO_FUNC26_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 26 + */ + +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5bc) + +/* GPIO_FUNC26_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC26_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC26_OEN_INV_SEL_M (GPIO_FUNC26_OEN_INV_SEL_V << GPIO_FUNC26_OEN_INV_SEL_S) +#define GPIO_FUNC26_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC26_OEN_INV_SEL_S 11 + +/* GPIO_FUNC26_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC26_OEN_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_SEL_M (GPIO_FUNC26_OEN_SEL_V << GPIO_FUNC26_OEN_SEL_S) +#define GPIO_FUNC26_OEN_SEL_V 0x00000001 +#define GPIO_FUNC26_OEN_SEL_S 10 + +/* GPIO_FUNC26_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC26_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC26_OUT_INV_SEL_S 9 + +/* GPIO_FUNC26_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC26_OUT_SEL 0x000001FF +#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S) +#define GPIO_FUNC26_OUT_SEL_V 0x000001FF +#define GPIO_FUNC26_OUT_SEL_S 0 + +/* GPIO_FUNC27_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 27 + */ + +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c0) + +/* GPIO_FUNC27_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC27_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC27_OEN_INV_SEL_M (GPIO_FUNC27_OEN_INV_SEL_V << GPIO_FUNC27_OEN_INV_SEL_S) +#define GPIO_FUNC27_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC27_OEN_INV_SEL_S 11 + +/* GPIO_FUNC27_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC27_OEN_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_SEL_M (GPIO_FUNC27_OEN_SEL_V << GPIO_FUNC27_OEN_SEL_S) +#define GPIO_FUNC27_OEN_SEL_V 0x00000001 +#define GPIO_FUNC27_OEN_SEL_S 10 + +/* GPIO_FUNC27_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC27_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC27_OUT_INV_SEL_S 9 + +/* GPIO_FUNC27_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC27_OUT_SEL 0x000001FF +#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S) +#define GPIO_FUNC27_OUT_SEL_V 0x000001FF +#define GPIO_FUNC27_OUT_SEL_S 0 + +/* GPIO_FUNC28_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 28 + */ + +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c4) + +/* GPIO_FUNC28_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC28_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC28_OEN_INV_SEL_M (GPIO_FUNC28_OEN_INV_SEL_V << GPIO_FUNC28_OEN_INV_SEL_S) +#define GPIO_FUNC28_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC28_OEN_INV_SEL_S 11 + +/* GPIO_FUNC28_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC28_OEN_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_SEL_M (GPIO_FUNC28_OEN_SEL_V << GPIO_FUNC28_OEN_SEL_S) +#define GPIO_FUNC28_OEN_SEL_V 0x00000001 +#define GPIO_FUNC28_OEN_SEL_S 10 + +/* GPIO_FUNC28_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC28_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC28_OUT_INV_SEL_S 9 + +/* GPIO_FUNC28_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC28_OUT_SEL 0x000001FF +#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S) +#define GPIO_FUNC28_OUT_SEL_V 0x000001FF +#define GPIO_FUNC28_OUT_SEL_S 0 + +/* GPIO_FUNC29_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 29 + */ + +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5c8) + +/* GPIO_FUNC29_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC29_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC29_OEN_INV_SEL_M (GPIO_FUNC29_OEN_INV_SEL_V << GPIO_FUNC29_OEN_INV_SEL_S) +#define GPIO_FUNC29_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC29_OEN_INV_SEL_S 11 + +/* GPIO_FUNC29_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC29_OEN_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_SEL_M (GPIO_FUNC29_OEN_SEL_V << GPIO_FUNC29_OEN_SEL_S) +#define GPIO_FUNC29_OEN_SEL_V 0x00000001 +#define GPIO_FUNC29_OEN_SEL_S 10 + +/* GPIO_FUNC29_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC29_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC29_OUT_INV_SEL_M (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC29_OUT_INV_SEL_S 9 + +/* GPIO_FUNC29_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC29_OUT_SEL 0x000001FF +#define GPIO_FUNC29_OUT_SEL_M (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S) +#define GPIO_FUNC29_OUT_SEL_V 0x000001FF +#define GPIO_FUNC29_OUT_SEL_S 0 + +/* GPIO_FUNC30_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 30 + */ + +#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5cc) + +/* GPIO_FUNC30_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC30_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC30_OEN_INV_SEL_M (GPIO_FUNC30_OEN_INV_SEL_V << GPIO_FUNC30_OEN_INV_SEL_S) +#define GPIO_FUNC30_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC30_OEN_INV_SEL_S 11 + +/* GPIO_FUNC30_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC30_OEN_SEL (BIT(10)) +#define GPIO_FUNC30_OEN_SEL_M (GPIO_FUNC30_OEN_SEL_V << GPIO_FUNC30_OEN_SEL_S) +#define GPIO_FUNC30_OEN_SEL_V 0x00000001 +#define GPIO_FUNC30_OEN_SEL_S 10 + +/* GPIO_FUNC30_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC30_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC30_OUT_INV_SEL_M (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S) +#define GPIO_FUNC30_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC30_OUT_INV_SEL_S 9 + +/* GPIO_FUNC30_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC30_OUT_SEL 0x000001FF +#define GPIO_FUNC30_OUT_SEL_M (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S) +#define GPIO_FUNC30_OUT_SEL_V 0x000001FF +#define GPIO_FUNC30_OUT_SEL_S 0 + +/* GPIO_FUNC31_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 31 + */ + +#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d0) + +/* GPIO_FUNC31_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC31_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC31_OEN_INV_SEL_M (GPIO_FUNC31_OEN_INV_SEL_V << GPIO_FUNC31_OEN_INV_SEL_S) +#define GPIO_FUNC31_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC31_OEN_INV_SEL_S 11 + +/* GPIO_FUNC31_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC31_OEN_SEL (BIT(10)) +#define GPIO_FUNC31_OEN_SEL_M (GPIO_FUNC31_OEN_SEL_V << GPIO_FUNC31_OEN_SEL_S) +#define GPIO_FUNC31_OEN_SEL_V 0x00000001 +#define GPIO_FUNC31_OEN_SEL_S 10 + +/* GPIO_FUNC31_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC31_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC31_OUT_INV_SEL_M (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S) +#define GPIO_FUNC31_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC31_OUT_INV_SEL_S 9 + +/* GPIO_FUNC31_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC31_OUT_SEL 0x000001FF +#define GPIO_FUNC31_OUT_SEL_M (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S) +#define GPIO_FUNC31_OUT_SEL_V 0x000001FF +#define GPIO_FUNC31_OUT_SEL_S 0 + +/* GPIO_FUNC32_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 32 + */ + +#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d4) + +/* GPIO_FUNC32_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC32_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC32_OEN_INV_SEL_M (GPIO_FUNC32_OEN_INV_SEL_V << GPIO_FUNC32_OEN_INV_SEL_S) +#define GPIO_FUNC32_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC32_OEN_INV_SEL_S 11 + +/* GPIO_FUNC32_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC32_OEN_SEL (BIT(10)) +#define GPIO_FUNC32_OEN_SEL_M (GPIO_FUNC32_OEN_SEL_V << GPIO_FUNC32_OEN_SEL_S) +#define GPIO_FUNC32_OEN_SEL_V 0x00000001 +#define GPIO_FUNC32_OEN_SEL_S 10 + +/* GPIO_FUNC32_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC32_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC32_OUT_INV_SEL_M (GPIO_FUNC32_OUT_INV_SEL_V << GPIO_FUNC32_OUT_INV_SEL_S) +#define GPIO_FUNC32_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC32_OUT_INV_SEL_S 9 + +/* GPIO_FUNC32_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC32_OUT_SEL 0x000001FF +#define GPIO_FUNC32_OUT_SEL_M (GPIO_FUNC32_OUT_SEL_V << GPIO_FUNC32_OUT_SEL_S) +#define GPIO_FUNC32_OUT_SEL_V 0x000001FF +#define GPIO_FUNC32_OUT_SEL_S 0 + +/* GPIO_FUNC33_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 33 + */ + +#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5d8) + +/* GPIO_FUNC33_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC33_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC33_OEN_INV_SEL_M (GPIO_FUNC33_OEN_INV_SEL_V << GPIO_FUNC33_OEN_INV_SEL_S) +#define GPIO_FUNC33_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC33_OEN_INV_SEL_S 11 + +/* GPIO_FUNC33_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC33_OEN_SEL (BIT(10)) +#define GPIO_FUNC33_OEN_SEL_M (GPIO_FUNC33_OEN_SEL_V << GPIO_FUNC33_OEN_SEL_S) +#define GPIO_FUNC33_OEN_SEL_V 0x00000001 +#define GPIO_FUNC33_OEN_SEL_S 10 + +/* GPIO_FUNC33_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC33_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC33_OUT_INV_SEL_M (GPIO_FUNC33_OUT_INV_SEL_V << GPIO_FUNC33_OUT_INV_SEL_S) +#define GPIO_FUNC33_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC33_OUT_INV_SEL_S 9 + +/* GPIO_FUNC33_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC33_OUT_SEL 0x000001FF +#define GPIO_FUNC33_OUT_SEL_M (GPIO_FUNC33_OUT_SEL_V << GPIO_FUNC33_OUT_SEL_S) +#define GPIO_FUNC33_OUT_SEL_V 0x000001FF +#define GPIO_FUNC33_OUT_SEL_S 0 + +/* GPIO_FUNC34_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 34 + */ + +#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5dc) + +/* GPIO_FUNC34_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC34_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC34_OEN_INV_SEL_M (GPIO_FUNC34_OEN_INV_SEL_V << GPIO_FUNC34_OEN_INV_SEL_S) +#define GPIO_FUNC34_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC34_OEN_INV_SEL_S 11 + +/* GPIO_FUNC34_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC34_OEN_SEL (BIT(10)) +#define GPIO_FUNC34_OEN_SEL_M (GPIO_FUNC34_OEN_SEL_V << GPIO_FUNC34_OEN_SEL_S) +#define GPIO_FUNC34_OEN_SEL_V 0x00000001 +#define GPIO_FUNC34_OEN_SEL_S 10 + +/* GPIO_FUNC34_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC34_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC34_OUT_INV_SEL_M (GPIO_FUNC34_OUT_INV_SEL_V << GPIO_FUNC34_OUT_INV_SEL_S) +#define GPIO_FUNC34_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC34_OUT_INV_SEL_S 9 + +/* GPIO_FUNC34_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC34_OUT_SEL 0x000001FF +#define GPIO_FUNC34_OUT_SEL_M (GPIO_FUNC34_OUT_SEL_V << GPIO_FUNC34_OUT_SEL_S) +#define GPIO_FUNC34_OUT_SEL_V 0x000001FF +#define GPIO_FUNC34_OUT_SEL_S 0 + +/* GPIO_FUNC35_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 35 + */ + +#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e0) + +/* GPIO_FUNC35_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC35_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC35_OEN_INV_SEL_M (GPIO_FUNC35_OEN_INV_SEL_V << GPIO_FUNC35_OEN_INV_SEL_S) +#define GPIO_FUNC35_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC35_OEN_INV_SEL_S 11 + +/* GPIO_FUNC35_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC35_OEN_SEL (BIT(10)) +#define GPIO_FUNC35_OEN_SEL_M (GPIO_FUNC35_OEN_SEL_V << GPIO_FUNC35_OEN_SEL_S) +#define GPIO_FUNC35_OEN_SEL_V 0x00000001 +#define GPIO_FUNC35_OEN_SEL_S 10 + +/* GPIO_FUNC35_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC35_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC35_OUT_INV_SEL_M (GPIO_FUNC35_OUT_INV_SEL_V << GPIO_FUNC35_OUT_INV_SEL_S) +#define GPIO_FUNC35_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC35_OUT_INV_SEL_S 9 + +/* GPIO_FUNC35_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC35_OUT_SEL 0x000001FF +#define GPIO_FUNC35_OUT_SEL_M (GPIO_FUNC35_OUT_SEL_V << GPIO_FUNC35_OUT_SEL_S) +#define GPIO_FUNC35_OUT_SEL_V 0x000001FF +#define GPIO_FUNC35_OUT_SEL_S 0 + +/* GPIO_FUNC36_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 36 + */ + +#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e4) + +/* GPIO_FUNC36_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC36_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC36_OEN_INV_SEL_M (GPIO_FUNC36_OEN_INV_SEL_V << GPIO_FUNC36_OEN_INV_SEL_S) +#define GPIO_FUNC36_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC36_OEN_INV_SEL_S 11 + +/* GPIO_FUNC36_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC36_OEN_SEL (BIT(10)) +#define GPIO_FUNC36_OEN_SEL_M (GPIO_FUNC36_OEN_SEL_V << GPIO_FUNC36_OEN_SEL_S) +#define GPIO_FUNC36_OEN_SEL_V 0x00000001 +#define GPIO_FUNC36_OEN_SEL_S 10 + +/* GPIO_FUNC36_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC36_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC36_OUT_INV_SEL_M (GPIO_FUNC36_OUT_INV_SEL_V << GPIO_FUNC36_OUT_INV_SEL_S) +#define GPIO_FUNC36_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC36_OUT_INV_SEL_S 9 + +/* GPIO_FUNC36_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC36_OUT_SEL 0x000001FF +#define GPIO_FUNC36_OUT_SEL_M (GPIO_FUNC36_OUT_SEL_V << GPIO_FUNC36_OUT_SEL_S) +#define GPIO_FUNC36_OUT_SEL_V 0x000001FF +#define GPIO_FUNC36_OUT_SEL_S 0 + +/* GPIO_FUNC37_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 37 + */ + +#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5e8) + +/* GPIO_FUNC37_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC37_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC37_OEN_INV_SEL_M (GPIO_FUNC37_OEN_INV_SEL_V << GPIO_FUNC37_OEN_INV_SEL_S) +#define GPIO_FUNC37_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC37_OEN_INV_SEL_S 11 + +/* GPIO_FUNC37_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC37_OEN_SEL (BIT(10)) +#define GPIO_FUNC37_OEN_SEL_M (GPIO_FUNC37_OEN_SEL_V << GPIO_FUNC37_OEN_SEL_S) +#define GPIO_FUNC37_OEN_SEL_V 0x00000001 +#define GPIO_FUNC37_OEN_SEL_S 10 + +/* GPIO_FUNC37_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC37_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC37_OUT_INV_SEL_M (GPIO_FUNC37_OUT_INV_SEL_V << GPIO_FUNC37_OUT_INV_SEL_S) +#define GPIO_FUNC37_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC37_OUT_INV_SEL_S 9 + +/* GPIO_FUNC37_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC37_OUT_SEL 0x000001FF +#define GPIO_FUNC37_OUT_SEL_M (GPIO_FUNC37_OUT_SEL_V << GPIO_FUNC37_OUT_SEL_S) +#define GPIO_FUNC37_OUT_SEL_V 0x000001FF +#define GPIO_FUNC37_OUT_SEL_S 0 + +/* GPIO_FUNC38_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 38 + */ + +#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ec) + +/* GPIO_FUNC38_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC38_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC38_OEN_INV_SEL_M (GPIO_FUNC38_OEN_INV_SEL_V << GPIO_FUNC38_OEN_INV_SEL_S) +#define GPIO_FUNC38_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC38_OEN_INV_SEL_S 11 + +/* GPIO_FUNC38_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC38_OEN_SEL (BIT(10)) +#define GPIO_FUNC38_OEN_SEL_M (GPIO_FUNC38_OEN_SEL_V << GPIO_FUNC38_OEN_SEL_S) +#define GPIO_FUNC38_OEN_SEL_V 0x00000001 +#define GPIO_FUNC38_OEN_SEL_S 10 + +/* GPIO_FUNC38_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC38_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC38_OUT_INV_SEL_M (GPIO_FUNC38_OUT_INV_SEL_V << GPIO_FUNC38_OUT_INV_SEL_S) +#define GPIO_FUNC38_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC38_OUT_INV_SEL_S 9 + +/* GPIO_FUNC38_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC38_OUT_SEL 0x000001FF +#define GPIO_FUNC38_OUT_SEL_M (GPIO_FUNC38_OUT_SEL_V << GPIO_FUNC38_OUT_SEL_S) +#define GPIO_FUNC38_OUT_SEL_V 0x000001FF +#define GPIO_FUNC38_OUT_SEL_S 0 + +/* GPIO_FUNC39_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 39 + */ + +#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f0) + +/* GPIO_FUNC39_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC39_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC39_OEN_INV_SEL_M (GPIO_FUNC39_OEN_INV_SEL_V << GPIO_FUNC39_OEN_INV_SEL_S) +#define GPIO_FUNC39_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC39_OEN_INV_SEL_S 11 + +/* GPIO_FUNC39_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC39_OEN_SEL (BIT(10)) +#define GPIO_FUNC39_OEN_SEL_M (GPIO_FUNC39_OEN_SEL_V << GPIO_FUNC39_OEN_SEL_S) +#define GPIO_FUNC39_OEN_SEL_V 0x00000001 +#define GPIO_FUNC39_OEN_SEL_S 10 + +/* GPIO_FUNC39_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC39_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC39_OUT_INV_SEL_M (GPIO_FUNC39_OUT_INV_SEL_V << GPIO_FUNC39_OUT_INV_SEL_S) +#define GPIO_FUNC39_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC39_OUT_INV_SEL_S 9 + +/* GPIO_FUNC39_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC39_OUT_SEL 0x000001FF +#define GPIO_FUNC39_OUT_SEL_M (GPIO_FUNC39_OUT_SEL_V << GPIO_FUNC39_OUT_SEL_S) +#define GPIO_FUNC39_OUT_SEL_V 0x000001FF +#define GPIO_FUNC39_OUT_SEL_S 0 + +/* GPIO_FUNC40_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 40 + */ + +#define GPIO_FUNC40_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f4) + +/* GPIO_FUNC40_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC40_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC40_OEN_INV_SEL_M (GPIO_FUNC40_OEN_INV_SEL_V << GPIO_FUNC40_OEN_INV_SEL_S) +#define GPIO_FUNC40_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC40_OEN_INV_SEL_S 11 + +/* GPIO_FUNC40_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC40_OEN_SEL (BIT(10)) +#define GPIO_FUNC40_OEN_SEL_M (GPIO_FUNC40_OEN_SEL_V << GPIO_FUNC40_OEN_SEL_S) +#define GPIO_FUNC40_OEN_SEL_V 0x00000001 +#define GPIO_FUNC40_OEN_SEL_S 10 + +/* GPIO_FUNC40_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC40_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC40_OUT_INV_SEL_M (GPIO_FUNC40_OUT_INV_SEL_V << GPIO_FUNC40_OUT_INV_SEL_S) +#define GPIO_FUNC40_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC40_OUT_INV_SEL_S 9 + +/* GPIO_FUNC40_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC40_OUT_SEL 0x000001FF +#define GPIO_FUNC40_OUT_SEL_M (GPIO_FUNC40_OUT_SEL_V << GPIO_FUNC40_OUT_SEL_S) +#define GPIO_FUNC40_OUT_SEL_V 0x000001FF +#define GPIO_FUNC40_OUT_SEL_S 0 + +/* GPIO_FUNC41_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 41 + */ + +#define GPIO_FUNC41_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5f8) + +/* GPIO_FUNC41_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC41_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC41_OEN_INV_SEL_M (GPIO_FUNC41_OEN_INV_SEL_V << GPIO_FUNC41_OEN_INV_SEL_S) +#define GPIO_FUNC41_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC41_OEN_INV_SEL_S 11 + +/* GPIO_FUNC41_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC41_OEN_SEL (BIT(10)) +#define GPIO_FUNC41_OEN_SEL_M (GPIO_FUNC41_OEN_SEL_V << GPIO_FUNC41_OEN_SEL_S) +#define GPIO_FUNC41_OEN_SEL_V 0x00000001 +#define GPIO_FUNC41_OEN_SEL_S 10 + +/* GPIO_FUNC41_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC41_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC41_OUT_INV_SEL_M (GPIO_FUNC41_OUT_INV_SEL_V << GPIO_FUNC41_OUT_INV_SEL_S) +#define GPIO_FUNC41_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC41_OUT_INV_SEL_S 9 + +/* GPIO_FUNC41_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC41_OUT_SEL 0x000001FF +#define GPIO_FUNC41_OUT_SEL_M (GPIO_FUNC41_OUT_SEL_V << GPIO_FUNC41_OUT_SEL_S) +#define GPIO_FUNC41_OUT_SEL_V 0x000001FF +#define GPIO_FUNC41_OUT_SEL_S 0 + +/* GPIO_FUNC42_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 42 + */ + +#define GPIO_FUNC42_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5fc) + +/* GPIO_FUNC42_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC42_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC42_OEN_INV_SEL_M (GPIO_FUNC42_OEN_INV_SEL_V << GPIO_FUNC42_OEN_INV_SEL_S) +#define GPIO_FUNC42_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC42_OEN_INV_SEL_S 11 + +/* GPIO_FUNC42_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC42_OEN_SEL (BIT(10)) +#define GPIO_FUNC42_OEN_SEL_M (GPIO_FUNC42_OEN_SEL_V << GPIO_FUNC42_OEN_SEL_S) +#define GPIO_FUNC42_OEN_SEL_V 0x00000001 +#define GPIO_FUNC42_OEN_SEL_S 10 + +/* GPIO_FUNC42_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC42_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC42_OUT_INV_SEL_M (GPIO_FUNC42_OUT_INV_SEL_V << GPIO_FUNC42_OUT_INV_SEL_S) +#define GPIO_FUNC42_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC42_OUT_INV_SEL_S 9 + +/* GPIO_FUNC42_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC42_OUT_SEL 0x000001FF +#define GPIO_FUNC42_OUT_SEL_M (GPIO_FUNC42_OUT_SEL_V << GPIO_FUNC42_OUT_SEL_S) +#define GPIO_FUNC42_OUT_SEL_V 0x000001FF +#define GPIO_FUNC42_OUT_SEL_S 0 + +/* GPIO_FUNC43_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 43 + */ + +#define GPIO_FUNC43_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x600) + +/* GPIO_FUNC43_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC43_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC43_OEN_INV_SEL_M (GPIO_FUNC43_OEN_INV_SEL_V << GPIO_FUNC43_OEN_INV_SEL_S) +#define GPIO_FUNC43_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC43_OEN_INV_SEL_S 11 + +/* GPIO_FUNC43_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC43_OEN_SEL (BIT(10)) +#define GPIO_FUNC43_OEN_SEL_M (GPIO_FUNC43_OEN_SEL_V << GPIO_FUNC43_OEN_SEL_S) +#define GPIO_FUNC43_OEN_SEL_V 0x00000001 +#define GPIO_FUNC43_OEN_SEL_S 10 + +/* GPIO_FUNC43_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC43_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC43_OUT_INV_SEL_M (GPIO_FUNC43_OUT_INV_SEL_V << GPIO_FUNC43_OUT_INV_SEL_S) +#define GPIO_FUNC43_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC43_OUT_INV_SEL_S 9 + +/* GPIO_FUNC43_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC43_OUT_SEL 0x000001FF +#define GPIO_FUNC43_OUT_SEL_M (GPIO_FUNC43_OUT_SEL_V << GPIO_FUNC43_OUT_SEL_S) +#define GPIO_FUNC43_OUT_SEL_V 0x000001FF +#define GPIO_FUNC43_OUT_SEL_S 0 + +/* GPIO_FUNC44_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 44 + */ + +#define GPIO_FUNC44_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x604) + +/* GPIO_FUNC44_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC44_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC44_OEN_INV_SEL_M (GPIO_FUNC44_OEN_INV_SEL_V << GPIO_FUNC44_OEN_INV_SEL_S) +#define GPIO_FUNC44_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC44_OEN_INV_SEL_S 11 + +/* GPIO_FUNC44_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC44_OEN_SEL (BIT(10)) +#define GPIO_FUNC44_OEN_SEL_M (GPIO_FUNC44_OEN_SEL_V << GPIO_FUNC44_OEN_SEL_S) +#define GPIO_FUNC44_OEN_SEL_V 0x00000001 +#define GPIO_FUNC44_OEN_SEL_S 10 + +/* GPIO_FUNC44_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC44_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC44_OUT_INV_SEL_M (GPIO_FUNC44_OUT_INV_SEL_V << GPIO_FUNC44_OUT_INV_SEL_S) +#define GPIO_FUNC44_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC44_OUT_INV_SEL_S 9 + +/* GPIO_FUNC44_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC44_OUT_SEL 0x000001FF +#define GPIO_FUNC44_OUT_SEL_M (GPIO_FUNC44_OUT_SEL_V << GPIO_FUNC44_OUT_SEL_S) +#define GPIO_FUNC44_OUT_SEL_V 0x000001FF +#define GPIO_FUNC44_OUT_SEL_S 0 + +/* GPIO_FUNC45_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 45 + */ + +#define GPIO_FUNC45_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x608) + +/* GPIO_FUNC45_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC45_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC45_OEN_INV_SEL_M (GPIO_FUNC45_OEN_INV_SEL_V << GPIO_FUNC45_OEN_INV_SEL_S) +#define GPIO_FUNC45_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC45_OEN_INV_SEL_S 11 + +/* GPIO_FUNC45_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC45_OEN_SEL (BIT(10)) +#define GPIO_FUNC45_OEN_SEL_M (GPIO_FUNC45_OEN_SEL_V << GPIO_FUNC45_OEN_SEL_S) +#define GPIO_FUNC45_OEN_SEL_V 0x00000001 +#define GPIO_FUNC45_OEN_SEL_S 10 + +/* GPIO_FUNC45_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC45_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC45_OUT_INV_SEL_M (GPIO_FUNC45_OUT_INV_SEL_V << GPIO_FUNC45_OUT_INV_SEL_S) +#define GPIO_FUNC45_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC45_OUT_INV_SEL_S 9 + +/* GPIO_FUNC45_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC45_OUT_SEL 0x000001FF +#define GPIO_FUNC45_OUT_SEL_M (GPIO_FUNC45_OUT_SEL_V << GPIO_FUNC45_OUT_SEL_S) +#define GPIO_FUNC45_OUT_SEL_V 0x000001FF +#define GPIO_FUNC45_OUT_SEL_S 0 + +/* GPIO_FUNC46_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 46 + */ + +#define GPIO_FUNC46_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x60c) + +/* GPIO_FUNC46_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC46_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC46_OEN_INV_SEL_M (GPIO_FUNC46_OEN_INV_SEL_V << GPIO_FUNC46_OEN_INV_SEL_S) +#define GPIO_FUNC46_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC46_OEN_INV_SEL_S 11 + +/* GPIO_FUNC46_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC46_OEN_SEL (BIT(10)) +#define GPIO_FUNC46_OEN_SEL_M (GPIO_FUNC46_OEN_SEL_V << GPIO_FUNC46_OEN_SEL_S) +#define GPIO_FUNC46_OEN_SEL_V 0x00000001 +#define GPIO_FUNC46_OEN_SEL_S 10 + +/* GPIO_FUNC46_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC46_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC46_OUT_INV_SEL_M (GPIO_FUNC46_OUT_INV_SEL_V << GPIO_FUNC46_OUT_INV_SEL_S) +#define GPIO_FUNC46_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC46_OUT_INV_SEL_S 9 + +/* GPIO_FUNC46_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC46_OUT_SEL 0x000001FF +#define GPIO_FUNC46_OUT_SEL_M (GPIO_FUNC46_OUT_SEL_V << GPIO_FUNC46_OUT_SEL_S) +#define GPIO_FUNC46_OUT_SEL_V 0x000001FF +#define GPIO_FUNC46_OUT_SEL_S 0 + +/* GPIO_FUNC47_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 47 + */ + +#define GPIO_FUNC47_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x610) + +/* GPIO_FUNC47_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC47_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC47_OEN_INV_SEL_M (GPIO_FUNC47_OEN_INV_SEL_V << GPIO_FUNC47_OEN_INV_SEL_S) +#define GPIO_FUNC47_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC47_OEN_INV_SEL_S 11 + +/* GPIO_FUNC47_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC47_OEN_SEL (BIT(10)) +#define GPIO_FUNC47_OEN_SEL_M (GPIO_FUNC47_OEN_SEL_V << GPIO_FUNC47_OEN_SEL_S) +#define GPIO_FUNC47_OEN_SEL_V 0x00000001 +#define GPIO_FUNC47_OEN_SEL_S 10 + +/* GPIO_FUNC47_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC47_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC47_OUT_INV_SEL_M (GPIO_FUNC47_OUT_INV_SEL_V << GPIO_FUNC47_OUT_INV_SEL_S) +#define GPIO_FUNC47_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC47_OUT_INV_SEL_S 9 + +/* GPIO_FUNC47_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC47_OUT_SEL 0x000001FF +#define GPIO_FUNC47_OUT_SEL_M (GPIO_FUNC47_OUT_SEL_V << GPIO_FUNC47_OUT_SEL_S) +#define GPIO_FUNC47_OUT_SEL_V 0x000001FF +#define GPIO_FUNC47_OUT_SEL_S 0 + +/* GPIO_FUNC48_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 48 + */ + +#define GPIO_FUNC48_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x614) + +/* GPIO_FUNC48_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC48_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC48_OEN_INV_SEL_M (GPIO_FUNC48_OEN_INV_SEL_V << GPIO_FUNC48_OEN_INV_SEL_S) +#define GPIO_FUNC48_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC48_OEN_INV_SEL_S 11 + +/* GPIO_FUNC48_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC48_OEN_SEL (BIT(10)) +#define GPIO_FUNC48_OEN_SEL_M (GPIO_FUNC48_OEN_SEL_V << GPIO_FUNC48_OEN_SEL_S) +#define GPIO_FUNC48_OEN_SEL_V 0x00000001 +#define GPIO_FUNC48_OEN_SEL_S 10 + +/* GPIO_FUNC48_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC48_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC48_OUT_INV_SEL_M (GPIO_FUNC48_OUT_INV_SEL_V << GPIO_FUNC48_OUT_INV_SEL_S) +#define GPIO_FUNC48_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC48_OUT_INV_SEL_S 9 + +/* GPIO_FUNC48_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC48_OUT_SEL 0x000001FF +#define GPIO_FUNC48_OUT_SEL_M (GPIO_FUNC48_OUT_SEL_V << GPIO_FUNC48_OUT_SEL_S) +#define GPIO_FUNC48_OUT_SEL_V 0x000001FF +#define GPIO_FUNC48_OUT_SEL_S 0 + +/* GPIO_FUNC49_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 49 + */ + +#define GPIO_FUNC49_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x618) + +/* GPIO_FUNC49_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC49_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC49_OEN_INV_SEL_M (GPIO_FUNC49_OEN_INV_SEL_V << GPIO_FUNC49_OEN_INV_SEL_S) +#define GPIO_FUNC49_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC49_OEN_INV_SEL_S 11 + +/* GPIO_FUNC49_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC49_OEN_SEL (BIT(10)) +#define GPIO_FUNC49_OEN_SEL_M (GPIO_FUNC49_OEN_SEL_V << GPIO_FUNC49_OEN_SEL_S) +#define GPIO_FUNC49_OEN_SEL_V 0x00000001 +#define GPIO_FUNC49_OEN_SEL_S 10 + +/* GPIO_FUNC49_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC49_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC49_OUT_INV_SEL_M (GPIO_FUNC49_OUT_INV_SEL_V << GPIO_FUNC49_OUT_INV_SEL_S) +#define GPIO_FUNC49_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC49_OUT_INV_SEL_S 9 + +/* GPIO_FUNC49_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC49_OUT_SEL 0x000001FF +#define GPIO_FUNC49_OUT_SEL_M (GPIO_FUNC49_OUT_SEL_V << GPIO_FUNC49_OUT_SEL_S) +#define GPIO_FUNC49_OUT_SEL_V 0x000001FF +#define GPIO_FUNC49_OUT_SEL_S 0 + +/* GPIO_FUNC50_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 50 + */ + +#define GPIO_FUNC50_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x61c) + +/* GPIO_FUNC50_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC50_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC50_OEN_INV_SEL_M (GPIO_FUNC50_OEN_INV_SEL_V << GPIO_FUNC50_OEN_INV_SEL_S) +#define GPIO_FUNC50_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC50_OEN_INV_SEL_S 11 + +/* GPIO_FUNC50_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC50_OEN_SEL (BIT(10)) +#define GPIO_FUNC50_OEN_SEL_M (GPIO_FUNC50_OEN_SEL_V << GPIO_FUNC50_OEN_SEL_S) +#define GPIO_FUNC50_OEN_SEL_V 0x00000001 +#define GPIO_FUNC50_OEN_SEL_S 10 + +/* GPIO_FUNC50_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC50_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC50_OUT_INV_SEL_M (GPIO_FUNC50_OUT_INV_SEL_V << GPIO_FUNC50_OUT_INV_SEL_S) +#define GPIO_FUNC50_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC50_OUT_INV_SEL_S 9 + +/* GPIO_FUNC50_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC50_OUT_SEL 0x000001FF +#define GPIO_FUNC50_OUT_SEL_M (GPIO_FUNC50_OUT_SEL_V << GPIO_FUNC50_OUT_SEL_S) +#define GPIO_FUNC50_OUT_SEL_V 0x000001FF +#define GPIO_FUNC50_OUT_SEL_S 0 + +/* GPIO_FUNC51_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 51 + */ + +#define GPIO_FUNC51_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x620) + +/* GPIO_FUNC51_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC51_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC51_OEN_INV_SEL_M (GPIO_FUNC51_OEN_INV_SEL_V << GPIO_FUNC51_OEN_INV_SEL_S) +#define GPIO_FUNC51_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC51_OEN_INV_SEL_S 11 + +/* GPIO_FUNC51_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC51_OEN_SEL (BIT(10)) +#define GPIO_FUNC51_OEN_SEL_M (GPIO_FUNC51_OEN_SEL_V << GPIO_FUNC51_OEN_SEL_S) +#define GPIO_FUNC51_OEN_SEL_V 0x00000001 +#define GPIO_FUNC51_OEN_SEL_S 10 + +/* GPIO_FUNC51_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC51_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC51_OUT_INV_SEL_M (GPIO_FUNC51_OUT_INV_SEL_V << GPIO_FUNC51_OUT_INV_SEL_S) +#define GPIO_FUNC51_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC51_OUT_INV_SEL_S 9 + +/* GPIO_FUNC51_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC51_OUT_SEL 0x000001FF +#define GPIO_FUNC51_OUT_SEL_M (GPIO_FUNC51_OUT_SEL_V << GPIO_FUNC51_OUT_SEL_S) +#define GPIO_FUNC51_OUT_SEL_V 0x000001FF +#define GPIO_FUNC51_OUT_SEL_S 0 + +/* GPIO_FUNC52_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 52 + */ + +#define GPIO_FUNC52_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x624) + +/* GPIO_FUNC52_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC52_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC52_OEN_INV_SEL_M (GPIO_FUNC52_OEN_INV_SEL_V << GPIO_FUNC52_OEN_INV_SEL_S) +#define GPIO_FUNC52_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC52_OEN_INV_SEL_S 11 + +/* GPIO_FUNC52_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC52_OEN_SEL (BIT(10)) +#define GPIO_FUNC52_OEN_SEL_M (GPIO_FUNC52_OEN_SEL_V << GPIO_FUNC52_OEN_SEL_S) +#define GPIO_FUNC52_OEN_SEL_V 0x00000001 +#define GPIO_FUNC52_OEN_SEL_S 10 + +/* GPIO_FUNC52_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC52_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC52_OUT_INV_SEL_M (GPIO_FUNC52_OUT_INV_SEL_V << GPIO_FUNC52_OUT_INV_SEL_S) +#define GPIO_FUNC52_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC52_OUT_INV_SEL_S 9 + +/* GPIO_FUNC52_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC52_OUT_SEL 0x000001FF +#define GPIO_FUNC52_OUT_SEL_M (GPIO_FUNC52_OUT_SEL_V << GPIO_FUNC52_OUT_SEL_S) +#define GPIO_FUNC52_OUT_SEL_V 0x000001FF +#define GPIO_FUNC52_OUT_SEL_S 0 + +/* GPIO_FUNC53_OUT_SEL_CFG_REG register + * Peripheral output selection for GPIO 53 + */ + +#define GPIO_FUNC53_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x628) + +/* GPIO_FUNC53_OEN_INV_SEL : R/W; bitpos: [11]; default: 0; + * 0: Do not invert the output enable signal; 1: Invert the output enable + * signal. + */ + +#define GPIO_FUNC53_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC53_OEN_INV_SEL_M (GPIO_FUNC53_OEN_INV_SEL_V << GPIO_FUNC53_OEN_INV_SEL_S) +#define GPIO_FUNC53_OEN_INV_SEL_V 0x00000001 +#define GPIO_FUNC53_OEN_INV_SEL_S 11 + +/* GPIO_FUNC53_OEN_SEL : R/W; bitpos: [10]; default: 0; + * 0: Use output enable signal from peripheral; 1: Force the output enable + * signal to be sourced from bit n of GPIO_ENABLE_REG. + */ + +#define GPIO_FUNC53_OEN_SEL (BIT(10)) +#define GPIO_FUNC53_OEN_SEL_M (GPIO_FUNC53_OEN_SEL_V << GPIO_FUNC53_OEN_SEL_S) +#define GPIO_FUNC53_OEN_SEL_V 0x00000001 +#define GPIO_FUNC53_OEN_SEL_S 10 + +/* GPIO_FUNC53_OUT_INV_SEL : R/W; bitpos: [9]; default: 0; + * 0: Do not invert the output value; 1: Invert the output value. + */ + +#define GPIO_FUNC53_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC53_OUT_INV_SEL_M (GPIO_FUNC53_OUT_INV_SEL_V << GPIO_FUNC53_OUT_INV_SEL_S) +#define GPIO_FUNC53_OUT_INV_SEL_V 0x00000001 +#define GPIO_FUNC53_OUT_INV_SEL_S 9 + +/* GPIO_FUNC53_OUT_SEL : R/W; bitpos: [8:0]; default: 256; + * Selection control for GPIO output n. If a value s (0<=s<256) is written + * to this field, the peripheral output signal s will be connected to GPIO + * output n. If a value 256 is written to this field, bit n of + * GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be + * selected as the output value and output enable. + */ + +#define GPIO_FUNC53_OUT_SEL 0x000001FF +#define GPIO_FUNC53_OUT_SEL_M (GPIO_FUNC53_OUT_SEL_V << GPIO_FUNC53_OUT_SEL_S) +#define GPIO_FUNC53_OUT_SEL_V 0x000001FF +#define GPIO_FUNC53_OUT_SEL_S 0 + +/* GPIO_CLOCK_GATE_REG register + * GPIO clock gating register + */ + +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c) + +/* GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; + * Clock gating enable bit. If set to 1, the clock is free running. + */ + +#define GPIO_CLK_EN (BIT(0)) +#define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) +#define GPIO_CLK_EN_V 0x00000001 +#define GPIO_CLK_EN_S 0 + +/* GPIO_REG_DATE_REG register + * Version control register + */ + +#define GPIO_REG_DATE_REG (DR_REG_GPIO_BASE + 0x6fc) + +/* GPIO_DATE : R/W; bitpos: [27:0]; default: 26234977; + * Version control register + */ + +#define GPIO_DATE 0x0FFFFFFF +#define GPIO_DATE_M (GPIO_DATE_V << GPIO_DATE_S) +#define GPIO_DATE_V 0x0FFFFFFF +#define GPIO_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h new file mode 100644 index 0000000000..95f4e671b3 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h @@ -0,0 +1,327 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_gpio_sigmap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_SIGMAP_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_SIGMAP_H + +#define SPICLK_OUT_IDX SPICLK_OUT_MUX_IDX +#define CLK_I2S_IDX CLK_I2S_MUX_IDX +#define FSPICLK_OUT_IDX FSPICLK_OUT_MUX_IDX + +#define SPIQ_IN_IDX 0 +#define SPIQ_OUT_IDX 0 +#define SPID_IN_IDX 1 +#define SPID_OUT_IDX 1 +#define SPIHD_IN_IDX 2 +#define SPIHD_OUT_IDX 2 +#define SPIWP_IN_IDX 3 +#define SPIWP_OUT_IDX 3 +#define SPICLK_OUT_MUX_IDX 4 +#define SPICS0_OUT_IDX 5 +#define SPICS1_OUT_IDX 6 +#define SPID4_IN_IDX 7 +#define SPID4_OUT_IDX 7 +#define SPID5_IN_IDX 8 +#define SPID5_OUT_IDX 8 +#define SPID6_IN_IDX 9 +#define SPID6_OUT_IDX 9 +#define SPID7_IN_IDX 10 +#define SPID7_OUT_IDX 10 +#define SPIDQS_IN_IDX 11 +#define SPIDQS_OUT_IDX 11 +#define U0RXD_IN_IDX 14 +#define U0TXD_OUT_IDX 14 +#define U0CTS_IN_IDX 15 +#define U0RTS_OUT_IDX 15 +#define U0DSR_IN_IDX 16 +#define U0DTR_OUT_IDX 16 +#define U1RXD_IN_IDX 17 +#define U1TXD_OUT_IDX 17 +#define U1CTS_IN_IDX 18 +#define U1RTS_OUT_IDX 18 +#define U1DSR_IN_IDX 21 +#define U1DTR_OUT_IDX 21 +#define I2S0O_BCK_IN_IDX 23 +#define I2S0O_BCK_OUT_IDX 23 +#define I2S0O_WS_IN_IDX 25 +#define I2S0O_WS_OUT_IDX 25 +#define I2S0I_BCK_IN_IDX 27 +#define I2S0I_BCK_OUT_IDX 27 +#define I2S0I_WS_IN_IDX 28 +#define I2S0I_WS_OUT_IDX 28 +#define I2CEXT0_SCL_IN_IDX 29 +#define I2CEXT0_SCL_OUT_IDX 29 +#define I2CEXT0_SDA_IN_IDX 30 +#define I2CEXT0_SDA_OUT_IDX 30 +#define SDIO_TOHOST_INT_OUT_IDX 31 +#define GPIO_BT_ACTIVE_IDX 37 +#define GPIO_BT_PRIORITY_IDX 38 +#define PCNT_SIG_CH0_IN0_IDX 39 +#define GPIO_WLAN_PRIO_IDX 39 +#define PCNT_SIG_CH1_IN0_IDX 40 +#define GPIO_WLAN_ACTIVE_IDX 40 +#define PCNT_CTRL_CH0_IN0_IDX 41 +#define BB_DIAG0_IDX 41 +#define PCNT_CTRL_CH1_IN0_IDX 42 +#define BB_DIAG1_IDX 42 +#define PCNT_SIG_CH0_IN1_IDX 43 +#define BB_DIAG2_IDX 43 +#define PCNT_SIG_CH1_IN1_IDX 44 +#define BB_DIAG3_IDX 44 +#define PCNT_CTRL_CH0_IN1_IDX 45 +#define BB_DIAG4_IDX 45 +#define PCNT_CTRL_CH1_IN1_IDX 46 +#define BB_DIAG5_IDX 46 +#define PCNT_SIG_CH0_IN2_IDX 47 +#define BB_DIAG6_IDX 47 +#define PCNT_SIG_CH1_IN2_IDX 48 +#define BB_DIAG7_IDX 48 +#define PCNT_CTRL_CH0_IN2_IDX 49 +#define BB_DIAG8_IDX 49 +#define PCNT_CTRL_CH1_IN2_IDX 50 +#define BB_DIAG9_IDX 50 +#define PCNT_SIG_CH0_IN3_IDX 51 +#define BB_DIAG10_IDX 51 +#define PCNT_SIG_CH1_IN3_IDX 52 +#define BB_DIAG11_IDX 52 +#define PCNT_CTRL_CH0_IN3_IDX 53 +#define BB_DIAG12_IDX 53 +#define PCNT_CTRL_CH1_IN3_IDX 54 +#define BB_DIAG13_IDX 54 +#define BB_DIAG14_IDX 55 +#define BB_DIAG15_IDX 56 +#define BB_DIAG16_IDX 57 +#define BB_DIAG17_IDX 58 +#define BB_DIAG18_IDX 59 +#define BB_DIAG19_IDX 60 +#define USB_EXTPHY_VP_IDX 61 +#define USB_EXTPHY_OEN_IDX 61 +#define USB_EXTPHY_VM_IDX 62 +#define USB_EXTPHY_SPEED_IDX 62 +#define USB_EXTPHY_RCV_IDX 63 +#define USB_EXTPHY_VPO_IDX 63 +#define USB_OTG_IDDIG_IN_IDX 64 +#define USB_EXTPHY_VMO_IDX 64 +#define USB_OTG_AVALID_IN_IDX 65 +#define USB_EXTPHY_SUSPND_IDX 65 +#define USB_SRP_BVALID_IN_IDX 66 +#define USB_OTG_IDPULLUP_IDX 66 +#define USB_OTG_VBUSVALID_IN_IDX 67 +#define USB_OTG_DPPULLDOWN_IDX 67 +#define USB_SRP_SESSEND_IN_IDX 68 +#define USB_OTG_DMPULLDOWN_IDX 68 +#define USB_OTG_DRVVBUS_IDX 69 +#define USB_SRP_CHRGVBUS_IDX 70 +#define USB_SRP_DISCHRGVBUS_IDX 71 +#define SPI3_CLK_IN_IDX 72 +#define SPI3_CLK_OUT_MUX_IDX 72 +#define SPI3_Q_IN_IDX 73 +#define SPI3_Q_OUT_IDX 73 +#define SPI3_D_IN_IDX 74 +#define SPI3_D_OUT_IDX 74 +#define SPI3_HD_IN_IDX 75 +#define SPI3_HD_OUT_IDX 75 +#define SPI3_CS0_IN_IDX 76 +#define SPI3_CS0_OUT_IDX 76 +#define SPI3_CS1_OUT_IDX 77 +#define SPI3_CS2_OUT_IDX 78 +#define LEDC_LS_SIG_OUT0_IDX 79 +#define LEDC_LS_SIG_OUT1_IDX 80 +#define LEDC_LS_SIG_OUT2_IDX 81 +#define LEDC_LS_SIG_OUT3_IDX 82 +#define RMT_SIG_IN0_IDX 83 +#define LEDC_LS_SIG_OUT4_IDX 83 +#define RMT_SIG_IN1_IDX 84 +#define LEDC_LS_SIG_OUT5_IDX 84 +#define RMT_SIG_IN2_IDX 85 +#define LEDC_LS_SIG_OUT6_IDX 85 +#define RMT_SIG_IN3_IDX 86 +#define LEDC_LS_SIG_OUT7_IDX 86 +#define RMT_SIG_OUT0_IDX 87 +#define RMT_SIG_OUT1_IDX 88 +#define RMT_SIG_OUT2_IDX 89 +#define RMT_SIG_OUT3_IDX 90 +#define EXT_ADC_START_IDX 93 +#define I2CEXT1_SCL_IN_IDX 95 +#define I2CEXT1_SCL_OUT_IDX 95 +#define I2CEXT1_SDA_IN_IDX 96 +#define I2CEXT1_SDA_OUT_IDX 96 +#define GPIO_SD0_OUT_IDX 100 +#define GPIO_SD1_OUT_IDX 101 +#define GPIO_SD2_OUT_IDX 102 +#define GPIO_SD3_OUT_IDX 103 +#define GPIO_SD4_OUT_IDX 104 +#define GPIO_SD5_OUT_IDX 105 +#define GPIO_SD6_OUT_IDX 106 +#define GPIO_SD7_OUT_IDX 107 +#define FSPICLK_IN_IDX 108 +#define FSPICLK_OUT_MUX_IDX 108 +#define FSPIQ_IN_IDX 109 +#define FSPIQ_OUT_IDX 109 +#define FSPID_IN_IDX 110 +#define FSPID_OUT_IDX 110 +#define FSPIHD_IN_IDX 111 +#define FSPIHD_OUT_IDX 111 +#define FSPIWP_IN_IDX 112 +#define FSPIWP_OUT_IDX 112 +#define FSPIIO4_IN_IDX 113 +#define FSPIIO4_OUT_IDX 113 +#define FSPIIO5_IN_IDX 114 +#define FSPIIO5_OUT_IDX 114 +#define FSPIIO6_IN_IDX 115 +#define FSPIIO6_OUT_IDX 115 +#define FSPIIO7_IN_IDX 116 +#define FSPIIO7_OUT_IDX 116 +#define FSPICS0_IN_IDX 117 +#define FSPICS0_OUT_IDX 117 +#define FSPICS1_OUT_IDX 118 +#define FSPICS2_OUT_IDX 119 +#define FSPICS3_OUT_IDX 120 +#define FSPICS4_OUT_IDX 121 +#define FSPICS5_OUT_IDX 122 +#define TWAI_RX_IDX 123 +#define TWAI_TX_IDX 123 +#define TWAI_BUS_OFF_ON_IDX 124 +#define TWAI_CLKOUT_IDX 125 +#define SUBSPICLK_OUT_MUX_IDX 126 +#define SUBSPIQ_IN_IDX 127 +#define SUBSPIQ_OUT_IDX 127 +#define SUBSPID_IN_IDX 128 +#define SUBSPID_OUT_IDX 128 +#define SUBSPIHD_IN_IDX 129 +#define SUBSPIHD_OUT_IDX 129 +#define SUBSPIWP_IN_IDX 130 +#define SUBSPIWP_OUT_IDX 130 +#define SUBSPICS0_OUT_IDX 131 +#define SUBSPICS1_OUT_IDX 132 +#define FSPIDQS_OUT_IDX 133 +#define FSPI_HSYNC_OUT_IDX 134 +#define FSPI_VSYNC_OUT_IDX 135 +#define FSPI_DE_OUT_IDX 136 +#define FSPICD_OUT_IDX 137 +#define SPI3_CD_OUT_IDX 139 +#define SPI3_DQS_OUT_IDX 140 +#define I2S0I_DATA_IN0_IDX 143 +#define I2S0O_DATA_OUT0_IDX 143 +#define I2S0I_DATA_IN1_IDX 144 +#define I2S0O_DATA_OUT1_IDX 144 +#define I2S0I_DATA_IN2_IDX 145 +#define I2S0O_DATA_OUT2_IDX 145 +#define I2S0I_DATA_IN3_IDX 146 +#define I2S0O_DATA_OUT3_IDX 146 +#define I2S0I_DATA_IN4_IDX 147 +#define I2S0O_DATA_OUT4_IDX 147 +#define I2S0I_DATA_IN5_IDX 148 +#define I2S0O_DATA_OUT5_IDX 148 +#define I2S0I_DATA_IN6_IDX 149 +#define I2S0O_DATA_OUT6_IDX 149 +#define I2S0I_DATA_IN7_IDX 150 +#define I2S0O_DATA_OUT7_IDX 150 +#define I2S0I_DATA_IN8_IDX 151 +#define I2S0O_DATA_OUT8_IDX 151 +#define I2S0I_DATA_IN9_IDX 152 +#define I2S0O_DATA_OUT9_IDX 152 +#define I2S0I_DATA_IN10_IDX 153 +#define I2S0O_DATA_OUT10_IDX 153 +#define I2S0I_DATA_IN11_IDX 154 +#define I2S0O_DATA_OUT11_IDX 154 +#define I2S0I_DATA_IN12_IDX 155 +#define I2S0O_DATA_OUT12_IDX 155 +#define I2S0I_DATA_IN13_IDX 156 +#define I2S0O_DATA_OUT13_IDX 156 +#define I2S0I_DATA_IN14_IDX 157 +#define I2S0O_DATA_OUT14_IDX 157 +#define I2S0I_DATA_IN15_IDX 158 +#define I2S0O_DATA_OUT15_IDX 158 +#define I2S0O_DATA_OUT16_IDX 159 +#define I2S0O_DATA_OUT17_IDX 160 +#define I2S0O_DATA_OUT18_IDX 161 +#define I2S0O_DATA_OUT19_IDX 162 +#define I2S0O_DATA_OUT20_IDX 163 +#define I2S0O_DATA_OUT21_IDX 164 +#define I2S0O_DATA_OUT22_IDX 165 +#define I2S0O_DATA_OUT23_IDX 166 +#define SUBSPID4_IN_IDX 167 +#define SUBSPID4_OUT_IDX 167 +#define SUBSPID5_IN_IDX 168 +#define SUBSPID5_OUT_IDX 168 +#define SUBSPID6_IN_IDX 169 +#define SUBSPID6_OUT_IDX 169 +#define SUBSPID7_IN_IDX 170 +#define SUBSPID7_OUT_IDX 170 +#define SUBSPIDQS_IN_IDX 171 +#define SUBSPIDQS_OUT_IDX 171 +#define I2S0I_H_SYNC_IDX 193 +#define I2S0I_V_SYNC_IDX 194 +#define I2S0I_H_ENABLE_IDX 195 +#define PCMFSYNC_IN_IDX 203 +#define BT_AUDIO0_IRQ_IDX 203 +#define PCMCLK_IN_IDX 204 +#define BT_AUDIO1_IRQ_IDX 204 +#define PCMDIN_IDX 205 +#define BT_AUDIO2_IRQ_IDX 205 +#define RW_WAKEUP_REQ_IDX 206 +#define BLE_AUDIO0_IRQ_IDX 206 +#define BLE_AUDIO1_IRQ_IDX 207 +#define BLE_AUDIO2_IRQ_IDX 208 +#define PCMFSYNC_OUT_IDX 209 +#define PCMCLK_OUT_IDX 210 +#define PCMDOUT_IDX 211 +#define BLE_AUDIO_SYNC0_P_IDX 212 +#define BLE_AUDIO_SYNC1_P_IDX 213 +#define BLE_AUDIO_SYNC2_P_IDX 214 +#define ANT_SEL0_IDX 215 +#define ANT_SEL1_IDX 216 +#define ANT_SEL2_IDX 217 +#define ANT_SEL3_IDX 218 +#define ANT_SEL4_IDX 219 +#define ANT_SEL5_IDX 220 +#define ANT_SEL6_IDX 221 +#define ANT_SEL7_IDX 222 +#define SIG_IN_FUNC_223_IDX 223 +#define SIG_IN_FUNC223_IDX 223 +#define SIG_IN_FUNC_224_IDX 224 +#define SIG_IN_FUNC224_IDX 224 +#define SIG_IN_FUNC_225_IDX 225 +#define SIG_IN_FUNC225_IDX 225 +#define SIG_IN_FUNC_226_IDX 226 +#define SIG_IN_FUNC226_IDX 226 +#define SIG_IN_FUNC_227_IDX 227 +#define SIG_IN_FUNC227_IDX 227 +#define PRO_ALONEGPIO_IN0_IDX 235 +#define PRO_ALONEGPIO_OUT0_IDX 235 +#define PRO_ALONEGPIO_IN1_IDX 236 +#define PRO_ALONEGPIO_OUT1_IDX 236 +#define PRO_ALONEGPIO_IN2_IDX 237 +#define PRO_ALONEGPIO_OUT2_IDX 237 +#define PRO_ALONEGPIO_IN3_IDX 238 +#define PRO_ALONEGPIO_OUT3_IDX 238 +#define PRO_ALONEGPIO_IN4_IDX 239 +#define PRO_ALONEGPIO_OUT4_IDX 239 +#define PRO_ALONEGPIO_IN5_IDX 240 +#define PRO_ALONEGPIO_OUT5_IDX 240 +#define PRO_ALONEGPIO_IN6_IDX 241 +#define PRO_ALONEGPIO_OUT6_IDX 241 +#define PRO_ALONEGPIO_IN7_IDX 242 +#define PRO_ALONEGPIO_OUT7_IDX 242 +#define CLK_I2S_MUX_IDX 251 +#define SIG_GPIO_OUT_IDX 256 +#define GPIO_MAP_DATE_IDX 0x1904100 +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_GPIO_SIGMAP_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h new file mode 100644 index 0000000000..a014cb3f6a --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h @@ -0,0 +1,191 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H + +/** + * Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal + * configuration bus. These definitions are used via macros defined in + * regi2c_ctrl.h, by rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 1 + +#define I2C_BBPLL_IR_CAL_DELAY 0 +#define I2C_BBPLL_IR_CAL_DELAY_MSB 3 +#define I2C_BBPLL_IR_CAL_DELAY_LSB 0 + +#define I2C_BBPLL_IR_CAL_CK_DIV 0 +#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7 +#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4 + +#define I2C_BBPLL_IR_CAL_EXT_CAP 1 +#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3 +#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_BBPLL_IR_CAL_ENX_CAP 1 +#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4 +#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4 + +#define I2C_BBPLL_IR_CAL_RSTB 1 +#define I2C_BBPLL_IR_CAL_RSTB_MSB 5 +#define I2C_BBPLL_IR_CAL_RSTB_LSB 5 + +#define I2C_BBPLL_IR_CAL_START 1 +#define I2C_BBPLL_IR_CAL_START_MSB 6 +#define I2C_BBPLL_IR_CAL_START_LSB 6 + +#define I2C_BBPLL_IR_CAL_UNSTOP 1 +#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 +#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DCHGP 2 +#define I2C_BBPLL_OC_DCHGP_MSB 6 +#define I2C_BBPLL_OC_DCHGP_LSB 4 + +#define I2C_BBPLL_OC_ENB_FCAL 2 +#define I2C_BBPLL_OC_ENB_FCAL_MSB 7 +#define I2C_BBPLL_OC_ENB_FCAL_LSB 7 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#define I2C_BBPLL_RSTB_DIV_ADC 4 +#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0 +#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0 + +#define I2C_BBPLL_MODE_HF 4 +#define I2C_BBPLL_MODE_HF_MSB 1 +#define I2C_BBPLL_MODE_HF_LSB 1 + +#define I2C_BBPLL_DIV_ADC 4 +#define I2C_BBPLL_DIV_ADC_MSB 3 +#define I2C_BBPLL_DIV_ADC_LSB 2 + +#define I2C_BBPLL_DIV_DAC 4 +#define I2C_BBPLL_DIV_DAC_MSB 4 +#define I2C_BBPLL_DIV_DAC_LSB 4 + +#define I2C_BBPLL_DIV_CPU 4 +#define I2C_BBPLL_DIV_CPU_MSB 5 +#define I2C_BBPLL_DIV_CPU_LSB 5 + +#define I2C_BBPLL_OC_ENB_VCON 4 +#define I2C_BBPLL_OC_ENB_VCON_MSB 6 +#define I2C_BBPLL_OC_ENB_VCON_LSB 6 + +#define I2C_BBPLL_OC_TSCHGP 4 +#define I2C_BBPLL_OC_TSCHGP_MSB 7 +#define I2C_BBPLL_OC_TSCHGP_LSB 7 + +#define I2C_BBPLL_OC_DR1 5 +#define I2C_BBPLL_OC_DR1_MSB 2 +#define I2C_BBPLL_OC_DR1_LSB 0 + +#define I2C_BBPLL_OC_DR3 5 +#define I2C_BBPLL_OC_DR3_MSB 6 +#define I2C_BBPLL_OC_DR3_LSB 4 + +#define I2C_BBPLL_EN_USB 5 +#define I2C_BBPLL_EN_USB_MSB 7 +#define I2C_BBPLL_EN_USB_LSB 7 + +#define I2C_BBPLL_OC_DCUR 6 +#define I2C_BBPLL_OC_DCUR_MSB 2 +#define I2C_BBPLL_OC_DCUR_LSB 0 + +#define I2C_BBPLL_INC_CUR 6 +#define I2C_BBPLL_INC_CUR_MSB 3 +#define I2C_BBPLL_INC_CUR_LSB 3 + +#define I2C_BBPLL_OC_DHREF_SEL 6 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 6 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 + +#define I2C_BBPLL_OR_CAL_CAP 8 +#define I2C_BBPLL_OR_CAL_CAP_MSB 3 +#define I2C_BBPLL_OR_CAL_CAP_LSB 0 + +#define I2C_BBPLL_OR_CAL_UDF 8 +#define I2C_BBPLL_OR_CAL_UDF_MSB 4 +#define I2C_BBPLL_OR_CAL_UDF_LSB 4 + +#define I2C_BBPLL_OR_CAL_OVF 8 +#define I2C_BBPLL_OR_CAL_OVF_MSB 5 +#define I2C_BBPLL_OR_CAL_OVF_LSB 5 + +#define I2C_BBPLL_OR_CAL_END 8 +#define I2C_BBPLL_OR_CAL_END_MSB 6 +#define I2C_BBPLL_OR_CAL_END_LSB 6 + +#define I2C_BBPLL_OR_LOCK 8 +#define I2C_BBPLL_OR_LOCK_MSB 7 +#define I2C_BBPLL_OR_LOCK_LSB 7 + +#define I2C_BBPLL_BBADC_DELAY1 9 +#define I2C_BBPLL_BBADC_DELAY1_MSB 1 +#define I2C_BBPLL_BBADC_DELAY1_LSB 0 + +#define I2C_BBPLL_BBADC_DELAY2 9 +#define I2C_BBPLL_BBADC_DELAY2_MSB 3 +#define I2C_BBPLL_BBADC_DELAY2_LSB 2 + +#define I2C_BBPLL_BBADC_DVDD 9 +#define I2C_BBPLL_BBADC_DVDD_MSB 5 +#define I2C_BBPLL_BBADC_DVDD_LSB 4 + +#define I2C_BBPLL_BBADC_DREF 9 +#define I2C_BBPLL_BBADC_DREF_MSB 7 +#define I2C_BBPLL_BBADC_DREF_LSB 6 + +#define I2C_BBPLL_BBADC_DCUR 10 +#define I2C_BBPLL_BBADC_DCUR_MSB 1 +#define I2C_BBPLL_BBADC_DCUR_LSB 0 + +#define I2C_BBPLL_BBADC_INPUT_SHORT 10 +#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2 +#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2 + +#define I2C_BBPLL_ENT_PLL 10 +#define I2C_BBPLL_ENT_PLL_MSB 3 +#define I2C_BBPLL_ENT_PLL_LSB 3 + +#define I2C_BBPLL_DTEST 10 +#define I2C_BBPLL_DTEST_MSB 5 +#define I2C_BBPLL_DTEST_LSB 4 + +#define I2C_BBPLL_ENT_ADC 10 +#define I2C_BBPLL_ENT_ADC_MSB 7 +#define I2C_BBPLL_ENT_ADC_LSB 6 + +#endif diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_i2s.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_i2s.h new file mode 100644 index 0000000000..74c3732c2c --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_i2s.h @@ -0,0 +1,2229 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_i2s.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2S_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2S_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* I2S_CONF_REG register + * I2S Configure register + */ + +#define I2S_CONF_REG (DR_REG_I2S_BASE + 0x8) + +/* I2S_RX_RESET_ST : RO; bitpos: [29]; default: 0; + * I2S RX reset status. 1: I2S_RX_RESET is not finished. 0: I2S_RX_RESET is + * finished. + */ + +#define I2S_RX_RESET_ST (BIT(29)) +#define I2S_RX_RESET_ST_M (I2S_RX_RESET_ST_V << I2S_RX_RESET_ST_S) +#define I2S_RX_RESET_ST_V 0x00000001 +#define I2S_RX_RESET_ST_S 29 + +/* I2S_RX_BIG_ENDIAN : R/W; bitpos: [28]; default: 0; + * I2S RX byte endian. + */ + +#define I2S_RX_BIG_ENDIAN (BIT(28)) +#define I2S_RX_BIG_ENDIAN_M (I2S_RX_BIG_ENDIAN_V << I2S_RX_BIG_ENDIAN_S) +#define I2S_RX_BIG_ENDIAN_V 0x00000001 +#define I2S_RX_BIG_ENDIAN_S 28 + +/* I2S_TX_BIG_ENDIAN : R/W; bitpos: [27]; default: 0; + * I2S TX byte endian. + */ + +#define I2S_TX_BIG_ENDIAN (BIT(27)) +#define I2S_TX_BIG_ENDIAN_M (I2S_TX_BIG_ENDIAN_V << I2S_TX_BIG_ENDIAN_S) +#define I2S_TX_BIG_ENDIAN_V 0x00000001 +#define I2S_TX_BIG_ENDIAN_S 27 + +/* I2S_PRE_REQ_EN : R/W; bitpos: [26]; default: 0; + * set this bit to enable i2s to prepare data earlier + */ + +#define I2S_PRE_REQ_EN (BIT(26)) +#define I2S_PRE_REQ_EN_M (I2S_PRE_REQ_EN_V << I2S_PRE_REQ_EN_S) +#define I2S_PRE_REQ_EN_V 0x00000001 +#define I2S_PRE_REQ_EN_S 26 + +/* I2S_RX_DMA_EQUAL : R/W; bitpos: [25]; default: 0; + * 1:data in left channel is equal to data in right channel + */ + +#define I2S_RX_DMA_EQUAL (BIT(25)) +#define I2S_RX_DMA_EQUAL_M (I2S_RX_DMA_EQUAL_V << I2S_RX_DMA_EQUAL_S) +#define I2S_RX_DMA_EQUAL_V 0x00000001 +#define I2S_RX_DMA_EQUAL_S 25 + +/* I2S_TX_DMA_EQUAL : R/W; bitpos: [24]; default: 0; + * 1:data in left channel is equal to data in right channel + */ + +#define I2S_TX_DMA_EQUAL (BIT(24)) +#define I2S_TX_DMA_EQUAL_M (I2S_TX_DMA_EQUAL_V << I2S_TX_DMA_EQUAL_S) +#define I2S_TX_DMA_EQUAL_V 0x00000001 +#define I2S_TX_DMA_EQUAL_S 24 + +/* I2S_TX_RESET_ST : RO; bitpos: [23]; default: 0; + * 1: i2s_tx_reset is not ok 0: i2s_tx_reset is ok + */ + +#define I2S_TX_RESET_ST (BIT(23)) +#define I2S_TX_RESET_ST_M (I2S_TX_RESET_ST_V << I2S_TX_RESET_ST_S) +#define I2S_TX_RESET_ST_V 0x00000001 +#define I2S_TX_RESET_ST_S 23 + +/* I2S_RX_FIFO_RESET_ST : RO; bitpos: [22]; default: 0; + * 1:i2s_rx_fifo_reset is not ok 0:i2s_rx_fifo reset is ok + */ + +#define I2S_RX_FIFO_RESET_ST (BIT(22)) +#define I2S_RX_FIFO_RESET_ST_M (I2S_RX_FIFO_RESET_ST_V << I2S_RX_FIFO_RESET_ST_S) +#define I2S_RX_FIFO_RESET_ST_V 0x00000001 +#define I2S_RX_FIFO_RESET_ST_S 22 + +/* I2S_TX_FIFO_RESET_ST : RO; bitpos: [21]; default: 0; + * 1:i2s_tx_fifo reset is not ok 0:i2s_tx_fifo_reset is ok + */ + +#define I2S_TX_FIFO_RESET_ST (BIT(21)) +#define I2S_TX_FIFO_RESET_ST_M (I2S_TX_FIFO_RESET_ST_V << I2S_TX_FIFO_RESET_ST_S) +#define I2S_TX_FIFO_RESET_ST_V 0x00000001 +#define I2S_TX_FIFO_RESET_ST_S 21 + +/* I2S_SIG_LOOPBACK : R/W; bitpos: [20]; default: 0; + * Enable signal loopback mode with transmitter module and receiver module + * sharing the same WS and BCK signals. + */ + +#define I2S_SIG_LOOPBACK (BIT(20)) +#define I2S_SIG_LOOPBACK_M (I2S_SIG_LOOPBACK_V << I2S_SIG_LOOPBACK_S) +#define I2S_SIG_LOOPBACK_V 0x00000001 +#define I2S_SIG_LOOPBACK_S 20 + +/* I2S_RX_LSB_FIRST_DMA : R/W; bitpos: [19]; default: 1; + * 1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB + * transform from high bits. + */ + +#define I2S_RX_LSB_FIRST_DMA (BIT(19)) +#define I2S_RX_LSB_FIRST_DMA_M (I2S_RX_LSB_FIRST_DMA_V << I2S_RX_LSB_FIRST_DMA_S) +#define I2S_RX_LSB_FIRST_DMA_V 0x00000001 +#define I2S_RX_LSB_FIRST_DMA_S 19 + +/* I2S_TX_LSB_FIRST_DMA : R/W; bitpos: [18]; default: 1; + * 1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB + * transform from high bits. + */ + +#define I2S_TX_LSB_FIRST_DMA (BIT(18)) +#define I2S_TX_LSB_FIRST_DMA_M (I2S_TX_LSB_FIRST_DMA_V << I2S_TX_LSB_FIRST_DMA_S) +#define I2S_TX_LSB_FIRST_DMA_V 0x00000001 +#define I2S_TX_LSB_FIRST_DMA_S 18 + +/* I2S_RX_MSB_RIGHT : R/W; bitpos: [17]; default: 0; + * Set this bit to place right channel data at the MSB in the receive FIFO. + */ + +#define I2S_RX_MSB_RIGHT (BIT(17)) +#define I2S_RX_MSB_RIGHT_M (I2S_RX_MSB_RIGHT_V << I2S_RX_MSB_RIGHT_S) +#define I2S_RX_MSB_RIGHT_V 0x00000001 +#define I2S_RX_MSB_RIGHT_S 17 + +/* I2S_TX_MSB_RIGHT : R/W; bitpos: [16]; default: 0; + * Set this bit to place right channel data at the MSB in the transmit FIFO. + */ + +#define I2S_TX_MSB_RIGHT (BIT(16)) +#define I2S_TX_MSB_RIGHT_M (I2S_TX_MSB_RIGHT_V << I2S_TX_MSB_RIGHT_S) +#define I2S_TX_MSB_RIGHT_V 0x00000001 +#define I2S_TX_MSB_RIGHT_S 16 + +/* I2S_RX_MONO : R/W; bitpos: [15]; default: 0; + * Set this bit to enable receiver in mono mode + */ + +#define I2S_RX_MONO (BIT(15)) +#define I2S_RX_MONO_M (I2S_RX_MONO_V << I2S_RX_MONO_S) +#define I2S_RX_MONO_V 0x00000001 +#define I2S_RX_MONO_S 15 + +/* I2S_TX_MONO : R/W; bitpos: [14]; default: 0; + * Set this bit to enable transmitter in mono mode + */ + +#define I2S_TX_MONO (BIT(14)) +#define I2S_TX_MONO_M (I2S_TX_MONO_V << I2S_TX_MONO_S) +#define I2S_TX_MONO_V 0x00000001 +#define I2S_TX_MONO_S 14 + +/* I2S_RX_SHORT_SYNC : R/W; bitpos: [13]; default: 0; + * Set this bit to enable receiver in PCM standard mode + */ + +#define I2S_RX_SHORT_SYNC (BIT(13)) +#define I2S_RX_SHORT_SYNC_M (I2S_RX_SHORT_SYNC_V << I2S_RX_SHORT_SYNC_S) +#define I2S_RX_SHORT_SYNC_V 0x00000001 +#define I2S_RX_SHORT_SYNC_S 13 + +/* I2S_TX_SHORT_SYNC : R/W; bitpos: [12]; default: 0; + * Set this bit to enable transmitter in PCM standard mode + */ + +#define I2S_TX_SHORT_SYNC (BIT(12)) +#define I2S_TX_SHORT_SYNC_M (I2S_TX_SHORT_SYNC_V << I2S_TX_SHORT_SYNC_S) +#define I2S_TX_SHORT_SYNC_V 0x00000001 +#define I2S_TX_SHORT_SYNC_S 12 + +/* I2S_RX_MSB_SHIFT : R/W; bitpos: [11]; default: 0; + * Set this bit to enable receiver in Phillips standard mode + */ + +#define I2S_RX_MSB_SHIFT (BIT(11)) +#define I2S_RX_MSB_SHIFT_M (I2S_RX_MSB_SHIFT_V << I2S_RX_MSB_SHIFT_S) +#define I2S_RX_MSB_SHIFT_V 0x00000001 +#define I2S_RX_MSB_SHIFT_S 11 + +/* I2S_TX_MSB_SHIFT : R/W; bitpos: [10]; default: 0; + * Set this bit to enable transmitter in Phillips standard mode + */ + +#define I2S_TX_MSB_SHIFT (BIT(10)) +#define I2S_TX_MSB_SHIFT_M (I2S_TX_MSB_SHIFT_V << I2S_TX_MSB_SHIFT_S) +#define I2S_TX_MSB_SHIFT_V 0x00000001 +#define I2S_TX_MSB_SHIFT_S 10 + +/* I2S_RX_RIGHT_FIRST : R/W; bitpos: [9]; default: 1; + * Set this bit to receive right channel data first + */ + +#define I2S_RX_RIGHT_FIRST (BIT(9)) +#define I2S_RX_RIGHT_FIRST_M (I2S_RX_RIGHT_FIRST_V << I2S_RX_RIGHT_FIRST_S) +#define I2S_RX_RIGHT_FIRST_V 0x00000001 +#define I2S_RX_RIGHT_FIRST_S 9 + +/* I2S_TX_RIGHT_FIRST : R/W; bitpos: [8]; default: 1; + * Set this bit to transmit right channel data first + */ + +#define I2S_TX_RIGHT_FIRST (BIT(8)) +#define I2S_TX_RIGHT_FIRST_M (I2S_TX_RIGHT_FIRST_V << I2S_TX_RIGHT_FIRST_S) +#define I2S_TX_RIGHT_FIRST_V 0x00000001 +#define I2S_TX_RIGHT_FIRST_S 8 + +/* I2S_RX_SLAVE_MOD : R/W; bitpos: [7]; default: 0; + * Set this bit to enable slave receiver mode + */ + +#define I2S_RX_SLAVE_MOD (BIT(7)) +#define I2S_RX_SLAVE_MOD_M (I2S_RX_SLAVE_MOD_V << I2S_RX_SLAVE_MOD_S) +#define I2S_RX_SLAVE_MOD_V 0x00000001 +#define I2S_RX_SLAVE_MOD_S 7 + +/* I2S_TX_SLAVE_MOD : R/W; bitpos: [6]; default: 0; + * Set this bit to enable slave transmitter mode + */ + +#define I2S_TX_SLAVE_MOD (BIT(6)) +#define I2S_TX_SLAVE_MOD_M (I2S_TX_SLAVE_MOD_V << I2S_TX_SLAVE_MOD_S) +#define I2S_TX_SLAVE_MOD_V 0x00000001 +#define I2S_TX_SLAVE_MOD_S 6 + +/* I2S_RX_START : R/W; bitpos: [5]; default: 0; + * Set this bit to start receiving data + */ + +#define I2S_RX_START (BIT(5)) +#define I2S_RX_START_M (I2S_RX_START_V << I2S_RX_START_S) +#define I2S_RX_START_V 0x00000001 +#define I2S_RX_START_S 5 + +/* I2S_TX_START : R/W; bitpos: [4]; default: 0; + * Set this bit to start transmitting data + */ + +#define I2S_TX_START (BIT(4)) +#define I2S_TX_START_M (I2S_TX_START_V << I2S_TX_START_S) +#define I2S_TX_START_V 0x00000001 +#define I2S_TX_START_S 4 + +/* I2S_RX_FIFO_RESET : WO; bitpos: [3]; default: 0; + * Set this bit to reset rxFIFO + */ + +#define I2S_RX_FIFO_RESET (BIT(3)) +#define I2S_RX_FIFO_RESET_M (I2S_RX_FIFO_RESET_V << I2S_RX_FIFO_RESET_S) +#define I2S_RX_FIFO_RESET_V 0x00000001 +#define I2S_RX_FIFO_RESET_S 3 + +/* I2S_TX_FIFO_RESET : WO; bitpos: [2]; default: 0; + * Set this bit to reset txFIFO + */ + +#define I2S_TX_FIFO_RESET (BIT(2)) +#define I2S_TX_FIFO_RESET_M (I2S_TX_FIFO_RESET_V << I2S_TX_FIFO_RESET_S) +#define I2S_TX_FIFO_RESET_V 0x00000001 +#define I2S_TX_FIFO_RESET_S 2 + +/* I2S_RX_RESET : WO; bitpos: [1]; default: 0; + * Set this bit to reset receiver + */ + +#define I2S_RX_RESET (BIT(1)) +#define I2S_RX_RESET_M (I2S_RX_RESET_V << I2S_RX_RESET_S) +#define I2S_RX_RESET_V 0x00000001 +#define I2S_RX_RESET_S 1 + +/* I2S_TX_RESET : WO; bitpos: [0]; default: 0; + * Set this bit to reset transmitter + */ + +#define I2S_TX_RESET (BIT(0)) +#define I2S_TX_RESET_M (I2S_TX_RESET_V << I2S_TX_RESET_S) +#define I2S_TX_RESET_V 0x00000001 +#define I2S_TX_RESET_S 0 + +/* I2S_INT_RAW_REG register + * Raw interrupt status + */ + +#define I2S_INT_RAW_REG (DR_REG_I2S_BASE + 0xc) + +/* I2S_V_SYNC_INT_RAW : RO; bitpos: [17]; default: 0; + * The raw interrupt status bit for the i2s_v_sync_int interrupt + */ + +#define I2S_V_SYNC_INT_RAW (BIT(17)) +#define I2S_V_SYNC_INT_RAW_M (I2S_V_SYNC_INT_RAW_V << I2S_V_SYNC_INT_RAW_S) +#define I2S_V_SYNC_INT_RAW_V 0x00000001 +#define I2S_V_SYNC_INT_RAW_S 17 + +/* I2S_OUT_TOTAL_EOF_INT_RAW : RO; bitpos: [16]; default: 0; + * The raw interrupt status bit for the i2s_out_total_eof_int interrupt + */ + +#define I2S_OUT_TOTAL_EOF_INT_RAW (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_RAW_M (I2S_OUT_TOTAL_EOF_INT_RAW_V << I2S_OUT_TOTAL_EOF_INT_RAW_S) +#define I2S_OUT_TOTAL_EOF_INT_RAW_V 0x00000001 +#define I2S_OUT_TOTAL_EOF_INT_RAW_S 16 + +/* I2S_IN_DSCR_EMPTY_INT_RAW : RO; bitpos: [15]; default: 0; + * The raw interrupt status bit for the i2s_in_dscr_empty_int interrupt + */ + +#define I2S_IN_DSCR_EMPTY_INT_RAW (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_RAW_M (I2S_IN_DSCR_EMPTY_INT_RAW_V << I2S_IN_DSCR_EMPTY_INT_RAW_S) +#define I2S_IN_DSCR_EMPTY_INT_RAW_V 0x00000001 +#define I2S_IN_DSCR_EMPTY_INT_RAW_S 15 + +/* I2S_OUT_DSCR_ERR_INT_RAW : RO; bitpos: [14]; default: 0; + * The raw interrupt status bit for the i2s_out_dscr_err_int interrupt + */ + +#define I2S_OUT_DSCR_ERR_INT_RAW (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_RAW_M (I2S_OUT_DSCR_ERR_INT_RAW_V << I2S_OUT_DSCR_ERR_INT_RAW_S) +#define I2S_OUT_DSCR_ERR_INT_RAW_V 0x00000001 +#define I2S_OUT_DSCR_ERR_INT_RAW_S 14 + +/* I2S_IN_DSCR_ERR_INT_RAW : RO; bitpos: [13]; default: 0; + * The raw interrupt status bit for the i2s_in_dscr_err_int interrupt + */ + +#define I2S_IN_DSCR_ERR_INT_RAW (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_RAW_M (I2S_IN_DSCR_ERR_INT_RAW_V << I2S_IN_DSCR_ERR_INT_RAW_S) +#define I2S_IN_DSCR_ERR_INT_RAW_V 0x00000001 +#define I2S_IN_DSCR_ERR_INT_RAW_S 13 + +/* I2S_OUT_EOF_INT_RAW : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the i2s_out_eof_int interrupt + */ + +#define I2S_OUT_EOF_INT_RAW (BIT(12)) +#define I2S_OUT_EOF_INT_RAW_M (I2S_OUT_EOF_INT_RAW_V << I2S_OUT_EOF_INT_RAW_S) +#define I2S_OUT_EOF_INT_RAW_V 0x00000001 +#define I2S_OUT_EOF_INT_RAW_S 12 + +/* I2S_OUT_DONE_INT_RAW : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the i2s_out_done_int interrupt + */ + +#define I2S_OUT_DONE_INT_RAW (BIT(11)) +#define I2S_OUT_DONE_INT_RAW_M (I2S_OUT_DONE_INT_RAW_V << I2S_OUT_DONE_INT_RAW_S) +#define I2S_OUT_DONE_INT_RAW_V 0x00000001 +#define I2S_OUT_DONE_INT_RAW_S 11 + +/* I2S_IN_ERR_EOF_INT_RAW : RO; bitpos: [10]; default: 0; + * don't use + */ + +#define I2S_IN_ERR_EOF_INT_RAW (BIT(10)) +#define I2S_IN_ERR_EOF_INT_RAW_M (I2S_IN_ERR_EOF_INT_RAW_V << I2S_IN_ERR_EOF_INT_RAW_S) +#define I2S_IN_ERR_EOF_INT_RAW_V 0x00000001 +#define I2S_IN_ERR_EOF_INT_RAW_S 10 + +/* I2S_IN_SUC_EOF_INT_RAW : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the i2s_in_suc_eof_int interrupt + */ + +#define I2S_IN_SUC_EOF_INT_RAW (BIT(9)) +#define I2S_IN_SUC_EOF_INT_RAW_M (I2S_IN_SUC_EOF_INT_RAW_V << I2S_IN_SUC_EOF_INT_RAW_S) +#define I2S_IN_SUC_EOF_INT_RAW_V 0x00000001 +#define I2S_IN_SUC_EOF_INT_RAW_S 9 + +/* I2S_IN_DONE_INT_RAW : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the i2s_in_done_int interrupt + */ + +#define I2S_IN_DONE_INT_RAW (BIT(8)) +#define I2S_IN_DONE_INT_RAW_M (I2S_IN_DONE_INT_RAW_V << I2S_IN_DONE_INT_RAW_S) +#define I2S_IN_DONE_INT_RAW_V 0x00000001 +#define I2S_IN_DONE_INT_RAW_S 8 + +/* I2S_TX_HUNG_INT_RAW : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the i2s_tx_hung_int interrupt + */ + +#define I2S_TX_HUNG_INT_RAW (BIT(7)) +#define I2S_TX_HUNG_INT_RAW_M (I2S_TX_HUNG_INT_RAW_V << I2S_TX_HUNG_INT_RAW_S) +#define I2S_TX_HUNG_INT_RAW_V 0x00000001 +#define I2S_TX_HUNG_INT_RAW_S 7 + +/* I2S_RX_HUNG_INT_RAW : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the i2s_rx_hung_int interrupt + */ + +#define I2S_RX_HUNG_INT_RAW (BIT(6)) +#define I2S_RX_HUNG_INT_RAW_M (I2S_RX_HUNG_INT_RAW_V << I2S_RX_HUNG_INT_RAW_S) +#define I2S_RX_HUNG_INT_RAW_V 0x00000001 +#define I2S_RX_HUNG_INT_RAW_S 6 + +/* I2S_TX_REMPTY_INT_RAW : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the i2s_tx_rempty_int interrupt + */ + +#define I2S_TX_REMPTY_INT_RAW (BIT(5)) +#define I2S_TX_REMPTY_INT_RAW_M (I2S_TX_REMPTY_INT_RAW_V << I2S_TX_REMPTY_INT_RAW_S) +#define I2S_TX_REMPTY_INT_RAW_V 0x00000001 +#define I2S_TX_REMPTY_INT_RAW_S 5 + +/* I2S_TX_WFULL_INT_RAW : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the i2s_tx_wfull_int interrupt + */ + +#define I2S_TX_WFULL_INT_RAW (BIT(4)) +#define I2S_TX_WFULL_INT_RAW_M (I2S_TX_WFULL_INT_RAW_V << I2S_TX_WFULL_INT_RAW_S) +#define I2S_TX_WFULL_INT_RAW_V 0x00000001 +#define I2S_TX_WFULL_INT_RAW_S 4 + +/* I2S_RX_REMPTY_INT_RAW : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the i2s_rx_rempty_int interrupt + */ + +#define I2S_RX_REMPTY_INT_RAW (BIT(3)) +#define I2S_RX_REMPTY_INT_RAW_M (I2S_RX_REMPTY_INT_RAW_V << I2S_RX_REMPTY_INT_RAW_S) +#define I2S_RX_REMPTY_INT_RAW_V 0x00000001 +#define I2S_RX_REMPTY_INT_RAW_S 3 + +/* I2S_RX_WFULL_INT_RAW : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the i2s_rx_wfull_int interrupt + */ + +#define I2S_RX_WFULL_INT_RAW (BIT(2)) +#define I2S_RX_WFULL_INT_RAW_M (I2S_RX_WFULL_INT_RAW_V << I2S_RX_WFULL_INT_RAW_S) +#define I2S_RX_WFULL_INT_RAW_V 0x00000001 +#define I2S_RX_WFULL_INT_RAW_S 2 + +/* I2S_TX_PUT_DATA_INT_RAW : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the i2s_tx_put_data_int interrupt + */ + +#define I2S_TX_PUT_DATA_INT_RAW (BIT(1)) +#define I2S_TX_PUT_DATA_INT_RAW_M (I2S_TX_PUT_DATA_INT_RAW_V << I2S_TX_PUT_DATA_INT_RAW_S) +#define I2S_TX_PUT_DATA_INT_RAW_V 0x00000001 +#define I2S_TX_PUT_DATA_INT_RAW_S 1 + +/* I2S_RX_TAKE_DATA_INT_RAW : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the i2s_rx_take_data_int interrupt + */ + +#define I2S_RX_TAKE_DATA_INT_RAW (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_RAW_M (I2S_RX_TAKE_DATA_INT_RAW_V << I2S_RX_TAKE_DATA_INT_RAW_S) +#define I2S_RX_TAKE_DATA_INT_RAW_V 0x00000001 +#define I2S_RX_TAKE_DATA_INT_RAW_S 0 + +/* I2S_INT_ST_REG register + * Masked interrupt status + */ + +#define I2S_INT_ST_REG (DR_REG_I2S_BASE + 0x10) + +/* I2S_V_SYNC_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for the i2s_v_sync_int interrupt + */ + +#define I2S_V_SYNC_INT_ST (BIT(17)) +#define I2S_V_SYNC_INT_ST_M (I2S_V_SYNC_INT_ST_V << I2S_V_SYNC_INT_ST_S) +#define I2S_V_SYNC_INT_ST_V 0x00000001 +#define I2S_V_SYNC_INT_ST_S 17 + +/* I2S_OUT_TOTAL_EOF_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for the i2s_out_total_eof_int interrupt + */ + +#define I2S_OUT_TOTAL_EOF_INT_ST (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_ST_M (I2S_OUT_TOTAL_EOF_INT_ST_V << I2S_OUT_TOTAL_EOF_INT_ST_S) +#define I2S_OUT_TOTAL_EOF_INT_ST_V 0x00000001 +#define I2S_OUT_TOTAL_EOF_INT_ST_S 16 + +/* I2S_IN_DSCR_EMPTY_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for the i2s_in_dscr_empty_int interrupt + */ + +#define I2S_IN_DSCR_EMPTY_INT_ST (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_ST_M (I2S_IN_DSCR_EMPTY_INT_ST_V << I2S_IN_DSCR_EMPTY_INT_ST_S) +#define I2S_IN_DSCR_EMPTY_INT_ST_V 0x00000001 +#define I2S_IN_DSCR_EMPTY_INT_ST_S 15 + +/* I2S_OUT_DSCR_ERR_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for the i2s_out_dscr_err_int interrupt + */ + +#define I2S_OUT_DSCR_ERR_INT_ST (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_ST_M (I2S_OUT_DSCR_ERR_INT_ST_V << I2S_OUT_DSCR_ERR_INT_ST_S) +#define I2S_OUT_DSCR_ERR_INT_ST_V 0x00000001 +#define I2S_OUT_DSCR_ERR_INT_ST_S 14 + +/* I2S_IN_DSCR_ERR_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for the i2s_in_dscr_err_int interrupt + */ + +#define I2S_IN_DSCR_ERR_INT_ST (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_ST_M (I2S_IN_DSCR_ERR_INT_ST_V << I2S_IN_DSCR_ERR_INT_ST_S) +#define I2S_IN_DSCR_ERR_INT_ST_V 0x00000001 +#define I2S_IN_DSCR_ERR_INT_ST_S 13 + +/* I2S_OUT_EOF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for the i2s_out_eof_int interrupt + */ + +#define I2S_OUT_EOF_INT_ST (BIT(12)) +#define I2S_OUT_EOF_INT_ST_M (I2S_OUT_EOF_INT_ST_V << I2S_OUT_EOF_INT_ST_S) +#define I2S_OUT_EOF_INT_ST_V 0x00000001 +#define I2S_OUT_EOF_INT_ST_S 12 + +/* I2S_OUT_DONE_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for the i2s_out_done_int interrupt + */ + +#define I2S_OUT_DONE_INT_ST (BIT(11)) +#define I2S_OUT_DONE_INT_ST_M (I2S_OUT_DONE_INT_ST_V << I2S_OUT_DONE_INT_ST_S) +#define I2S_OUT_DONE_INT_ST_V 0x00000001 +#define I2S_OUT_DONE_INT_ST_S 11 + +/* I2S_IN_ERR_EOF_INT_ST : RO; bitpos: [10]; default: 0; + * don't use + */ + +#define I2S_IN_ERR_EOF_INT_ST (BIT(10)) +#define I2S_IN_ERR_EOF_INT_ST_M (I2S_IN_ERR_EOF_INT_ST_V << I2S_IN_ERR_EOF_INT_ST_S) +#define I2S_IN_ERR_EOF_INT_ST_V 0x00000001 +#define I2S_IN_ERR_EOF_INT_ST_S 10 + +/* I2S_IN_SUC_EOF_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the i2s_in_suc_eof_int interrupt + */ + +#define I2S_IN_SUC_EOF_INT_ST (BIT(9)) +#define I2S_IN_SUC_EOF_INT_ST_M (I2S_IN_SUC_EOF_INT_ST_V << I2S_IN_SUC_EOF_INT_ST_S) +#define I2S_IN_SUC_EOF_INT_ST_V 0x00000001 +#define I2S_IN_SUC_EOF_INT_ST_S 9 + +/* I2S_IN_DONE_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the i2s_in_done_int interrupt + */ + +#define I2S_IN_DONE_INT_ST (BIT(8)) +#define I2S_IN_DONE_INT_ST_M (I2S_IN_DONE_INT_ST_V << I2S_IN_DONE_INT_ST_S) +#define I2S_IN_DONE_INT_ST_V 0x00000001 +#define I2S_IN_DONE_INT_ST_S 8 + +/* I2S_TX_HUNG_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the i2s_tx_hung_int interrupt + */ + +#define I2S_TX_HUNG_INT_ST (BIT(7)) +#define I2S_TX_HUNG_INT_ST_M (I2S_TX_HUNG_INT_ST_V << I2S_TX_HUNG_INT_ST_S) +#define I2S_TX_HUNG_INT_ST_V 0x00000001 +#define I2S_TX_HUNG_INT_ST_S 7 + +/* I2S_RX_HUNG_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for the i2s_rx_hung_int interrupt + */ + +#define I2S_RX_HUNG_INT_ST (BIT(6)) +#define I2S_RX_HUNG_INT_ST_M (I2S_RX_HUNG_INT_ST_V << I2S_RX_HUNG_INT_ST_S) +#define I2S_RX_HUNG_INT_ST_V 0x00000001 +#define I2S_RX_HUNG_INT_ST_S 6 + +/* I2S_TX_REMPTY_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the i2s_tx_rempty_int interrupt + */ + +#define I2S_TX_REMPTY_INT_ST (BIT(5)) +#define I2S_TX_REMPTY_INT_ST_M (I2S_TX_REMPTY_INT_ST_V << I2S_TX_REMPTY_INT_ST_S) +#define I2S_TX_REMPTY_INT_ST_V 0x00000001 +#define I2S_TX_REMPTY_INT_ST_S 5 + +/* I2S_TX_WFULL_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the i2s_tx_wfull_int interrupt + */ + +#define I2S_TX_WFULL_INT_ST (BIT(4)) +#define I2S_TX_WFULL_INT_ST_M (I2S_TX_WFULL_INT_ST_V << I2S_TX_WFULL_INT_ST_S) +#define I2S_TX_WFULL_INT_ST_V 0x00000001 +#define I2S_TX_WFULL_INT_ST_S 4 + +/* I2S_RX_REMPTY_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the i2s_rx_rempty_int interrupt + */ + +#define I2S_RX_REMPTY_INT_ST (BIT(3)) +#define I2S_RX_REMPTY_INT_ST_M (I2S_RX_REMPTY_INT_ST_V << I2S_RX_REMPTY_INT_ST_S) +#define I2S_RX_REMPTY_INT_ST_V 0x00000001 +#define I2S_RX_REMPTY_INT_ST_S 3 + +/* I2S_RX_WFULL_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the i2s_rx_wfull_int interrupt + */ + +#define I2S_RX_WFULL_INT_ST (BIT(2)) +#define I2S_RX_WFULL_INT_ST_M (I2S_RX_WFULL_INT_ST_V << I2S_RX_WFULL_INT_ST_S) +#define I2S_RX_WFULL_INT_ST_V 0x00000001 +#define I2S_RX_WFULL_INT_ST_S 2 + +/* I2S_TX_PUT_DATA_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the i2s_tx_put_data_int interrupt + */ + +#define I2S_TX_PUT_DATA_INT_ST (BIT(1)) +#define I2S_TX_PUT_DATA_INT_ST_M (I2S_TX_PUT_DATA_INT_ST_V << I2S_TX_PUT_DATA_INT_ST_S) +#define I2S_TX_PUT_DATA_INT_ST_V 0x00000001 +#define I2S_TX_PUT_DATA_INT_ST_S 1 + +/* I2S_RX_TAKE_DATA_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the i2s_rx_take_data_int interrupt + */ + +#define I2S_RX_TAKE_DATA_INT_ST (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_ST_M (I2S_RX_TAKE_DATA_INT_ST_V << I2S_RX_TAKE_DATA_INT_ST_S) +#define I2S_RX_TAKE_DATA_INT_ST_V 0x00000001 +#define I2S_RX_TAKE_DATA_INT_ST_S 0 + +/* I2S_INT_ENA_REG register + * Interrupt enable bits + */ + +#define I2S_INT_ENA_REG (DR_REG_I2S_BASE + 0x14) + +/* I2S_V_SYNC_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for the i2s_v_sync_int interrupt + */ + +#define I2S_V_SYNC_INT_ENA (BIT(17)) +#define I2S_V_SYNC_INT_ENA_M (I2S_V_SYNC_INT_ENA_V << I2S_V_SYNC_INT_ENA_S) +#define I2S_V_SYNC_INT_ENA_V 0x00000001 +#define I2S_V_SYNC_INT_ENA_S 17 + +/* I2S_OUT_TOTAL_EOF_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for the i2s_out_total_eof_int interrupt + */ + +#define I2S_OUT_TOTAL_EOF_INT_ENA (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_ENA_M (I2S_OUT_TOTAL_EOF_INT_ENA_V << I2S_OUT_TOTAL_EOF_INT_ENA_S) +#define I2S_OUT_TOTAL_EOF_INT_ENA_V 0x00000001 +#define I2S_OUT_TOTAL_EOF_INT_ENA_S 16 + +/* I2S_IN_DSCR_EMPTY_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the i2s_in_dscr_empty_int interrupt + */ + +#define I2S_IN_DSCR_EMPTY_INT_ENA (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_ENA_M (I2S_IN_DSCR_EMPTY_INT_ENA_V << I2S_IN_DSCR_EMPTY_INT_ENA_S) +#define I2S_IN_DSCR_EMPTY_INT_ENA_V 0x00000001 +#define I2S_IN_DSCR_EMPTY_INT_ENA_S 15 + +/* I2S_OUT_DSCR_ERR_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the i2s_out_dscr_err_int interrupt + */ + +#define I2S_OUT_DSCR_ERR_INT_ENA (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_ENA_M (I2S_OUT_DSCR_ERR_INT_ENA_V << I2S_OUT_DSCR_ERR_INT_ENA_S) +#define I2S_OUT_DSCR_ERR_INT_ENA_V 0x00000001 +#define I2S_OUT_DSCR_ERR_INT_ENA_S 14 + +/* I2S_IN_DSCR_ERR_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the i2s_in_dscr_err_int interrupt + */ + +#define I2S_IN_DSCR_ERR_INT_ENA (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_ENA_M (I2S_IN_DSCR_ERR_INT_ENA_V << I2S_IN_DSCR_ERR_INT_ENA_S) +#define I2S_IN_DSCR_ERR_INT_ENA_V 0x00000001 +#define I2S_IN_DSCR_ERR_INT_ENA_S 13 + +/* I2S_OUT_EOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the i2s_out_eof_int interrupt + */ + +#define I2S_OUT_EOF_INT_ENA (BIT(12)) +#define I2S_OUT_EOF_INT_ENA_M (I2S_OUT_EOF_INT_ENA_V << I2S_OUT_EOF_INT_ENA_S) +#define I2S_OUT_EOF_INT_ENA_V 0x00000001 +#define I2S_OUT_EOF_INT_ENA_S 12 + +/* I2S_OUT_DONE_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the i2s_out_done_int interrupt + */ + +#define I2S_OUT_DONE_INT_ENA (BIT(11)) +#define I2S_OUT_DONE_INT_ENA_M (I2S_OUT_DONE_INT_ENA_V << I2S_OUT_DONE_INT_ENA_S) +#define I2S_OUT_DONE_INT_ENA_V 0x00000001 +#define I2S_OUT_DONE_INT_ENA_S 11 + +/* I2S_IN_ERR_EOF_INT_ENA : R/W; bitpos: [10]; default: 0; + * don't use + */ + +#define I2S_IN_ERR_EOF_INT_ENA (BIT(10)) +#define I2S_IN_ERR_EOF_INT_ENA_M (I2S_IN_ERR_EOF_INT_ENA_V << I2S_IN_ERR_EOF_INT_ENA_S) +#define I2S_IN_ERR_EOF_INT_ENA_V 0x00000001 +#define I2S_IN_ERR_EOF_INT_ENA_S 10 + +/* I2S_IN_SUC_EOF_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the i2s_in_suc_eof_int interrupt + */ + +#define I2S_IN_SUC_EOF_INT_ENA (BIT(9)) +#define I2S_IN_SUC_EOF_INT_ENA_M (I2S_IN_SUC_EOF_INT_ENA_V << I2S_IN_SUC_EOF_INT_ENA_S) +#define I2S_IN_SUC_EOF_INT_ENA_V 0x00000001 +#define I2S_IN_SUC_EOF_INT_ENA_S 9 + +/* I2S_IN_DONE_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the i2s_in_done_int interrupt + */ + +#define I2S_IN_DONE_INT_ENA (BIT(8)) +#define I2S_IN_DONE_INT_ENA_M (I2S_IN_DONE_INT_ENA_V << I2S_IN_DONE_INT_ENA_S) +#define I2S_IN_DONE_INT_ENA_V 0x00000001 +#define I2S_IN_DONE_INT_ENA_S 8 + +/* I2S_TX_HUNG_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the i2s_tx_hung_int interrupt + */ + +#define I2S_TX_HUNG_INT_ENA (BIT(7)) +#define I2S_TX_HUNG_INT_ENA_M (I2S_TX_HUNG_INT_ENA_V << I2S_TX_HUNG_INT_ENA_S) +#define I2S_TX_HUNG_INT_ENA_V 0x00000001 +#define I2S_TX_HUNG_INT_ENA_S 7 + +/* I2S_RX_HUNG_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the i2s_rx_hung_int interrupt + */ + +#define I2S_RX_HUNG_INT_ENA (BIT(6)) +#define I2S_RX_HUNG_INT_ENA_M (I2S_RX_HUNG_INT_ENA_V << I2S_RX_HUNG_INT_ENA_S) +#define I2S_RX_HUNG_INT_ENA_V 0x00000001 +#define I2S_RX_HUNG_INT_ENA_S 6 + +/* I2S_TX_REMPTY_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the i2s_tx_rempty_int interrupt + */ + +#define I2S_TX_REMPTY_INT_ENA (BIT(5)) +#define I2S_TX_REMPTY_INT_ENA_M (I2S_TX_REMPTY_INT_ENA_V << I2S_TX_REMPTY_INT_ENA_S) +#define I2S_TX_REMPTY_INT_ENA_V 0x00000001 +#define I2S_TX_REMPTY_INT_ENA_S 5 + +/* I2S_TX_WFULL_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the i2s_tx_wfull_int interrupt + */ + +#define I2S_TX_WFULL_INT_ENA (BIT(4)) +#define I2S_TX_WFULL_INT_ENA_M (I2S_TX_WFULL_INT_ENA_V << I2S_TX_WFULL_INT_ENA_S) +#define I2S_TX_WFULL_INT_ENA_V 0x00000001 +#define I2S_TX_WFULL_INT_ENA_S 4 + +/* I2S_RX_REMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the i2s_rx_rempty_int interrupt + */ + +#define I2S_RX_REMPTY_INT_ENA (BIT(3)) +#define I2S_RX_REMPTY_INT_ENA_M (I2S_RX_REMPTY_INT_ENA_V << I2S_RX_REMPTY_INT_ENA_S) +#define I2S_RX_REMPTY_INT_ENA_V 0x00000001 +#define I2S_RX_REMPTY_INT_ENA_S 3 + +/* I2S_RX_WFULL_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the i2s_rx_wfull_int interrupt + */ + +#define I2S_RX_WFULL_INT_ENA (BIT(2)) +#define I2S_RX_WFULL_INT_ENA_M (I2S_RX_WFULL_INT_ENA_V << I2S_RX_WFULL_INT_ENA_S) +#define I2S_RX_WFULL_INT_ENA_V 0x00000001 +#define I2S_RX_WFULL_INT_ENA_S 2 + +/* I2S_TX_PUT_DATA_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the i2s_tx_put_data_int interrupt + */ + +#define I2S_TX_PUT_DATA_INT_ENA (BIT(1)) +#define I2S_TX_PUT_DATA_INT_ENA_M (I2S_TX_PUT_DATA_INT_ENA_V << I2S_TX_PUT_DATA_INT_ENA_S) +#define I2S_TX_PUT_DATA_INT_ENA_V 0x00000001 +#define I2S_TX_PUT_DATA_INT_ENA_S 1 + +/* I2S_RX_TAKE_DATA_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the i2s_rx_take_data_int interrupt + */ + +#define I2S_RX_TAKE_DATA_INT_ENA (BIT(0)) +#define I2S_RX_TAKE_DATA_INT_ENA_M (I2S_RX_TAKE_DATA_INT_ENA_V << I2S_RX_TAKE_DATA_INT_ENA_S) +#define I2S_RX_TAKE_DATA_INT_ENA_V 0x00000001 +#define I2S_RX_TAKE_DATA_INT_ENA_S 0 + +/* I2S_INT_CLR_REG register + * Interrupt clear bits + */ + +#define I2S_INT_CLR_REG (DR_REG_I2S_BASE + 0x18) + +/* I2S_V_SYNC_INT_CLR : WO; bitpos: [17]; default: 0; + * Set this bit to clear the i2s_v_sync_int interrupt + */ + +#define I2S_V_SYNC_INT_CLR (BIT(17)) +#define I2S_V_SYNC_INT_CLR_M (I2S_V_SYNC_INT_CLR_V << I2S_V_SYNC_INT_CLR_S) +#define I2S_V_SYNC_INT_CLR_V 0x00000001 +#define I2S_V_SYNC_INT_CLR_S 17 + +/* I2S_OUT_TOTAL_EOF_INT_CLR : WO; bitpos: [16]; default: 0; + * Set this bit to clear the i2s_out_total_eof_int interrupt + */ + +#define I2S_OUT_TOTAL_EOF_INT_CLR (BIT(16)) +#define I2S_OUT_TOTAL_EOF_INT_CLR_M (I2S_OUT_TOTAL_EOF_INT_CLR_V << I2S_OUT_TOTAL_EOF_INT_CLR_S) +#define I2S_OUT_TOTAL_EOF_INT_CLR_V 0x00000001 +#define I2S_OUT_TOTAL_EOF_INT_CLR_S 16 + +/* I2S_IN_DSCR_EMPTY_INT_CLR : WO; bitpos: [15]; default: 0; + * Set this bit to clear the i2s_in_dscr_empty_int interrupt + */ + +#define I2S_IN_DSCR_EMPTY_INT_CLR (BIT(15)) +#define I2S_IN_DSCR_EMPTY_INT_CLR_M (I2S_IN_DSCR_EMPTY_INT_CLR_V << I2S_IN_DSCR_EMPTY_INT_CLR_S) +#define I2S_IN_DSCR_EMPTY_INT_CLR_V 0x00000001 +#define I2S_IN_DSCR_EMPTY_INT_CLR_S 15 + +/* I2S_OUT_DSCR_ERR_INT_CLR : WO; bitpos: [14]; default: 0; + * Set this bit to clear the i2s_out_dscr_err_int interrupt + */ + +#define I2S_OUT_DSCR_ERR_INT_CLR (BIT(14)) +#define I2S_OUT_DSCR_ERR_INT_CLR_M (I2S_OUT_DSCR_ERR_INT_CLR_V << I2S_OUT_DSCR_ERR_INT_CLR_S) +#define I2S_OUT_DSCR_ERR_INT_CLR_V 0x00000001 +#define I2S_OUT_DSCR_ERR_INT_CLR_S 14 + +/* I2S_IN_DSCR_ERR_INT_CLR : WO; bitpos: [13]; default: 0; + * Set this bit to clear the i2s_in_dscr_err_int interrupt + */ + +#define I2S_IN_DSCR_ERR_INT_CLR (BIT(13)) +#define I2S_IN_DSCR_ERR_INT_CLR_M (I2S_IN_DSCR_ERR_INT_CLR_V << I2S_IN_DSCR_ERR_INT_CLR_S) +#define I2S_IN_DSCR_ERR_INT_CLR_V 0x00000001 +#define I2S_IN_DSCR_ERR_INT_CLR_S 13 + +/* I2S_OUT_EOF_INT_CLR : WO; bitpos: [12]; default: 0; + * Set this bit to clear the i2s_out_eof_int interrupt + */ + +#define I2S_OUT_EOF_INT_CLR (BIT(12)) +#define I2S_OUT_EOF_INT_CLR_M (I2S_OUT_EOF_INT_CLR_V << I2S_OUT_EOF_INT_CLR_S) +#define I2S_OUT_EOF_INT_CLR_V 0x00000001 +#define I2S_OUT_EOF_INT_CLR_S 12 + +/* I2S_OUT_DONE_INT_CLR : WO; bitpos: [11]; default: 0; + * Set this bit to clear the i2s_out_done_int interrupt + */ + +#define I2S_OUT_DONE_INT_CLR (BIT(11)) +#define I2S_OUT_DONE_INT_CLR_M (I2S_OUT_DONE_INT_CLR_V << I2S_OUT_DONE_INT_CLR_S) +#define I2S_OUT_DONE_INT_CLR_V 0x00000001 +#define I2S_OUT_DONE_INT_CLR_S 11 + +/* I2S_IN_ERR_EOF_INT_CLR : WO; bitpos: [10]; default: 0; + * don't use + */ + +#define I2S_IN_ERR_EOF_INT_CLR (BIT(10)) +#define I2S_IN_ERR_EOF_INT_CLR_M (I2S_IN_ERR_EOF_INT_CLR_V << I2S_IN_ERR_EOF_INT_CLR_S) +#define I2S_IN_ERR_EOF_INT_CLR_V 0x00000001 +#define I2S_IN_ERR_EOF_INT_CLR_S 10 + +/* I2S_IN_SUC_EOF_INT_CLR : WO; bitpos: [9]; default: 0; + * Set this bit to clear the i2s_in_suc_eof_int interrupt + */ + +#define I2S_IN_SUC_EOF_INT_CLR (BIT(9)) +#define I2S_IN_SUC_EOF_INT_CLR_M (I2S_IN_SUC_EOF_INT_CLR_V << I2S_IN_SUC_EOF_INT_CLR_S) +#define I2S_IN_SUC_EOF_INT_CLR_V 0x00000001 +#define I2S_IN_SUC_EOF_INT_CLR_S 9 + +/* I2S_IN_DONE_INT_CLR : WO; bitpos: [8]; default: 0; + * Set this bit to clear the i2s_in_done_int interrupt + */ + +#define I2S_IN_DONE_INT_CLR (BIT(8)) +#define I2S_IN_DONE_INT_CLR_M (I2S_IN_DONE_INT_CLR_V << I2S_IN_DONE_INT_CLR_S) +#define I2S_IN_DONE_INT_CLR_V 0x00000001 +#define I2S_IN_DONE_INT_CLR_S 8 + +/* I2S_TX_HUNG_INT_CLR : WO; bitpos: [7]; default: 0; + * Set this bit to clear the i2s_tx_hung_int interrupt + */ + +#define I2S_TX_HUNG_INT_CLR (BIT(7)) +#define I2S_TX_HUNG_INT_CLR_M (I2S_TX_HUNG_INT_CLR_V << I2S_TX_HUNG_INT_CLR_S) +#define I2S_TX_HUNG_INT_CLR_V 0x00000001 +#define I2S_TX_HUNG_INT_CLR_S 7 + +/* I2S_RX_HUNG_INT_CLR : WO; bitpos: [6]; default: 0; + * Set this bit to clear the i2s_rx_hung_int interrupt + */ + +#define I2S_RX_HUNG_INT_CLR (BIT(6)) +#define I2S_RX_HUNG_INT_CLR_M (I2S_RX_HUNG_INT_CLR_V << I2S_RX_HUNG_INT_CLR_S) +#define I2S_RX_HUNG_INT_CLR_V 0x00000001 +#define I2S_RX_HUNG_INT_CLR_S 6 + +/* I2S_TX_REMPTY_INT_CLR : WO; bitpos: [5]; default: 0; + * Set this bit to clear the i2s_tx_rempty_int interrupt + */ + +#define I2S_TX_REMPTY_INT_CLR (BIT(5)) +#define I2S_TX_REMPTY_INT_CLR_M (I2S_TX_REMPTY_INT_CLR_V << I2S_TX_REMPTY_INT_CLR_S) +#define I2S_TX_REMPTY_INT_CLR_V 0x00000001 +#define I2S_TX_REMPTY_INT_CLR_S 5 + +/* I2S_TX_WFULL_INT_CLR : WO; bitpos: [4]; default: 0; + * Set this bit to clear the i2s_tx_wfull_int interrupt + */ + +#define I2S_TX_WFULL_INT_CLR (BIT(4)) +#define I2S_TX_WFULL_INT_CLR_M (I2S_TX_WFULL_INT_CLR_V << I2S_TX_WFULL_INT_CLR_S) +#define I2S_TX_WFULL_INT_CLR_V 0x00000001 +#define I2S_TX_WFULL_INT_CLR_S 4 + +/* I2S_RX_REMPTY_INT_CLR : WO; bitpos: [3]; default: 0; + * Set this bit to clear the i2s_rx_rempty_int interrupt + */ + +#define I2S_RX_REMPTY_INT_CLR (BIT(3)) +#define I2S_RX_REMPTY_INT_CLR_M (I2S_RX_REMPTY_INT_CLR_V << I2S_RX_REMPTY_INT_CLR_S) +#define I2S_RX_REMPTY_INT_CLR_V 0x00000001 +#define I2S_RX_REMPTY_INT_CLR_S 3 + +/* I2S_RX_WFULL_INT_CLR : WO; bitpos: [2]; default: 0; + * Set this bit to clear the i2s_rx_wfull_int interrupt + */ + +#define I2S_RX_WFULL_INT_CLR (BIT(2)) +#define I2S_RX_WFULL_INT_CLR_M (I2S_RX_WFULL_INT_CLR_V << I2S_RX_WFULL_INT_CLR_S) +#define I2S_RX_WFULL_INT_CLR_V 0x00000001 +#define I2S_RX_WFULL_INT_CLR_S 2 + +/* I2S_PUT_DATA_INT_CLR : WO; bitpos: [1]; default: 0; + * Set this bit to clear the i2s_tx_put_data_int interrupt + */ + +#define I2S_PUT_DATA_INT_CLR (BIT(1)) +#define I2S_PUT_DATA_INT_CLR_M (I2S_PUT_DATA_INT_CLR_V << I2S_PUT_DATA_INT_CLR_S) +#define I2S_PUT_DATA_INT_CLR_V 0x00000001 +#define I2S_PUT_DATA_INT_CLR_S 1 + +/* I2S_TAKE_DATA_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to clear the i2s_rx_take_data_int interrupt + */ + +#define I2S_TAKE_DATA_INT_CLR (BIT(0)) +#define I2S_TAKE_DATA_INT_CLR_M (I2S_TAKE_DATA_INT_CLR_V << I2S_TAKE_DATA_INT_CLR_S) +#define I2S_TAKE_DATA_INT_CLR_V 0x00000001 +#define I2S_TAKE_DATA_INT_CLR_S 0 + +/* I2S_TIMING_REG register + * I2S timing register + */ + +#define I2S_TIMING_REG (DR_REG_I2S_BASE + 0x1c) + +/* I2S_TX_BCK_IN_INV : R/W; bitpos: [24]; default: 0; + * Set this bit to invert BCK signal input to the slave transmitter + */ + +#define I2S_TX_BCK_IN_INV (BIT(24)) +#define I2S_TX_BCK_IN_INV_M (I2S_TX_BCK_IN_INV_V << I2S_TX_BCK_IN_INV_S) +#define I2S_TX_BCK_IN_INV_V 0x00000001 +#define I2S_TX_BCK_IN_INV_S 24 + +/* I2S_DATA_ENABLE_DELAY : R/W; bitpos: [23:22]; default: 0; + * Number of delay cycles for data valid flag. + */ + +#define I2S_DATA_ENABLE_DELAY 0x00000003 +#define I2S_DATA_ENABLE_DELAY_M (I2S_DATA_ENABLE_DELAY_V << I2S_DATA_ENABLE_DELAY_S) +#define I2S_DATA_ENABLE_DELAY_V 0x00000003 +#define I2S_DATA_ENABLE_DELAY_S 22 + +/* I2S_RX_DSYNC_SW : R/W; bitpos: [21]; default: 0; + * Set this bit to synchronize signals with the double sync method into the + * receiver + */ + +#define I2S_RX_DSYNC_SW (BIT(21)) +#define I2S_RX_DSYNC_SW_M (I2S_RX_DSYNC_SW_V << I2S_RX_DSYNC_SW_S) +#define I2S_RX_DSYNC_SW_V 0x00000001 +#define I2S_RX_DSYNC_SW_S 21 + +/* I2S_TX_DSYNC_SW : R/W; bitpos: [20]; default: 0; + * Set this bit to synchronize signals with the double sync method into the + * transmitter + */ + +#define I2S_TX_DSYNC_SW (BIT(20)) +#define I2S_TX_DSYNC_SW_M (I2S_TX_DSYNC_SW_V << I2S_TX_DSYNC_SW_S) +#define I2S_TX_DSYNC_SW_V 0x00000001 +#define I2S_TX_DSYNC_SW_S 20 + +/* I2S_RX_BCK_OUT_DELAY : R/W; bitpos: [19:18]; default: 0; + * Number of delay cycles for BCK out of the receiver + */ + +#define I2S_RX_BCK_OUT_DELAY 0x00000003 +#define I2S_RX_BCK_OUT_DELAY_M (I2S_RX_BCK_OUT_DELAY_V << I2S_RX_BCK_OUT_DELAY_S) +#define I2S_RX_BCK_OUT_DELAY_V 0x00000003 +#define I2S_RX_BCK_OUT_DELAY_S 18 + +/* I2S_RX_WS_OUT_DELAY : R/W; bitpos: [17:16]; default: 0; + * Number of delay cycles for WS out of the receiver + */ + +#define I2S_RX_WS_OUT_DELAY 0x00000003 +#define I2S_RX_WS_OUT_DELAY_M (I2S_RX_WS_OUT_DELAY_V << I2S_RX_WS_OUT_DELAY_S) +#define I2S_RX_WS_OUT_DELAY_V 0x00000003 +#define I2S_RX_WS_OUT_DELAY_S 16 + +/* I2S_TX_SD_OUT_DELAY : R/W; bitpos: [15:14]; default: 0; + * Number of delay cycles for SD out of the transmitter + */ + +#define I2S_TX_SD_OUT_DELAY 0x00000003 +#define I2S_TX_SD_OUT_DELAY_M (I2S_TX_SD_OUT_DELAY_V << I2S_TX_SD_OUT_DELAY_S) +#define I2S_TX_SD_OUT_DELAY_V 0x00000003 +#define I2S_TX_SD_OUT_DELAY_S 14 + +/* I2S_TX_WS_OUT_DELAY : R/W; bitpos: [13:12]; default: 0; + * Number of delay cycles for WS out of the transmitter + */ + +#define I2S_TX_WS_OUT_DELAY 0x00000003 +#define I2S_TX_WS_OUT_DELAY_M (I2S_TX_WS_OUT_DELAY_V << I2S_TX_WS_OUT_DELAY_S) +#define I2S_TX_WS_OUT_DELAY_V 0x00000003 +#define I2S_TX_WS_OUT_DELAY_S 12 + +/* I2S_TX_BCK_OUT_DELAY : R/W; bitpos: [11:10]; default: 0; + * Number of delay cycles for BCK out of the transmitter + */ + +#define I2S_TX_BCK_OUT_DELAY 0x00000003 +#define I2S_TX_BCK_OUT_DELAY_M (I2S_TX_BCK_OUT_DELAY_V << I2S_TX_BCK_OUT_DELAY_S) +#define I2S_TX_BCK_OUT_DELAY_V 0x00000003 +#define I2S_TX_BCK_OUT_DELAY_S 10 + +/* I2S_RX_SD_IN_DELAY : R/W; bitpos: [9:8]; default: 0; + * Number of delay cycles for SD into the receiver + */ + +#define I2S_RX_SD_IN_DELAY 0x00000003 +#define I2S_RX_SD_IN_DELAY_M (I2S_RX_SD_IN_DELAY_V << I2S_RX_SD_IN_DELAY_S) +#define I2S_RX_SD_IN_DELAY_V 0x00000003 +#define I2S_RX_SD_IN_DELAY_S 8 + +/* I2S_RX_WS_IN_DELAY : R/W; bitpos: [7:6]; default: 0; + * Number of delay cycles for WS into the receiver + */ + +#define I2S_RX_WS_IN_DELAY 0x00000003 +#define I2S_RX_WS_IN_DELAY_M (I2S_RX_WS_IN_DELAY_V << I2S_RX_WS_IN_DELAY_S) +#define I2S_RX_WS_IN_DELAY_V 0x00000003 +#define I2S_RX_WS_IN_DELAY_S 6 + +/* I2S_RX_BCK_IN_DELAY : R/W; bitpos: [5:4]; default: 0; + * Number of delay cycles for BCK into the receiver + */ + +#define I2S_RX_BCK_IN_DELAY 0x00000003 +#define I2S_RX_BCK_IN_DELAY_M (I2S_RX_BCK_IN_DELAY_V << I2S_RX_BCK_IN_DELAY_S) +#define I2S_RX_BCK_IN_DELAY_V 0x00000003 +#define I2S_RX_BCK_IN_DELAY_S 4 + +/* I2S_TX_WS_IN_DELAY : R/W; bitpos: [3:2]; default: 0; + * Number of delay cycles for WS into the transmitter + */ + +#define I2S_TX_WS_IN_DELAY 0x00000003 +#define I2S_TX_WS_IN_DELAY_M (I2S_TX_WS_IN_DELAY_V << I2S_TX_WS_IN_DELAY_S) +#define I2S_TX_WS_IN_DELAY_V 0x00000003 +#define I2S_TX_WS_IN_DELAY_S 2 + +/* I2S_TX_BCK_IN_DELAY : R/W; bitpos: [1:0]; default: 0; + * Number of delay cycles for BCK into the transmitter + */ + +#define I2S_TX_BCK_IN_DELAY 0x00000003 +#define I2S_TX_BCK_IN_DELAY_M (I2S_TX_BCK_IN_DELAY_V << I2S_TX_BCK_IN_DELAY_S) +#define I2S_TX_BCK_IN_DELAY_V 0x00000003 +#define I2S_TX_BCK_IN_DELAY_S 0 + +/* I2S_FIFO_CONF_REG register + * I2S FIFO configure register + */ + +#define I2S_FIFO_CONF_REG (DR_REG_I2S_BASE + 0x20) + +/* I2S_TX_24MSB_EN : R/W; bitpos: [23]; default: 0; + * Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s + * fifo 0: the low 24 bits are effective in i2s fifo + */ + +#define I2S_TX_24MSB_EN (BIT(23)) +#define I2S_TX_24MSB_EN_M (I2S_TX_24MSB_EN_V << I2S_TX_24MSB_EN_S) +#define I2S_TX_24MSB_EN_V 0x00000001 +#define I2S_TX_24MSB_EN_S 23 + +/* I2S_RX_24MSB_EN : R/W; bitpos: [22]; default: 0; + * Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s + * fifo 0: the low 24 bits are effective in i2s fifo + */ + +#define I2S_RX_24MSB_EN (BIT(22)) +#define I2S_RX_24MSB_EN_M (I2S_RX_24MSB_EN_V << I2S_RX_24MSB_EN_S) +#define I2S_RX_24MSB_EN_V 0x00000001 +#define I2S_RX_24MSB_EN_S 22 + +/* I2S_RX_FIFO_SYNC : R/W; bitpos: [21]; default: 0; + * force write back rx data to memory + */ + +#define I2S_RX_FIFO_SYNC (BIT(21)) +#define I2S_RX_FIFO_SYNC_M (I2S_RX_FIFO_SYNC_V << I2S_RX_FIFO_SYNC_S) +#define I2S_RX_FIFO_SYNC_V 0x00000001 +#define I2S_RX_FIFO_SYNC_S 21 + +/* I2S_RX_FIFO_MOD_FORCE_EN : R/W; bitpos: [20]; default: 0; + * The bit should always be set to 1 + */ + +#define I2S_RX_FIFO_MOD_FORCE_EN (BIT(20)) +#define I2S_RX_FIFO_MOD_FORCE_EN_M (I2S_RX_FIFO_MOD_FORCE_EN_V << I2S_RX_FIFO_MOD_FORCE_EN_S) +#define I2S_RX_FIFO_MOD_FORCE_EN_V 0x00000001 +#define I2S_RX_FIFO_MOD_FORCE_EN_S 20 + +/* I2S_TX_FIFO_MOD_FORCE_EN : R/W; bitpos: [19]; default: 0; + * The bit should always be set to 1 + */ + +#define I2S_TX_FIFO_MOD_FORCE_EN (BIT(19)) +#define I2S_TX_FIFO_MOD_FORCE_EN_M (I2S_TX_FIFO_MOD_FORCE_EN_V << I2S_TX_FIFO_MOD_FORCE_EN_S) +#define I2S_TX_FIFO_MOD_FORCE_EN_V 0x00000001 +#define I2S_TX_FIFO_MOD_FORCE_EN_S 19 + +/* I2S_RX_FIFO_MOD : R/W; bitpos: [18:16]; default: 0; + * Receiver FIFO mode configuration bits + */ + +#define I2S_RX_FIFO_MOD 0x00000007 +#define I2S_RX_FIFO_MOD_M (I2S_RX_FIFO_MOD_V << I2S_RX_FIFO_MOD_S) +#define I2S_RX_FIFO_MOD_V 0x00000007 +#define I2S_RX_FIFO_MOD_S 16 + +/* I2S_TX_FIFO_MOD : R/W; bitpos: [15:13]; default: 0; + * Transmitter FIFO mode configuration bits + */ + +#define I2S_TX_FIFO_MOD 0x00000007 +#define I2S_TX_FIFO_MOD_M (I2S_TX_FIFO_MOD_V << I2S_TX_FIFO_MOD_S) +#define I2S_TX_FIFO_MOD_V 0x00000007 +#define I2S_TX_FIFO_MOD_S 13 + +/* I2S_DSCR_EN : R/W; bitpos: [12]; default: 1; + * Set this bit to enable I2S DMA mode + */ + +#define I2S_DSCR_EN (BIT(12)) +#define I2S_DSCR_EN_M (I2S_DSCR_EN_V << I2S_DSCR_EN_S) +#define I2S_DSCR_EN_V 0x00000001 +#define I2S_DSCR_EN_S 12 + +/* I2S_TX_DATA_NUM : R/W; bitpos: [11:6]; default: 32; + * Threshold of data length in transmitter FIFO + */ + +#define I2S_TX_DATA_NUM 0x0000003F +#define I2S_TX_DATA_NUM_M (I2S_TX_DATA_NUM_V << I2S_TX_DATA_NUM_S) +#define I2S_TX_DATA_NUM_V 0x0000003F +#define I2S_TX_DATA_NUM_S 6 + +/* I2S_RX_DATA_NUM : R/W; bitpos: [5:0]; default: 32; + * Threshold of data length in receiver FIFO + */ + +#define I2S_RX_DATA_NUM 0x0000003F +#define I2S_RX_DATA_NUM_M (I2S_RX_DATA_NUM_V << I2S_RX_DATA_NUM_S) +#define I2S_RX_DATA_NUM_V 0x0000003F +#define I2S_RX_DATA_NUM_S 0 + +/* I2S_RXEOF_NUM_REG register + * I2S DMA RX EOF data length + */ + +#define I2S_RXEOF_NUM_REG (DR_REG_I2S_BASE + 0x24) + +/* I2S_RX_EOF_NUM : R/W; bitpos: [31:0]; default: 64; + * the length of data to be received. It will trigger i2s_in_suc_eof_int. + */ + +#define I2S_RX_EOF_NUM 0xFFFFFFFF +#define I2S_RX_EOF_NUM_M (I2S_RX_EOF_NUM_V << I2S_RX_EOF_NUM_S) +#define I2S_RX_EOF_NUM_V 0xFFFFFFFF +#define I2S_RX_EOF_NUM_S 0 + +/* I2S_CONF_SIGLE_DATA_REG register + * Constant single channel data + */ + +#define I2S_CONF_SIGLE_DATA_REG (DR_REG_I2S_BASE + 0x28) + +/* I2S_SIGLE_DATA : R/W; bitpos: [31:0]; default: 0; + * the right channel or left channel put out constant value stored in this + * register according to tx_chan_mod and reg_tx_msb_right + */ + +#define I2S_SIGLE_DATA 0xFFFFFFFF +#define I2S_SIGLE_DATA_M (I2S_SIGLE_DATA_V << I2S_SIGLE_DATA_S) +#define I2S_SIGLE_DATA_V 0xFFFFFFFF +#define I2S_SIGLE_DATA_S 0 + +/* I2S_CONF_CHAN_REG register + * I2S channel configure register + */ + +#define I2S_CONF_CHAN_REG (DR_REG_I2S_BASE + 0x2c) + +/* I2S_RX_CHAN_MOD : R/W; bitpos: [4:3]; default: 0; + * I2S receiver channel mode configuration bits. + */ + +#define I2S_RX_CHAN_MOD 0x00000003 +#define I2S_RX_CHAN_MOD_M (I2S_RX_CHAN_MOD_V << I2S_RX_CHAN_MOD_S) +#define I2S_RX_CHAN_MOD_V 0x00000003 +#define I2S_RX_CHAN_MOD_S 3 + +/* I2S_TX_CHAN_MOD : R/W; bitpos: [2:0]; default: 0; + * I2S transmitter channel mode configuration bits. + */ + +#define I2S_TX_CHAN_MOD 0x00000007 +#define I2S_TX_CHAN_MOD_M (I2S_TX_CHAN_MOD_V << I2S_TX_CHAN_MOD_S) +#define I2S_TX_CHAN_MOD_V 0x00000007 +#define I2S_TX_CHAN_MOD_S 0 + +/* I2S_OUT_LINK_REG register + * I2S DMA TX configure register + */ + +#define I2S_OUT_LINK_REG (DR_REG_I2S_BASE + 0x30) + +/* I2S_OUTLINK_PARK : RO; bitpos: [31]; default: 0; */ + +#define I2S_OUTLINK_PARK (BIT(31)) +#define I2S_OUTLINK_PARK_M (I2S_OUTLINK_PARK_V << I2S_OUTLINK_PARK_S) +#define I2S_OUTLINK_PARK_V 0x00000001 +#define I2S_OUTLINK_PARK_S 31 + +/* I2S_OUTLINK_RESTART : R/W; bitpos: [30]; default: 0; + * Set this bit to restart outlink descriptor + */ + +#define I2S_OUTLINK_RESTART (BIT(30)) +#define I2S_OUTLINK_RESTART_M (I2S_OUTLINK_RESTART_V << I2S_OUTLINK_RESTART_S) +#define I2S_OUTLINK_RESTART_V 0x00000001 +#define I2S_OUTLINK_RESTART_S 30 + +/* I2S_OUTLINK_START : R/W; bitpos: [29]; default: 0; + * Set this bit to start outlink descriptor + */ + +#define I2S_OUTLINK_START (BIT(29)) +#define I2S_OUTLINK_START_M (I2S_OUTLINK_START_V << I2S_OUTLINK_START_S) +#define I2S_OUTLINK_START_V 0x00000001 +#define I2S_OUTLINK_START_S 29 + +/* I2S_OUTLINK_STOP : R/W; bitpos: [28]; default: 0; + * Set this bit to stop outlink descriptor + */ + +#define I2S_OUTLINK_STOP (BIT(28)) +#define I2S_OUTLINK_STOP_M (I2S_OUTLINK_STOP_V << I2S_OUTLINK_STOP_S) +#define I2S_OUTLINK_STOP_V 0x00000001 +#define I2S_OUTLINK_STOP_S 28 + +/* I2S_OUTLINK_ADDR : R/W; bitpos: [19:0]; default: 0; + * The address of first outlink descriptor + */ + +#define I2S_OUTLINK_ADDR 0x000FFFFF +#define I2S_OUTLINK_ADDR_M (I2S_OUTLINK_ADDR_V << I2S_OUTLINK_ADDR_S) +#define I2S_OUTLINK_ADDR_V 0x000FFFFF +#define I2S_OUTLINK_ADDR_S 0 + +/* I2S_IN_LINK_REG register + * I2S DMA RX configure register + */ + +#define I2S_IN_LINK_REG (DR_REG_I2S_BASE + 0x34) + +/* I2S_INLINK_PARK : RO; bitpos: [31]; default: 0; */ + +#define I2S_INLINK_PARK (BIT(31)) +#define I2S_INLINK_PARK_M (I2S_INLINK_PARK_V << I2S_INLINK_PARK_S) +#define I2S_INLINK_PARK_V 0x00000001 +#define I2S_INLINK_PARK_S 31 + +/* I2S_INLINK_RESTART : R/W; bitpos: [30]; default: 0; + * Set this bit to restart inlink descriptor + */ + +#define I2S_INLINK_RESTART (BIT(30)) +#define I2S_INLINK_RESTART_M (I2S_INLINK_RESTART_V << I2S_INLINK_RESTART_S) +#define I2S_INLINK_RESTART_V 0x00000001 +#define I2S_INLINK_RESTART_S 30 + +/* I2S_INLINK_START : R/W; bitpos: [29]; default: 0; + * Set this bit to start inlink descriptor + */ + +#define I2S_INLINK_START (BIT(29)) +#define I2S_INLINK_START_M (I2S_INLINK_START_V << I2S_INLINK_START_S) +#define I2S_INLINK_START_V 0x00000001 +#define I2S_INLINK_START_S 29 + +/* I2S_INLINK_STOP : R/W; bitpos: [28]; default: 0; + * Set this bit to stop inlink descriptor + */ + +#define I2S_INLINK_STOP (BIT(28)) +#define I2S_INLINK_STOP_M (I2S_INLINK_STOP_V << I2S_INLINK_STOP_S) +#define I2S_INLINK_STOP_V 0x00000001 +#define I2S_INLINK_STOP_S 28 + +/* I2S_INLINK_ADDR : R/W; bitpos: [19:0]; default: 0; + * The address of first inlink descriptor + */ + +#define I2S_INLINK_ADDR 0x000FFFFF +#define I2S_INLINK_ADDR_M (I2S_INLINK_ADDR_V << I2S_INLINK_ADDR_S) +#define I2S_INLINK_ADDR_V 0x000FFFFF +#define I2S_INLINK_ADDR_S 0 + +/* I2S_OUT_EOF_DES_ADDR_REG register + * The address of outlink descriptor that produces EOF + */ + +#define I2S_OUT_EOF_DES_ADDR_REG (DR_REG_I2S_BASE + 0x38) + +/* I2S_OUT_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The address of outlink descriptor that produces EOF + */ + +#define I2S_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define I2S_OUT_EOF_DES_ADDR_M (I2S_OUT_EOF_DES_ADDR_V << I2S_OUT_EOF_DES_ADDR_S) +#define I2S_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define I2S_OUT_EOF_DES_ADDR_S 0 + +/* I2S_IN_EOF_DES_ADDR_REG register + * The address of inlink descriptor that produces EOF + */ + +#define I2S_IN_EOF_DES_ADDR_REG (DR_REG_I2S_BASE + 0x3c) + +/* I2S_IN_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The address of inlink descriptor that produces EOF + */ + +#define I2S_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define I2S_IN_SUC_EOF_DES_ADDR_M (I2S_IN_SUC_EOF_DES_ADDR_V << I2S_IN_SUC_EOF_DES_ADDR_S) +#define I2S_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define I2S_IN_SUC_EOF_DES_ADDR_S 0 + +/* I2S_OUT_EOF_BFR_DES_ADDR_REG register + * The address of buffer relative to the outlink descriptor that produces EOF + */ + +#define I2S_OUT_EOF_BFR_DES_ADDR_REG (DR_REG_I2S_BASE + 0x40) + +/* I2S_OUT_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The address of buffer relative to the outlink descriptor that produces EOF + */ + +#define I2S_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define I2S_OUT_EOF_BFR_DES_ADDR_M (I2S_OUT_EOF_BFR_DES_ADDR_V << I2S_OUT_EOF_BFR_DES_ADDR_S) +#define I2S_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define I2S_OUT_EOF_BFR_DES_ADDR_S 0 + +/* I2S_INLINK_DSCR_REG register + * The address of current inlink descriptor + */ + +#define I2S_INLINK_DSCR_REG (DR_REG_I2S_BASE + 0x48) + +/* I2S_INLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * The address of current inlink descriptor + */ + +#define I2S_INLINK_DSCR 0xFFFFFFFF +#define I2S_INLINK_DSCR_M (I2S_INLINK_DSCR_V << I2S_INLINK_DSCR_S) +#define I2S_INLINK_DSCR_V 0xFFFFFFFF +#define I2S_INLINK_DSCR_S 0 + +/* I2S_INLINK_DSCR_BF0_REG register + * The address of next inlink descriptor + */ + +#define I2S_INLINK_DSCR_BF0_REG (DR_REG_I2S_BASE + 0x4c) + +/* I2S_INLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * The address of next inlink descriptor + */ + +#define I2S_INLINK_DSCR_BF0 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF0_M (I2S_INLINK_DSCR_BF0_V << I2S_INLINK_DSCR_BF0_S) +#define I2S_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF0_S 0 + +/* I2S_INLINK_DSCR_BF1_REG register + * The address of next inlink data buffer + */ + +#define I2S_INLINK_DSCR_BF1_REG (DR_REG_I2S_BASE + 0x50) + +/* I2S_INLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * The address of next inlink data buffer + */ + +#define I2S_INLINK_DSCR_BF1 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF1_M (I2S_INLINK_DSCR_BF1_V << I2S_INLINK_DSCR_BF1_S) +#define I2S_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define I2S_INLINK_DSCR_BF1_S 0 + +/* I2S_OUTLINK_DSCR_REG register + * The address of current outlink descriptor + */ + +#define I2S_OUTLINK_DSCR_REG (DR_REG_I2S_BASE + 0x54) + +/* I2S_OUTLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * The address of current outlink descriptor + */ + +#define I2S_OUTLINK_DSCR 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_M (I2S_OUTLINK_DSCR_V << I2S_OUTLINK_DSCR_S) +#define I2S_OUTLINK_DSCR_V 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_S 0 + +/* I2S_OUTLINK_DSCR_BF0_REG register + * The address of next outlink descriptor + */ + +#define I2S_OUTLINK_DSCR_BF0_REG (DR_REG_I2S_BASE + 0x58) + +/* I2S_OUTLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * The address of next outlink descriptor + */ + +#define I2S_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF0_M (I2S_OUTLINK_DSCR_BF0_V << I2S_OUTLINK_DSCR_BF0_S) +#define I2S_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF0_S 0 + +/* I2S_OUTLINK_DSCR_BF1_REG register + * The address of next outlink data buffer + */ + +#define I2S_OUTLINK_DSCR_BF1_REG (DR_REG_I2S_BASE + 0x5c) + +/* I2S_OUTLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * The address of next outlink data buffer + */ + +#define I2S_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF1_M (I2S_OUTLINK_DSCR_BF1_V << I2S_OUTLINK_DSCR_BF1_S) +#define I2S_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define I2S_OUTLINK_DSCR_BF1_S 0 + +/* I2S_LC_CONF_REG register + * I2S DMA configuration register + */ + +#define I2S_LC_CONF_REG (DR_REG_I2S_BASE + 0x60) + +/* I2S_EXT_MEM_BK_SIZE : R/W; bitpos: [15:14]; default: 0; + * DMA access external memory block size. 0: 16 bytes 1: 32 bytes + * 2:64 bytes 3:reserved + */ + +#define I2S_EXT_MEM_BK_SIZE 0x00000003 +#define I2S_EXT_MEM_BK_SIZE_M (I2S_EXT_MEM_BK_SIZE_V << I2S_EXT_MEM_BK_SIZE_S) +#define I2S_EXT_MEM_BK_SIZE_V 0x00000003 +#define I2S_EXT_MEM_BK_SIZE_S 14 + +/* I2S_MEM_TRANS_EN : R/W; bitpos: [13]; default: 0; + * don't use + */ + +#define I2S_MEM_TRANS_EN (BIT(13)) +#define I2S_MEM_TRANS_EN_M (I2S_MEM_TRANS_EN_V << I2S_MEM_TRANS_EN_S) +#define I2S_MEM_TRANS_EN_V 0x00000001 +#define I2S_MEM_TRANS_EN_S 13 + +/* I2S_CHECK_OWNER : R/W; bitpos: [12]; default: 0; + * Set this bit to enable check owner bit by hardware + */ + +#define I2S_CHECK_OWNER (BIT(12)) +#define I2S_CHECK_OWNER_M (I2S_CHECK_OWNER_V << I2S_CHECK_OWNER_S) +#define I2S_CHECK_OWNER_V 0x00000001 +#define I2S_CHECK_OWNER_S 12 + +/* I2S_OUT_DATA_BURST_EN : R/W; bitpos: [11]; default: 0; + * Transmitter data transfer mode configuration bit. 1: to prepare out data + * with burst mode 0: to prepare out data with byte mode + */ + +#define I2S_OUT_DATA_BURST_EN (BIT(11)) +#define I2S_OUT_DATA_BURST_EN_M (I2S_OUT_DATA_BURST_EN_V << I2S_OUT_DATA_BURST_EN_S) +#define I2S_OUT_DATA_BURST_EN_V 0x00000001 +#define I2S_OUT_DATA_BURST_EN_S 11 + +/* I2S_INDSCR_BURST_EN : R/W; bitpos: [10]; default: 0; + * DMA inlink descriptor transfer mode configuration bit. 1: to prepare + * inlink descriptor with burst mode 0: to prepare inlink descriptor with + * byte mode + */ + +#define I2S_INDSCR_BURST_EN (BIT(10)) +#define I2S_INDSCR_BURST_EN_M (I2S_INDSCR_BURST_EN_V << I2S_INDSCR_BURST_EN_S) +#define I2S_INDSCR_BURST_EN_V 0x00000001 +#define I2S_INDSCR_BURST_EN_S 10 + +/* I2S_OUTDSCR_BURST_EN : R/W; bitpos: [9]; default: 0; + * DMA outlink descriptor transfer mode configuration bit. 1: to prepare + * outlink descriptor with burst mode 0: to prepare outlink descriptor + * with byte mode + */ + +#define I2S_OUTDSCR_BURST_EN (BIT(9)) +#define I2S_OUTDSCR_BURST_EN_M (I2S_OUTDSCR_BURST_EN_V << I2S_OUTDSCR_BURST_EN_S) +#define I2S_OUTDSCR_BURST_EN_V 0x00000001 +#define I2S_OUTDSCR_BURST_EN_S 9 + +/* I2S_OUT_EOF_MODE : R/W; bitpos: [8]; default: 1; + * DMA out EOF flag generation mode . 1: when dma has popped all data from + * the FIFO 0:when ahb has pushed all data to the FIFO + */ + +#define I2S_OUT_EOF_MODE (BIT(8)) +#define I2S_OUT_EOF_MODE_M (I2S_OUT_EOF_MODE_V << I2S_OUT_EOF_MODE_S) +#define I2S_OUT_EOF_MODE_V 0x00000001 +#define I2S_OUT_EOF_MODE_S 8 + +/* I2S_OUT_NO_RESTART_CLR : R/W; bitpos: [7]; default: 0; + * don't use + */ + +#define I2S_OUT_NO_RESTART_CLR (BIT(7)) +#define I2S_OUT_NO_RESTART_CLR_M (I2S_OUT_NO_RESTART_CLR_V << I2S_OUT_NO_RESTART_CLR_S) +#define I2S_OUT_NO_RESTART_CLR_V 0x00000001 +#define I2S_OUT_NO_RESTART_CLR_S 7 + +/* I2S_OUT_AUTO_WRBACK : R/W; bitpos: [6]; default: 0; + * Set this bit to enable outlink-written-back automatically when out buffer + * is transmitted done. + */ + +#define I2S_OUT_AUTO_WRBACK (BIT(6)) +#define I2S_OUT_AUTO_WRBACK_M (I2S_OUT_AUTO_WRBACK_V << I2S_OUT_AUTO_WRBACK_S) +#define I2S_OUT_AUTO_WRBACK_V 0x00000001 +#define I2S_OUT_AUTO_WRBACK_S 6 + +/* I2S_IN_LOOP_TEST : R/W; bitpos: [5]; default: 0; + * Set this bit to loop test outlink + */ + +#define I2S_IN_LOOP_TEST (BIT(5)) +#define I2S_IN_LOOP_TEST_M (I2S_IN_LOOP_TEST_V << I2S_IN_LOOP_TEST_S) +#define I2S_IN_LOOP_TEST_V 0x00000001 +#define I2S_IN_LOOP_TEST_S 5 + +/* I2S_OUT_LOOP_TEST : R/W; bitpos: [4]; default: 0; + * Set this bit to loop test inlink + */ + +#define I2S_OUT_LOOP_TEST (BIT(4)) +#define I2S_OUT_LOOP_TEST_M (I2S_OUT_LOOP_TEST_V << I2S_OUT_LOOP_TEST_S) +#define I2S_OUT_LOOP_TEST_V 0x00000001 +#define I2S_OUT_LOOP_TEST_S 4 + +/* I2S_AHBM_RST : R/W; bitpos: [3]; default: 0; + * Set this bit to reset ahb interface of DMA + */ + +#define I2S_AHBM_RST (BIT(3)) +#define I2S_AHBM_RST_M (I2S_AHBM_RST_V << I2S_AHBM_RST_S) +#define I2S_AHBM_RST_V 0x00000001 +#define I2S_AHBM_RST_S 3 + +/* I2S_AHBM_FIFO_RST : R/W; bitpos: [2]; default: 0; + * Set this bit to reset ahb interface cmdFIFO of DMA + */ + +#define I2S_AHBM_FIFO_RST (BIT(2)) +#define I2S_AHBM_FIFO_RST_M (I2S_AHBM_FIFO_RST_V << I2S_AHBM_FIFO_RST_S) +#define I2S_AHBM_FIFO_RST_V 0x00000001 +#define I2S_AHBM_FIFO_RST_S 2 + +/* I2S_OUT_RST : R/W; bitpos: [1]; default: 0; + * Set this bit to reset out dma FSM + */ + +#define I2S_OUT_RST (BIT(1)) +#define I2S_OUT_RST_M (I2S_OUT_RST_V << I2S_OUT_RST_S) +#define I2S_OUT_RST_V 0x00000001 +#define I2S_OUT_RST_S 1 + +/* I2S_IN_RST : R/W; bitpos: [0]; default: 0; + * Set this bit to reset in dma FSM + */ + +#define I2S_IN_RST (BIT(0)) +#define I2S_IN_RST_M (I2S_IN_RST_V << I2S_IN_RST_S) +#define I2S_IN_RST_V 0x00000001 +#define I2S_IN_RST_S 0 + +/* I2S_OUTFIFO_PUSH_REG register + * APB out FIFO mode register + */ + +#define I2S_OUTFIFO_PUSH_REG (DR_REG_I2S_BASE + 0x64) + +/* I2S_OUTFIFO_PUSH : R/W; bitpos: [16]; default: 0; + * APB out FIFO push. + */ + +#define I2S_OUTFIFO_PUSH (BIT(16)) +#define I2S_OUTFIFO_PUSH_M (I2S_OUTFIFO_PUSH_V << I2S_OUTFIFO_PUSH_S) +#define I2S_OUTFIFO_PUSH_V 0x00000001 +#define I2S_OUTFIFO_PUSH_S 16 + +/* I2S_OUTFIFO_WDATA : R/W; bitpos: [8:0]; default: 0; + * APB out FIFO write data. + */ + +#define I2S_OUTFIFO_WDATA 0x000001FF +#define I2S_OUTFIFO_WDATA_M (I2S_OUTFIFO_WDATA_V << I2S_OUTFIFO_WDATA_S) +#define I2S_OUTFIFO_WDATA_V 0x000001FF +#define I2S_OUTFIFO_WDATA_S 0 + +/* I2S_INFIFO_POP_REG register + * APB in FIFO mode register + */ + +#define I2S_INFIFO_POP_REG (DR_REG_I2S_BASE + 0x68) + +/* I2S_INFIFO_POP : R/W; bitpos: [16]; default: 0; + * APB in FIFO pop. + */ + +#define I2S_INFIFO_POP (BIT(16)) +#define I2S_INFIFO_POP_M (I2S_INFIFO_POP_V << I2S_INFIFO_POP_S) +#define I2S_INFIFO_POP_V 0x00000001 +#define I2S_INFIFO_POP_S 16 + +/* I2S_INFIFO_RDATA : RO; bitpos: [11:0]; default: 0; + * APB in FIFO read data. + */ + +#define I2S_INFIFO_RDATA 0x00000FFF +#define I2S_INFIFO_RDATA_M (I2S_INFIFO_RDATA_V << I2S_INFIFO_RDATA_S) +#define I2S_INFIFO_RDATA_V 0x00000FFF +#define I2S_INFIFO_RDATA_S 0 + +/* I2S_LC_STATE0_REG register + * I2S DMA TX status + */ + +#define I2S_LC_STATE0_REG (DR_REG_I2S_BASE + 0x6c) + +/* I2S_OUT_EMPTY : RO; bitpos: [31]; default: 0; + * I2S DMA outfifo is empty. + */ + +#define I2S_OUT_EMPTY (BIT(31)) +#define I2S_OUT_EMPTY_M (I2S_OUT_EMPTY_V << I2S_OUT_EMPTY_S) +#define I2S_OUT_EMPTY_V 0x00000001 +#define I2S_OUT_EMPTY_S 31 + +/* I2S_OUT_FULL : RO; bitpos: [30]; default: 0; + * I2S DMA outfifo is full. + */ + +#define I2S_OUT_FULL (BIT(30)) +#define I2S_OUT_FULL_M (I2S_OUT_FULL_V << I2S_OUT_FULL_S) +#define I2S_OUT_FULL_V 0x00000001 +#define I2S_OUT_FULL_S 30 + +/* I2S_OUTFIFO_CNT : RO; bitpos: [29:23]; default: 0; + * The remains of I2S DMA outfifo data. + */ + +#define I2S_OUTFIFO_CNT 0x0000007F +#define I2S_OUTFIFO_CNT_M (I2S_OUTFIFO_CNT_V << I2S_OUTFIFO_CNT_S) +#define I2S_OUTFIFO_CNT_V 0x0000007F +#define I2S_OUTFIFO_CNT_S 23 + +/* I2S_OUT_STATE : RO; bitpos: [22:20]; default: 0; + * I2S DMA out data state. + */ + +#define I2S_OUT_STATE 0x00000007 +#define I2S_OUT_STATE_M (I2S_OUT_STATE_V << I2S_OUT_STATE_S) +#define I2S_OUT_STATE_V 0x00000007 +#define I2S_OUT_STATE_S 20 + +/* I2S_OUT_DSCR_STATE : RO; bitpos: [19:18]; default: 0; + * I2S DMA out descriptor state. + */ + +#define I2S_OUT_DSCR_STATE 0x00000003 +#define I2S_OUT_DSCR_STATE_M (I2S_OUT_DSCR_STATE_V << I2S_OUT_DSCR_STATE_S) +#define I2S_OUT_DSCR_STATE_V 0x00000003 +#define I2S_OUT_DSCR_STATE_S 18 + +/* I2S_OUTLINK_DSCR_ADDR : RO; bitpos: [17:0]; default: 0; + * I2S DMA out descriptor address. + */ + +#define I2S_OUTLINK_DSCR_ADDR 0x0003FFFF +#define I2S_OUTLINK_DSCR_ADDR_M (I2S_OUTLINK_DSCR_ADDR_V << I2S_OUTLINK_DSCR_ADDR_S) +#define I2S_OUTLINK_DSCR_ADDR_V 0x0003FFFF +#define I2S_OUTLINK_DSCR_ADDR_S 0 + +/* I2S_LC_STATE1_REG register + * I2S DMA RX status + */ + +#define I2S_LC_STATE1_REG (DR_REG_I2S_BASE + 0x70) + +/* I2S_IN_EMPTY : RO; bitpos: [31]; default: 0; + * I2S DMA infifo is empty. + */ + +#define I2S_IN_EMPTY (BIT(31)) +#define I2S_IN_EMPTY_M (I2S_IN_EMPTY_V << I2S_IN_EMPTY_S) +#define I2S_IN_EMPTY_V 0x00000001 +#define I2S_IN_EMPTY_S 31 + +/* I2S_IN_FULL : RO; bitpos: [30]; default: 0; + * I2S DMA infifo is full. + */ + +#define I2S_IN_FULL (BIT(30)) +#define I2S_IN_FULL_M (I2S_IN_FULL_V << I2S_IN_FULL_S) +#define I2S_IN_FULL_V 0x00000001 +#define I2S_IN_FULL_S 30 + +/* I2S_INFIFO_CNT_DEBUG : RO; bitpos: [29:23]; default: 0; + * The remains of I2S DMA infifo data. + */ + +#define I2S_INFIFO_CNT_DEBUG 0x0000007F +#define I2S_INFIFO_CNT_DEBUG_M (I2S_INFIFO_CNT_DEBUG_V << I2S_INFIFO_CNT_DEBUG_S) +#define I2S_INFIFO_CNT_DEBUG_V 0x0000007F +#define I2S_INFIFO_CNT_DEBUG_S 23 + +/* I2S_IN_STATE : RO; bitpos: [22:20]; default: 0; + * I2S DMA in data state. + */ + +#define I2S_IN_STATE 0x00000007 +#define I2S_IN_STATE_M (I2S_IN_STATE_V << I2S_IN_STATE_S) +#define I2S_IN_STATE_V 0x00000007 +#define I2S_IN_STATE_S 20 + +/* I2S_IN_DSCR_STATE : RO; bitpos: [19:18]; default: 0; + * I2S DMA in descriptor state. + */ + +#define I2S_IN_DSCR_STATE 0x00000003 +#define I2S_IN_DSCR_STATE_M (I2S_IN_DSCR_STATE_V << I2S_IN_DSCR_STATE_S) +#define I2S_IN_DSCR_STATE_V 0x00000003 +#define I2S_IN_DSCR_STATE_S 18 + +/* I2S_INLINK_DSCR_ADDR : RO; bitpos: [17:0]; default: 0; + * I2S DMA in descriptor address. + */ + +#define I2S_INLINK_DSCR_ADDR 0x0003FFFF +#define I2S_INLINK_DSCR_ADDR_M (I2S_INLINK_DSCR_ADDR_V << I2S_INLINK_DSCR_ADDR_S) +#define I2S_INLINK_DSCR_ADDR_V 0x0003FFFF +#define I2S_INLINK_DSCR_ADDR_S 0 + +/* I2S_LC_HUNG_CONF_REG register + * I2S Hung configure register + */ + +#define I2S_LC_HUNG_CONF_REG (DR_REG_I2S_BASE + 0x74) + +/* I2S_LC_FIFO_TIMEOUT_ENA : R/W; bitpos: [11]; default: 1; + * The enable bit for FIFO timeout + */ + +#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_M (I2S_LC_FIFO_TIMEOUT_ENA_V << I2S_LC_FIFO_TIMEOUT_ENA_S) +#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x00000001 +#define I2S_LC_FIFO_TIMEOUT_ENA_S 11 + +/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W; bitpos: [10:8]; default: 0; + * The bits are used to scale tick counter threshold. The tick counter is + * reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + */ + +#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007 +#define I2S_LC_FIFO_TIMEOUT_SHIFT_M (I2S_LC_FIFO_TIMEOUT_SHIFT_V << I2S_LC_FIFO_TIMEOUT_SHIFT_S) +#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x00000007 +#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 + +/* I2S_LC_FIFO_TIMEOUT : R/W; bitpos: [7:0]; default: 16; + * the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be + * triggered when fifo hung counter is equal to this value + */ + +#define I2S_LC_FIFO_TIMEOUT 0x000000FF +#define I2S_LC_FIFO_TIMEOUT_M (I2S_LC_FIFO_TIMEOUT_V << I2S_LC_FIFO_TIMEOUT_S) +#define I2S_LC_FIFO_TIMEOUT_V 0x000000FF +#define I2S_LC_FIFO_TIMEOUT_S 0 + +/* I2S_CONF1 _REG register + * I2S configure1 register + */ + +#define I2S_CONF1 _REG (DR_REG_I2S_BASE + 0xa0) + +/* I2S_TX_ZEROS_RM_EN : R/W; bitpos: [9]; default: 0; + * don't use + */ + +#define I2S_TX_ZEROS_RM_EN (BIT(9)) +#define I2S_TX_ZEROS_RM_EN_M (I2S_TX_ZEROS_RM_EN_V << I2S_TX_ZEROS_RM_EN_S) +#define I2S_TX_ZEROS_RM_EN_V 0x00000001 +#define I2S_TX_ZEROS_RM_EN_S 9 + +/* I2S_TX_STOP_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to stop disable output BCK signal and WS signal when tx FIFO + * is emtpy + */ + +#define I2S_TX_STOP_EN (BIT(8)) +#define I2S_TX_STOP_EN_M (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S) +#define I2S_TX_STOP_EN_V 0x00000001 +#define I2S_TX_STOP_EN_S 8 + +/* I2S_RX_PCM_BYPASS : R/W; bitpos: [7]; default: 1; + * Set this bit to bypass Compress/Decompress module for received data. + */ + +#define I2S_RX_PCM_BYPASS (BIT(7)) +#define I2S_RX_PCM_BYPASS_M (I2S_RX_PCM_BYPASS_V << I2S_RX_PCM_BYPASS_S) +#define I2S_RX_PCM_BYPASS_V 0x00000001 +#define I2S_RX_PCM_BYPASS_S 7 + +/* I2S_RX_PCM_CONF : R/W; bitpos: [6:4]; default: 0; + * Compress/Decompress module configuration bits. 0: decompress received + * data 1:compress received data + */ + +#define I2S_RX_PCM_CONF 0x00000007 +#define I2S_RX_PCM_CONF_M (I2S_RX_PCM_CONF_V << I2S_RX_PCM_CONF_S) +#define I2S_RX_PCM_CONF_V 0x00000007 +#define I2S_RX_PCM_CONF_S 4 + +/* I2S_TX_PCM_BYPASS : R/W; bitpos: [3]; default: 1; + * Set this bit to bypass Compress/Decompress module for transmitted data. + */ + +#define I2S_TX_PCM_BYPASS (BIT(3)) +#define I2S_TX_PCM_BYPASS_M (I2S_TX_PCM_BYPASS_V << I2S_TX_PCM_BYPASS_S) +#define I2S_TX_PCM_BYPASS_V 0x00000001 +#define I2S_TX_PCM_BYPASS_S 3 + +/* I2S_TX_PCM_CONF : R/W; bitpos: [2:0]; default: 1; + * Compress/Decompress module configuration bits. 0: decompress transmitted + * data 1:compress transmitted data + */ + +#define I2S_TX_PCM_CONF 0x00000007 +#define I2S_TX_PCM_CONF_M (I2S_TX_PCM_CONF_V << I2S_TX_PCM_CONF_S) +#define I2S_TX_PCM_CONF_V 0x00000007 +#define I2S_TX_PCM_CONF_S 0 + +/* I2S_PD_CONF_REG register + * I2S power down configure register + */ + +#define I2S_PD_CONF_REG (DR_REG_I2S_BASE + 0xa4) + +/* I2S_DMA_RAM_CLK_FO : R/W; bitpos: [6]; default: 0; + * Set this bit to force on the DMA ram clock. + */ + +#define I2S_DMA_RAM_CLK_FO (BIT(6)) +#define I2S_DMA_RAM_CLK_FO_M (I2S_DMA_RAM_CLK_FO_V << I2S_DMA_RAM_CLK_FO_S) +#define I2S_DMA_RAM_CLK_FO_V 0x00000001 +#define I2S_DMA_RAM_CLK_FO_S 6 + +/* I2S_DMA_RAM_FORCE_PU : R/W; bitpos: [5]; default: 1; + * Force DMA FIFO power-up + */ + +#define I2S_DMA_RAM_FORCE_PU (BIT(5)) +#define I2S_DMA_RAM_FORCE_PU_M (I2S_DMA_RAM_FORCE_PU_V << I2S_DMA_RAM_FORCE_PU_S) +#define I2S_DMA_RAM_FORCE_PU_V 0x00000001 +#define I2S_DMA_RAM_FORCE_PU_S 5 + +/* I2S_DMA_RAM_FORCE_PD : R/W; bitpos: [4]; default: 0; + * Force DMA FIFO power-down + */ + +#define I2S_DMA_RAM_FORCE_PD (BIT(4)) +#define I2S_DMA_RAM_FORCE_PD_M (I2S_DMA_RAM_FORCE_PD_V << I2S_DMA_RAM_FORCE_PD_S) +#define I2S_DMA_RAM_FORCE_PD_V 0x00000001 +#define I2S_DMA_RAM_FORCE_PD_S 4 + +/* I2S_PLC_MEM_FORCE_PU : R/W; bitpos: [3]; default: 1; + * Force I2S memory power-up + */ + +#define I2S_PLC_MEM_FORCE_PU (BIT(3)) +#define I2S_PLC_MEM_FORCE_PU_M (I2S_PLC_MEM_FORCE_PU_V << I2S_PLC_MEM_FORCE_PU_S) +#define I2S_PLC_MEM_FORCE_PU_V 0x00000001 +#define I2S_PLC_MEM_FORCE_PU_S 3 + +/* I2S_PLC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Force I2S memory power-down + */ + +#define I2S_PLC_MEM_FORCE_PD (BIT(2)) +#define I2S_PLC_MEM_FORCE_PD_M (I2S_PLC_MEM_FORCE_PD_V << I2S_PLC_MEM_FORCE_PD_S) +#define I2S_PLC_MEM_FORCE_PD_V 0x00000001 +#define I2S_PLC_MEM_FORCE_PD_S 2 + +/* I2S_FIFO_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Force FIFO power-up + */ + +#define I2S_FIFO_FORCE_PU (BIT(1)) +#define I2S_FIFO_FORCE_PU_M (I2S_FIFO_FORCE_PU_V << I2S_FIFO_FORCE_PU_S) +#define I2S_FIFO_FORCE_PU_V 0x00000001 +#define I2S_FIFO_FORCE_PU_S 1 + +/* I2S_FIFO_FORCE_PD : R/W; bitpos: [0]; default: 0; + * Force FIFO power-down + */ + +#define I2S_FIFO_FORCE_PD (BIT(0)) +#define I2S_FIFO_FORCE_PD_M (I2S_FIFO_FORCE_PD_V << I2S_FIFO_FORCE_PD_S) +#define I2S_FIFO_FORCE_PD_V 0x00000001 +#define I2S_FIFO_FORCE_PD_S 0 + +/* I2S_CONF2_REG register + * I2S configure2 register + */ + +#define I2S_CONF2_REG (DR_REG_I2S_BASE + 0xa8) + +/* I2S_VSYNC_FILTER_THRES : R/W; bitpos: [13:11]; default: 0; + * Configure the I2S VSYNC filter threshold value + */ + +#define I2S_VSYNC_FILTER_THRES 0x00000007 +#define I2S_VSYNC_FILTER_THRES_M (I2S_VSYNC_FILTER_THRES_V << I2S_VSYNC_FILTER_THRES_S) +#define I2S_VSYNC_FILTER_THRES_V 0x00000007 +#define I2S_VSYNC_FILTER_THRES_S 11 + +/* I2S_VSYNC_FILTER_EN : R/W; bitpos: [10]; default: 0; + * Set this bit to enable I2S VSYNC filter function. + */ + +#define I2S_VSYNC_FILTER_EN (BIT(10)) +#define I2S_VSYNC_FILTER_EN_M (I2S_VSYNC_FILTER_EN_V << I2S_VSYNC_FILTER_EN_S) +#define I2S_VSYNC_FILTER_EN_V 0x00000001 +#define I2S_VSYNC_FILTER_EN_S 10 + +/* I2S_CAM_CLK_LOOPBACK : R/W; bitpos: [9]; default: 0; + * Set this bit to loopback cam_clk from i2s_rx + */ + +#define I2S_CAM_CLK_LOOPBACK (BIT(9)) +#define I2S_CAM_CLK_LOOPBACK_M (I2S_CAM_CLK_LOOPBACK_V << I2S_CAM_CLK_LOOPBACK_S) +#define I2S_CAM_CLK_LOOPBACK_V 0x00000001 +#define I2S_CAM_CLK_LOOPBACK_S 9 + +/* I2S_CAM_SYNC_FIFO_RESET : R/W; bitpos: [8]; default: 0; + * Set this bit to reset cam_sync_fifo + */ + +#define I2S_CAM_SYNC_FIFO_RESET (BIT(8)) +#define I2S_CAM_SYNC_FIFO_RESET_M (I2S_CAM_SYNC_FIFO_RESET_V << I2S_CAM_SYNC_FIFO_RESET_S) +#define I2S_CAM_SYNC_FIFO_RESET_V 0x00000001 +#define I2S_CAM_SYNC_FIFO_RESET_S 8 + +/* I2S_INTER_VALID_EN : R/W; bitpos: [7]; default: 0; + * Set this bit to enable camera internal valid + */ + +#define I2S_INTER_VALID_EN (BIT(7)) +#define I2S_INTER_VALID_EN_M (I2S_INTER_VALID_EN_V << I2S_INTER_VALID_EN_S) +#define I2S_INTER_VALID_EN_V 0x00000001 +#define I2S_INTER_VALID_EN_S 7 + +/* I2S_EXT_ADC_START_EN : R/W; bitpos: [6]; default: 0; + * Set this bit to enable the function that ADC mode is triggered by + * external signal. + */ + +#define I2S_EXT_ADC_START_EN (BIT(6)) +#define I2S_EXT_ADC_START_EN_M (I2S_EXT_ADC_START_EN_V << I2S_EXT_ADC_START_EN_S) +#define I2S_EXT_ADC_START_EN_V 0x00000001 +#define I2S_EXT_ADC_START_EN_S 6 + +/* I2S_LCD_EN : R/W; bitpos: [5]; default: 0; + * Set this bit to enable LCD mode + */ + +#define I2S_LCD_EN (BIT(5)) +#define I2S_LCD_EN_M (I2S_LCD_EN_V << I2S_LCD_EN_S) +#define I2S_LCD_EN_V 0x00000001 +#define I2S_LCD_EN_S 5 + +/* I2S_DATA_ENABLE : R/W; bitpos: [4]; default: 0; + * for debug camera mode enable + */ + +#define I2S_DATA_ENABLE (BIT(4)) +#define I2S_DATA_ENABLE_M (I2S_DATA_ENABLE_V << I2S_DATA_ENABLE_S) +#define I2S_DATA_ENABLE_V 0x00000001 +#define I2S_DATA_ENABLE_S 4 + +/* I2S_DATA_ENABLE_TEST_EN : R/W; bitpos: [3]; default: 0; + * for debug camera mode enable + */ + +#define I2S_DATA_ENABLE_TEST_EN (BIT(3)) +#define I2S_DATA_ENABLE_TEST_EN_M (I2S_DATA_ENABLE_TEST_EN_V << I2S_DATA_ENABLE_TEST_EN_S) +#define I2S_DATA_ENABLE_TEST_EN_V 0x00000001 +#define I2S_DATA_ENABLE_TEST_EN_S 3 + +/* I2S_LCD_TX_SDX2_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to duplicate data pairs (Frame Form 2) in LCD mode. + */ + +#define I2S_LCD_TX_SDX2_EN (BIT(2)) +#define I2S_LCD_TX_SDX2_EN_M (I2S_LCD_TX_SDX2_EN_V << I2S_LCD_TX_SDX2_EN_S) +#define I2S_LCD_TX_SDX2_EN_V 0x00000001 +#define I2S_LCD_TX_SDX2_EN_S 2 + +/* I2S_LCD_TX_WRX2_EN : R/W; bitpos: [1]; default: 0; + * LCD WR double for one datum. + */ + +#define I2S_LCD_TX_WRX2_EN (BIT(1)) +#define I2S_LCD_TX_WRX2_EN_M (I2S_LCD_TX_WRX2_EN_V << I2S_LCD_TX_WRX2_EN_S) +#define I2S_LCD_TX_WRX2_EN_V 0x00000001 +#define I2S_LCD_TX_WRX2_EN_S 1 + +/* I2S_CAMERA_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to enable camera mode + */ + +#define I2S_CAMERA_EN (BIT(0)) +#define I2S_CAMERA_EN_M (I2S_CAMERA_EN_V << I2S_CAMERA_EN_S) +#define I2S_CAMERA_EN_V 0x00000001 +#define I2S_CAMERA_EN_S 0 + +/* I2S_CLKM_CONF_REG register + * I2S module clock configure register + */ + +#define I2S_CLKM_CONF_REG (DR_REG_I2S_BASE + 0xac) + +/* I2S_CLK_SEL : R/W; bitpos: [22:21]; default: 0; + * Set this bit to select I2S module clock source. 0: No clock. 1: APLL_CLK. + * 2: PLL_160M_CLK. 3: No clock. + */ + +#define I2S_CLK_SEL 0x00000003 +#define I2S_CLK_SEL_M (I2S_CLK_SEL_V << I2S_CLK_SEL_S) +#define I2S_CLK_SEL_V 0x00000003 +#define I2S_CLK_SEL_S 21 + +/* I2S_CLK_EN : R/W; bitpos: [20]; default: 0; + * Set this bit to enable clk gate + */ + +#define I2S_CLK_EN (BIT(20)) +#define I2S_CLK_EN_M (I2S_CLK_EN_V << I2S_CLK_EN_S) +#define I2S_CLK_EN_V 0x00000001 +#define I2S_CLK_EN_S 20 + +/* I2S_CLKM_DIV_A : R/W; bitpos: [19:14]; default: 0; + * Fractional clock divider denominator value + */ + +#define I2S_CLKM_DIV_A 0x0000003F +#define I2S_CLKM_DIV_A_M (I2S_CLKM_DIV_A_V << I2S_CLKM_DIV_A_S) +#define I2S_CLKM_DIV_A_V 0x0000003F +#define I2S_CLKM_DIV_A_S 14 + +/* I2S_CLKM_DIV_B : R/W; bitpos: [13:8]; default: 0; + * Fractional clock divider numerator value + */ + +#define I2S_CLKM_DIV_B 0x0000003F +#define I2S_CLKM_DIV_B_M (I2S_CLKM_DIV_B_V << I2S_CLKM_DIV_B_S) +#define I2S_CLKM_DIV_B_V 0x0000003F +#define I2S_CLKM_DIV_B_S 8 + +/* I2S_CLKM_DIV_NUM : R/W; bitpos: [7:0]; default: 4; + * Integral I2S clock divider value + */ + +#define I2S_CLKM_DIV_NUM 0x000000FF +#define I2S_CLKM_DIV_NUM_M (I2S_CLKM_DIV_NUM_V << I2S_CLKM_DIV_NUM_S) +#define I2S_CLKM_DIV_NUM_V 0x000000FF +#define I2S_CLKM_DIV_NUM_S 0 + +/* I2S_SAMPLE_RATE_CONF_REG register + * I2S sample rate register + */ + +#define I2S_SAMPLE_RATE_CONF_REG (DR_REG_I2S_BASE + 0xb0) + +/* I2S_RX_BITS_MOD : R/W; bitpos: [23:18]; default: 16; + * Set the bits to configure bit length of I2S receiver channel. + */ + +#define I2S_RX_BITS_MOD 0x0000003F +#define I2S_RX_BITS_MOD_M (I2S_RX_BITS_MOD_V << I2S_RX_BITS_MOD_S) +#define I2S_RX_BITS_MOD_V 0x0000003F +#define I2S_RX_BITS_MOD_S 18 + +/* I2S_TX_BITS_MOD : R/W; bitpos: [17:12]; default: 16; + * Set the bits to configure bit length of I2S transmitter channel. + */ + +#define I2S_TX_BITS_MOD 0x0000003F +#define I2S_TX_BITS_MOD_M (I2S_TX_BITS_MOD_V << I2S_TX_BITS_MOD_S) +#define I2S_TX_BITS_MOD_V 0x0000003F +#define I2S_TX_BITS_MOD_S 12 + +/* I2S_RX_BCK_DIV_NUM : R/W; bitpos: [11:6]; default: 6; + * Bit clock configuration bits in receiver mode. + */ + +#define I2S_RX_BCK_DIV_NUM 0x0000003F +#define I2S_RX_BCK_DIV_NUM_M (I2S_RX_BCK_DIV_NUM_V << I2S_RX_BCK_DIV_NUM_S) +#define I2S_RX_BCK_DIV_NUM_V 0x0000003F +#define I2S_RX_BCK_DIV_NUM_S 6 + +/* I2S_TX_BCK_DIV_NUM : R/W; bitpos: [5:0]; default: 6; + * Bit clock configuration bits in transmitter mode. + */ + +#define I2S_TX_BCK_DIV_NUM 0x0000003F +#define I2S_TX_BCK_DIV_NUM_M (I2S_TX_BCK_DIV_NUM_V << I2S_TX_BCK_DIV_NUM_S) +#define I2S_TX_BCK_DIV_NUM_V 0x0000003F +#define I2S_TX_BCK_DIV_NUM_S 0 + +/* I2S_STATE_REG register + * I2S TX status register + */ + +#define I2S_STATE_REG (DR_REG_I2S_BASE + 0xbc) + +/* I2S_TX_IDLE : RO; bitpos: [0]; default: 1; + * 1: I2S TX is in idle state. 0: I2S TX is at work. + */ + +#define I2S_TX_IDLE (BIT(0)) +#define I2S_TX_IDLE_M (I2S_TX_IDLE_V << I2S_TX_IDLE_S) +#define I2S_TX_IDLE_V 0x00000001 +#define I2S_TX_IDLE_S 0 + +/* I2S_DATE_REG register + * Version control register + */ + +#define I2S_DATE_REG (DR_REG_I2S_BASE + 0xfc) + +/* I2S_DATE : R/W; bitpos: [31:0]; default: 419767552; + * Version control register + */ + +#define I2S_DATE 0xFFFFFFFF +#define I2S_DATE_M (I2S_DATE_V << I2S_DATE_S) +#define I2S_DATE_V 0xFFFFFFFF +#define I2S_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2S_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_interrupt.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_interrupt.h new file mode 100644 index 0000000000..623ace908c --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_interrupt.h @@ -0,0 +1,1647 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/interrupt_reg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_INTERRUPT_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_INTERRUPT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* INTERRUPT_PRO_MAC_INTR_MAP_REG register + * MAC_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x0) + +/* INTERRUPT_PRO_MAC_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map MAC_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_MAC_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_MAC_INTR_MAP_M (INTERRUPT_PRO_MAC_INTR_MAP_V << INTERRUPT_PRO_MAC_INTR_MAP_S) +#define INTERRUPT_PRO_MAC_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_MAC_INTR_MAP_S 0 + +/* INTERRUPT_PRO_MAC_NMI_MAP_REG register + * MAC_NMI interrupt configuration register + */ + +#define INTERRUPT_PRO_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x4) + +/* INTERRUPT_PRO_MAC_NMI_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map MAC_NMI interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_MAC_NMI_MAP 0x0000001F +#define INTERRUPT_PRO_MAC_NMI_MAP_M (INTERRUPT_PRO_MAC_NMI_MAP_V << INTERRUPT_PRO_MAC_NMI_MAP_S) +#define INTERRUPT_PRO_MAC_NMI_MAP_V 0x0000001F +#define INTERRUPT_PRO_MAC_NMI_MAP_S 0 + +/* INTERRUPT_PRO_PWR_INTR_MAP_REG register + * PWR_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x8) + +/* INTERRUPT_PRO_PWR_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PWR_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_PWR_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PWR_INTR_MAP_M (INTERRUPT_PRO_PWR_INTR_MAP_V << INTERRUPT_PRO_PWR_INTR_MAP_S) +#define INTERRUPT_PRO_PWR_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PWR_INTR_MAP_S 0 + +/* INTERRUPT_PRO_BB_INT_MAP_REG register + * BB_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc) + +/* INTERRUPT_PRO_BB_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map BB_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_BB_INT_MAP 0x0000001F +#define INTERRUPT_PRO_BB_INT_MAP_M (INTERRUPT_PRO_BB_INT_MAP_V << INTERRUPT_PRO_BB_INT_MAP_S) +#define INTERRUPT_PRO_BB_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_BB_INT_MAP_S 0 + +/* INTERRUPT_PRO_BT_MAC_INT_MAP_REG register + * BT_MAC_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10) + +/* INTERRUPT_PRO_BT_MAC_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map BT_MAC_INT interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_BT_MAC_INT_MAP 0x0000001F +#define INTERRUPT_PRO_BT_MAC_INT_MAP_M (INTERRUPT_PRO_BT_MAC_INT_MAP_V << INTERRUPT_PRO_BT_MAC_INT_MAP_S) +#define INTERRUPT_PRO_BT_MAC_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_BT_MAC_INT_MAP_S 0 + +/* INTERRUPT_PRO_BT_BB_INT_MAP_REG register + * BT_BB_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x14) + +/* INTERRUPT_PRO_BT_BB_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map BT_BB_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_BT_BB_INT_MAP 0x0000001F +#define INTERRUPT_PRO_BT_BB_INT_MAP_M (INTERRUPT_PRO_BT_BB_INT_MAP_V << INTERRUPT_PRO_BT_BB_INT_MAP_S) +#define INTERRUPT_PRO_BT_BB_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_BT_BB_INT_MAP_S 0 + +/* INTERRUPT_PRO_BT_BB_NMI_MAP_REG register + * BT_BB_NMI interrupt configuration register + */ + +#define INTERRUPT_PRO_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x18) + +/* INTERRUPT_PRO_BT_BB_NMI_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map BT_BB_NMI interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_BT_BB_NMI_MAP 0x0000001F +#define INTERRUPT_PRO_BT_BB_NMI_MAP_M (INTERRUPT_PRO_BT_BB_NMI_MAP_V << INTERRUPT_PRO_BT_BB_NMI_MAP_S) +#define INTERRUPT_PRO_BT_BB_NMI_MAP_V 0x0000001F +#define INTERRUPT_PRO_BT_BB_NMI_MAP_S 0 + +/* INTERRUPT_PRO_RWBT_IRQ_MAP_REG register + * RWBT_IRQ interrupt configuration register + */ + +#define INTERRUPT_PRO_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x1c) + +/* INTERRUPT_PRO_RWBT_IRQ_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map RWBT_IRQ interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_RWBT_IRQ_MAP 0x0000001F +#define INTERRUPT_PRO_RWBT_IRQ_MAP_M (INTERRUPT_PRO_RWBT_IRQ_MAP_V << INTERRUPT_PRO_RWBT_IRQ_MAP_S) +#define INTERRUPT_PRO_RWBT_IRQ_MAP_V 0x0000001F +#define INTERRUPT_PRO_RWBT_IRQ_MAP_S 0 + +/* INTERRUPT_PRO_RWBLE_IRQ_MAP_REG register + * RWBLE_IRQ interrupt configuration register + */ + +#define INTERRUPT_PRO_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_BASE + 0x20) + +/* INTERRUPT_PRO_RWBLE_IRQ_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map RWBLE_IRQ interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_RWBLE_IRQ_MAP 0x0000001F +#define INTERRUPT_PRO_RWBLE_IRQ_MAP_M (INTERRUPT_PRO_RWBLE_IRQ_MAP_V << INTERRUPT_PRO_RWBLE_IRQ_MAP_S) +#define INTERRUPT_PRO_RWBLE_IRQ_MAP_V 0x0000001F +#define INTERRUPT_PRO_RWBLE_IRQ_MAP_S 0 + +/* INTERRUPT_PRO_RWBT_NMI_MAP_REG register + * RWBT_NMI interrupt configuration register + */ + +#define INTERRUPT_PRO_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x24) + +/* INTERRUPT_PRO_RWBT_NMI_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map RWBT_NMI interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_RWBT_NMI_MAP 0x0000001F +#define INTERRUPT_PRO_RWBT_NMI_MAP_M (INTERRUPT_PRO_RWBT_NMI_MAP_V << INTERRUPT_PRO_RWBT_NMI_MAP_S) +#define INTERRUPT_PRO_RWBT_NMI_MAP_V 0x0000001F +#define INTERRUPT_PRO_RWBT_NMI_MAP_S 0 + +/* INTERRUPT_PRO_RWBLE_NMI_MAP_REG register + * RWBLE_NMI interrupt configuration register + */ + +#define INTERRUPT_PRO_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x28) + +/* INTERRUPT_PRO_RWBLE_NMI_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map RWBLE_NMI interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_RWBLE_NMI_MAP 0x0000001F +#define INTERRUPT_PRO_RWBLE_NMI_MAP_M (INTERRUPT_PRO_RWBLE_NMI_MAP_V << INTERRUPT_PRO_RWBLE_NMI_MAP_S) +#define INTERRUPT_PRO_RWBLE_NMI_MAP_V 0x0000001F +#define INTERRUPT_PRO_RWBLE_NMI_MAP_S 0 + +/* INTERRUPT_PRO_SLC0_INTR_MAP_REG register + * SLC0_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x2c) + +/* INTERRUPT_PRO_SLC0_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SLC0_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_SLC0_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_SLC0_INTR_MAP_M (INTERRUPT_PRO_SLC0_INTR_MAP_V << INTERRUPT_PRO_SLC0_INTR_MAP_S) +#define INTERRUPT_PRO_SLC0_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_SLC0_INTR_MAP_S 0 + +/* INTERRUPT_PRO_SLC1_INTR_MAP_REG register + * SLC1_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x30) + +/* INTERRUPT_PRO_SLC1_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SLC1_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_SLC1_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_SLC1_INTR_MAP_M (INTERRUPT_PRO_SLC1_INTR_MAP_V << INTERRUPT_PRO_SLC1_INTR_MAP_S) +#define INTERRUPT_PRO_SLC1_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_SLC1_INTR_MAP_S 0 + +/* INTERRUPT_PRO_UHCI0_INTR_MAP_REG register + * UHCI0_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x34) + +/* INTERRUPT_PRO_UHCI0_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map UHCI0_INTR interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_UHCI0_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_UHCI0_INTR_MAP_M (INTERRUPT_PRO_UHCI0_INTR_MAP_V << INTERRUPT_PRO_UHCI0_INTR_MAP_S) +#define INTERRUPT_PRO_UHCI0_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_UHCI0_INTR_MAP_S 0 + +/* INTERRUPT_PRO_UHCI1_INTR_MAP_REG register + * UHCI1_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_UHCI1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x38) + +/* INTERRUPT_PRO_UHCI1_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map UHCI1_INTR interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_UHCI1_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_UHCI1_INTR_MAP_M (INTERRUPT_PRO_UHCI1_INTR_MAP_V << INTERRUPT_PRO_UHCI1_INTR_MAP_S) +#define INTERRUPT_PRO_UHCI1_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_UHCI1_INTR_MAP_S 0 + +/* INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_REG register + * TG_T0_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x3c) + +/* INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_T0_LEVEL_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_T0_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_REG register + * TG_T1_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x40) + +/* INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_T1_LEVEL_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_T1_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_REG register + * TG_WDT_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x44) + +/* INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_WDT_LEVEL_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_WDT_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_REG register + * TG_LACT_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x48) + +/* INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_LACT_LEVEL_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_LACT_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_REG register + * TG1_T0_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x4c) + +/* INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_T0_LEVEL_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_T0_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_REG register + * TG1_T1_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x50) + +/* INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_T1_LEVEL_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_T1_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_REG register + * TG1_WDT_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x54) + +/* INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_WDT_LEVEL_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_WDT_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_REG register + * TG1_LACT_LEVEL_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x58) + +/* INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_LACT_LEVEL_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_M (INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_V << INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_S) +#define INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_LACT_LEVEL_INT_MAP_S 0 + +/* INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_REG register + * GPIO_INTERRUPT_PRO interrupt configuration register + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_BASE + 0x5c) + +/* INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map GPIO_INTERRUPT_PRO interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_M (INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_S) +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_V 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_MAP_S 0 + +/* INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_REG register + * GPIO_INTERRUPT_PRO_NMI interrupt configuration register + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x60) + +/* INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map GPIO_INTERRUPT_PRO_NMI interrupt signal to + * one of the CPU interrupts. + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_M (INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S) +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +/* INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP_REG register + * GPIO_INTERRUPT_APP interrupt configuration register + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP_REG (DR_REG_INTERRUPT_BASE + 0x64) + +/* INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map GPIO_INTERRUPT_APP interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP_M (INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP_V << INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP_S) +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP_V 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_MAP_S 0 + +/* INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP_REG register + * GPIO_INTERRUPT_APP_NMI interrupt configuration register + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP_REG (DR_REG_INTERRUPT_BASE + 0x68) + +/* INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map GPIO_INTERRUPT_APP_NMI interrupt signal to + * one of the CPU interrupts. + */ + +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP_M (INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP_V << INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP_S) +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP_V 0x0000001F +#define INTERRUPT_PRO_GPIO_INTERRUPT_APP_NMI_MAP_S 0 + +/* INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_REG register + * DEDICATED_GPIO_IN_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x6c) + +/* INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map DEDICATED_GPIO_IN_INTR interrupt signal to + * one of the CPU interrupts. + */ + +#define INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_M (INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_V << INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_S) +#define INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_DEDICATED_GPIO_IN_INTR_MAP_S 0 + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG register + * CPU_INTR_FROM_CPU_0 interrupt configuration register + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_BASE + 0x70) + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CPU_INTR_FROM_CPU_0 interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_M (INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_S) +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_V 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_0_MAP_S 0 + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG register + * CPU_INTR_FROM_CPU_1 interrupt configuration register + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x74) + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CPU_INTR_FROM_CPU_1 interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_M (INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_S) +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_V 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_1_MAP_S 0 + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG register + * CPU_INTR_FROM_CPU_2 interrupt configuration register + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x78) + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CPU_INTR_FROM_CPU_2 interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_M (INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_S) +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_V 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_2_MAP_S 0 + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG register + * CPU_INTR_FROM_CPU_3 interrupt configuration register + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_BASE + 0x7c) + +/* INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CPU_INTR_FROM_CPU_3 interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_M (INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_S) +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_V 0x0000001F +#define INTERRUPT_PRO_CPU_INTR_FROM_CPU_3_MAP_S 0 + +/* INTERRUPT_PRO_SPI_INTR_1_MAP_REG register + * SPI_INTR_1 interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_BASE + 0x80) + +/* INTERRUPT_PRO_SPI_INTR_1_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SPI_INTR_1 interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_SPI_INTR_1_MAP 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_1_MAP_M (INTERRUPT_PRO_SPI_INTR_1_MAP_V << INTERRUPT_PRO_SPI_INTR_1_MAP_S) +#define INTERRUPT_PRO_SPI_INTR_1_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_1_MAP_S 0 + +/* INTERRUPT_PRO_SPI_INTR_2_MAP_REG register + * SPI_INTR_2 interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_BASE + 0x84) + +/* INTERRUPT_PRO_SPI_INTR_2_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SPI_INTR_2 interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_SPI_INTR_2_MAP 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_2_MAP_M (INTERRUPT_PRO_SPI_INTR_2_MAP_V << INTERRUPT_PRO_SPI_INTR_2_MAP_S) +#define INTERRUPT_PRO_SPI_INTR_2_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_2_MAP_S 0 + +/* INTERRUPT_PRO_SPI_INTR_3_MAP_REG register + * SPI_INTR_3 interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI_INTR_3_MAP_REG (DR_REG_INTERRUPT_BASE + 0x88) + +/* INTERRUPT_PRO_SPI_INTR_3_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SPI_INTR_3 interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_SPI_INTR_3_MAP 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_3_MAP_M (INTERRUPT_PRO_SPI_INTR_3_MAP_V << INTERRUPT_PRO_SPI_INTR_3_MAP_S) +#define INTERRUPT_PRO_SPI_INTR_3_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_3_MAP_S 0 + +/* INTERRUPT_PRO_I2S0_INT_MAP_REG register + * I2S0_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x8c) + +/* INTERRUPT_PRO_I2S0_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map I2S0_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_I2S0_INT_MAP 0x0000001F +#define INTERRUPT_PRO_I2S0_INT_MAP_M (INTERRUPT_PRO_I2S0_INT_MAP_V << INTERRUPT_PRO_I2S0_INT_MAP_S) +#define INTERRUPT_PRO_I2S0_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_I2S0_INT_MAP_S 0 + +/* INTERRUPT_PRO_I2S1_INT_MAP_REG register + * I2S1_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x90) + +/* INTERRUPT_PRO_I2S1_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map I2S1_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_I2S1_INT_MAP 0x0000001F +#define INTERRUPT_PRO_I2S1_INT_MAP_M (INTERRUPT_PRO_I2S1_INT_MAP_V << INTERRUPT_PRO_I2S1_INT_MAP_S) +#define INTERRUPT_PRO_I2S1_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_I2S1_INT_MAP_S 0 + +/* INTERRUPT_PRO_UART_INTR_MAP_REG register + * UART_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_UART_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x94) + +/* INTERRUPT_PRO_UART_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map UART_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_UART_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_UART_INTR_MAP_M (INTERRUPT_PRO_UART_INTR_MAP_V << INTERRUPT_PRO_UART_INTR_MAP_S) +#define INTERRUPT_PRO_UART_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_UART_INTR_MAP_S 0 + +/* INTERRUPT_PRO_UART1_INTR_MAP_REG register + * UART1_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x98) + +/* INTERRUPT_PRO_UART1_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map UART1_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_UART1_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_UART1_INTR_MAP_M (INTERRUPT_PRO_UART1_INTR_MAP_V << INTERRUPT_PRO_UART1_INTR_MAP_S) +#define INTERRUPT_PRO_UART1_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_UART1_INTR_MAP_S 0 + +/* INTERRUPT_PRO_UART2_INTR_MAP_REG register + * UART2_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x9c) + +/* INTERRUPT_PRO_UART2_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map UART2_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_UART2_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_UART2_INTR_MAP_M (INTERRUPT_PRO_UART2_INTR_MAP_V << INTERRUPT_PRO_UART2_INTR_MAP_S) +#define INTERRUPT_PRO_UART2_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_UART2_INTR_MAP_S 0 + +/* INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP_REG register + * SDIO_HOST_INTERRUPT configuration register + */ + +#define INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa0) + +/* INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SDIO_HOST_INTERRUPT signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP 0x0000001F +#define INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP_M (INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP_V << INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP_S) +#define INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP_V 0x0000001F +#define INTERRUPT_PRO_SDIO_HOST_INTERRUPT_MAP_S 0 + +/* INTERRUPT_PRO_PWM0_INTR_MAP_REG register + * PWM0_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa4) + +/* INTERRUPT_PRO_PWM0_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PWM0_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_PWM0_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PWM0_INTR_MAP_M (INTERRUPT_PRO_PWM0_INTR_MAP_V << INTERRUPT_PRO_PWM0_INTR_MAP_S) +#define INTERRUPT_PRO_PWM0_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PWM0_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PWM1_INTR_MAP_REG register + * PWM1_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xa8) + +/* INTERRUPT_PRO_PWM1_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PWM1_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_PWM1_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PWM1_INTR_MAP_M (INTERRUPT_PRO_PWM1_INTR_MAP_V << INTERRUPT_PRO_PWM1_INTR_MAP_S) +#define INTERRUPT_PRO_PWM1_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PWM1_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PWM2_INTR_MAP_REG register + * PWM2_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xac) + +/* INTERRUPT_PRO_PWM2_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PWM2_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_PWM2_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PWM2_INTR_MAP_M (INTERRUPT_PRO_PWM2_INTR_MAP_V << INTERRUPT_PRO_PWM2_INTR_MAP_S) +#define INTERRUPT_PRO_PWM2_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PWM2_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PWM3_INTR_MAP_REG register + * PWM3_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xb0) + +/* INTERRUPT_PRO_PWM3_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PWM3_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_PWM3_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PWM3_INTR_MAP_M (INTERRUPT_PRO_PWM3_INTR_MAP_V << INTERRUPT_PRO_PWM3_INTR_MAP_S) +#define INTERRUPT_PRO_PWM3_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PWM3_INTR_MAP_S 0 + +/* INTERRUPT_PRO_LEDC_INT_MAP_REG register + * LEDC_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xb4) + +/* INTERRUPT_PRO_LEDC_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map LEDC_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_LEDC_INT_MAP 0x0000001F +#define INTERRUPT_PRO_LEDC_INT_MAP_M (INTERRUPT_PRO_LEDC_INT_MAP_V << INTERRUPT_PRO_LEDC_INT_MAP_S) +#define INTERRUPT_PRO_LEDC_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_LEDC_INT_MAP_S 0 + +/* INTERRUPT_PRO_EFUSE_INT_MAP_REG register + * EFUSE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xb8) + +/* INTERRUPT_PRO_EFUSE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map EFUSE_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_EFUSE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_EFUSE_INT_MAP_M (INTERRUPT_PRO_EFUSE_INT_MAP_V << INTERRUPT_PRO_EFUSE_INT_MAP_S) +#define INTERRUPT_PRO_EFUSE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_EFUSE_INT_MAP_S 0 + +/* INTERRUPT_PRO_CAN_INT_MAP_REG register + * CAN_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_CAN_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xbc) + +/* INTERRUPT_PRO_CAN_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CAN_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_CAN_INT_MAP 0x0000001F +#define INTERRUPT_PRO_CAN_INT_MAP_M (INTERRUPT_PRO_CAN_INT_MAP_V << INTERRUPT_PRO_CAN_INT_MAP_S) +#define INTERRUPT_PRO_CAN_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_CAN_INT_MAP_S 0 + +/* INTERRUPT_PRO_USB_INTR_MAP_REG register + * USB_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_USB_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc0) + +/* INTERRUPT_PRO_USB_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map USB_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_USB_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_USB_INTR_MAP_M (INTERRUPT_PRO_USB_INTR_MAP_V << INTERRUPT_PRO_USB_INTR_MAP_S) +#define INTERRUPT_PRO_USB_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_USB_INTR_MAP_S 0 + +/* INTERRUPT_PRO_RTC_CORE_INTR_MAP_REG register + * RTC_CORE_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc4) + +/* INTERRUPT_PRO_RTC_CORE_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map RTC_CORE_INTR interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_RTC_CORE_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_RTC_CORE_INTR_MAP_M (INTERRUPT_PRO_RTC_CORE_INTR_MAP_V << INTERRUPT_PRO_RTC_CORE_INTR_MAP_S) +#define INTERRUPT_PRO_RTC_CORE_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_RTC_CORE_INTR_MAP_S 0 + +/* INTERRUPT_PRO_RMT_INTR_MAP_REG register + * RMT_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xc8) + +/* INTERRUPT_PRO_RMT_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map RMT_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_RMT_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_RMT_INTR_MAP_M (INTERRUPT_PRO_RMT_INTR_MAP_V << INTERRUPT_PRO_RMT_INTR_MAP_S) +#define INTERRUPT_PRO_RMT_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_RMT_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PCNT_INTR_MAP_REG register + * PCNT_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xcc) + +/* INTERRUPT_PRO_PCNT_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PCNT_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_PCNT_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PCNT_INTR_MAP_M (INTERRUPT_PRO_PCNT_INTR_MAP_V << INTERRUPT_PRO_PCNT_INTR_MAP_S) +#define INTERRUPT_PRO_PCNT_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PCNT_INTR_MAP_S 0 + +/* INTERRUPT_PRO_I2C_EXT0_INTR_MAP_REG register + * I2C_EXT0_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xd0) + +/* INTERRUPT_PRO_I2C_EXT0_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map I2C_EXT0_INTR interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_I2C_EXT0_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_I2C_EXT0_INTR_MAP_M (INTERRUPT_PRO_I2C_EXT0_INTR_MAP_V << INTERRUPT_PRO_I2C_EXT0_INTR_MAP_S) +#define INTERRUPT_PRO_I2C_EXT0_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_I2C_EXT0_INTR_MAP_S 0 + +/* INTERRUPT_PRO_I2C_EXT1_INTR_MAP_REG register + * I2C_EXT1_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xd4) + +/* INTERRUPT_PRO_I2C_EXT1_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map I2C_EXT1_INTR interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_I2C_EXT1_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_I2C_EXT1_INTR_MAP_M (INTERRUPT_PRO_I2C_EXT1_INTR_MAP_V << INTERRUPT_PRO_I2C_EXT1_INTR_MAP_S) +#define INTERRUPT_PRO_I2C_EXT1_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_I2C_EXT1_INTR_MAP_S 0 + +/* INTERRUPT_PRO_RSA_INTR_MAP_REG register + * RSA_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xd8) + +/* INTERRUPT_PRO_RSA_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map RSA_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_RSA_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_RSA_INTR_MAP_M (INTERRUPT_PRO_RSA_INTR_MAP_V << INTERRUPT_PRO_RSA_INTR_MAP_S) +#define INTERRUPT_PRO_RSA_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_RSA_INTR_MAP_S 0 + +/* INTERRUPT_PRO_SHA_INTR_MAP_REG register + * SHA_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xdc) + +/* INTERRUPT_PRO_SHA_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SHA_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_SHA_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_SHA_INTR_MAP_M (INTERRUPT_PRO_SHA_INTR_MAP_V << INTERRUPT_PRO_SHA_INTR_MAP_S) +#define INTERRUPT_PRO_SHA_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_SHA_INTR_MAP_S 0 + +/* INTERRUPT_PRO_AES_INTR_MAP_REG register + * AES_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_AES_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0xe0) + +/* INTERRUPT_PRO_AES_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map AES_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_AES_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_AES_INTR_MAP_M (INTERRUPT_PRO_AES_INTR_MAP_V << INTERRUPT_PRO_AES_INTR_MAP_S) +#define INTERRUPT_PRO_AES_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_AES_INTR_MAP_S 0 + +/* INTERRUPT_PRO_SPI2_DMA_INT_MAP_REG register + * SPI2_DMA_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xe4) + +/* INTERRUPT_PRO_SPI2_DMA_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map AES_INTR interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_SPI2_DMA_INT_MAP 0x0000001F +#define INTERRUPT_PRO_SPI2_DMA_INT_MAP_M (INTERRUPT_PRO_SPI2_DMA_INT_MAP_V << INTERRUPT_PRO_SPI2_DMA_INT_MAP_S) +#define INTERRUPT_PRO_SPI2_DMA_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI2_DMA_INT_MAP_S 0 + +/* INTERRUPT_PRO_SPI3_DMA_INT_MAP_REG register + * SPI3_DMA_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xe8) + +/* INTERRUPT_PRO_SPI3_DMA_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SPI3_DMA_INT dma interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_SPI3_DMA_INT_MAP 0x0000001F +#define INTERRUPT_PRO_SPI3_DMA_INT_MAP_M (INTERRUPT_PRO_SPI3_DMA_INT_MAP_V << INTERRUPT_PRO_SPI3_DMA_INT_MAP_S) +#define INTERRUPT_PRO_SPI3_DMA_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI3_DMA_INT_MAP_S 0 + +/* INTERRUPT_PRO_WDG_INT_MAP_REG register + * WDG_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_WDG_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xec) + +/* INTERRUPT_PRO_WDG_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map WDG_INT interrupt signal to one of the CPU + * interrupts. + */ + +#define INTERRUPT_PRO_WDG_INT_MAP 0x0000001F +#define INTERRUPT_PRO_WDG_INT_MAP_M (INTERRUPT_PRO_WDG_INT_MAP_V << INTERRUPT_PRO_WDG_INT_MAP_S) +#define INTERRUPT_PRO_WDG_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_WDG_INT_MAP_S 0 + +/* INTERRUPT_PRO_TIMER_INT1_MAP_REG register + * TIMER_INT1 interrupt configuration register + */ + +#define INTERRUPT_PRO_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_BASE + 0xf0) + +/* INTERRUPT_PRO_TIMER_INT1_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TIMER_INT1 interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_TIMER_INT1_MAP 0x0000001F +#define INTERRUPT_PRO_TIMER_INT1_MAP_M (INTERRUPT_PRO_TIMER_INT1_MAP_V << INTERRUPT_PRO_TIMER_INT1_MAP_S) +#define INTERRUPT_PRO_TIMER_INT1_MAP_V 0x0000001F +#define INTERRUPT_PRO_TIMER_INT1_MAP_S 0 + +/* INTERRUPT_PRO_TIMER_INT2_MAP_REG register + * TIMER_INT2 interrupt configuration register + */ + +#define INTERRUPT_PRO_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_BASE + 0xf4) + +/* INTERRUPT_PRO_TIMER_INT2_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TIMER_INT2 interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_TIMER_INT2_MAP 0x0000001F +#define INTERRUPT_PRO_TIMER_INT2_MAP_M (INTERRUPT_PRO_TIMER_INT2_MAP_V << INTERRUPT_PRO_TIMER_INT2_MAP_S) +#define INTERRUPT_PRO_TIMER_INT2_MAP_V 0x0000001F +#define INTERRUPT_PRO_TIMER_INT2_MAP_S 0 + +/* INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_REG register + * TG_T0_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xf8) + +/* INTERRUPT_PRO_TG_T0_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_T0_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_T0_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_M (INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_V << INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_T0_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_REG register + * TG_T1_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0xfc) + +/* INTERRUPT_PRO_TG_T1_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_T1_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_T1_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_M (INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_V << INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_T1_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_REG register + * TG_WDT_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x100) + +/* INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_WDT_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_M (INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_V << INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_WDT_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_REG register + * TG_LACT_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x104) + +/* INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG_LACT_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_M (INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_V << INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG_LACT_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_REG register + * TG1_T0_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x108) + +/* INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_T0_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_M (INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_V << INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_T0_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_REG register + * TG1_T1_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x10c) + +/* INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_T1_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_M (INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_V << INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_T1_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_REG register + * TG1_WDT_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x110) + +/* INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_WDT_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_M (INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_V << INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_WDT_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_REG register + * TG1_LACT_EDGE_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x114) + +/* INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map TG1_LACT_EDGE_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP 0x0000001F +#define INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_M (INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_V << INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_S) +#define INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_TG1_LACT_EDGE_INT_MAP_S 0 + +/* INTERRUPT_PRO_CACHE_IA_INT_MAP_REG register + * CACHE_IA_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x118) + +/* INTERRUPT_PRO_CACHE_IA_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CACHE_IA_INT interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_CACHE_IA_INT_MAP 0x0000001F +#define INTERRUPT_PRO_CACHE_IA_INT_MAP_M (INTERRUPT_PRO_CACHE_IA_INT_MAP_V << INTERRUPT_PRO_CACHE_IA_INT_MAP_S) +#define INTERRUPT_PRO_CACHE_IA_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_CACHE_IA_INT_MAP_S 0 + +/* INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_REG register + * SYSTIMER_TARGET0_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x11c) + +/* INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SYSTIMER_TARGET0_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP 0x0000001F +#define INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_M (INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_V << INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_S) +#define INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_SYSTIMER_TARGET0_INT_MAP_S 0 + +/* INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_REG register + * SYSTIMER_TARGET1_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x120) + +/* INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SYSTIMER_TARGET1_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP 0x0000001F +#define INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_M (INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_V << INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_S) +#define INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_SYSTIMER_TARGET1_INT_MAP_S 0 + +/* INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_REG register + * SYSTIMER_TARGET2_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x124) + +/* INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SYSTIMER_TARGET2_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP 0x0000001F +#define INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_M (INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_V << INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_S) +#define INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_SYSTIMER_TARGET2_INT_MAP_S 0 + +/* INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_REG register + * ASSIST_DEBUG_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x128) + +/* INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map ASSIST_DEBUG_INTR interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_M (INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_S) +#define INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_ASSIST_DEBUG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_REG register + * PMS_PRO_IRAM0_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x12c) + +/* INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map PMS_PRO_IRAM0_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_REG register + * PMS_PRO_DRAM0_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x130) + +/* INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map PMS_PRO_DRAM0_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_REG register + * PMS_PRO_DPORT_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x134) + +/* INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map PMS_PRO_DPORT_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_REG register + * PMS_PRO_AHB_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x138) + +/* INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PMS_PRO_AHB_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_REG register + * PMS_PRO_CACHE_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x13c) + +/* INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map PMS_PRO_CACHE_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_REG register + * PMS_DMA_APB_I_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x140) + +/* INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: + * 16; + * This register is used to map PMS_DMA_APB_I_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_REG register + * PMS_DMA_RX_I_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x144) + +/* INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PMS_DMA_RX_I_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_REG register + * PMS_DMA_TX_I_ILG interrupt configuration register + */ + +#define INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x148) + +/* INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map PMS_DMA_TX_I_ILG interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_M (INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_V << INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_S) +#define INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_S 0 + +/* INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_REG register + * SPI_MEM_REJECT_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x14c) + +/* INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SPI_MEM_REJECT_INTR interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_M (INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_V << INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_S) +#define INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI_MEM_REJECT_INTR_MAP_S 0 + +/* INTERRUPT_PRO_DMA_COPY_INTR_MAP_REG register + * DMA_COPY_INTR interrupt configuration register + */ + +#define INTERRUPT_PRO_DMA_COPY_INTR_MAP_REG (DR_REG_INTERRUPT_BASE + 0x150) + +/* INTERRUPT_PRO_DMA_COPY_INTR_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map DMA_COPY_INTR interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_DMA_COPY_INTR_MAP 0x0000001F +#define INTERRUPT_PRO_DMA_COPY_INTR_MAP_M (INTERRUPT_PRO_DMA_COPY_INTR_MAP_V << INTERRUPT_PRO_DMA_COPY_INTR_MAP_S) +#define INTERRUPT_PRO_DMA_COPY_INTR_MAP_V 0x0000001F +#define INTERRUPT_PRO_DMA_COPY_INTR_MAP_S 0 + +/* INTERRUPT_PRO_SPI4_DMA_INT_MAP_REG register + * SPI4_DMA_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI4_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x154) + +/* INTERRUPT_PRO_SPI4_DMA_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SPI4_DMA_INT interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_SPI4_DMA_INT_MAP 0x0000001F +#define INTERRUPT_PRO_SPI4_DMA_INT_MAP_M (INTERRUPT_PRO_SPI4_DMA_INT_MAP_V << INTERRUPT_PRO_SPI4_DMA_INT_MAP_S) +#define INTERRUPT_PRO_SPI4_DMA_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI4_DMA_INT_MAP_S 0 + +/* INTERRUPT_PRO_SPI_INTR_4_MAP_REG register + * SPI_INTR_4 interrupt configuration register + */ + +#define INTERRUPT_PRO_SPI_INTR_4_MAP_REG (DR_REG_INTERRUPT_BASE + 0x158) + +/* INTERRUPT_PRO_SPI_INTR_4_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map SPI_INTR_4 interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_SPI_INTR_4_MAP 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_4_MAP_M (INTERRUPT_PRO_SPI_INTR_4_MAP_V << INTERRUPT_PRO_SPI_INTR_4_MAP_S) +#define INTERRUPT_PRO_SPI_INTR_4_MAP_V 0x0000001F +#define INTERRUPT_PRO_SPI_INTR_4_MAP_S 0 + +/* INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_REG register + * DCACHE_PRELOAD_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x15c) + +/* INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map DCACHE_PRELOAD_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP 0x0000001F +#define INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_M (INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_V << INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_S) +#define INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_DCACHE_PRELOAD_INT_MAP_S 0 + +/* INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_REG register + * ICACHE_PRELOAD_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x160) + +/* INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map ICACHE_PRELOAD_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP 0x0000001F +#define INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_M (INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_V << INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_S) +#define INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_ICACHE_PRELOAD_INT_MAP_S 0 + +/* INTERRUPT_PRO_APB_ADC_INT_MAP_REG register + * APB_ADC_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x164) + +/* INTERRUPT_PRO_APB_ADC_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map APB_ADC_INT interrupt signal to one of the + * CPU interrupts. + */ + +#define INTERRUPT_PRO_APB_ADC_INT_MAP 0x0000001F +#define INTERRUPT_PRO_APB_ADC_INT_MAP_M (INTERRUPT_PRO_APB_ADC_INT_MAP_V << INTERRUPT_PRO_APB_ADC_INT_MAP_S) +#define INTERRUPT_PRO_APB_ADC_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_APB_ADC_INT_MAP_S 0 + +/* INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_REG register + * CRYPTO_DMA_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x168) + +/* INTERRUPT_PRO_CRYPTO_DMA_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CRYPTO_DMA_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_CRYPTO_DMA_INT_MAP 0x0000001F +#define INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_M (INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_V << INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_S) +#define INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_CRYPTO_DMA_INT_MAP_S 0 + +/* INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_REG register + * CPU_PERI_ERROR_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x16c) + +/* INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map CPU_PERI_ERROR_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP 0x0000001F +#define INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_M (INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_V << INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_S) +#define INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_CPU_PERI_ERROR_INT_MAP_S 0 + +/* INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_REG register + * APB_PERI_ERROR_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x170) + +/* INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map APB_PERI_ERROR_INT interrupt signal to one + * of the CPU interrupts. + */ + +#define INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP 0x0000001F +#define INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_M (INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_V << INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_S) +#define INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_APB_PERI_ERROR_INT_MAP_S 0 + +/* INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_REG register + * DCACHE_SYNC_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x174) + +/* INTERRUPT_PRO_DCACHE_SYNC_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map DCACHE_SYNC_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_DCACHE_SYNC_INT_MAP 0x0000001F +#define INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_M (INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_V << INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_S) +#define INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_DCACHE_SYNC_INT_MAP_S 0 + +/* INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_REG register + * ICACHE_SYNC_INT interrupt configuration register + */ + +#define INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_BASE + 0x178) + +/* INTERRUPT_PRO_ICACHE_SYNC_INT_MAP : R/W; bitpos: [4:0]; default: 16; + * This register is used to map ICACHE_SYNC_INT interrupt signal to one of + * the CPU interrupts. + */ + +#define INTERRUPT_PRO_ICACHE_SYNC_INT_MAP 0x0000001F +#define INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_M (INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_V << INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_S) +#define INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_V 0x0000001F +#define INTERRUPT_PRO_ICACHE_SYNC_INT_MAP_S 0 + +/* INTERRUPT_PRO_INTR_STATUS_REG_0_REG register + * Interrupt status register 0 + */ + +#define INTERRUPT_PRO_INTR_STATUS_REG_0_REG (DR_REG_INTERRUPT_BASE + 0x17c) + +/* INTERRUPT_PRO_INTR_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * This register stores the status of the first 32 input interrupt sources. + */ + +#define INTERRUPT_PRO_INTR_STATUS_0 0xFFFFFFFF +#define INTERRUPT_PRO_INTR_STATUS_0_M (INTERRUPT_PRO_INTR_STATUS_0_V << INTERRUPT_PRO_INTR_STATUS_0_S) +#define INTERRUPT_PRO_INTR_STATUS_0_V 0xFFFFFFFF +#define INTERRUPT_PRO_INTR_STATUS_0_S 0 + +/* INTERRUPT_PRO_INTR_STATUS_REG_1_REG register + * Interrupt status register 1 + */ + +#define INTERRUPT_PRO_INTR_STATUS_REG_1_REG (DR_REG_INTERRUPT_BASE + 0x180) + +/* INTERRUPT_PRO_INTR_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * This register stores the status of the second 32 input interrupt sources. + */ + +#define INTERRUPT_PRO_INTR_STATUS_1 0xFFFFFFFF +#define INTERRUPT_PRO_INTR_STATUS_1_M (INTERRUPT_PRO_INTR_STATUS_1_V << INTERRUPT_PRO_INTR_STATUS_1_S) +#define INTERRUPT_PRO_INTR_STATUS_1_V 0xFFFFFFFF +#define INTERRUPT_PRO_INTR_STATUS_1_S 0 + +/* INTERRUPT_PRO_INTR_STATUS_REG_2_REG register + * Interrupt status register 2 + */ + +#define INTERRUPT_PRO_INTR_STATUS_REG_2_REG (DR_REG_INTERRUPT_BASE + 0x184) + +/* INTERRUPT_PRO_INTR_STATUS_2 : RO; bitpos: [31:0]; default: 0; + * This register stores the status of the last 31 input interrupt sources. + */ + +#define INTERRUPT_PRO_INTR_STATUS_2 0xFFFFFFFF +#define INTERRUPT_PRO_INTR_STATUS_2_M (INTERRUPT_PRO_INTR_STATUS_2_V << INTERRUPT_PRO_INTR_STATUS_2_S) +#define INTERRUPT_PRO_INTR_STATUS_2_V 0xFFFFFFFF +#define INTERRUPT_PRO_INTR_STATUS_2_S 0 + +/* INTERRUPT_CLOCK_GATE_REG register + * NMI interrupt signals mask register + */ + +#define INTERRUPT_CLOCK_GATE_REG (DR_REG_INTERRUPT_BASE + 0x188) + +/* INTERRUPT_PRO_NMI_MASK_HW : R/W; bitpos: [1]; default: 0; + * This bit is used to disable all NMI interrupt signals to CPU. + */ + +#define INTERRUPT_PRO_NMI_MASK_HW (BIT(1)) +#define INTERRUPT_PRO_NMI_MASK_HW_M (INTERRUPT_PRO_NMI_MASK_HW_V << INTERRUPT_PRO_NMI_MASK_HW_S) +#define INTERRUPT_PRO_NMI_MASK_HW_V 0x00000001 +#define INTERRUPT_PRO_NMI_MASK_HW_S 1 + +/* INTERRUPT_CLK_EN : R/W; bitpos: [0]; default: 1; + * This bit is used to enable or disable the clock of interrupt matrix. 1: + * enable the clock. 0: disable the clock. + */ + +#define INTERRUPT_CLK_EN (BIT(0)) +#define INTERRUPT_CLK_EN_M (INTERRUPT_CLK_EN_V << INTERRUPT_CLK_EN_S) +#define INTERRUPT_CLK_EN_V 0x00000001 +#define INTERRUPT_CLK_EN_S 0 + +/* INTERRUPT_REG_DATE_REG register + * Version control register + */ + +#define INTERRUPT_REG_DATE_REG (DR_REG_INTERRUPT_BASE + 0xffc) + +/* INTERRUPT_INTERRUPT_REG_DATE : R/W; bitpos: [27:0]; default: 26231168; + * This is the version register. + */ + +#define INTERRUPT_INTERRUPT_REG_DATE 0x0FFFFFFF +#define INTERRUPT_INTERRUPT_REG_DATE_M (INTERRUPT_INTERRUPT_REG_DATE_V << INTERRUPT_INTERRUPT_REG_DATE_S) +#define INTERRUPT_INTERRUPT_REG_DATE_V 0x0FFFFFFF +#define INTERRUPT_INTERRUPT_REG_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_INTERRUPT_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h new file mode 100644 index 0000000000..818c987236 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h @@ -0,0 +1,460 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_iomux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_IOMUM_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_IOMUM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers + * Output enable in sleep mode + */ + +#define SLP_OE (BIT(0)) +#define SLP_OE_M (BIT(0)) +#define SLP_OE_V 1 +#define SLP_OE_S 0 + +/* Pin used for wakeup from sleep */ + +#define SLP_SEL (BIT(1)) +#define SLP_SEL_M (BIT(1)) +#define SLP_SEL_V 1 +#define SLP_SEL_S 1 + +/* Pulldown enable in sleep mode */ + +#define SLP_PD (BIT(2)) +#define SLP_PD_M (BIT(2)) +#define SLP_PD_V 1 +#define SLP_PD_S 2 + +/* Pullup enable in sleep mode */ + +#define SLP_PU (BIT(3)) +#define SLP_PU_M (BIT(3)) +#define SLP_PU_V 1 +#define SLP_PU_S 3 + +/* Input enable in sleep mode */ + +#define SLP_IE (BIT(4)) +#define SLP_IE_M (BIT(4)) +#define SLP_IE_V 1 +#define SLP_IE_S 4 + +/* Drive strength in sleep mode */ + +#define SLP_DRV 0x3 +#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) +#define SLP_DRV_V 0x3 +#define SLP_DRV_S 5 + +/* Pulldown enable */ + +#define FUN_PD (BIT(7)) +#define FUN_PD_M (BIT(7)) +#define FUN_PD_V 1 +#define FUN_PD_S 7 + +/* Pullup enable */ + +#define FUN_PU (BIT(8)) +#define FUN_PU_M (BIT(8)) +#define FUN_PU_V 1 +#define FUN_PU_S 8 + +/* Input enable */ + +#define FUN_IE (BIT(9)) +#define FUN_IE_M (FUN_IE_V << FUN_IE_S) +#define FUN_IE_V 1 +#define FUN_IE_S 9 + +/* Drive strength */ + +#define FUN_DRV 0x3 +#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) +#define FUN_DRV_V 0x3 +#define FUN_DRV_S 10 + +/* Function select (possible values are defined for each pin as + * FUNC_pinname_function below) + */ + +#define MCU_SEL 0x7 +#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) +#define MCU_SEL_V 0x7 +#define MCU_SEL_S 12 + +#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) +#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) +#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) +#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) +#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) + +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_GPIO4_U +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_GPIO5_U +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_XTAL_32K_P_U +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_XTAL_32K_N_U +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_DAC_1_U +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_DAC_2_U +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_GPIO21_U +#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPICS1_U +#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SPIHD_U +#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIWP_U +#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICS0_U +#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPICLK_U +#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_SPIQ_U +#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_SPID_U +#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U +#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U +#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U +#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U +#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U +#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U +#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_MTCK_U +#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_MTDO_U +#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_MTDI_U +#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_MTMS_U +#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U0TXD_U +#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U0RXD_U +#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U +#define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_GPIO46_U + +#define FUNC_GPIO_GPIO 1 +#define PIN_FUNC_GPIO 1 + +#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) + +#define U1RXD_GPIO_NUM 18 +#define U1TXD_GPIO_NUM 17 +#define U0RXD_GPIO_NUM 44 +#define U0TXD_GPIO_NUM 43 + +#define SPI_CS1_GPIO_NUM 26 +#define SPI_HD_GPIO_NUM 27 +#define SPI_WP_GPIO_NUM 28 +#define SPI_CS0_GPIO_NUM 29 +#define SPI_CLK_GPIO_NUM 30 +#define SPI_Q_GPIO_NUM 31 +#define SPI_D_GPIO_NUM 32 +#define SPI_D4_GPIO_NUM 33 +#define SPI_D5_GPIO_NUM 34 +#define SPI_D6_GPIO_NUM 35 +#define SPI_D7_GPIO_NUM 36 +#define SPI_DQS_GPIO_NUM 37 + +#define MAX_RTC_GPIO_NUM 21 +#define MAX_PAD_GPIO_NUM 46 +#define MAX_GPIO_NUM 53 + +#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE +#define PIN_CTRL (REG_IO_MUX_BASE +0x00) +#define PAD_POWER_SEL BIT(15) +#define PAD_POWER_SEL_V 0x1 +#define PAD_POWER_SEL_M BIT(15) +#define PAD_POWER_SEL_S 15 + +#define PAD_POWER_SWITCH_DELAY 0x7 +#define PAD_POWER_SWITCH_DELAY_V 0x7 +#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) +#define PAD_POWER_SWITCH_DELAY_S 12 + +#define CLK_OUT3 0xf +#define CLK_OUT3_V CLK_OUT3 +#define CLK_OUT3_S 8 +#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S) +#define CLK_OUT2 0xf +#define CLK_OUT2_V CLK_OUT2 +#define CLK_OUT2_S 4 +#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S) +#define CLK_OUT1 0xf +#define CLK_OUT1_V CLK_OUT1 +#define CLK_OUT1_S 0 +#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S) + +#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE +0x04) +#define FUNC_GPIO0_GPIO0 1 +#define FUNC_GPIO0_GPIO0_0 0 + +#define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE +0x08) +#define FUNC_GPIO1_GPIO1 1 +#define FUNC_GPIO1_GPIO1_0 0 + +#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE +0x0c) +#define FUNC_GPIO2_GPIO2 1 +#define FUNC_GPIO2_GPIO2_0 0 + +#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE +0x10) +#define FUNC_GPIO3_GPIO3 1 +#define FUNC_GPIO3_GPIO3_0 0 + +#define PERIPHS_IO_MUX_GPIO4_U (REG_IO_MUX_BASE +0x14) +#define FUNC_GPIO4_GPIO4 1 +#define FUNC_GPIO4_GPIO4_0 0 + +#define PERIPHS_IO_MUX_GPIO5_U (REG_IO_MUX_BASE +0x18) +#define FUNC_GPIO5_GPIO5 1 +#define FUNC_GPIO5_GPIO5_0 0 + +#define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE +0x1c) +#define FUNC_GPIO6_GPIO6 1 +#define FUNC_GPIO6_GPIO6_0 0 + +#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE +0x20) +#define FUNC_GPIO7_GPIO7 1 +#define FUNC_GPIO7_GPIO7_0 0 + +#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE +0x24) +#define FUNC_GPIO8_SUBSPICS1 3 +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_GPIO8_0 0 + +#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE +0x28) +#define FUNC_GPIO9_FSPIHD 4 +#define FUNC_GPIO9_SUBSPIHD 3 +#define FUNC_GPIO9_GPIO9 1 +#define FUNC_GPIO9_GPIO9_0 0 + +#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE +0x2c) +#define FUNC_GPIO10_FSPICS0 4 +#define FUNC_GPIO10_SUBSPICS0 3 +#define FUNC_GPIO10_FSPIIO4 2 +#define FUNC_GPIO10_GPIO10 1 +#define FUNC_GPIO10_GPIO10_0 0 + +#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE +0x30) +#define FUNC_GPIO11_FSPID 4 +#define FUNC_GPIO11_SUBSPID 3 +#define FUNC_GPIO11_FSPIIO5 2 +#define FUNC_GPIO11_GPIO11 1 +#define FUNC_GPIO11_GPIO11_0 0 + +#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE +0x34) +#define FUNC_GPIO12_FSPICLK 4 +#define FUNC_GPIO12_SUBSPICLK 3 +#define FUNC_GPIO12_FSPIIO6 2 +#define FUNC_GPIO12_GPIO12 1 +#define FUNC_GPIO12_GPIO12_0 0 + +#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE +0x38) +#define FUNC_GPIO13_FSPIQ 4 +#define FUNC_GPIO13_SUBSPIQ 3 +#define FUNC_GPIO13_FSPIIO7 2 +#define FUNC_GPIO13_GPIO13 1 +#define FUNC_GPIO13_GPIO13_0 0 + +#define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE +0x3c) +#define FUNC_GPIO14_FSPIWP 4 +#define FUNC_GPIO14_SUBSPIWP 3 +#define FUNC_GPIO14_FSPIDQS 2 +#define FUNC_GPIO14_GPIO14 1 +#define FUNC_GPIO14_GPIO14_0 0 + +#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE +0x40) +#define FUNC_XTAL_32K_P_U0RTS 2 +#define FUNC_XTAL_32K_P_GPIO15 1 +#define FUNC_XTAL_32K_P_GPIO15_0 0 + +#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE +0x44) +#define FUNC_XTAL_32K_N_U0CTS 2 +#define FUNC_XTAL_32K_N_GPIO16 1 +#define FUNC_XTAL_32K_N_GPIO16_0 0 + +#define PERIPHS_IO_MUX_DAC_1_U (REG_IO_MUX_BASE +0x48) +#define FUNC_DAC_1_U1TXD 2 +#define FUNC_DAC_1_GPIO17 1 +#define FUNC_DAC_1_GPIO17_0 0 + +#define PERIPHS_IO_MUX_DAC_2_U (REG_IO_MUX_BASE +0x4c) +#define FUNC_DAC_2_CLK_OUT3 3 +#define FUNC_DAC_2_U1RXD 2 +#define FUNC_DAC_2_GPIO18 1 +#define FUNC_DAC_2_GPIO18_0 0 + +#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE +0x50) +#define FUNC_GPIO19_CLK_OUT2 3 +#define FUNC_GPIO19_U1RTS 2 +#define FUNC_GPIO19_GPIO19 1 +#define FUNC_GPIO19_GPIO19_0 0 + +#define PERIPHS_IO_MUX_GPIO20_U (REG_IO_MUX_BASE +0x54) +#define FUNC_GPIO20_CLK_OUT1 3 +#define FUNC_GPIO20_U1CTS 2 +#define FUNC_GPIO20_GPIO20 1 +#define FUNC_GPIO20_GPIO20_0 0 + +#define PERIPHS_IO_MUX_GPIO21_U (REG_IO_MUX_BASE +0x58) +#define FUNC_GPIO21_GPIO21 1 +#define FUNC_GPIO21_GPIO21_0 0 + +#define PERIPHS_IO_MUX_SPICS1_U (REG_IO_MUX_BASE +0x6c) +#define FUNC_SPICS1_GPIO26 1 +#define FUNC_SPICS1_SPICS1 0 + +#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE +0x70) +#define FUNC_SPIHD_GPIO27 1 +#define FUNC_SPIHD_SPIHD 0 + +#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE +0x74) +#define FUNC_SPIWP_GPIO28 1 +#define FUNC_SPIWP_SPIWP 0 + +#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE +0x78) +#define FUNC_SPICS0_GPIO29 1 +#define FUNC_SPICS0_SPICS0 0 + +#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE +0x7c) +#define FUNC_SPICLK_GPIO30 1 +#define FUNC_SPICLK_SPICLK 0 + +#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE +0x80) +#define FUNC_SPIQ_GPIO31 1 +#define FUNC_SPIQ_SPIQ 0 + +#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE +0x84) +#define FUNC_SPID_GPIO32 1 +#define FUNC_SPID_SPID 0 + +#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88) +#define FUNC_GPIO33_SPIIO4 4 +#define FUNC_GPIO33_SUBSPIHD 3 +#define FUNC_GPIO33_FSPIHD 2 +#define FUNC_GPIO33_GPIO33 1 +#define FUNC_GPIO33_GPIO33_0 0 + +#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c) +#define FUNC_GPIO34_SPIIO5 4 +#define FUNC_GPIO34_SUBSPICS0 3 +#define FUNC_GPIO34_FSPICS0 2 +#define FUNC_GPIO34_GPIO34 1 +#define FUNC_GPIO34_GPIO34_0 0 + +#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90) +#define FUNC_GPIO35_SPIIO6 4 +#define FUNC_GPIO35_SUBSPID 3 +#define FUNC_GPIO35_FSPID 2 +#define FUNC_GPIO35_GPIO35 1 +#define FUNC_GPIO35_GPIO35_0 0 + +#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94) +#define FUNC_GPIO36_SPIIO7 4 +#define FUNC_GPIO36_SUBSPICLK 3 +#define FUNC_GPIO36_FSPICLK 2 +#define FUNC_GPIO36_GPIO36 1 +#define FUNC_GPIO36_GPIO36_0 0 + +#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98) +#define FUNC_GPIO37_SPIDQS 4 +#define FUNC_GPIO37_SUBSPIQ 3 +#define FUNC_GPIO37_FSPIQ 2 +#define FUNC_GPIO37_GPIO37 1 +#define FUNC_GPIO37_GPIO37_0 0 + +#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c) +#define FUNC_GPIO38_SUBSPIWP 3 +#define FUNC_GPIO38_FSPIWP 2 +#define FUNC_GPIO38_GPIO38 1 +#define FUNC_GPIO38_GPIO38_0 0 + +#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE +0xa0) +#define FUNC_MTCK_SUBSPICS1 3 +#define FUNC_MTCK_CLK_OUT3 2 +#define FUNC_MTCK_GPIO39 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE +0xa4) +#define FUNC_MTDO_CLK_OUT2 2 +#define FUNC_MTDO_GPIO40 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE +0xa8) +#define FUNC_MTDI_CLK_OUT1 2 +#define FUNC_MTDI_GPIO41 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE +0xac) +#define FUNC_MTMS_GPIO42 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE +0xb0) +#define FUNC_U0TXD_CLK_OUT1 2 +#define FUNC_U0TXD_GPIO43 1 +#define FUNC_U0TXD_U0TXD 0 + +#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE +0xb4) +#define FUNC_U0RXD_CLK_OUT2 2 +#define FUNC_U0RXD_GPIO44 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_GPIO45_U (REG_IO_MUX_BASE +0xb8) +#define FUNC_GPIO45_GPIO45 1 +#define FUNC_GPIO45_GPIO45_0 0 + +#define PERIPHS_IO_MUX_GPIO46_U (REG_IO_MUX_BASE +0xbc) +#define FUNC_GPIO46_GPIO46 1 +#define FUNC_GPIO46_GPIO46_0 0 + +#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc) +#define IO_MUX_DATE 0xFFFFFFFF +#define IO_MUX_DATE_S 0 +#define IO_MUX_DATE_VERSION 0x1907160 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_I2CBBPLL_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_rsa.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_rsa.h new file mode 100644 index 0000000000..8d2b5d2883 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_rsa.h @@ -0,0 +1,233 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_rsa.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RSA_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RSA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RSA_M_PRIME_REG register + * Register to store M' + */ + +#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800) + +/* RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0; + * Stores M' + */ + +#define RSA_M_PRIME 0xFFFFFFFF +#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S) +#define RSA_M_PRIME_V 0xFFFFFFFF +#define RSA_M_PRIME_S 0 + +/* RSA_MODE_REG register + * RSA length mode + */ + +#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804) + +/* RSA_MODE : R/W; bitpos: [6:0]; default: 0; + * Stores the mode of modular exponentiation. + */ + +#define RSA_MODE 0x0000007F +#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S) +#define RSA_MODE_V 0x0000007F +#define RSA_MODE_S 0 + +/* RSA_CLEAN_REG register + * RSA clean register + */ + +#define RSA_CLEAN_REG (DR_REG_RSA_BASE + 0x808) + +/* RSA_CLEAN : RO; bitpos: [0]; default: 0; + * The content of this bit is 1 when memories complete initialization. + */ + +#define RSA_CLEAN (BIT(0)) +#define RSA_CLEAN_M (RSA_CLEAN_V << RSA_CLEAN_S) +#define RSA_CLEAN_V 0x00000001 +#define RSA_CLEAN_S 0 + +/* RSA_MODEXP_START_REG register + * Modular exponentiation starting bit + */ + +#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c) + +/* RSA_MODEXP_START : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start the modular exponentiation. + */ + +#define RSA_MODEXP_START (BIT(0)) +#define RSA_MODEXP_START_M (RSA_MODEXP_START_V << RSA_MODEXP_START_S) +#define RSA_MODEXP_START_V 0x00000001 +#define RSA_MODEXP_START_S 0 + +/* RSA_MODMULT_START_REG register + * Modular multiplication starting bit + */ + +#define RSA_MODMULT_START_REG (DR_REG_RSA_BASE + 0x810) + +/* RSA_MODMULT_START : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start the modular multiplication. + */ + +#define RSA_MODMULT_START (BIT(0)) +#define RSA_MODMULT_START_M (RSA_MODMULT_START_V << RSA_MODMULT_START_S) +#define RSA_MODMULT_START_V 0x00000001 +#define RSA_MODMULT_START_S 0 + +/* RSA_MULT_START_REG register + * Normal multiplicaiton starting bit + */ + +#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814) + +/* RSA_MULT_START : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start the multiplication. + */ + +#define RSA_MULT_START (BIT(0)) +#define RSA_MULT_START_M (RSA_MULT_START_V << RSA_MULT_START_S) +#define RSA_MULT_START_V 0x00000001 +#define RSA_MULT_START_S 0 + +/* RSA_IDLE_REG register + * RSA idle register + */ + +#define RSA_IDLE_REG (DR_REG_RSA_BASE + 0x818) + +/* RSA_IDLE : RO; bitpos: [0]; default: 0; + * The content of this bit is 1 when the RSA accelerator is idle. + */ + +#define RSA_IDLE (BIT(0)) +#define RSA_IDLE_M (RSA_IDLE_V << RSA_IDLE_S) +#define RSA_IDLE_V 0x00000001 +#define RSA_IDLE_S 0 + +/* RSA_CLEAR_INTERRUPT_REG register + * RSA clear interrupt register + */ + +#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81c) + +/* RSA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to clear the RSA interrupts. + */ + +#define RSA_CLEAR_INTERRUPT (BIT(0)) +#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S) +#define RSA_CLEAR_INTERRUPT_V 0x00000001 +#define RSA_CLEAR_INTERRUPT_S 0 + +/* RSA_CONSTANT_TIME_REG register + * The constant_time option + */ + +#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) + +/* RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1; + * Set this bit to 0 to enable the acceleration option of constant_time for + * modular exponentiation. Set to 1 to disable the acceleration (by default). + */ + +#define RSA_CONSTANT_TIME (BIT(0)) +#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S) +#define RSA_CONSTANT_TIME_V 0x00000001 +#define RSA_CONSTANT_TIME_S 0 + +/* RSA_SEARCH_ENABLE_REG register + * The search option + */ + +#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) + +/* RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable the acceleration option of search for modular + * exponentiation. Set to 0 to disable the acceleration (by default). + */ + +#define RSA_SEARCH_ENABLE (BIT(0)) +#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S) +#define RSA_SEARCH_ENABLE_V 0x00000001 +#define RSA_SEARCH_ENABLE_S 0 + +/* RSA_SEARCH_POS_REG register + * The search position + */ + +#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) + +/* RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0; + * Is used to configure the starting address when the acceleration option of + * search is used. + */ + +#define RSA_SEARCH_POS 0x00000FFF +#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S) +#define RSA_SEARCH_POS_V 0x00000FFF +#define RSA_SEARCH_POS_S 0 + +/* RSA_INTERRUPT_ENA_REG register + * RSA interrupt enable register + */ + +#define RSA_INTERRUPT_ENA_REG (DR_REG_RSA_BASE + 0x82c) + +/* RSA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable the RSA interrupt. This option is enabled by + * default. + */ + +#define RSA_INTERRUPT_ENA (BIT(0)) +#define RSA_INTERRUPT_ENA_M (RSA_INTERRUPT_ENA_V << RSA_INTERRUPT_ENA_S) +#define RSA_INTERRUPT_ENA_V 0x00000001 +#define RSA_INTERRUPT_ENA_S 0 + +/* RSA_DATE_REG register + * Version control register + */ + +#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830) + +/* RSA_DATE : R/W; bitpos: [29:0]; default: 538510373; + * Version control register + */ + +#define RSA_DATE 0x3FFFFFFF +#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S) +#define RSA_DATE_V 0x3FFFFFFF +#define RSA_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RSA_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_rtc_io.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtc_io.h new file mode 100644 index 0000000000..e0f6f15130 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtc_io.h @@ -0,0 +1,3704 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_rtc_io.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTCIO_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTCIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RTCIO_RTC_GPIO_OUT_REG register + * RTC GPIO output register + */ + +#define RTCIO_RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) + +/* RTCIO_GPIO_OUT_DATA : R/W; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corre- + * sponds to GPIO1, etc. + */ + +#define RTCIO_GPIO_OUT_DATA 0x003FFFFF +#define RTCIO_GPIO_OUT_DATA_M (RTCIO_GPIO_OUT_DATA_V << RTCIO_GPIO_OUT_DATA_S) +#define RTCIO_GPIO_OUT_DATA_V 0x003FFFFF +#define RTCIO_GPIO_OUT_DATA_S 10 + +/* RTCIO_RTC_GPIO_OUT_W1TS_REG register + * RTC GPIO output bit set register + */ + +#define RTCIO_RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) + +/* RTCIO_GPIO_OUT_DATA_W1TS : WO; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 output set register. If the value 1 is written to a bit here, + * the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be set to 1. + * Recommended operation: use this register to set RTCIO_RTC_GPIO_OUT_REG. + */ + +#define RTCIO_GPIO_OUT_DATA_W1TS 0x003FFFFF +#define RTCIO_GPIO_OUT_DATA_W1TS_M (RTCIO_GPIO_OUT_DATA_W1TS_V << RTCIO_GPIO_OUT_DATA_W1TS_S) +#define RTCIO_GPIO_OUT_DATA_W1TS_V 0x003FFFFF +#define RTCIO_GPIO_OUT_DATA_W1TS_S 10 + +/* RTCIO_RTC_GPIO_OUT_W1TC_REG register + * RTC GPIO output bit clear register + */ + +#define RTCIO_RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) + +/* RTCIO_GPIO_OUT_DATA_W1TC : WO; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 output clear register. If the value 1 is written to a bit + * here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. + * Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG. + */ + +#define RTCIO_GPIO_OUT_DATA_W1TC 0x003FFFFF +#define RTCIO_GPIO_OUT_DATA_W1TC_M (RTCIO_GPIO_OUT_DATA_W1TC_V << RTCIO_GPIO_OUT_DATA_W1TC_S) +#define RTCIO_GPIO_OUT_DATA_W1TC_V 0x003FFFFF +#define RTCIO_GPIO_OUT_DATA_W1TC_S 10 + +/* RTCIO_RTC_GPIO_ENABLE_REG register + * RTC GPIO output enable register + */ + +#define RTCIO_RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xc) + +/* RTCIO_REG_RTCIO_REG_GPIO_ENABLE : R/W; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds + * to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output. + */ + +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE 0x003FFFFF +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_M (RTCIO_REG_RTCIO_REG_GPIO_ENABLE_V << RTCIO_REG_RTCIO_REG_GPIO_ENABLE_S) +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_V 0x003FFFFF +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_S 10 + +/* RTCIO_RTC_GPIO_ENABLE_W1TS_REG register + * RTC GPIO output enable bit set register + */ + +#define RTCIO_RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) + +/* RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TS : WO; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit + * here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to + * 1. Recommended operation: use this register to set + * RTCIO_RTC_GPIO_ENABLE_REG. + */ + +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TS 0x003FFFFF +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TS_M (RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TS_V << RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TS_S) +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TS_V 0x003FFFFF +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TS_S 10 + +/* RTCIO_RTC_GPIO_ENABLE_W1TC_REG register + * RTC GPIO output enable bit clear register + */ + +#define RTCIO_RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) + +/* RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TC : WO; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 output enable clear register. If the value 1 is written to a + * bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be + * cleared. Recom- mended operation: use this register to clear + * RTCIO_RTC_GPIO_ENABLE_REG. + */ + +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TC 0x003FFFFF +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TC_M (RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TC_V << RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TC_S) +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TC_V 0x003FFFFF +#define RTCIO_REG_RTCIO_REG_GPIO_ENABLE_W1TC_S 10 + +/* RTCIO_RTC_GPIO_STATUS_REG register + * RTC GPIO interrupt status register + */ + +#define RTCIO_RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) + +/* RTCIO_GPIO_STATUS_INT : R/W; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 interrupt status register. Bit10 corresponds to GPIO0, bit11 + * corresponds to GPIO1, etc. This register should be used together with RT- + * CIO_RTC_GPIO_PINn_INT_TYPE in RTCIO_RTC_GPIO_PINn_REG. 0: no interrupt; + * 1: corresponding interrupt. + */ + +#define RTCIO_GPIO_STATUS_INT 0x003FFFFF +#define RTCIO_GPIO_STATUS_INT_M (RTCIO_GPIO_STATUS_INT_V << RTCIO_GPIO_STATUS_INT_S) +#define RTCIO_GPIO_STATUS_INT_V 0x003FFFFF +#define RTCIO_GPIO_STATUS_INT_S 10 + +/* RTCIO_RTC_GPIO_STATUS_W1TS_REG register + * RTC GPIO interrupt status bit set register + */ + +#define RTCIO_RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1c) + +/* RTCIO_GPIO_STATUS_INT_W1TS : WO; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 interrupt set register. If the value 1 is written to a bit + * here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be set to 1. + * Recommended operation: use this register to set RTCIO_GPIO_STATUS_INT. + */ + +#define RTCIO_GPIO_STATUS_INT_W1TS 0x003FFFFF +#define RTCIO_GPIO_STATUS_INT_W1TS_M (RTCIO_GPIO_STATUS_INT_W1TS_V << RTCIO_GPIO_STATUS_INT_W1TS_S) +#define RTCIO_GPIO_STATUS_INT_W1TS_V 0x003FFFFF +#define RTCIO_GPIO_STATUS_INT_W1TS_S 10 + +/* RTCIO_RTC_GPIO_STATUS_W1TC_REG register + * RTC GPIO interrupt status bit clear register + */ + +#define RTCIO_RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) + +/* RTCIO_GPIO_STATUS_INT_W1TC : WO; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 interrupt clear register. If the value 1 is written to a bit + * here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be cleared. + * Recommended operation: use this register to clear RTCIO_GPIO_STATUS_INT. + */ + +#define RTCIO_GPIO_STATUS_INT_W1TC 0x003FFFFF +#define RTCIO_GPIO_STATUS_INT_W1TC_M (RTCIO_GPIO_STATUS_INT_W1TC_V << RTCIO_GPIO_STATUS_INT_W1TC_S) +#define RTCIO_GPIO_STATUS_INT_W1TC_V 0x003FFFFF +#define RTCIO_GPIO_STATUS_INT_W1TC_S 10 + +/* RTCIO_RTC_GPIO_IN_REG register + * RTC GPIO input register + */ + +#define RTCIO_RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) + +/* RTCIO_GPIO_IN_NEXT : RO; bitpos: [31:10]; default: 0; + * GPIO0 ~ 21 input value. Bit10 corresponds to GPIO0, bit11 corresponds to + * GPIO1, etc. Each bit represents a pad input value, 1 for high level, and + * 0 for low level. + */ + +#define RTCIO_GPIO_IN_NEXT 0x003FFFFF +#define RTCIO_GPIO_IN_NEXT_M (RTCIO_GPIO_IN_NEXT_V << RTCIO_GPIO_IN_NEXT_S) +#define RTCIO_GPIO_IN_NEXT_V 0x003FFFFF +#define RTCIO_GPIO_IN_NEXT_S 10 + +/* RTCIO_RTC_GPIO_PIN0_REG register + * RTC configuration for pin 0 + */ + +#define RTCIO_RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28) + +/* RTCIO_GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN0_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN0_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN0_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN0_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN0_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN0_INT_TYPE_M (RTCIO_GPIO_PIN0_INT_TYPE_V << RTCIO_GPIO_PIN0_INT_TYPE_S) +#define RTCIO_GPIO_PIN0_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN0_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN0_PAD_DRIVER_M (RTCIO_GPIO_PIN0_PAD_DRIVER_V << RTCIO_GPIO_PIN0_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN0_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN0_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN1_REG register + * RTC configuration for pin 1 + */ + +#define RTCIO_RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2c) + +/* RTCIO_GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN1_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN1_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN1_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN1_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN1_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN1_INT_TYPE_M (RTCIO_GPIO_PIN1_INT_TYPE_V << RTCIO_GPIO_PIN1_INT_TYPE_S) +#define RTCIO_GPIO_PIN1_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN1_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN1_PAD_DRIVER_M (RTCIO_GPIO_PIN1_PAD_DRIVER_V << RTCIO_GPIO_PIN1_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN1_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN1_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN2_REG register + * RTC configuration for pin 2 + */ + +#define RTCIO_RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30) + +/* RTCIO_GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN2_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN2_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN2_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN2_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN2_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN2_INT_TYPE_M (RTCIO_GPIO_PIN2_INT_TYPE_V << RTCIO_GPIO_PIN2_INT_TYPE_S) +#define RTCIO_GPIO_PIN2_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN2_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN2_PAD_DRIVER_M (RTCIO_GPIO_PIN2_PAD_DRIVER_V << RTCIO_GPIO_PIN2_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN2_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN2_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN3_REG register + * RTC configuration for pin 3 + */ + +#define RTCIO_RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34) + +/* RTCIO_GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN3_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN3_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN3_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN3_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN3_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN3_INT_TYPE_M (RTCIO_GPIO_PIN3_INT_TYPE_V << RTCIO_GPIO_PIN3_INT_TYPE_S) +#define RTCIO_GPIO_PIN3_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN3_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN3_PAD_DRIVER_M (RTCIO_GPIO_PIN3_PAD_DRIVER_V << RTCIO_GPIO_PIN3_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN3_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN3_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN4_REG register + * RTC configuration for pin 4 + */ + +#define RTCIO_RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38) + +/* RTCIO_GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN4_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN4_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN4_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN4_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN4_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN4_INT_TYPE_M (RTCIO_GPIO_PIN4_INT_TYPE_V << RTCIO_GPIO_PIN4_INT_TYPE_S) +#define RTCIO_GPIO_PIN4_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN4_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN4_PAD_DRIVER_M (RTCIO_GPIO_PIN4_PAD_DRIVER_V << RTCIO_GPIO_PIN4_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN4_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN4_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN5_REG register + * RTC configuration for pin 5 + */ + +#define RTCIO_RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3c) + +/* RTCIO_GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN5_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN5_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN5_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN5_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN5_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN5_INT_TYPE_M (RTCIO_GPIO_PIN5_INT_TYPE_V << RTCIO_GPIO_PIN5_INT_TYPE_S) +#define RTCIO_GPIO_PIN5_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN5_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN5_PAD_DRIVER_M (RTCIO_GPIO_PIN5_PAD_DRIVER_V << RTCIO_GPIO_PIN5_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN5_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN5_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN6_REG register + * RTC configuration for pin 6 + */ + +#define RTCIO_RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40) + +/* RTCIO_GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN6_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN6_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN6_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN6_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN6_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN6_INT_TYPE_M (RTCIO_GPIO_PIN6_INT_TYPE_V << RTCIO_GPIO_PIN6_INT_TYPE_S) +#define RTCIO_GPIO_PIN6_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN6_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN6_PAD_DRIVER_M (RTCIO_GPIO_PIN6_PAD_DRIVER_V << RTCIO_GPIO_PIN6_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN6_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN6_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN7_REG register + * RTC configuration for pin 7 + */ + +#define RTCIO_RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44) + +/* RTCIO_GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN7_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN7_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN7_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN7_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN7_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN7_INT_TYPE_M (RTCIO_GPIO_PIN7_INT_TYPE_V << RTCIO_GPIO_PIN7_INT_TYPE_S) +#define RTCIO_GPIO_PIN7_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN7_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN7_PAD_DRIVER_M (RTCIO_GPIO_PIN7_PAD_DRIVER_V << RTCIO_GPIO_PIN7_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN7_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN7_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN8_REG register + * RTC configuration for pin 8 + */ + +#define RTCIO_RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48) + +/* RTCIO_GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN8_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN8_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN8_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN8_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN8_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN8_INT_TYPE_M (RTCIO_GPIO_PIN8_INT_TYPE_V << RTCIO_GPIO_PIN8_INT_TYPE_S) +#define RTCIO_GPIO_PIN8_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN8_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN8_PAD_DRIVER_M (RTCIO_GPIO_PIN8_PAD_DRIVER_V << RTCIO_GPIO_PIN8_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN8_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN8_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN9_REG register + * RTC configuration for pin 9 + */ + +#define RTCIO_RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4c) + +/* RTCIO_GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN9_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN9_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN9_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN9_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN9_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN9_INT_TYPE_M (RTCIO_GPIO_PIN9_INT_TYPE_V << RTCIO_GPIO_PIN9_INT_TYPE_S) +#define RTCIO_GPIO_PIN9_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN9_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN9_PAD_DRIVER_M (RTCIO_GPIO_PIN9_PAD_DRIVER_V << RTCIO_GPIO_PIN9_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN9_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN9_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN10_REG register + * RTC configuration for pin 10 + */ + +#define RTCIO_RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50) + +/* RTCIO_GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN10_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN10_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN10_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN10_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN10_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN10_INT_TYPE_M (RTCIO_GPIO_PIN10_INT_TYPE_V << RTCIO_GPIO_PIN10_INT_TYPE_S) +#define RTCIO_GPIO_PIN10_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN10_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN10_PAD_DRIVER_M (RTCIO_GPIO_PIN10_PAD_DRIVER_V << RTCIO_GPIO_PIN10_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN10_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN10_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN11_REG register + * RTC configuration for pin 11 + */ + +#define RTCIO_RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54) + +/* RTCIO_GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN11_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN11_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN11_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN11_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN11_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN11_INT_TYPE_M (RTCIO_GPIO_PIN11_INT_TYPE_V << RTCIO_GPIO_PIN11_INT_TYPE_S) +#define RTCIO_GPIO_PIN11_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN11_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN11_PAD_DRIVER_M (RTCIO_GPIO_PIN11_PAD_DRIVER_V << RTCIO_GPIO_PIN11_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN11_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN11_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN12_REG register + * RTC configuration for pin 12 + */ + +#define RTCIO_RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58) + +/* RTCIO_GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN12_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN12_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN12_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN12_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN12_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN12_INT_TYPE_M (RTCIO_GPIO_PIN12_INT_TYPE_V << RTCIO_GPIO_PIN12_INT_TYPE_S) +#define RTCIO_GPIO_PIN12_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN12_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN12_PAD_DRIVER_M (RTCIO_GPIO_PIN12_PAD_DRIVER_V << RTCIO_GPIO_PIN12_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN12_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN12_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN13_REG register + * RTC configuration for pin 13 + */ + +#define RTCIO_RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5c) + +/* RTCIO_GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN13_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN13_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN13_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN13_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN13_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN13_INT_TYPE_M (RTCIO_GPIO_PIN13_INT_TYPE_V << RTCIO_GPIO_PIN13_INT_TYPE_S) +#define RTCIO_GPIO_PIN13_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN13_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN13_PAD_DRIVER_M (RTCIO_GPIO_PIN13_PAD_DRIVER_V << RTCIO_GPIO_PIN13_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN13_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN13_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN14_REG register + * RTC configuration for pin 14 + */ + +#define RTCIO_RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60) + +/* RTCIO_GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN14_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN14_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN14_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN14_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN14_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN14_INT_TYPE_M (RTCIO_GPIO_PIN14_INT_TYPE_V << RTCIO_GPIO_PIN14_INT_TYPE_S) +#define RTCIO_GPIO_PIN14_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN14_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN14_PAD_DRIVER_M (RTCIO_GPIO_PIN14_PAD_DRIVER_V << RTCIO_GPIO_PIN14_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN14_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN14_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN15_REG register + * RTC configuration for pin 15 + */ + +#define RTCIO_RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64) + +/* RTCIO_GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN15_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN15_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN15_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN15_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN15_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN15_INT_TYPE_M (RTCIO_GPIO_PIN15_INT_TYPE_V << RTCIO_GPIO_PIN15_INT_TYPE_S) +#define RTCIO_GPIO_PIN15_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN15_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN15_PAD_DRIVER_M (RTCIO_GPIO_PIN15_PAD_DRIVER_V << RTCIO_GPIO_PIN15_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN15_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN15_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN16_REG register + * RTC configuration for pin 16 + */ + +#define RTCIO_RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68) + +/* RTCIO_GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN16_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN16_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN16_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN16_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN16_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN16_INT_TYPE_M (RTCIO_GPIO_PIN16_INT_TYPE_V << RTCIO_GPIO_PIN16_INT_TYPE_S) +#define RTCIO_GPIO_PIN16_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN16_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN16_PAD_DRIVER_M (RTCIO_GPIO_PIN16_PAD_DRIVER_V << RTCIO_GPIO_PIN16_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN16_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN16_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN17_REG register + * RTC configuration for pin 17 + */ + +#define RTCIO_RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6c) + +/* RTCIO_GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN17_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN17_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN17_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN17_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN17_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN17_INT_TYPE_M (RTCIO_GPIO_PIN17_INT_TYPE_V << RTCIO_GPIO_PIN17_INT_TYPE_S) +#define RTCIO_GPIO_PIN17_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN17_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN17_PAD_DRIVER_M (RTCIO_GPIO_PIN17_PAD_DRIVER_V << RTCIO_GPIO_PIN17_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN17_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN17_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN18_REG register + * RTC configuration for pin 18 + */ + +#define RTCIO_RTC_GPIO_PIN18_REG (DR_REG_RTCIO_BASE + 0x70) + +/* RTCIO_GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN18_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN18_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN18_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN18_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN18_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN18_INT_TYPE_M (RTCIO_GPIO_PIN18_INT_TYPE_V << RTCIO_GPIO_PIN18_INT_TYPE_S) +#define RTCIO_GPIO_PIN18_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN18_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN18_PAD_DRIVER_M (RTCIO_GPIO_PIN18_PAD_DRIVER_V << RTCIO_GPIO_PIN18_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN18_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN18_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN19_REG register + * RTC configuration for pin 19 + */ + +#define RTCIO_RTC_GPIO_PIN19_REG (DR_REG_RTCIO_BASE + 0x74) + +/* RTCIO_GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN19_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN19_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN19_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN19_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN19_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN19_INT_TYPE_M (RTCIO_GPIO_PIN19_INT_TYPE_V << RTCIO_GPIO_PIN19_INT_TYPE_S) +#define RTCIO_GPIO_PIN19_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN19_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN19_PAD_DRIVER_M (RTCIO_GPIO_PIN19_PAD_DRIVER_V << RTCIO_GPIO_PIN19_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN19_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN19_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN20_REG register + * RTC configuration for pin 20 + */ + +#define RTCIO_RTC_GPIO_PIN20_REG (DR_REG_RTCIO_BASE + 0x78) + +/* RTCIO_GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN20_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN20_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN20_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN20_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN20_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN20_INT_TYPE_M (RTCIO_GPIO_PIN20_INT_TYPE_V << RTCIO_GPIO_PIN20_INT_TYPE_S) +#define RTCIO_GPIO_PIN20_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN20_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN20_PAD_DRIVER_M (RTCIO_GPIO_PIN20_PAD_DRIVER_V << RTCIO_GPIO_PIN20_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN20_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN20_PAD_DRIVER_S 2 + +/* RTCIO_RTC_GPIO_PIN21_REG register + * RTC configuration for pin 21 + */ + +#define RTCIO_RTC_GPIO_PIN21_REG (DR_REG_RTCIO_BASE + 0x7c) + +/* RTCIO_GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + */ + +#define RTCIO_GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define RTCIO_GPIO_PIN21_WAKEUP_ENABLE_M (RTCIO_GPIO_PIN21_WAKEUP_ENABLE_V << RTCIO_GPIO_PIN21_WAKEUP_ENABLE_S) +#define RTCIO_GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001 +#define RTCIO_GPIO_PIN21_WAKEUP_ENABLE_S 10 + +/* RTCIO_GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * GPIO interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge + * trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level + * trigger; 5: high level trigger. + */ + +#define RTCIO_GPIO_PIN21_INT_TYPE 0x00000007 +#define RTCIO_GPIO_PIN21_INT_TYPE_M (RTCIO_GPIO_PIN21_INT_TYPE_V << RTCIO_GPIO_PIN21_INT_TYPE_S) +#define RTCIO_GPIO_PIN21_INT_TYPE_V 0x00000007 +#define RTCIO_GPIO_PIN21_INT_TYPE_S 7 + +/* RTCIO_GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * Pad driver selection. 0: normal output; 1: open drain. + */ + +#define RTCIO_GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define RTCIO_GPIO_PIN21_PAD_DRIVER_M (RTCIO_GPIO_PIN21_PAD_DRIVER_V << RTCIO_GPIO_PIN21_PAD_DRIVER_S) +#define RTCIO_GPIO_PIN21_PAD_DRIVER_V 0x00000001 +#define RTCIO_GPIO_PIN21_PAD_DRIVER_S 2 + +/* RTCIO_RTC_DEBUG_SEL_REG register + * RTC debug select register + */ + +#define RTCIO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x80) + +/* RTCIO_RTC_DEBUG_12M_NO_GATING : R/W; bitpos: [25]; default: 0; */ + +#define RTCIO_RTC_DEBUG_12M_NO_GATING (BIT(25)) +#define RTCIO_RTC_DEBUG_12M_NO_GATING_M (RTCIO_RTC_DEBUG_12M_NO_GATING_V << RTCIO_RTC_DEBUG_12M_NO_GATING_S) +#define RTCIO_RTC_DEBUG_12M_NO_GATING_V 0x00000001 +#define RTCIO_RTC_DEBUG_12M_NO_GATING_S 25 + +/* RTCIO_RTC_DEBUG_SEL4 : R/W; bitpos: [24:20]; default: 0; */ + +#define RTCIO_RTC_DEBUG_SEL4 0x0000001F +#define RTCIO_RTC_DEBUG_SEL4_M (RTCIO_RTC_DEBUG_SEL4_V << RTCIO_RTC_DEBUG_SEL4_S) +#define RTCIO_RTC_DEBUG_SEL4_V 0x0000001F +#define RTCIO_RTC_DEBUG_SEL4_S 20 + +/* RTCIO_RTC_DEBUG_SEL3 : R/W; bitpos: [19:15]; default: 0; */ + +#define RTCIO_RTC_DEBUG_SEL3 0x0000001F +#define RTCIO_RTC_DEBUG_SEL3_M (RTCIO_RTC_DEBUG_SEL3_V << RTCIO_RTC_DEBUG_SEL3_S) +#define RTCIO_RTC_DEBUG_SEL3_V 0x0000001F +#define RTCIO_RTC_DEBUG_SEL3_S 15 + +/* RTCIO_RTC_DEBUG_SEL2 : R/W; bitpos: [14:10]; default: 0; */ + +#define RTCIO_RTC_DEBUG_SEL2 0x0000001F +#define RTCIO_RTC_DEBUG_SEL2_M (RTCIO_RTC_DEBUG_SEL2_V << RTCIO_RTC_DEBUG_SEL2_S) +#define RTCIO_RTC_DEBUG_SEL2_V 0x0000001F +#define RTCIO_RTC_DEBUG_SEL2_S 10 + +/* RTCIO_RTC_DEBUG_SEL1 : R/W; bitpos: [9:5]; default: 0; */ + +#define RTCIO_RTC_DEBUG_SEL1 0x0000001F +#define RTCIO_RTC_DEBUG_SEL1_M (RTCIO_RTC_DEBUG_SEL1_V << RTCIO_RTC_DEBUG_SEL1_S) +#define RTCIO_RTC_DEBUG_SEL1_V 0x0000001F +#define RTCIO_RTC_DEBUG_SEL1_S 5 + +/* RTCIO_RTC_DEBUG_SEL0 : R/W; bitpos: [4:0]; default: 0; */ + +#define RTCIO_RTC_DEBUG_SEL0 0x0000001F +#define RTCIO_RTC_DEBUG_SEL0_M (RTCIO_RTC_DEBUG_SEL0_V << RTCIO_RTC_DEBUG_SEL0_S) +#define RTCIO_RTC_DEBUG_SEL0_V 0x0000001F +#define RTCIO_RTC_DEBUG_SEL0_S 0 + +/* RTCIO_TOUCH_PAD0_REG register + * Touch pad 0 configuration register + */ + +#define RTCIO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x84) + +/* RTCIO_TOUCH_PAD0_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD0_DRV 0x00000003 +#define RTCIO_TOUCH_PAD0_DRV_M (RTCIO_TOUCH_PAD0_DRV_V << RTCIO_TOUCH_PAD0_DRV_S) +#define RTCIO_TOUCH_PAD0_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD0_DRV_S 29 + +/* RTCIO_TOUCH_PAD0_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD0_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD0_RDE_M (RTCIO_TOUCH_PAD0_RDE_V << RTCIO_TOUCH_PAD0_RDE_S) +#define RTCIO_TOUCH_PAD0_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD0_RDE_S 28 + +/* RTCIO_TOUCH_PAD0_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD0_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD0_RUE_M (RTCIO_TOUCH_PAD0_RUE_V << RTCIO_TOUCH_PAD0_RUE_S) +#define RTCIO_TOUCH_PAD0_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD0_RUE_S 27 + +/* RTCIO_TOUCH_PAD0_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD0_DAC 0x00000007 +#define RTCIO_TOUCH_PAD0_DAC_M (RTCIO_TOUCH_PAD0_DAC_V << RTCIO_TOUCH_PAD0_DAC_S) +#define RTCIO_TOUCH_PAD0_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD0_DAC_S 23 + +/* RTCIO_TOUCH_PAD0_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD0_START (BIT(22)) +#define RTCIO_TOUCH_PAD0_START_M (RTCIO_TOUCH_PAD0_START_V << RTCIO_TOUCH_PAD0_START_S) +#define RTCIO_TOUCH_PAD0_START_V 0x00000001 +#define RTCIO_TOUCH_PAD0_START_S 22 + +/* RTCIO_TOUCH_PAD0_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD0_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD0_TIE_OPT_M (RTCIO_TOUCH_PAD0_TIE_OPT_V << RTCIO_TOUCH_PAD0_TIE_OPT_S) +#define RTCIO_TOUCH_PAD0_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD0_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD0_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD0_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD0_XPD_M (RTCIO_TOUCH_PAD0_XPD_V << RTCIO_TOUCH_PAD0_XPD_S) +#define RTCIO_TOUCH_PAD0_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD0_XPD_S 20 + +/* RTCIO_TOUCH_PAD0_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD0_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD0_MUX_SEL_M (RTCIO_TOUCH_PAD0_MUX_SEL_V << RTCIO_TOUCH_PAD0_MUX_SEL_S) +#define RTCIO_TOUCH_PAD0_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD0_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD0_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD0_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD0_FUN_SEL_M (RTCIO_TOUCH_PAD0_FUN_SEL_V << RTCIO_TOUCH_PAD0_FUN_SEL_S) +#define RTCIO_TOUCH_PAD0_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD0_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD0_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD0_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD0_SLP_SEL_M (RTCIO_TOUCH_PAD0_SLP_SEL_V << RTCIO_TOUCH_PAD0_SLP_SEL_S) +#define RTCIO_TOUCH_PAD0_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD0_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD0_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD0_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD0_SLP_IE_M (RTCIO_TOUCH_PAD0_SLP_IE_V << RTCIO_TOUCH_PAD0_SLP_IE_S) +#define RTCIO_TOUCH_PAD0_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD0_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD0_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD0_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD0_SLP_OE_M (RTCIO_TOUCH_PAD0_SLP_OE_V << RTCIO_TOUCH_PAD0_SLP_OE_S) +#define RTCIO_TOUCH_PAD0_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD0_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD0_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD0_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD0_FUN_IE_M (RTCIO_TOUCH_PAD0_FUN_IE_V << RTCIO_TOUCH_PAD0_FUN_IE_S) +#define RTCIO_TOUCH_PAD0_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD0_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD1_REG register + * Touch pad 1 configuration register + */ + +#define RTCIO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x88) + +/* RTCIO_TOUCH_PAD1_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD1_DRV 0x00000003 +#define RTCIO_TOUCH_PAD1_DRV_M (RTCIO_TOUCH_PAD1_DRV_V << RTCIO_TOUCH_PAD1_DRV_S) +#define RTCIO_TOUCH_PAD1_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD1_DRV_S 29 + +/* RTCIO_TOUCH_PAD1_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD1_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD1_RDE_M (RTCIO_TOUCH_PAD1_RDE_V << RTCIO_TOUCH_PAD1_RDE_S) +#define RTCIO_TOUCH_PAD1_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD1_RDE_S 28 + +/* RTCIO_TOUCH_PAD1_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD1_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD1_RUE_M (RTCIO_TOUCH_PAD1_RUE_V << RTCIO_TOUCH_PAD1_RUE_S) +#define RTCIO_TOUCH_PAD1_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD1_RUE_S 27 + +/* RTCIO_TOUCH_PAD1_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD1_DAC 0x00000007 +#define RTCIO_TOUCH_PAD1_DAC_M (RTCIO_TOUCH_PAD1_DAC_V << RTCIO_TOUCH_PAD1_DAC_S) +#define RTCIO_TOUCH_PAD1_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD1_DAC_S 23 + +/* RTCIO_TOUCH_PAD1_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD1_START (BIT(22)) +#define RTCIO_TOUCH_PAD1_START_M (RTCIO_TOUCH_PAD1_START_V << RTCIO_TOUCH_PAD1_START_S) +#define RTCIO_TOUCH_PAD1_START_V 0x00000001 +#define RTCIO_TOUCH_PAD1_START_S 22 + +/* RTCIO_TOUCH_PAD1_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD1_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD1_TIE_OPT_M (RTCIO_TOUCH_PAD1_TIE_OPT_V << RTCIO_TOUCH_PAD1_TIE_OPT_S) +#define RTCIO_TOUCH_PAD1_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD1_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD1_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD1_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD1_XPD_M (RTCIO_TOUCH_PAD1_XPD_V << RTCIO_TOUCH_PAD1_XPD_S) +#define RTCIO_TOUCH_PAD1_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD1_XPD_S 20 + +/* RTCIO_TOUCH_PAD1_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD1_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD1_MUX_SEL_M (RTCIO_TOUCH_PAD1_MUX_SEL_V << RTCIO_TOUCH_PAD1_MUX_SEL_S) +#define RTCIO_TOUCH_PAD1_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD1_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD1_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD1_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD1_FUN_SEL_M (RTCIO_TOUCH_PAD1_FUN_SEL_V << RTCIO_TOUCH_PAD1_FUN_SEL_S) +#define RTCIO_TOUCH_PAD1_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD1_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD1_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD1_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD1_SLP_SEL_M (RTCIO_TOUCH_PAD1_SLP_SEL_V << RTCIO_TOUCH_PAD1_SLP_SEL_S) +#define RTCIO_TOUCH_PAD1_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD1_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD1_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD1_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD1_SLP_IE_M (RTCIO_TOUCH_PAD1_SLP_IE_V << RTCIO_TOUCH_PAD1_SLP_IE_S) +#define RTCIO_TOUCH_PAD1_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD1_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD1_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD1_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD1_SLP_OE_M (RTCIO_TOUCH_PAD1_SLP_OE_V << RTCIO_TOUCH_PAD1_SLP_OE_S) +#define RTCIO_TOUCH_PAD1_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD1_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD1_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD1_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD1_FUN_IE_M (RTCIO_TOUCH_PAD1_FUN_IE_V << RTCIO_TOUCH_PAD1_FUN_IE_S) +#define RTCIO_TOUCH_PAD1_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD1_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD2_REG register + * Touch pad 2 configuration register + */ + +#define RTCIO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x8c) + +/* RTCIO_TOUCH_PAD2_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD2_DRV 0x00000003 +#define RTCIO_TOUCH_PAD2_DRV_M (RTCIO_TOUCH_PAD2_DRV_V << RTCIO_TOUCH_PAD2_DRV_S) +#define RTCIO_TOUCH_PAD2_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD2_DRV_S 29 + +/* RTCIO_TOUCH_PAD2_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD2_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD2_RDE_M (RTCIO_TOUCH_PAD2_RDE_V << RTCIO_TOUCH_PAD2_RDE_S) +#define RTCIO_TOUCH_PAD2_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD2_RDE_S 28 + +/* RTCIO_TOUCH_PAD2_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD2_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD2_RUE_M (RTCIO_TOUCH_PAD2_RUE_V << RTCIO_TOUCH_PAD2_RUE_S) +#define RTCIO_TOUCH_PAD2_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD2_RUE_S 27 + +/* RTCIO_TOUCH_PAD2_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD2_DAC 0x00000007 +#define RTCIO_TOUCH_PAD2_DAC_M (RTCIO_TOUCH_PAD2_DAC_V << RTCIO_TOUCH_PAD2_DAC_S) +#define RTCIO_TOUCH_PAD2_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD2_DAC_S 23 + +/* RTCIO_TOUCH_PAD2_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD2_START (BIT(22)) +#define RTCIO_TOUCH_PAD2_START_M (RTCIO_TOUCH_PAD2_START_V << RTCIO_TOUCH_PAD2_START_S) +#define RTCIO_TOUCH_PAD2_START_V 0x00000001 +#define RTCIO_TOUCH_PAD2_START_S 22 + +/* RTCIO_TOUCH_PAD2_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD2_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD2_TIE_OPT_M (RTCIO_TOUCH_PAD2_TIE_OPT_V << RTCIO_TOUCH_PAD2_TIE_OPT_S) +#define RTCIO_TOUCH_PAD2_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD2_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD2_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD2_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD2_XPD_M (RTCIO_TOUCH_PAD2_XPD_V << RTCIO_TOUCH_PAD2_XPD_S) +#define RTCIO_TOUCH_PAD2_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD2_XPD_S 20 + +/* RTCIO_TOUCH_PAD2_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD2_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD2_MUX_SEL_M (RTCIO_TOUCH_PAD2_MUX_SEL_V << RTCIO_TOUCH_PAD2_MUX_SEL_S) +#define RTCIO_TOUCH_PAD2_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD2_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD2_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD2_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD2_FUN_SEL_M (RTCIO_TOUCH_PAD2_FUN_SEL_V << RTCIO_TOUCH_PAD2_FUN_SEL_S) +#define RTCIO_TOUCH_PAD2_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD2_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD2_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD2_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD2_SLP_SEL_M (RTCIO_TOUCH_PAD2_SLP_SEL_V << RTCIO_TOUCH_PAD2_SLP_SEL_S) +#define RTCIO_TOUCH_PAD2_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD2_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD2_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD2_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD2_SLP_IE_M (RTCIO_TOUCH_PAD2_SLP_IE_V << RTCIO_TOUCH_PAD2_SLP_IE_S) +#define RTCIO_TOUCH_PAD2_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD2_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD2_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD2_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD2_SLP_OE_M (RTCIO_TOUCH_PAD2_SLP_OE_V << RTCIO_TOUCH_PAD2_SLP_OE_S) +#define RTCIO_TOUCH_PAD2_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD2_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD2_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD2_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD2_FUN_IE_M (RTCIO_TOUCH_PAD2_FUN_IE_V << RTCIO_TOUCH_PAD2_FUN_IE_S) +#define RTCIO_TOUCH_PAD2_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD2_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD3_REG register + * Touch pad 3 configuration register + */ + +#define RTCIO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0x90) + +/* RTCIO_TOUCH_PAD3_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD3_DRV 0x00000003 +#define RTCIO_TOUCH_PAD3_DRV_M (RTCIO_TOUCH_PAD3_DRV_V << RTCIO_TOUCH_PAD3_DRV_S) +#define RTCIO_TOUCH_PAD3_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD3_DRV_S 29 + +/* RTCIO_TOUCH_PAD3_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD3_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD3_RDE_M (RTCIO_TOUCH_PAD3_RDE_V << RTCIO_TOUCH_PAD3_RDE_S) +#define RTCIO_TOUCH_PAD3_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD3_RDE_S 28 + +/* RTCIO_TOUCH_PAD3_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD3_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD3_RUE_M (RTCIO_TOUCH_PAD3_RUE_V << RTCIO_TOUCH_PAD3_RUE_S) +#define RTCIO_TOUCH_PAD3_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD3_RUE_S 27 + +/* RTCIO_TOUCH_PAD3_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD3_DAC 0x00000007 +#define RTCIO_TOUCH_PAD3_DAC_M (RTCIO_TOUCH_PAD3_DAC_V << RTCIO_TOUCH_PAD3_DAC_S) +#define RTCIO_TOUCH_PAD3_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD3_DAC_S 23 + +/* RTCIO_TOUCH_PAD3_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD3_START (BIT(22)) +#define RTCIO_TOUCH_PAD3_START_M (RTCIO_TOUCH_PAD3_START_V << RTCIO_TOUCH_PAD3_START_S) +#define RTCIO_TOUCH_PAD3_START_V 0x00000001 +#define RTCIO_TOUCH_PAD3_START_S 22 + +/* RTCIO_TOUCH_PAD3_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD3_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD3_TIE_OPT_M (RTCIO_TOUCH_PAD3_TIE_OPT_V << RTCIO_TOUCH_PAD3_TIE_OPT_S) +#define RTCIO_TOUCH_PAD3_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD3_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD3_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD3_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD3_XPD_M (RTCIO_TOUCH_PAD3_XPD_V << RTCIO_TOUCH_PAD3_XPD_S) +#define RTCIO_TOUCH_PAD3_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD3_XPD_S 20 + +/* RTCIO_TOUCH_PAD3_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD3_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD3_MUX_SEL_M (RTCIO_TOUCH_PAD3_MUX_SEL_V << RTCIO_TOUCH_PAD3_MUX_SEL_S) +#define RTCIO_TOUCH_PAD3_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD3_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD3_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD3_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD3_FUN_SEL_M (RTCIO_TOUCH_PAD3_FUN_SEL_V << RTCIO_TOUCH_PAD3_FUN_SEL_S) +#define RTCIO_TOUCH_PAD3_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD3_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD3_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD3_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD3_SLP_SEL_M (RTCIO_TOUCH_PAD3_SLP_SEL_V << RTCIO_TOUCH_PAD3_SLP_SEL_S) +#define RTCIO_TOUCH_PAD3_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD3_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD3_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD3_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD3_SLP_IE_M (RTCIO_TOUCH_PAD3_SLP_IE_V << RTCIO_TOUCH_PAD3_SLP_IE_S) +#define RTCIO_TOUCH_PAD3_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD3_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD3_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD3_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD3_SLP_OE_M (RTCIO_TOUCH_PAD3_SLP_OE_V << RTCIO_TOUCH_PAD3_SLP_OE_S) +#define RTCIO_TOUCH_PAD3_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD3_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD3_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD3_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD3_FUN_IE_M (RTCIO_TOUCH_PAD3_FUN_IE_V << RTCIO_TOUCH_PAD3_FUN_IE_S) +#define RTCIO_TOUCH_PAD3_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD3_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD4_REG register + * Touch pad 4 configuration register + */ + +#define RTCIO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0x94) + +/* RTCIO_TOUCH_PAD4_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD4_DRV 0x00000003 +#define RTCIO_TOUCH_PAD4_DRV_M (RTCIO_TOUCH_PAD4_DRV_V << RTCIO_TOUCH_PAD4_DRV_S) +#define RTCIO_TOUCH_PAD4_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD4_DRV_S 29 + +/* RTCIO_TOUCH_PAD4_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD4_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD4_RDE_M (RTCIO_TOUCH_PAD4_RDE_V << RTCIO_TOUCH_PAD4_RDE_S) +#define RTCIO_TOUCH_PAD4_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD4_RDE_S 28 + +/* RTCIO_TOUCH_PAD4_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD4_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD4_RUE_M (RTCIO_TOUCH_PAD4_RUE_V << RTCIO_TOUCH_PAD4_RUE_S) +#define RTCIO_TOUCH_PAD4_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD4_RUE_S 27 + +/* RTCIO_TOUCH_PAD4_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD4_DAC 0x00000007 +#define RTCIO_TOUCH_PAD4_DAC_M (RTCIO_TOUCH_PAD4_DAC_V << RTCIO_TOUCH_PAD4_DAC_S) +#define RTCIO_TOUCH_PAD4_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD4_DAC_S 23 + +/* RTCIO_TOUCH_PAD4_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD4_START (BIT(22)) +#define RTCIO_TOUCH_PAD4_START_M (RTCIO_TOUCH_PAD4_START_V << RTCIO_TOUCH_PAD4_START_S) +#define RTCIO_TOUCH_PAD4_START_V 0x00000001 +#define RTCIO_TOUCH_PAD4_START_S 22 + +/* RTCIO_TOUCH_PAD4_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD4_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD4_TIE_OPT_M (RTCIO_TOUCH_PAD4_TIE_OPT_V << RTCIO_TOUCH_PAD4_TIE_OPT_S) +#define RTCIO_TOUCH_PAD4_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD4_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD4_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD4_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD4_XPD_M (RTCIO_TOUCH_PAD4_XPD_V << RTCIO_TOUCH_PAD4_XPD_S) +#define RTCIO_TOUCH_PAD4_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD4_XPD_S 20 + +/* RTCIO_TOUCH_PAD4_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD4_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD4_MUX_SEL_M (RTCIO_TOUCH_PAD4_MUX_SEL_V << RTCIO_TOUCH_PAD4_MUX_SEL_S) +#define RTCIO_TOUCH_PAD4_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD4_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD4_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD4_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD4_FUN_SEL_M (RTCIO_TOUCH_PAD4_FUN_SEL_V << RTCIO_TOUCH_PAD4_FUN_SEL_S) +#define RTCIO_TOUCH_PAD4_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD4_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD4_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD4_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD4_SLP_SEL_M (RTCIO_TOUCH_PAD4_SLP_SEL_V << RTCIO_TOUCH_PAD4_SLP_SEL_S) +#define RTCIO_TOUCH_PAD4_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD4_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD4_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD4_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD4_SLP_IE_M (RTCIO_TOUCH_PAD4_SLP_IE_V << RTCIO_TOUCH_PAD4_SLP_IE_S) +#define RTCIO_TOUCH_PAD4_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD4_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD4_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD4_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD4_SLP_OE_M (RTCIO_TOUCH_PAD4_SLP_OE_V << RTCIO_TOUCH_PAD4_SLP_OE_S) +#define RTCIO_TOUCH_PAD4_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD4_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD4_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD4_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD4_FUN_IE_M (RTCIO_TOUCH_PAD4_FUN_IE_V << RTCIO_TOUCH_PAD4_FUN_IE_S) +#define RTCIO_TOUCH_PAD4_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD4_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD5_REG register + * Touch pad 5 configuration register + */ + +#define RTCIO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0x98) + +/* RTCIO_TOUCH_PAD5_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD5_DRV 0x00000003 +#define RTCIO_TOUCH_PAD5_DRV_M (RTCIO_TOUCH_PAD5_DRV_V << RTCIO_TOUCH_PAD5_DRV_S) +#define RTCIO_TOUCH_PAD5_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD5_DRV_S 29 + +/* RTCIO_TOUCH_PAD5_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD5_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD5_RDE_M (RTCIO_TOUCH_PAD5_RDE_V << RTCIO_TOUCH_PAD5_RDE_S) +#define RTCIO_TOUCH_PAD5_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD5_RDE_S 28 + +/* RTCIO_TOUCH_PAD5_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD5_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD5_RUE_M (RTCIO_TOUCH_PAD5_RUE_V << RTCIO_TOUCH_PAD5_RUE_S) +#define RTCIO_TOUCH_PAD5_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD5_RUE_S 27 + +/* RTCIO_TOUCH_PAD5_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD5_DAC 0x00000007 +#define RTCIO_TOUCH_PAD5_DAC_M (RTCIO_TOUCH_PAD5_DAC_V << RTCIO_TOUCH_PAD5_DAC_S) +#define RTCIO_TOUCH_PAD5_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD5_DAC_S 23 + +/* RTCIO_TOUCH_PAD5_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD5_START (BIT(22)) +#define RTCIO_TOUCH_PAD5_START_M (RTCIO_TOUCH_PAD5_START_V << RTCIO_TOUCH_PAD5_START_S) +#define RTCIO_TOUCH_PAD5_START_V 0x00000001 +#define RTCIO_TOUCH_PAD5_START_S 22 + +/* RTCIO_TOUCH_PAD5_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD5_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD5_TIE_OPT_M (RTCIO_TOUCH_PAD5_TIE_OPT_V << RTCIO_TOUCH_PAD5_TIE_OPT_S) +#define RTCIO_TOUCH_PAD5_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD5_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD5_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD5_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD5_XPD_M (RTCIO_TOUCH_PAD5_XPD_V << RTCIO_TOUCH_PAD5_XPD_S) +#define RTCIO_TOUCH_PAD5_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD5_XPD_S 20 + +/* RTCIO_TOUCH_PAD5_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD5_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD5_MUX_SEL_M (RTCIO_TOUCH_PAD5_MUX_SEL_V << RTCIO_TOUCH_PAD5_MUX_SEL_S) +#define RTCIO_TOUCH_PAD5_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD5_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD5_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD5_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD5_FUN_SEL_M (RTCIO_TOUCH_PAD5_FUN_SEL_V << RTCIO_TOUCH_PAD5_FUN_SEL_S) +#define RTCIO_TOUCH_PAD5_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD5_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD5_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD5_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD5_SLP_SEL_M (RTCIO_TOUCH_PAD5_SLP_SEL_V << RTCIO_TOUCH_PAD5_SLP_SEL_S) +#define RTCIO_TOUCH_PAD5_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD5_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD5_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD5_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD5_SLP_IE_M (RTCIO_TOUCH_PAD5_SLP_IE_V << RTCIO_TOUCH_PAD5_SLP_IE_S) +#define RTCIO_TOUCH_PAD5_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD5_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD5_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD5_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD5_SLP_OE_M (RTCIO_TOUCH_PAD5_SLP_OE_V << RTCIO_TOUCH_PAD5_SLP_OE_S) +#define RTCIO_TOUCH_PAD5_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD5_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD5_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD5_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD5_FUN_IE_M (RTCIO_TOUCH_PAD5_FUN_IE_V << RTCIO_TOUCH_PAD5_FUN_IE_S) +#define RTCIO_TOUCH_PAD5_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD5_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD6_REG register + * Touch pad 6 configuration register + */ + +#define RTCIO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0x9c) + +/* RTCIO_TOUCH_PAD6_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD6_DRV 0x00000003 +#define RTCIO_TOUCH_PAD6_DRV_M (RTCIO_TOUCH_PAD6_DRV_V << RTCIO_TOUCH_PAD6_DRV_S) +#define RTCIO_TOUCH_PAD6_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD6_DRV_S 29 + +/* RTCIO_TOUCH_PAD6_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD6_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD6_RDE_M (RTCIO_TOUCH_PAD6_RDE_V << RTCIO_TOUCH_PAD6_RDE_S) +#define RTCIO_TOUCH_PAD6_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD6_RDE_S 28 + +/* RTCIO_TOUCH_PAD6_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD6_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD6_RUE_M (RTCIO_TOUCH_PAD6_RUE_V << RTCIO_TOUCH_PAD6_RUE_S) +#define RTCIO_TOUCH_PAD6_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD6_RUE_S 27 + +/* RTCIO_TOUCH_PAD6_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD6_DAC 0x00000007 +#define RTCIO_TOUCH_PAD6_DAC_M (RTCIO_TOUCH_PAD6_DAC_V << RTCIO_TOUCH_PAD6_DAC_S) +#define RTCIO_TOUCH_PAD6_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD6_DAC_S 23 + +/* RTCIO_TOUCH_PAD6_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD6_START (BIT(22)) +#define RTCIO_TOUCH_PAD6_START_M (RTCIO_TOUCH_PAD6_START_V << RTCIO_TOUCH_PAD6_START_S) +#define RTCIO_TOUCH_PAD6_START_V 0x00000001 +#define RTCIO_TOUCH_PAD6_START_S 22 + +/* RTCIO_TOUCH_PAD6_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD6_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD6_TIE_OPT_M (RTCIO_TOUCH_PAD6_TIE_OPT_V << RTCIO_TOUCH_PAD6_TIE_OPT_S) +#define RTCIO_TOUCH_PAD6_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD6_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD6_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD6_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD6_XPD_M (RTCIO_TOUCH_PAD6_XPD_V << RTCIO_TOUCH_PAD6_XPD_S) +#define RTCIO_TOUCH_PAD6_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD6_XPD_S 20 + +/* RTCIO_TOUCH_PAD6_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD6_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD6_MUX_SEL_M (RTCIO_TOUCH_PAD6_MUX_SEL_V << RTCIO_TOUCH_PAD6_MUX_SEL_S) +#define RTCIO_TOUCH_PAD6_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD6_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD6_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD6_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD6_FUN_SEL_M (RTCIO_TOUCH_PAD6_FUN_SEL_V << RTCIO_TOUCH_PAD6_FUN_SEL_S) +#define RTCIO_TOUCH_PAD6_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD6_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD6_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD6_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD6_SLP_SEL_M (RTCIO_TOUCH_PAD6_SLP_SEL_V << RTCIO_TOUCH_PAD6_SLP_SEL_S) +#define RTCIO_TOUCH_PAD6_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD6_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD6_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD6_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD6_SLP_IE_M (RTCIO_TOUCH_PAD6_SLP_IE_V << RTCIO_TOUCH_PAD6_SLP_IE_S) +#define RTCIO_TOUCH_PAD6_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD6_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD6_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD6_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD6_SLP_OE_M (RTCIO_TOUCH_PAD6_SLP_OE_V << RTCIO_TOUCH_PAD6_SLP_OE_S) +#define RTCIO_TOUCH_PAD6_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD6_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD6_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD6_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD6_FUN_IE_M (RTCIO_TOUCH_PAD6_FUN_IE_V << RTCIO_TOUCH_PAD6_FUN_IE_S) +#define RTCIO_TOUCH_PAD6_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD6_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD7_REG register + * Touch pad 7 configuration register + */ + +#define RTCIO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xa0) + +/* RTCIO_TOUCH_PAD7_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD7_DRV 0x00000003 +#define RTCIO_TOUCH_PAD7_DRV_M (RTCIO_TOUCH_PAD7_DRV_V << RTCIO_TOUCH_PAD7_DRV_S) +#define RTCIO_TOUCH_PAD7_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD7_DRV_S 29 + +/* RTCIO_TOUCH_PAD7_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD7_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD7_RDE_M (RTCIO_TOUCH_PAD7_RDE_V << RTCIO_TOUCH_PAD7_RDE_S) +#define RTCIO_TOUCH_PAD7_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD7_RDE_S 28 + +/* RTCIO_TOUCH_PAD7_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD7_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD7_RUE_M (RTCIO_TOUCH_PAD7_RUE_V << RTCIO_TOUCH_PAD7_RUE_S) +#define RTCIO_TOUCH_PAD7_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD7_RUE_S 27 + +/* RTCIO_TOUCH_PAD7_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD7_DAC 0x00000007 +#define RTCIO_TOUCH_PAD7_DAC_M (RTCIO_TOUCH_PAD7_DAC_V << RTCIO_TOUCH_PAD7_DAC_S) +#define RTCIO_TOUCH_PAD7_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD7_DAC_S 23 + +/* RTCIO_TOUCH_PAD7_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD7_START (BIT(22)) +#define RTCIO_TOUCH_PAD7_START_M (RTCIO_TOUCH_PAD7_START_V << RTCIO_TOUCH_PAD7_START_S) +#define RTCIO_TOUCH_PAD7_START_V 0x00000001 +#define RTCIO_TOUCH_PAD7_START_S 22 + +/* RTCIO_TOUCH_PAD7_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD7_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD7_TIE_OPT_M (RTCIO_TOUCH_PAD7_TIE_OPT_V << RTCIO_TOUCH_PAD7_TIE_OPT_S) +#define RTCIO_TOUCH_PAD7_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD7_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD7_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD7_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD7_XPD_M (RTCIO_TOUCH_PAD7_XPD_V << RTCIO_TOUCH_PAD7_XPD_S) +#define RTCIO_TOUCH_PAD7_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD7_XPD_S 20 + +/* RTCIO_TOUCH_PAD7_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD7_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD7_MUX_SEL_M (RTCIO_TOUCH_PAD7_MUX_SEL_V << RTCIO_TOUCH_PAD7_MUX_SEL_S) +#define RTCIO_TOUCH_PAD7_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD7_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD7_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD7_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD7_FUN_SEL_M (RTCIO_TOUCH_PAD7_FUN_SEL_V << RTCIO_TOUCH_PAD7_FUN_SEL_S) +#define RTCIO_TOUCH_PAD7_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD7_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD7_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD7_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD7_SLP_SEL_M (RTCIO_TOUCH_PAD7_SLP_SEL_V << RTCIO_TOUCH_PAD7_SLP_SEL_S) +#define RTCIO_TOUCH_PAD7_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD7_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD7_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD7_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD7_SLP_IE_M (RTCIO_TOUCH_PAD7_SLP_IE_V << RTCIO_TOUCH_PAD7_SLP_IE_S) +#define RTCIO_TOUCH_PAD7_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD7_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD7_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD7_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD7_SLP_OE_M (RTCIO_TOUCH_PAD7_SLP_OE_V << RTCIO_TOUCH_PAD7_SLP_OE_S) +#define RTCIO_TOUCH_PAD7_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD7_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD7_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD7_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD7_FUN_IE_M (RTCIO_TOUCH_PAD7_FUN_IE_V << RTCIO_TOUCH_PAD7_FUN_IE_S) +#define RTCIO_TOUCH_PAD7_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD7_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD8_REG register + * Touch pad 8 configuration register + */ + +#define RTCIO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xa4) + +/* RTCIO_TOUCH_PAD8_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD8_DRV 0x00000003 +#define RTCIO_TOUCH_PAD8_DRV_M (RTCIO_TOUCH_PAD8_DRV_V << RTCIO_TOUCH_PAD8_DRV_S) +#define RTCIO_TOUCH_PAD8_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD8_DRV_S 29 + +/* RTCIO_TOUCH_PAD8_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD8_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD8_RDE_M (RTCIO_TOUCH_PAD8_RDE_V << RTCIO_TOUCH_PAD8_RDE_S) +#define RTCIO_TOUCH_PAD8_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD8_RDE_S 28 + +/* RTCIO_TOUCH_PAD8_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD8_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD8_RUE_M (RTCIO_TOUCH_PAD8_RUE_V << RTCIO_TOUCH_PAD8_RUE_S) +#define RTCIO_TOUCH_PAD8_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD8_RUE_S 27 + +/* RTCIO_TOUCH_PAD8_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD8_DAC 0x00000007 +#define RTCIO_TOUCH_PAD8_DAC_M (RTCIO_TOUCH_PAD8_DAC_V << RTCIO_TOUCH_PAD8_DAC_S) +#define RTCIO_TOUCH_PAD8_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD8_DAC_S 23 + +/* RTCIO_TOUCH_PAD8_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD8_START (BIT(22)) +#define RTCIO_TOUCH_PAD8_START_M (RTCIO_TOUCH_PAD8_START_V << RTCIO_TOUCH_PAD8_START_S) +#define RTCIO_TOUCH_PAD8_START_V 0x00000001 +#define RTCIO_TOUCH_PAD8_START_S 22 + +/* RTCIO_TOUCH_PAD8_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD8_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD8_TIE_OPT_M (RTCIO_TOUCH_PAD8_TIE_OPT_V << RTCIO_TOUCH_PAD8_TIE_OPT_S) +#define RTCIO_TOUCH_PAD8_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD8_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD8_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD8_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD8_XPD_M (RTCIO_TOUCH_PAD8_XPD_V << RTCIO_TOUCH_PAD8_XPD_S) +#define RTCIO_TOUCH_PAD8_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD8_XPD_S 20 + +/* RTCIO_TOUCH_PAD8_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD8_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD8_MUX_SEL_M (RTCIO_TOUCH_PAD8_MUX_SEL_V << RTCIO_TOUCH_PAD8_MUX_SEL_S) +#define RTCIO_TOUCH_PAD8_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD8_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD8_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD8_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD8_FUN_SEL_M (RTCIO_TOUCH_PAD8_FUN_SEL_V << RTCIO_TOUCH_PAD8_FUN_SEL_S) +#define RTCIO_TOUCH_PAD8_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD8_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD8_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD8_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD8_SLP_SEL_M (RTCIO_TOUCH_PAD8_SLP_SEL_V << RTCIO_TOUCH_PAD8_SLP_SEL_S) +#define RTCIO_TOUCH_PAD8_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD8_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD8_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD8_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD8_SLP_IE_M (RTCIO_TOUCH_PAD8_SLP_IE_V << RTCIO_TOUCH_PAD8_SLP_IE_S) +#define RTCIO_TOUCH_PAD8_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD8_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD8_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD8_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD8_SLP_OE_M (RTCIO_TOUCH_PAD8_SLP_OE_V << RTCIO_TOUCH_PAD8_SLP_OE_S) +#define RTCIO_TOUCH_PAD8_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD8_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD8_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD8_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD8_FUN_IE_M (RTCIO_TOUCH_PAD8_FUN_IE_V << RTCIO_TOUCH_PAD8_FUN_IE_S) +#define RTCIO_TOUCH_PAD8_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD8_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD9_REG register + * Touch pad 9 configuration register + */ + +#define RTCIO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xa8) + +/* RTCIO_TOUCH_PAD9_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD9_DRV 0x00000003 +#define RTCIO_TOUCH_PAD9_DRV_M (RTCIO_TOUCH_PAD9_DRV_V << RTCIO_TOUCH_PAD9_DRV_S) +#define RTCIO_TOUCH_PAD9_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD9_DRV_S 29 + +/* RTCIO_TOUCH_PAD9_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD9_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD9_RDE_M (RTCIO_TOUCH_PAD9_RDE_V << RTCIO_TOUCH_PAD9_RDE_S) +#define RTCIO_TOUCH_PAD9_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD9_RDE_S 28 + +/* RTCIO_TOUCH_PAD9_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD9_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD9_RUE_M (RTCIO_TOUCH_PAD9_RUE_V << RTCIO_TOUCH_PAD9_RUE_S) +#define RTCIO_TOUCH_PAD9_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD9_RUE_S 27 + +/* RTCIO_TOUCH_PAD9_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD9_DAC 0x00000007 +#define RTCIO_TOUCH_PAD9_DAC_M (RTCIO_TOUCH_PAD9_DAC_V << RTCIO_TOUCH_PAD9_DAC_S) +#define RTCIO_TOUCH_PAD9_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD9_DAC_S 23 + +/* RTCIO_TOUCH_PAD9_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD9_START (BIT(22)) +#define RTCIO_TOUCH_PAD9_START_M (RTCIO_TOUCH_PAD9_START_V << RTCIO_TOUCH_PAD9_START_S) +#define RTCIO_TOUCH_PAD9_START_V 0x00000001 +#define RTCIO_TOUCH_PAD9_START_S 22 + +/* RTCIO_TOUCH_PAD9_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD9_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD9_TIE_OPT_M (RTCIO_TOUCH_PAD9_TIE_OPT_V << RTCIO_TOUCH_PAD9_TIE_OPT_S) +#define RTCIO_TOUCH_PAD9_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD9_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD9_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD9_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD9_XPD_M (RTCIO_TOUCH_PAD9_XPD_V << RTCIO_TOUCH_PAD9_XPD_S) +#define RTCIO_TOUCH_PAD9_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD9_XPD_S 20 + +/* RTCIO_TOUCH_PAD9_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD9_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD9_MUX_SEL_M (RTCIO_TOUCH_PAD9_MUX_SEL_V << RTCIO_TOUCH_PAD9_MUX_SEL_S) +#define RTCIO_TOUCH_PAD9_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD9_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD9_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD9_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD9_FUN_SEL_M (RTCIO_TOUCH_PAD9_FUN_SEL_V << RTCIO_TOUCH_PAD9_FUN_SEL_S) +#define RTCIO_TOUCH_PAD9_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD9_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD9_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD9_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD9_SLP_SEL_M (RTCIO_TOUCH_PAD9_SLP_SEL_V << RTCIO_TOUCH_PAD9_SLP_SEL_S) +#define RTCIO_TOUCH_PAD9_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD9_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD9_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD9_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD9_SLP_IE_M (RTCIO_TOUCH_PAD9_SLP_IE_V << RTCIO_TOUCH_PAD9_SLP_IE_S) +#define RTCIO_TOUCH_PAD9_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD9_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD9_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD9_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD9_SLP_OE_M (RTCIO_TOUCH_PAD9_SLP_OE_V << RTCIO_TOUCH_PAD9_SLP_OE_S) +#define RTCIO_TOUCH_PAD9_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD9_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD9_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD9_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD9_FUN_IE_M (RTCIO_TOUCH_PAD9_FUN_IE_V << RTCIO_TOUCH_PAD9_FUN_IE_S) +#define RTCIO_TOUCH_PAD9_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD9_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD10_REG register + * Touch pad 10 configuration register + */ + +#define RTCIO_TOUCH_PAD10_REG (DR_REG_RTCIO_BASE + 0xac) + +/* RTCIO_TOUCH_PAD10_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD10_DRV 0x00000003 +#define RTCIO_TOUCH_PAD10_DRV_M (RTCIO_TOUCH_PAD10_DRV_V << RTCIO_TOUCH_PAD10_DRV_S) +#define RTCIO_TOUCH_PAD10_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD10_DRV_S 29 + +/* RTCIO_TOUCH_PAD10_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD10_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD10_RDE_M (RTCIO_TOUCH_PAD10_RDE_V << RTCIO_TOUCH_PAD10_RDE_S) +#define RTCIO_TOUCH_PAD10_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD10_RDE_S 28 + +/* RTCIO_TOUCH_PAD10_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD10_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD10_RUE_M (RTCIO_TOUCH_PAD10_RUE_V << RTCIO_TOUCH_PAD10_RUE_S) +#define RTCIO_TOUCH_PAD10_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD10_RUE_S 27 + +/* RTCIO_TOUCH_PAD10_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD10_DAC 0x00000007 +#define RTCIO_TOUCH_PAD10_DAC_M (RTCIO_TOUCH_PAD10_DAC_V << RTCIO_TOUCH_PAD10_DAC_S) +#define RTCIO_TOUCH_PAD10_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD10_DAC_S 23 + +/* RTCIO_TOUCH_PAD10_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD10_START (BIT(22)) +#define RTCIO_TOUCH_PAD10_START_M (RTCIO_TOUCH_PAD10_START_V << RTCIO_TOUCH_PAD10_START_S) +#define RTCIO_TOUCH_PAD10_START_V 0x00000001 +#define RTCIO_TOUCH_PAD10_START_S 22 + +/* RTCIO_TOUCH_PAD10_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD10_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD10_TIE_OPT_M (RTCIO_TOUCH_PAD10_TIE_OPT_V << RTCIO_TOUCH_PAD10_TIE_OPT_S) +#define RTCIO_TOUCH_PAD10_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD10_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD10_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD10_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD10_XPD_M (RTCIO_TOUCH_PAD10_XPD_V << RTCIO_TOUCH_PAD10_XPD_S) +#define RTCIO_TOUCH_PAD10_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD10_XPD_S 20 + +/* RTCIO_TOUCH_PAD10_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD10_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD10_MUX_SEL_M (RTCIO_TOUCH_PAD10_MUX_SEL_V << RTCIO_TOUCH_PAD10_MUX_SEL_S) +#define RTCIO_TOUCH_PAD10_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD10_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD10_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD10_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD10_FUN_SEL_M (RTCIO_TOUCH_PAD10_FUN_SEL_V << RTCIO_TOUCH_PAD10_FUN_SEL_S) +#define RTCIO_TOUCH_PAD10_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD10_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD10_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD10_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD10_SLP_SEL_M (RTCIO_TOUCH_PAD10_SLP_SEL_V << RTCIO_TOUCH_PAD10_SLP_SEL_S) +#define RTCIO_TOUCH_PAD10_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD10_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD10_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD10_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD10_SLP_IE_M (RTCIO_TOUCH_PAD10_SLP_IE_V << RTCIO_TOUCH_PAD10_SLP_IE_S) +#define RTCIO_TOUCH_PAD10_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD10_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD10_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD10_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD10_SLP_OE_M (RTCIO_TOUCH_PAD10_SLP_OE_V << RTCIO_TOUCH_PAD10_SLP_OE_S) +#define RTCIO_TOUCH_PAD10_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD10_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD10_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD10_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD10_FUN_IE_M (RTCIO_TOUCH_PAD10_FUN_IE_V << RTCIO_TOUCH_PAD10_FUN_IE_S) +#define RTCIO_TOUCH_PAD10_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD10_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD11_REG register + * Touch pad 11 configuration register + */ + +#define RTCIO_TOUCH_PAD11_REG (DR_REG_RTCIO_BASE + 0xb0) + +/* RTCIO_TOUCH_PAD11_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD11_DRV 0x00000003 +#define RTCIO_TOUCH_PAD11_DRV_M (RTCIO_TOUCH_PAD11_DRV_V << RTCIO_TOUCH_PAD11_DRV_S) +#define RTCIO_TOUCH_PAD11_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD11_DRV_S 29 + +/* RTCIO_TOUCH_PAD11_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD11_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD11_RDE_M (RTCIO_TOUCH_PAD11_RDE_V << RTCIO_TOUCH_PAD11_RDE_S) +#define RTCIO_TOUCH_PAD11_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD11_RDE_S 28 + +/* RTCIO_TOUCH_PAD11_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD11_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD11_RUE_M (RTCIO_TOUCH_PAD11_RUE_V << RTCIO_TOUCH_PAD11_RUE_S) +#define RTCIO_TOUCH_PAD11_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD11_RUE_S 27 + +/* RTCIO_TOUCH_PAD11_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD11_DAC 0x00000007 +#define RTCIO_TOUCH_PAD11_DAC_M (RTCIO_TOUCH_PAD11_DAC_V << RTCIO_TOUCH_PAD11_DAC_S) +#define RTCIO_TOUCH_PAD11_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD11_DAC_S 23 + +/* RTCIO_TOUCH_PAD11_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD11_START (BIT(22)) +#define RTCIO_TOUCH_PAD11_START_M (RTCIO_TOUCH_PAD11_START_V << RTCIO_TOUCH_PAD11_START_S) +#define RTCIO_TOUCH_PAD11_START_V 0x00000001 +#define RTCIO_TOUCH_PAD11_START_S 22 + +/* RTCIO_TOUCH_PAD11_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD11_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD11_TIE_OPT_M (RTCIO_TOUCH_PAD11_TIE_OPT_V << RTCIO_TOUCH_PAD11_TIE_OPT_S) +#define RTCIO_TOUCH_PAD11_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD11_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD11_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD11_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD11_XPD_M (RTCIO_TOUCH_PAD11_XPD_V << RTCIO_TOUCH_PAD11_XPD_S) +#define RTCIO_TOUCH_PAD11_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD11_XPD_S 20 + +/* RTCIO_TOUCH_PAD11_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD11_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD11_MUX_SEL_M (RTCIO_TOUCH_PAD11_MUX_SEL_V << RTCIO_TOUCH_PAD11_MUX_SEL_S) +#define RTCIO_TOUCH_PAD11_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD11_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD11_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD11_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD11_FUN_SEL_M (RTCIO_TOUCH_PAD11_FUN_SEL_V << RTCIO_TOUCH_PAD11_FUN_SEL_S) +#define RTCIO_TOUCH_PAD11_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD11_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD11_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD11_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD11_SLP_SEL_M (RTCIO_TOUCH_PAD11_SLP_SEL_V << RTCIO_TOUCH_PAD11_SLP_SEL_S) +#define RTCIO_TOUCH_PAD11_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD11_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD11_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD11_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD11_SLP_IE_M (RTCIO_TOUCH_PAD11_SLP_IE_V << RTCIO_TOUCH_PAD11_SLP_IE_S) +#define RTCIO_TOUCH_PAD11_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD11_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD11_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD11_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD11_SLP_OE_M (RTCIO_TOUCH_PAD11_SLP_OE_V << RTCIO_TOUCH_PAD11_SLP_OE_S) +#define RTCIO_TOUCH_PAD11_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD11_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD11_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD11_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD11_FUN_IE_M (RTCIO_TOUCH_PAD11_FUN_IE_V << RTCIO_TOUCH_PAD11_FUN_IE_S) +#define RTCIO_TOUCH_PAD11_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD11_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD12_REG register + * Touch pad 12 configuration register + */ + +#define RTCIO_TOUCH_PAD12_REG (DR_REG_RTCIO_BASE + 0xb4) + +/* RTCIO_TOUCH_PAD12_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD12_DRV 0x00000003 +#define RTCIO_TOUCH_PAD12_DRV_M (RTCIO_TOUCH_PAD12_DRV_V << RTCIO_TOUCH_PAD12_DRV_S) +#define RTCIO_TOUCH_PAD12_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD12_DRV_S 29 + +/* RTCIO_TOUCH_PAD12_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD12_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD12_RDE_M (RTCIO_TOUCH_PAD12_RDE_V << RTCIO_TOUCH_PAD12_RDE_S) +#define RTCIO_TOUCH_PAD12_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD12_RDE_S 28 + +/* RTCIO_TOUCH_PAD12_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD12_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD12_RUE_M (RTCIO_TOUCH_PAD12_RUE_V << RTCIO_TOUCH_PAD12_RUE_S) +#define RTCIO_TOUCH_PAD12_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD12_RUE_S 27 + +/* RTCIO_TOUCH_PAD12_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD12_DAC 0x00000007 +#define RTCIO_TOUCH_PAD12_DAC_M (RTCIO_TOUCH_PAD12_DAC_V << RTCIO_TOUCH_PAD12_DAC_S) +#define RTCIO_TOUCH_PAD12_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD12_DAC_S 23 + +/* RTCIO_TOUCH_PAD12_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD12_START (BIT(22)) +#define RTCIO_TOUCH_PAD12_START_M (RTCIO_TOUCH_PAD12_START_V << RTCIO_TOUCH_PAD12_START_S) +#define RTCIO_TOUCH_PAD12_START_V 0x00000001 +#define RTCIO_TOUCH_PAD12_START_S 22 + +/* RTCIO_TOUCH_PAD12_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD12_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD12_TIE_OPT_M (RTCIO_TOUCH_PAD12_TIE_OPT_V << RTCIO_TOUCH_PAD12_TIE_OPT_S) +#define RTCIO_TOUCH_PAD12_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD12_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD12_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD12_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD12_XPD_M (RTCIO_TOUCH_PAD12_XPD_V << RTCIO_TOUCH_PAD12_XPD_S) +#define RTCIO_TOUCH_PAD12_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD12_XPD_S 20 + +/* RTCIO_TOUCH_PAD12_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD12_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD12_MUX_SEL_M (RTCIO_TOUCH_PAD12_MUX_SEL_V << RTCIO_TOUCH_PAD12_MUX_SEL_S) +#define RTCIO_TOUCH_PAD12_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD12_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD12_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD12_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD12_FUN_SEL_M (RTCIO_TOUCH_PAD12_FUN_SEL_V << RTCIO_TOUCH_PAD12_FUN_SEL_S) +#define RTCIO_TOUCH_PAD12_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD12_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD12_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD12_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD12_SLP_SEL_M (RTCIO_TOUCH_PAD12_SLP_SEL_V << RTCIO_TOUCH_PAD12_SLP_SEL_S) +#define RTCIO_TOUCH_PAD12_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD12_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD12_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD12_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD12_SLP_IE_M (RTCIO_TOUCH_PAD12_SLP_IE_V << RTCIO_TOUCH_PAD12_SLP_IE_S) +#define RTCIO_TOUCH_PAD12_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD12_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD12_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD12_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD12_SLP_OE_M (RTCIO_TOUCH_PAD12_SLP_OE_V << RTCIO_TOUCH_PAD12_SLP_OE_S) +#define RTCIO_TOUCH_PAD12_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD12_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD12_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD12_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD12_FUN_IE_M (RTCIO_TOUCH_PAD12_FUN_IE_V << RTCIO_TOUCH_PAD12_FUN_IE_S) +#define RTCIO_TOUCH_PAD12_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD12_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD13_REG register + * Touch pad 13 configuration register + */ + +#define RTCIO_TOUCH_PAD13_REG (DR_REG_RTCIO_BASE + 0xb8) + +/* RTCIO_TOUCH_PAD13_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD13_DRV 0x00000003 +#define RTCIO_TOUCH_PAD13_DRV_M (RTCIO_TOUCH_PAD13_DRV_V << RTCIO_TOUCH_PAD13_DRV_S) +#define RTCIO_TOUCH_PAD13_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD13_DRV_S 29 + +/* RTCIO_TOUCH_PAD13_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD13_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD13_RDE_M (RTCIO_TOUCH_PAD13_RDE_V << RTCIO_TOUCH_PAD13_RDE_S) +#define RTCIO_TOUCH_PAD13_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD13_RDE_S 28 + +/* RTCIO_TOUCH_PAD13_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD13_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD13_RUE_M (RTCIO_TOUCH_PAD13_RUE_V << RTCIO_TOUCH_PAD13_RUE_S) +#define RTCIO_TOUCH_PAD13_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD13_RUE_S 27 + +/* RTCIO_TOUCH_PAD13_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD13_DAC 0x00000007 +#define RTCIO_TOUCH_PAD13_DAC_M (RTCIO_TOUCH_PAD13_DAC_V << RTCIO_TOUCH_PAD13_DAC_S) +#define RTCIO_TOUCH_PAD13_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD13_DAC_S 23 + +/* RTCIO_TOUCH_PAD13_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD13_START (BIT(22)) +#define RTCIO_TOUCH_PAD13_START_M (RTCIO_TOUCH_PAD13_START_V << RTCIO_TOUCH_PAD13_START_S) +#define RTCIO_TOUCH_PAD13_START_V 0x00000001 +#define RTCIO_TOUCH_PAD13_START_S 22 + +/* RTCIO_TOUCH_PAD13_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD13_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD13_TIE_OPT_M (RTCIO_TOUCH_PAD13_TIE_OPT_V << RTCIO_TOUCH_PAD13_TIE_OPT_S) +#define RTCIO_TOUCH_PAD13_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD13_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD13_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD13_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD13_XPD_M (RTCIO_TOUCH_PAD13_XPD_V << RTCIO_TOUCH_PAD13_XPD_S) +#define RTCIO_TOUCH_PAD13_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD13_XPD_S 20 + +/* RTCIO_TOUCH_PAD13_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD13_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD13_MUX_SEL_M (RTCIO_TOUCH_PAD13_MUX_SEL_V << RTCIO_TOUCH_PAD13_MUX_SEL_S) +#define RTCIO_TOUCH_PAD13_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD13_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD13_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD13_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD13_FUN_SEL_M (RTCIO_TOUCH_PAD13_FUN_SEL_V << RTCIO_TOUCH_PAD13_FUN_SEL_S) +#define RTCIO_TOUCH_PAD13_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD13_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD13_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD13_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD13_SLP_SEL_M (RTCIO_TOUCH_PAD13_SLP_SEL_V << RTCIO_TOUCH_PAD13_SLP_SEL_S) +#define RTCIO_TOUCH_PAD13_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD13_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD13_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD13_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD13_SLP_IE_M (RTCIO_TOUCH_PAD13_SLP_IE_V << RTCIO_TOUCH_PAD13_SLP_IE_S) +#define RTCIO_TOUCH_PAD13_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD13_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD13_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD13_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD13_SLP_OE_M (RTCIO_TOUCH_PAD13_SLP_OE_V << RTCIO_TOUCH_PAD13_SLP_OE_S) +#define RTCIO_TOUCH_PAD13_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD13_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD13_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD13_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD13_FUN_IE_M (RTCIO_TOUCH_PAD13_FUN_IE_V << RTCIO_TOUCH_PAD13_FUN_IE_S) +#define RTCIO_TOUCH_PAD13_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD13_FUN_IE_S 13 + +/* RTCIO_TOUCH_PAD14_REG register + * Touch pad 14 configuration register + */ + +#define RTCIO_TOUCH_PAD14_REG (DR_REG_RTCIO_BASE + 0xbc) + +/* RTCIO_TOUCH_PAD14_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_TOUCH_PAD14_DRV 0x00000003 +#define RTCIO_TOUCH_PAD14_DRV_M (RTCIO_TOUCH_PAD14_DRV_V << RTCIO_TOUCH_PAD14_DRV_S) +#define RTCIO_TOUCH_PAD14_DRV_V 0x00000003 +#define RTCIO_TOUCH_PAD14_DRV_S 29 + +/* RTCIO_TOUCH_PAD14_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_TOUCH_PAD14_RDE (BIT(28)) +#define RTCIO_TOUCH_PAD14_RDE_M (RTCIO_TOUCH_PAD14_RDE_V << RTCIO_TOUCH_PAD14_RDE_S) +#define RTCIO_TOUCH_PAD14_RDE_V 0x00000001 +#define RTCIO_TOUCH_PAD14_RDE_S 28 + +/* RTCIO_TOUCH_PAD14_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_TOUCH_PAD14_RUE (BIT(27)) +#define RTCIO_TOUCH_PAD14_RUE_M (RTCIO_TOUCH_PAD14_RUE_V << RTCIO_TOUCH_PAD14_RUE_S) +#define RTCIO_TOUCH_PAD14_RUE_V 0x00000001 +#define RTCIO_TOUCH_PAD14_RUE_S 27 + +/* RTCIO_TOUCH_PAD14_DAC : R/W; bitpos: [25:23]; default: 4; + * Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4. + */ + +#define RTCIO_TOUCH_PAD14_DAC 0x00000007 +#define RTCIO_TOUCH_PAD14_DAC_M (RTCIO_TOUCH_PAD14_DAC_V << RTCIO_TOUCH_PAD14_DAC_S) +#define RTCIO_TOUCH_PAD14_DAC_V 0x00000007 +#define RTCIO_TOUCH_PAD14_DAC_S 23 + +/* RTCIO_TOUCH_PAD14_START : R/W; bitpos: [22]; default: 0; + * Start touch sensor. + */ + +#define RTCIO_TOUCH_PAD14_START (BIT(22)) +#define RTCIO_TOUCH_PAD14_START_M (RTCIO_TOUCH_PAD14_START_V << RTCIO_TOUCH_PAD14_START_S) +#define RTCIO_TOUCH_PAD14_START_V 0x00000001 +#define RTCIO_TOUCH_PAD14_START_S 22 + +/* RTCIO_TOUCH_PAD14_TIE_OPT : R/W; bitpos: [21]; default: 0; + * The tie option of touch sensor. 0: tie low; 1: tie high. + */ + +#define RTCIO_TOUCH_PAD14_TIE_OPT (BIT(21)) +#define RTCIO_TOUCH_PAD14_TIE_OPT_M (RTCIO_TOUCH_PAD14_TIE_OPT_V << RTCIO_TOUCH_PAD14_TIE_OPT_S) +#define RTCIO_TOUCH_PAD14_TIE_OPT_V 0x00000001 +#define RTCIO_TOUCH_PAD14_TIE_OPT_S 21 + +/* RTCIO_TOUCH_PAD14_XPD : R/W; bitpos: [20]; default: 0; + * Touch sensor power on. + */ + +#define RTCIO_TOUCH_PAD14_XPD (BIT(20)) +#define RTCIO_TOUCH_PAD14_XPD_M (RTCIO_TOUCH_PAD14_XPD_V << RTCIO_TOUCH_PAD14_XPD_S) +#define RTCIO_TOUCH_PAD14_XPD_V 0x00000001 +#define RTCIO_TOUCH_PAD14_XPD_S 20 + +/* RTCIO_TOUCH_PAD14_MUX_SEL : R/W; bitpos: [19]; default: 0; + * Connect the RTC pad input to digital pad input. 0 is available. + */ + +#define RTCIO_TOUCH_PAD14_MUX_SEL (BIT(19)) +#define RTCIO_TOUCH_PAD14_MUX_SEL_M (RTCIO_TOUCH_PAD14_MUX_SEL_V << RTCIO_TOUCH_PAD14_MUX_SEL_S) +#define RTCIO_TOUCH_PAD14_MUX_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD14_MUX_SEL_S 19 + +/* RTCIO_TOUCH_PAD14_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_TOUCH_PAD14_FUN_SEL 0x00000003 +#define RTCIO_TOUCH_PAD14_FUN_SEL_M (RTCIO_TOUCH_PAD14_FUN_SEL_V << RTCIO_TOUCH_PAD14_FUN_SEL_S) +#define RTCIO_TOUCH_PAD14_FUN_SEL_V 0x00000003 +#define RTCIO_TOUCH_PAD14_FUN_SEL_S 17 + +/* RTCIO_TOUCH_PAD14_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 0: no sleep mode; 1: enable sleep mode. + */ + +#define RTCIO_TOUCH_PAD14_SLP_SEL (BIT(16)) +#define RTCIO_TOUCH_PAD14_SLP_SEL_M (RTCIO_TOUCH_PAD14_SLP_SEL_V << RTCIO_TOUCH_PAD14_SLP_SEL_S) +#define RTCIO_TOUCH_PAD14_SLP_SEL_V 0x00000001 +#define RTCIO_TOUCH_PAD14_SLP_SEL_S 16 + +/* RTCIO_TOUCH_PAD14_SLP_IE : R/W; bitpos: [15]; default: 0; + * Input enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD14_SLP_IE (BIT(15)) +#define RTCIO_TOUCH_PAD14_SLP_IE_M (RTCIO_TOUCH_PAD14_SLP_IE_V << RTCIO_TOUCH_PAD14_SLP_IE_S) +#define RTCIO_TOUCH_PAD14_SLP_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD14_SLP_IE_S 15 + +/* RTCIO_TOUCH_PAD14_SLP_OE : R/W; bitpos: [14]; default: 0; + * Output enable in sleep mode. + */ + +#define RTCIO_TOUCH_PAD14_SLP_OE (BIT(14)) +#define RTCIO_TOUCH_PAD14_SLP_OE_M (RTCIO_TOUCH_PAD14_SLP_OE_V << RTCIO_TOUCH_PAD14_SLP_OE_S) +#define RTCIO_TOUCH_PAD14_SLP_OE_V 0x00000001 +#define RTCIO_TOUCH_PAD14_SLP_OE_S 14 + +/* RTCIO_TOUCH_PAD14_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_TOUCH_PAD14_FUN_IE (BIT(13)) +#define RTCIO_TOUCH_PAD14_FUN_IE_M (RTCIO_TOUCH_PAD14_FUN_IE_V << RTCIO_TOUCH_PAD14_FUN_IE_S) +#define RTCIO_TOUCH_PAD14_FUN_IE_V 0x00000001 +#define RTCIO_TOUCH_PAD14_FUN_IE_S 13 + +/* RTCIO_XTAL_32P_PAD_REG register + * 32KHz crystal P-pad configuration register + */ + +#define RTCIO_XTAL_32P_PAD_REG (DR_REG_RTCIO_BASE + 0xc0) + +/* RTCIO_X32P_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_X32P_DRV 0x00000003 +#define RTCIO_X32P_DRV_M (RTCIO_X32P_DRV_V << RTCIO_X32P_DRV_S) +#define RTCIO_X32P_DRV_V 0x00000003 +#define RTCIO_X32P_DRV_S 29 + +/* RTCIO_X32P_RDE : R/W; bitpos: [28]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_X32P_RDE (BIT(28)) +#define RTCIO_X32P_RDE_M (RTCIO_X32P_RDE_V << RTCIO_X32P_RDE_S) +#define RTCIO_X32P_RDE_V 0x00000001 +#define RTCIO_X32P_RDE_S 28 + +/* RTCIO_X32P_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_X32P_RUE (BIT(27)) +#define RTCIO_X32P_RUE_M (RTCIO_X32P_RUE_V << RTCIO_X32P_RUE_S) +#define RTCIO_X32P_RUE_V 0x00000001 +#define RTCIO_X32P_RUE_S 27 + +/* RTCIO_X32P_MUX_SEL : R/W; bitpos: [19]; default: 0; + * 1: use RTC GPIO,0: use digital GPIO + */ + +#define RTCIO_X32P_MUX_SEL (BIT(19)) +#define RTCIO_X32P_MUX_SEL_M (RTCIO_X32P_MUX_SEL_V << RTCIO_X32P_MUX_SEL_S) +#define RTCIO_X32P_MUX_SEL_V 0x00000001 +#define RTCIO_X32P_MUX_SEL_S 19 + +/* RTCIO_X32P_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_X32P_FUN_SEL 0x00000003 +#define RTCIO_X32P_FUN_SEL_M (RTCIO_X32P_FUN_SEL_V << RTCIO_X32P_FUN_SEL_S) +#define RTCIO_X32P_FUN_SEL_V 0x00000003 +#define RTCIO_X32P_FUN_SEL_S 17 + +/* RTCIO_X32P_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 1: enable sleep mode, 0: no sleep mode + */ + +#define RTCIO_X32P_SLP_SEL (BIT(16)) +#define RTCIO_X32P_SLP_SEL_M (RTCIO_X32P_SLP_SEL_V << RTCIO_X32P_SLP_SEL_S) +#define RTCIO_X32P_SLP_SEL_V 0x00000001 +#define RTCIO_X32P_SLP_SEL_S 16 + +/* RTCIO_X32P_SLP_IE : R/W; bitpos: [15]; default: 0; + * input enable in sleep mode + */ + +#define RTCIO_X32P_SLP_IE (BIT(15)) +#define RTCIO_X32P_SLP_IE_M (RTCIO_X32P_SLP_IE_V << RTCIO_X32P_SLP_IE_S) +#define RTCIO_X32P_SLP_IE_V 0x00000001 +#define RTCIO_X32P_SLP_IE_S 15 + +/* RTCIO_X32P_SLP_OE : R/W; bitpos: [14]; default: 0; + * output enable in sleep mode + */ + +#define RTCIO_X32P_SLP_OE (BIT(14)) +#define RTCIO_X32P_SLP_OE_M (RTCIO_X32P_SLP_OE_V << RTCIO_X32P_SLP_OE_S) +#define RTCIO_X32P_SLP_OE_V 0x00000001 +#define RTCIO_X32P_SLP_OE_S 14 + +/* RTCIO_X32P_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_X32P_FUN_IE (BIT(13)) +#define RTCIO_X32P_FUN_IE_M (RTCIO_X32P_FUN_IE_V << RTCIO_X32P_FUN_IE_S) +#define RTCIO_X32P_FUN_IE_V 0x00000001 +#define RTCIO_X32P_FUN_IE_S 13 + +/* RTCIO_XTAL_32N_PAD_REG register + * 32KHz crystal N-pad configuration register + */ + +#define RTCIO_XTAL_32N_PAD_REG (DR_REG_RTCIO_BASE + 0xc4) + +/* RTCIO_X32N_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_X32N_DRV 0x00000003 +#define RTCIO_X32N_DRV_M (RTCIO_X32N_DRV_V << RTCIO_X32N_DRV_S) +#define RTCIO_X32N_DRV_V 0x00000003 +#define RTCIO_X32N_DRV_S 29 + +/* RTCIO_X32N_RDE : R/W; bitpos: [28]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_X32N_RDE (BIT(28)) +#define RTCIO_X32N_RDE_M (RTCIO_X32N_RDE_V << RTCIO_X32N_RDE_S) +#define RTCIO_X32N_RDE_V 0x00000001 +#define RTCIO_X32N_RDE_S 28 + +/* RTCIO_X32N_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_X32N_RUE (BIT(27)) +#define RTCIO_X32N_RUE_M (RTCIO_X32N_RUE_V << RTCIO_X32N_RUE_S) +#define RTCIO_X32N_RUE_V 0x00000001 +#define RTCIO_X32N_RUE_S 27 + +/* RTCIO_X32N_MUX_SEL : R/W; bitpos: [19]; default: 0; + * 1: use RTC GPIO,0: use digital GPIO + */ + +#define RTCIO_X32N_MUX_SEL (BIT(19)) +#define RTCIO_X32N_MUX_SEL_M (RTCIO_X32N_MUX_SEL_V << RTCIO_X32N_MUX_SEL_S) +#define RTCIO_X32N_MUX_SEL_V 0x00000001 +#define RTCIO_X32N_MUX_SEL_S 19 + +/* RTCIO_X32N_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_X32N_FUN_SEL 0x00000003 +#define RTCIO_X32N_FUN_SEL_M (RTCIO_X32N_FUN_SEL_V << RTCIO_X32N_FUN_SEL_S) +#define RTCIO_X32N_FUN_SEL_V 0x00000003 +#define RTCIO_X32N_FUN_SEL_S 17 + +/* RTCIO_X32N_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 1: enable sleep mode, 0: no sleep mode + */ + +#define RTCIO_X32N_SLP_SEL (BIT(16)) +#define RTCIO_X32N_SLP_SEL_M (RTCIO_X32N_SLP_SEL_V << RTCIO_X32N_SLP_SEL_S) +#define RTCIO_X32N_SLP_SEL_V 0x00000001 +#define RTCIO_X32N_SLP_SEL_S 16 + +/* RTCIO_X32N_SLP_IE : R/W; bitpos: [15]; default: 0; + * input enable in sleep mode + */ + +#define RTCIO_X32N_SLP_IE (BIT(15)) +#define RTCIO_X32N_SLP_IE_M (RTCIO_X32N_SLP_IE_V << RTCIO_X32N_SLP_IE_S) +#define RTCIO_X32N_SLP_IE_V 0x00000001 +#define RTCIO_X32N_SLP_IE_S 15 + +/* RTCIO_X32N_SLP_OE : R/W; bitpos: [14]; default: 0; + * output enable in sleep mode + */ + +#define RTCIO_X32N_SLP_OE (BIT(14)) +#define RTCIO_X32N_SLP_OE_M (RTCIO_X32N_SLP_OE_V << RTCIO_X32N_SLP_OE_S) +#define RTCIO_X32N_SLP_OE_V 0x00000001 +#define RTCIO_X32N_SLP_OE_S 14 + +/* RTCIO_X32N_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_X32N_FUN_IE (BIT(13)) +#define RTCIO_X32N_FUN_IE_M (RTCIO_X32N_FUN_IE_V << RTCIO_X32N_FUN_IE_S) +#define RTCIO_X32N_FUN_IE_V 0x00000001 +#define RTCIO_X32N_FUN_IE_S 13 + +/* RTCIO_PAD_DAC1_REG register + * DAC1 configuration register + */ + +#define RTCIO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0xc8) + +/* RTCIO_PDAC1_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_PDAC1_DRV 0x00000003 +#define RTCIO_PDAC1_DRV_M (RTCIO_PDAC1_DRV_V << RTCIO_PDAC1_DRV_S) +#define RTCIO_PDAC1_DRV_V 0x00000003 +#define RTCIO_PDAC1_DRV_S 29 + +/* RTCIO_PDAC1_RDE : R/W; bitpos: [28]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_PDAC1_RDE (BIT(28)) +#define RTCIO_PDAC1_RDE_M (RTCIO_PDAC1_RDE_V << RTCIO_PDAC1_RDE_S) +#define RTCIO_PDAC1_RDE_V 0x00000001 +#define RTCIO_PDAC1_RDE_S 28 + +/* RTCIO_PDAC1_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_PDAC1_RUE (BIT(27)) +#define RTCIO_PDAC1_RUE_M (RTCIO_PDAC1_RUE_V << RTCIO_PDAC1_RUE_S) +#define RTCIO_PDAC1_RUE_V 0x00000001 +#define RTCIO_PDAC1_RUE_S 27 + +/* RTCIO_PDAC1_MUX_SEL : R/W; bitpos: [19]; default: 0; + * 1: use RTC GPIO, 0: use digital GPIO + */ + +#define RTCIO_PDAC1_MUX_SEL (BIT(19)) +#define RTCIO_PDAC1_MUX_SEL_M (RTCIO_PDAC1_MUX_SEL_V << RTCIO_PDAC1_MUX_SEL_S) +#define RTCIO_PDAC1_MUX_SEL_V 0x00000001 +#define RTCIO_PDAC1_MUX_SEL_S 19 + +/* RTCIO_PDAC1_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * DAC_1 function selection. + */ + +#define RTCIO_PDAC1_FUN_SEL 0x00000003 +#define RTCIO_PDAC1_FUN_SEL_M (RTCIO_PDAC1_FUN_SEL_V << RTCIO_PDAC1_FUN_SEL_S) +#define RTCIO_PDAC1_FUN_SEL_V 0x00000003 +#define RTCIO_PDAC1_FUN_SEL_S 17 + +/* RTCIO_PDAC1_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 1: enable sleep mode, 0: no sleep mode + */ + +#define RTCIO_PDAC1_SLP_SEL (BIT(16)) +#define RTCIO_PDAC1_SLP_SEL_M (RTCIO_PDAC1_SLP_SEL_V << RTCIO_PDAC1_SLP_SEL_S) +#define RTCIO_PDAC1_SLP_SEL_V 0x00000001 +#define RTCIO_PDAC1_SLP_SEL_S 16 + +/* RTCIO_PDAC1_SLP_IE : R/W; bitpos: [15]; default: 0; + * input enable in sleep mode + */ + +#define RTCIO_PDAC1_SLP_IE (BIT(15)) +#define RTCIO_PDAC1_SLP_IE_M (RTCIO_PDAC1_SLP_IE_V << RTCIO_PDAC1_SLP_IE_S) +#define RTCIO_PDAC1_SLP_IE_V 0x00000001 +#define RTCIO_PDAC1_SLP_IE_S 15 + +/* RTCIO_PDAC1_SLP_OE : R/W; bitpos: [14]; default: 0; + * output enable in sleep mode + */ + +#define RTCIO_PDAC1_SLP_OE (BIT(14)) +#define RTCIO_PDAC1_SLP_OE_M (RTCIO_PDAC1_SLP_OE_V << RTCIO_PDAC1_SLP_OE_S) +#define RTCIO_PDAC1_SLP_OE_V 0x00000001 +#define RTCIO_PDAC1_SLP_OE_S 14 + +/* RTCIO_PDAC1_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_PDAC1_FUN_IE (BIT(13)) +#define RTCIO_PDAC1_FUN_IE_M (RTCIO_PDAC1_FUN_IE_V << RTCIO_PDAC1_FUN_IE_S) +#define RTCIO_PDAC1_FUN_IE_V 0x00000001 +#define RTCIO_PDAC1_FUN_IE_S 13 + +/* RTCIO_PDAC1_DAC_XPD_FORCE : R/W; bitpos: [12]; default: 0; + * 1: use RTCIO_PDAC1_XPD_DAC to control DAC_1 output; 0: use SAR ADC FSM to + * control DAC_1 output. + */ + +#define RTCIO_PDAC1_DAC_XPD_FORCE (BIT(12)) +#define RTCIO_PDAC1_DAC_XPD_FORCE_M (RTCIO_PDAC1_DAC_XPD_FORCE_V << RTCIO_PDAC1_DAC_XPD_FORCE_S) +#define RTCIO_PDAC1_DAC_XPD_FORCE_V 0x00000001 +#define RTCIO_PDAC1_DAC_XPD_FORCE_S 12 + +/* RTCIO_PDAC1_XPD_DAC : R/W; bitpos: [11]; default: 0; + * When RTCIO_PDAC1_DAC_XPD_FORCE is set to 1, 1: enable DAC_1 output; 0: + * disable DAC_1 output. + */ + +#define RTCIO_PDAC1_XPD_DAC (BIT(11)) +#define RTCIO_PDAC1_XPD_DAC_M (RTCIO_PDAC1_XPD_DAC_V << RTCIO_PDAC1_XPD_DAC_S) +#define RTCIO_PDAC1_XPD_DAC_V 0x00000001 +#define RTCIO_PDAC1_XPD_DAC_S 11 + +/* RTCIO_PDAC1_DAC : R/W; bitpos: [10:3]; default: 0; + * Configure DAC_1 output when RTCIO_PDAC1_DAC_XPD_FORCE is set to 1. + */ + +#define RTCIO_PDAC1_DAC 0x000000FF +#define RTCIO_PDAC1_DAC_M (RTCIO_PDAC1_DAC_V << RTCIO_PDAC1_DAC_S) +#define RTCIO_PDAC1_DAC_V 0x000000FF +#define RTCIO_PDAC1_DAC_S 3 + +/* RTCIO_PAD_DAC2_REG register + * DAC2 configuration register + */ + +#define RTCIO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0xcc) + +/* RTCIO_PDAC2_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_PDAC2_DRV 0x00000003 +#define RTCIO_PDAC2_DRV_M (RTCIO_PDAC2_DRV_V << RTCIO_PDAC2_DRV_S) +#define RTCIO_PDAC2_DRV_V 0x00000003 +#define RTCIO_PDAC2_DRV_S 29 + +/* RTCIO_PDAC2_RDE : R/W; bitpos: [28]; default: 0; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_PDAC2_RDE (BIT(28)) +#define RTCIO_PDAC2_RDE_M (RTCIO_PDAC2_RDE_V << RTCIO_PDAC2_RDE_S) +#define RTCIO_PDAC2_RDE_V 0x00000001 +#define RTCIO_PDAC2_RDE_S 28 + +/* RTCIO_PDAC2_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_PDAC2_RUE (BIT(27)) +#define RTCIO_PDAC2_RUE_M (RTCIO_PDAC2_RUE_V << RTCIO_PDAC2_RUE_S) +#define RTCIO_PDAC2_RUE_V 0x00000001 +#define RTCIO_PDAC2_RUE_S 27 + +/* RTCIO_PDAC2_MUX_SEL : R/W; bitpos: [19]; default: 0; + * 1: use RTC GPIO, 0: use digital GPIO + */ + +#define RTCIO_PDAC2_MUX_SEL (BIT(19)) +#define RTCIO_PDAC2_MUX_SEL_M (RTCIO_PDAC2_MUX_SEL_V << RTCIO_PDAC2_MUX_SEL_S) +#define RTCIO_PDAC2_MUX_SEL_V 0x00000001 +#define RTCIO_PDAC2_MUX_SEL_S 19 + +/* RTCIO_PDAC2_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * DAC_2 function selection. + */ + +#define RTCIO_PDAC2_FUN_SEL 0x00000003 +#define RTCIO_PDAC2_FUN_SEL_M (RTCIO_PDAC2_FUN_SEL_V << RTCIO_PDAC2_FUN_SEL_S) +#define RTCIO_PDAC2_FUN_SEL_V 0x00000003 +#define RTCIO_PDAC2_FUN_SEL_S 17 + +/* RTCIO_PDAC2_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 1: enable sleep mode, 0: no sleep mode + */ + +#define RTCIO_PDAC2_SLP_SEL (BIT(16)) +#define RTCIO_PDAC2_SLP_SEL_M (RTCIO_PDAC2_SLP_SEL_V << RTCIO_PDAC2_SLP_SEL_S) +#define RTCIO_PDAC2_SLP_SEL_V 0x00000001 +#define RTCIO_PDAC2_SLP_SEL_S 16 + +/* RTCIO_PDAC2_SLP_IE : R/W; bitpos: [15]; default: 0; + * input enable in sleep mode + */ + +#define RTCIO_PDAC2_SLP_IE (BIT(15)) +#define RTCIO_PDAC2_SLP_IE_M (RTCIO_PDAC2_SLP_IE_V << RTCIO_PDAC2_SLP_IE_S) +#define RTCIO_PDAC2_SLP_IE_V 0x00000001 +#define RTCIO_PDAC2_SLP_IE_S 15 + +/* RTCIO_PDAC2_SLP_OE : R/W; bitpos: [14]; default: 0; + * output enable in sleep mode + */ + +#define RTCIO_PDAC2_SLP_OE (BIT(14)) +#define RTCIO_PDAC2_SLP_OE_M (RTCIO_PDAC2_SLP_OE_V << RTCIO_PDAC2_SLP_OE_S) +#define RTCIO_PDAC2_SLP_OE_V 0x00000001 +#define RTCIO_PDAC2_SLP_OE_S 14 + +/* RTCIO_PDAC2_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_PDAC2_FUN_IE (BIT(13)) +#define RTCIO_PDAC2_FUN_IE_M (RTCIO_PDAC2_FUN_IE_V << RTCIO_PDAC2_FUN_IE_S) +#define RTCIO_PDAC2_FUN_IE_V 0x00000001 +#define RTCIO_PDAC2_FUN_IE_S 13 + +/* RTCIO_PDAC2_DAC_XPD_FORCE : R/W; bitpos: [12]; default: 0; + * 1: use RTCIO_PDAC2_XPD_DAC to control DAC_2 output; 0: use SAR ADC FSM to + * control DAC_2 output. + */ + +#define RTCIO_PDAC2_DAC_XPD_FORCE (BIT(12)) +#define RTCIO_PDAC2_DAC_XPD_FORCE_M (RTCIO_PDAC2_DAC_XPD_FORCE_V << RTCIO_PDAC2_DAC_XPD_FORCE_S) +#define RTCIO_PDAC2_DAC_XPD_FORCE_V 0x00000001 +#define RTCIO_PDAC2_DAC_XPD_FORCE_S 12 + +/* RTCIO_PDAC2_XPD_DAC : R/W; bitpos: [11]; default: 0; + * When RTCIO_PDAC2_DAC_XPD_FORCE is set to 1, 1: enable DAC_2 output; 0: + * disable DAC_2 output. + */ + +#define RTCIO_PDAC2_XPD_DAC (BIT(11)) +#define RTCIO_PDAC2_XPD_DAC_M (RTCIO_PDAC2_XPD_DAC_V << RTCIO_PDAC2_XPD_DAC_S) +#define RTCIO_PDAC2_XPD_DAC_V 0x00000001 +#define RTCIO_PDAC2_XPD_DAC_S 11 + +/* RTCIO_PDAC2_DAC : R/W; bitpos: [10:3]; default: 0; + * Configure DAC_2 output when RTCIO_PDAC2_DAC_XPD_FORCE is set to 1. + */ + +#define RTCIO_PDAC2_DAC 0x000000FF +#define RTCIO_PDAC2_DAC_M (RTCIO_PDAC2_DAC_V << RTCIO_PDAC2_DAC_S) +#define RTCIO_PDAC2_DAC_V 0x000000FF +#define RTCIO_PDAC2_DAC_S 3 + +/* RTCIO_RTC_PAD19_REG register + * Touch pad 19 configuration register + */ + +#define RTCIO_RTC_PAD19_REG (DR_REG_RTCIO_BASE + 0xd0) + +/* RTCIO_RTC_PAD19_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_RTC_PAD19_DRV 0x00000003 +#define RTCIO_RTC_PAD19_DRV_M (RTCIO_RTC_PAD19_DRV_V << RTCIO_RTC_PAD19_DRV_S) +#define RTCIO_RTC_PAD19_DRV_V 0x00000003 +#define RTCIO_RTC_PAD19_DRV_S 29 + +/* RTCIO_RTC_PAD19_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_RTC_PAD19_RDE (BIT(28)) +#define RTCIO_RTC_PAD19_RDE_M (RTCIO_RTC_PAD19_RDE_V << RTCIO_RTC_PAD19_RDE_S) +#define RTCIO_RTC_PAD19_RDE_V 0x00000001 +#define RTCIO_RTC_PAD19_RDE_S 28 + +/* RTCIO_RTC_PAD19_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_RTC_PAD19_RUE (BIT(27)) +#define RTCIO_RTC_PAD19_RUE_M (RTCIO_RTC_PAD19_RUE_V << RTCIO_RTC_PAD19_RUE_S) +#define RTCIO_RTC_PAD19_RUE_V 0x00000001 +#define RTCIO_RTC_PAD19_RUE_S 27 + +/* RTCIO_RTC_PAD19_MUX_SEL : R/W; bitpos: [19]; default: 0; + * 1: use RTC GPIO, 0: use digital GPIO + */ + +#define RTCIO_RTC_PAD19_MUX_SEL (BIT(19)) +#define RTCIO_RTC_PAD19_MUX_SEL_M (RTCIO_RTC_PAD19_MUX_SEL_V << RTCIO_RTC_PAD19_MUX_SEL_S) +#define RTCIO_RTC_PAD19_MUX_SEL_V 0x00000001 +#define RTCIO_RTC_PAD19_MUX_SEL_S 19 + +/* RTCIO_RTC_PAD19_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_RTC_PAD19_FUN_SEL 0x00000003 +#define RTCIO_RTC_PAD19_FUN_SEL_M (RTCIO_RTC_PAD19_FUN_SEL_V << RTCIO_RTC_PAD19_FUN_SEL_S) +#define RTCIO_RTC_PAD19_FUN_SEL_V 0x00000003 +#define RTCIO_RTC_PAD19_FUN_SEL_S 17 + +/* RTCIO_RTC_PAD19_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 1: enable sleep mode, 0: no sleep mode + */ + +#define RTCIO_RTC_PAD19_SLP_SEL (BIT(16)) +#define RTCIO_RTC_PAD19_SLP_SEL_M (RTCIO_RTC_PAD19_SLP_SEL_V << RTCIO_RTC_PAD19_SLP_SEL_S) +#define RTCIO_RTC_PAD19_SLP_SEL_V 0x00000001 +#define RTCIO_RTC_PAD19_SLP_SEL_S 16 + +/* RTCIO_RTC_PAD19_SLP_IE : R/W; bitpos: [15]; default: 0; + * input enable in sleep mode + */ + +#define RTCIO_RTC_PAD19_SLP_IE (BIT(15)) +#define RTCIO_RTC_PAD19_SLP_IE_M (RTCIO_RTC_PAD19_SLP_IE_V << RTCIO_RTC_PAD19_SLP_IE_S) +#define RTCIO_RTC_PAD19_SLP_IE_V 0x00000001 +#define RTCIO_RTC_PAD19_SLP_IE_S 15 + +/* RTCIO_RTC_PAD19_SLP_OE : R/W; bitpos: [14]; default: 0; + * output enable in sleep mode + */ + +#define RTCIO_RTC_PAD19_SLP_OE (BIT(14)) +#define RTCIO_RTC_PAD19_SLP_OE_M (RTCIO_RTC_PAD19_SLP_OE_V << RTCIO_RTC_PAD19_SLP_OE_S) +#define RTCIO_RTC_PAD19_SLP_OE_V 0x00000001 +#define RTCIO_RTC_PAD19_SLP_OE_S 14 + +/* RTCIO_RTC_PAD19_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_RTC_PAD19_FUN_IE (BIT(13)) +#define RTCIO_RTC_PAD19_FUN_IE_M (RTCIO_RTC_PAD19_FUN_IE_V << RTCIO_RTC_PAD19_FUN_IE_S) +#define RTCIO_RTC_PAD19_FUN_IE_V 0x00000001 +#define RTCIO_RTC_PAD19_FUN_IE_S 13 + +/* RTCIO_RTC_PAD20_REG register + * Touch pad 20 configuration register + */ + +#define RTCIO_RTC_PAD20_REG (DR_REG_RTCIO_BASE + 0xd4) + +/* RTCIO_RTC_PAD20_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_RTC_PAD20_DRV 0x00000003 +#define RTCIO_RTC_PAD20_DRV_M (RTCIO_RTC_PAD20_DRV_V << RTCIO_RTC_PAD20_DRV_S) +#define RTCIO_RTC_PAD20_DRV_V 0x00000003 +#define RTCIO_RTC_PAD20_DRV_S 29 + +/* RTCIO_RTC_PAD20_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_RTC_PAD20_RDE (BIT(28)) +#define RTCIO_RTC_PAD20_RDE_M (RTCIO_RTC_PAD20_RDE_V << RTCIO_RTC_PAD20_RDE_S) +#define RTCIO_RTC_PAD20_RDE_V 0x00000001 +#define RTCIO_RTC_PAD20_RDE_S 28 + +/* RTCIO_RTC_PAD20_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_RTC_PAD20_RUE (BIT(27)) +#define RTCIO_RTC_PAD20_RUE_M (RTCIO_RTC_PAD20_RUE_V << RTCIO_RTC_PAD20_RUE_S) +#define RTCIO_RTC_PAD20_RUE_V 0x00000001 +#define RTCIO_RTC_PAD20_RUE_S 27 + +/* RTCIO_RTC_PAD20_MUX_SEL : R/W; bitpos: [19]; default: 0; + * 1: use RTC GPIO, 0: use digital GPIO + */ + +#define RTCIO_RTC_PAD20_MUX_SEL (BIT(19)) +#define RTCIO_RTC_PAD20_MUX_SEL_M (RTCIO_RTC_PAD20_MUX_SEL_V << RTCIO_RTC_PAD20_MUX_SEL_S) +#define RTCIO_RTC_PAD20_MUX_SEL_V 0x00000001 +#define RTCIO_RTC_PAD20_MUX_SEL_S 19 + +/* RTCIO_RTC_PAD20_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_RTC_PAD20_FUN_SEL 0x00000003 +#define RTCIO_RTC_PAD20_FUN_SEL_M (RTCIO_RTC_PAD20_FUN_SEL_V << RTCIO_RTC_PAD20_FUN_SEL_S) +#define RTCIO_RTC_PAD20_FUN_SEL_V 0x00000003 +#define RTCIO_RTC_PAD20_FUN_SEL_S 17 + +/* RTCIO_RTC_PAD20_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 1: enable sleep mode, 0: no sleep mode + */ + +#define RTCIO_RTC_PAD20_SLP_SEL (BIT(16)) +#define RTCIO_RTC_PAD20_SLP_SEL_M (RTCIO_RTC_PAD20_SLP_SEL_V << RTCIO_RTC_PAD20_SLP_SEL_S) +#define RTCIO_RTC_PAD20_SLP_SEL_V 0x00000001 +#define RTCIO_RTC_PAD20_SLP_SEL_S 16 + +/* RTCIO_RTC_PAD20_SLP_IE : R/W; bitpos: [15]; default: 0; + * input enable in sleep mode + */ + +#define RTCIO_RTC_PAD20_SLP_IE (BIT(15)) +#define RTCIO_RTC_PAD20_SLP_IE_M (RTCIO_RTC_PAD20_SLP_IE_V << RTCIO_RTC_PAD20_SLP_IE_S) +#define RTCIO_RTC_PAD20_SLP_IE_V 0x00000001 +#define RTCIO_RTC_PAD20_SLP_IE_S 15 + +/* RTCIO_RTC_PAD20_SLP_OE : R/W; bitpos: [14]; default: 0; + * output enable in sleep mode + */ + +#define RTCIO_RTC_PAD20_SLP_OE (BIT(14)) +#define RTCIO_RTC_PAD20_SLP_OE_M (RTCIO_RTC_PAD20_SLP_OE_V << RTCIO_RTC_PAD20_SLP_OE_S) +#define RTCIO_RTC_PAD20_SLP_OE_V 0x00000001 +#define RTCIO_RTC_PAD20_SLP_OE_S 14 + +/* RTCIO_RTC_PAD20_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_RTC_PAD20_FUN_IE (BIT(13)) +#define RTCIO_RTC_PAD20_FUN_IE_M (RTCIO_RTC_PAD20_FUN_IE_V << RTCIO_RTC_PAD20_FUN_IE_S) +#define RTCIO_RTC_PAD20_FUN_IE_V 0x00000001 +#define RTCIO_RTC_PAD20_FUN_IE_S 13 + +/* RTCIO_RTC_PAD21_REG register + * Touch pad 21 configuration register + */ + +#define RTCIO_RTC_PAD21_REG (DR_REG_RTCIO_BASE + 0xd8) + +/* RTCIO_RTC_PAD21_DRV : R/W; bitpos: [30:29]; default: 2; + * Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA: 2: ~20 mA; 3: + * ~40 mA. + */ + +#define RTCIO_RTC_PAD21_DRV 0x00000003 +#define RTCIO_RTC_PAD21_DRV_M (RTCIO_RTC_PAD21_DRV_V << RTCIO_RTC_PAD21_DRV_S) +#define RTCIO_RTC_PAD21_DRV_V 0x00000003 +#define RTCIO_RTC_PAD21_DRV_S 29 + +/* RTCIO_RTC_PAD21_RDE : R/W; bitpos: [28]; default: 1; + * Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal + * pull-up disabled. + */ + +#define RTCIO_RTC_PAD21_RDE (BIT(28)) +#define RTCIO_RTC_PAD21_RDE_M (RTCIO_RTC_PAD21_RDE_V << RTCIO_RTC_PAD21_RDE_S) +#define RTCIO_RTC_PAD21_RDE_V 0x00000001 +#define RTCIO_RTC_PAD21_RDE_S 28 + +/* RTCIO_RTC_PAD21_RUE : R/W; bitpos: [27]; default: 0; + * Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal + * pull-down disabled. + */ + +#define RTCIO_RTC_PAD21_RUE (BIT(27)) +#define RTCIO_RTC_PAD21_RUE_M (RTCIO_RTC_PAD21_RUE_V << RTCIO_RTC_PAD21_RUE_S) +#define RTCIO_RTC_PAD21_RUE_V 0x00000001 +#define RTCIO_RTC_PAD21_RUE_S 27 + +/* RTCIO_RTC_PAD21_MUX_SEL : R/W; bitpos: [19]; default: 0; + * 1: use RTC GPIO, 0: use digital GPIO + */ + +#define RTCIO_RTC_PAD21_MUX_SEL (BIT(19)) +#define RTCIO_RTC_PAD21_MUX_SEL_M (RTCIO_RTC_PAD21_MUX_SEL_V << RTCIO_RTC_PAD21_MUX_SEL_S) +#define RTCIO_RTC_PAD21_MUX_SEL_V 0x00000001 +#define RTCIO_RTC_PAD21_MUX_SEL_S 19 + +/* RTCIO_RTC_PAD21_FUN_SEL : R/W; bitpos: [18:17]; default: 0; + * Function selection. + */ + +#define RTCIO_RTC_PAD21_FUN_SEL 0x00000003 +#define RTCIO_RTC_PAD21_FUN_SEL_M (RTCIO_RTC_PAD21_FUN_SEL_V << RTCIO_RTC_PAD21_FUN_SEL_S) +#define RTCIO_RTC_PAD21_FUN_SEL_V 0x00000003 +#define RTCIO_RTC_PAD21_FUN_SEL_S 17 + +/* RTCIO_RTC_PAD21_SLP_SEL : R/W; bitpos: [16]; default: 0; + * 1: enable sleep mode, 0: no sleep mode + */ + +#define RTCIO_RTC_PAD21_SLP_SEL (BIT(16)) +#define RTCIO_RTC_PAD21_SLP_SEL_M (RTCIO_RTC_PAD21_SLP_SEL_V << RTCIO_RTC_PAD21_SLP_SEL_S) +#define RTCIO_RTC_PAD21_SLP_SEL_V 0x00000001 +#define RTCIO_RTC_PAD21_SLP_SEL_S 16 + +/* RTCIO_RTC_PAD21_SLP_IE : R/W; bitpos: [15]; default: 0; + * input enable in sleep mode + */ + +#define RTCIO_RTC_PAD21_SLP_IE (BIT(15)) +#define RTCIO_RTC_PAD21_SLP_IE_M (RTCIO_RTC_PAD21_SLP_IE_V << RTCIO_RTC_PAD21_SLP_IE_S) +#define RTCIO_RTC_PAD21_SLP_IE_V 0x00000001 +#define RTCIO_RTC_PAD21_SLP_IE_S 15 + +/* RTCIO_RTC_PAD21_SLP_OE : R/W; bitpos: [14]; default: 0; + * output enable in sleep mode + */ + +#define RTCIO_RTC_PAD21_SLP_OE (BIT(14)) +#define RTCIO_RTC_PAD21_SLP_OE_M (RTCIO_RTC_PAD21_SLP_OE_V << RTCIO_RTC_PAD21_SLP_OE_S) +#define RTCIO_RTC_PAD21_SLP_OE_V 0x00000001 +#define RTCIO_RTC_PAD21_SLP_OE_S 14 + +/* RTCIO_RTC_PAD21_FUN_IE : R/W; bitpos: [13]; default: 0; + * Input enable in normal execution. + */ + +#define RTCIO_RTC_PAD21_FUN_IE (BIT(13)) +#define RTCIO_RTC_PAD21_FUN_IE_M (RTCIO_RTC_PAD21_FUN_IE_V << RTCIO_RTC_PAD21_FUN_IE_S) +#define RTCIO_RTC_PAD21_FUN_IE_V 0x00000001 +#define RTCIO_RTC_PAD21_FUN_IE_S 13 + +/* RTCIO_EXT_WAKEUP0_REG register + * External wake up configuration register + */ + +#define RTCIO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xdc) + +/* RTCIO_EXT_WAKEUP0_SEL : R/W; bitpos: [31:27]; default: 0; + * GPIO[0-17] can be used to wake up the chip when the chip is in the sleep + * mode. This register prompts the pad source to wake up the chip when the + * latter is indeep/light sleep mode. + * 0: select GPIO0; 1: select GPIO2, etc + */ + +#define RTCIO_EXT_WAKEUP0_SEL 0x0000001F +#define RTCIO_EXT_WAKEUP0_SEL_M (RTCIO_EXT_WAKEUP0_SEL_V << RTCIO_EXT_WAKEUP0_SEL_S) +#define RTCIO_EXT_WAKEUP0_SEL_V 0x0000001F +#define RTCIO_EXT_WAKEUP0_SEL_S 27 + +/* RTCIO_XTL_EXT_CTR_REG register + * Crystal power down enable GPIO source + */ + +#define RTCIO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xe0) + +/* RTCIO_XTL_EXT_CTR_SEL : R/W; bitpos: [31:27]; default: 0; + * Select the external crystal power down enable source to get into sleep + * mode. 0: select GPIO0; 1: select GPIO1, etc. The input value on this pin + * XOR RTC_CNTL_EXT_XTL_CONF_REG[30] is the crystal power down enable signal. + */ + +#define RTCIO_XTL_EXT_CTR_SEL 0x0000001F +#define RTCIO_XTL_EXT_CTR_SEL_M (RTCIO_XTL_EXT_CTR_SEL_V << RTCIO_XTL_EXT_CTR_SEL_S) +#define RTCIO_XTL_EXT_CTR_SEL_V 0x0000001F +#define RTCIO_XTL_EXT_CTR_SEL_S 27 + +/* RTCIO_SAR_I2C_IO_REG register + * RTC I²C pad selection + */ + +#define RTCIO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xe4) + +/* RTCIO_SAR_I2C_SDA_SEL : R/W; bitpos: [31:30]; default: 0; + * Selects a pad the RTC I2C SDA signal connects to. 0: use TOUCH PAD1; 1: + * use TOUCH PAD3. + */ + +#define RTCIO_SAR_I2C_SDA_SEL 0x00000003 +#define RTCIO_SAR_I2C_SDA_SEL_M (RTCIO_SAR_I2C_SDA_SEL_V << RTCIO_SAR_I2C_SDA_SEL_S) +#define RTCIO_SAR_I2C_SDA_SEL_V 0x00000003 +#define RTCIO_SAR_I2C_SDA_SEL_S 30 + +/* RTCIO_SAR_I2C_SCL_SEL : R/W; bitpos: [29:28]; default: 0; + * Selects a pad the RTC I2C SCL signal connects to. 0: use TOUCH PAD0; 1: + * use TOUCH PAD2. + */ + +#define RTCIO_SAR_I2C_SCL_SEL 0x00000003 +#define RTCIO_SAR_I2C_SCL_SEL_M (RTCIO_SAR_I2C_SCL_SEL_V << RTCIO_SAR_I2C_SCL_SEL_S) +#define RTCIO_SAR_I2C_SCL_SEL_V 0x00000003 +#define RTCIO_SAR_I2C_SCL_SEL_S 28 + +/* RTCIO_SAR_DEBUG_BIT_SEL : R/W; bitpos: [27:23]; default: 0; */ + +#define RTCIO_SAR_DEBUG_BIT_SEL 0x0000001F +#define RTCIO_SAR_DEBUG_BIT_SEL_M (RTCIO_SAR_DEBUG_BIT_SEL_V << RTCIO_SAR_DEBUG_BIT_SEL_S) +#define RTCIO_SAR_DEBUG_BIT_SEL_V 0x0000001F +#define RTCIO_SAR_DEBUG_BIT_SEL_S 23 + +/* RTCIO_RTC_IO_TOUCH_CTRL_REG register + * Touch Control register + */ + +#define RTCIO_RTC_IO_TOUCH_CTRL_REG (DR_REG_RTCIO_BASE + 0xe8) + +/* RTCIO_IO_TOUCH_BUFMODE : R/W; bitpos: [4]; default: 0; */ + +#define RTCIO_IO_TOUCH_BUFMODE (BIT(4)) +#define RTCIO_IO_TOUCH_BUFMODE_M (RTCIO_IO_TOUCH_BUFMODE_V << RTCIO_IO_TOUCH_BUFMODE_S) +#define RTCIO_IO_TOUCH_BUFMODE_V 0x00000001 +#define RTCIO_IO_TOUCH_BUFMODE_S 4 + +/* RTCIO_IO_TOUCH_BUFSEL : R/W; bitpos: [3:0]; default: 0; */ + +#define RTCIO_IO_TOUCH_BUFSEL 0x0000000F +#define RTCIO_IO_TOUCH_BUFSEL_M (RTCIO_IO_TOUCH_BUFSEL_V << RTCIO_IO_TOUCH_BUFSEL_S) +#define RTCIO_IO_TOUCH_BUFSEL_V 0x0000000F +#define RTCIO_IO_TOUCH_BUFSEL_S 0 + +/* RTCIO_RTC_IO_DATE_REG register + * Version control register + */ + +#define RTCIO_RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0x1fc) + +/* RTCIO_IO_DATE : R/W; bitpos: [27:0]; default: 26227056; + * Version control register + */ + +#define RTCIO_IO_DATE 0x0FFFFFFF +#define RTCIO_IO_DATE_M (RTCIO_IO_DATE_V << RTCIO_IO_DATE_S) +#define RTCIO_IO_DATE_V 0x0FFFFFFF +#define RTCIO_IO_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTCIO_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h new file mode 100644 index 0000000000..7b7f7b37c5 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h @@ -0,0 +1,4419 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTC_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DPORT_CPUPERIOD_SEL_80 0 +#define DPORT_CPUPERIOD_SEL_160 1 +#define DPORT_CPUPERIOD_SEL_240 2 + +#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG + +/* RTC_CNTL_OPTIONS0_REG register + * set xtal and pll power and sw reset register + */ + +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) + +/* RTC_CNTL_SW_SYS_RST : WO; bitpos: [31]; default: 0; + * SW system reset + */ + +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (RTC_CNTL_SW_SYS_RST_V << RTC_CNTL_SW_SYS_RST_S) +#define RTC_CNTL_SW_SYS_RST_V 0x00000001 +#define RTC_CNTL_SW_SYS_RST_S 31 + +/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W; bitpos: [30]; default: 0; + * digital core force no reset in deep sleep + */ + +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (RTC_CNTL_DG_WRAP_FORCE_NORST_V << RTC_CNTL_DG_WRAP_FORCE_NORST_S) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x00000001 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 + +/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W; bitpos: [29]; default: 0; + * digital wrap force reset in deep sleep + */ + +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (RTC_CNTL_DG_WRAP_FORCE_RST_V << RTC_CNTL_DG_WRAP_FORCE_RST_S) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x00000001 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 + +/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W; bitpos: [28]; default: 1; */ + +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (RTC_CNTL_ANALOG_FORCE_NOISO_V << RTC_CNTL_ANALOG_FORCE_NOISO_S) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 + +/* RTC_CNTL_PLL_FORCE_NOISO : R/W; bitpos: [27]; default: 1; */ + +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (RTC_CNTL_PLL_FORCE_NOISO_V << RTC_CNTL_PLL_FORCE_NOISO_S) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 + +/* RTC_CNTL_XTL_FORCE_NOISO : R/W; bitpos: [26]; default: 1; */ + +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (RTC_CNTL_XTL_FORCE_NOISO_V << RTC_CNTL_XTL_FORCE_NOISO_S) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 + +/* RTC_CNTL_ANALOG_FORCE_ISO : R/W; bitpos: [25]; default: 0; */ + +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (RTC_CNTL_ANALOG_FORCE_ISO_V << RTC_CNTL_ANALOG_FORCE_ISO_S) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 + +/* RTC_CNTL_PLL_FORCE_ISO : R/W; bitpos: [24]; default: 0; */ + +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (RTC_CNTL_PLL_FORCE_ISO_V << RTC_CNTL_PLL_FORCE_ISO_S) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 + +/* RTC_CNTL_XTL_FORCE_ISO : R/W; bitpos: [23]; default: 0; */ + +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (RTC_CNTL_XTL_FORCE_ISO_V << RTC_CNTL_XTL_FORCE_ISO_S) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 + +/* RTC_CNTL_XTL_FORCE_PU : R/W; bitpos: [13]; default: 1; + * crystall force power up + */ + +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (RTC_CNTL_XTL_FORCE_PU_V << RTC_CNTL_XTL_FORCE_PU_S) +#define RTC_CNTL_XTL_FORCE_PU_V 0x00000001 +#define RTC_CNTL_XTL_FORCE_PU_S 13 + +/* RTC_CNTL_XTL_FORCE_PD : R/W; bitpos: [12]; default: 0; + * crystall force power down + */ + +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (RTC_CNTL_XTL_FORCE_PD_V << RTC_CNTL_XTL_FORCE_PD_S) +#define RTC_CNTL_XTL_FORCE_PD_V 0x00000001 +#define RTC_CNTL_XTL_FORCE_PD_S 12 + +/* RTC_CNTL_BBPLL_FORCE_PU : R/W; bitpos: [11]; default: 0; + * BB_PLL force power up + */ + +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (RTC_CNTL_BBPLL_FORCE_PU_V << RTC_CNTL_BBPLL_FORCE_PU_S) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x00000001 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 + +/* RTC_CNTL_BBPLL_FORCE_PD : R/W; bitpos: [10]; default: 0; + * BB_PLL force power down + */ + +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (RTC_CNTL_BBPLL_FORCE_PD_V << RTC_CNTL_BBPLL_FORCE_PD_S) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x00000001 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 + +/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W; bitpos: [9]; default: 0; + * BB_PLL_I2C force power up + */ + +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (RTC_CNTL_BBPLL_I2C_FORCE_PU_V << RTC_CNTL_BBPLL_I2C_FORCE_PU_S) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x00000001 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 + +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W; bitpos: [8]; default: 0; + * BB_PLL _I2C force power down + */ + +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (RTC_CNTL_BBPLL_I2C_FORCE_PD_V << RTC_CNTL_BBPLL_I2C_FORCE_PD_S) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x00000001 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 + +/* RTC_CNTL_BB_I2C_FORCE_PU : R/W; bitpos: [7]; default: 0; + * BB_I2C force power up + */ + +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (RTC_CNTL_BB_I2C_FORCE_PU_V << RTC_CNTL_BB_I2C_FORCE_PU_S) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x00000001 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 + +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W; bitpos: [6]; default: 0; + * BB_I2C force power down + */ + +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (RTC_CNTL_BB_I2C_FORCE_PD_V << RTC_CNTL_BB_I2C_FORCE_PD_S) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x00000001 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 + +/* RTC_CNTL_SW_PROCPU_RST : WO; bitpos: [5]; default: 0; + * PRO CPU SW reset + */ + +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (RTC_CNTL_SW_PROCPU_RST_V << RTC_CNTL_SW_PROCPU_RST_S) +#define RTC_CNTL_SW_PROCPU_RST_V 0x00000001 +#define RTC_CNTL_SW_PROCPU_RST_S 5 + +/* RTC_CNTL_SW_APPCPU_RST : WO; bitpos: [4]; default: 0; + * APP CPU SW reset + */ + +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (RTC_CNTL_SW_APPCPU_RST_V << RTC_CNTL_SW_APPCPU_RST_S) +#define RTC_CNTL_SW_APPCPU_RST_V 0x00000001 +#define RTC_CNTL_SW_APPCPU_RST_S 4 + +/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W; bitpos: [3:2]; default: 0; + * {reg_sw_stall_procpu_c1[5:0] , reg_sw_stall_procpu_c0[1:0]} == 0x86 will + * stall PRO CPU + */ + +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M (RTC_CNTL_SW_STALL_PROCPU_C0_V << RTC_CNTL_SW_STALL_PROCPU_C0_S) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 + +/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W; bitpos: [1:0]; default: 0; + * {reg_sw_stall_appcpu_c1[5:0] , reg_sw_stall_appcpu_c0[1:0]} == 0x86 will + * stall APP CPU + */ + +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M (RTC_CNTL_SW_STALL_APPCPU_C0_V << RTC_CNTL_SW_STALL_APPCPU_C0_S) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 + +/* RTC_CNTL_SLP_TIMER0_REG register + * rtc_sleep_timer0 register + */ + +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) + +/* RTC_CNTL_SLP_VAL_LO : R/W; bitpos: [31:0]; default: 0; + * RTC sleep timer low 32 bits + */ + +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M (RTC_CNTL_SLP_VAL_LO_V << RTC_CNTL_SLP_VAL_LO_S) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 + +/* RTC_CNTL_SLP_TIMER1_REG register + * rtc_sleep_timer1 register + */ + +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) + +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO; bitpos: [16]; default: 0; + * timer alarm enable bit + */ + +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (RTC_CNTL_MAIN_TIMER_ALARM_EN_V << RTC_CNTL_MAIN_TIMER_ALARM_EN_S) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x00000001 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 + +/* RTC_CNTL_SLP_VAL_HI : R/W; bitpos: [15:0]; default: 0; + * RTC sleep timer high 16 bits + */ + +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M (RTC_CNTL_SLP_VAL_HI_V << RTC_CNTL_SLP_VAL_HI_S) +#define RTC_CNTL_SLP_VAL_HI_V 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 + +/* RTC_CNTL_TIME_UPDATE_REG register + * rtc time update register + */ + +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) + +/* RTC_CNTL_TIME_UPDATE : WO; bitpos: [31]; default: 0; + * Set 1: to update register with RTC timer + */ + +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (RTC_CNTL_TIME_UPDATE_V << RTC_CNTL_TIME_UPDATE_S) +#define RTC_CNTL_TIME_UPDATE_V 0x00000001 +#define RTC_CNTL_TIME_UPDATE_S 31 + +/* RTC_CNTL_TIMER_SYS_RST : R/W; bitpos: [29]; default: 0; + * enable to record system reset time + */ + +#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_M (RTC_CNTL_TIMER_SYS_RST_V << RTC_CNTL_TIMER_SYS_RST_S) +#define RTC_CNTL_TIMER_SYS_RST_V 0x00000001 +#define RTC_CNTL_TIMER_SYS_RST_S 29 + +/* RTC_CNTL_TIMER_XTL_OFF : R/W; bitpos: [28]; default: 0; + * Enable to record 40M XTAL OFF time + */ + +#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_M (RTC_CNTL_TIMER_XTL_OFF_V << RTC_CNTL_TIMER_XTL_OFF_S) +#define RTC_CNTL_TIMER_XTL_OFF_V 0x00000001 +#define RTC_CNTL_TIMER_XTL_OFF_S 28 + +/* RTC_CNTL_TIMER_SYS_STALL : R/W; bitpos: [27]; default: 0; + * Enable to record system stall time + */ + +#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_M (RTC_CNTL_TIMER_SYS_STALL_V << RTC_CNTL_TIMER_SYS_STALL_S) +#define RTC_CNTL_TIMER_SYS_STALL_V 0x00000001 +#define RTC_CNTL_TIMER_SYS_STALL_S 27 + +/* RTC_CNTL_TIME_LOW0_REG register + * RTC timer0 low 32 bits + */ + +#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10) + +/* RTC_CNTL_TIMER_VALUE0_LOW : RO; bitpos: [31:0]; default: 0; + * RTC timer low 32 bits + */ + +#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_M (RTC_CNTL_TIMER_VALUE0_LOW_V << RTC_CNTL_TIMER_VALUE0_LOW_S) +#define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_S 0 + +/* RTC_CNTL_TIME_HIGH0_REG register + * RTC timer0 high16 bits + */ + +#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14) + +/* RTC_CNTL_TIMER_VALUE0_HIGH : RO; bitpos: [15:0]; default: 0; + * RTC timer high 16 bits + */ + +#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_M (RTC_CNTL_TIMER_VALUE0_HIGH_V << RTC_CNTL_TIMER_VALUE0_HIGH_S) +#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 + +/* RTC_CNTL_STATE0_REG register + * configure sleep/reject/wakeup state + */ + +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) + +/* RTC_CNTL_SLEEP_EN : R/W; bitpos: [31]; default: 0; + * sleep enable bit + */ + +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (RTC_CNTL_SLEEP_EN_V << RTC_CNTL_SLEEP_EN_S) +#define RTC_CNTL_SLEEP_EN_V 0x00000001 +#define RTC_CNTL_SLEEP_EN_S 31 + +/* RTC_CNTL_SLP_REJECT : R/W; bitpos: [30]; default: 0; + * leep reject bit + */ + +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (RTC_CNTL_SLP_REJECT_V << RTC_CNTL_SLP_REJECT_S) +#define RTC_CNTL_SLP_REJECT_V 0x00000001 +#define RTC_CNTL_SLP_REJECT_S 30 + +/* RTC_CNTL_SLP_WAKEUP : R/W; bitpos: [29]; default: 0; + * leep wakeup bit + */ + +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (RTC_CNTL_SLP_WAKEUP_V << RTC_CNTL_SLP_WAKEUP_S) +#define RTC_CNTL_SLP_WAKEUP_V 0x00000001 +#define RTC_CNTL_SLP_WAKEUP_S 29 + +/* RTC_CNTL_SDIO_ACTIVE_IND : RO; bitpos: [28]; default: 0; + * SDIO active indication + */ + +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (RTC_CNTL_SDIO_ACTIVE_IND_V << RTC_CNTL_SDIO_ACTIVE_IND_S) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x00000001 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 + +/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W; bitpos: [22]; default: 0; + * 1: APB to RTC using bridge 0: APB to RTC using sync + */ + +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (RTC_CNTL_APB2RTC_BRIDGE_SEL_V << RTC_CNTL_APB2RTC_BRIDGE_SEL_S) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x00000001 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 + +/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; + *description: clear rtc sleep reject cause + */ + +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 + +/* RTC_CNTL_SW_CPU_INT : WO; bitpos: [0]; default: 0; + * rtc software interrupt to main cpu + */ + +#define RTC_CNTL_SW_CPU_INT (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_M (RTC_CNTL_SW_CPU_INT_V << RTC_CNTL_SW_CPU_INT_S) +#define RTC_CNTL_SW_CPU_INT_V 0x00000001 +#define RTC_CNTL_SW_CPU_INT_S 0 + +/* RTC_CNTL_TIMER1_REG register + * configure time that wait analog state stable + */ + +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) + +/* RTC_CNTL_PLL_BUF_WAIT : R/W; bitpos: [31:24]; default: 40; + * PLL wait cycles in slow_clk_rtc + */ + +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M (RTC_CNTL_PLL_BUF_WAIT_V << RTC_CNTL_PLL_BUF_WAIT_S) +#define RTC_CNTL_PLL_BUF_WAIT_V 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 + +/* RTC_CNTL_XTL_BUF_WAIT : R/W; bitpos: [23:14]; default: 80; + * XTAL wait cycles in slow_clk_rtc + */ + +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M (RTC_CNTL_XTL_BUF_WAIT_V << RTC_CNTL_XTL_BUF_WAIT_S) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 20 + +/* RTC_CNTL_CK8M_WAIT : R/W; bitpos: [13:6]; default: 16; + * CK8M wait cycles in slow_clk_rtc + */ + +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M (RTC_CNTL_CK8M_WAIT_V << RTC_CNTL_CK8M_WAIT_S) +#define RTC_CNTL_CK8M_WAIT_V 0x000000FF +#define RTC_CNTL_CK8M_WAIT_S 6 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 + +/* RTC_CNTL_CPU_STALL_WAIT : R/W; bitpos: [5:1]; default: 1; + * CPU stall wait cycles in fast_clk_rtc + */ + +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M (RTC_CNTL_CPU_STALL_WAIT_V << RTC_CNTL_CPU_STALL_WAIT_S) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 + +/* RTC_CNTL_CPU_STALL_EN : R/W; bitpos: [0]; default: 1; + * CPU stall enable bit + */ + +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (RTC_CNTL_CPU_STALL_EN_V << RTC_CNTL_CPU_STALL_EN_S) +#define RTC_CNTL_CPU_STALL_EN_V 0x00000001 +#define RTC_CNTL_CPU_STALL_EN_S 0 + +/* RTC_CNTL_TIMER2_REG register + * configure time that wait analog state stable + */ + +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) + +/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W; bitpos: [31:24]; default: 1; + * minimal cycles in slow_clk_rtc for CK8M in power down state + */ + +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M (RTC_CNTL_MIN_TIME_CK8M_OFF_V << RTC_CNTL_MIN_TIME_CK8M_OFF_S) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 + +/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W; bitpos: [23:15]; default: 16; + * wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller + * start to work + */ + +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M (RTC_CNTL_ULPCP_TOUCH_START_WAIT_V << RTC_CNTL_ULPCP_TOUCH_START_WAIT_S) +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x000001FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 + +/* RTC_CNTL_TIMER3_REG register + * configure some wait time for power on + */ + +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) + +/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 10; */ + +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M (RTC_CNTL_ROM_RAM_POWERUP_TIMER_V << RTC_CNTL_ROM_RAM_POWERUP_TIMER_S) +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x0000007F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 + +/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W; bitpos: [24:16]; default: 22; */ + +#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M (RTC_CNTL_ROM_RAM_WAIT_TIMER_V << RTC_CNTL_ROM_RAM_WAIT_TIMER_S) +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x000001FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 + +/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W; bitpos: [15:9]; default: 5; */ + +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M (RTC_CNTL_WIFI_POWERUP_TIMER_V << RTC_CNTL_WIFI_POWERUP_TIMER_S) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 + +/* RTC_CNTL_WIFI_WAIT_TIMER : R/W; bitpos: [8:0]; default: 8; */ + +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M (RTC_CNTL_WIFI_WAIT_TIMER_V << RTC_CNTL_WIFI_WAIT_TIMER_S) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 + +/* RTC_CNTL_TIMER4_REG register + * configure some wait time for power on + */ + +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) + +/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 8; */ + +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M (RTC_CNTL_DG_WRAP_POWERUP_TIMER_V << RTC_CNTL_DG_WRAP_POWERUP_TIMER_S) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 + +/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W; bitpos: [24:16]; default: 32; */ + +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M (RTC_CNTL_DG_WRAP_WAIT_TIMER_V << RTC_CNTL_DG_WRAP_WAIT_TIMER_S) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 + +/* RTC_CNTL_POWERUP_TIMER : R/W; bitpos: [15:9]; default: 5; */ + +#define RTC_CNTL_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_POWERUP_TIMER_M (RTC_CNTL_POWERUP_TIMER_V << RTC_CNTL_POWERUP_TIMER_S) +#define RTC_CNTL_POWERUP_TIMER_V 0x0000007F +#define RTC_CNTL_POWERUP_TIMER_S 9 + +/* RTC_CNTL_WAIT_TIMER : R/W; bitpos: [8:0]; default: 8; */ + +#define RTC_CNTL_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WAIT_TIMER_M (RTC_CNTL_WAIT_TIMER_V << RTC_CNTL_WAIT_TIMER_S) +#define RTC_CNTL_WAIT_TIMER_V 0x000001FF +#define RTC_CNTL_WAIT_TIMER_S 0 + +/* RTC_CNTL_TIMER5_REG register + * Configure minimal sleep cycles register + */ + +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) + +/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 9; */ + +#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M (RTC_CNTL_RTCMEM_POWERUP_TIMER_V << RTC_CNTL_RTCMEM_POWERUP_TIMER_S) +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x0000007F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 + +/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W; bitpos: [24:16]; default: 20; */ + +#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_M (RTC_CNTL_RTCMEM_WAIT_TIMER_V << RTC_CNTL_RTCMEM_WAIT_TIMER_S) +#define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x000001FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 + +/* RTC_CNTL_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 128; + * minimal sleep cycles in slow_clk_rtc + */ + +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M (RTC_CNTL_MIN_SLP_VAL_V << RTC_CNTL_MIN_SLP_VAL_S) +#define RTC_CNTL_MIN_SLP_VAL_V 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_S 8 +#define RTC_CNTL_MIN_SLP_VAL_MIN 2 + +/* RTC_CNTL_TIMER6_REG register + * Configure minimal sleep cycles register + */ + +#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x30) + +/* RTC_CNTL_DG_DCDC_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 8; */ + +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_M (RTC_CNTL_DG_DCDC_POWERUP_TIMER_V << RTC_CNTL_DG_DCDC_POWERUP_TIMER_S) +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_V 0x0000007F +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_S 25 + +/* RTC_CNTL_DG_DCDC_WAIT_TIMER : R/W; bitpos: [24:16]; default: 32; */ + +#define RTC_CNTL_DG_DCDC_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_M (RTC_CNTL_DG_DCDC_WAIT_TIMER_V << RTC_CNTL_DG_DCDC_WAIT_TIMER_S) +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_V 0x000001FF +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_S 16 + +/* RTC_CNTL_ANA_CONF_REG register + * configure some i2c and plla power + */ + +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x34) + +/* RTC_CNTL_PLL_I2C_PU : R/W; bitpos: [31]; default: 0; + * 1. PLL_I2C power up ,otherwise power down + */ + +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (RTC_CNTL_PLL_I2C_PU_V << RTC_CNTL_PLL_I2C_PU_S) +#define RTC_CNTL_PLL_I2C_PU_V 0x00000001 +#define RTC_CNTL_PLL_I2C_PU_S 31 + +/* RTC_CNTL_CKGEN_I2C_PU : R/W; bitpos: [30]; default: 0; + * 1: CKGEN_I2C power up , otherwise power down + */ + +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (RTC_CNTL_CKGEN_I2C_PU_V << RTC_CNTL_CKGEN_I2C_PU_S) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x00000001 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 + +/* RTC_CNTL_RFRX_PBUS_PU : R/W; bitpos: [28]; default: 0; + * 1: RFRX_PBUS power up , otherwise power down + */ + +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (RTC_CNTL_RFRX_PBUS_PU_V << RTC_CNTL_RFRX_PBUS_PU_S) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x00000001 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 + +/* RTC_CNTL_TXRF_I2C_PU : R/W; bitpos: [27]; default: 0; + * 1: TXRF_I2C power up , otherwise power down + */ + +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (RTC_CNTL_TXRF_I2C_PU_V << RTC_CNTL_TXRF_I2C_PU_S) +#define RTC_CNTL_TXRF_I2C_PU_V 0x00000001 +#define RTC_CNTL_TXRF_I2C_PU_S 27 + +/* RTC_CNTL_PVTMON_PU : R/W; bitpos: [26]; default: 0; + * 1: PVTMON power up , otherwise power down + */ + +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (RTC_CNTL_PVTMON_PU_V << RTC_CNTL_PVTMON_PU_S) +#define RTC_CNTL_PVTMON_PU_V 0x00000001 +#define RTC_CNTL_PVTMON_PU_S 26 + +/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W; bitpos: [25]; default: 0; + * start BBPLL calibration during sleep + */ + +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (RTC_CNTL_BBPLL_CAL_SLP_START_V << RTC_CNTL_BBPLL_CAL_SLP_START_S) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x00000001 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 + +/* RTC_CNTL_PLLA_FORCE_PU : R/W; bitpos: [24]; default: 0; + * PLLA force power up + */ + +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_M (RTC_CNTL_PLLA_FORCE_PU_V << RTC_CNTL_PLLA_FORCE_PU_S) +#define RTC_CNTL_PLLA_FORCE_PU_V 0x00000001 +#define RTC_CNTL_PLLA_FORCE_PU_S 24 + +/* RTC_CNTL_PLLA_FORCE_PD : R/W; bitpos: [23]; default: 1; + * PLLA force power down + */ + +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_M (RTC_CNTL_PLLA_FORCE_PD_V << RTC_CNTL_PLLA_FORCE_PD_S) +#define RTC_CNTL_PLLA_FORCE_PD_V 0x00000001 +#define RTC_CNTL_PLLA_FORCE_PD_S 23 + +/* RTC_CNTL_SAR_I2C_FORCE_PU : R/W; bitpos: [22]; default: 0; + * SAR_I2C force power up + */ + +#define RTC_CNTL_SAR_I2C_FORCE_PU (BIT(22)) +#define RTC_CNTL_SAR_I2C_FORCE_PU_M (RTC_CNTL_SAR_I2C_FORCE_PU_V << RTC_CNTL_SAR_I2C_FORCE_PU_S) +#define RTC_CNTL_SAR_I2C_FORCE_PU_V 0x00000001 +#define RTC_CNTL_SAR_I2C_FORCE_PU_S 22 + +/* RTC_CNTL_SAR_I2C_FORCE_PD : R/W; bitpos: [21]; default: 1; + * SAR_I2C force power down + */ + +#define RTC_CNTL_SAR_I2C_FORCE_PD (BIT(21)) +#define RTC_CNTL_SAR_I2C_FORCE_PD_M (RTC_CNTL_SAR_I2C_FORCE_PD_V << RTC_CNTL_SAR_I2C_FORCE_PD_S) +#define RTC_CNTL_SAR_I2C_FORCE_PD_V 0x00000001 +#define RTC_CNTL_SAR_I2C_FORCE_PD_S 21 + +/* RTC_CNTL_GLITCH_RST_EN : R/W; bitpos: [20]; default: 0; + * enable glitch reset if system detect glitch + */ + +#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_M (RTC_CNTL_GLITCH_RST_EN_V << RTC_CNTL_GLITCH_RST_EN_S) +#define RTC_CNTL_GLITCH_RST_EN_V 0x00000001 +#define RTC_CNTL_GLITCH_RST_EN_S 20 + +/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W; bitpos: [19]; default: 0; + * SLEEP_I2CPOR force pu + */ + +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (RTC_CNTL_I2C_RESET_POR_FORCE_PU_V << RTC_CNTL_I2C_RESET_POR_FORCE_PU_S) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x00000001 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 + +/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W; bitpos: [18]; default: 1; + * SLEEP_I2CPOR force pd + */ + +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (RTC_CNTL_I2C_RESET_POR_FORCE_PD_V << RTC_CNTL_I2C_RESET_POR_FORCE_PD_S) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x00000001 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 + +/* RTC_CNTL_RESET_STATE_REG register + * reset cause state register + */ + +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) + +/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W; bitpos: [13]; default: 1; + * PRO CPU state vector sel + */ + +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V << RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x00000001 +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 + +/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W; bitpos: [12]; default: 1; + * APP CPU state vector sel + */ + +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V << RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x00000001 +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 + +/* RTC_CNTL_RESET_CAUSE_APPCPU : RO; bitpos: [11:6]; default: 0; + * reset cause of APP CPU + */ + +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M (RTC_CNTL_RESET_CAUSE_APPCPU_V << RTC_CNTL_RESET_CAUSE_APPCPU_S) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 + +/* RTC_CNTL_RESET_CAUSE_PROCPU : RO; bitpos: [5:0]; default: 0; + * reset cause of PRO CPU + */ + +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M (RTC_CNTL_RESET_CAUSE_PROCPU_V << RTC_CNTL_RESET_CAUSE_PROCPU_S) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 + +/* RTC_CNTL_WAKEUP_STATE_REG register + * wakeup enable register + */ + +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x3c) + +/* RTC_CNTL_WAKEUP_ENA : R/W; bitpos: [31:15]; default: 12; + * wakeup enable bitmap + */ + +#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF +#define RTC_CNTL_WAKEUP_ENA_M (RTC_CNTL_WAKEUP_ENA_V << RTC_CNTL_WAKEUP_ENA_S) +#define RTC_CNTL_WAKEUP_ENA_V 0x0001FFFF +#define RTC_CNTL_WAKEUP_ENA_S 15 + +/* RTC_CNTL_INT_ENA_RTC_REG register + * rtc interrupt enable register + */ + +#define RTC_CNTL_INT_ENA_RTC_REG (DR_REG_RTCCNTL_BASE + 0x40) + +/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W; bitpos: [19]; default: 0; + * enbale gitch det interrupt + */ + +#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_M (RTC_CNTL_GLITCH_DET_INT_ENA_V << RTC_CNTL_GLITCH_DET_INT_ENA_S) +#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x00000001 +#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 + +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA : R/W; bitpos: [18]; default: 0; + * enable touch timeout interrupt + */ + +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M (RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V << RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V 0x00000001 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S 18 + +/* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W; bitpos: [17]; default: 0; + * enable cocpu trap interrupt + */ + +#define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_M (RTC_CNTL_COCPU_TRAP_INT_ENA_V << RTC_CNTL_COCPU_TRAP_INT_ENA_S) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_V 0x00000001 +#define RTC_CNTL_COCPU_TRAP_INT_ENA_S 17 + +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W; bitpos: [16]; default: 0; + * enable xtal32k_dead interrupt + */ + +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (RTC_CNTL_XTAL32K_DEAD_INT_ENA_V << RTC_CNTL_XTAL32K_DEAD_INT_ENA_S) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x00000001 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 + +/* RTC_CNTL_SWD_INT_ENA : R/W; bitpos: [15]; default: 0; + * enable super watch dog interrupt + */ + +#define RTC_CNTL_SWD_INT_ENA (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_M (RTC_CNTL_SWD_INT_ENA_V << RTC_CNTL_SWD_INT_ENA_S) +#define RTC_CNTL_SWD_INT_ENA_V 0x00000001 +#define RTC_CNTL_SWD_INT_ENA_S 15 + +/* RTC_CNTL_SARADC2_INT_ENA : R/W; bitpos: [14]; default: 0; + * enable saradc2 interrupt + */ + +#define RTC_CNTL_SARADC2_INT_ENA (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_M (RTC_CNTL_SARADC2_INT_ENA_V << RTC_CNTL_SARADC2_INT_ENA_S) +#define RTC_CNTL_SARADC2_INT_ENA_V 0x00000001 +#define RTC_CNTL_SARADC2_INT_ENA_S 14 + +/* RTC_CNTL_COCPU_INT_ENA : R/W; bitpos: [13]; default: 0; + * enable riscV cocpu interrupt + */ + +#define RTC_CNTL_COCPU_INT_ENA (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_M (RTC_CNTL_COCPU_INT_ENA_V << RTC_CNTL_COCPU_INT_ENA_S) +#define RTC_CNTL_COCPU_INT_ENA_V 0x00000001 +#define RTC_CNTL_COCPU_INT_ENA_S 13 + +/* RTC_CNTL_TSENS_INT_ENA : R/W; bitpos: [12]; default: 0; + * enable tsens interrupt + */ + +#define RTC_CNTL_TSENS_INT_ENA (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_M (RTC_CNTL_TSENS_INT_ENA_V << RTC_CNTL_TSENS_INT_ENA_S) +#define RTC_CNTL_TSENS_INT_ENA_V 0x00000001 +#define RTC_CNTL_TSENS_INT_ENA_S 12 + +/* RTC_CNTL_SARADC1_INT_ENA : R/W; bitpos: [11]; default: 0; + * enable saradc1 interrupt + */ + +#define RTC_CNTL_SARADC1_INT_ENA (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_M (RTC_CNTL_SARADC1_INT_ENA_V << RTC_CNTL_SARADC1_INT_ENA_S) +#define RTC_CNTL_SARADC1_INT_ENA_V 0x00000001 +#define RTC_CNTL_SARADC1_INT_ENA_S 11 + +/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W; bitpos: [10]; default: 0; + * enable RTC main timer interrupt + */ + +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (RTC_CNTL_MAIN_TIMER_INT_ENA_V << RTC_CNTL_MAIN_TIMER_INT_ENA_S) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x00000001 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 + +/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W; bitpos: [9]; default: 0; + * enable brown out interrupt + */ + +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (RTC_CNTL_BROWN_OUT_INT_ENA_V << RTC_CNTL_BROWN_OUT_INT_ENA_S) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 + +/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA : R/W; bitpos: [8]; default: 0; + * enable touch inactive interrupt + */ + +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M (RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V << RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V 0x00000001 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S 8 + +/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W; bitpos: [7]; default: 0; + * enable touch active interrupt + */ + +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M (RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V << RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V 0x00000001 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S 7 + +/* RTC_CNTL_TOUCH_DONE_INT_ENA : R/W; bitpos: [6]; default: 0; + * enable touch done interrupt + */ + +#define RTC_CNTL_TOUCH_DONE_INT_ENA (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_M (RTC_CNTL_TOUCH_DONE_INT_ENA_V << RTC_CNTL_TOUCH_DONE_INT_ENA_S) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_V 0x00000001 +#define RTC_CNTL_TOUCH_DONE_INT_ENA_S 6 + +/* RTC_CNTL_ULP_CP_INT_ENA : R/W; bitpos: [5]; default: 0; + * enable ULP-coprocessor interrupt + */ + +#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_M (RTC_CNTL_ULP_CP_INT_ENA_V << RTC_CNTL_ULP_CP_INT_ENA_S) +#define RTC_CNTL_ULP_CP_INT_ENA_V 0x00000001 +#define RTC_CNTL_ULP_CP_INT_ENA_S 5 + +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * enable touch scan done interrupt + */ + +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M (RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V << RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V 0x00000001 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S 4 + +/* RTC_CNTL_WDT_INT_ENA : R/W; bitpos: [3]; default: 0; + * enable RTC WDT interrupt + */ + +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (RTC_CNTL_WDT_INT_ENA_V << RTC_CNTL_WDT_INT_ENA_S) +#define RTC_CNTL_WDT_INT_ENA_V 0x00000001 +#define RTC_CNTL_WDT_INT_ENA_S 3 + +/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W; bitpos: [2]; default: 0; + * enable SDIO idle interrupt + */ + +#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (RTC_CNTL_SDIO_IDLE_INT_ENA_V << RTC_CNTL_SDIO_IDLE_INT_ENA_S) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x00000001 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 + +/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W; bitpos: [1]; default: 0; + * enable sleep reject interrupt + */ + +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (RTC_CNTL_SLP_REJECT_INT_ENA_V << RTC_CNTL_SLP_REJECT_INT_ENA_S) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x00000001 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 + +/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W; bitpos: [0]; default: 0; + * enable sleep wakeup interrupt + */ + +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (RTC_CNTL_SLP_WAKEUP_INT_ENA_V << RTC_CNTL_SLP_WAKEUP_INT_ENA_S) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x00000001 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 + +/* RTC_CNTL_INT_RAW_RTC_REG register + * rtc_interrupt raw register + */ + +#define RTC_CNTL_INT_RAW_RTC_REG (DR_REG_RTCCNTL_BASE + 0x44) + +/* RTC_CNTL_GLITCH_DET_INT_RAW : RO; bitpos: [19]; default: 0; + * glitch_det_interrupt_raw + */ + +#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_M (RTC_CNTL_GLITCH_DET_INT_RAW_V << RTC_CNTL_GLITCH_DET_INT_RAW_S) +#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x00000001 +#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 + +/* RTC_CNTL_TOUCH_TIMEOUT_INT_RAW : RO; bitpos: [18]; default: 0; + * touch timeout interrupt raw + */ + +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M (RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V << RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V 0x00000001 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S 18 + +/* RTC_CNTL_COCPU_TRAP_INT_RAW : RO; bitpos: [17]; default: 0; + * cocpu trap interrupt raw + */ + +#define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_RAW_M (RTC_CNTL_COCPU_TRAP_INT_RAW_V << RTC_CNTL_COCPU_TRAP_INT_RAW_S) +#define RTC_CNTL_COCPU_TRAP_INT_RAW_V 0x00000001 +#define RTC_CNTL_COCPU_TRAP_INT_RAW_S 17 + +/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO; bitpos: [16]; default: 0; + * xtal32k dead detection interrupt raw + */ + +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (RTC_CNTL_XTAL32K_DEAD_INT_RAW_V << RTC_CNTL_XTAL32K_DEAD_INT_RAW_S) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x00000001 +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 + +/* RTC_CNTL_SWD_INT_RAW : RO; bitpos: [15]; default: 0; + * super watch dog interrupt raw + */ + +#define RTC_CNTL_SWD_INT_RAW (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_M (RTC_CNTL_SWD_INT_RAW_V << RTC_CNTL_SWD_INT_RAW_S) +#define RTC_CNTL_SWD_INT_RAW_V 0x00000001 +#define RTC_CNTL_SWD_INT_RAW_S 15 + +/* RTC_CNTL_SARADC2_INT_RAW : RO; bitpos: [14]; default: 0; + * saradc2 interrupt raw + */ + +#define RTC_CNTL_SARADC2_INT_RAW (BIT(14)) +#define RTC_CNTL_SARADC2_INT_RAW_M (RTC_CNTL_SARADC2_INT_RAW_V << RTC_CNTL_SARADC2_INT_RAW_S) +#define RTC_CNTL_SARADC2_INT_RAW_V 0x00000001 +#define RTC_CNTL_SARADC2_INT_RAW_S 14 + +/* RTC_CNTL_COCPU_INT_RAW : RO; bitpos: [13]; default: 0; + * riscV cocpu interrupt raw + */ + +#define RTC_CNTL_COCPU_INT_RAW (BIT(13)) +#define RTC_CNTL_COCPU_INT_RAW_M (RTC_CNTL_COCPU_INT_RAW_V << RTC_CNTL_COCPU_INT_RAW_S) +#define RTC_CNTL_COCPU_INT_RAW_V 0x00000001 +#define RTC_CNTL_COCPU_INT_RAW_S 13 + +/* RTC_CNTL_TSENS_INT_RAW : RO; bitpos: [12]; default: 0; + * tsens interrupt raw + */ + +#define RTC_CNTL_TSENS_INT_RAW (BIT(12)) +#define RTC_CNTL_TSENS_INT_RAW_M (RTC_CNTL_TSENS_INT_RAW_V << RTC_CNTL_TSENS_INT_RAW_S) +#define RTC_CNTL_TSENS_INT_RAW_V 0x00000001 +#define RTC_CNTL_TSENS_INT_RAW_S 12 + +/* RTC_CNTL_SARADC1_INT_RAW : RO; bitpos: [11]; default: 0; + * saradc1 interrupt raw + */ + +#define RTC_CNTL_SARADC1_INT_RAW (BIT(11)) +#define RTC_CNTL_SARADC1_INT_RAW_M (RTC_CNTL_SARADC1_INT_RAW_V << RTC_CNTL_SARADC1_INT_RAW_S) +#define RTC_CNTL_SARADC1_INT_RAW_V 0x00000001 +#define RTC_CNTL_SARADC1_INT_RAW_S 11 + +/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO; bitpos: [10]; default: 0; + * RTC main timer interrupt raw + */ + +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (RTC_CNTL_MAIN_TIMER_INT_RAW_V << RTC_CNTL_MAIN_TIMER_INT_RAW_S) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x00000001 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 + +/* RTC_CNTL_BROWN_OUT_INT_RAW : RO; bitpos: [9]; default: 0; + * brown out interrupt raw + */ + +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (RTC_CNTL_BROWN_OUT_INT_RAW_V << RTC_CNTL_BROWN_OUT_INT_RAW_S) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 + +/* RTC_CNTL_TOUCH_INACTIVE_INT_RAW : RO; bitpos: [8]; default: 0; + * touch inactive interrupt raw + */ + +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M (RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V << RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S) +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V 0x00000001 +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S 8 + +/* RTC_CNTL_TOUCH_ACTIVE_INT_RAW : RO; bitpos: [7]; default: 0; + * touch active interrupt raw + */ + +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M (RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V << RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S) +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V 0x00000001 +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S 7 + +/* RTC_CNTL_TOUCH_DONE_INT_RAW : RO; bitpos: [6]; default: 0; + * touch interrupt raw + */ + +#define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_RAW_M (RTC_CNTL_TOUCH_DONE_INT_RAW_V << RTC_CNTL_TOUCH_DONE_INT_RAW_S) +#define RTC_CNTL_TOUCH_DONE_INT_RAW_V 0x00000001 +#define RTC_CNTL_TOUCH_DONE_INT_RAW_S 6 + +/* RTC_CNTL_ULP_CP_INT_RAW : RO; bitpos: [5]; default: 0; + * ULP-coprocessor interrupt raw + */ + +#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_M (RTC_CNTL_ULP_CP_INT_RAW_V << RTC_CNTL_ULP_CP_INT_RAW_S) +#define RTC_CNTL_ULP_CP_INT_RAW_V 0x00000001 +#define RTC_CNTL_ULP_CP_INT_RAW_S 5 + +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW : RO; bitpos: [4]; default: 0; + * touch complete a loop interrupt raw + */ + +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M (RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V << RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V 0x00000001 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S 4 + +/* RTC_CNTL_WDT_INT_RAW : RO; bitpos: [3]; default: 0; + * RTC WDT interrupt raw + */ + +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (RTC_CNTL_WDT_INT_RAW_V << RTC_CNTL_WDT_INT_RAW_S) +#define RTC_CNTL_WDT_INT_RAW_V 0x00000001 +#define RTC_CNTL_WDT_INT_RAW_S 3 + +/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO; bitpos: [2]; default: 0; + * SDIO idle interrupt raw + */ + +#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (RTC_CNTL_SDIO_IDLE_INT_RAW_V << RTC_CNTL_SDIO_IDLE_INT_RAW_S) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x00000001 +#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 + +/* RTC_CNTL_SLP_REJECT_INT_RAW : RO; bitpos: [1]; default: 0; + * sleep reject interrupt raw + */ + +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (RTC_CNTL_SLP_REJECT_INT_RAW_V << RTC_CNTL_SLP_REJECT_INT_RAW_S) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x00000001 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 + +/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO; bitpos: [0]; default: 0; + * sleep wakeup interrupt raw + */ + +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (RTC_CNTL_SLP_WAKEUP_INT_RAW_V << RTC_CNTL_SLP_WAKEUP_INT_RAW_S) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x00000001 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 + +/* RTC_CNTL_INT_ST_RTC_REG register + * rtc_interrupt state register + */ + +#define RTC_CNTL_INT_ST_RTC_REG (DR_REG_RTCCNTL_BASE + 0x48) + +/* RTC_CNTL_GLITCH_DET_INT_ST : RO; bitpos: [19]; default: 0; + * glitch_det_interrupt state + */ + +#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_M (RTC_CNTL_GLITCH_DET_INT_ST_V << RTC_CNTL_GLITCH_DET_INT_ST_S) +#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x00000001 +#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 + +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO; bitpos: [18]; default: 0; + * Touch timeout interrupt state + */ + +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M (RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V << RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V 0x00000001 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S 18 + +/* RTC_CNTL_COCPU_TRAP_INT_ST : RO; bitpos: [17]; default: 0; + * cocpu trap interrupt state + */ + +#define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ST_M (RTC_CNTL_COCPU_TRAP_INT_ST_V << RTC_CNTL_COCPU_TRAP_INT_ST_S) +#define RTC_CNTL_COCPU_TRAP_INT_ST_V 0x00000001 +#define RTC_CNTL_COCPU_TRAP_INT_ST_S 17 + +/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO; bitpos: [16]; default: 0; + * xtal32k dead detection interrupt state + */ + +#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (RTC_CNTL_XTAL32K_DEAD_INT_ST_V << RTC_CNTL_XTAL32K_DEAD_INT_ST_S) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x00000001 +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 + +/* RTC_CNTL_SWD_INT_ST : RO; bitpos: [15]; default: 0; + * super watch dog interrupt state + */ + +#define RTC_CNTL_SWD_INT_ST (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_M (RTC_CNTL_SWD_INT_ST_V << RTC_CNTL_SWD_INT_ST_S) +#define RTC_CNTL_SWD_INT_ST_V 0x00000001 +#define RTC_CNTL_SWD_INT_ST_S 15 + +/* RTC_CNTL_SARADC2_INT_ST : RO; bitpos: [14]; default: 0; + * saradc2 interrupt state + */ + +#define RTC_CNTL_SARADC2_INT_ST (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ST_M (RTC_CNTL_SARADC2_INT_ST_V << RTC_CNTL_SARADC2_INT_ST_S) +#define RTC_CNTL_SARADC2_INT_ST_V 0x00000001 +#define RTC_CNTL_SARADC2_INT_ST_S 14 + +/* RTC_CNTL_COCPU_INT_ST : RO; bitpos: [13]; default: 0; + * riscV cocpu interrupt state + */ + +#define RTC_CNTL_COCPU_INT_ST (BIT(13)) +#define RTC_CNTL_COCPU_INT_ST_M (RTC_CNTL_COCPU_INT_ST_V << RTC_CNTL_COCPU_INT_ST_S) +#define RTC_CNTL_COCPU_INT_ST_V 0x00000001 +#define RTC_CNTL_COCPU_INT_ST_S 13 + +/* RTC_CNTL_TSENS_INT_ST : RO; bitpos: [12]; default: 0; + * tsens interrupt state + */ + +#define RTC_CNTL_TSENS_INT_ST (BIT(12)) +#define RTC_CNTL_TSENS_INT_ST_M (RTC_CNTL_TSENS_INT_ST_V << RTC_CNTL_TSENS_INT_ST_S) +#define RTC_CNTL_TSENS_INT_ST_V 0x00000001 +#define RTC_CNTL_TSENS_INT_ST_S 12 + +/* RTC_CNTL_SARADC1_INT_ST : RO; bitpos: [11]; default: 0; + * saradc1 interrupt state + */ + +#define RTC_CNTL_SARADC1_INT_ST (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ST_M (RTC_CNTL_SARADC1_INT_ST_V << RTC_CNTL_SARADC1_INT_ST_S) +#define RTC_CNTL_SARADC1_INT_ST_V 0x00000001 +#define RTC_CNTL_SARADC1_INT_ST_S 11 + +/* RTC_CNTL_MAIN_TIMER_INT_ST : RO; bitpos: [10]; default: 0; + * RTC main timer interrupt state + */ + +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (RTC_CNTL_MAIN_TIMER_INT_ST_V << RTC_CNTL_MAIN_TIMER_INT_ST_S) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x00000001 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 + +/* RTC_CNTL_BROWN_OUT_INT_ST : RO; bitpos: [9]; default: 0; + * brown out interrupt state + */ + +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (RTC_CNTL_BROWN_OUT_INT_ST_V << RTC_CNTL_BROWN_OUT_INT_ST_S) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 9 + +/* RTC_CNTL_TOUCH_INACTIVE_INT_ST : RO; bitpos: [8]; default: 0; + * touch inactive interrupt state + */ + +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M (RTC_CNTL_TOUCH_INACTIVE_INT_ST_V << RTC_CNTL_TOUCH_INACTIVE_INT_ST_S) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V 0x00000001 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S 8 + +/* RTC_CNTL_TOUCH_ACTIVE_INT_ST : RO; bitpos: [7]; default: 0; + * touch active interrupt state + */ + +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M (RTC_CNTL_TOUCH_ACTIVE_INT_ST_V << RTC_CNTL_TOUCH_ACTIVE_INT_ST_S) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V 0x00000001 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S 7 + +/* RTC_CNTL_TOUCH_DONE_INT_ST : RO; bitpos: [6]; default: 0; + * touch done interrupt state + */ + +#define RTC_CNTL_TOUCH_DONE_INT_ST (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ST_M (RTC_CNTL_TOUCH_DONE_INT_ST_V << RTC_CNTL_TOUCH_DONE_INT_ST_S) +#define RTC_CNTL_TOUCH_DONE_INT_ST_V 0x00000001 +#define RTC_CNTL_TOUCH_DONE_INT_ST_S 6 + +/* RTC_CNTL_ULP_CP_INT_ST : RO; bitpos: [5]; default: 0; + * ULP-coprocessor interrupt state + */ + +#define RTC_CNTL_ULP_CP_INT_ST (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ST_M (RTC_CNTL_ULP_CP_INT_ST_V << RTC_CNTL_ULP_CP_INT_ST_S) +#define RTC_CNTL_ULP_CP_INT_ST_V 0x00000001 +#define RTC_CNTL_ULP_CP_INT_ST_S 5 + +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * touch complete a loop interrupt state + */ + +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M (RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V << RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V 0x00000001 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S 4 + +/* RTC_CNTL_WDT_INT_ST : RO; bitpos: [3]; default: 0; + * RTC WDT interrupt state + */ + +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (RTC_CNTL_WDT_INT_ST_V << RTC_CNTL_WDT_INT_ST_S) +#define RTC_CNTL_WDT_INT_ST_V 0x00000001 +#define RTC_CNTL_WDT_INT_ST_S 3 + +/* RTC_CNTL_SDIO_IDLE_INT_ST : RO; bitpos: [2]; default: 0; + * SDIO idle interrupt state + */ + +#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_M (RTC_CNTL_SDIO_IDLE_INT_ST_V << RTC_CNTL_SDIO_IDLE_INT_ST_S) +#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x00000001 +#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 + +/* RTC_CNTL_SLP_REJECT_INT_ST : RO; bitpos: [1]; default: 0; + * sleep reject interrupt state + */ + +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (RTC_CNTL_SLP_REJECT_INT_ST_V << RTC_CNTL_SLP_REJECT_INT_ST_S) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x00000001 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 + +/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO; bitpos: [0]; default: 0; + * sleep wakeup interrupt state + */ + +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (RTC_CNTL_SLP_WAKEUP_INT_ST_V << RTC_CNTL_SLP_WAKEUP_INT_ST_S) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x00000001 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 + +/* RTC_CNTL_INT_CLR_RTC_REG register + * Clear rtc_interrupt register + */ + +#define RTC_CNTL_INT_CLR_RTC_REG (DR_REG_RTCCNTL_BASE + 0x4c) + +/* RTC_CNTL_GLITCH_DET_INT_CLR : WO; bitpos: [19]; default: 0; + * Clear glitch det interrupt state + */ + +#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_M (RTC_CNTL_GLITCH_DET_INT_CLR_V << RTC_CNTL_GLITCH_DET_INT_CLR_S) +#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x00000001 +#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 + +/* RTC_CNTL_TOUCH_TIMEOUT_INT_CLR : WO; bitpos: [18]; default: 0; + * Clear touch timeout interrupt state + */ + +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M (RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V << RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V 0x00000001 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S 18 + +/* RTC_CNTL_COCPU_TRAP_INT_CLR : WO; bitpos: [17]; default: 0; + * Clear cocpu trap interrupt state + */ + +#define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_CLR_M (RTC_CNTL_COCPU_TRAP_INT_CLR_V << RTC_CNTL_COCPU_TRAP_INT_CLR_S) +#define RTC_CNTL_COCPU_TRAP_INT_CLR_V 0x00000001 +#define RTC_CNTL_COCPU_TRAP_INT_CLR_S 17 + +/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO; bitpos: [16]; default: 0; + * Clear RTC WDT interrupt state + */ + +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (RTC_CNTL_XTAL32K_DEAD_INT_CLR_V << RTC_CNTL_XTAL32K_DEAD_INT_CLR_S) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x00000001 +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 + +/* RTC_CNTL_SWD_INT_CLR : WO; bitpos: [15]; default: 0; + * Clear super watch dog interrupt state + */ + +#define RTC_CNTL_SWD_INT_CLR (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_M (RTC_CNTL_SWD_INT_CLR_V << RTC_CNTL_SWD_INT_CLR_S) +#define RTC_CNTL_SWD_INT_CLR_V 0x00000001 +#define RTC_CNTL_SWD_INT_CLR_S 15 + +/* RTC_CNTL_SARADC2_INT_CLR : WO; bitpos: [14]; default: 0; + * Clear saradc2 interrupt state + */ + +#define RTC_CNTL_SARADC2_INT_CLR (BIT(14)) +#define RTC_CNTL_SARADC2_INT_CLR_M (RTC_CNTL_SARADC2_INT_CLR_V << RTC_CNTL_SARADC2_INT_CLR_S) +#define RTC_CNTL_SARADC2_INT_CLR_V 0x00000001 +#define RTC_CNTL_SARADC2_INT_CLR_S 14 + +/* RTC_CNTL_COCPU_INT_CLR : WO; bitpos: [13]; default: 0; + * Clear riscV cocpu interrupt state + */ + +#define RTC_CNTL_COCPU_INT_CLR (BIT(13)) +#define RTC_CNTL_COCPU_INT_CLR_M (RTC_CNTL_COCPU_INT_CLR_V << RTC_CNTL_COCPU_INT_CLR_S) +#define RTC_CNTL_COCPU_INT_CLR_V 0x00000001 +#define RTC_CNTL_COCPU_INT_CLR_S 13 + +/* RTC_CNTL_TSENS_INT_CLR : WO; bitpos: [12]; default: 0; + * Clear tsens interrupt state + */ + +#define RTC_CNTL_TSENS_INT_CLR (BIT(12)) +#define RTC_CNTL_TSENS_INT_CLR_M (RTC_CNTL_TSENS_INT_CLR_V << RTC_CNTL_TSENS_INT_CLR_S) +#define RTC_CNTL_TSENS_INT_CLR_V 0x00000001 +#define RTC_CNTL_TSENS_INT_CLR_S 12 + +/* RTC_CNTL_SARADC1_INT_CLR : WO; bitpos: [11]; default: 0; + * Clear saradc1 interrupt state + */ + +#define RTC_CNTL_SARADC1_INT_CLR (BIT(11)) +#define RTC_CNTL_SARADC1_INT_CLR_M (RTC_CNTL_SARADC1_INT_CLR_V << RTC_CNTL_SARADC1_INT_CLR_S) +#define RTC_CNTL_SARADC1_INT_CLR_V 0x00000001 +#define RTC_CNTL_SARADC1_INT_CLR_S 11 + +/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO; bitpos: [10]; default: 0; + * Clear RTC main timer interrupt state + */ + +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (RTC_CNTL_MAIN_TIMER_INT_CLR_V << RTC_CNTL_MAIN_TIMER_INT_CLR_S) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x00000001 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 + +/* RTC_CNTL_BROWN_OUT_INT_CLR : WO; bitpos: [9]; default: 0; + * Clear brown out interrupt state + */ + +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (RTC_CNTL_BROWN_OUT_INT_CLR_V << RTC_CNTL_BROWN_OUT_INT_CLR_S) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 + +/* RTC_CNTL_TOUCH_INACTIVE_INT_CLR : WO; bitpos: [8]; default: 0; + * Clear touch inactive interrupt state + */ + +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M (RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V << RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S) +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V 0x00000001 +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S 8 + +/* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO; bitpos: [7]; default: 0; + * Clear touch active interrupt state + */ + +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M (RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V << RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S) +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V 0x00000001 +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S 7 + +/* RTC_CNTL_TOUCH_DONE_INT_CLR : WO; bitpos: [6]; default: 0; + * Clear touch done interrupt state + */ + +#define RTC_CNTL_TOUCH_DONE_INT_CLR (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_CLR_M (RTC_CNTL_TOUCH_DONE_INT_CLR_V << RTC_CNTL_TOUCH_DONE_INT_CLR_S) +#define RTC_CNTL_TOUCH_DONE_INT_CLR_V 0x00000001 +#define RTC_CNTL_TOUCH_DONE_INT_CLR_S 6 + +/* RTC_CNTL_ULP_CP_INT_CLR : WO; bitpos: [5]; default: 0; + * Clear ULP-coprocessor interrupt state + */ + +#define RTC_CNTL_ULP_CP_INT_CLR (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_CLR_M (RTC_CNTL_ULP_CP_INT_CLR_V << RTC_CNTL_ULP_CP_INT_CLR_S) +#define RTC_CNTL_ULP_CP_INT_CLR_V 0x00000001 +#define RTC_CNTL_ULP_CP_INT_CLR_S 5 + +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR : WO; bitpos: [4]; default: 0; + * Clear touch complete a loop interrupt state + */ + +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M (RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V << RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V 0x00000001 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S 4 + +/* RTC_CNTL_WDT_INT_CLR : WO; bitpos: [3]; default: 0; + * Clear RTC WDT interrupt state + */ + +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (RTC_CNTL_WDT_INT_CLR_V << RTC_CNTL_WDT_INT_CLR_S) +#define RTC_CNTL_WDT_INT_CLR_V 0x00000001 +#define RTC_CNTL_WDT_INT_CLR_S 3 + +/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO; bitpos: [2]; default: 0; + * Clear SDIO idle interrupt state + */ + +#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (RTC_CNTL_SDIO_IDLE_INT_CLR_V << RTC_CNTL_SDIO_IDLE_INT_CLR_S) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x00000001 +#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 + +/* RTC_CNTL_SLP_REJECT_INT_CLR : WO; bitpos: [1]; default: 0; + * Clear sleep reject interrupt state + */ + +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (RTC_CNTL_SLP_REJECT_INT_CLR_V << RTC_CNTL_SLP_REJECT_INT_CLR_S) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x00000001 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 + +/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO; bitpos: [0]; default: 0; + * Clear sleep wakeup interrupt state + */ + +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (RTC_CNTL_SLP_WAKEUP_INT_CLR_V << RTC_CNTL_SLP_WAKEUP_INT_CLR_S) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x00000001 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 + +/* RTC_CNTL_STORE0_REG register + * reservation register0 + */ + +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x50) + +/* RTC_CNTL_SCRATCH0 : R/W; bitpos: [31:0]; default: 0; + * reservation register0 + */ + +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M (RTC_CNTL_SCRATCH0_V << RTC_CNTL_SCRATCH0_S) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 + +/* RTC_CNTL_STORE1_REG register + * reservation register1 + */ + +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x54) + +#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG + +/* RTC_CNTL_SCRATCH1 : R/W; bitpos: [31:0]; default: 0; + * reservation register1 + */ + +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M (RTC_CNTL_SCRATCH1_V << RTC_CNTL_SCRATCH1_S) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 + +/* RTC_CNTL_STORE2_REG register + * reservation register2 + */ + +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x58) + +/* RTC_CNTL_SCRATCH2 : R/W; bitpos: [31:0]; default: 0; + * reservation register2 + */ + +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M (RTC_CNTL_SCRATCH2_V << RTC_CNTL_SCRATCH2_S) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 + +/* RTC_CNTL_STORE3_REG register + * reservation register3 + */ + +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x5c) + +/* RTC_CNTL_SCRATCH3 : R/W; bitpos: [31:0]; default: 0; + * reservation register3 + */ + +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M (RTC_CNTL_SCRATCH3_V << RTC_CNTL_SCRATCH3_S) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 + +/* RTC_CNTL_EXT_XTL_CONF_REG register + * configure 32k xtal register + */ + +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) + +/* RTC_CNTL_XTL_EXT_CTR_EN : R/W; bitpos: [31]; default: 0; + * enable gpio power down XTAL + */ + +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (RTC_CNTL_XTL_EXT_CTR_EN_V << RTC_CNTL_XTL_EXT_CTR_EN_S) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x00000001 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 + +/* RTC_CNTL_XTL_EXT_CTR_LV : R/W; bitpos: [30]; default: 0; + * 0: power down XTAL at high level 1: power down XTAL at low level + */ + +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (RTC_CNTL_XTL_EXT_CTR_LV_V << RTC_CNTL_XTL_EXT_CTR_LV_S) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x00000001 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 + +/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W; bitpos: [23]; default: 0; + * XTAL_32K sel. 0: external XTAL_32K 1: CLK from RTC pad X32P_C + */ + +#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_M (RTC_CNTL_XTAL32K_GPIO_SEL_V << RTC_CNTL_XTAL32K_GPIO_SEL_S) +#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x00000001 +#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 + +/* RTC_CNTL_WDT_STATE : RO; bitpos: [22:20]; default: 0; + * state of 32k_wdt + */ + +#define RTC_CNTL_WDT_STATE 0x00000007 +#define RTC_CNTL_WDT_STATE_M (RTC_CNTL_WDT_STATE_V << RTC_CNTL_WDT_STATE_S) +#define RTC_CNTL_WDT_STATE_V 0x00000007 +#define RTC_CNTL_WDT_STATE_S 20 + +/* RTC_CNTL_DAC_XTAL_32K : R/W; bitpos: [19:17]; default: 3; + * DAC_XTAL_32K + */ + +#define RTC_CNTL_DAC_XTAL_32K 0x00000007 +#define RTC_CNTL_DAC_XTAL_32K_M (RTC_CNTL_DAC_XTAL_32K_V << RTC_CNTL_DAC_XTAL_32K_S) +#define RTC_CNTL_DAC_XTAL_32K_V 0x00000007 +#define RTC_CNTL_DAC_XTAL_32K_S 17 + +/* RTC_CNTL_XPD_XTAL_32K : R/W; bitpos: [16]; default: 0; + * XPD_XTAL_32K + */ + +#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_M (RTC_CNTL_XPD_XTAL_32K_V << RTC_CNTL_XPD_XTAL_32K_S) +#define RTC_CNTL_XPD_XTAL_32K_V 0x00000001 +#define RTC_CNTL_XPD_XTAL_32K_S 16 + +/* RTC_CNTL_DRES_XTAL_32K : R/W; bitpos: [15:13]; default: 3; + * DRES_XTAL_32K + */ + +#define RTC_CNTL_DRES_XTAL_32K 0x00000007 +#define RTC_CNTL_DRES_XTAL_32K_M (RTC_CNTL_DRES_XTAL_32K_V << RTC_CNTL_DRES_XTAL_32K_S) +#define RTC_CNTL_DRES_XTAL_32K_V 0x00000007 +#define RTC_CNTL_DRES_XTAL_32K_S 13 + +/* RTC_CNTL_DGM_XTAL_32K : R/W; bitpos: [12:10]; default: 3; + * xtal_32k gm control + */ + +#define RTC_CNTL_DGM_XTAL_32K 0x00000007 +#define RTC_CNTL_DGM_XTAL_32K_M (RTC_CNTL_DGM_XTAL_32K_V << RTC_CNTL_DGM_XTAL_32K_S) +#define RTC_CNTL_DGM_XTAL_32K_V 0x00000007 +#define RTC_CNTL_DGM_XTAL_32K_S 10 + +/* RTC_CNTL_DBUF_XTAL_32K : R/W; bitpos: [9]; default: 0; + * 0: single-end buffer 1: differential buffer + */ + +#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_M (RTC_CNTL_DBUF_XTAL_32K_V << RTC_CNTL_DBUF_XTAL_32K_S) +#define RTC_CNTL_DBUF_XTAL_32K_V 0x00000001 +#define RTC_CNTL_DBUF_XTAL_32K_S 9 + +/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W; bitpos: [8]; default: 0; + * apply an internal clock to help xtal 32k to start + */ + +#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_M (RTC_CNTL_ENCKINIT_XTAL_32K_V << RTC_CNTL_ENCKINIT_XTAL_32K_S) +#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x00000001 +#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 + +/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W; bitpos: [7]; default: 1; + * Xtal 32k xpd control by sw or fsm + */ + +#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_M (RTC_CNTL_XTAL32K_XPD_FORCE_V << RTC_CNTL_XTAL32K_XPD_FORCE_S) +#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x00000001 +#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 + +/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W; bitpos: [6]; default: 0; + * xtal 32k switch back xtal when xtal is restarted + */ + +#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (RTC_CNTL_XTAL32K_AUTO_RETURN_V << RTC_CNTL_XTAL32K_AUTO_RETURN_S) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x00000001 +#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 + +/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W; bitpos: [5]; default: 0; + * xtal 32k restart xtal when xtal is dead + */ + +#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (RTC_CNTL_XTAL32K_AUTO_RESTART_V << RTC_CNTL_XTAL32K_AUTO_RESTART_S) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x00000001 +#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 + +/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W; bitpos: [4]; default: 0; + * xtal 32k switch to back up clock when xtal is dead + */ + +#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (RTC_CNTL_XTAL32K_AUTO_BACKUP_V << RTC_CNTL_XTAL32K_AUTO_BACKUP_S) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x00000001 +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 + +/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W; bitpos: [3]; default: 0; + * xtal 32k external xtal clock force on + */ + +#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (RTC_CNTL_XTAL32K_EXT_CLK_FO_V << RTC_CNTL_XTAL32K_EXT_CLK_FO_S) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x00000001 +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 + +/* RTC_CNTL_XTAL32K_WDT_RESET : R/W; bitpos: [2]; default: 0; + * xtal 32k watch dog sw reset + */ + +#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_M (RTC_CNTL_XTAL32K_WDT_RESET_V << RTC_CNTL_XTAL32K_WDT_RESET_S) +#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x00000001 +#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 + +/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W; bitpos: [1]; default: 0; + * xtal 32k watch dog clock force on + */ + +#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (RTC_CNTL_XTAL32K_WDT_CLK_FO_V << RTC_CNTL_XTAL32K_WDT_CLK_FO_S) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x00000001 +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 + +/* RTC_CNTL_XTAL32K_WDT_EN : R/W; bitpos: [0]; default: 0; + * xtal 32k watch dog enable + */ + +#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_M (RTC_CNTL_XTAL32K_WDT_EN_V << RTC_CNTL_XTAL32K_WDT_EN_S) +#define RTC_CNTL_XTAL32K_WDT_EN_V 0x00000001 +#define RTC_CNTL_XTAL32K_WDT_EN_S 0 + +/* RTC_CNTL_EXT_WAKEUP_CONF_REG register + * configure gpio wakeup register + */ + +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) + +/* RTC_CNTL_EXT_WAKEUP1_LV : R/W; bitpos: [31]; default: 0; + * 0: external wakeup at low level 1: external wakeup at high level + */ + +#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_M (RTC_CNTL_EXT_WAKEUP1_LV_V << RTC_CNTL_EXT_WAKEUP1_LV_S) +#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x00000001 +#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 + +/* RTC_CNTL_EXT_WAKEUP0_LV : R/W; bitpos: [30]; default: 0; + * 0: external wakeup at low level 1: external wakeup at high level + */ + +#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_M (RTC_CNTL_EXT_WAKEUP0_LV_V << RTC_CNTL_EXT_WAKEUP0_LV_S) +#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x00000001 +#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 + +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W; bitpos: [29]; default: 0; + * enable filter for gpio wakeup event + */ + +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (RTC_CNTL_GPIO_WAKEUP_FILTER_V << RTC_CNTL_GPIO_WAKEUP_FILTER_S) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x00000001 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29 + +/* RTC_CNTL_SLP_REJECT_CONF_REG register + * configure sleep reject register + */ + +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) + +/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; + * enable reject for deep sleep + */ + +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (RTC_CNTL_DEEP_SLP_REJECT_EN_V << RTC_CNTL_DEEP_SLP_REJECT_EN_S) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x00000001 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 + +/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W; bitpos: [30]; default: 0; + * enable reject for light sleep + */ + +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (RTC_CNTL_LIGHT_SLP_REJECT_EN_V << RTC_CNTL_LIGHT_SLP_REJECT_EN_S) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x00000001 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 + +/* RTC_CNTL_SLEEP_REJECT_ENA : R/W; bitpos: [29:13]; default: 0; + * sleep reject enable + */ + +#define RTC_CNTL_SLEEP_REJECT_ENA 0x0001FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_M (RTC_CNTL_SLEEP_REJECT_ENA_V << RTC_CNTL_SLEEP_REJECT_ENA_S) +#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x0001FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_S 13 + +/* RTC_CNTL_CPU_PERIOD_CONF_REG register + * CPU sel option + */ + +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) + +/* RTC_CNTL_CPUPERIOD_SEL : R/W; bitpos: [31:30]; default: 0; */ + +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M (RTC_CNTL_CPUPERIOD_SEL_V << RTC_CNTL_CPUPERIOD_SEL_S) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 + +/* RTC_CNTL_CPUSEL_CONF : R/W; bitpos: [29]; default: 0; + * CPU sel option + */ + +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (RTC_CNTL_CPUSEL_CONF_V << RTC_CNTL_CPUSEL_CONF_S) +#define RTC_CNTL_CPUSEL_CONF_V 0x00000001 +#define RTC_CNTL_CPUSEL_CONF_S 29 + +/* RTC_CNTL_SDIO_ACT_CONF_REG register + * configure sdio active register + */ + +#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) + +/* RTC_CNTL_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 0; + * configure sdio act dnum + */ + +#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF +#define RTC_CNTL_SDIO_ACT_DNUM_M (RTC_CNTL_SDIO_ACT_DNUM_V << RTC_CNTL_SDIO_ACT_DNUM_S) +#define RTC_CNTL_SDIO_ACT_DNUM_V 0x000003FF +#define RTC_CNTL_SDIO_ACT_DNUM_S 22 + +/* RTC_CNTL_CLK_CONF_REG register + * configure rtc clk register + */ + +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) + +/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W; bitpos: [31:30]; default: 0; + * slow clk sel 0 : 90K rtc_clk 1 : 32k XTAL 2 : 8md256 + */ + +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M (RTC_CNTL_ANA_CLK_RTC_SEL_V << RTC_CNTL_ANA_CLK_RTC_SEL_S) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 + +/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W; bitpos: [29]; default: 0; + * fast_clk_rtc sel. 0: XTAL div 4 1: CK8M + */ + +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (RTC_CNTL_FAST_CLK_RTC_SEL_V << RTC_CNTL_FAST_CLK_RTC_SEL_S) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x00000001 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 + +/* RTC_CNTL_CK8M_FORCE_PU : R/W; bitpos: [26]; default: 0; + * CK8M force power up + */ + +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (RTC_CNTL_CK8M_FORCE_PU_V << RTC_CNTL_CK8M_FORCE_PU_S) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x00000001 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 + +/* RTC_CNTL_CK8M_FORCE_PD : R/W; bitpos: [25]; default: 0; + * CK8M force power down + */ + +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (RTC_CNTL_CK8M_FORCE_PD_V << RTC_CNTL_CK8M_FORCE_PD_S) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x00000001 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 + +/* RTC_CNTL_CK8M_DFREQ : R/W; bitpos: [24:17]; default: 172; + * CK8M_DFREQ + */ + +#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_M (RTC_CNTL_CK8M_DFREQ_V << RTC_CNTL_CK8M_DFREQ_S) +#define RTC_CNTL_CK8M_DFREQ_V 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_S 17 + +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W; bitpos: [16]; default: 0; + * CK8M force no gating during sleep + */ + +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (RTC_CNTL_CK8M_FORCE_NOGATING_V << RTC_CNTL_CK8M_FORCE_NOGATING_S) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x00000001 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 + +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W; bitpos: [15]; default: 0; + * XTAL force no gating during sleep + */ + +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (RTC_CNTL_XTAL_FORCE_NOGATING_V << RTC_CNTL_XTAL_FORCE_NOGATING_S) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x00000001 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 + +/* RTC_CNTL_CK8M_DIV_SEL : R/W; bitpos: [14:12]; default: 3; + * divider = reg_ck8m_div_sel + 1 + */ + +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M (RTC_CNTL_CK8M_DIV_SEL_V << RTC_CNTL_CK8M_DIV_SEL_S) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_S 12 + +/* RTC_CNTL_DIG_CLK8M_EN : R/W; bitpos: [10]; default: 0; + * enable CK8M for digital core (no relationship with RTC core) + */ + +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_M (RTC_CNTL_DIG_CLK8M_EN_V << RTC_CNTL_DIG_CLK8M_EN_S) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x00000001 +#define RTC_CNTL_DIG_CLK8M_EN_S 10 + +/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W; bitpos: [9]; default: 1; + * enable CK8M_D256_OUT for digital core (no relationship with RTC core) + */ + +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_M (RTC_CNTL_DIG_CLK8M_D256_EN_V << RTC_CNTL_DIG_CLK8M_D256_EN_S) +#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x00000001 +#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 + +/* RTC_CNTL_DIG_XTAL32K_EN : R/W; bitpos: [8]; default: 0; + * enable CK_XTAL_32K for digital core (no relationship with RTC core) + */ + +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (RTC_CNTL_DIG_XTAL32K_EN_V << RTC_CNTL_DIG_XTAL32K_EN_S) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x00000001 +#define RTC_CNTL_DIG_XTAL32K_EN_S 8 + +/* RTC_CNTL_ENB_CK8M_DIV : R/W; bitpos: [7]; default: 0; + * 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by + * 256 + */ + +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_M (RTC_CNTL_ENB_CK8M_DIV_V << RTC_CNTL_ENB_CK8M_DIV_S) +#define RTC_CNTL_ENB_CK8M_DIV_V 0x00000001 +#define RTC_CNTL_ENB_CK8M_DIV_S 7 + +/* RTC_CNTL_ENB_CK8M : R/W; bitpos: [6]; default: 0; + * disable CK8M and CK8M_D256_OUT + */ + +#define RTC_CNTL_ENB_CK8M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_M (RTC_CNTL_ENB_CK8M_V << RTC_CNTL_ENB_CK8M_S) +#define RTC_CNTL_ENB_CK8M_V 0x00000001 +#define RTC_CNTL_ENB_CK8M_S 6 + +/* RTC_CNTL_CK8M_DIV : R/W; bitpos: [5:4]; default: 1; + * CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: + * div1024. + */ + +#define RTC_CNTL_CK8M_DIV 0x00000003 +#define RTC_CNTL_CK8M_DIV_M (RTC_CNTL_CK8M_DIV_V << RTC_CNTL_CK8M_DIV_S) +#define RTC_CNTL_CK8M_DIV_V 0x00000003 +#define RTC_CNTL_CK8M_DIV_S 4 + +/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W; bitpos: [3]; default: 1; + * used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel + * then set vld to actually switch the clk + */ + +#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (RTC_CNTL_CK8M_DIV_SEL_VLD_V << RTC_CNTL_CK8M_DIV_SEL_VLD_S) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x00000001 +#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 + +/* RTC_CNTL_SLOW_CLK_CONF_REG register + * configure rtc slow clk register + */ + +#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) + +/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W; bitpos: [31]; default: 0; */ + +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (RTC_CNTL_SLOW_CLK_NEXT_EDGE_V << RTC_CNTL_SLOW_CLK_NEXT_EDGE_S) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x00000001 +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 + +/* RTC_CNTL_ANA_CLK_DIV : R/W; bitpos: [30:23]; default: 0; + * rtc_clk divider + */ + +#define RTC_CNTL_ANA_CLK_DIV 0x000000FF +#define RTC_CNTL_ANA_CLK_DIV_M (RTC_CNTL_ANA_CLK_DIV_V << RTC_CNTL_ANA_CLK_DIV_S) +#define RTC_CNTL_ANA_CLK_DIV_V 0x000000FF +#define RTC_CNTL_ANA_CLK_DIV_S 23 + +/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W; bitpos: [22]; default: 1; + * used to sync div bus. clear vld before set reg_rtc_ana_clk_div then set + * vld to actually switch the clk + */ + +#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_M (RTC_CNTL_ANA_CLK_DIV_VLD_V << RTC_CNTL_ANA_CLK_DIV_VLD_S) +#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x00000001 +#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 + +/* RTC_CNTL_SDIO_CONF_REG register + * configure vddsdio register + */ + +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x7c) + +/* RTC_CNTL_XPD_SDIO_REG : R/W; bitpos: [31]; default: 0; + * SW option for XPD_VOOSDIO. Only active when reg_sdio_force = 1 + */ + +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (RTC_CNTL_XPD_SDIO_REG_V << RTC_CNTL_XPD_SDIO_REG_S) +#define RTC_CNTL_XPD_SDIO_REG_V 0x00000001 +#define RTC_CNTL_XPD_SDIO_REG_S 31 + +/* RTC_CNTL_DREFH_SDIO : R/W; bitpos: [30:29]; default: 0; + * SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 + */ + +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M (RTC_CNTL_DREFH_SDIO_V << RTC_CNTL_DREFH_SDIO_S) +#define RTC_CNTL_DREFH_SDIO_V 0x00000003 +#define RTC_CNTL_DREFH_SDIO_S 29 + +/* RTC_CNTL_DREFM_SDIO : R/W; bitpos: [28:27]; default: 0; + * SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 + */ + +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M (RTC_CNTL_DREFM_SDIO_V << RTC_CNTL_DREFM_SDIO_S) +#define RTC_CNTL_DREFM_SDIO_V 0x00000003 +#define RTC_CNTL_DREFM_SDIO_S 27 + +/* RTC_CNTL_DREFL_SDIO : R/W; bitpos: [26:25]; default: 1; + * SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 + */ + +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M (RTC_CNTL_DREFL_SDIO_V << RTC_CNTL_DREFL_SDIO_S) +#define RTC_CNTL_DREFL_SDIO_V 0x00000003 +#define RTC_CNTL_DREFL_SDIO_S 25 + +/* RTC_CNTL_REG1P8_READY : RO; bitpos: [24]; default: 0; + * read only register for REG1P8_READY + */ + +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (RTC_CNTL_REG1P8_READY_V << RTC_CNTL_REG1P8_READY_S) +#define RTC_CNTL_REG1P8_READY_V 0x00000001 +#define RTC_CNTL_REG1P8_READY_S 24 + +/* RTC_CNTL_SDIO_TIEH : R/W; bitpos: [23]; default: 1; + * SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 + */ + +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (RTC_CNTL_SDIO_TIEH_V << RTC_CNTL_SDIO_TIEH_S) +#define RTC_CNTL_SDIO_TIEH_V 0x00000001 +#define RTC_CNTL_SDIO_TIEH_S 23 + +/* RTC_CNTL_SDIO_FORCE : R/W; bitpos: [22]; default: 0; + * 1: use SW option to control SDIO_REG 0: use state machine + */ + +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (RTC_CNTL_SDIO_FORCE_V << RTC_CNTL_SDIO_FORCE_S) +#define RTC_CNTL_SDIO_FORCE_V 0x00000001 +#define RTC_CNTL_SDIO_FORCE_S 22 + +/* RTC_CNTL_SDIO_REG_PD_EN : R/W; bitpos: [21]; default: 1; + * power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 + */ + +#define RTC_CNTL_SDIO_REG_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_REG_PD_EN_M (RTC_CNTL_SDIO_REG_PD_EN_V << RTC_CNTL_SDIO_REG_PD_EN_S) +#define RTC_CNTL_SDIO_REG_PD_EN_V 0x00000001 +#define RTC_CNTL_SDIO_REG_PD_EN_S 21 + +/* RTC_CNTL_SDIO_ENCURLIM : R/W; bitpos: [20]; default: 1; + * enable current limit + */ + +#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_M (RTC_CNTL_SDIO_ENCURLIM_V << RTC_CNTL_SDIO_ENCURLIM_S) +#define RTC_CNTL_SDIO_ENCURLIM_V 0x00000001 +#define RTC_CNTL_SDIO_ENCURLIM_S 20 + +/* RTC_CNTL_SDIO_MODECURLIM : R/W; bitpos: [19]; default: 0; + * select current limit mode + */ + +#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_M (RTC_CNTL_SDIO_MODECURLIM_V << RTC_CNTL_SDIO_MODECURLIM_S) +#define RTC_CNTL_SDIO_MODECURLIM_V 0x00000001 +#define RTC_CNTL_SDIO_MODECURLIM_S 19 + +/* RTC_CNTL_SDIO_DCURLIM : R/W; bitpos: [18:16]; default: 0; + * tune current limit threshold when tieh = 0. About 800mA/(8+d) + */ + +#define RTC_CNTL_SDIO_DCURLIM 0x00000007 +#define RTC_CNTL_SDIO_DCURLIM_M (RTC_CNTL_SDIO_DCURLIM_V << RTC_CNTL_SDIO_DCURLIM_S) +#define RTC_CNTL_SDIO_DCURLIM_V 0x00000007 +#define RTC_CNTL_SDIO_DCURLIM_S 16 + +/* RTC_CNTL_SDIO_EN_INITI : R/W; bitpos: [15]; default: 1; + * 0 to set init[1:0]=0 + */ + +#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_M (RTC_CNTL_SDIO_EN_INITI_V << RTC_CNTL_SDIO_EN_INITI_S) +#define RTC_CNTL_SDIO_EN_INITI_V 0x00000001 +#define RTC_CNTL_SDIO_EN_INITI_S 15 + +/* RTC_CNTL_SDIO_INITI : R/W; bitpos: [14:13]; default: 1; + * add resistor from ldo output to ground. 0: no res 1: 6k 2: 4k 3: 2k + */ + +#define RTC_CNTL_SDIO_INITI 0x00000003 +#define RTC_CNTL_SDIO_INITI_M (RTC_CNTL_SDIO_INITI_V << RTC_CNTL_SDIO_INITI_S) +#define RTC_CNTL_SDIO_INITI_V 0x00000003 +#define RTC_CNTL_SDIO_INITI_S 13 + +/* RTC_CNTL_SDIO_DCAP : R/W; bitpos: [12:11]; default: 3; + * ability to prevent LDO from overshoot + */ + +#define RTC_CNTL_SDIO_DCAP 0x00000003 +#define RTC_CNTL_SDIO_DCAP_M (RTC_CNTL_SDIO_DCAP_V << RTC_CNTL_SDIO_DCAP_S) +#define RTC_CNTL_SDIO_DCAP_V 0x00000003 +#define RTC_CNTL_SDIO_DCAP_S 11 + +/* RTC_CNTL_SDIO_DTHDRV : R/W; bitpos: [10:9]; default: 3; + * Tieh = 1 mode drive ability. Initially set to 0 to limit charge current + * set to 3 after several us. + */ + +#define RTC_CNTL_SDIO_DTHDRV 0x00000003 +#define RTC_CNTL_SDIO_DTHDRV_M (RTC_CNTL_SDIO_DTHDRV_V << RTC_CNTL_SDIO_DTHDRV_S) +#define RTC_CNTL_SDIO_DTHDRV_V 0x00000003 +#define RTC_CNTL_SDIO_DTHDRV_S 9 + +/* RTC_CNTL_SDIO_TIMER_TARGET : R/W; bitpos: [7:0]; default: 10; + * timer count to apply reg_sdio_dcap after sdio power on + */ + +#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF +#define RTC_CNTL_SDIO_TIMER_TARGET_M (RTC_CNTL_SDIO_TIMER_TARGET_V << RTC_CNTL_SDIO_TIMER_TARGET_S) +#define RTC_CNTL_SDIO_TIMER_TARGET_V 0x000000FF +#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 + +/* RTC_CNTL_BIAS_CONF_REG register + * configure power register + */ + +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x80) + +/* RTC_CNTL_RST_BIAS_I2C : R/W; bitpos: [31]; default: 0; */ + +#define RTC_CNTL_RST_BIAS_I2C (BIT(31)) +#define RTC_CNTL_RST_BIAS_I2C_M (RTC_CNTL_RST_BIAS_I2C_V << RTC_CNTL_RST_BIAS_I2C_S) +#define RTC_CNTL_RST_BIAS_I2C_V 0x00000001 +#define RTC_CNTL_RST_BIAS_I2C_S 31 + +/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W; bitpos: [30]; default: 0; + * DEC_HEARTBEAT_WIDTH + */ + +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30)) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (RTC_CNTL_DEC_HEARTBEAT_WIDTH_V << RTC_CNTL_DEC_HEARTBEAT_WIDTH_S) +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x00000001 +#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30 + +/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W; bitpos: [29]; default: 0; + * INC_HEARTBEAT_PERIOD + */ + +#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29)) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_M (RTC_CNTL_INC_HEARTBEAT_PERIOD_V << RTC_CNTL_INC_HEARTBEAT_PERIOD_S) +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x00000001 +#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29 + +/* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W; bitpos: [28]; default: 0; + * DEC_HEARTBEAT_PERIOD + */ + +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28)) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (RTC_CNTL_DEC_HEARTBEAT_PERIOD_V << RTC_CNTL_DEC_HEARTBEAT_PERIOD_S) +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x00000001 +#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28 + +/* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W; bitpos: [27]; default: 0; + * INC_HEARTBEAT_REFRESH + */ + +#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27)) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_M (RTC_CNTL_INC_HEARTBEAT_REFRESH_V << RTC_CNTL_INC_HEARTBEAT_REFRESH_S) +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x00000001 +#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27 + +/* RTC_CNTL_ENB_SCK_XTAL : R/W; bitpos: [26]; default: 0; + * ENB_SCK_XTAL + */ + +#define RTC_CNTL_ENB_SCK_XTAL (BIT(26)) +#define RTC_CNTL_ENB_SCK_XTAL_M (RTC_CNTL_ENB_SCK_XTAL_V << RTC_CNTL_ENB_SCK_XTAL_S) +#define RTC_CNTL_ENB_SCK_XTAL_V 0x00000001 +#define RTC_CNTL_ENB_SCK_XTAL_S 26 + +/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W; bitpos: [25:22]; default: 0; + * DBG_ATTEN when rtc in monitor state + */ + +#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F +#define RTC_CNTL_DBG_ATTEN_MONITOR_M (RTC_CNTL_DBG_ATTEN_MONITOR_V << RTC_CNTL_DBG_ATTEN_MONITOR_S) +#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0x0000000F +#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 + +/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W; bitpos: [21:18]; default: 0; + * DBG_ATTEN when rtc in sleep state + */ + +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M (RTC_CNTL_DBG_ATTEN_DEEP_SLP_V << RTC_CNTL_DBG_ATTEN_DEEP_SLP_S) +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0x0000000F +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 + +/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W; bitpos: [17]; default: 0; + * bias_sleep when rtc in monitor state + */ + +#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (RTC_CNTL_BIAS_SLEEP_MONITOR_V << RTC_CNTL_BIAS_SLEEP_MONITOR_S) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x00000001 +#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 + +/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W; bitpos: [16]; default: 1; + * bias_sleep when rtc in sleep_state + */ + +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V << RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x00000001 +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 + +/* RTC_CNTL_PD_CUR_MONITOR : R/W; bitpos: [15]; default: 0; + * xpd cur when rtc in monitor state + */ + +#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_M (RTC_CNTL_PD_CUR_MONITOR_V << RTC_CNTL_PD_CUR_MONITOR_S) +#define RTC_CNTL_PD_CUR_MONITOR_V 0x00000001 +#define RTC_CNTL_PD_CUR_MONITOR_S 15 + +/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W; bitpos: [14]; default: 0; + * xpd cur when rtc in sleep_state + */ + +#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_M (RTC_CNTL_PD_CUR_DEEP_SLP_V << RTC_CNTL_PD_CUR_DEEP_SLP_S) +#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x00000001 +#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 + +/* RTC_CNTL_BIAS_BUF_MONITOR : R/W; bitpos: [13]; default: 0; + * open bias buf when rtc in monitor state + */ + +#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_M (RTC_CNTL_BIAS_BUF_MONITOR_V << RTC_CNTL_BIAS_BUF_MONITOR_S) +#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x00000001 +#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 + +/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W; bitpos: [12]; default: 0; + * open bias buf when rtc in deep sleep + */ + +#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (RTC_CNTL_BIAS_BUF_DEEP_SLP_V << RTC_CNTL_BIAS_BUF_DEEP_SLP_S) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x00000001 +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 + +/* RTC_CNTL_BIAS_BUF_WAKE : R/W; bitpos: [11]; default: 1; + * open bias buf when rtc in wakeup + */ + +#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_M (RTC_CNTL_BIAS_BUF_WAKE_V << RTC_CNTL_BIAS_BUF_WAKE_S) +#define RTC_CNTL_BIAS_BUF_WAKE_V 0x00000001 +#define RTC_CNTL_BIAS_BUF_WAKE_S 11 + +/* RTC_CNTL_BIAS_BUF_IDLE : R/W; bitpos: [10]; default: 0; + * open bias buf when system in active + */ + +#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_M (RTC_CNTL_BIAS_BUF_IDLE_V << RTC_CNTL_BIAS_BUF_IDLE_S) +#define RTC_CNTL_BIAS_BUF_IDLE_V 0x00000001 +#define RTC_CNTL_BIAS_BUF_IDLE_S 10 + +/* RTC_CNTL_REG register + * configure rtc/dig regulator register + */ +#define RTC_CNTL_DIG_DBIAS_0V85 0 +#define RTC_CNTL_DIG_DBIAS_0V90 1 +#define RTC_CNTL_DIG_DBIAS_0V95 2 +#define RTC_CNTL_DIG_DBIAS_1V00 3 +#define RTC_CNTL_DIG_DBIAS_1V05 4 +#define RTC_CNTL_DIG_DBIAS_1V10 5 +#define RTC_CNTL_DIG_DBIAS_1V15 6 +#define RTC_CNTL_DIG_DBIAS_1V20 7 + +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x84) + +/* RTC_CNTL_REGULATOR_FORCE_PU : R/W; bitpos: [31]; default: 1; + * RTC_REG force power pu + */ + +#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_M (RTC_CNTL_REGULATOR_FORCE_PU_V << RTC_CNTL_REGULATOR_FORCE_PU_S) +#define RTC_CNTL_REGULATOR_FORCE_PU_V 0x00000001 +#define RTC_CNTL_REGULATOR_FORCE_PU_S 31 + +/* RTC_CNTL_REGULATOR_FORCE_PD : R/W; bitpos: [30]; default: 0; + * RTC_REG force power down (for RTC_REG power down means decrease the + * voltage to 0.8v or lower ) + */ + +#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_M (RTC_CNTL_REGULATOR_FORCE_PD_V << RTC_CNTL_REGULATOR_FORCE_PD_S) +#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x00000001 +#define RTC_CNTL_REGULATOR_FORCE_PD_S 30 + +/* RTC_CNTL_DBOOST_FORCE_PU : R/W; bitpos: [29]; default: 1; + * RTC_DBOOST force power up + */ + +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (RTC_CNTL_DBOOST_FORCE_PU_V << RTC_CNTL_DBOOST_FORCE_PU_S) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x00000001 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 + +/* RTC_CNTL_DBOOST_FORCE_PD : R/W; bitpos: [28]; default: 0; + * RTC_DBOOST force power down + */ + +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (RTC_CNTL_DBOOST_FORCE_PD_V << RTC_CNTL_DBOOST_FORCE_PD_S) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x00000001 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 + +/* RTC_CNTL_DBIAS_WAK : R/W; bitpos: [27:25]; default: 4; + * RTC_DBIAS during wakeup + */ + +#define RTC_CNTL_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DBIAS_WAK_M (RTC_CNTL_DBIAS_WAK_V << RTC_CNTL_DBIAS_WAK_S) +#define RTC_CNTL_DBIAS_WAK_V 0x00000007 +#define RTC_CNTL_DBIAS_WAK_S 25 + +/* RTC_CNTL_DBIAS_SLP : R/W; bitpos: [24:22]; default: 4; + * RTC_DBIAS during sleep + */ + +#define RTC_CNTL_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DBIAS_SLP_M (RTC_CNTL_DBIAS_SLP_V << RTC_CNTL_DBIAS_SLP_S) +#define RTC_CNTL_DBIAS_SLP_V 0x00000007 +#define RTC_CNTL_DBIAS_SLP_S 22 + +/* RTC_CNTL_SCK_DCAP : R/W; bitpos: [21:14]; default: 0; + * SCK_DCAP + */ + +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M (RTC_CNTL_SCK_DCAP_V << RTC_CNTL_SCK_DCAP_S) +#define RTC_CNTL_SCK_DCAP_V 0x000000FF +#define RTC_CNTL_SCK_DCAP_S 14 + +/* RTC_CNTL_DIG_REG_DBIAS_WAK : R/W; bitpos: [13:11]; default: 4; + * DIG_REG_DBIAS during wakeup + */ + +#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 +#define RTC_CNTL_DIG_DBIAS_WAK_M (RTC_CNTL_DIG_DBIAS_WAK_V << RTC_CNTL_DIG_DBIAS_WAK_S) +#define RTC_CNTL_DIG_DBIAS_WAK_V 0x00000007 +#define RTC_CNTL_DIG_DBIAS_WAK_S 11 + +/* RTC_CNTL_DIG_REG_DBIAS_SLP : R/W; bitpos: [10:8]; default: 4; + * DIG_REG_DBIAS during sleep + */ + +#define RTC_CNTL_DIG_DBIAS_SLP 0x00000007 +#define RTC_CNTL_DIG_DBIAS_SLP_M (RTC_CNTL_DIG_DBIAS_SLP_V << RTC_CNTL_DIG_DBIAS_SLP_S) +#define RTC_CNTL_DIG_DBIAS_SLP_V 0x00000007 +#define RTC_CNTL_DIG_DBIAS_SLP_S 8 + +/* RTC_CNTL_PWC_REG register + * configure rtc power configure + */ + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x88) + +/* RTC_CNTL_PAD_FORCE_HOLD : R/W; bitpos: [21]; default: 0; + * rtc pad force hold + */ + +#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_M (RTC_CNTL_PAD_FORCE_HOLD_V << RTC_CNTL_PAD_FORCE_HOLD_S) +#define RTC_CNTL_PAD_FORCE_HOLD_V 0x00000001 +#define RTC_CNTL_PAD_FORCE_HOLD_S 21 + +/* RTC_CNTL_PD_EN : R/W; bitpos: [20]; default: 0; + * enable power down rtc_peri in sleep + */ + +#define RTC_CNTL_PD_EN (BIT(20)) +#define RTC_CNTL_PD_EN_M (RTC_CNTL_PD_EN_V << RTC_CNTL_PD_EN_S) +#define RTC_CNTL_PD_EN_V 0x00000001 +#define RTC_CNTL_PD_EN_S 20 + +/* RTC_CNTL_FORCE_PU : R/W; bitpos: [19]; default: 0; + * rtc_peri force power up + */ + +#define RTC_CNTL_FORCE_PU (BIT(19)) +#define RTC_CNTL_FORCE_PU_M (RTC_CNTL_FORCE_PU_V << RTC_CNTL_FORCE_PU_S) +#define RTC_CNTL_FORCE_PU_V 0x00000001 +#define RTC_CNTL_FORCE_PU_S 19 + +/* RTC_CNTL_FORCE_PD : R/W; bitpos: [18]; default: 0; + * rtc_peri force power down + */ + +#define RTC_CNTL_FORCE_PD (BIT(18)) +#define RTC_CNTL_FORCE_PD_M (RTC_CNTL_FORCE_PD_V << RTC_CNTL_FORCE_PD_S) +#define RTC_CNTL_FORCE_PD_V 0x00000001 +#define RTC_CNTL_FORCE_PD_S 18 + +/* RTC_CNTL_SLOWMEM_PD_EN : R/W; bitpos: [17]; default: 0; + * enable power down RTC memory in sleep + */ + +#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_M (RTC_CNTL_SLOWMEM_PD_EN_V << RTC_CNTL_SLOWMEM_PD_EN_S) +#define RTC_CNTL_SLOWMEM_PD_EN_V 0x00000001 +#define RTC_CNTL_SLOWMEM_PD_EN_S 17 + +/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W; bitpos: [16]; default: 1; + * RTC memory force power up + */ + +#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_M (RTC_CNTL_SLOWMEM_FORCE_PU_V << RTC_CNTL_SLOWMEM_FORCE_PU_S) +#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x00000001 +#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 + +/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W; bitpos: [15]; default: 0; + * RTC memory force power down + */ + +#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_M (RTC_CNTL_SLOWMEM_FORCE_PD_V << RTC_CNTL_SLOWMEM_FORCE_PD_S) +#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x00000001 +#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 + +/* RTC_CNTL_FASTMEM_PD_EN : R/W; bitpos: [14]; default: 0; + * enable power down fast RTC memory in sleep + */ + +#define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_M (RTC_CNTL_FASTMEM_PD_EN_V << RTC_CNTL_FASTMEM_PD_EN_S) +#define RTC_CNTL_FASTMEM_PD_EN_V 0x00000001 +#define RTC_CNTL_FASTMEM_PD_EN_S 14 + +/* RTC_CNTL_FASTMEM_FORCE_PU : R/W; bitpos: [13]; default: 1; + * Fast RTC memory force power up + */ + +#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_M (RTC_CNTL_FASTMEM_FORCE_PU_V << RTC_CNTL_FASTMEM_FORCE_PU_S) +#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x00000001 +#define RTC_CNTL_FASTMEM_FORCE_PU_S 13 + +/* RTC_CNTL_FASTMEM_FORCE_PD : R/W; bitpos: [12]; default: 0; + * Fast RTC memory force power down + */ + +#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_M (RTC_CNTL_FASTMEM_FORCE_PD_V << RTC_CNTL_FASTMEM_FORCE_PD_S) +#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x00000001 +#define RTC_CNTL_FASTMEM_FORCE_PD_S 12 + +/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W; bitpos: [11]; default: 1; + * RTC memory force no PD + */ + +#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (RTC_CNTL_SLOWMEM_FORCE_LPU_V << RTC_CNTL_SLOWMEM_FORCE_LPU_S) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x00000001 +#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 + +/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W; bitpos: [10]; default: 0; + * RTC memory force PD + */ + +#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (RTC_CNTL_SLOWMEM_FORCE_LPD_V << RTC_CNTL_SLOWMEM_FORCE_LPD_S) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x00000001 +#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 + +/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W; bitpos: [9]; default: 0; + * 1: RTC memory PD following CPU 0: RTC memory PD following RTC state + * machine + */ + +#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (RTC_CNTL_SLOWMEM_FOLW_CPU_V << RTC_CNTL_SLOWMEM_FOLW_CPU_S) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x00000001 +#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 + +/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W; bitpos: [8]; default: 1; + * Fast RTC memory force no PD + */ + +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (RTC_CNTL_FASTMEM_FORCE_LPU_V << RTC_CNTL_FASTMEM_FORCE_LPU_S) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x00000001 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 + +/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W; bitpos: [7]; default: 0; + * Fast RTC memory force PD + */ + +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (RTC_CNTL_FASTMEM_FORCE_LPD_V << RTC_CNTL_FASTMEM_FORCE_LPD_S) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x00000001 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 + +/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W; bitpos: [6]; default: 0; + * 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC + * state machine + */ + +#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_M (RTC_CNTL_FASTMEM_FOLW_CPU_V << RTC_CNTL_FASTMEM_FOLW_CPU_S) +#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x00000001 +#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 + +/* RTC_CNTL_FORCE_NOISO : R/W; bitpos: [5]; default: 1; + * rtc_peri force no ISO + */ + +#define RTC_CNTL_FORCE_NOISO (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_M (RTC_CNTL_FORCE_NOISO_V << RTC_CNTL_FORCE_NOISO_S) +#define RTC_CNTL_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_FORCE_NOISO_S 5 + +/* RTC_CNTL_FORCE_ISO : R/W; bitpos: [4]; default: 0; + * rtc_peri force ISO + */ + +#define RTC_CNTL_FORCE_ISO (BIT(4)) +#define RTC_CNTL_FORCE_ISO_M (RTC_CNTL_FORCE_ISO_V << RTC_CNTL_FORCE_ISO_S) +#define RTC_CNTL_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_FORCE_ISO_S 4 + +/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W; bitpos: [3]; default: 0; + * RTC memory force ISO + */ + +#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (RTC_CNTL_SLOWMEM_FORCE_ISO_V << RTC_CNTL_SLOWMEM_FORCE_ISO_S) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 + +/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W; bitpos: [2]; default: 1; + * RTC memory force no ISO + */ + +#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (RTC_CNTL_SLOWMEM_FORCE_NOISO_V << RTC_CNTL_SLOWMEM_FORCE_NOISO_S) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 + +/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W; bitpos: [1]; default: 0; + * Fast RTC memory force ISO + */ + +#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_M (RTC_CNTL_FASTMEM_FORCE_ISO_V << RTC_CNTL_FASTMEM_FORCE_ISO_S) +#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 + +/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W; bitpos: [0]; default: 1; + * Fast RTC memory force no ISO + */ + +#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (RTC_CNTL_FASTMEM_FORCE_NOISO_V << RTC_CNTL_FASTMEM_FORCE_NOISO_S) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 + +/* RTC_CNTL_DIG_PWC_REG register + * configure power of digital core + */ + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x8c) + +/* RTC_CNTL_DG_WRAP_PD_EN : R/W; bitpos: [31]; default: 0; + * enable power down digital core in sleep + */ + +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (RTC_CNTL_DG_WRAP_PD_EN_V << RTC_CNTL_DG_WRAP_PD_EN_S) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x00000001 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 + +/* RTC_CNTL_WIFI_PD_EN : R/W; bitpos: [30]; default: 0; + * enable power down wifi in sleep + */ + +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (RTC_CNTL_WIFI_PD_EN_V << RTC_CNTL_WIFI_PD_EN_S) +#define RTC_CNTL_WIFI_PD_EN_V 0x00000001 +#define RTC_CNTL_WIFI_PD_EN_S 30 + +/* RTC_CNTL_INTER_RAM4_PD_EN : R/W; bitpos: [29]; default: 0; + * enable power down internal SRAM 4 in sleep + */ + +#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_M (RTC_CNTL_INTER_RAM4_PD_EN_V << RTC_CNTL_INTER_RAM4_PD_EN_S) +#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x00000001 +#define RTC_CNTL_INTER_RAM4_PD_EN_S 29 + +/* RTC_CNTL_INTER_RAM3_PD_EN : R/W; bitpos: [28]; default: 0; + * enable power down internal SRAM 3 in sleep + */ + +#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_M (RTC_CNTL_INTER_RAM3_PD_EN_V << RTC_CNTL_INTER_RAM3_PD_EN_S) +#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x00000001 +#define RTC_CNTL_INTER_RAM3_PD_EN_S 28 + +/* RTC_CNTL_INTER_RAM2_PD_EN : R/W; bitpos: [27]; default: 0; + * enable power down internal SRAM 2 in sleep + */ + +#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_M (RTC_CNTL_INTER_RAM2_PD_EN_V << RTC_CNTL_INTER_RAM2_PD_EN_S) +#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x00000001 +#define RTC_CNTL_INTER_RAM2_PD_EN_S 27 + +/* RTC_CNTL_INTER_RAM1_PD_EN : R/W; bitpos: [26]; default: 0; + * enable power down internal SRAM 1 in sleep + */ + +#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_M (RTC_CNTL_INTER_RAM1_PD_EN_V << RTC_CNTL_INTER_RAM1_PD_EN_S) +#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x00000001 +#define RTC_CNTL_INTER_RAM1_PD_EN_S 26 + +/* RTC_CNTL_INTER_RAM0_PD_EN : R/W; bitpos: [25]; default: 0; + * enable power down internal SRAM 0 in sleep + */ + +#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_M (RTC_CNTL_INTER_RAM0_PD_EN_V << RTC_CNTL_INTER_RAM0_PD_EN_S) +#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x00000001 +#define RTC_CNTL_INTER_RAM0_PD_EN_S 25 + +/* RTC_CNTL_ROM0_PD_EN : R/W; bitpos: [24]; default: 0; + * enable power down ROM in sleep + */ + +#define RTC_CNTL_ROM0_PD_EN (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_M (RTC_CNTL_ROM0_PD_EN_V << RTC_CNTL_ROM0_PD_EN_S) +#define RTC_CNTL_ROM0_PD_EN_V 0x00000001 +#define RTC_CNTL_ROM0_PD_EN_S 24 + +/* RTC_CNTL_DG_DCDC_PD_EN : R/W; bitpos: [23]; default: 0; + * enable power down digital dcdc in sleep + */ + +#define RTC_CNTL_DG_DCDC_PD_EN (BIT(23)) +#define RTC_CNTL_DG_DCDC_PD_EN_M (RTC_CNTL_DG_DCDC_PD_EN_V << RTC_CNTL_DG_DCDC_PD_EN_S) +#define RTC_CNTL_DG_DCDC_PD_EN_V 0x00000001 +#define RTC_CNTL_DG_DCDC_PD_EN_S 23 + +/* RTC_CNTL_DG_DCDC_FORCE_PU : R/W; bitpos: [22]; default: 1; + * digital dcdc force power up + */ + +#define RTC_CNTL_DG_DCDC_FORCE_PU (BIT(22)) +#define RTC_CNTL_DG_DCDC_FORCE_PU_M (RTC_CNTL_DG_DCDC_FORCE_PU_V << RTC_CNTL_DG_DCDC_FORCE_PU_S) +#define RTC_CNTL_DG_DCDC_FORCE_PU_V 0x00000001 +#define RTC_CNTL_DG_DCDC_FORCE_PU_S 22 + +/* RTC_CNTL_DG_DCDC_FORCE_PD : R/W; bitpos: [21]; default: 0; + * digital dcdc force power down + */ + +#define RTC_CNTL_DG_DCDC_FORCE_PD (BIT(21)) +#define RTC_CNTL_DG_DCDC_FORCE_PD_M (RTC_CNTL_DG_DCDC_FORCE_PD_V << RTC_CNTL_DG_DCDC_FORCE_PD_S) +#define RTC_CNTL_DG_DCDC_FORCE_PD_V 0x00000001 +#define RTC_CNTL_DG_DCDC_FORCE_PD_S 21 + +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W; bitpos: [20]; default: 1; + * digital core force power up + */ + +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (RTC_CNTL_DG_WRAP_FORCE_PU_V << RTC_CNTL_DG_WRAP_FORCE_PU_S) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x00000001 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 + +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W; bitpos: [19]; default: 0; + * digital core force power down + */ + +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (RTC_CNTL_DG_WRAP_FORCE_PD_V << RTC_CNTL_DG_WRAP_FORCE_PD_S) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x00000001 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 + +/* RTC_CNTL_WIFI_FORCE_PU : R/W; bitpos: [18]; default: 1; + * wifi force power up + */ + +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (RTC_CNTL_WIFI_FORCE_PU_V << RTC_CNTL_WIFI_FORCE_PU_S) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x00000001 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 + +/* RTC_CNTL_WIFI_FORCE_PD : R/W; bitpos: [17]; default: 0; + * wifi force power down + */ + +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (RTC_CNTL_WIFI_FORCE_PD_V << RTC_CNTL_WIFI_FORCE_PD_S) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x00000001 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 + +/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W; bitpos: [16]; default: 1; + * internal SRAM 4 force power up + */ + +#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (RTC_CNTL_INTER_RAM4_FORCE_PU_V << RTC_CNTL_INTER_RAM4_FORCE_PU_S) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x00000001 +#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 + +/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W; bitpos: [15]; default: 0; + * internal SRAM 4 force power down + */ + +#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (RTC_CNTL_INTER_RAM4_FORCE_PD_V << RTC_CNTL_INTER_RAM4_FORCE_PD_S) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x00000001 +#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 + +/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W; bitpos: [14]; default: 1; + * internal SRAM 3 force power up + */ + +#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (RTC_CNTL_INTER_RAM3_FORCE_PU_V << RTC_CNTL_INTER_RAM3_FORCE_PU_S) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x00000001 +#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 + +/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W; bitpos: [13]; default: 0; + * internal SRAM 3 force power down + */ + +#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (RTC_CNTL_INTER_RAM3_FORCE_PD_V << RTC_CNTL_INTER_RAM3_FORCE_PD_S) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x00000001 +#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 + +/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W; bitpos: [12]; default: 1; + * internal SRAM 2 force power up + */ + +#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (RTC_CNTL_INTER_RAM2_FORCE_PU_V << RTC_CNTL_INTER_RAM2_FORCE_PU_S) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x00000001 +#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 + +/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W; bitpos: [11]; default: 0; + * internal SRAM 2 force power down + */ + +#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (RTC_CNTL_INTER_RAM2_FORCE_PD_V << RTC_CNTL_INTER_RAM2_FORCE_PD_S) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x00000001 +#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 + +/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W; bitpos: [10]; default: 1; + * internal SRAM 1 force power up + */ + +#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (RTC_CNTL_INTER_RAM1_FORCE_PU_V << RTC_CNTL_INTER_RAM1_FORCE_PU_S) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x00000001 +#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 + +/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W; bitpos: [9]; default: 0; + * internal SRAM 1 force power down + */ + +#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (RTC_CNTL_INTER_RAM1_FORCE_PD_V << RTC_CNTL_INTER_RAM1_FORCE_PD_S) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x00000001 +#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 + +/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W; bitpos: [8]; default: 1; + * internal SRAM 0 force power up + */ + +#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (RTC_CNTL_INTER_RAM0_FORCE_PU_V << RTC_CNTL_INTER_RAM0_FORCE_PU_S) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x00000001 +#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 + +/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W; bitpos: [7]; default: 0; + * internal SRAM 0 force power down + */ + +#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (RTC_CNTL_INTER_RAM0_FORCE_PD_V << RTC_CNTL_INTER_RAM0_FORCE_PD_S) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x00000001 +#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 + +/* RTC_CNTL_ROM0_FORCE_PU : R/W; bitpos: [6]; default: 1; + * ROM force power up + */ + +#define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_M (RTC_CNTL_ROM0_FORCE_PU_V << RTC_CNTL_ROM0_FORCE_PU_S) +#define RTC_CNTL_ROM0_FORCE_PU_V 0x00000001 +#define RTC_CNTL_ROM0_FORCE_PU_S 6 + +/* RTC_CNTL_ROM0_FORCE_PD : R/W; bitpos: [5]; default: 0; + * ROM force power down + */ + +#define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_M (RTC_CNTL_ROM0_FORCE_PD_V << RTC_CNTL_ROM0_FORCE_PD_S) +#define RTC_CNTL_ROM0_FORCE_PD_V 0x00000001 +#define RTC_CNTL_ROM0_FORCE_PD_S 5 + +/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1; + * memories in digital core force no PD in sleep + */ + +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (RTC_CNTL_LSLP_MEM_FORCE_PU_V << RTC_CNTL_LSLP_MEM_FORCE_PU_S) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x00000001 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 + +/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; + * memories in digital core force PD in sleep + */ + +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (RTC_CNTL_LSLP_MEM_FORCE_PD_V << RTC_CNTL_LSLP_MEM_FORCE_PD_S) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x00000001 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 + +/* RTC_CNTL_DIG_ISO_REG register + * configure ISO of digital core + */ + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x90) + +/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W; bitpos: [31]; default: 1; + * digital core force no ISO + */ + +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (RTC_CNTL_DG_WRAP_FORCE_NOISO_V << RTC_CNTL_DG_WRAP_FORCE_NOISO_S) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 + +/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W; bitpos: [30]; default: 0; + * digital core force ISO + */ + +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (RTC_CNTL_DG_WRAP_FORCE_ISO_V << RTC_CNTL_DG_WRAP_FORCE_ISO_S) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 + +/* RTC_CNTL_WIFI_FORCE_NOISO : R/W; bitpos: [29]; default: 1; + * wifi force no ISO + */ + +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (RTC_CNTL_WIFI_FORCE_NOISO_V << RTC_CNTL_WIFI_FORCE_NOISO_S) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 + +/* RTC_CNTL_WIFI_FORCE_ISO : R/W; bitpos: [28]; default: 0; + * wifi force ISO + */ + +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (RTC_CNTL_WIFI_FORCE_ISO_V << RTC_CNTL_WIFI_FORCE_ISO_S) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 + +/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W; bitpos: [27]; default: 1; + * internal SRAM 4 force no ISO + */ + +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (RTC_CNTL_INTER_RAM4_FORCE_NOISO_V << RTC_CNTL_INTER_RAM4_FORCE_NOISO_S) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 + +/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W; bitpos: [26]; default: 0; + * internal SRAM 4 force ISO + */ + +#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (RTC_CNTL_INTER_RAM4_FORCE_ISO_V << RTC_CNTL_INTER_RAM4_FORCE_ISO_S) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 + +/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W; bitpos: [25]; default: 1; + * internal SRAM 3 force no ISO + */ + +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (RTC_CNTL_INTER_RAM3_FORCE_NOISO_V << RTC_CNTL_INTER_RAM3_FORCE_NOISO_S) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 + +/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W; bitpos: [24]; default: 0; + * internal SRAM 3 force ISO + */ + +#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (RTC_CNTL_INTER_RAM3_FORCE_ISO_V << RTC_CNTL_INTER_RAM3_FORCE_ISO_S) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 + +/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W; bitpos: [23]; default: 1; + * internal SRAM 2 force no ISO + */ + +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (RTC_CNTL_INTER_RAM2_FORCE_NOISO_V << RTC_CNTL_INTER_RAM2_FORCE_NOISO_S) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 + +/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W; bitpos: [22]; default: 0; + * internal SRAM 2 force ISO + */ + +#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (RTC_CNTL_INTER_RAM2_FORCE_ISO_V << RTC_CNTL_INTER_RAM2_FORCE_ISO_S) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 + +/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W; bitpos: [21]; default: 1; + * internal SRAM 1 force no ISO + */ + +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (RTC_CNTL_INTER_RAM1_FORCE_NOISO_V << RTC_CNTL_INTER_RAM1_FORCE_NOISO_S) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 + +/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W; bitpos: [20]; default: 0; + * internal SRAM 1 force ISO + */ + +#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (RTC_CNTL_INTER_RAM1_FORCE_ISO_V << RTC_CNTL_INTER_RAM1_FORCE_ISO_S) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 + +/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W; bitpos: [19]; default: 1; + * internal SRAM 0 force no ISO + */ + +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (RTC_CNTL_INTER_RAM0_FORCE_NOISO_V << RTC_CNTL_INTER_RAM0_FORCE_NOISO_S) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 + +/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W; bitpos: [18]; default: 0; + * internal SRAM 0 force ISO + */ + +#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (RTC_CNTL_INTER_RAM0_FORCE_ISO_V << RTC_CNTL_INTER_RAM0_FORCE_ISO_S) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 + +/* RTC_CNTL_ROM0_FORCE_NOISO : R/W; bitpos: [17]; default: 1; + * ROM force no ISO + */ + +#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_M (RTC_CNTL_ROM0_FORCE_NOISO_V << RTC_CNTL_ROM0_FORCE_NOISO_S) +#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_ROM0_FORCE_NOISO_S 17 + +/* RTC_CNTL_ROM0_FORCE_ISO : R/W; bitpos: [16]; default: 0; + * ROM force ISO + */ + +#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_M (RTC_CNTL_ROM0_FORCE_ISO_V << RTC_CNTL_ROM0_FORCE_ISO_S) +#define RTC_CNTL_ROM0_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_ROM0_FORCE_ISO_S 16 + +/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W; bitpos: [15]; default: 0; + * digital pad force hold + */ + +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (RTC_CNTL_DG_PAD_FORCE_HOLD_V << RTC_CNTL_DG_PAD_FORCE_HOLD_S) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x00000001 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 + +/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W; bitpos: [14]; default: 1; + * digital pad force un-hold + */ + +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (RTC_CNTL_DG_PAD_FORCE_UNHOLD_V << RTC_CNTL_DG_PAD_FORCE_UNHOLD_S) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x00000001 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 + +/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W; bitpos: [13]; default: 0; + * digital pad force ISO + */ + +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (RTC_CNTL_DG_PAD_FORCE_ISO_V << RTC_CNTL_DG_PAD_FORCE_ISO_S) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x00000001 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 + +/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W; bitpos: [12]; default: 1; + * digital pad force no ISO + */ + +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (RTC_CNTL_DG_PAD_FORCE_NOISO_V << RTC_CNTL_DG_PAD_FORCE_NOISO_S) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x00000001 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 + +/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W; bitpos: [11]; default: 0; + * digital pad enable auto-hold + */ + +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (RTC_CNTL_DG_PAD_AUTOHOLD_EN_V << RTC_CNTL_DG_PAD_AUTOHOLD_EN_S) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x00000001 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 + +/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO; bitpos: [10]; default: 0; + * wtite only register to clear digital pad auto-hold + */ + +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V << RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x00000001 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 + +/* RTC_CNTL_DG_PAD_AUTOHOLD : RO; bitpos: [9]; default: 0; + * read only register to indicate digital pad auto-hold status + */ + +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (RTC_CNTL_DG_PAD_AUTOHOLD_V << RTC_CNTL_DG_PAD_AUTOHOLD_S) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x00000001 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 + +/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W; bitpos: [8]; default: 0; */ + +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (RTC_CNTL_DIG_ISO_FORCE_ON_V << RTC_CNTL_DIG_ISO_FORCE_ON_S) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x00000001 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 + +/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W; bitpos: [7]; default: 0; */ + +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (RTC_CNTL_DIG_ISO_FORCE_OFF_V << RTC_CNTL_DIG_ISO_FORCE_OFF_S) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x00000001 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 + +/* RTC_CNTL_WDTCONFIG0_REG register + * configure rtc watch dog register + */ + +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x94) + +/* RTC_CNTL_WDT_EN : R/W; bitpos: [31]; default: 0; + * enable rtc wdt + */ + +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (RTC_CNTL_WDT_EN_V << RTC_CNTL_WDT_EN_S) +#define RTC_CNTL_WDT_EN_V 0x00000001 +#define RTC_CNTL_WDT_EN_S 31 + +/* RTC_CNTL_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; + * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en + * 4: RTC reset stage en + */ + +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M (RTC_CNTL_WDT_STG0_V << RTC_CNTL_WDT_STG0_S) +#define RTC_CNTL_WDT_STG0_V 0x00000007 +#define RTC_CNTL_WDT_STG0_S 28 + +/* RTC_CNTL_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; + * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en + * 4: RTC reset stage en + */ + +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M (RTC_CNTL_WDT_STG1_V << RTC_CNTL_WDT_STG1_S) +#define RTC_CNTL_WDT_STG1_V 0x00000007 +#define RTC_CNTL_WDT_STG1_S 25 + +/* RTC_CNTL_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; + * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en + * 4: RTC reset stage en + */ + +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M (RTC_CNTL_WDT_STG2_V << RTC_CNTL_WDT_STG2_S) +#define RTC_CNTL_WDT_STG2_V 0x00000007 +#define RTC_CNTL_WDT_STG2_S 22 + +/* RTC_CNTL_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; + * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en + * 4: RTC reset stage en + */ + +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M (RTC_CNTL_WDT_STG3_V << RTC_CNTL_WDT_STG3_S) +#define RTC_CNTL_WDT_STG3_V 0x00000007 +#define RTC_CNTL_WDT_STG3_S 19 + +/* RTC_CNTL_WDT_STGX : + * description: stage action selection values + */ + +#define RTC_WDT_STG_SEL_OFF 0 +#define RTC_WDT_STG_SEL_INT 1 +#define RTC_WDT_STG_SEL_RESET_CPU 2 +#define RTC_WDT_STG_SEL_RESET_SYSTEM 3 +#define RTC_WDT_STG_SEL_RESET_RTC 4 + +/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; + * CPU reset counter length + */ + +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M (RTC_CNTL_WDT_CPU_RESET_LENGTH_V << RTC_CNTL_WDT_CPU_RESET_LENGTH_S) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 + +/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; + * system reset counter length + */ + +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M (RTC_CNTL_WDT_SYS_RESET_LENGTH_V << RTC_CNTL_WDT_SYS_RESET_LENGTH_S) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 + +/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; + * enable WDT in flash boot + */ + +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V << RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x00000001 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 + +/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; + * enable WDT reset PRO CPU + */ + +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (RTC_CNTL_WDT_PROCPU_RESET_EN_V << RTC_CNTL_WDT_PROCPU_RESET_EN_S) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x00000001 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 + +/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; + * enable WDT reset APP CPU + */ + +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (RTC_CNTL_WDT_APPCPU_RESET_EN_V << RTC_CNTL_WDT_APPCPU_RESET_EN_S) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x00000001 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 + +/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; + * pause WDT in sleep + */ + +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (RTC_CNTL_WDT_PAUSE_IN_SLP_V << RTC_CNTL_WDT_PAUSE_IN_SLP_S) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x00000001 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 + +/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0; + * wdt reset whole chip enable + */ + +#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_M (RTC_CNTL_WDT_CHIP_RESET_EN_V << RTC_CNTL_WDT_CHIP_RESET_EN_S) +#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x00000001 +#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 + +/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W; bitpos: [7:0]; default: 20; + * chip reset siginal pulse width + */ + +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M (RTC_CNTL_WDT_CHIP_RESET_WIDTH_V << RTC_CNTL_WDT_CHIP_RESET_WIDTH_S) +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0x000000FF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 + +/* RTC_CNTL_WDTCONFIG1_REG register + * Configure hold time of rtc wdt at level1 + */ + +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x98) + +/* RTC_CNTL_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; + * Configure hold time of rtc wdt at level1 + */ + +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M (RTC_CNTL_WDT_STG0_HOLD_V << RTC_CNTL_WDT_STG0_HOLD_S) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 + +/* RTC_CNTL_WDTCONFIG2_REG register + * Configure hold time of rtc wdt at level2 + */ + +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x9c) + +/* RTC_CNTL_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; + * Configure hold time of rtc wdt at level2 + */ + +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M (RTC_CNTL_WDT_STG1_HOLD_V << RTC_CNTL_WDT_STG1_HOLD_S) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 + +/* RTC_CNTL_WDTCONFIG3_REG register + * Configure hold time of rtc wdt at level3 + */ + +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0xa0) + +/* RTC_CNTL_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; + * Configure hold time of rtc wdt at level3 + */ + +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M (RTC_CNTL_WDT_STG2_HOLD_V << RTC_CNTL_WDT_STG2_HOLD_S) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 + +/* RTC_CNTL_WDTCONFIG4_REG register + * Configure hold time of rtc wdt at level4 + */ + +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0xa4) + +/* RTC_CNTL_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; + * Configure hold time of rtc wdt at level4 + */ + +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M (RTC_CNTL_WDT_STG3_HOLD_V << RTC_CNTL_WDT_STG3_HOLD_S) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 + +/* RTC_CNTL_WDTFEED_REG register + * feed rtc wdt by sw + */ + +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa8) + +/* RTC_CNTL_WDT_FEED : WO; bitpos: [31]; default: 0; + * Set 1 to feed rtc wdt + */ + +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (RTC_CNTL_WDT_FEED_V << RTC_CNTL_WDT_FEED_S) +#define RTC_CNTL_WDT_FEED_V 0x00000001 +#define RTC_CNTL_WDT_FEED_S 31 + +/* RTC_CNTL_WDTWPROTECT_REG register + * configure rtc wdt write protect + */ + +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xac) + +/* RTC_CNTL_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; + * wdt_wprotectn + */ + +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M (RTC_CNTL_WDT_WKEY_V << RTC_CNTL_WDT_WKEY_S) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 + +/* RTC_CNTL_SWD_CONF_REG register + * configure super watch dog + */ + +#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xb0) + +/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W; bitpos: [31]; default: 0; + * automatically feed swd when int comes + */ + +#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_M (RTC_CNTL_SWD_AUTO_FEED_EN_V << RTC_CNTL_SWD_AUTO_FEED_EN_S) +#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x00000001 +#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 + +/* RTC_CNTL_SWD_DISABLE : R/W; bitpos: [30]; default: 0; + * disabel SWD + */ + +#define RTC_CNTL_SWD_DISABLE (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_M (RTC_CNTL_SWD_DISABLE_V << RTC_CNTL_SWD_DISABLE_S) +#define RTC_CNTL_SWD_DISABLE_V 0x00000001 +#define RTC_CNTL_SWD_DISABLE_S 30 + +/* RTC_CNTL_SWD_FEED : WO; bitpos: [29]; default: 0; + * Sw feed swd + */ + +#define RTC_CNTL_SWD_FEED (BIT(29)) +#define RTC_CNTL_SWD_FEED_M (RTC_CNTL_SWD_FEED_V << RTC_CNTL_SWD_FEED_S) +#define RTC_CNTL_SWD_FEED_V 0x00000001 +#define RTC_CNTL_SWD_FEED_S 29 + +/* RTC_CNTL_SWD_RST_FLAG_CLR : WO; bitpos: [28]; default: 0; + * reset swd reset flag + */ + +#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_M (RTC_CNTL_SWD_RST_FLAG_CLR_V << RTC_CNTL_SWD_RST_FLAG_CLR_S) +#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x00000001 +#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 + +/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W; bitpos: [27:18]; default: 300; + * adjust signal width send to swd + */ + +#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_M (RTC_CNTL_SWD_SIGNAL_WIDTH_V << RTC_CNTL_SWD_SIGNAL_WIDTH_S) +#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x000003FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 + +/* RTC_CNTL_SWD_FEED_INT : RO; bitpos: [1]; default: 0; + * swd interrupt for feeding + */ + +#define RTC_CNTL_SWD_FEED_INT (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_M (RTC_CNTL_SWD_FEED_INT_V << RTC_CNTL_SWD_FEED_INT_S) +#define RTC_CNTL_SWD_FEED_INT_V 0x00000001 +#define RTC_CNTL_SWD_FEED_INT_S 1 + +/* RTC_CNTL_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; + * swd reset flag + */ + +#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_M (RTC_CNTL_SWD_RESET_FLAG_V << RTC_CNTL_SWD_RESET_FLAG_S) +#define RTC_CNTL_SWD_RESET_FLAG_V 0x00000001 +#define RTC_CNTL_SWD_RESET_FLAG_S 0 + +/* RTC_CNTL_SWD_WPROTECT_REG register + * configure super watch dog write protect + */ + +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xb4) + +/* RTC_CNTL_SWD_WKEY : R/W; bitpos: [31:0]; default: 2401055018; + * swd write protect + */ + +#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_M (RTC_CNTL_SWD_WKEY_V << RTC_CNTL_SWD_WKEY_S) +#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_S 0 + +/* RTC_CNTL_SW_CPU_STALL_REG register + * configure cpu stall register + */ + +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xb8) + +/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W; bitpos: [31:26]; default: 0; + * enable cpu enter stall status by sw + */ + +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M (RTC_CNTL_SW_STALL_PROCPU_C1_V << RTC_CNTL_SW_STALL_PROCPU_C1_S) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 + +/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W; bitpos: [25:20]; default: 0; + * {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will + * stall APP CPU + */ + +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M (RTC_CNTL_SW_STALL_APPCPU_C1_V << RTC_CNTL_SW_STALL_APPCPU_C1_S) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 + +/* RTC_CNTL_STORE4_REG register + * reservation register4 + */ + +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xbc) + +/* RTC_CNTL_SCRATCH4 : R/W; bitpos: [31:0]; default: 0; + * reservation register4 + */ + +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M (RTC_CNTL_SCRATCH4_V << RTC_CNTL_SCRATCH4_S) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 + +/* RTC_CNTL_STORE5_REG register + * reservation register5 + */ + +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xc0) + +/* RTC_CNTL_SCRATCH5 : R/W; bitpos: [31:0]; default: 0; + * reservation register5 + */ + +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M (RTC_CNTL_SCRATCH5_V << RTC_CNTL_SCRATCH5_S) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 + +/* RTC_CNTL_STORE6_REG register + * reservation register6 + */ + +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xc4) + +/* RTC_CNTL_SCRATCH6 : R/W; bitpos: [31:0]; default: 0; + * reservation register6 + */ + +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M (RTC_CNTL_SCRATCH6_V << RTC_CNTL_SCRATCH6_S) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 + +/* RTC_CNTL_STORE7_REG register + * reservation register7 + */ + +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xc8) + +/* RTC_CNTL_SCRATCH7 : R/W; bitpos: [31:0]; default: 0; + * reservation register7 + */ + +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M (RTC_CNTL_SCRATCH7_V << RTC_CNTL_SCRATCH7_S) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 + +/* RTC_CNTL_LOW_POWER_ST_REG register + * rtc main state machine status + */ + +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xcc) + +/* RTC_CNTL_MAIN_STATE : RO; bitpos: [31:28]; default: 0; + * rtc main state machine status + */ + +#define RTC_CNTL_MAIN_STATE 0x0000000F +#define RTC_CNTL_MAIN_STATE_M (RTC_CNTL_MAIN_STATE_V << RTC_CNTL_MAIN_STATE_S) +#define RTC_CNTL_MAIN_STATE_V 0x0000000F +#define RTC_CNTL_MAIN_STATE_S 28 + +/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO; bitpos: [27]; default: 0; + * rtc main state machine is in idle state + */ + +#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (RTC_CNTL_MAIN_STATE_IN_IDLE_V << RTC_CNTL_MAIN_STATE_IN_IDLE_S) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 + +/* RTC_CNTL_MAIN_STATE_IN_SLP : RO; bitpos: [26]; default: 0; + * rtc main state machine is in sleep state + */ + +#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_M (RTC_CNTL_MAIN_STATE_IN_SLP_V << RTC_CNTL_MAIN_STATE_IN_SLP_S) +#define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 + +/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO; bitpos: [25]; default: 0; + * rtc main state machine is in wait xtal state + */ + +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V << RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 + +/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO; bitpos: [24]; default: 0; + * rtc main state machine is in wait pll state + */ + +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V << RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 + +/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO; bitpos: [23]; default: 0; + * rtc main state machine is in wait 8m state + */ + +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V << RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 + +/* RTC_CNTL_IN_LOW_POWER_STATE : RO; bitpos: [22]; default: 0; + * rtc main state machine is in the states of low power + */ + +#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_M (RTC_CNTL_IN_LOW_POWER_STATE_V << RTC_CNTL_IN_LOW_POWER_STATE_S) +#define RTC_CNTL_IN_LOW_POWER_STATE_V 0x00000001 +#define RTC_CNTL_IN_LOW_POWER_STATE_S 22 + +/* RTC_CNTL_IN_WAKEUP_STATE : RO; bitpos: [21]; default: 0; + * rtc main state machine is in the states of wakeup process + */ + +#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_M (RTC_CNTL_IN_WAKEUP_STATE_V << RTC_CNTL_IN_WAKEUP_STATE_S) +#define RTC_CNTL_IN_WAKEUP_STATE_V 0x00000001 +#define RTC_CNTL_IN_WAKEUP_STATE_S 21 + +/* RTC_CNTL_MAIN_STATE_WAIT_END : RO; bitpos: [20]; default: 0; + * rtc main state machine has been waited for some cycles + */ + +#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_M (RTC_CNTL_MAIN_STATE_WAIT_END_V << RTC_CNTL_MAIN_STATE_WAIT_END_S) +#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 + +/* RTC_CNTL_RDY_FOR_WAKEUP : RO; bitpos: [19]; default: 0; + * rtc is ready to receive wake up trigger from wake up source + */ + +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_M (RTC_CNTL_RDY_FOR_WAKEUP_V << RTC_CNTL_RDY_FOR_WAKEUP_S) +#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x00000001 +#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 + +/* RTC_CNTL_MAIN_STATE_PLL_ON : RO; bitpos: [18]; default: 0; + * rtc main state machine is in states that pll should be running + */ + +#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_M (RTC_CNTL_MAIN_STATE_PLL_ON_V << RTC_CNTL_MAIN_STATE_PLL_ON_S) +#define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 + +/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO; bitpos: [17]; default: 0; + * no use any more + */ + +#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (RTC_CNTL_MAIN_STATE_XTAL_ISO_V << RTC_CNTL_MAIN_STATE_XTAL_ISO_S) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x00000001 +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 + +/* RTC_CNTL_COCPU_STATE_DONE : RO; bitpos: [16]; default: 0; + * ulp/cocpu is done + */ + +#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_M (RTC_CNTL_COCPU_STATE_DONE_V << RTC_CNTL_COCPU_STATE_DONE_S) +#define RTC_CNTL_COCPU_STATE_DONE_V 0x00000001 +#define RTC_CNTL_COCPU_STATE_DONE_S 16 + +/* RTC_CNTL_COCPU_STATE_SLP : RO; bitpos: [15]; default: 0; + * ulp/cocpu is in sleep state + */ + +#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_M (RTC_CNTL_COCPU_STATE_SLP_V << RTC_CNTL_COCPU_STATE_SLP_S) +#define RTC_CNTL_COCPU_STATE_SLP_V 0x00000001 +#define RTC_CNTL_COCPU_STATE_SLP_S 15 + +/* RTC_CNTL_COCPU_STATE_SWITCH : RO; bitpos: [14]; default: 0; + * ulp/cocpu is about to working. Switch rtc main state + */ + +#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_M (RTC_CNTL_COCPU_STATE_SWITCH_V << RTC_CNTL_COCPU_STATE_SWITCH_S) +#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x00000001 +#define RTC_CNTL_COCPU_STATE_SWITCH_S 14 + +/* RTC_CNTL_COCPU_STATE_START : RO; bitpos: [13]; default: 0; + * ulp/cocpu should start to work + */ + +#define RTC_CNTL_COCPU_STATE_START (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_M (RTC_CNTL_COCPU_STATE_START_V << RTC_CNTL_COCPU_STATE_START_S) +#define RTC_CNTL_COCPU_STATE_START_V 0x00000001 +#define RTC_CNTL_COCPU_STATE_START_S 13 + +/* RTC_CNTL_TOUCH_STATE_DONE : RO; bitpos: [12]; default: 0; + * touch is done + */ + +#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_M (RTC_CNTL_TOUCH_STATE_DONE_V << RTC_CNTL_TOUCH_STATE_DONE_S) +#define RTC_CNTL_TOUCH_STATE_DONE_V 0x00000001 +#define RTC_CNTL_TOUCH_STATE_DONE_S 12 + +/* RTC_CNTL_TOUCH_STATE_SLP : RO; bitpos: [11]; default: 0; + * touch is in sleep state + */ + +#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_M (RTC_CNTL_TOUCH_STATE_SLP_V << RTC_CNTL_TOUCH_STATE_SLP_S) +#define RTC_CNTL_TOUCH_STATE_SLP_V 0x00000001 +#define RTC_CNTL_TOUCH_STATE_SLP_S 11 + +/* RTC_CNTL_TOUCH_STATE_SWITCH : RO; bitpos: [10]; default: 0; + * touch is about to working. Switch rtc main state + */ + +#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_M (RTC_CNTL_TOUCH_STATE_SWITCH_V << RTC_CNTL_TOUCH_STATE_SWITCH_S) +#define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x00000001 +#define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 + +/* RTC_CNTL_TOUCH_STATE_START : RO; bitpos: [9]; default: 0; + * touch should start to work + */ + +#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_M (RTC_CNTL_TOUCH_STATE_START_V << RTC_CNTL_TOUCH_STATE_START_S) +#define RTC_CNTL_TOUCH_STATE_START_V 0x00000001 +#define RTC_CNTL_TOUCH_STATE_START_S 9 + +/* RTC_CNTL_XPD_DIG : RO; bitpos: [8]; default: 0; + * digital wrap power down + */ + +#define RTC_CNTL_XPD_DIG (BIT(8)) +#define RTC_CNTL_XPD_DIG_M (RTC_CNTL_XPD_DIG_V << RTC_CNTL_XPD_DIG_S) +#define RTC_CNTL_XPD_DIG_V 0x00000001 +#define RTC_CNTL_XPD_DIG_S 8 + +/* RTC_CNTL_DIG_ISO : RO; bitpos: [7]; default: 0; + * digital wrap iso + */ + +#define RTC_CNTL_DIG_ISO (BIT(7)) +#define RTC_CNTL_DIG_ISO_M (RTC_CNTL_DIG_ISO_V << RTC_CNTL_DIG_ISO_S) +#define RTC_CNTL_DIG_ISO_V 0x00000001 +#define RTC_CNTL_DIG_ISO_S 7 + +/* RTC_CNTL_XPD_WIFI : RO; bitpos: [6]; default: 0; + * wifi wrap power down + */ + +#define RTC_CNTL_XPD_WIFI (BIT(6)) +#define RTC_CNTL_XPD_WIFI_M (RTC_CNTL_XPD_WIFI_V << RTC_CNTL_XPD_WIFI_S) +#define RTC_CNTL_XPD_WIFI_V 0x00000001 +#define RTC_CNTL_XPD_WIFI_S 6 + +/* RTC_CNTL_WIFI_ISO : RO; bitpos: [5]; default: 0; + * wifi iso + */ + +#define RTC_CNTL_WIFI_ISO (BIT(5)) +#define RTC_CNTL_WIFI_ISO_M (RTC_CNTL_WIFI_ISO_V << RTC_CNTL_WIFI_ISO_S) +#define RTC_CNTL_WIFI_ISO_V 0x00000001 +#define RTC_CNTL_WIFI_ISO_S 5 + +/* RTC_CNTL_XPD_RTC_PERI : RO; bitpos: [4]; default: 0; + * rtc peripheral power down + */ + +#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_M (RTC_CNTL_XPD_RTC_PERI_V << RTC_CNTL_XPD_RTC_PERI_S) +#define RTC_CNTL_XPD_RTC_PERI_V 0x00000001 +#define RTC_CNTL_XPD_RTC_PERI_S 4 + +/* RTC_CNTL_PERI_ISO : RO; bitpos: [3]; default: 0; + * rtc peripheral iso + */ + +#define RTC_CNTL_PERI_ISO (BIT(3)) +#define RTC_CNTL_PERI_ISO_M (RTC_CNTL_PERI_ISO_V << RTC_CNTL_PERI_ISO_S) +#define RTC_CNTL_PERI_ISO_V 0x00000001 +#define RTC_CNTL_PERI_ISO_S 3 + +/* RTC_CNTL_XPD_DIG_DCDC : RO; bitpos: [2]; default: 0; + * External DCDC power down + */ + +#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_M (RTC_CNTL_XPD_DIG_DCDC_V << RTC_CNTL_XPD_DIG_DCDC_S) +#define RTC_CNTL_XPD_DIG_DCDC_V 0x00000001 +#define RTC_CNTL_XPD_DIG_DCDC_S 2 + +/* RTC_CNTL_XPD_ROM0 : RO; bitpos: [0]; default: 0; + * rom0 power down + */ + +#define RTC_CNTL_XPD_ROM0 (BIT(0)) +#define RTC_CNTL_XPD_ROM0_M (RTC_CNTL_XPD_ROM0_V << RTC_CNTL_XPD_ROM0_S) +#define RTC_CNTL_XPD_ROM0_V 0x00000001 +#define RTC_CNTL_XPD_ROM0_S 0 + +/* RTC_CNTL_DIAG0_REG register + * debug register + */ + +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xd0) + +/* RTC_CNTL_LOW_POWER_DIAG1 : RO; bitpos: [31:0]; default: 0; */ + +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M (RTC_CNTL_LOW_POWER_DIAG1_V << RTC_CNTL_LOW_POWER_DIAG1_S) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 + +/* RTC_CNTL_PAD_HOLD_REG register + * configure rtc pad hold register + */ + +#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xd4) + +/* RTC_CNTL_PAD21_HOLD : R/W; bitpos: [21]; default: 0; + * set rtc_pad21_hold + */ + +#define RTC_CNTL_PAD21_HOLD (BIT(21)) +#define RTC_CNTL_PAD21_HOLD_M (RTC_CNTL_PAD21_HOLD_V << RTC_CNTL_PAD21_HOLD_S) +#define RTC_CNTL_PAD21_HOLD_V 0x00000001 +#define RTC_CNTL_PAD21_HOLD_S 21 + +/* RTC_CNTL_PAD20_HOLD : R/W; bitpos: [20]; default: 0; + * set rtc_pad20_hold + */ + +#define RTC_CNTL_PAD20_HOLD (BIT(20)) +#define RTC_CNTL_PAD20_HOLD_M (RTC_CNTL_PAD20_HOLD_V << RTC_CNTL_PAD20_HOLD_S) +#define RTC_CNTL_PAD20_HOLD_V 0x00000001 +#define RTC_CNTL_PAD20_HOLD_S 20 + +/* RTC_CNTL_PAD19_HOLD : R/W; bitpos: [19]; default: 0; + * set rtc_pad19_hold + */ + +#define RTC_CNTL_PAD19_HOLD (BIT(19)) +#define RTC_CNTL_PAD19_HOLD_M (RTC_CNTL_PAD19_HOLD_V << RTC_CNTL_PAD19_HOLD_S) +#define RTC_CNTL_PAD19_HOLD_V 0x00000001 +#define RTC_CNTL_PAD19_HOLD_S 19 + +/* RTC_CNTL_PDAC2_HOLD : R/W; bitpos: [18]; default: 0; + * set pdac2_hold + */ + +#define RTC_CNTL_PDAC2_HOLD (BIT(18)) +#define RTC_CNTL_PDAC2_HOLD_M (RTC_CNTL_PDAC2_HOLD_V << RTC_CNTL_PDAC2_HOLD_S) +#define RTC_CNTL_PDAC2_HOLD_V 0x00000001 +#define RTC_CNTL_PDAC2_HOLD_S 18 + +/* RTC_CNTL_PDAC1_HOLD : R/W; bitpos: [17]; default: 0; + * set pdac1_hold + */ + +#define RTC_CNTL_PDAC1_HOLD (BIT(17)) +#define RTC_CNTL_PDAC1_HOLD_M (RTC_CNTL_PDAC1_HOLD_V << RTC_CNTL_PDAC1_HOLD_S) +#define RTC_CNTL_PDAC1_HOLD_V 0x00000001 +#define RTC_CNTL_PDAC1_HOLD_S 17 + +/* RTC_CNTL_X32N_HOLD : R/W; bitpos: [16]; default: 0; + * set x32n_hold + */ + +#define RTC_CNTL_X32N_HOLD (BIT(16)) +#define RTC_CNTL_X32N_HOLD_M (RTC_CNTL_X32N_HOLD_V << RTC_CNTL_X32N_HOLD_S) +#define RTC_CNTL_X32N_HOLD_V 0x00000001 +#define RTC_CNTL_X32N_HOLD_S 16 + +/* RTC_CNTL_X32P_HOLD : R/W; bitpos: [15]; default: 0; + * Set x32p_hold + */ + +#define RTC_CNTL_X32P_HOLD (BIT(15)) +#define RTC_CNTL_X32P_HOLD_M (RTC_CNTL_X32P_HOLD_V << RTC_CNTL_X32P_HOLD_S) +#define RTC_CNTL_X32P_HOLD_V 0x00000001 +#define RTC_CNTL_X32P_HOLD_S 15 + +/* RTC_CNTL_TOUCH_PAD14_HOLD : R/W; bitpos: [14]; default: 0; + * set touch_pad14_hold + */ + +#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) +#define RTC_CNTL_TOUCH_PAD14_HOLD_M (RTC_CNTL_TOUCH_PAD14_HOLD_V << RTC_CNTL_TOUCH_PAD14_HOLD_S) +#define RTC_CNTL_TOUCH_PAD14_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD14_HOLD_S 14 + +/* RTC_CNTL_TOUCH_PAD13_HOLD : R/W; bitpos: [13]; default: 0; + * set touch_pad13_hold + */ + +#define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) +#define RTC_CNTL_TOUCH_PAD13_HOLD_M (RTC_CNTL_TOUCH_PAD13_HOLD_V << RTC_CNTL_TOUCH_PAD13_HOLD_S) +#define RTC_CNTL_TOUCH_PAD13_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD13_HOLD_S 13 + +/* RTC_CNTL_TOUCH_PAD12_HOLD : R/W; bitpos: [12]; default: 0; + * set touch_pad12_hold + */ + +#define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) +#define RTC_CNTL_TOUCH_PAD12_HOLD_M (RTC_CNTL_TOUCH_PAD12_HOLD_V << RTC_CNTL_TOUCH_PAD12_HOLD_S) +#define RTC_CNTL_TOUCH_PAD12_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD12_HOLD_S 12 + +/* RTC_CNTL_TOUCH_PAD11_HOLD : R/W; bitpos: [11]; default: 0; + * set touch_pad11_hold + */ + +#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) +#define RTC_CNTL_TOUCH_PAD11_HOLD_M (RTC_CNTL_TOUCH_PAD11_HOLD_V << RTC_CNTL_TOUCH_PAD11_HOLD_S) +#define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD11_HOLD_S 11 + +/* RTC_CNTL_TOUCH_PAD10_HOLD : R/W; bitpos: [10]; default: 0; + * set touch_pad10_hold + */ + +#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) +#define RTC_CNTL_TOUCH_PAD10_HOLD_M (RTC_CNTL_TOUCH_PAD10_HOLD_V << RTC_CNTL_TOUCH_PAD10_HOLD_S) +#define RTC_CNTL_TOUCH_PAD10_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD10_HOLD_S 10 + +/* RTC_CNTL_TOUCH_PAD9_HOLD : R/W; bitpos: [9]; default: 0; + * set touch_pad9_hold + */ + +#define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) +#define RTC_CNTL_TOUCH_PAD9_HOLD_M (RTC_CNTL_TOUCH_PAD9_HOLD_V << RTC_CNTL_TOUCH_PAD9_HOLD_S) +#define RTC_CNTL_TOUCH_PAD9_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD9_HOLD_S 9 + +/* RTC_CNTL_TOUCH_PAD8_HOLD : R/W; bitpos: [8]; default: 0; + * set touch_pad8_hold + */ + +#define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) +#define RTC_CNTL_TOUCH_PAD8_HOLD_M (RTC_CNTL_TOUCH_PAD8_HOLD_V << RTC_CNTL_TOUCH_PAD8_HOLD_S) +#define RTC_CNTL_TOUCH_PAD8_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD8_HOLD_S 8 + +/* RTC_CNTL_TOUCH_PAD7_HOLD : R/W; bitpos: [7]; default: 0; + * set touch_pad7_hold + */ + +#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_M (RTC_CNTL_TOUCH_PAD7_HOLD_V << RTC_CNTL_TOUCH_PAD7_HOLD_S) +#define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD7_HOLD_S 7 + +/* RTC_CNTL_TOUCH_PAD6_HOLD : R/W; bitpos: [6]; default: 0; + * set touch_pad6_hold + */ + +#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_M (RTC_CNTL_TOUCH_PAD6_HOLD_V << RTC_CNTL_TOUCH_PAD6_HOLD_S) +#define RTC_CNTL_TOUCH_PAD6_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD6_HOLD_S 6 + +/* RTC_CNTL_TOUCH_PAD5_HOLD : R/W; bitpos: [5]; default: 0; + * set touch_pad5_hold + */ + +#define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_M (RTC_CNTL_TOUCH_PAD5_HOLD_V << RTC_CNTL_TOUCH_PAD5_HOLD_S) +#define RTC_CNTL_TOUCH_PAD5_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD5_HOLD_S 5 + +/* RTC_CNTL_TOUCH_PAD4_HOLD : R/W; bitpos: [4]; default: 0; + * set touch_pad4_hold + */ + +#define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_M (RTC_CNTL_TOUCH_PAD4_HOLD_V << RTC_CNTL_TOUCH_PAD4_HOLD_S) +#define RTC_CNTL_TOUCH_PAD4_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD4_HOLD_S 4 + +/* RTC_CNTL_TOUCH_PAD3_HOLD : R/W; bitpos: [3]; default: 0; + * set touch_pad3_hold + */ + +#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_M (RTC_CNTL_TOUCH_PAD3_HOLD_V << RTC_CNTL_TOUCH_PAD3_HOLD_S) +#define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD3_HOLD_S 3 + +/* RTC_CNTL_TOUCH_PAD2_HOLD : R/W; bitpos: [2]; default: 0; + * set touch_pad2_hold + */ + +#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_M (RTC_CNTL_TOUCH_PAD2_HOLD_V << RTC_CNTL_TOUCH_PAD2_HOLD_S) +#define RTC_CNTL_TOUCH_PAD2_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD2_HOLD_S 2 + +/* RTC_CNTL_TOUCH_PAD1_HOLD : R/W; bitpos: [1]; default: 0; + * set touch_pad1_hold + */ + +#define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_M (RTC_CNTL_TOUCH_PAD1_HOLD_V << RTC_CNTL_TOUCH_PAD1_HOLD_S) +#define RTC_CNTL_TOUCH_PAD1_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD1_HOLD_S 1 + +/* RTC_CNTL_TOUCH_PAD0_HOLD : R/W; bitpos: [0]; default: 0; + * set touch_pad0_hold + */ + +#define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_M (RTC_CNTL_TOUCH_PAD0_HOLD_V << RTC_CNTL_TOUCH_PAD0_HOLD_S) +#define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x00000001 +#define RTC_CNTL_TOUCH_PAD0_HOLD_S 0 + +/* RTC_CNTL_DIG_PAD_HOLD_REG register + * configure digital pad hold register + */ + +#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xd8) + +/* RTC_CNTL_DIG_PAD_HOLD : R/W; bitpos: [31:0]; default: 0; + * Hold GPIO21~GPIO45 base on bitmap + */ + +#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_M (RTC_CNTL_DIG_PAD_HOLD_V << RTC_CNTL_DIG_PAD_HOLD_S) +#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_S 0 + +/* RTC_CNTL_EXT_WAKEUP1_REG register + * configure EXT1 wakeup register + */ + +#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xdc) + +/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO; bitpos: [22]; default: 0; + * clear ext wakeup1 status + */ + +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V << RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x00000001 +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 22 + +/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W; bitpos: [21:0]; default: 0; + * Bitmap to select RTC pads for ext wakeup1 + */ + +#define RTC_CNTL_EXT_WAKEUP1_SEL 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_M (RTC_CNTL_EXT_WAKEUP1_SEL_V << RTC_CNTL_EXT_WAKEUP1_SEL_S) +#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 + +/* RTC_CNTL_EXT_WAKEUP1_STATUS_REG register + * EXT1 wakeup source register + */ + +#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xe0) + +/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO; bitpos: [21:0]; default: 0; + * ext wakeup1 status + */ + +#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_M (RTC_CNTL_EXT_WAKEUP1_STATUS_V << RTC_CNTL_EXT_WAKEUP1_STATUS_S) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 + +/* RTC_CNTL_BROWN_OUT_REG register + * configure brownout register + */ + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xe4) + +/* RTC_CNTL_BROWN_OUT_DET : RO; bitpos: [31]; default: 0; + * status of brown detcet signal + */ + +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (RTC_CNTL_BROWN_OUT_DET_V << RTC_CNTL_BROWN_OUT_DET_S) +#define RTC_CNTL_BROWN_OUT_DET_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_DET_S 31 + +/* RTC_CNTL_BROWN_OUT_ENA : R/W; bitpos: [30]; default: 0; + * enable brown out + */ + +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (RTC_CNTL_BROWN_OUT_ENA_V << RTC_CNTL_BROWN_OUT_ENA_S) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 + +/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO; bitpos: [29]; default: 0; + * clear brown out counter + */ + +#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (RTC_CNTL_BROWN_OUT_CNT_CLR_V << RTC_CNTL_BROWN_OUT_CNT_CLR_S) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 + +/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W; bitpos: [27]; default: 0; + * 1: chip reset 0: sys_reset + */ + +#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_M (RTC_CNTL_BROWN_OUT_RST_SEL_V << RTC_CNTL_BROWN_OUT_RST_SEL_S) +#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 + +/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W; bitpos: [26]; default: 0; + * enable brown out reset + */ + +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (RTC_CNTL_BROWN_OUT_RST_ENA_V << RTC_CNTL_BROWN_OUT_RST_ENA_S) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 + +/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W; bitpos: [25:16]; default: 1023; + * brown out reset wait cycles + */ + +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M (RTC_CNTL_BROWN_OUT_RST_WAIT_V << RTC_CNTL_BROWN_OUT_RST_WAIT_S) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 + +/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W; bitpos: [15]; default: 0; + * enable power down RF when brown out happens + */ + +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (RTC_CNTL_BROWN_OUT_PD_RF_ENA_V << RTC_CNTL_BROWN_OUT_PD_RF_ENA_S) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 + +/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W; bitpos: [14]; default: 0; + * enable close flash when brown out happens + */ + +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V << RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x00000001 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 + +/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W; bitpos: [13:4]; default: 767; + * brown out interrupt wait cycles + */ + +#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_M (RTC_CNTL_BROWN_OUT_INT_WAIT_V << RTC_CNTL_BROWN_OUT_INT_WAIT_S) +#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x000003FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 + +/* RTC_CNTL_BROWN_OUT2_ENA : R/W; bitpos: [0]; default: 1; + * enable brown_out2 to start chip reset + */ + +#define RTC_CNTL_BROWN_OUT2_ENA (BIT(0)) +#define RTC_CNTL_BROWN_OUT2_ENA_M (RTC_CNTL_BROWN_OUT2_ENA_V << RTC_CNTL_BROWN_OUT2_ENA_S) +#define RTC_CNTL_BROWN_OUT2_ENA_V 0x00000001 +#define RTC_CNTL_BROWN_OUT2_ENA_S 0 + +/* RTC_CNTL_TIME_LOW1_REG register + * RTC timer1 low 32 bits + */ + +#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0xe8) + +/* RTC_CNTL_TIMER_VALUE1_LOW : RO; bitpos: [31:0]; default: 0; + * RTC timer low 32 bits + */ + +#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_M (RTC_CNTL_TIMER_VALUE1_LOW_V << RTC_CNTL_TIMER_VALUE1_LOW_S) +#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_S 0 + +/* RTC_CNTL_TIME_HIGH1_REG register + * RTC timer1 high 16 bits + */ + +#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0xec) + +/* RTC_CNTL_TIMER_VALUE1_HIGH : RO; bitpos: [15:0]; default: 0; + * RTC timer high 16 bits + */ + +#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_M (RTC_CNTL_TIMER_VALUE1_HIGH_V << RTC_CNTL_TIMER_VALUE1_HIGH_S) +#define RTC_CNTL_TIMER_VALUE1_HIGH_V 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 + +/* RTC_CNTL_XTAL32K_CLK_FACTOR_REG register + * configure xtal32k backup fatcor register + */ + +#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0xf0) + +/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W; bitpos: [31:0]; default: 0; + * xtal 32k watch dog backup clock factor + */ + +#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_M (RTC_CNTL_XTAL32K_CLK_FACTOR_V << RTC_CNTL_XTAL32K_CLK_FACTOR_S) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 + +/* RTC_CNTL_XTAL32K_CONF_REG register + * configure xtal32k register + */ + +#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0xf4) + +/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W; bitpos: [31:28]; default: 0; + * if restarted xtal32k period is smaller than this it is regarded as stable + */ + +#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F +#define RTC_CNTL_XTAL32K_STABLE_THRES_M (RTC_CNTL_XTAL32K_STABLE_THRES_V << RTC_CNTL_XTAL32K_STABLE_THRES_S) +#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0x0000000F +#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 + +/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W; bitpos: [27:20]; default: 255; + * If no clock detected for this amount of time 32k is regarded as dead + */ + +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M (RTC_CNTL_XTAL32K_WDT_TIMEOUT_V << RTC_CNTL_XTAL32K_WDT_TIMEOUT_S) +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0x000000FF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 + +/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W; bitpos: [19:4]; default: 0; + * cycles to wait to repower on xtal 32k + */ + +#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_M (RTC_CNTL_XTAL32K_RESTART_WAIT_V << RTC_CNTL_XTAL32K_RESTART_WAIT_S) +#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0x0000FFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 + +/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W; bitpos: [3:0]; default: 0; + * cycles to wait to return noral xtal 32k + */ + +#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F +#define RTC_CNTL_XTAL32K_RETURN_WAIT_M (RTC_CNTL_XTAL32K_RETURN_WAIT_V << RTC_CNTL_XTAL32K_RETURN_WAIT_S) +#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0x0000000F +#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 + +/* RTC_CNTL_USB_CONF_REG register + * configure usb control register + */ + +#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x11c) + +/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W; bitpos: [18]; default: 0; */ + +#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (RTC_CNTL_IO_MUX_RESET_DISABLE_V << RTC_CNTL_IO_MUX_RESET_DISABLE_S) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x00000001 +#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 + +/* RTC_CNTL_USB_RESET_DISABLE : R/W; bitpos: [17]; default: 0; */ + +#define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) +#define RTC_CNTL_USB_RESET_DISABLE_M (RTC_CNTL_USB_RESET_DISABLE_V << RTC_CNTL_USB_RESET_DISABLE_S) +#define RTC_CNTL_USB_RESET_DISABLE_V 0x00000001 +#define RTC_CNTL_USB_RESET_DISABLE_S 17 + +/* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W; bitpos: [16]; default: 0; */ + +#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) +#define RTC_CNTL_USB_TX_EN_OVERRIDE_M (RTC_CNTL_USB_TX_EN_OVERRIDE_V << RTC_CNTL_USB_TX_EN_OVERRIDE_S) +#define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x00000001 +#define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16 + +/* RTC_CNTL_USB_TX_EN : R/W; bitpos: [15]; default: 0; */ + +#define RTC_CNTL_USB_TX_EN (BIT(15)) +#define RTC_CNTL_USB_TX_EN_M (RTC_CNTL_USB_TX_EN_V << RTC_CNTL_USB_TX_EN_S) +#define RTC_CNTL_USB_TX_EN_V 0x00000001 +#define RTC_CNTL_USB_TX_EN_S 15 + +/* RTC_CNTL_USB_TXP : R/W; bitpos: [14]; default: 0; */ + +#define RTC_CNTL_USB_TXP (BIT(14)) +#define RTC_CNTL_USB_TXP_M (RTC_CNTL_USB_TXP_V << RTC_CNTL_USB_TXP_S) +#define RTC_CNTL_USB_TXP_V 0x00000001 +#define RTC_CNTL_USB_TXP_S 14 + +/* RTC_CNTL_USB_TXM : R/W; bitpos: [13]; default: 0; */ + +#define RTC_CNTL_USB_TXM (BIT(13)) +#define RTC_CNTL_USB_TXM_M (RTC_CNTL_USB_TXM_V << RTC_CNTL_USB_TXM_S) +#define RTC_CNTL_USB_TXM_V 0x00000001 +#define RTC_CNTL_USB_TXM_S 13 + +/* RTC_CNTL_USB_PAD_ENABLE : R/W; bitpos: [12]; default: 0; */ + +#define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) +#define RTC_CNTL_USB_PAD_ENABLE_M (RTC_CNTL_USB_PAD_ENABLE_V << RTC_CNTL_USB_PAD_ENABLE_S) +#define RTC_CNTL_USB_PAD_ENABLE_V 0x00000001 +#define RTC_CNTL_USB_PAD_ENABLE_S 12 + +/* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W; bitpos: [11]; default: 0; */ + +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V << RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S) +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x00000001 +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11 + +/* RTC_CNTL_USB_PULLUP_VALUE : R/W; bitpos: [10]; default: 0; */ + +#define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) +#define RTC_CNTL_USB_PULLUP_VALUE_M (RTC_CNTL_USB_PULLUP_VALUE_V << RTC_CNTL_USB_PULLUP_VALUE_S) +#define RTC_CNTL_USB_PULLUP_VALUE_V 0x00000001 +#define RTC_CNTL_USB_PULLUP_VALUE_S 10 + +/* RTC_CNTL_USB_DM_PULLDOWN : R/W; bitpos: [9]; default: 0; */ + +#define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) +#define RTC_CNTL_USB_DM_PULLDOWN_M (RTC_CNTL_USB_DM_PULLDOWN_V << RTC_CNTL_USB_DM_PULLDOWN_S) +#define RTC_CNTL_USB_DM_PULLDOWN_V 0x00000001 +#define RTC_CNTL_USB_DM_PULLDOWN_S 9 + +/* RTC_CNTL_USB_DM_PULLUP : R/W; bitpos: [8]; default: 0; */ + +#define RTC_CNTL_USB_DM_PULLUP (BIT(8)) +#define RTC_CNTL_USB_DM_PULLUP_M (RTC_CNTL_USB_DM_PULLUP_V << RTC_CNTL_USB_DM_PULLUP_S) +#define RTC_CNTL_USB_DM_PULLUP_V 0x00000001 +#define RTC_CNTL_USB_DM_PULLUP_S 8 + +/* RTC_CNTL_USB_DP_PULLDOWN : R/W; bitpos: [7]; default: 0; */ + +#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) +#define RTC_CNTL_USB_DP_PULLDOWN_M (RTC_CNTL_USB_DP_PULLDOWN_V << RTC_CNTL_USB_DP_PULLDOWN_S) +#define RTC_CNTL_USB_DP_PULLDOWN_V 0x00000001 +#define RTC_CNTL_USB_DP_PULLDOWN_S 7 + +/* RTC_CNTL_USB_DP_PULLUP : R/W; bitpos: [6]; default: 0; */ + +#define RTC_CNTL_USB_DP_PULLUP (BIT(6)) +#define RTC_CNTL_USB_DP_PULLUP_M (RTC_CNTL_USB_DP_PULLUP_V << RTC_CNTL_USB_DP_PULLUP_S) +#define RTC_CNTL_USB_DP_PULLUP_V 0x00000001 +#define RTC_CNTL_USB_DP_PULLUP_S 6 + +/* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W; bitpos: [5]; default: 0; */ + +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M (RTC_CNTL_USB_PAD_PULL_OVERRIDE_V << RTC_CNTL_USB_PAD_PULL_OVERRIDE_S) +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V 0x00000001 +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S 5 + +/* RTC_CNTL_USB_VREF_OVERRIDE : R/W; bitpos: [4]; default: 0; */ + +#define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) +#define RTC_CNTL_USB_VREF_OVERRIDE_M (RTC_CNTL_USB_VREF_OVERRIDE_V << RTC_CNTL_USB_VREF_OVERRIDE_S) +#define RTC_CNTL_USB_VREF_OVERRIDE_V 0x00000001 +#define RTC_CNTL_USB_VREF_OVERRIDE_S 4 + +/* RTC_CNTL_USB_VREFL : R/W; bitpos: [3:2]; default: 0; */ + +#define RTC_CNTL_USB_VREFL 0x00000003 +#define RTC_CNTL_USB_VREFL_M (RTC_CNTL_USB_VREFL_V << RTC_CNTL_USB_VREFL_S) +#define RTC_CNTL_USB_VREFL_V 0x00000003 +#define RTC_CNTL_USB_VREFL_S 2 + +/* RTC_CNTL_USB_VREFH : R/W; bitpos: [1:0]; default: 0; */ + +#define RTC_CNTL_USB_VREFH 0x00000003 +#define RTC_CNTL_USB_VREFH_M (RTC_CNTL_USB_VREFH_V << RTC_CNTL_USB_VREFH_S) +#define RTC_CNTL_USB_VREFH_V 0x00000003 +#define RTC_CNTL_USB_VREFH_S 0 + +/* RTC_CNTL_SLP_REJECT_CAUSE_REG register + * sleep reject casue register + */ + +#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x124) + +/* RTC_CNTL_REJECT_CAUSE : RO; bitpos: [16:0]; default: 0; + * sleep reject cause + */ + +#define RTC_CNTL_REJECT_CAUSE 0x0001FFFF +#define RTC_CNTL_REJECT_CAUSE_M (RTC_CNTL_REJECT_CAUSE_V << RTC_CNTL_REJECT_CAUSE_S) +#define RTC_CNTL_REJECT_CAUSE_V 0x0001FFFF +#define RTC_CNTL_REJECT_CAUSE_S 0 + +/* RTC_CNTL_OPTION1_REG register + * configure rtc option + */ + +#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x128) + +/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [0]; default: 0; + * force chip boot from download mode + */ + +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (RTC_CNTL_FORCE_DOWNLOAD_BOOT_V << RTC_CNTL_FORCE_DOWNLOAD_BOOT_S) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x00000001 +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 + +/* RTC_CNTL_SLP_WAKEUP_CAUSE_REG register + * sleep wakeup cause state register + */ + +#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x12c) + +/* RTC_CNTL_WAKEUP_CAUSE : RO; bitpos: [16:0]; default: 0; + * sleep wakeup cause + */ + +#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE_M (RTC_CNTL_WAKEUP_CAUSE_V << RTC_CNTL_WAKEUP_CAUSE_S) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +/* RTC_CNTL_DATE_REG register */ + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x138) + +/* RTC_CNTL_CNTL_DATE : R/W; bitpos: [27:0]; default: 26239377; */ + +#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_M (RTC_CNTL_CNTL_DATE_V << RTC_CNTL_CNTL_DATE_S) +#define RTC_CNTL_CNTL_DATE_V 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTC_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h new file mode 100644 index 0000000000..e6a5f94db8 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h @@ -0,0 +1,786 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H +#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "xtensa_attr.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Bits */ + +#define BIT31 0x80000000 +#define BIT30 0x40000000 +#define BIT29 0x20000000 +#define BIT28 0x10000000 +#define BIT27 0x08000000 +#define BIT26 0x04000000 +#define BIT25 0x02000000 +#define BIT24 0x01000000 +#define BIT23 0x00800000 +#define BIT22 0x00400000 +#define BIT21 0x00200000 +#define BIT20 0x00100000 +#define BIT19 0x00080000 +#define BIT18 0x00040000 +#define BIT17 0x00020000 +#define BIT16 0x00010000 +#define BIT15 0x00008000 +#define BIT14 0x00004000 +#define BIT13 0x00002000 +#define BIT12 0x00001000 +#define BIT11 0x00000800 +#define BIT10 0x00000400 +#define BIT9 0x00000200 +#define BIT8 0x00000100 +#define BIT7 0x00000080 +#define BIT6 0x00000040 +#define BIT5 0x00000020 +#define BIT4 0x00000010 +#define BIT3 0x00000008 +#define BIT2 0x00000004 +#define BIT1 0x00000002 +#define BIT0 0x00000001 + +#define PRO_CPU_NUM (0) + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) /* Largest span of contiguous memory (DRAM or IRAM) in the address space */ + +/* Registers Operation */ + +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#define BIT(nr) (1UL << (nr)) + +/* Write value to register */ + +#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +/* Read value from register */ + +#define REG_READ(_r) (*(volatile uint32_t *)(_r)) + +/* Get bit or get bits from register */ + +#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b)) + +/* Set bit or set bits to register */ + +#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b)) + +/* Clear bit or clear bits of register */ + +#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b)) + +/* Set bits of register controlled by mask */ + +#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))) + +/* Get field from register, + * used when _f is not left shifted by _f##_S + */ + +#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +/* Set field to register, + * used when _f is not left shifted by _f##_S + */ + +#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))) + +/* Set field value from a variable, + * used when _f is not left shifted by _f##_S + */ + +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +/* Get field value from a variable, + * used when _f is left shifted by _f##_S + */ + +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +/* Set field value to a variable, + * used when _f is not left shifted by _f##_S + */ + +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +/* Set field value to a variable, + * used when _f is left shifted by _f##_S + */ + +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +/* Generate a value from a field value, + * used when _f is not left shifted by _f##_S + */ + +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +/* Generate a value from a field value, + * used when _f is left shifted by _f##_S + */ + +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +/* Read value from register */ + +#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) + +/* Write value to register */ + +#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) + +/* Clear bits of register controlled by mask */ + +#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) + +/* Set bits of register controlled by mask */ + +#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) + +/* Get bits of register controlled by mask */ + +#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask)) + +/* Get bits of register controlled by highest bit and lowest bit */ + +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +/* Set bits of register controlled by mask and shift */ + +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )) + +/* Get field of register */ + +#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask)) + +/* Extract the field from the register and shift it to avoid wrong reading */ + +#define REG_MASK(_reg, _field) ((_reg & (_field##_M)) >> (_field##_S)) + +/* Helper to place a value in a field */ + +#define VALUE_TO_FIELD(_value, _field) ((_value << (_field##_S)) & (_field##_M)) + +/* Periheral Clock */ + +#define APB_CLK_FREQ_ROM 40 * 1000000 +#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define UART_CLK_FREQ_ROM APB_CLK_FREQ_ROM +#define CPU_CLK_FREQ APB_CLK_FREQ +#define APB_CLK_FREQ 80 * 1000000 /* Unit: Hz */ +#define REF_CLK_FREQ (1000000) +#define UART_CLK_FREQ APB_CLK_FREQ +#define MWDT_CLK_FREQ APB_CLK_FREQ +#define TIMER_CLK_FREQ (80000000 >> 4) /* 80MHz divided by 16 */ +#define SPI_CLK_DIV 4 +#define TICKS_PER_US_ROM 40 /* CPU is 80MHz */ + +#define DR_REG_SYSTEM_BASE 0x3f4c0000 +#define DR_REG_SENSITIVE_BASE 0x3f4c1000 +#define DR_REG_INTERRUPT_BASE 0x3f4c2000 +#define DR_REG_DMA_COPY_BASE 0x3f4c3000 +#define DR_REG_EXTMEM_BASE 0x61800000 +#define DR_REG_MMU_TABLE 0x61801000 +#define DR_REG_ITAG_TABLE 0x61802000 +#define DR_REG_DTAG_TABLE 0x61803000 +#define DR_REG_AES_BASE 0x6003a000 +#define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_RSA_BASE 0x6003c000 +#define DR_REG_HMAC_BASE 0x6003e000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define DR_REG_CRYPTO_DMA_BASE 0x6003f000 +#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000 +#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000 +#define DR_REG_INTRUSION_BASE 0x3f4d0000 +#define DR_REG_DPORT_END 0x3f4d3FFC +#define DR_REG_UART_BASE 0x3f400000 +#define DR_REG_SPI1_BASE 0x3f402000 +#define DR_REG_SPI0_BASE 0x3f403000 +#define DR_REG_GPIO_BASE 0x3f404000 +#define DR_REG_GPIO_SD_BASE 0x3f404f00 +#define DR_REG_FE2_BASE 0x3f405000 +#define DR_REG_FE_BASE 0x3f406000 +#define DR_REG_FRC_TIMER_BASE 0x3f407000 +#define DR_REG_RTCCNTL_BASE 0x3f408000 +#define DR_REG_RTCIO_BASE 0x3f408400 +#define DR_REG_SENS_BASE 0x3f408800 +#define DR_REG_RTC_I2C_BASE 0x3f408C00 +#define DR_REG_IO_MUX_BASE 0x3f409000 +#define DR_REG_HINF_BASE 0x3f40B000 +#define DR_REG_I2S_BASE 0x3f40F000 +#define DR_REG_UART1_BASE 0x3f410000 +#define DR_REG_I2C_EXT_BASE 0x3f413000 +#define DR_REG_UHCI0_BASE 0x3f414000 +#define DR_REG_SLCHOST_BASE 0x3f415000 +#define DR_REG_RMT_BASE 0x3f416000 +#define DR_REG_PCNT_BASE 0x3f417000 +#define DR_REG_SLC_BASE 0x3f418000 +#define DR_REG_LEDC_BASE 0x3f419000 +#define DR_REG_CP_BASE 0x3f4c3000 +#define DR_REG_EFUSE_BASE 0x3f41A000 +#define DR_REG_NRX_BASE 0x3f41CC00 +#define DR_REG_BB_BASE 0x3f41D000 +#define DR_REG_TIMERGROUP0_BASE 0x3f41F000 +#define DR_REG_TIMERGROUP1_BASE 0x3f420000 +#define DR_REG_RTC_SLOWMEM_BASE 0x3f421000 +#define DR_REG_SYSTIMER_BASE 0x3f423000 +#define DR_REG_SPI2_BASE 0x3f424000 +#define DR_REG_SPI3_BASE 0x3f425000 +#define DR_REG_SYSCON_BASE 0x3f426000 +#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */ +#define DR_REG_I2C1_EXT_BASE 0x3f427000 +#define DR_REG_SPI4_BASE 0x3f437000 +#define DR_REG_USB_WRAP_BASE 0x3f439000 +#define DR_REG_APB_SARADC_BASE 0x3f440000 +#define DR_REG_USB_BASE 0x60080000 + +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) +#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000 ) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 ) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) +#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) + +/* Registers Operation */ + +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) + +/* Overall memory map */ + +#define SOC_DROM_LOW 0x3f000000 /* drom0 low address for icache */ +#define SOC_DROM_HIGH 0x3ff80000 /* dram0 high address for dcache */ +#define SOC_IROM_LOW 0x40080000 +#define SOC_IROM_HIGH 0x40800000 +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x40020000 +#define SOC_IRAM_LOW 0x40020000 +#define SOC_IRAM_HIGH 0x40070000 +#define SOC_DRAM_LOW 0x3ffb0000 +#define SOC_DRAM_HIGH 0x40000000 +#define SOC_RTC_IRAM_LOW 0x40070000 +#define SOC_RTC_IRAM_HIGH 0x40072000 +#define SOC_RTC_DRAM_LOW 0x3ff9e000 +#define SOC_RTC_DRAM_HIGH 0x3ffa0000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50002000 +#define SOC_EXTRAM_DATA_LOW 0x3f500000 +#define SOC_EXTRAM_DATA_HIGH 0x3ff80000 + +/* Virtual address 0 */ + +#define VADDR0_START_ADDR SOC_DROM_LOW +#define VADDR0_END_ADDR (SOC_DROM_HIGH - 1) + +/* Interrupt hardware source table + * This table is decided by hardware, don't touch this. + */ + +#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) +#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038) + +/* Interrupt cpu using table */ + +/**************************************************************************** + *Intr num Level Type PRO CPU usage APP CPU uasge + * 0 1 extern level WMAC Reserved + * 1 1 extern level BT/BLE Host VHCI Reserved + * 2 1 extern level FROM_CPU FROM_CPU + * 3 1 extern level TG0_WDT Reserved + * 4 1 extern level WBB + * 5 1 extern level BT Controller + * 6 1 timer RTOS Tick RTOS Tick + * 7 1 software Reserved Reserved + * 8 1 extern level BLE Controller + * 9 1 extern level + * 10 1 extern edge Internal Timer + * 11 3 profiling + * 12 1 extern level + * 13 1 extern level + * 14 7 nmi Reserved Reserved + * 15 3 timer Internal Timer + * 16 5 timer + * 17 1 extern level + * 18 1 extern level + * 19 2 extern level + * 20 2 extern level + * 21 2 extern level + * 22 3 extern edge + * 23 3 extern level + * 24 4 extern level + * 25 4 extern level Reserved Reserved + * 26 5 extern level Reserved Reserved + * 27 3 extern level Reserved Reserved + * 28 4 extern edge + * 29 3 software Reserved Reserved + * 30 4 extern edge Reserved Reserved + * 31 5 extern level Reserved Reserved + ****************************************************************************/ + +/* CPU0 Interrupt number reserved, not touch this. */ + +#define ETS_WMAC_INUM 0 +#define ETS_BT_HOST_INUM 1 +#define ETS_FROM_CPU_INUM 2 +#define ETS_T0_WDT_INUM 3 +#define ETS_WBB_INUM 4 +#define ETS_TG0_T1_INUM 10 /* Use edge interrupt */ + +/* CPU0 Interrupt number used in ROM, should be cancelled in SDK */ + +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 + +/* Other interrupt numbers should be managed by the user */ + +#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0) +#define APB_CTRL_XTAL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4) + +/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ + +#define APB_CTRL_PRE_DIV_CNT 0x000003ff +#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V) << \ + (APB_CTRL_PRE_DIV_CNT_S)) +#define APB_CTRL_PRE_DIV_CNT_V 0x3ff +#define APB_CTRL_PRE_DIV_CNT_S 0 + +#define I2C_BBPLL_IR_CAL_DELAY 0 +#define I2C_BBPLL_IR_CAL_EXT_CAP 1 +#define I2C_BBPLL_OC_ENB_FCAL 4 +#define I2C_BBPLL_OC_ENB_VCON 10 +#define I2C_BBPLL_BBADC_CAL_7_0 12 + +#define I2C_BBPLL_OC_LREF 2 +#define I2C_BBPLL_OC_LREF_MSB 7 +#define I2C_BBPLL_OC_LREF_LSB 7 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#define I2C_BBPLL_BBADC_DSMP 9 +#define I2C_BBPLL_BBADC_DSMP_MSB 7 +#define I2C_BBPLL_BBADC_DSMP_LSB 4 + +#define I2C_BBPLL_OC_DCUR 5 +#define I2C_BBPLL_OC_DCUR_MSB 2 +#define I2C_BBPLL_OC_DCUR_LSB 0 + +#define I2C_BBPLL_ENDIV5 11 + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 4 + +extern int rom_i2c_writereg(int block, int block_id, int reg_add, + int indata); + +#define I2C_WRITEREG_RTC(block, reg_add, indata) \ + rom_i2c_writereg(block, block##_HOSTID, reg_add, indata) + +#define I2C_READREG_RTC(block, reg_add) \ + rom_i2c_readreg(block, block##_HOSTID, reg_add) + +#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \ + rom_i2c_writereg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata) + +#define I2C_READREG_MASK_RTC(block, reg_add) \ + rom_i2c_readreg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB) + +/* BBPLL configuration values */ + +#define BBPLL_ENDIV5_VAL_320M 0x43 +#define BBPLL_BBADC_DSMP_VAL_320M 0x84 +#define BBPLL_ENDIV5_VAL_480M 0xc3 +#define BBPLL_BBADC_DSMP_VAL_480M 0x74 + +#define BBPLL_IR_CAL_DELAY_VAL 0x18 +#define BBPLL_IR_CAL_EXT_CAP_VAL 0x20 +#define BBPLL_OC_ENB_FCAL_VAL 0x9a +#define BBPLL_OC_ENB_VCON_VAL 0x00 +#define BBPLL_BBADC_CAL_7_0_VAL 0x00 + +#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) + +/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */ + +/* description: This field stores the voltage level for + * CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. + * 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) + */ + +#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03 +#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V) << (EFUSE_RD_VOL_LEVEL_HP_INV_S)) +#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 +#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 + +/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */ + +/* description: read for sdio_force */ + +#define EFUSE_RD_SDIO_FORCE (BIT(16)) +#define EFUSE_RD_SDIO_FORCE_M (BIT(16)) +#define EFUSE_RD_SDIO_FORCE_V 0x1 +#define EFUSE_RD_SDIO_FORCE_S 16 + +/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */ + +/* description: read for XPD_SDIO_REG */ + +#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) +#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) +#define EFUSE_RD_XPD_SDIO_REG_V 0x1 +#define EFUSE_RD_XPD_SDIO_REG_S 14 + +/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */ + +/* description: read for SDIO_TIEH */ + +#define EFUSE_RD_SDIO_TIEH (BIT(15)) +#define EFUSE_RD_SDIO_TIEH_M (BIT(15)) +#define EFUSE_RD_SDIO_TIEH_V 0x1 +#define EFUSE_RD_SDIO_TIEH_S 15 + +/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ + +/* description: If set, this bit indicates that + * BLOCK3[143:96] is reserved for internal use + */ + +#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) +#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V) << (EFUSE_RD_BLK3_PART_RESERVE_S)) +#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1 +#define EFUSE_RD_BLK3_PART_RESERVE_S 14 + +/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */ + +#define EFUSE_RD_SDIO_DREFH 0x00000003 +#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V) << (EFUSE_RD_SDIO_DREFH_S)) +#define EFUSE_RD_SDIO_DREFH_V 0x3 +#define EFUSE_RD_SDIO_DREFH_S 8 + +/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */ + +#define EFUSE_RD_SDIO_DREFM 0x00000003 +#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V) << (EFUSE_RD_SDIO_DREFM_S)) +#define EFUSE_RD_SDIO_DREFM_V 0x3 +#define EFUSE_RD_SDIO_DREFM_S 10 + +/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. + * Newer versions of ESP32 come with EFUSE_ADC_VREF already burned, + * therefore SDIO_DREFH/M/L is only available in older versions of ESP32 + */ + +/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */ + +#define EFUSE_RD_SDIO_DREFL 0x00000003 +#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V) << (EFUSE_RD_SDIO_DREFL_S)) +#define EFUSE_RD_SDIO_DREFL_V 0x3 +#define EFUSE_RD_SDIO_DREFL_S 12 + +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) + +#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG + +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ + +#define RTC_CNTL_DBIAS_1V00 2 +#define RTC_CNTL_DBIAS_1V10 4 +#define RTC_CNTL_DBIAS_1V25 7 + +/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; + * description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL + */ + +#define RTC_CNTL_SOC_CLK_SEL 0x00000003 +#define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V) << (RTC_CNTL_SOC_CLK_SEL_S)) +#define RTC_CNTL_SOC_CLK_SEL_V 0x3 +#define RTC_CNTL_SOC_CLK_SEL_S 27 +#define RTC_CNTL_SOC_CLK_SEL_XTL 0 +#define RTC_CNTL_SOC_CLK_SEL_PLL 1 +#define RTC_CNTL_SOC_CLK_SEL_8M 2 +#define RTC_CNTL_SOC_CLK_SEL_APLL 3 + +/* Core voltage needs to be increased in two cases: + * 1. running at 240 MHz + * 2. running with 80MHz Flash frequency + * There is a record in efuse which indicates the + * proper voltage for these two cases. + */ + +#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - \ + (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, \ + EFUSE_RD_VOL_LEVEL_HP_INV))) + +#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M +#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT +#else +#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10 +#endif +#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT +#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 +#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 + +#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT +#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 +#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 + +#define DELAY_PLL_DBIAS_RAISE 3 +#define DELAY_PLL_ENABLE_WITH_150K 80 +#define DELAY_PLL_ENABLE_WITH_32K 160 + +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; + * description: BB_I2C force power down + */ + +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) + +/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; + * description: BB_PLL force power down + */ + +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) + +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; + * description: BB_PLL _I2C force power down + */ + +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) + +/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; + * description: PLLA force power down + */ + +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_S 23 + +/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; + * description: BIAS_I2C force power down + */ + +#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18)) + +#define MHZ (1000000) +#define RTC_PLL_FREQ_320M 320 +#define RTC_PLL_FREQ_480M 480 + +/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ + +#define TIMG_RTC_CALI_CLK_SEL 0x00000003 +#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V) << (TIMG_RTC_CALI_CLK_SEL_S)) +#define TIMG_RTC_CALI_CLK_SEL_V 0x3 +#define TIMG_RTC_CALI_CLK_SEL_S 13 + +/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */ + +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_V 0x1 +#define TIMG_RTC_CALI_START_CYCLING_S 12 + +/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (BIT(31)) +#define TIMG_RTC_CALI_START_V 0x1 +#define TIMG_RTC_CALI_START_S 31 + +/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */ + +#define TIMG_RTC_CALI_MAX 0x00007fff +#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V) << (TIMG_RTC_CALI_MAX_S)) +#define TIMG_RTC_CALI_MAX_V 0x7fff +#define TIMG_RTC_CALI_MAX_S 16 + +/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */ + +#define TIMG_RTC_CALI_VALUE 0x01ffffff +#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V) << (TIMG_RTC_CALI_VALUE_S)) +#define TIMG_RTC_CALI_VALUE_V 0x1ffffff +#define TIMG_RTC_CALI_VALUE_S 7 + +/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */ + +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (BIT(15)) +#define TIMG_RTC_CALI_RDY_V 0x1 +#define TIMG_RTC_CALI_RDY_S 15 + +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c) + +/* Some of the baseband control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054) +#define BB_FFT_FORCE_PU (BIT(3)) +#define BB_FFT_FORCE_PU_M (BIT(3)) +#define BB_FFT_FORCE_PU_V 1 +#define BB_FFT_FORCE_PU_S 3 +#define BB_FFT_FORCE_PD (BIT(2)) +#define BB_FFT_FORCE_PD_M (BIT(2)) +#define BB_FFT_FORCE_PD_V 1 +#define BB_FFT_FORCE_PD_S 2 +#define BB_DC_EST_FORCE_PU (BIT(1)) +#define BB_DC_EST_FORCE_PU_M (BIT(1)) +#define BB_DC_EST_FORCE_PU_V 1 +#define BB_DC_EST_FORCE_PU_S 1 +#define BB_DC_EST_FORCE_PD (BIT(0)) +#define BB_DC_EST_FORCE_PD_M (BIT(0)) +#define BB_DC_EST_FORCE_PD_V 1 +#define BB_DC_EST_FORCE_PD_S 0 + +/* Some of the WiFi RX control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4) +#define NRX_RX_ROT_FORCE_PU (BIT(5)) +#define NRX_RX_ROT_FORCE_PU_M (BIT(5)) +#define NRX_RX_ROT_FORCE_PU_V 1 +#define NRX_RX_ROT_FORCE_PU_S 5 +#define NRX_RX_ROT_FORCE_PD (BIT(4)) +#define NRX_RX_ROT_FORCE_PD_M (BIT(4)) +#define NRX_RX_ROT_FORCE_PD_V 1 +#define NRX_RX_ROT_FORCE_PD_S 4 +#define NRX_VIT_FORCE_PU (BIT(3)) +#define NRX_VIT_FORCE_PU_M (BIT(3)) +#define NRX_VIT_FORCE_PU_V 1 +#define NRX_VIT_FORCE_PU_S 3 +#define NRX_VIT_FORCE_PD (BIT(2)) +#define NRX_VIT_FORCE_PD_M (BIT(2)) +#define NRX_VIT_FORCE_PD_V 1 +#define NRX_VIT_FORCE_PD_S 2 +#define NRX_DEMAP_FORCE_PU (BIT(1)) +#define NRX_DEMAP_FORCE_PU_M (BIT(1)) +#define NRX_DEMAP_FORCE_PU_V 1 +#define NRX_DEMAP_FORCE_PU_S 1 +#define NRX_DEMAP_FORCE_PD (BIT(0)) +#define NRX_DEMAP_FORCE_PD_M (BIT(0)) +#define NRX_DEMAP_FORCE_PD_V 1 +#define NRX_DEMAP_FORCE_PD_S 0 + +/* Some of the RF frontend control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090) +#define FE_IQ_EST_FORCE_PU (BIT(5)) +#define FE_IQ_EST_FORCE_PU_M (BIT(5)) +#define FE_IQ_EST_FORCE_PU_V 1 +#define FE_IQ_EST_FORCE_PU_S 5 +#define FE_IQ_EST_FORCE_PD (BIT(4)) +#define FE_IQ_EST_FORCE_PD_M (BIT(4)) +#define FE_IQ_EST_FORCE_PD_V 1 +#define FE_IQ_EST_FORCE_PD_S 4 + +#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0) +#define FE2_TX_INF_FORCE_PU (BIT(10)) +#define FE2_TX_INF_FORCE_PU_M (BIT(10)) +#define FE2_TX_INF_FORCE_PU_V 1 +#define FE2_TX_INF_FORCE_PU_S 10 +#define FE2_TX_INF_FORCE_PD (BIT(9)) +#define FE2_TX_INF_FORCE_PD_M (BIT(9)) +#define FE2_TX_INF_FORCE_PD_V 1 +#define FE2_TX_INF_FORCE_PD_S 9 + +/* RO data page in MMU index */ + +#define DROM0_PAGES_START 0 +#define DROM0_PAGES_END 64 + +#define IROM0_PAGES_START 64 +#define IROM0_PAGES_END 256 + +/* MMU invalid value */ + +#define INVALID_MMU_VAL 0x100 + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_sp_dram + * + * Description: + * Check if the stack pointer is in DRAM. + * + ****************************************************************************/ + +static inline bool IRAM_ATTR esp32s2_sp_dram(uint32_t sp) +{ + return (sp >= SOC_DRAM_LOW + 0x10 && sp < SOC_DRAM_HIGH - 0x10); +} + +/**************************************************************************** + * Name: esp32s2_ptr_extram + * + * Description: + * Check if the buffer comes from the external RAM + * + ****************************************************************************/ + +static inline bool IRAM_ATTR esp32s2_ptr_extram(const void *p) +{ + return ((intptr_t)p >= SOC_EXTRAM_DATA_LOW && + (intptr_t)p < SOC_EXTRAM_DATA_HIGH); +} + +/**************************************************************************** + * Name: esp32s2_ptr_exec + * + * Description: + * Check if the pointer is within an executable range. + * + ****************************************************************************/ + +static inline bool IRAM_ATTR esp32s2_ptr_exec(const void *p) +{ + intptr_t ip = (intptr_t)p; + return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH) + || (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH) + || (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH) +#if defined(SOC_CACHE_APP_LOW) && !defined(CONFIG_SMP) + || (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH) +#endif + || (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH); +} + +#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h new file mode 100644 index 0000000000..1fa5538c47 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h @@ -0,0 +1,3139 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_spi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SPI_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SPI_CMD_REG register */ + +#define SPI_CMD_REG (DR_REG_SPI_BASE + 0x0) + +/* SPI_USR : R/W; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit + * is set. The bit will be cleared once the operation done.1: enable 0: + * disable. Can not be changed by CONF_buf. + */ + +#define SPI_USR (BIT(24)) +#define SPI_USR_M (SPI_USR_V << SPI_USR_S) +#define SPI_USR_V 0x00000001 +#define SPI_USR_S 24 + +/* SPI_CONF_BITLEN : R/W; bitpos: [22:0]; default: 104; + * Define the spi_clk cycles of SPI_CONF state. + */ + +#define SPI_CONF_BITLEN 0x007FFFFF +#define SPI_CONF_BITLEN_M (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S) +#define SPI_CONF_BITLEN_V 0x007FFFFF +#define SPI_CONF_BITLEN_S 0 + +/* SPI_ADDR_REG register */ + +#define SPI_ADDR_REG (DR_REG_SPI_BASE + 0x4) + +/* SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * [31:8]:address to slave, [7:0]:Reserved. + */ + +#define SPI_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_USR_ADDR_VALUE_M (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S) +#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_USR_ADDR_VALUE_S 0 + +/* SPI_CTRL_REG register */ + +#define SPI_CTRL_REG (DR_REG_SPI_BASE + 0x8) + +/* SPI_WR_BIT_ORDER : R/W; bitpos: [26]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first + */ + +#define SPI_WR_BIT_ORDER (BIT(26)) +#define SPI_WR_BIT_ORDER_M (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S) +#define SPI_WR_BIT_ORDER_V 0x00000001 +#define SPI_WR_BIT_ORDER_S 26 + +/* SPI_RD_BIT_ORDER : R/W; bitpos: [25]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first + */ + +#define SPI_RD_BIT_ORDER (BIT(25)) +#define SPI_RD_BIT_ORDER_M (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S) +#define SPI_RD_BIT_ORDER_V 0x00000001 +#define SPI_RD_BIT_ORDER_S 25 + +/* SPI_WP_REG : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output + * low. + */ + +#define SPI_WP_REG (BIT(21)) +#define SPI_WP_REG_M (SPI_WP_REG_V << SPI_WP_REG_S) +#define SPI_WP_REG_V 0x00000001 +#define SPI_WP_REG_S 21 + +/* SPI_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low + */ + +#define SPI_D_POL (BIT(19)) +#define SPI_D_POL_M (SPI_D_POL_V << SPI_D_POL_S) +#define SPI_D_POL_V 0x00000001 +#define SPI_D_POL_S 19 + +/* SPI_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low + */ + +#define SPI_Q_POL (BIT(18)) +#define SPI_Q_POL_M (SPI_Q_POL_V << SPI_Q_POL_S) +#define SPI_Q_POL_V 0x00000001 +#define SPI_Q_POL_S 18 + +/* SPI_FREAD_OCT : R/W; bitpos: [16]; default: 0; + * In the read operations read-data phase apply 8 signals. 1: enable 0: + * disable. + */ + +#define SPI_FREAD_OCT (BIT(16)) +#define SPI_FREAD_OCT_M (SPI_FREAD_OCT_V << SPI_FREAD_OCT_S) +#define SPI_FREAD_OCT_V 0x00000001 +#define SPI_FREAD_OCT_S 16 + +/* SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: + * disable. + */ + +#define SPI_FREAD_QUAD (BIT(15)) +#define SPI_FREAD_QUAD_M (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S) +#define SPI_FREAD_QUAD_V 0x00000001 +#define SPI_FREAD_QUAD_S 15 + +/* SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: + * disable. + */ + +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S) +#define SPI_FREAD_DUAL_V 0x00000001 +#define SPI_FREAD_DUAL_S 14 + +/* SPI_FCMD_OCT : R/W; bitpos: [10]; default: 0; + * Apply 8 signals during command phase 1:enable 0: disable + */ + +#define SPI_FCMD_OCT (BIT(10)) +#define SPI_FCMD_OCT_M (SPI_FCMD_OCT_V << SPI_FCMD_OCT_S) +#define SPI_FCMD_OCT_V 0x00000001 +#define SPI_FCMD_OCT_S 10 + +/* SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable + */ + +#define SPI_FCMD_QUAD (BIT(9)) +#define SPI_FCMD_QUAD_M (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S) +#define SPI_FCMD_QUAD_V 0x00000001 +#define SPI_FCMD_QUAD_S 9 + +/* SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable + */ + +#define SPI_FCMD_DUAL (BIT(8)) +#define SPI_FCMD_DUAL_M (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S) +#define SPI_FCMD_DUAL_V 0x00000001 +#define SPI_FCMD_DUAL_S 8 + +/* SPI_FADDR_OCT : R/W; bitpos: [7]; default: 0; + * Apply 8 signals during addr phase 1:enable 0: disable + */ + +#define SPI_FADDR_OCT (BIT(7)) +#define SPI_FADDR_OCT_M (SPI_FADDR_OCT_V << SPI_FADDR_OCT_S) +#define SPI_FADDR_OCT_V 0x00000001 +#define SPI_FADDR_OCT_S 7 + +/* SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable + */ + +#define SPI_FADDR_QUAD (BIT(6)) +#define SPI_FADDR_QUAD_M (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S) +#define SPI_FADDR_QUAD_V 0x00000001 +#define SPI_FADDR_QUAD_S 6 + +/* SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable + */ + +#define SPI_FADDR_DUAL (BIT(5)) +#define SPI_FADDR_DUAL_M (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S) +#define SPI_FADDR_DUAL_V 0x00000001 +#define SPI_FADDR_DUAL_S 5 + +/* SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0; + * In the dummy phase the signal level of spi is output by the spi + * controller. + */ + +#define SPI_DUMMY_OUT (BIT(3)) +#define SPI_DUMMY_OUT_M (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S) +#define SPI_DUMMY_OUT_V 0x00000001 +#define SPI_DUMMY_OUT_S 3 + +/* SPI_EXT_HOLD_EN : R/W; bitpos: [2]; default: 0; + * Set the bit to hold spi. The bit is combined with + * spi_usr_prep_hold,spi_usr_cmd_hold,spi_usr_addr_hold, spi_usr_dummy_hold, + * spi_usr_din_hold,spi_usr_dout_hold and spi_usr_hold_pol. + */ + +#define SPI_EXT_HOLD_EN (BIT(2)) +#define SPI_EXT_HOLD_EN_M (SPI_EXT_HOLD_EN_V << SPI_EXT_HOLD_EN_S) +#define SPI_EXT_HOLD_EN_V 0x00000001 +#define SPI_EXT_HOLD_EN_S 2 + +/* SPI_CTRL1_REG register */ + +#define SPI_CTRL1_REG (DR_REG_SPI_BASE + 0xc) + +/* SPI_CS_HOLD_DELAY : R/W; bitpos: [19:14]; default: 1; + * SPI cs signal is delayed by spi clock cycles. + */ + +#define SPI_CS_HOLD_DELAY 0x0000003F +#define SPI_CS_HOLD_DELAY_M (SPI_CS_HOLD_DELAY_V << SPI_CS_HOLD_DELAY_S) +#define SPI_CS_HOLD_DELAY_V 0x0000003F +#define SPI_CS_HOLD_DELAY_S 14 + +/* SPI_W16_17_WR_ENA : R/W; bitpos: [4]; default: 1; + * 1:reg_buf[16] [17] can be written 0:reg_buf[16] [17] can not be + * written. + */ + +#define SPI_W16_17_WR_ENA (BIT(4)) +#define SPI_W16_17_WR_ENA_M (SPI_W16_17_WR_ENA_V << SPI_W16_17_WR_ENA_S) +#define SPI_W16_17_WR_ENA_V 0x00000001 +#define SPI_W16_17_WR_ENA_S 4 + +/* SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at + * rsck posedge 0: output data at tsck posedge + */ + +#define SPI_RSCK_DATA_OUT (BIT(3)) +#define SPI_RSCK_DATA_OUT_M (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S) +#define SPI_RSCK_DATA_OUT_V 0x00000001 +#define SPI_RSCK_DATA_OUT_S 3 + +/* SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data + * B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data + * B[1]/B[6]. + */ + +#define SPI_CLK_MODE_13 (BIT(2)) +#define SPI_CLK_MODE_13_M (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S) +#define SPI_CLK_MODE_13_V 0x00000001 +#define SPI_CLK_MODE_13_S 2 + +/* SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is + * delayed one cycle after CS inactive 2: SPI clock is delayed two cycles + * after CS inactive 3: SPI clock is alwasy on. + */ + +#define SPI_CLK_MODE 0x00000003 +#define SPI_CLK_MODE_M (SPI_CLK_MODE_V << SPI_CLK_MODE_S) +#define SPI_CLK_MODE_V 0x00000003 +#define SPI_CLK_MODE_S 0 + +/* SPI_CTRL2_REG register */ + +#define SPI_CTRL2_REG (DR_REG_SPI_BASE + 0x10) + +/* SPI_CS_DELAY_NUM : R/W; bitpos: [30:29]; default: 0; + * spi_cs signal is delayed by system clock cycles + */ + +#define SPI_CS_DELAY_NUM 0x00000003 +#define SPI_CS_DELAY_NUM_M (SPI_CS_DELAY_NUM_V << SPI_CS_DELAY_NUM_S) +#define SPI_CS_DELAY_NUM_V 0x00000003 +#define SPI_CS_DELAY_NUM_S 29 + +/* SPI_CS_DELAY_MODE : R/W; bitpos: [28:26]; default: 0; + * spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or + * spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle + * 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle, + * else delayed by half cycle 3: delayed one cycle + */ + +#define SPI_CS_DELAY_MODE 0x00000007 +#define SPI_CS_DELAY_MODE_M (SPI_CS_DELAY_MODE_V << SPI_CS_DELAY_MODE_S) +#define SPI_CS_DELAY_MODE_V 0x00000007 +#define SPI_CS_DELAY_MODE_S 26 + +/* SPI_CS_HOLD_TIME : R/W; bitpos: [25:13]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with + * spi_cs_hold bit. + */ + +#define SPI_CS_HOLD_TIME 0x00001FFF +#define SPI_CS_HOLD_TIME_M (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S) +#define SPI_CS_HOLD_TIME_V 0x00001FFF +#define SPI_CS_HOLD_TIME_S 13 + +/* SPI_CS_SETUP_TIME : R/W; bitpos: [12:0]; default: 1; + * (cycles-1) of prepare phase by spi clock this bits are combined with + * spi_cs_setup bit. + */ + +#define SPI_CS_SETUP_TIME 0x00001FFF +#define SPI_CS_SETUP_TIME_M (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S) +#define SPI_CS_SETUP_TIME_V 0x00001FFF +#define SPI_CS_SETUP_TIME_S 0 + +/* SPI_CLOCK_REG register */ + +#define SPI_CLOCK_REG (DR_REG_SPI_BASE + 0x14) + +/* SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided + * from system clock. + */ + +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S) +#define SPI_CLK_EQU_SYSCLK_V 0x00000001 +#define SPI_CLK_EQU_SYSCLK_S 31 + +/* SPI_CLKDIV_PRE : R/W; bitpos: [30:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. + */ + +#define SPI_CLKDIV_PRE 0x00001FFF +#define SPI_CLKDIV_PRE_M (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S) +#define SPI_CLKDIV_PRE_V 0x00001FFF +#define SPI_CLKDIV_PRE_S 18 + +/* SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1) + */ + +#define SPI_CLKCNT_N 0x0000003F +#define SPI_CLKCNT_N_M (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S) +#define SPI_CLKCNT_N_V 0x0000003F +#define SPI_CLKCNT_N_S 12 + +/* SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave + * mode it must be 0. + */ + +#define SPI_CLKCNT_H 0x0000003F +#define SPI_CLKCNT_H_M (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S) +#define SPI_CLKCNT_H_V 0x0000003F +#define SPI_CLKCNT_H_S 6 + +/* SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it + * must be 0. + */ + +#define SPI_CLKCNT_L 0x0000003F +#define SPI_CLKCNT_L_M (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S) +#define SPI_CLKCNT_L_V 0x0000003F +#define SPI_CLKCNT_L_S 0 + +/* SPI_USER_REG register */ + +#define SPI_USER_REG (DR_REG_SPI_BASE + 0x18) + +/* SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. + */ + +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S) +#define SPI_USR_COMMAND_V 0x00000001 +#define SPI_USR_COMMAND_S 31 + +/* SPI_USR_ADDR : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. + */ + +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (SPI_USR_ADDR_V << SPI_USR_ADDR_S) +#define SPI_USR_ADDR_V 0x00000001 +#define SPI_USR_ADDR_S 30 + +/* SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. + */ + +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S) +#define SPI_USR_DUMMY_V 0x00000001 +#define SPI_USR_DUMMY_S 29 + +/* SPI_USR_MISO : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. + */ + +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (SPI_USR_MISO_V << SPI_USR_MISO_S) +#define SPI_USR_MISO_V 0x00000001 +#define SPI_USR_MISO_S 28 + +/* SPI_USR_MOSI : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. + */ + +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (SPI_USR_MOSI_V << SPI_USR_MOSI_S) +#define SPI_USR_MOSI_V 0x00000001 +#define SPI_USR_MOSI_S 27 + +/* SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. + */ + +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S) +#define SPI_USR_DUMMY_IDLE_V 0x00000001 +#define SPI_USR_DUMMY_IDLE_S 26 + +/* SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. + * 1: enable 0: disable. + */ + +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S) +#define SPI_USR_MOSI_HIGHPART_V 0x00000001 +#define SPI_USR_MOSI_HIGHPART_S 25 + +/* SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: + * enable 0: disable. + */ + +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S) +#define SPI_USR_MISO_HIGHPART_V 0x00000001 +#define SPI_USR_MISO_HIGHPART_S 24 + +/* SPI_USR_PREP_HOLD : R/W; bitpos: [23]; default: 0; + * spi is hold at prepare state the bit are combined with spi_usr_hold_pol + * bit. + */ + +#define SPI_USR_PREP_HOLD (BIT(23)) +#define SPI_USR_PREP_HOLD_M (SPI_USR_PREP_HOLD_V << SPI_USR_PREP_HOLD_S) +#define SPI_USR_PREP_HOLD_V 0x00000001 +#define SPI_USR_PREP_HOLD_S 23 + +/* SPI_USR_CMD_HOLD : R/W; bitpos: [22]; default: 0; + * spi is hold at command state the bit are combined with spi_usr_hold_pol + * bit. + */ + +#define SPI_USR_CMD_HOLD (BIT(22)) +#define SPI_USR_CMD_HOLD_M (SPI_USR_CMD_HOLD_V << SPI_USR_CMD_HOLD_S) +#define SPI_USR_CMD_HOLD_V 0x00000001 +#define SPI_USR_CMD_HOLD_S 22 + +/* SPI_USR_ADDR_HOLD : R/W; bitpos: [21]; default: 0; + * spi is hold at address state the bit are combined with spi_usr_hold_pol + * bit. + */ + +#define SPI_USR_ADDR_HOLD (BIT(21)) +#define SPI_USR_ADDR_HOLD_M (SPI_USR_ADDR_HOLD_V << SPI_USR_ADDR_HOLD_S) +#define SPI_USR_ADDR_HOLD_V 0x00000001 +#define SPI_USR_ADDR_HOLD_S 21 + +/* SPI_USR_DUMMY_HOLD : R/W; bitpos: [20]; default: 0; + * spi is hold at dummy state the bit are combined with spi_usr_hold_pol bit. + */ + +#define SPI_USR_DUMMY_HOLD (BIT(20)) +#define SPI_USR_DUMMY_HOLD_M (SPI_USR_DUMMY_HOLD_V << SPI_USR_DUMMY_HOLD_S) +#define SPI_USR_DUMMY_HOLD_V 0x00000001 +#define SPI_USR_DUMMY_HOLD_S 20 + +/* SPI_USR_DIN_HOLD : R/W; bitpos: [19]; default: 0; + * spi is hold at data in state the bit are combined with spi_usr_hold_pol + * bit. + */ + +#define SPI_USR_DIN_HOLD (BIT(19)) +#define SPI_USR_DIN_HOLD_M (SPI_USR_DIN_HOLD_V << SPI_USR_DIN_HOLD_S) +#define SPI_USR_DIN_HOLD_V 0x00000001 +#define SPI_USR_DIN_HOLD_S 19 + +/* SPI_USR_DOUT_HOLD : R/W; bitpos: [18]; default: 0; + * spi is hold at data out state the bit are combined with spi_usr_hold_pol + * bit. + */ + +#define SPI_USR_DOUT_HOLD (BIT(18)) +#define SPI_USR_DOUT_HOLD_M (SPI_USR_DOUT_HOLD_V << SPI_USR_DOUT_HOLD_S) +#define SPI_USR_DOUT_HOLD_V 0x00000001 +#define SPI_USR_DOUT_HOLD_S 18 + +/* SPI_USR_HOLD_POL : R/W; bitpos: [17]; default: 0; + * It is combined with hold bits to set the polarity of spi hold line 1: spi + * will be held when spi hold line is high 0: spi will be held when spi hold + * line is low + */ + +#define SPI_USR_HOLD_POL (BIT(17)) +#define SPI_USR_HOLD_POL_M (SPI_USR_HOLD_POL_V << SPI_USR_HOLD_POL_S) +#define SPI_USR_HOLD_POL_V 0x00000001 +#define SPI_USR_HOLD_POL_S 17 + +/* SPI_SIO : R/W; bitpos: [16]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso + * signals share the same pin. 1: enable 0: disable. + */ + +#define SPI_SIO (BIT(16)) +#define SPI_SIO_M (SPI_SIO_V << SPI_SIO_S) +#define SPI_SIO_V 0x00000001 +#define SPI_SIO_S 16 + +/* SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means + * seg-trans will continue. 0: The seg-trans will end after the current SPI + * seg-trans or this is not seg-trans mode. + */ + +#define SPI_USR_CONF_NXT (BIT(15)) +#define SPI_USR_CONF_NXT_M (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S) +#define SPI_USR_CONF_NXT_V 0x00000001 +#define SPI_USR_CONF_NXT_S 15 + +/* SPI_FWRITE_OCT : R/W; bitpos: [14]; default: 0; + * In the write operations read-data phase apply 8 signals + */ + +#define SPI_FWRITE_OCT (BIT(14)) +#define SPI_FWRITE_OCT_M (SPI_FWRITE_OCT_V << SPI_FWRITE_OCT_S) +#define SPI_FWRITE_OCT_V 0x00000001 +#define SPI_FWRITE_OCT_S 14 + +/* SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals + */ + +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S) +#define SPI_FWRITE_QUAD_V 0x00000001 +#define SPI_FWRITE_QUAD_S 13 + +/* SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals + */ + +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S) +#define SPI_FWRITE_DUAL_V 0x00000001 +#define SPI_FWRITE_DUAL_S 12 + +/* SPI_WR_BYTE_ORDER : R/W; bitpos: [11]; default: 0; + * In command address write-data (MOSI) phases 1: big-endian 0: litte_endian + */ + +#define SPI_WR_BYTE_ORDER (BIT(11)) +#define SPI_WR_BYTE_ORDER_M (SPI_WR_BYTE_ORDER_V << SPI_WR_BYTE_ORDER_S) +#define SPI_WR_BYTE_ORDER_V 0x00000001 +#define SPI_WR_BYTE_ORDER_S 11 + +/* SPI_RD_BYTE_ORDER : R/W; bitpos: [10]; default: 0; + * In read-data (MISO) phase 1: big-endian 0: little_endian + */ + +#define SPI_RD_BYTE_ORDER (BIT(10)) +#define SPI_RD_BYTE_ORDER_M (SPI_RD_BYTE_ORDER_V << SPI_RD_BYTE_ORDER_S) +#define SPI_RD_BYTE_ORDER_V 0x00000001 +#define SPI_RD_BYTE_ORDER_S 10 + +/* SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay + * mode. + */ + +#define SPI_CK_OUT_EDGE (BIT(9)) +#define SPI_CK_OUT_EDGE_M (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S) +#define SPI_CK_OUT_EDGE_V 0x00000001 +#define SPI_CK_OUT_EDGE_S 9 + +/* SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. + * 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + */ + +#define SPI_RSCK_I_EDGE (BIT(8)) +#define SPI_RSCK_I_EDGE_M (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S) +#define SPI_RSCK_I_EDGE_V 0x00000001 +#define SPI_RSCK_I_EDGE_S 8 + +/* SPI_CS_SETUP : R/W; bitpos: [7]; default: 0; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + */ + +#define SPI_CS_SETUP (BIT(7)) +#define SPI_CS_SETUP_M (SPI_CS_SETUP_V << SPI_CS_SETUP_S) +#define SPI_CS_SETUP_V 0x00000001 +#define SPI_CS_SETUP_S 7 + +/* SPI_CS_HOLD : R/W; bitpos: [6]; default: 0; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. + */ + +#define SPI_CS_HOLD (BIT(6)) +#define SPI_CS_HOLD_M (SPI_CS_HOLD_V << SPI_CS_HOLD_S) +#define SPI_CS_HOLD_V 0x00000001 +#define SPI_CS_HOLD_S 6 + +/* SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. + * 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + */ + +#define SPI_TSCK_I_EDGE (BIT(5)) +#define SPI_TSCK_I_EDGE_M (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S) +#define SPI_TSCK_I_EDGE_V 0x00000001 +#define SPI_TSCK_I_EDGE_S 5 + +/* SPI_DOUTDIN : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. + */ + +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (SPI_DOUTDIN_V << SPI_DOUTDIN_S) +#define SPI_DOUTDIN_V 0x00000001 +#define SPI_DOUTDIN_S 0 + +/* SPI_USER1_REG register */ + +#define SPI_USER1_REG (DR_REG_SPI_BASE + 0x1c) + +/* SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be + * (bit_num-1). + */ + +#define SPI_USR_ADDR_BITLEN 0x0000001F +#define SPI_USR_ADDR_BITLEN_M (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S) +#define SPI_USR_ADDR_BITLEN_V 0x0000001F +#define SPI_USR_ADDR_BITLEN_S 27 + +/* SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). + */ + +#define SPI_USR_DUMMY_CYCLELEN 0x000000FF +#define SPI_USR_DUMMY_CYCLELEN_M (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S) +#define SPI_USR_DUMMY_CYCLELEN_V 0x000000FF +#define SPI_USR_DUMMY_CYCLELEN_S 0 + +/* SPI_USER2_REG register */ + +#define SPI_USER2_REG (DR_REG_SPI_BASE + 0x20) + +/* SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be + * (bit_num-1) + */ + +#define SPI_USR_COMMAND_BITLEN 0x0000000F +#define SPI_USR_COMMAND_BITLEN_M (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S) +#define SPI_USR_COMMAND_BITLEN_V 0x0000000F +#define SPI_USR_COMMAND_BITLEN_S 28 + +/* SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. + */ + +#define SPI_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_USR_COMMAND_VALUE_M (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S) +#define SPI_USR_COMMAND_VALUE_V 0x0000FFFF +#define SPI_USR_COMMAND_VALUE_S 0 + +/* SPI_MOSI_DLEN_REG register */ + +#define SPI_MOSI_DLEN_REG (DR_REG_SPI_BASE + 0x24) + +/* SPI_USR_MOSI_DBITLEN : R/W; bitpos: [22:0]; default: 0; + * The length in bits of write-data. The register value shall be (bit_num-1). + */ + +#define SPI_USR_MOSI_DBITLEN 0x007FFFFF +#define SPI_USR_MOSI_DBITLEN_M (SPI_USR_MOSI_DBITLEN_V << SPI_USR_MOSI_DBITLEN_S) +#define SPI_USR_MOSI_DBITLEN_V 0x007FFFFF +#define SPI_USR_MOSI_DBITLEN_S 0 + +/* SPI_MISO_DLEN_REG register */ + +#define SPI_MISO_DLEN_REG (DR_REG_SPI_BASE + 0x28) + +/* SPI_USR_MISO_DBITLEN : R/W; bitpos: [22:0]; default: 0; + * The length in bits of read-data. The register value shall be (bit_num-1). + */ + +#define SPI_USR_MISO_DBITLEN 0x007FFFFF +#define SPI_USR_MISO_DBITLEN_M (SPI_USR_MISO_DBITLEN_V << SPI_USR_MISO_DBITLEN_S) +#define SPI_USR_MISO_DBITLEN_V 0x007FFFFF +#define SPI_USR_MISO_DBITLEN_S 0 + +/* SPI_SLV_WR_STATUS_REG register */ + +#define SPI_SLV_WR_STATUS_REG (DR_REG_SPI_BASE + 0x2c) + +/* SPI_OPI_MODE : R/W; bitpos: [1]; default: 0; + * Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: + * others. + */ + +#define SPI_OPI_MODE (BIT(1)) +#define SPI_OPI_MODE_M (SPI_OPI_MODE_V << SPI_OPI_MODE_S) +#define SPI_OPI_MODE_V 0x00000001 +#define SPI_OPI_MODE_S 1 + +/* SPI_QPI_MODE : R/W; bitpos: [0]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: + * others. + */ + +#define SPI_QPI_MODE (BIT(0)) +#define SPI_QPI_MODE_M (SPI_QPI_MODE_V << SPI_QPI_MODE_S) +#define SPI_QPI_MODE_V 0x00000001 +#define SPI_QPI_MODE_S 0 + +/* SPI_MISC_REG register */ + +#define SPI_MISC_REG (DR_REG_SPI_BASE + 0x30) + +/* SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0; + * 1: spi quad input swap enable 0: spi quad input swap disable + */ + +#define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_M (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S) +#define SPI_QUAD_DIN_PIN_SWAP_V 0x00000001 +#define SPI_QUAD_DIN_PIN_SWAP_S 31 + +/* SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. + */ + +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S) +#define SPI_CS_KEEP_ACTIVE_V 0x00000001 +#define SPI_CS_KEEP_ACTIVE_S 30 + +/* SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle + */ + +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S) +#define SPI_CK_IDLE_EDGE_V 0x00000001 +#define SPI_CK_IDLE_EDGE_S 29 + +/* SPI_CD_IDLE_EDGE : R/W; bitpos: [26]; default: 0; + * The default value of spi_cd. + */ + +#define SPI_CD_IDLE_EDGE (BIT(26)) +#define SPI_CD_IDLE_EDGE_M (SPI_CD_IDLE_EDGE_V << SPI_CD_IDLE_EDGE_S) +#define SPI_CD_IDLE_EDGE_V 0x00000001 +#define SPI_CD_IDLE_EDGE_S 26 + +/* SPI_CD_CMD_SET : R/W; bitpos: [25]; default: 0; + * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_CMD state. + * 0: spi_cd = spi_cd_idle_edge. + */ + +#define SPI_CD_CMD_SET (BIT(25)) +#define SPI_CD_CMD_SET_M (SPI_CD_CMD_SET_V << SPI_CD_CMD_SET_S) +#define SPI_CD_CMD_SET_V 0x00000001 +#define SPI_CD_CMD_SET_S 25 + +/* SPI_DQS_IDLE_EDGE : R/W; bitpos: [24]; default: 0; + * The default value of spi_dqs. + */ + +#define SPI_DQS_IDLE_EDGE (BIT(24)) +#define SPI_DQS_IDLE_EDGE_M (SPI_DQS_IDLE_EDGE_V << SPI_DQS_IDLE_EDGE_S) +#define SPI_DQS_IDLE_EDGE_V 0x00000001 +#define SPI_DQS_IDLE_EDGE_S 24 + +/* SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change + */ + +#define SPI_SLAVE_CS_POL (BIT(23)) +#define SPI_SLAVE_CS_POL_M (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S) +#define SPI_SLAVE_CS_POL_V 0x00000001 +#define SPI_SLAVE_CS_POL_S 23 + +/* SPI_CD_ADDR_SET : R/W; bitpos: [22]; default: 0; + * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_SEND_ADDR state. + * 0: spi_cd = spi_cd_idle_edge. + */ + +#define SPI_CD_ADDR_SET (BIT(22)) +#define SPI_CD_ADDR_SET_M (SPI_CD_ADDR_SET_V << SPI_CD_ADDR_SET_S) +#define SPI_CD_ADDR_SET_V 0x00000001 +#define SPI_CD_ADDR_SET_S 22 + +/* SPI_CD_DUMMY_SET : R/W; bitpos: [21]; default: 0; + * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DUMMY state. 0: + * spi_cd = spi_cd_idle_edge. + */ + +#define SPI_CD_DUMMY_SET (BIT(21)) +#define SPI_CD_DUMMY_SET_M (SPI_CD_DUMMY_SET_V << SPI_CD_DUMMY_SET_S) +#define SPI_CD_DUMMY_SET_V 0x00000001 +#define SPI_CD_DUMMY_SET_S 21 + +/* SPI_CD_DATA_SET : R/W; bitpos: [20]; default: 0; + * 1: spi_cd = !spi_cd_idle_edge when spi_st[3:0] is in SPI_DOUT or SPI_DIN + * state. 0: spi_cd = spi_cd_idle_edge. + */ + +#define SPI_CD_DATA_SET (BIT(20)) +#define SPI_CD_DATA_SET_M (SPI_CD_DATA_SET_V << SPI_CD_DATA_SET_S) +#define SPI_CD_DATA_SET_V 0x00000001 +#define SPI_CD_DATA_SET_S 20 + +/* SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. + */ + +#define SPI_MASTER_CS_POL 0x0000003F +#define SPI_MASTER_CS_POL_M (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S) +#define SPI_MASTER_CS_POL_V 0x0000003F +#define SPI_MASTER_CS_POL_S 7 + +/* SPI_CK_DIS : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable + */ + +#define SPI_CK_DIS (BIT(6)) +#define SPI_CK_DIS_M (SPI_CK_DIS_V << SPI_CK_DIS_S) +#define SPI_CK_DIS_V 0x00000001 +#define SPI_CK_DIS_S 6 + +/* SPI_CS5_DIS : R/W; bitpos: [5]; default: 1; + * SPI CS5 pin enable, 1: disable CS5, 0: SPI_CS5 signal is from/to CS5 pin + */ + +#define SPI_CS5_DIS (BIT(5)) +#define SPI_CS5_DIS_M (SPI_CS5_DIS_V << SPI_CS5_DIS_S) +#define SPI_CS5_DIS_V 0x00000001 +#define SPI_CS5_DIS_S 5 + +/* SPI_CS4_DIS : R/W; bitpos: [4]; default: 1; + * SPI CS4 pin enable, 1: disable CS4, 0: SPI_CS4 signal is from/to CS4 pin + */ + +#define SPI_CS4_DIS (BIT(4)) +#define SPI_CS4_DIS_M (SPI_CS4_DIS_V << SPI_CS4_DIS_S) +#define SPI_CS4_DIS_V 0x00000001 +#define SPI_CS4_DIS_S 4 + +/* SPI_CS3_DIS : R/W; bitpos: [3]; default: 1; + * SPI CS3 pin enable, 1: disable CS3, 0: SPI_CS3 signal is from/to CS3 pin + */ + +#define SPI_CS3_DIS (BIT(3)) +#define SPI_CS3_DIS_M (SPI_CS3_DIS_V << SPI_CS3_DIS_S) +#define SPI_CS3_DIS_V 0x00000001 +#define SPI_CS3_DIS_S 3 + +/* SPI_CS2_DIS : R/W; bitpos: [2]; default: 1; + * SPI CS2 pin enable, 1: disable CS2, 0: SPI_CS2 signal is from/to CS2 pin + */ + +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (SPI_CS2_DIS_V << SPI_CS2_DIS_S) +#define SPI_CS2_DIS_V 0x00000001 +#define SPI_CS2_DIS_S 2 + +/* SPI_CS1_DIS : R/W; bitpos: [1]; default: 1; + * SPI CS1 pin enable, 1: disable CS1, 0: SPI_CS1 signal is from/to CS1 pin + */ + +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (SPI_CS1_DIS_V << SPI_CS1_DIS_S) +#define SPI_CS1_DIS_V 0x00000001 +#define SPI_CS1_DIS_S 1 + +/* SPI_CS0_DIS : R/W; bitpos: [0]; default: 1; + * SPI CS0 pin enable, 1: disable CS0, 0: SPI_CS0 signal is from/to CS0 pin + */ + +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (SPI_CS0_DIS_V << SPI_CS0_DIS_S) +#define SPI_CS0_DIS_V 0x00000001 +#define SPI_CS0_DIS_S 0 + +/* SPI_SLAVE_REG register */ + +#define SPI_SLAVE_REG (DR_REG_SPI_BASE + 0x34) + +/* SPI_SOFT_RESET : R/W; bitpos: [31]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. + */ + +#define SPI_SOFT_RESET (BIT(31)) +#define SPI_SOFT_RESET_M (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S) +#define SPI_SOFT_RESET_V 0x00000001 +#define SPI_SOFT_RESET_S 31 + +/* SPI_SLAVE_MODE : R/W; bitpos: [30]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ + +#define SPI_SLAVE_MODE (BIT(30)) +#define SPI_SLAVE_MODE_M (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S) +#define SPI_SLAVE_MODE_V 0x00000001 +#define SPI_SLAVE_MODE_S 30 + +/* SPI_TRANS_DONE_AUTO_CLR_EN : R/W; bitpos: [29]; default: 0; + * spi_trans_done auto clear enable, clear it 3 apb cycles after the pos + * edge of spi_trans_done. 0:disable. 1: enable. + */ + +#define SPI_TRANS_DONE_AUTO_CLR_EN (BIT(29)) +#define SPI_TRANS_DONE_AUTO_CLR_EN_M (SPI_TRANS_DONE_AUTO_CLR_EN_V << SPI_TRANS_DONE_AUTO_CLR_EN_S) +#define SPI_TRANS_DONE_AUTO_CLR_EN_V 0x00000001 +#define SPI_TRANS_DONE_AUTO_CLR_EN_S 29 + +/* SPI_TRANS_CNT : RO; bitpos: [26:23]; default: 0; + * The operations counter in both the master mode and the slave mode. + */ + +#define SPI_TRANS_CNT 0x0000000F +#define SPI_TRANS_CNT_M (SPI_TRANS_CNT_V << SPI_TRANS_CNT_S) +#define SPI_TRANS_CNT_V 0x0000000F +#define SPI_TRANS_CNT_S 23 + +/* SPI_SEG_MAGIC_ERR_INT_EN : R/W; bitpos: [11]; default: 0; + * 1: Enable seg magic value error interrupt. 0: Others + */ + +#define SPI_SEG_MAGIC_ERR_INT_EN (BIT(11)) +#define SPI_SEG_MAGIC_ERR_INT_EN_M (SPI_SEG_MAGIC_ERR_INT_EN_V << SPI_SEG_MAGIC_ERR_INT_EN_S) +#define SPI_SEG_MAGIC_ERR_INT_EN_V 0x00000001 +#define SPI_SEG_MAGIC_ERR_INT_EN_S 11 + +/* SPI_INT_DMA_SEG_TRANS_EN : R/W; bitpos: [10]; default: 0; + * spi_dma_seg_trans_done Interrupt enable. 1: enable 0: disable + */ + +#define SPI_INT_DMA_SEG_TRANS_EN (BIT(10)) +#define SPI_INT_DMA_SEG_TRANS_EN_M (SPI_INT_DMA_SEG_TRANS_EN_V << SPI_INT_DMA_SEG_TRANS_EN_S) +#define SPI_INT_DMA_SEG_TRANS_EN_V 0x00000001 +#define SPI_INT_DMA_SEG_TRANS_EN_S 10 + +/* SPI_INT_TRANS_DONE_EN : R/W; bitpos: [9]; default: 1; + * spi_trans_done Interrupt enable. 1: enable 0: disable + */ + +#define SPI_INT_TRANS_DONE_EN (BIT(9)) +#define SPI_INT_TRANS_DONE_EN_M (SPI_INT_TRANS_DONE_EN_V << SPI_INT_TRANS_DONE_EN_S) +#define SPI_INT_TRANS_DONE_EN_V 0x00000001 +#define SPI_INT_TRANS_DONE_EN_S 9 + +/* SPI_INT_WR_DMA_DONE_EN : R/W; bitpos: [8]; default: 0; + * spi_slv_wr_dma Interrupt enable. 1: enable 0: disable + */ + +#define SPI_INT_WR_DMA_DONE_EN (BIT(8)) +#define SPI_INT_WR_DMA_DONE_EN_M (SPI_INT_WR_DMA_DONE_EN_V << SPI_INT_WR_DMA_DONE_EN_S) +#define SPI_INT_WR_DMA_DONE_EN_V 0x00000001 +#define SPI_INT_WR_DMA_DONE_EN_S 8 + +/* SPI_INT_RD_DMA_DONE_EN : R/W; bitpos: [7]; default: 0; + * spi_slv_rd_dma Interrupt enable. 1: enable 0: disable + */ + +#define SPI_INT_RD_DMA_DONE_EN (BIT(7)) +#define SPI_INT_RD_DMA_DONE_EN_M (SPI_INT_RD_DMA_DONE_EN_V << SPI_INT_RD_DMA_DONE_EN_S) +#define SPI_INT_RD_DMA_DONE_EN_V 0x00000001 +#define SPI_INT_RD_DMA_DONE_EN_S 7 + +/* SPI_INT_WR_BUF_DONE_EN : R/W; bitpos: [6]; default: 0; + * spi_slv_wr_buf Interrupt enable. 1: enable 0: disable + */ + +#define SPI_INT_WR_BUF_DONE_EN (BIT(6)) +#define SPI_INT_WR_BUF_DONE_EN_M (SPI_INT_WR_BUF_DONE_EN_V << SPI_INT_WR_BUF_DONE_EN_S) +#define SPI_INT_WR_BUF_DONE_EN_V 0x00000001 +#define SPI_INT_WR_BUF_DONE_EN_S 6 + +/* SPI_INT_RD_BUF_DONE_EN : R/W; bitpos: [5]; default: 0; + * spi_slv_rd_buf Interrupt enable. 1: enable 0: disable + */ + +#define SPI_INT_RD_BUF_DONE_EN (BIT(5)) +#define SPI_INT_RD_BUF_DONE_EN_M (SPI_INT_RD_BUF_DONE_EN_V << SPI_INT_RD_BUF_DONE_EN_S) +#define SPI_INT_RD_BUF_DONE_EN_V 0x00000001 +#define SPI_INT_RD_BUF_DONE_EN_S 5 + +/* SPI_TRANS_DONE : R/W; bitpos: [4]; default: 0; + * The interrupt raw bit for the completion of any operation in both the + * master mode and the slave mode. Can not be changed by CONF_buf. + */ + +#define SPI_TRANS_DONE (BIT(4)) +#define SPI_TRANS_DONE_M (SPI_TRANS_DONE_V << SPI_TRANS_DONE_S) +#define SPI_TRANS_DONE_V 0x00000001 +#define SPI_TRANS_DONE_S 4 + +/* SPI_SLAVE1_REG register */ + +#define SPI_SLAVE1_REG (DR_REG_SPI_BASE + 0x38) + +/* SPI_SLV_LAST_ADDR : R/W; bitpos: [31:24]; default: 0; + * In the slave mode it is the value of address. + */ + +#define SPI_SLV_LAST_ADDR 0x000000FF +#define SPI_SLV_LAST_ADDR_M (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S) +#define SPI_SLV_LAST_ADDR_V 0x000000FF +#define SPI_SLV_LAST_ADDR_S 24 + +/* SPI_SLV_LAST_COMMAND : R/W; bitpos: [23:16]; default: 0; + * In the slave mode it is the value of command. + */ + +#define SPI_SLV_LAST_COMMAND 0x000000FF +#define SPI_SLV_LAST_COMMAND_M (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S) +#define SPI_SLV_LAST_COMMAND_V 0x000000FF +#define SPI_SLV_LAST_COMMAND_S 16 + +/* SPI_SLV_WR_DMA_DONE : R/W; bitpos: [15]; default: 0; + * The interrupt raw bit for the completion of dma write operation in the + * slave mode. Can not be changed by CONF_buf. + */ + +#define SPI_SLV_WR_DMA_DONE (BIT(15)) +#define SPI_SLV_WR_DMA_DONE_M (SPI_SLV_WR_DMA_DONE_V << SPI_SLV_WR_DMA_DONE_S) +#define SPI_SLV_WR_DMA_DONE_V 0x00000001 +#define SPI_SLV_WR_DMA_DONE_S 15 + +/* SPI_SLV_CMD_ERR : R/W; bitpos: [14]; default: 0; + * 1: The command value of the last SPI transfer is not supported by SPI + * slave. 0: The command value is supported or no command value is received. + */ + +#define SPI_SLV_CMD_ERR (BIT(14)) +#define SPI_SLV_CMD_ERR_M (SPI_SLV_CMD_ERR_V << SPI_SLV_CMD_ERR_S) +#define SPI_SLV_CMD_ERR_V 0x00000001 +#define SPI_SLV_CMD_ERR_S 14 + +/* SPI_SLV_ADDR_ERR : R/W; bitpos: [13]; default: 0; + * 1: The address value of the last SPI transfer is not supported by SPI + * slave. 0: The address value is supported or no address value is received. + */ + +#define SPI_SLV_ADDR_ERR (BIT(13)) +#define SPI_SLV_ADDR_ERR_M (SPI_SLV_ADDR_ERR_V << SPI_SLV_ADDR_ERR_S) +#define SPI_SLV_ADDR_ERR_V 0x00000001 +#define SPI_SLV_ADDR_ERR_S 13 + +/* SPI_SLAVE2_REG register */ + +#define SPI_SLAVE2_REG (DR_REG_SPI_BASE + 0x3c) + +/* SPI_SLV_RD_DMA_DONE : R/W; bitpos: [8]; default: 0; + * The interrupt raw bit for the completion of Rd-DMA operation in the slave + * mode. Can not be changed by CONF_buf. + */ + +#define SPI_SLV_RD_DMA_DONE (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_M (SPI_SLV_RD_DMA_DONE_V << SPI_SLV_RD_DMA_DONE_S) +#define SPI_SLV_RD_DMA_DONE_V 0x00000001 +#define SPI_SLV_RD_DMA_DONE_S 8 + +/* SPI_SLV_WRBUF_DLEN_REG register */ + +#define SPI_SLV_WRBUF_DLEN_REG (DR_REG_SPI_BASE + 0x40) + +/* SPI_CONF_BASE_BITLEN : R/W; bitpos: [31:25]; default: 108; + * The basic spi_clk cycles of CONF state. The real cycle length of CONF + * state, if spi_usr_conf is enabled, is spi_conf_base_bitlen[6:0] + + * spi_conf_bitlen[23:0]. + */ + +#define SPI_CONF_BASE_BITLEN 0x0000007F +#define SPI_CONF_BASE_BITLEN_M (SPI_CONF_BASE_BITLEN_V << SPI_CONF_BASE_BITLEN_S) +#define SPI_CONF_BASE_BITLEN_V 0x0000007F +#define SPI_CONF_BASE_BITLEN_S 25 + +/* SPI_SLV_WR_BUF_DONE : R/W; bitpos: [24]; default: 0; + * The interrupt raw bit for the completion of write-buffer operation in the + * slave mode. Can not be changed by CONF_buf. + */ + +#define SPI_SLV_WR_BUF_DONE (BIT(24)) +#define SPI_SLV_WR_BUF_DONE_M (SPI_SLV_WR_BUF_DONE_V << SPI_SLV_WR_BUF_DONE_S) +#define SPI_SLV_WR_BUF_DONE_V 0x00000001 +#define SPI_SLV_WR_BUF_DONE_S 24 + +/* SPI_SLV_RDBUF_DLEN_REG register */ + +#define SPI_SLV_RDBUF_DLEN_REG (DR_REG_SPI_BASE + 0x44) + +/* SPI_SEG_MAGIC_ERR : R/W; bitpos: [25]; default: 0; + * 1: The recent magic value in CONF buffer is not right in master DMA + * seg-trans mode. 0: others. + */ + +#define SPI_SEG_MAGIC_ERR (BIT(25)) +#define SPI_SEG_MAGIC_ERR_M (SPI_SEG_MAGIC_ERR_V << SPI_SEG_MAGIC_ERR_S) +#define SPI_SEG_MAGIC_ERR_V 0x00000001 +#define SPI_SEG_MAGIC_ERR_S 25 + +/* SPI_SLV_RD_BUF_DONE : R/W; bitpos: [24]; default: 0; + * The interrupt raw bit for the completion of read-buffer operation in the + * slave mode. Can not be changed by CONF_buf. + */ + +#define SPI_SLV_RD_BUF_DONE (BIT(24)) +#define SPI_SLV_RD_BUF_DONE_M (SPI_SLV_RD_BUF_DONE_V << SPI_SLV_RD_BUF_DONE_S) +#define SPI_SLV_RD_BUF_DONE_V 0x00000001 +#define SPI_SLV_RD_BUF_DONE_S 24 + +/* SPI_SLV_DMA_RD_BYTELEN : R/W; bitpos: [19:0]; default: 0; + * In the slave mode it is the length in bytes for read operations. The + * register value shall be byte_num. + */ + +#define SPI_SLV_DMA_RD_BYTELEN 0x000FFFFF +#define SPI_SLV_DMA_RD_BYTELEN_M (SPI_SLV_DMA_RD_BYTELEN_V << SPI_SLV_DMA_RD_BYTELEN_S) +#define SPI_SLV_DMA_RD_BYTELEN_V 0x000FFFFF +#define SPI_SLV_DMA_RD_BYTELEN_S 0 + +/* SPI_SLV_RD_BYTE_REG register */ + +#define SPI_SLV_RD_BYTE_REG (DR_REG_SPI_BASE + 0x48) + +/* SPI_USR_CONF : R/W; bitpos: [31]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means + * seg-trans will start. 0: This is not seg-trans mode. + */ + +#define SPI_USR_CONF (BIT(31)) +#define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S) +#define SPI_USR_CONF_V 0x00000001 +#define SPI_USR_CONF_S 31 + +/* SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [29:24]; default: 23; + * The magic value of BM table in master DMA seg-trans. + */ + +#define SPI_DMA_SEG_MAGIC_VALUE 0x0000003F +#define SPI_DMA_SEG_MAGIC_VALUE_M (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S) +#define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000003F +#define SPI_DMA_SEG_MAGIC_VALUE_S 24 + +/* SPI_SLV_WRBUF_BYTELEN_EN : R/W; bitpos: [23]; default: 0; + * 1: spi_slv_data_bytelen stores data byte length of master-write-to-slave + * data length in CPU controlled mode(Wr_BUF). 0: others + */ + +#define SPI_SLV_WRBUF_BYTELEN_EN (BIT(23)) +#define SPI_SLV_WRBUF_BYTELEN_EN_M (SPI_SLV_WRBUF_BYTELEN_EN_V << SPI_SLV_WRBUF_BYTELEN_EN_S) +#define SPI_SLV_WRBUF_BYTELEN_EN_V 0x00000001 +#define SPI_SLV_WRBUF_BYTELEN_EN_S 23 + +/* SPI_SLV_RDBUF_BYTELEN_EN : R/W; bitpos: [22]; default: 0; + * 1: spi_slv_data_bytelen stores data byte length of master-read-slave data + * length in CPU controlled mode(Rd_BUF). 0: others + */ + +#define SPI_SLV_RDBUF_BYTELEN_EN (BIT(22)) +#define SPI_SLV_RDBUF_BYTELEN_EN_M (SPI_SLV_RDBUF_BYTELEN_EN_V << SPI_SLV_RDBUF_BYTELEN_EN_S) +#define SPI_SLV_RDBUF_BYTELEN_EN_V 0x00000001 +#define SPI_SLV_RDBUF_BYTELEN_EN_S 22 + +/* SPI_SLV_WRDMA_BYTELEN_EN : R/W; bitpos: [21]; default: 0; + * 1: spi_slv_data_bytelen stores data byte length of master-write-to-slave + * data length in DMA controlled mode(Wr_DMA). 0: others + */ + +#define SPI_SLV_WRDMA_BYTELEN_EN (BIT(21)) +#define SPI_SLV_WRDMA_BYTELEN_EN_M (SPI_SLV_WRDMA_BYTELEN_EN_V << SPI_SLV_WRDMA_BYTELEN_EN_S) +#define SPI_SLV_WRDMA_BYTELEN_EN_V 0x00000001 +#define SPI_SLV_WRDMA_BYTELEN_EN_S 21 + +/* SPI_SLV_RDDMA_BYTELEN_EN : R/W; bitpos: [20]; default: 0; + * 1: spi_slv_data_bytelen stores data byte length of master-read-slave data + * length in DMA controlled mode(Rd_DMA). 0: others + */ + +#define SPI_SLV_RDDMA_BYTELEN_EN (BIT(20)) +#define SPI_SLV_RDDMA_BYTELEN_EN_M (SPI_SLV_RDDMA_BYTELEN_EN_V << SPI_SLV_RDDMA_BYTELEN_EN_S) +#define SPI_SLV_RDDMA_BYTELEN_EN_V 0x00000001 +#define SPI_SLV_RDDMA_BYTELEN_EN_S 20 + +/* SPI_SLV_DATA_BYTELEN : R/W; bitpos: [19:0]; default: 0; + * The full-duplex or half-duplex data byte length of the last SPI transfer + * in slave mode. In half-duplex mode, this value is controlled by bits + * [23:20]. + */ + +#define SPI_SLV_DATA_BYTELEN 0x000FFFFF +#define SPI_SLV_DATA_BYTELEN_M (SPI_SLV_DATA_BYTELEN_V << SPI_SLV_DATA_BYTELEN_S) +#define SPI_SLV_DATA_BYTELEN_V 0x000FFFFF +#define SPI_SLV_DATA_BYTELEN_S 0 + +/* SPI_FSM_REG register */ + +#define SPI_FSM_REG (DR_REG_SPI_BASE + 0x50) + +/* SPI_MST_DMA_RD_BYTELEN : R/W; bitpos: [31:12]; default: 0; + * Define the master DMA read byte length in non seg-trans or seg-trans + * mode. Invalid when spi_rx_eof_en is 0. + */ + +#define SPI_MST_DMA_RD_BYTELEN 0x000FFFFF +#define SPI_MST_DMA_RD_BYTELEN_M (SPI_MST_DMA_RD_BYTELEN_V << SPI_MST_DMA_RD_BYTELEN_S) +#define SPI_MST_DMA_RD_BYTELEN_V 0x000FFFFF +#define SPI_MST_DMA_RD_BYTELEN_S 12 + +/* SPI_ST : RO; bitpos: [3:0]; default: 0; + * The status of spi state machine. 0: idle state, 1: preparation state, 2: + * send command state, 3: send data state, 4: red data state, 5:write data + * state, 6: wait state, 7: done state. + */ + +#define SPI_ST 0x0000000F +#define SPI_ST_M (SPI_ST_V << SPI_ST_S) +#define SPI_ST_V 0x0000000F +#define SPI_ST_S 0 + +/* SPI_HOLD_REG register */ + +#define SPI_HOLD_REG (DR_REG_SPI_BASE + 0x54) + +/* SPI_DMA_SEG_TRANS_DONE : R/W; bitpos: [7]; default: 0; + * 1: spi master DMA full-duplex/half-duplex seg-trans ends or slave + * half-duplex seg-trans ends. And data has been pushed to corresponding + * memory. 0: seg-trans is not ended or not occurred. Can not be changed + * by CONF_buf. + */ + +#define SPI_DMA_SEG_TRANS_DONE (BIT(7)) +#define SPI_DMA_SEG_TRANS_DONE_M (SPI_DMA_SEG_TRANS_DONE_V << SPI_DMA_SEG_TRANS_DONE_S) +#define SPI_DMA_SEG_TRANS_DONE_V 0x00000001 +#define SPI_DMA_SEG_TRANS_DONE_S 7 + +/* SPI_HOLD_OUT_TIME : R/W; bitpos: [6:4]; default: 0; + * set the hold cycles of output spi_hold signal when spi_hold_out_en is + * enable. + */ + +#define SPI_HOLD_OUT_TIME 0x00000007 +#define SPI_HOLD_OUT_TIME_M (SPI_HOLD_OUT_TIME_V << SPI_HOLD_OUT_TIME_S) +#define SPI_HOLD_OUT_TIME_V 0x00000007 +#define SPI_HOLD_OUT_TIME_S 4 + +/* SPI_HOLD_OUT_EN : R/W; bitpos: [3]; default: 0; + * Enable set spi output hold value to spi_hold_reg. It can be used to hold + * spi state machine with spi_ext_hold_en and other usr hold signals. + */ + +#define SPI_HOLD_OUT_EN (BIT(3)) +#define SPI_HOLD_OUT_EN_M (SPI_HOLD_OUT_EN_V << SPI_HOLD_OUT_EN_S) +#define SPI_HOLD_OUT_EN_V 0x00000001 +#define SPI_HOLD_OUT_EN_S 3 + +/* SPI_HOLD_VAL_REG : R/W; bitpos: [2]; default: 0; + * spi hold output value, which should be used with spi_hold_out_en. + */ + +#define SPI_HOLD_VAL_REG (BIT(2)) +#define SPI_HOLD_VAL_REG_M (SPI_HOLD_VAL_REG_V << SPI_HOLD_VAL_REG_S) +#define SPI_HOLD_VAL_REG_V 0x00000001 +#define SPI_HOLD_VAL_REG_S 2 + +/* SPI_INT_HOLD_ENA : R/W; bitpos: [1:0]; default: 0; + * This register is for two SPI masters to share the same cs clock and data + * signals. The bits of one SPI are set, if the other SPI is busy, the SPI + * will be hold. 1(3): hold at idle phase 2: hold at prepare phase. + */ + +#define SPI_INT_HOLD_ENA 0x00000003 +#define SPI_INT_HOLD_ENA_M (SPI_INT_HOLD_ENA_V << SPI_INT_HOLD_ENA_S) +#define SPI_INT_HOLD_ENA_V 0x00000003 +#define SPI_INT_HOLD_ENA_S 0 + +/* SPI_DMA_CONF_REG register */ + +#define SPI_DMA_CONF_REG (DR_REG_SPI_BASE + 0x58) + +/* SPI_EXT_MEM_BK_SIZE : R/W; bitpos: [27:26]; default: 0; + * Select the external memory block size. + */ + +#define SPI_EXT_MEM_BK_SIZE 0x00000003 +#define SPI_EXT_MEM_BK_SIZE_M (SPI_EXT_MEM_BK_SIZE_V << SPI_EXT_MEM_BK_SIZE_S) +#define SPI_EXT_MEM_BK_SIZE_V 0x00000003 +#define SPI_EXT_MEM_BK_SIZE_S 26 + +/* SPI_DMA_OUTFIFO_EMPTY_ERR : R/W; bitpos: [25]; default: 0; + * 1:spi_dma_outfifo_empty and spi_pop_data_prep are valid, which means that + * there is no data to pop but pop is valid. 0: Others. Can not be changed + * by CONF_buf. + */ + +#define SPI_DMA_OUTFIFO_EMPTY_ERR (BIT(25)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_M (SPI_DMA_OUTFIFO_EMPTY_ERR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_V 0x00000001 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_S 25 + +/* SPI_DMA_INFIFO_FULL_ERR : R/W; bitpos: [24]; default: 0; + * 1:spi_dma_infifo_full and spi_push_data_prep are valid, which means that + * DMA Rx buffer is full but push is valid. 0: Others. Can not be changed + * by CONF_buf. + */ + +#define SPI_DMA_INFIFO_FULL_ERR (BIT(24)) +#define SPI_DMA_INFIFO_FULL_ERR_M (SPI_DMA_INFIFO_FULL_ERR_V << SPI_DMA_INFIFO_FULL_ERR_S) +#define SPI_DMA_INFIFO_FULL_ERR_V 0x00000001 +#define SPI_DMA_INFIFO_FULL_ERR_S 24 + +/* SPI_DMA_OUTFIFO_EMPTY_CLR : R/W; bitpos: [23]; default: 0; + * 1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it. + */ + +#define SPI_DMA_OUTFIFO_EMPTY_CLR (BIT(23)) +#define SPI_DMA_OUTFIFO_EMPTY_CLR_M (SPI_DMA_OUTFIFO_EMPTY_CLR_V << SPI_DMA_OUTFIFO_EMPTY_CLR_S) +#define SPI_DMA_OUTFIFO_EMPTY_CLR_V 0x00000001 +#define SPI_DMA_OUTFIFO_EMPTY_CLR_S 23 + +/* SPI_DMA_INFIFO_FULL_CLR : R/W; bitpos: [22]; default: 0; + * 1:Clear spi_dma_infifo_full_vld. 0: Do not control it. + */ + +#define SPI_DMA_INFIFO_FULL_CLR (BIT(22)) +#define SPI_DMA_INFIFO_FULL_CLR_M (SPI_DMA_INFIFO_FULL_CLR_V << SPI_DMA_INFIFO_FULL_CLR_S) +#define SPI_DMA_INFIFO_FULL_CLR_V 0x00000001 +#define SPI_DMA_INFIFO_FULL_CLR_S 22 + +/* SPI_REG_SPI_REG_RX_EOF_EN : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is + * equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma + * transition. 0: spi_dma_inlink_eof is set by spi_trans_done in + * non-seg-trans or spi_dma_seg_trans_done in seg-trans. + */ + +#define SPI_REG_SPI_REG_RX_EOF_EN (BIT(21)) +#define SPI_REG_SPI_REG_RX_EOF_EN_M (SPI_REG_SPI_REG_RX_EOF_EN_V << SPI_REG_SPI_REG_RX_EOF_EN_S) +#define SPI_REG_SPI_REG_RX_EOF_EN_V 0x00000001 +#define SPI_REG_SPI_REG_RX_EOF_EN_S 21 + +/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ + +#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x00000001 +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 + +/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ + +#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x00000001 +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 + +/* SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: + * disable. + */ + +#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_M (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S) +#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x00000001 +#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 + +/* SPI_SLV_LAST_SEG_POP_CLR : R/W; bitpos: [17]; default: 0; + * 1: Clear spi_slv_seg_frt_pop_mask. 0 : others + */ + +#define SPI_SLV_LAST_SEG_POP_CLR (BIT(17)) +#define SPI_SLV_LAST_SEG_POP_CLR_M (SPI_SLV_LAST_SEG_POP_CLR_V << SPI_SLV_LAST_SEG_POP_CLR_S) +#define SPI_SLV_LAST_SEG_POP_CLR_V 0x00000001 +#define SPI_SLV_LAST_SEG_POP_CLR_S 17 + +/* SPI_DMA_CONTINUE : R/W; bitpos: [16]; default: 0; + * spi dma continue tx/rx data. + */ + +#define SPI_DMA_CONTINUE (BIT(16)) +#define SPI_DMA_CONTINUE_M (SPI_DMA_CONTINUE_V << SPI_DMA_CONTINUE_S) +#define SPI_DMA_CONTINUE_V 0x00000001 +#define SPI_DMA_CONTINUE_S 16 + +/* SPI_DMA_TX_STOP : R/W; bitpos: [15]; default: 0; + * spi dma write data stop when in continue tx/rx mode. + */ + +#define SPI_DMA_TX_STOP (BIT(15)) +#define SPI_DMA_TX_STOP_M (SPI_DMA_TX_STOP_V << SPI_DMA_TX_STOP_S) +#define SPI_DMA_TX_STOP_V 0x00000001 +#define SPI_DMA_TX_STOP_S 15 + +/* SPI_REG_SPI_REG_DMA_RX_STOP : R/W; bitpos: [14]; default: 0; + * spi dma read data stop when in continue tx/rx mode. + */ + +#define SPI_REG_SPI_REG_DMA_RX_STOP (BIT(14)) +#define SPI_REG_SPI_REG_DMA_RX_STOP_M (SPI_REG_SPI_REG_DMA_RX_STOP_V << SPI_REG_SPI_REG_DMA_RX_STOP_S) +#define SPI_REG_SPI_REG_DMA_RX_STOP_V 0x00000001 +#define SPI_REG_SPI_REG_DMA_RX_STOP_S 14 + +/* SPI_MEM_TRANS_EN : R/W; bitpos: [13]; default: 0; + * DMA internal memory data transfer enable signal. + */ + +#define SPI_MEM_TRANS_EN (BIT(13)) +#define SPI_MEM_TRANS_EN_M (SPI_MEM_TRANS_EN_V << SPI_MEM_TRANS_EN_S) +#define SPI_MEM_TRANS_EN_V 0x00000001 +#define SPI_MEM_TRANS_EN_S 13 + +/* SPI_OUT_DATA_BURST_EN : R/W; bitpos: [12]; default: 0; + * spi dma read data from memory in burst mode. + */ + +#define SPI_OUT_DATA_BURST_EN (BIT(12)) +#define SPI_OUT_DATA_BURST_EN_M (SPI_OUT_DATA_BURST_EN_V << SPI_OUT_DATA_BURST_EN_S) +#define SPI_OUT_DATA_BURST_EN_V 0x00000001 +#define SPI_OUT_DATA_BURST_EN_S 12 + +/* SPI_INDSCR_BURST_EN : R/W; bitpos: [11]; default: 0; + * read descriptor use burst mode when write data to memory. + */ + +#define SPI_INDSCR_BURST_EN (BIT(11)) +#define SPI_INDSCR_BURST_EN_M (SPI_INDSCR_BURST_EN_V << SPI_INDSCR_BURST_EN_S) +#define SPI_INDSCR_BURST_EN_V 0x00000001 +#define SPI_INDSCR_BURST_EN_S 11 + +/* SPI_OUTDSCR_BURST_EN : R/W; bitpos: [10]; default: 0; + * read descriptor use burst mode when read data for memory. + */ + +#define SPI_OUTDSCR_BURST_EN (BIT(10)) +#define SPI_OUTDSCR_BURST_EN_M (SPI_OUTDSCR_BURST_EN_V << SPI_OUTDSCR_BURST_EN_S) +#define SPI_OUTDSCR_BURST_EN_V 0x00000001 +#define SPI_OUTDSCR_BURST_EN_S 10 + +/* SPI_OUT_EOF_MODE : R/W; bitpos: [9]; default: 1; + * out eof flag generation mode . 1: when dma pop all data from fifo 0:when + * ahb push all data to fifo. + */ + +#define SPI_OUT_EOF_MODE (BIT(9)) +#define SPI_OUT_EOF_MODE_M (SPI_OUT_EOF_MODE_V << SPI_OUT_EOF_MODE_S) +#define SPI_OUT_EOF_MODE_V 0x00000001 +#define SPI_OUT_EOF_MODE_S 9 + +/* SPI_OUT_AUTO_WRBACK : R/W; bitpos: [8]; default: 0; + * when the bit is set, DMA continue to use the next inlink node when the + * length of inlink is 0. + */ + +#define SPI_OUT_AUTO_WRBACK (BIT(8)) +#define SPI_OUT_AUTO_WRBACK_M (SPI_OUT_AUTO_WRBACK_V << SPI_OUT_AUTO_WRBACK_S) +#define SPI_OUT_AUTO_WRBACK_V 0x00000001 +#define SPI_OUT_AUTO_WRBACK_S 8 + +/* SPI_OUT_LOOP_TEST : R/W; bitpos: [7]; default: 0; + * Set bit to test out link. + */ + +#define SPI_OUT_LOOP_TEST (BIT(7)) +#define SPI_OUT_LOOP_TEST_M (SPI_OUT_LOOP_TEST_V << SPI_OUT_LOOP_TEST_S) +#define SPI_OUT_LOOP_TEST_V 0x00000001 +#define SPI_OUT_LOOP_TEST_S 7 + +/* SPI_IN_LOOP_TEST : R/W; bitpos: [6]; default: 0; + * Set bit to test in link. + */ + +#define SPI_IN_LOOP_TEST (BIT(6)) +#define SPI_IN_LOOP_TEST_M (SPI_IN_LOOP_TEST_V << SPI_IN_LOOP_TEST_S) +#define SPI_IN_LOOP_TEST_V 0x00000001 +#define SPI_IN_LOOP_TEST_S 6 + +/* SPI_AHBM_RST : R/W; bitpos: [5]; default: 0; + * Reset spi dma ahb master. + */ + +#define SPI_AHBM_RST (BIT(5)) +#define SPI_AHBM_RST_M (SPI_AHBM_RST_V << SPI_AHBM_RST_S) +#define SPI_AHBM_RST_V 0x00000001 +#define SPI_AHBM_RST_S 5 + +/* SPI_AHBM_FIFO_RST : R/W; bitpos: [4]; default: 0; + * Reset spi dma ahb master fifo pointer. + */ + +#define SPI_AHBM_FIFO_RST (BIT(4)) +#define SPI_AHBM_FIFO_RST_M (SPI_AHBM_FIFO_RST_V << SPI_AHBM_FIFO_RST_S) +#define SPI_AHBM_FIFO_RST_V 0x00000001 +#define SPI_AHBM_FIFO_RST_S 4 + +/* SPI_OUT_RST : R/W; bitpos: [3]; default: 0; + * The bit is used to reset out dma fsm and out data fifo pointer. + */ + +#define SPI_OUT_RST (BIT(3)) +#define SPI_OUT_RST_M (SPI_OUT_RST_V << SPI_OUT_RST_S) +#define SPI_OUT_RST_V 0x00000001 +#define SPI_OUT_RST_S 3 + +/* SPI_IN_RST : R/W; bitpos: [2]; default: 0; + * The bit is used to reset in dma fsm and in data fifo pointer. + */ + +#define SPI_IN_RST (BIT(2)) +#define SPI_IN_RST_M (SPI_IN_RST_V << SPI_IN_RST_S) +#define SPI_IN_RST_V 0x00000001 +#define SPI_IN_RST_S 2 + +/* SPI_DMA_OUT_LINK_REG register */ + +#define SPI_DMA_OUT_LINK_REG (DR_REG_SPI_BASE + 0x5c) + +/* SPI_DMA_TX_ENA : R/W; bitpos: [31]; default: 0; + * spi dma write data status bit. + */ + +#define SPI_DMA_TX_ENA (BIT(31)) +#define SPI_DMA_TX_ENA_M (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S) +#define SPI_DMA_TX_ENA_V 0x00000001 +#define SPI_DMA_TX_ENA_S 31 + +/* SPI_OUTLINK_RESTART : R/W; bitpos: [30]; default: 0; + * Set the bit to mount on new outlink descriptors. + */ + +#define SPI_OUTLINK_RESTART (BIT(30)) +#define SPI_OUTLINK_RESTART_M (SPI_OUTLINK_RESTART_V << SPI_OUTLINK_RESTART_S) +#define SPI_OUTLINK_RESTART_V 0x00000001 +#define SPI_OUTLINK_RESTART_S 30 + +/* SPI_OUTLINK_START : R/W; bitpos: [29]; default: 0; + * Set the bit to start to use outlink descriptor. + */ + +#define SPI_OUTLINK_START (BIT(29)) +#define SPI_OUTLINK_START_M (SPI_OUTLINK_START_V << SPI_OUTLINK_START_S) +#define SPI_OUTLINK_START_V 0x00000001 +#define SPI_OUTLINK_START_S 29 + +/* SPI_OUTLINK_STOP : R/W; bitpos: [28]; default: 0; + * Set the bit to stop to use outlink descriptor. + */ + +#define SPI_OUTLINK_STOP (BIT(28)) +#define SPI_OUTLINK_STOP_M (SPI_OUTLINK_STOP_V << SPI_OUTLINK_STOP_S) +#define SPI_OUTLINK_STOP_V 0x00000001 +#define SPI_OUTLINK_STOP_S 28 + +/* SPI_OUTLINK_ADDR : R/W; bitpos: [19:0]; default: 0; + * The address of the first outlink descriptor. + */ + +#define SPI_OUTLINK_ADDR 0x000FFFFF +#define SPI_OUTLINK_ADDR_M (SPI_OUTLINK_ADDR_V << SPI_OUTLINK_ADDR_S) +#define SPI_OUTLINK_ADDR_V 0x000FFFFF +#define SPI_OUTLINK_ADDR_S 0 + +/* SPI_DMA_IN_LINK_REG register */ + +#define SPI_DMA_IN_LINK_REG (DR_REG_SPI_BASE + 0x60) + +/* SPI_DMA_RX_ENA : R/W; bitpos: [31]; default: 0; + * spi dma read data status bit. + */ + +#define SPI_DMA_RX_ENA (BIT(31)) +#define SPI_DMA_RX_ENA_M (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S) +#define SPI_DMA_RX_ENA_V 0x00000001 +#define SPI_DMA_RX_ENA_S 31 + +/* SPI_INLINK_RESTART : R/W; bitpos: [30]; default: 0; + * Set the bit to mount on new inlink descriptors. + */ + +#define SPI_INLINK_RESTART (BIT(30)) +#define SPI_INLINK_RESTART_M (SPI_INLINK_RESTART_V << SPI_INLINK_RESTART_S) +#define SPI_INLINK_RESTART_V 0x00000001 +#define SPI_INLINK_RESTART_S 30 + +/* SPI_INLINK_START : R/W; bitpos: [29]; default: 0; + * Set the bit to start to use inlink descriptor. + */ + +#define SPI_INLINK_START (BIT(29)) +#define SPI_INLINK_START_M (SPI_INLINK_START_V << SPI_INLINK_START_S) +#define SPI_INLINK_START_V 0x00000001 +#define SPI_INLINK_START_S 29 + +/* SPI_INLINK_STOP : R/W; bitpos: [28]; default: 0; + * Set the bit to stop to use inlink descriptor. + */ + +#define SPI_INLINK_STOP (BIT(28)) +#define SPI_INLINK_STOP_M (SPI_INLINK_STOP_V << SPI_INLINK_STOP_S) +#define SPI_INLINK_STOP_V 0x00000001 +#define SPI_INLINK_STOP_S 28 + +/* SPI_INLINK_AUTO_RET : R/W; bitpos: [20]; default: 0; + * when the bit is set, the inlink descriptor returns to the first link node + * when a packet is error. + */ + +#define SPI_INLINK_AUTO_RET (BIT(20)) +#define SPI_INLINK_AUTO_RET_M (SPI_INLINK_AUTO_RET_V << SPI_INLINK_AUTO_RET_S) +#define SPI_INLINK_AUTO_RET_V 0x00000001 +#define SPI_INLINK_AUTO_RET_S 20 + +/* SPI_INLINK_ADDR : R/W; bitpos: [19:0]; default: 0; + * The address of the first inlink descriptor. + */ + +#define SPI_INLINK_ADDR 0x000FFFFF +#define SPI_INLINK_ADDR_M (SPI_INLINK_ADDR_V << SPI_INLINK_ADDR_S) +#define SPI_INLINK_ADDR_V 0x000FFFFF +#define SPI_INLINK_ADDR_S 0 + +/* SPI_DMA_INT_ENA_REG register */ + +#define SPI_DMA_INT_ENA_REG (DR_REG_SPI_BASE + 0x64) + +/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for sending all the packets to host done. + */ + +#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ENA_M (SPI_OUT_TOTAL_EOF_INT_ENA_V << SPI_OUT_TOTAL_EOF_INT_ENA_S) +#define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x00000001 +#define SPI_OUT_TOTAL_EOF_INT_ENA_S 8 + +/* SPI_OUT_EOF_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for sending a packet to host done. + */ + +#define SPI_OUT_EOF_INT_ENA (BIT(7)) +#define SPI_OUT_EOF_INT_ENA_M (SPI_OUT_EOF_INT_ENA_V << SPI_OUT_EOF_INT_ENA_S) +#define SPI_OUT_EOF_INT_ENA_V 0x00000001 +#define SPI_OUT_EOF_INT_ENA_S 7 + +/* SPI_OUT_DONE_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for completing usage of a outlink descriptor . + */ + +#define SPI_OUT_DONE_INT_ENA (BIT(6)) +#define SPI_OUT_DONE_INT_ENA_M (SPI_OUT_DONE_INT_ENA_V << SPI_OUT_DONE_INT_ENA_S) +#define SPI_OUT_DONE_INT_ENA_V 0x00000001 +#define SPI_OUT_DONE_INT_ENA_S 6 + +/* SPI_IN_SUC_EOF_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for completing receiving all the packets from host. + */ + +#define SPI_IN_SUC_EOF_INT_ENA (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ENA_M (SPI_IN_SUC_EOF_INT_ENA_V << SPI_IN_SUC_EOF_INT_ENA_S) +#define SPI_IN_SUC_EOF_INT_ENA_V 0x00000001 +#define SPI_IN_SUC_EOF_INT_ENA_S 5 + +/* SPI_IN_ERR_EOF_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for receiving error. + */ + +#define SPI_IN_ERR_EOF_INT_ENA (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ENA_M (SPI_IN_ERR_EOF_INT_ENA_V << SPI_IN_ERR_EOF_INT_ENA_S) +#define SPI_IN_ERR_EOF_INT_ENA_V 0x00000001 +#define SPI_IN_ERR_EOF_INT_ENA_S 4 + +/* SPI_IN_DONE_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for completing usage of a inlink descriptor. + */ + +#define SPI_IN_DONE_INT_ENA (BIT(3)) +#define SPI_IN_DONE_INT_ENA_M (SPI_IN_DONE_INT_ENA_V << SPI_IN_DONE_INT_ENA_S) +#define SPI_IN_DONE_INT_ENA_V 0x00000001 +#define SPI_IN_DONE_INT_ENA_S 3 + +/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for inlink descriptor error. + */ + +#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ENA_M (SPI_INLINK_DSCR_ERROR_INT_ENA_V << SPI_INLINK_DSCR_ERROR_INT_ENA_S) +#define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x00000001 +#define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2 + +/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for outlink descriptor error. + */ + +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (SPI_OUTLINK_DSCR_ERROR_INT_ENA_V << SPI_OUTLINK_DSCR_ERROR_INT_ENA_S) +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x00000001 +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1 + +/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for lack of enough inlink descriptors. + */ + +#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (SPI_INLINK_DSCR_EMPTY_INT_ENA_V << SPI_INLINK_DSCR_EMPTY_INT_ENA_S) +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x00000001 +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0 + +/* SPI_DMA_INT_RAW_REG register */ + +#define SPI_DMA_INT_RAW_REG (DR_REG_SPI_BASE + 0x68) + +/* SPI_OUT_TOTAL_EOF_INT_RAW : RO; bitpos: [8]; default: 0; + * The raw bit for sending all the packets to host done. + */ + +#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_RAW_M (SPI_OUT_TOTAL_EOF_INT_RAW_V << SPI_OUT_TOTAL_EOF_INT_RAW_S) +#define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x00000001 +#define SPI_OUT_TOTAL_EOF_INT_RAW_S 8 + +/* SPI_OUT_EOF_INT_RAW : RO; bitpos: [7]; default: 0; + * The raw bit for sending a packet to host done. + */ + +#define SPI_OUT_EOF_INT_RAW (BIT(7)) +#define SPI_OUT_EOF_INT_RAW_M (SPI_OUT_EOF_INT_RAW_V << SPI_OUT_EOF_INT_RAW_S) +#define SPI_OUT_EOF_INT_RAW_V 0x00000001 +#define SPI_OUT_EOF_INT_RAW_S 7 + +/* SPI_OUT_DONE_INT_RAW : RO; bitpos: [6]; default: 0; + * The raw bit for completing usage of a outlink descriptor. + */ + +#define SPI_OUT_DONE_INT_RAW (BIT(6)) +#define SPI_OUT_DONE_INT_RAW_M (SPI_OUT_DONE_INT_RAW_V << SPI_OUT_DONE_INT_RAW_S) +#define SPI_OUT_DONE_INT_RAW_V 0x00000001 +#define SPI_OUT_DONE_INT_RAW_S 6 + +/* SPI_IN_SUC_EOF_INT_RAW : RO; bitpos: [5]; default: 0; + * The raw bit for completing receiving all the packets from host. + */ + +#define SPI_IN_SUC_EOF_INT_RAW (BIT(5)) +#define SPI_IN_SUC_EOF_INT_RAW_M (SPI_IN_SUC_EOF_INT_RAW_V << SPI_IN_SUC_EOF_INT_RAW_S) +#define SPI_IN_SUC_EOF_INT_RAW_V 0x00000001 +#define SPI_IN_SUC_EOF_INT_RAW_S 5 + +/* SPI_IN_ERR_EOF_INT_RAW : RO; bitpos: [4]; default: 0; + * The raw bit for receiving error. + */ + +#define SPI_IN_ERR_EOF_INT_RAW (BIT(4)) +#define SPI_IN_ERR_EOF_INT_RAW_M (SPI_IN_ERR_EOF_INT_RAW_V << SPI_IN_ERR_EOF_INT_RAW_S) +#define SPI_IN_ERR_EOF_INT_RAW_V 0x00000001 +#define SPI_IN_ERR_EOF_INT_RAW_S 4 + +/* SPI_IN_DONE_INT_RAW : RO; bitpos: [3]; default: 0; + * The raw bit for completing usage of a inlink descriptor. + */ + +#define SPI_IN_DONE_INT_RAW (BIT(3)) +#define SPI_IN_DONE_INT_RAW_M (SPI_IN_DONE_INT_RAW_V << SPI_IN_DONE_INT_RAW_S) +#define SPI_IN_DONE_INT_RAW_V 0x00000001 +#define SPI_IN_DONE_INT_RAW_S 3 + +/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO; bitpos: [2]; default: 0; + * The raw bit for inlink descriptor error. + */ + +#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_RAW_M (SPI_INLINK_DSCR_ERROR_INT_RAW_V << SPI_INLINK_DSCR_ERROR_INT_RAW_S) +#define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x00000001 +#define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2 + +/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO; bitpos: [1]; default: 0; + * The raw bit for outlink descriptor error. + */ + +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (SPI_OUTLINK_DSCR_ERROR_INT_RAW_V << SPI_OUTLINK_DSCR_ERROR_INT_RAW_S) +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x00000001 +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1 + +/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO; bitpos: [0]; default: 0; + * The raw bit for lack of enough inlink descriptors. + */ + +#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (SPI_INLINK_DSCR_EMPTY_INT_RAW_V << SPI_INLINK_DSCR_EMPTY_INT_RAW_S) +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x00000001 +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0 + +/* SPI_DMA_INT_ST_REG register */ + +#define SPI_DMA_INT_ST_REG (DR_REG_SPI_BASE + 0x6c) + +/* SPI_OUT_TOTAL_EOF_INT_ST : RO; bitpos: [8]; default: 0; + * The status bit for sending all the packets to host done. + */ + +#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ST_M (SPI_OUT_TOTAL_EOF_INT_ST_V << SPI_OUT_TOTAL_EOF_INT_ST_S) +#define SPI_OUT_TOTAL_EOF_INT_ST_V 0x00000001 +#define SPI_OUT_TOTAL_EOF_INT_ST_S 8 + +/* SPI_OUT_EOF_INT_ST : RO; bitpos: [7]; default: 0; + * The status bit for sending a packet to host done. + */ + +#define SPI_OUT_EOF_INT_ST (BIT(7)) +#define SPI_OUT_EOF_INT_ST_M (SPI_OUT_EOF_INT_ST_V << SPI_OUT_EOF_INT_ST_S) +#define SPI_OUT_EOF_INT_ST_V 0x00000001 +#define SPI_OUT_EOF_INT_ST_S 7 + +/* SPI_OUT_DONE_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for completing usage of a outlink descriptor. + */ + +#define SPI_OUT_DONE_INT_ST (BIT(6)) +#define SPI_OUT_DONE_INT_ST_M (SPI_OUT_DONE_INT_ST_V << SPI_OUT_DONE_INT_ST_S) +#define SPI_OUT_DONE_INT_ST_V 0x00000001 +#define SPI_OUT_DONE_INT_ST_S 6 + +/* SPI_IN_SUC_EOF_INT_ST : RO; bitpos: [5]; default: 0; + * The status bit for completing receiving all the packets from host. + */ + +#define SPI_IN_SUC_EOF_INT_ST (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ST_M (SPI_IN_SUC_EOF_INT_ST_V << SPI_IN_SUC_EOF_INT_ST_S) +#define SPI_IN_SUC_EOF_INT_ST_V 0x00000001 +#define SPI_IN_SUC_EOF_INT_ST_S 5 + +/* SPI_IN_ERR_EOF_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for receiving error. + */ + +#define SPI_IN_ERR_EOF_INT_ST (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ST_M (SPI_IN_ERR_EOF_INT_ST_V << SPI_IN_ERR_EOF_INT_ST_S) +#define SPI_IN_ERR_EOF_INT_ST_V 0x00000001 +#define SPI_IN_ERR_EOF_INT_ST_S 4 + +/* SPI_IN_DONE_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for completing usage of a inlink descriptor. + */ + +#define SPI_IN_DONE_INT_ST (BIT(3)) +#define SPI_IN_DONE_INT_ST_M (SPI_IN_DONE_INT_ST_V << SPI_IN_DONE_INT_ST_S) +#define SPI_IN_DONE_INT_ST_V 0x00000001 +#define SPI_IN_DONE_INT_ST_S 3 + +/* SPI_INLINK_DSCR_ERROR_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for inlink descriptor error. + */ + +#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ST_M (SPI_INLINK_DSCR_ERROR_INT_ST_V << SPI_INLINK_DSCR_ERROR_INT_ST_S) +#define SPI_INLINK_DSCR_ERROR_INT_ST_V 0x00000001 +#define SPI_INLINK_DSCR_ERROR_INT_ST_S 2 + +/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for outlink descriptor error. + */ + +#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (SPI_OUTLINK_DSCR_ERROR_INT_ST_V << SPI_OUTLINK_DSCR_ERROR_INT_ST_S) +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x00000001 +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1 + +/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for lack of enough inlink descriptors. + */ + +#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ST_M (SPI_INLINK_DSCR_EMPTY_INT_ST_V << SPI_INLINK_DSCR_EMPTY_INT_ST_S) +#define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x00000001 +#define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0 + +/* SPI_DMA_INT_CLR_REG register */ + +#define SPI_DMA_INT_CLR_REG (DR_REG_SPI_BASE + 0x70) + +/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W; bitpos: [8]; default: 0; + * The clear bit for sending all the packets to host done. + */ + +#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_CLR_M (SPI_OUT_TOTAL_EOF_INT_CLR_V << SPI_OUT_TOTAL_EOF_INT_CLR_S) +#define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x00000001 +#define SPI_OUT_TOTAL_EOF_INT_CLR_S 8 + +/* SPI_OUT_EOF_INT_CLR : R/W; bitpos: [7]; default: 0; + * The clear bit for sending a packet to host done. + */ + +#define SPI_OUT_EOF_INT_CLR (BIT(7)) +#define SPI_OUT_EOF_INT_CLR_M (SPI_OUT_EOF_INT_CLR_V << SPI_OUT_EOF_INT_CLR_S) +#define SPI_OUT_EOF_INT_CLR_V 0x00000001 +#define SPI_OUT_EOF_INT_CLR_S 7 + +/* SPI_OUT_DONE_INT_CLR : R/W; bitpos: [6]; default: 0; + * The clear bit for completing usage of a outlink descriptor. + */ + +#define SPI_OUT_DONE_INT_CLR (BIT(6)) +#define SPI_OUT_DONE_INT_CLR_M (SPI_OUT_DONE_INT_CLR_V << SPI_OUT_DONE_INT_CLR_S) +#define SPI_OUT_DONE_INT_CLR_V 0x00000001 +#define SPI_OUT_DONE_INT_CLR_S 6 + +/* SPI_IN_SUC_EOF_INT_CLR : R/W; bitpos: [5]; default: 0; + * The clear bit for completing receiving all the packets from host. + */ + +#define SPI_IN_SUC_EOF_INT_CLR (BIT(5)) +#define SPI_IN_SUC_EOF_INT_CLR_M (SPI_IN_SUC_EOF_INT_CLR_V << SPI_IN_SUC_EOF_INT_CLR_S) +#define SPI_IN_SUC_EOF_INT_CLR_V 0x00000001 +#define SPI_IN_SUC_EOF_INT_CLR_S 5 + +/* SPI_IN_ERR_EOF_INT_CLR : R/W; bitpos: [4]; default: 0; + * The clear bit for receiving error. + */ + +#define SPI_IN_ERR_EOF_INT_CLR (BIT(4)) +#define SPI_IN_ERR_EOF_INT_CLR_M (SPI_IN_ERR_EOF_INT_CLR_V << SPI_IN_ERR_EOF_INT_CLR_S) +#define SPI_IN_ERR_EOF_INT_CLR_V 0x00000001 +#define SPI_IN_ERR_EOF_INT_CLR_S 4 + +/* SPI_IN_DONE_INT_CLR : R/W; bitpos: [3]; default: 0; + * The clear bit for completing usage of a inlink descriptor. + */ + +#define SPI_IN_DONE_INT_CLR (BIT(3)) +#define SPI_IN_DONE_INT_CLR_M (SPI_IN_DONE_INT_CLR_V << SPI_IN_DONE_INT_CLR_S) +#define SPI_IN_DONE_INT_CLR_V 0x00000001 +#define SPI_IN_DONE_INT_CLR_S 3 + +/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W; bitpos: [2]; default: 0; + * The clear bit for inlink descriptor error. + */ + +#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_CLR_M (SPI_INLINK_DSCR_ERROR_INT_CLR_V << SPI_INLINK_DSCR_ERROR_INT_CLR_S) +#define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x00000001 +#define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2 + +/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W; bitpos: [1]; default: 0; + * The clear bit for outlink descriptor error. + */ + +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (SPI_OUTLINK_DSCR_ERROR_INT_CLR_V << SPI_OUTLINK_DSCR_ERROR_INT_CLR_S) +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x00000001 +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1 + +/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W; bitpos: [0]; default: 0; + * The clear bit for lack of enough inlink descriptors. + */ + +#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (SPI_INLINK_DSCR_EMPTY_INT_CLR_V << SPI_INLINK_DSCR_EMPTY_INT_CLR_S) +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x00000001 +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0 + +/* SPI_IN_ERR_EOF_DES_ADDR_REG register */ + +#define SPI_IN_ERR_EOF_DES_ADDR_REG (DR_REG_SPI_BASE + 0x74) + +/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The inlink descriptor address when spi dma produce receiving error. + */ + +#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M (SPI_DMA_IN_ERR_EOF_DES_ADDR_V << SPI_DMA_IN_ERR_EOF_DES_ADDR_S) +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0 + +/* SPI_IN_SUC_EOF_DES_ADDR_REG register */ + +#define SPI_IN_SUC_EOF_DES_ADDR_REG (DR_REG_SPI_BASE + 0x78) + +/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The last inlink descriptor address when spi dma produce from_suc_eof. + */ + +#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M (SPI_DMA_IN_SUC_EOF_DES_ADDR_V << SPI_DMA_IN_SUC_EOF_DES_ADDR_S) +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0 + +/* SPI_INLINK_DSCR_REG register */ + +#define SPI_INLINK_DSCR_REG (DR_REG_SPI_BASE + 0x7c) + +/* SPI_DMA_INLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * The content of current in descriptor pointer. + */ + +#define SPI_DMA_INLINK_DSCR 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_M (SPI_DMA_INLINK_DSCR_V << SPI_DMA_INLINK_DSCR_S) +#define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_S 0 + +/* SPI_INLINK_DSCR_BF0_REG register */ + +#define SPI_INLINK_DSCR_BF0_REG (DR_REG_SPI_BASE + 0x80) + +/* SPI_DMA_INLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * The content of next in descriptor pointer. + */ + +#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF0_M (SPI_DMA_INLINK_DSCR_BF0_V << SPI_DMA_INLINK_DSCR_BF0_S) +#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF0_S 0 + +/* SPI_INLINK_DSCR_BF1_REG register */ + +#define SPI_INLINK_DSCR_BF1_REG (DR_REG_SPI_BASE + 0x84) + +/* SPI_DMA_INLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * The content of current in descriptor data buffer pointer. + */ + +#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF1_M (SPI_DMA_INLINK_DSCR_BF1_V << SPI_DMA_INLINK_DSCR_BF1_S) +#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF1_S 0 + +/* SPI_OUT_EOF_BFR_DES_ADDR_REG register */ + +#define SPI_OUT_EOF_BFR_DES_ADDR_REG (DR_REG_SPI_BASE + 0x88) + +/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The address of buffer relative to the outlink descriptor that produce eof. + */ + +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M (SPI_DMA_OUT_EOF_BFR_DES_ADDR_V << SPI_DMA_OUT_EOF_BFR_DES_ADDR_S) +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0 + +/* SPI_OUT_EOF_DES_ADDR_REG register */ + +#define SPI_OUT_EOF_DES_ADDR_REG (DR_REG_SPI_BASE + 0x8c) + +/* SPI_DMA_OUT_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The last outlink descriptor address when spi dma produce to_eof. + */ + +#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_DES_ADDR_M (SPI_DMA_OUT_EOF_DES_ADDR_V << SPI_DMA_OUT_EOF_DES_ADDR_S) +#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_DES_ADDR_S 0 + +/* SPI_OUTLINK_DSCR_REG register */ + +#define SPI_OUTLINK_DSCR_REG (DR_REG_SPI_BASE + 0x90) + +/* SPI_DMA_OUTLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * The content of current out descriptor pointer. + */ + +#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_M (SPI_DMA_OUTLINK_DSCR_V << SPI_DMA_OUTLINK_DSCR_S) +#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_S 0 + +/* SPI_OUTLINK_DSCR_BF0_REG register */ + +#define SPI_OUTLINK_DSCR_BF0_REG (DR_REG_SPI_BASE + 0x94) + +/* SPI_DMA_OUTLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * The content of next out descriptor pointer. + */ + +#define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF0_M (SPI_DMA_OUTLINK_DSCR_BF0_V << SPI_DMA_OUTLINK_DSCR_BF0_S) +#define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF0_S 0 + +/* SPI_OUTLINK_DSCR_BF1_REG register */ + +#define SPI_OUTLINK_DSCR_BF1_REG (DR_REG_SPI_BASE + 0x98) + +/* SPI_DMA_OUTLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * The content of current out descriptor data buffer pointer. + */ + +#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF1_M (SPI_DMA_OUTLINK_DSCR_BF1_V << SPI_DMA_OUTLINK_DSCR_BF1_S) +#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF1_S 0 + +/* SPI_DMA_OUTSTATUS_REG register */ + +#define SPI_DMA_OUTSTATUS_REG (DR_REG_SPI_BASE + 0x9c) + +/* SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [31]; default: 1; + * SPI dma outfifo is empty. + */ + +#define SPI_DMA_OUTFIFO_EMPTY (BIT(31)) +#define SPI_DMA_OUTFIFO_EMPTY_M (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S) +#define SPI_DMA_OUTFIFO_EMPTY_V 0x00000001 +#define SPI_DMA_OUTFIFO_EMPTY_S 31 + +/* SPI_DMA_OUTFIFO_FULL : RO; bitpos: [30]; default: 0; + * SPI dma outfifo is full. + */ + +#define SPI_DMA_OUTFIFO_FULL (BIT(30)) +#define SPI_DMA_OUTFIFO_FULL_M (SPI_DMA_OUTFIFO_FULL_V << SPI_DMA_OUTFIFO_FULL_S) +#define SPI_DMA_OUTFIFO_FULL_V 0x00000001 +#define SPI_DMA_OUTFIFO_FULL_S 30 + +/* SPI_DMA_OUTFIFO_CNT : RO; bitpos: [29:23]; default: 0; + * The remains of SPI dma outfifo data. + */ + +#define SPI_DMA_OUTFIFO_CNT 0x0000007F +#define SPI_DMA_OUTFIFO_CNT_M (SPI_DMA_OUTFIFO_CNT_V << SPI_DMA_OUTFIFO_CNT_S) +#define SPI_DMA_OUTFIFO_CNT_V 0x0000007F +#define SPI_DMA_OUTFIFO_CNT_S 23 + +/* SPI_DMA_OUT_STATE : RO; bitpos: [22:20]; default: 0; + * SPI dma out data state. + */ + +#define SPI_DMA_OUT_STATE 0x00000007 +#define SPI_DMA_OUT_STATE_M (SPI_DMA_OUT_STATE_V << SPI_DMA_OUT_STATE_S) +#define SPI_DMA_OUT_STATE_V 0x00000007 +#define SPI_DMA_OUT_STATE_S 20 + +/* SPI_DMA_OUTDSCR_STATE : RO; bitpos: [19:18]; default: 0; + * SPI dma out descriptor state. + */ + +#define SPI_DMA_OUTDSCR_STATE 0x00000003 +#define SPI_DMA_OUTDSCR_STATE_M (SPI_DMA_OUTDSCR_STATE_V << SPI_DMA_OUTDSCR_STATE_S) +#define SPI_DMA_OUTDSCR_STATE_V 0x00000003 +#define SPI_DMA_OUTDSCR_STATE_S 18 + +/* SPI_DMA_OUTDSCR_ADDR : RO; bitpos: [17:0]; default: 0; + * SPI dma out descriptor address. + */ + +#define SPI_DMA_OUTDSCR_ADDR 0x0003FFFF +#define SPI_DMA_OUTDSCR_ADDR_M (SPI_DMA_OUTDSCR_ADDR_V << SPI_DMA_OUTDSCR_ADDR_S) +#define SPI_DMA_OUTDSCR_ADDR_V 0x0003FFFF +#define SPI_DMA_OUTDSCR_ADDR_S 0 + +/* SPI_DMA_INSTATUS_REG register */ + +#define SPI_DMA_INSTATUS_REG (DR_REG_SPI_BASE + 0xa0) + +/* SPI_DMA_INFIFO_EMPTY : RO; bitpos: [31]; default: 1; + * SPI dma infifo is empty. + */ + +#define SPI_DMA_INFIFO_EMPTY (BIT(31)) +#define SPI_DMA_INFIFO_EMPTY_M (SPI_DMA_INFIFO_EMPTY_V << SPI_DMA_INFIFO_EMPTY_S) +#define SPI_DMA_INFIFO_EMPTY_V 0x00000001 +#define SPI_DMA_INFIFO_EMPTY_S 31 + +/* SPI_DMA_INFIFO_FULL : RO; bitpos: [30]; default: 0; + * SPI dma infifo is full. + */ + +#define SPI_DMA_INFIFO_FULL (BIT(30)) +#define SPI_DMA_INFIFO_FULL_M (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S) +#define SPI_DMA_INFIFO_FULL_V 0x00000001 +#define SPI_DMA_INFIFO_FULL_S 30 + +/* SPI_DMA_INFIFO_CNT : RO; bitpos: [29:23]; default: 0; + * The remains of SPI dma infifo data. + */ + +#define SPI_DMA_INFIFO_CNT 0x0000007F +#define SPI_DMA_INFIFO_CNT_M (SPI_DMA_INFIFO_CNT_V << SPI_DMA_INFIFO_CNT_S) +#define SPI_DMA_INFIFO_CNT_V 0x0000007F +#define SPI_DMA_INFIFO_CNT_S 23 + +/* SPI_DMA_IN_STATE : RO; bitpos: [22:20]; default: 0; + * SPI dma in data state. + */ + +#define SPI_DMA_IN_STATE 0x00000007 +#define SPI_DMA_IN_STATE_M (SPI_DMA_IN_STATE_V << SPI_DMA_IN_STATE_S) +#define SPI_DMA_IN_STATE_V 0x00000007 +#define SPI_DMA_IN_STATE_S 20 + +/* SPI_DMA_INDSCR_STATE : RO; bitpos: [19:18]; default: 0; + * SPI dma in descriptor state. + */ + +#define SPI_DMA_INDSCR_STATE 0x00000003 +#define SPI_DMA_INDSCR_STATE_M (SPI_DMA_INDSCR_STATE_V << SPI_DMA_INDSCR_STATE_S) +#define SPI_DMA_INDSCR_STATE_V 0x00000003 +#define SPI_DMA_INDSCR_STATE_S 18 + +/* SPI_DMA_INDSCR_ADDR : RO; bitpos: [17:0]; default: 0; + * SPI dma in descriptor address. + */ + +#define SPI_DMA_INDSCR_ADDR 0x0003FFFF +#define SPI_DMA_INDSCR_ADDR_M (SPI_DMA_INDSCR_ADDR_V << SPI_DMA_INDSCR_ADDR_S) +#define SPI_DMA_INDSCR_ADDR_V 0x0003FFFF +#define SPI_DMA_INDSCR_ADDR_S 0 + +/* SPI_W0_REG register */ + +#define SPI_W0_REG (DR_REG_SPI_BASE + 0xa4) + +/* SPI_BUF0 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF0 0xFFFFFFFF +#define SPI_BUF0_M (SPI_BUF0_V << SPI_BUF0_S) +#define SPI_BUF0_V 0xFFFFFFFF +#define SPI_BUF0_S 0 + +/* SPI_W1_REG register */ + +#define SPI_W1_REG (DR_REG_SPI_BASE + 0xa8) + +/* SPI_BUF1 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF1 0xFFFFFFFF +#define SPI_BUF1_M (SPI_BUF1_V << SPI_BUF1_S) +#define SPI_BUF1_V 0xFFFFFFFF +#define SPI_BUF1_S 0 + +/* SPI_W2_REG register */ + +#define SPI_W2_REG (DR_REG_SPI_BASE + 0xac) + +/* SPI_BUF2 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF2 0xFFFFFFFF +#define SPI_BUF2_M (SPI_BUF2_V << SPI_BUF2_S) +#define SPI_BUF2_V 0xFFFFFFFF +#define SPI_BUF2_S 0 + +/* SPI_W3_REG register */ + +#define SPI_W3_REG (DR_REG_SPI_BASE + 0xb0) + +/* SPI_BUF3 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF3 0xFFFFFFFF +#define SPI_BUF3_M (SPI_BUF3_V << SPI_BUF3_S) +#define SPI_BUF3_V 0xFFFFFFFF +#define SPI_BUF3_S 0 + +/* SPI_W4_REG register */ + +#define SPI_W4_REG (DR_REG_SPI_BASE + 0xb4) + +/* SPI_BUF4 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF4 0xFFFFFFFF +#define SPI_BUF4_M (SPI_BUF4_V << SPI_BUF4_S) +#define SPI_BUF4_V 0xFFFFFFFF +#define SPI_BUF4_S 0 + +/* SPI_W5_REG register */ + +#define SPI_W5_REG (DR_REG_SPI_BASE + 0xb8) + +/* SPI_BUF5 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF5 0xFFFFFFFF +#define SPI_BUF5_M (SPI_BUF5_V << SPI_BUF5_S) +#define SPI_BUF5_V 0xFFFFFFFF +#define SPI_BUF5_S 0 + +/* SPI_W6_REG register */ + +#define SPI_W6_REG (DR_REG_SPI_BASE + 0xbc) + +/* SPI_BUF6 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF6 0xFFFFFFFF +#define SPI_BUF6_M (SPI_BUF6_V << SPI_BUF6_S) +#define SPI_BUF6_V 0xFFFFFFFF +#define SPI_BUF6_S 0 + +/* SPI_W7_REG register */ + +#define SPI_W7_REG (DR_REG_SPI_BASE + 0xc0) + +/* SPI_BUF7 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF7 0xFFFFFFFF +#define SPI_BUF7_M (SPI_BUF7_V << SPI_BUF7_S) +#define SPI_BUF7_V 0xFFFFFFFF +#define SPI_BUF7_S 0 + +/* SPI_W8_REG register */ + +#define SPI_W8_REG (DR_REG_SPI_BASE + 0xc4) + +/* SPI_BUF8 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF8 0xFFFFFFFF +#define SPI_BUF8_M (SPI_BUF8_V << SPI_BUF8_S) +#define SPI_BUF8_V 0xFFFFFFFF +#define SPI_BUF8_S 0 + +/* SPI_W9_REG register */ + +#define SPI_W9_REG (DR_REG_SPI_BASE + 0xc8) + +/* SPI_BUF9 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF9 0xFFFFFFFF +#define SPI_BUF9_M (SPI_BUF9_V << SPI_BUF9_S) +#define SPI_BUF9_V 0xFFFFFFFF +#define SPI_BUF9_S 0 + +/* SPI_W10_REG register */ + +#define SPI_W10_REG (DR_REG_SPI_BASE + 0xcc) + +/* SPI_BUF10 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF10 0xFFFFFFFF +#define SPI_BUF10_M (SPI_BUF10_V << SPI_BUF10_S) +#define SPI_BUF10_V 0xFFFFFFFF +#define SPI_BUF10_S 0 + +/* SPI_W11_REG register */ + +#define SPI_W11_REG (DR_REG_SPI_BASE + 0xd0) + +/* SPI_BUF11 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF11 0xFFFFFFFF +#define SPI_BUF11_M (SPI_BUF11_V << SPI_BUF11_S) +#define SPI_BUF11_V 0xFFFFFFFF +#define SPI_BUF11_S 0 + +/* SPI_W12_REG register */ + +#define SPI_W12_REG (DR_REG_SPI_BASE + 0xd4) + +/* SPI_BUF12 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF12 0xFFFFFFFF +#define SPI_BUF12_M (SPI_BUF12_V << SPI_BUF12_S) +#define SPI_BUF12_V 0xFFFFFFFF +#define SPI_BUF12_S 0 + +/* SPI_W13_REG register */ + +#define SPI_W13_REG (DR_REG_SPI_BASE + 0xd8) + +/* SPI_BUF13 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF13 0xFFFFFFFF +#define SPI_BUF13_M (SPI_BUF13_V << SPI_BUF13_S) +#define SPI_BUF13_V 0xFFFFFFFF +#define SPI_BUF13_S 0 + +/* SPI_W14_REG register */ + +#define SPI_W14_REG (DR_REG_SPI_BASE + 0xdc) + +/* SPI_BUF14 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF14 0xFFFFFFFF +#define SPI_BUF14_M (SPI_BUF14_V << SPI_BUF14_S) +#define SPI_BUF14_V 0xFFFFFFFF +#define SPI_BUF14_S 0 + +/* SPI_W15_REG register */ + +#define SPI_W15_REG (DR_REG_SPI_BASE + 0xe0) + +/* SPI_BUF15 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF15 0xFFFFFFFF +#define SPI_BUF15_M (SPI_BUF15_V << SPI_BUF15_S) +#define SPI_BUF15_V 0xFFFFFFFF +#define SPI_BUF15_S 0 + +/* SPI_W16_REG register */ + +#define SPI_W16_REG (DR_REG_SPI_BASE + 0xe4) + +/* SPI_BUF16 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF16 0xFFFFFFFF +#define SPI_BUF16_M (SPI_BUF16_V << SPI_BUF16_S) +#define SPI_BUF16_V 0xFFFFFFFF +#define SPI_BUF16_S 0 + +/* SPI_W17_REG register */ + +#define SPI_W17_REG (DR_REG_SPI_BASE + 0xe8) + +/* SPI_BUF17 : R/W; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF17 0xFFFFFFFF +#define SPI_BUF17_M (SPI_BUF17_V << SPI_BUF17_S) +#define SPI_BUF17_V 0xFFFFFFFF +#define SPI_BUF17_S 0 + +/* SPI_DIN_MODE_REG register */ + +#define SPI_DIN_MODE_REG (DR_REG_SPI_BASE + 0xec) + +/* SPI_TIMING_CLK_ENA : R/W; bitpos: [24]; default: 0; + * 1:enable hclk in spi_timing.v. 0: disable it. + */ + +#define SPI_TIMING_CLK_ENA (BIT(24)) +#define SPI_TIMING_CLK_ENA_M (SPI_TIMING_CLK_ENA_V << SPI_TIMING_CLK_ENA_S) +#define SPI_TIMING_CLK_ENA_V 0x00000001 +#define SPI_TIMING_CLK_ENA_S 24 + +/* SPI_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN7_MODE 0x00000007 +#define SPI_DIN7_MODE_M (SPI_DIN7_MODE_V << SPI_DIN7_MODE_S) +#define SPI_DIN7_MODE_V 0x00000007 +#define SPI_DIN7_MODE_S 21 + +/* SPI_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN6_MODE 0x00000007 +#define SPI_DIN6_MODE_M (SPI_DIN6_MODE_V << SPI_DIN6_MODE_S) +#define SPI_DIN6_MODE_V 0x00000007 +#define SPI_DIN6_MODE_S 18 + +/* SPI_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN5_MODE 0x00000007 +#define SPI_DIN5_MODE_M (SPI_DIN5_MODE_V << SPI_DIN5_MODE_S) +#define SPI_DIN5_MODE_V 0x00000007 +#define SPI_DIN5_MODE_S 15 + +/* SPI_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN4_MODE 0x00000007 +#define SPI_DIN4_MODE_M (SPI_DIN4_MODE_V << SPI_DIN4_MODE_S) +#define SPI_DIN4_MODE_V 0x00000007 +#define SPI_DIN4_MODE_S 12 + +/* SPI_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN3_MODE 0x00000007 +#define SPI_DIN3_MODE_M (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S) +#define SPI_DIN3_MODE_V 0x00000007 +#define SPI_DIN3_MODE_S 9 + +/* SPI_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN2_MODE 0x00000007 +#define SPI_DIN2_MODE_M (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S) +#define SPI_DIN2_MODE_V 0x00000007 +#define SPI_DIN2_MODE_S 6 + +/* SPI_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN1_MODE 0x00000007 +#define SPI_DIN1_MODE_M (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S) +#define SPI_DIN1_MODE_V 0x00000007 +#define SPI_DIN1_MODE_S 3 + +/* SPI_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; + * Configure the input signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DIN0_MODE 0x00000007 +#define SPI_DIN0_MODE_M (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S) +#define SPI_DIN0_MODE_V 0x00000007 +#define SPI_DIN0_MODE_S 0 + +/* SPI_DIN_NUM_REG register */ + +#define SPI_DIN_NUM_REG (DR_REG_SPI_BASE + 0xf0) + +/* SPI_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN7_NUM 0x00000003 +#define SPI_DIN7_NUM_M (SPI_DIN7_NUM_V << SPI_DIN7_NUM_S) +#define SPI_DIN7_NUM_V 0x00000003 +#define SPI_DIN7_NUM_S 14 + +/* SPI_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN6_NUM 0x00000003 +#define SPI_DIN6_NUM_M (SPI_DIN6_NUM_V << SPI_DIN6_NUM_S) +#define SPI_DIN6_NUM_V 0x00000003 +#define SPI_DIN6_NUM_S 12 + +/* SPI_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN5_NUM 0x00000003 +#define SPI_DIN5_NUM_M (SPI_DIN5_NUM_V << SPI_DIN5_NUM_S) +#define SPI_DIN5_NUM_V 0x00000003 +#define SPI_DIN5_NUM_S 10 + +/* SPI_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN4_NUM 0x00000003 +#define SPI_DIN4_NUM_M (SPI_DIN4_NUM_V << SPI_DIN4_NUM_S) +#define SPI_DIN4_NUM_V 0x00000003 +#define SPI_DIN4_NUM_S 8 + +/* SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN3_NUM 0x00000003 +#define SPI_DIN3_NUM_M (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S) +#define SPI_DIN3_NUM_V 0x00000003 +#define SPI_DIN3_NUM_S 6 + +/* SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN2_NUM 0x00000003 +#define SPI_DIN2_NUM_M (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S) +#define SPI_DIN2_NUM_V 0x00000003 +#define SPI_DIN2_NUM_S 4 + +/* SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN1_NUM 0x00000003 +#define SPI_DIN1_NUM_M (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S) +#define SPI_DIN1_NUM_V 0x00000003 +#define SPI_DIN1_NUM_S 2 + +/* SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DIN0_NUM 0x00000003 +#define SPI_DIN0_NUM_M (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S) +#define SPI_DIN0_NUM_V 0x00000003 +#define SPI_DIN0_NUM_S 0 + +/* SPI_DOUT_MODE_REG register */ + +#define SPI_DOUT_MODE_REG (DR_REG_SPI_BASE + 0xf4) + +/* SPI_DOUT7_MODE : R/W; bitpos: [23:21]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT7_MODE 0x00000007 +#define SPI_DOUT7_MODE_M (SPI_DOUT7_MODE_V << SPI_DOUT7_MODE_S) +#define SPI_DOUT7_MODE_V 0x00000007 +#define SPI_DOUT7_MODE_S 21 + +/* SPI_DOUT6_MODE : R/W; bitpos: [20:18]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT6_MODE 0x00000007 +#define SPI_DOUT6_MODE_M (SPI_DOUT6_MODE_V << SPI_DOUT6_MODE_S) +#define SPI_DOUT6_MODE_V 0x00000007 +#define SPI_DOUT6_MODE_S 18 + +/* SPI_DOUT5_MODE : R/W; bitpos: [17:15]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT5_MODE 0x00000007 +#define SPI_DOUT5_MODE_M (SPI_DOUT5_MODE_V << SPI_DOUT5_MODE_S) +#define SPI_DOUT5_MODE_V 0x00000007 +#define SPI_DOUT5_MODE_S 15 + +/* SPI_DOUT4_MODE : R/W; bitpos: [14:12]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT4_MODE 0x00000007 +#define SPI_DOUT4_MODE_M (SPI_DOUT4_MODE_V << SPI_DOUT4_MODE_S) +#define SPI_DOUT4_MODE_V 0x00000007 +#define SPI_DOUT4_MODE_S 12 + +/* SPI_DOUT3_MODE : R/W; bitpos: [11:9]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT3_MODE 0x00000007 +#define SPI_DOUT3_MODE_M (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S) +#define SPI_DOUT3_MODE_V 0x00000007 +#define SPI_DOUT3_MODE_S 9 + +/* SPI_DOUT2_MODE : R/W; bitpos: [8:6]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT2_MODE 0x00000007 +#define SPI_DOUT2_MODE_M (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S) +#define SPI_DOUT2_MODE_V 0x00000007 +#define SPI_DOUT2_MODE_S 6 + +/* SPI_DOUT1_MODE : R/W; bitpos: [5:3]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT1_MODE 0x00000007 +#define SPI_DOUT1_MODE_M (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S) +#define SPI_DOUT1_MODE_V 0x00000007 +#define SPI_DOUT1_MODE_S 3 + +/* SPI_DOUT0_MODE : R/W; bitpos: [2:0]; default: 0; + * Configure the output signal delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_DOUT0_MODE 0x00000007 +#define SPI_DOUT0_MODE_M (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S) +#define SPI_DOUT0_MODE_V 0x00000007 +#define SPI_DOUT0_MODE_S 0 + +/* SPI_DOUT_NUM_REG register */ + +#define SPI_DOUT_NUM_REG (DR_REG_SPI_BASE + 0xf8) + +/* SPI_DOUT7_NUM : R/W; bitpos: [15:14]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT7_NUM 0x00000003 +#define SPI_DOUT7_NUM_M (SPI_DOUT7_NUM_V << SPI_DOUT7_NUM_S) +#define SPI_DOUT7_NUM_V 0x00000003 +#define SPI_DOUT7_NUM_S 14 + +/* SPI_DOUT6_NUM : R/W; bitpos: [13:12]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT6_NUM 0x00000003 +#define SPI_DOUT6_NUM_M (SPI_DOUT6_NUM_V << SPI_DOUT6_NUM_S) +#define SPI_DOUT6_NUM_V 0x00000003 +#define SPI_DOUT6_NUM_S 12 + +/* SPI_DOUT5_NUM : R/W; bitpos: [11:10]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT5_NUM 0x00000003 +#define SPI_DOUT5_NUM_M (SPI_DOUT5_NUM_V << SPI_DOUT5_NUM_S) +#define SPI_DOUT5_NUM_V 0x00000003 +#define SPI_DOUT5_NUM_S 10 + +/* SPI_DOUT4_NUM : R/W; bitpos: [9:8]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT4_NUM 0x00000003 +#define SPI_DOUT4_NUM_M (SPI_DOUT4_NUM_V << SPI_DOUT4_NUM_S) +#define SPI_DOUT4_NUM_V 0x00000003 +#define SPI_DOUT4_NUM_S 8 + +/* SPI_DOUT3_NUM : R/W; bitpos: [7:6]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT3_NUM 0x00000003 +#define SPI_DOUT3_NUM_M (SPI_DOUT3_NUM_V << SPI_DOUT3_NUM_S) +#define SPI_DOUT3_NUM_V 0x00000003 +#define SPI_DOUT3_NUM_S 6 + +/* SPI_DOUT2_NUM : R/W; bitpos: [5:4]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT2_NUM 0x00000003 +#define SPI_DOUT2_NUM_M (SPI_DOUT2_NUM_V << SPI_DOUT2_NUM_S) +#define SPI_DOUT2_NUM_V 0x00000003 +#define SPI_DOUT2_NUM_S 4 + +/* SPI_DOUT1_NUM : R/W; bitpos: [3:2]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT1_NUM 0x00000003 +#define SPI_DOUT1_NUM_M (SPI_DOUT1_NUM_V << SPI_DOUT1_NUM_S) +#define SPI_DOUT1_NUM_V 0x00000003 +#define SPI_DOUT1_NUM_S 2 + +/* SPI_DOUT0_NUM : R/W; bitpos: [1:0]; default: 0; + * the output signals are delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_DOUT0_NUM 0x00000003 +#define SPI_DOUT0_NUM_M (SPI_DOUT0_NUM_V << SPI_DOUT0_NUM_S) +#define SPI_DOUT0_NUM_V 0x00000003 +#define SPI_DOUT0_NUM_S 0 + +/* SPI_LCD_CTRL_REG register */ + +#define SPI_LCD_CTRL_REG (DR_REG_SPI_BASE + 0xfc) + +/* SPI_LCD_SRGB_MODE_EN : R/W; bitpos: [31]; default: 0; + * 1: Enable LCD mode output vsync, hsync, de. 0: Disable. + */ + +#define SPI_LCD_SRGB_MODE_EN (BIT(31)) +#define SPI_LCD_SRGB_MODE_EN_M (SPI_LCD_SRGB_MODE_EN_V << SPI_LCD_SRGB_MODE_EN_S) +#define SPI_LCD_SRGB_MODE_EN_V 0x00000001 +#define SPI_LCD_SRGB_MODE_EN_S 31 + +/* SPI_LCD_VT_HEIGHT : R/W; bitpos: [30:21]; default: 0; + * It is the vertical total height of a frame. + */ + +#define SPI_LCD_VT_HEIGHT 0x000003FF +#define SPI_LCD_VT_HEIGHT_M (SPI_LCD_VT_HEIGHT_V << SPI_LCD_VT_HEIGHT_S) +#define SPI_LCD_VT_HEIGHT_V 0x000003FF +#define SPI_LCD_VT_HEIGHT_S 21 + +/* SPI_LCD_VA_HEIGHT : R/W; bitpos: [20:11]; default: 0; + * It is the vertical active height of a frame. + */ + +#define SPI_LCD_VA_HEIGHT 0x000003FF +#define SPI_LCD_VA_HEIGHT_M (SPI_LCD_VA_HEIGHT_V << SPI_LCD_VA_HEIGHT_S) +#define SPI_LCD_VA_HEIGHT_V 0x000003FF +#define SPI_LCD_VA_HEIGHT_S 11 + +/* SPI_LCD_HB_FRONT : R/W; bitpos: [10:0]; default: 0; + * It is the horizontal blank front porch of a frame. + */ + +#define SPI_LCD_HB_FRONT 0x000007FF +#define SPI_LCD_HB_FRONT_M (SPI_LCD_HB_FRONT_V << SPI_LCD_HB_FRONT_S) +#define SPI_LCD_HB_FRONT_V 0x000007FF +#define SPI_LCD_HB_FRONT_S 0 + +/* SPI_LCD_CTRL1_REG register */ + +#define SPI_LCD_CTRL1_REG (DR_REG_SPI_BASE + 0x100) + +/* SPI_LCD_HT_WIDTH : R/W; bitpos: [31:20]; default: 0; + * It is the horizontal total width of a frame. + */ + +#define SPI_LCD_HT_WIDTH 0x00000FFF +#define SPI_LCD_HT_WIDTH_M (SPI_LCD_HT_WIDTH_V << SPI_LCD_HT_WIDTH_S) +#define SPI_LCD_HT_WIDTH_V 0x00000FFF +#define SPI_LCD_HT_WIDTH_S 20 + +/* SPI_LCD_HA_WIDTH : R/W; bitpos: [19:8]; default: 0; + * It is the horizontal active width of a frame. + */ + +#define SPI_LCD_HA_WIDTH 0x00000FFF +#define SPI_LCD_HA_WIDTH_M (SPI_LCD_HA_WIDTH_V << SPI_LCD_HA_WIDTH_S) +#define SPI_LCD_HA_WIDTH_V 0x00000FFF +#define SPI_LCD_HA_WIDTH_S 8 + +/* SPI_LCD_VB_FRONT : R/W; bitpos: [7:0]; default: 0; + * It is the vertical blank front porch of a frame. + */ + +#define SPI_LCD_VB_FRONT 0x000000FF +#define SPI_LCD_VB_FRONT_M (SPI_LCD_VB_FRONT_V << SPI_LCD_VB_FRONT_S) +#define SPI_LCD_VB_FRONT_V 0x000000FF +#define SPI_LCD_VB_FRONT_S 0 + +/* SPI_LCD_CTRL2_REG register */ + +#define SPI_LCD_CTRL2_REG (DR_REG_SPI_BASE + 0x104) + +/* SPI_LCD_HSYNC_POSITION : R/W; bitpos: [31:24]; default: 0; + * It is the position of spi_hsync_out active pulse in a line. + */ + +#define SPI_LCD_HSYNC_POSITION 0x000000FF +#define SPI_LCD_HSYNC_POSITION_M (SPI_LCD_HSYNC_POSITION_V << SPI_LCD_HSYNC_POSITION_S) +#define SPI_LCD_HSYNC_POSITION_V 0x000000FF +#define SPI_LCD_HSYNC_POSITION_S 24 + +/* SPI_HSYNC_IDLE_POL : R/W; bitpos: [23]; default: 0; + * It is the idle value of spi_hsync_out. + */ + +#define SPI_HSYNC_IDLE_POL (BIT(23)) +#define SPI_HSYNC_IDLE_POL_M (SPI_HSYNC_IDLE_POL_V << SPI_HSYNC_IDLE_POL_S) +#define SPI_HSYNC_IDLE_POL_V 0x00000001 +#define SPI_HSYNC_IDLE_POL_S 23 + +/* SPI_LCD_HSYNC_WIDTH : R/W; bitpos: [22:16]; default: 0; + * It is the position of spi_hsync_out active pulse in a line. + */ + +#define SPI_LCD_HSYNC_WIDTH 0x0000007F +#define SPI_LCD_HSYNC_WIDTH_M (SPI_LCD_HSYNC_WIDTH_V << SPI_LCD_HSYNC_WIDTH_S) +#define SPI_LCD_HSYNC_WIDTH_V 0x0000007F +#define SPI_LCD_HSYNC_WIDTH_S 16 + +/* SPI_LCD_VSYNC_POSITION : R/W; bitpos: [15:8]; default: 0; + * It is the position of spi_vsync_out active pulse in a line. + */ + +#define SPI_LCD_VSYNC_POSITION 0x000000FF +#define SPI_LCD_VSYNC_POSITION_M (SPI_LCD_VSYNC_POSITION_V << SPI_LCD_VSYNC_POSITION_S) +#define SPI_LCD_VSYNC_POSITION_V 0x000000FF +#define SPI_LCD_VSYNC_POSITION_S 8 + +/* SPI_VSYNC_IDLE_POL : R/W; bitpos: [7]; default: 0; + * It is the idle value of spi_vsync_out. + */ + +#define SPI_VSYNC_IDLE_POL (BIT(7)) +#define SPI_VSYNC_IDLE_POL_M (SPI_VSYNC_IDLE_POL_V << SPI_VSYNC_IDLE_POL_S) +#define SPI_VSYNC_IDLE_POL_V 0x00000001 +#define SPI_VSYNC_IDLE_POL_S 7 + +/* SPI_LCD_VSYNC_WIDTH : R/W; bitpos: [6:0]; default: 0; + * It is the position of spi_vsync_out active pulse in a line. + */ + +#define SPI_LCD_VSYNC_WIDTH 0x0000007F +#define SPI_LCD_VSYNC_WIDTH_M (SPI_LCD_VSYNC_WIDTH_V << SPI_LCD_VSYNC_WIDTH_S) +#define SPI_LCD_VSYNC_WIDTH_V 0x0000007F +#define SPI_LCD_VSYNC_WIDTH_S 0 + +/* SPI_LCD_D_MODE_REG register */ + +#define SPI_LCD_D_MODE_REG (DR_REG_SPI_BASE + 0x108) + +/* SPI_D_VSYNC_MODE : R/W; bitpos: [14:12]; default: 0; + * Configure the output spi_vsync delay mode. 0: without delayed, 1: with + * the posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the + * posedge of hclk, whose frequency is the double of the clk_apb frequency, + * 4: with the negedge of hclk, 5: with the posedge of spi_clk, 6: with the + * negedge of spi_clk. + */ + +#define SPI_D_VSYNC_MODE 0x00000007 +#define SPI_D_VSYNC_MODE_M (SPI_D_VSYNC_MODE_V << SPI_D_VSYNC_MODE_S) +#define SPI_D_VSYNC_MODE_V 0x00000007 +#define SPI_D_VSYNC_MODE_S 12 + +/* SPI_D_HSYNC_MODE : R/W; bitpos: [11:9]; default: 0; + * Configure the output spi_hsync delay mode. 0: without delayed, 1: with + * the posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the + * posedge of hclk, whose frequency is the double of the clk_apb frequency, + * 4: with the negedge of hclk, 5: with the posedge of spi_clk, 6: with the + * negedge of spi_clk. + */ + +#define SPI_D_HSYNC_MODE 0x00000007 +#define SPI_D_HSYNC_MODE_M (SPI_D_HSYNC_MODE_V << SPI_D_HSYNC_MODE_S) +#define SPI_D_HSYNC_MODE_V 0x00000007 +#define SPI_D_HSYNC_MODE_S 9 + +/* SPI_D_DE_MODE : R/W; bitpos: [8:6]; default: 0; + * Configure the output spi_de delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_D_DE_MODE 0x00000007 +#define SPI_D_DE_MODE_M (SPI_D_DE_MODE_V << SPI_D_DE_MODE_S) +#define SPI_D_DE_MODE_V 0x00000007 +#define SPI_D_DE_MODE_S 6 + +/* SPI_D_CD_MODE : R/W; bitpos: [5:3]; default: 0; + * Configure the output spi_cd delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_D_CD_MODE 0x00000007 +#define SPI_D_CD_MODE_M (SPI_D_CD_MODE_V << SPI_D_CD_MODE_S) +#define SPI_D_CD_MODE_V 0x00000007 +#define SPI_D_CD_MODE_S 3 + +/* SPI_D_DQS_MODE : R/W; bitpos: [2:0]; default: 0; + * Configure the output spi_dqs delay mode. 0: without delayed, 1: with the + * posedge of clk_apb, 2: with the negedge of clk_apb, 3: with the posedge + * of hclk, whose frequency is the double of the clk_apb frequency, 4: with + * the negedge of hclk, 5: with the posedge of spi_clk, 6: with the negedge + * of spi_clk. + */ + +#define SPI_D_DQS_MODE 0x00000007 +#define SPI_D_DQS_MODE_M (SPI_D_DQS_MODE_V << SPI_D_DQS_MODE_S) +#define SPI_D_DQS_MODE_V 0x00000007 +#define SPI_D_DQS_MODE_S 0 + +/* SPI_LCD_D_NUM_REG register */ + +#define SPI_LCD_D_NUM_REG (DR_REG_SPI_BASE + 0x10c) + +/* SPI_D_VSYNC_NUM : R/W; bitpos: [9:8]; default: 0; + * the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_D_VSYNC_NUM 0x00000003 +#define SPI_D_VSYNC_NUM_M (SPI_D_VSYNC_NUM_V << SPI_D_VSYNC_NUM_S) +#define SPI_D_VSYNC_NUM_V 0x00000003 +#define SPI_D_VSYNC_NUM_S 8 + +/* SPI_D_HSYNC_NUM : R/W; bitpos: [7:6]; default: 0; + * the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_D_HSYNC_NUM 0x00000003 +#define SPI_D_HSYNC_NUM_M (SPI_D_HSYNC_NUM_V << SPI_D_HSYNC_NUM_S) +#define SPI_D_HSYNC_NUM_V 0x00000003 +#define SPI_D_HSYNC_NUM_S 6 + +/* SPI_D_DE_NUM : R/W; bitpos: [5:4]; default: 0; + * the output spi_de is delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_D_DE_NUM 0x00000003 +#define SPI_D_DE_NUM_M (SPI_D_DE_NUM_V << SPI_D_DE_NUM_S) +#define SPI_D_DE_NUM_V 0x00000003 +#define SPI_D_DE_NUM_S 4 + +/* SPI_D_CD_NUM : R/W; bitpos: [3:2]; default: 0; + * the output spi_cd is delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_D_CD_NUM 0x00000003 +#define SPI_D_CD_NUM_M (SPI_D_CD_NUM_V << SPI_D_CD_NUM_S) +#define SPI_D_CD_NUM_V 0x00000003 +#define SPI_D_CD_NUM_S 2 + +/* SPI_D_DQS_NUM : R/W; bitpos: [1:0]; default: 0; + * the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... + */ + +#define SPI_D_DQS_NUM 0x00000003 +#define SPI_D_DQS_NUM_M (SPI_D_DQS_NUM_V << SPI_D_DQS_NUM_S) +#define SPI_D_DQS_NUM_V 0x00000003 +#define SPI_D_DQS_NUM_S 0 + +/* SPI_REG_DATE_REG register */ + +#define SPI_REG_DATE_REG (DR_REG_SPI_BASE + 0x3fc) + +/* SPI_DATE : RW; bitpos: [27:0]; default: 26222993; + * SPI register version. + */ + +#define SPI_DATE 0x0FFFFFFF +#define SPI_DATE_M (SPI_DATE_V << SPI_DATE_S) +#define SPI_DATE_V 0x0FFFFFFF +#define SPI_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SPI_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_system.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_system.h new file mode 100644 index 0000000000..884298bc19 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_system.h @@ -0,0 +1,1465 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_system.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SYSTEM_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SYSTEM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SYSTEM_ROM_CTRL_0_REG register + * System ROM configuration register 0 + */ + +#define SYSTEM_ROM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x0) + +/* SYSTEM_ROM_FO : R/W; bitpos: [1:0]; default: 3; + * This field is used to force on clock gate of internal ROM. + */ + +#define SYSTEM_ROM_FO 0x00000003 +#define SYSTEM_ROM_FO_M (SYSTEM_ROM_FO_V << SYSTEM_ROM_FO_S) +#define SYSTEM_ROM_FO_V 0x00000003 +#define SYSTEM_ROM_FO_S 0 + +/* SYSTEM_ROM_CTRL_1_REG register + * System ROM configuration register 1 + */ + +#define SYSTEM_ROM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x4) + +/* SYSTEM_ROM_FORCE_PU : R/W; bitpos: [3:2]; default: 3; + * This field is used to power up internal ROM. + */ + +#define SYSTEM_ROM_FORCE_PU 0x00000003 +#define SYSTEM_ROM_FORCE_PU_M (SYSTEM_ROM_FORCE_PU_V << SYSTEM_ROM_FORCE_PU_S) +#define SYSTEM_ROM_FORCE_PU_V 0x00000003 +#define SYSTEM_ROM_FORCE_PU_S 2 + +/* SYSTEM_ROM_FORCE_PD : R/W; bitpos: [1:0]; default: 0; + * This field is used to power down internal ROM. + */ + +#define SYSTEM_ROM_FORCE_PD 0x00000003 +#define SYSTEM_ROM_FORCE_PD_M (SYSTEM_ROM_FORCE_PD_V << SYSTEM_ROM_FORCE_PD_S) +#define SYSTEM_ROM_FORCE_PD_V 0x00000003 +#define SYSTEM_ROM_FORCE_PD_S 0 + +/* SYSTEM_SRAM_CTRL_0_REG register + * System SRAM configuration register 0 + */ + +#define SYSTEM_SRAM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x8) + +/* SYSTEM_SRAM_FO : R/W; bitpos: [21:0]; default: 4194303; + * This field is used to force on clock gate of internal SRAM. + */ + +#define SYSTEM_SRAM_FO 0x003FFFFF +#define SYSTEM_SRAM_FO_M (SYSTEM_SRAM_FO_V << SYSTEM_SRAM_FO_S) +#define SYSTEM_SRAM_FO_V 0x003FFFFF +#define SYSTEM_SRAM_FO_S 0 + +/* SYSTEM_SRAM_CTRL_1_REG register + * System SRAM configuration register 1 + */ + +#define SYSTEM_SRAM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0xc) + +/* SYSTEM_SRAM_FORCE_PD : R/W; bitpos: [21:0]; default: 0; + * This field is used to power down internal SRAM. + */ + +#define SYSTEM_SRAM_FORCE_PD 0x003FFFFF +#define SYSTEM_SRAM_FORCE_PD_M (SYSTEM_SRAM_FORCE_PD_V << SYSTEM_SRAM_FORCE_PD_S) +#define SYSTEM_SRAM_FORCE_PD_V 0x003FFFFF +#define SYSTEM_SRAM_FORCE_PD_S 0 + +/* SYSTEM_CPU_PERI_CLK_EN_REG register + * CPU peripheral clock enable register + */ + +#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x10) + +/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 0; + * Set this bit to enable clock of DEDICATED GPIO module. + */ + +#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (SYSTEM_CLK_EN_DEDICATED_GPIO_V << SYSTEM_CLK_EN_DEDICATED_GPIO_S) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x00000001 +#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 + +/* SYSTEM_CPU_PERI_RST_EN_REG register + * CPU peripheral reset register + */ + +#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x14) + +/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 1; + * Set this bit to reset DEDICATED GPIO module. + */ + +#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_M (SYSTEM_RST_EN_DEDICATED_GPIO_V << SYSTEM_RST_EN_DEDICATED_GPIO_S) +#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x00000001 +#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 + +/* SYSTEM_CPU_PER_CONF_REG register + * CPU peripheral clock configuration register + */ + +#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x18) +#define DPORT_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x018) /* old name */ + +/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; + * Sets the number of delay cycles to enter CPU wait mode after a WAITI + * instruction. + */ + +#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000F +#define SYSTEM_CPU_WAITI_DELAY_NUM_M (SYSTEM_CPU_WAITI_DELAY_NUM_V << SYSTEM_CPU_WAITI_DELAY_NUM_S) +#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0x0000000F +#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 + +/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; + * Set this bit to force on CPU wait mode. In this mode, the clock gate of + * CPU is turned off until any interrupts happen. This mode could also be + * force on via WAITI instruction. + */ + +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (SYSTEM_CPU_WAIT_MODE_FORCE_ON_V << SYSTEM_CPU_WAIT_MODE_FORCE_ON_S) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x00000001 +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 + +/* SYSTEM_PLL_FREQ_SEL : R/W; bitpos: [2]; default: 1; + * This field is used to select the PLL clock frequency based on CPU period. + */ + +#define SYSTEM_PLL_FREQ_SEL (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_M (SYSTEM_PLL_FREQ_SEL_V << SYSTEM_PLL_FREQ_SEL_S) +#define SYSTEM_PLL_FREQ_SEL_V 0x00000001 +#define SYSTEM_PLL_FREQ_SEL_S 2 + +/* SYSTEM_CPUPERIOD_SEL : R/W; bitpos: [1:0]; default: 0; + * This field is used to select the clock frequency of CPU or CPU period. + */ + +#define SYSTEM_CPUPERIOD_SEL 0x00000003 +#define SYSTEM_CPUPERIOD_SEL_M (SYSTEM_CPUPERIOD_SEL_V << SYSTEM_CPUPERIOD_SEL_S) +#define SYSTEM_CPUPERIOD_SEL_V 0x00000003 +#define SYSTEM_CPUPERIOD_SEL_S 0 + +/* SYSTEM_JTAG_CTRL_0_REG register + * JTAG configuration register 0 + */ + +#define SYSTEM_JTAG_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x1c) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 0 to 31 bits of the 256 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S 0 + +/* SYSTEM_JTAG_CTRL_1_REG register + * JTAG configuration register 1 + */ + +#define SYSTEM_JTAG_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x20) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 32 to 63 bits of the 256 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S 0 + +/* SYSTEM_JTAG_CTRL_2_REG register + * JTAG configuration register 2 + */ + +#define SYSTEM_JTAG_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x24) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 64 to 95 bits of the 256 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S 0 + +/* SYSTEM_JTAG_CTRL_3_REG register + * JTAG configuration register 3 + */ + +#define SYSTEM_JTAG_CTRL_3_REG (DR_REG_SYSTEM_BASE + 0x28) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 96 to 127 bits of the 256 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S 0 + +/* SYSTEM_JTAG_CTRL_4_REG register + * JTAG configuration register 4 + */ + +#define SYSTEM_JTAG_CTRL_4_REG (DR_REG_SYSTEM_BASE + 0x2c) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 128 to 159 bits of the 256 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S 0 + +/* SYSTEM_JTAG_CTRL_5_REG register + * JTAG configuration register 5 + */ + +#define SYSTEM_JTAG_CTRL_5_REG (DR_REG_SYSTEM_BASE + 0x30) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 160 to 191 bits of the 256 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S 0 + +/* SYSTEM_JTAG_CTRL_6_REG register + * JTAG configuration register 6 + */ + +#define SYSTEM_JTAG_CTRL_6_REG (DR_REG_SYSTEM_BASE + 0x34) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 192 to 223 bits of the 256 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S 0 + +/* SYSTEM_JTAG_CTRL_7_REG register + * JTAG configuration register 7 + */ + +#define SYSTEM_JTAG_CTRL_7_REG (DR_REG_SYSTEM_BASE + 0x38) + +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 : WOR; bitpos: [31:0]; + * default: 0; + * Stores the 0 to 224 bits of the 255 bits register used to cancel the + * temporary disable of eFuse to JTAG. + */ + +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S 0 + +/* SYSTEM_MEM_PD_MASK_REG register + * Memory power-related controlling register (under low-sleep) + */ + +#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x3c) + +/* SYSTEM_LSLP_MEM_PD_MASK : R/W; bitpos: [0]; default: 1; + * Set this bit to allow the memory to work as usual when the chip enters + * the light-sleep state. + */ + +#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_M (SYSTEM_LSLP_MEM_PD_MASK_V << SYSTEM_LSLP_MEM_PD_MASK_S) +#define SYSTEM_LSLP_MEM_PD_MASK_V 0x00000001 +#define SYSTEM_LSLP_MEM_PD_MASK_S 0 + +/* SYSTEM_PERIP_CLK_EN0_REG register + * System peripheral clock (for hardware accelerators) enable register + */ + +#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x40) + +/* SYSTEM_SPI4_CLK_EN : R/W; bitpos: [31]; default: 1; + * Set this bit to enable clock of SPI4. + */ + +#define SYSTEM_SPI4_CLK_EN (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_M (SYSTEM_SPI4_CLK_EN_V << SYSTEM_SPI4_CLK_EN_S) +#define SYSTEM_SPI4_CLK_EN_V 0x00000001 +#define SYSTEM_SPI4_CLK_EN_S 31 + +/* SYSTEM_ADC2_ARB_CLK_EN : R/W; bitpos: [30]; default: 1; + * Set this bit to enable clock of aribiter of ADC2. + */ + +#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_M (SYSTEM_ADC2_ARB_CLK_EN_V << SYSTEM_ADC2_ARB_CLK_EN_S) +#define SYSTEM_ADC2_ARB_CLK_EN_V 0x00000001 +#define SYSTEM_ADC2_ARB_CLK_EN_S 30 + +/* SYSTEM_SYSTIMER_CLK_EN : R/W; bitpos: [29]; default: 1; + * Set this bit to enable clock of system timer. + */ + +#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_M (SYSTEM_SYSTIMER_CLK_EN_V << SYSTEM_SYSTIMER_CLK_EN_S) +#define SYSTEM_SYSTIMER_CLK_EN_V 0x00000001 +#define SYSTEM_SYSTIMER_CLK_EN_S 29 + +/* SYSTEM_APB_SARADC_CLK_EN : R/W; bitpos: [28]; default: 1; + * Set this bit to enable clock of SAR ADC. + */ + +#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_M (SYSTEM_APB_SARADC_CLK_EN_V << SYSTEM_APB_SARADC_CLK_EN_S) +#define SYSTEM_APB_SARADC_CLK_EN_V 0x00000001 +#define SYSTEM_APB_SARADC_CLK_EN_S 28 + +/* SYSTEM_SPI3_DMA_CLK_EN : R/W; bitpos: [27]; default: 1; + * Set this bit to enable clock of SPI3 DMA. + */ + +#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_M (SYSTEM_SPI3_DMA_CLK_EN_V << SYSTEM_SPI3_DMA_CLK_EN_S) +#define SYSTEM_SPI3_DMA_CLK_EN_V 0x00000001 +#define SYSTEM_SPI3_DMA_CLK_EN_S 27 + +/* SYSTEM_PWM3_CLK_EN : R/W; bitpos: [26]; default: 0; + * Set this bit to enable clock of PWM3. + */ + +#define SYSTEM_PWM3_CLK_EN (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_M (SYSTEM_PWM3_CLK_EN_V << SYSTEM_PWM3_CLK_EN_S) +#define SYSTEM_PWM3_CLK_EN_V 0x00000001 +#define SYSTEM_PWM3_CLK_EN_S 26 + +/* SYSTEM_PWM2_CLK_EN : R/W; bitpos: [25]; default: 0; + * Set this bit to enable clock of PWM2. + */ + +#define SYSTEM_PWM2_CLK_EN (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_M (SYSTEM_PWM2_CLK_EN_V << SYSTEM_PWM2_CLK_EN_S) +#define SYSTEM_PWM2_CLK_EN_V 0x00000001 +#define SYSTEM_PWM2_CLK_EN_S 25 + +/* SYSTEM_UART_MEM_CLK_EN : R/W; bitpos: [24]; default: 1; + * Set this bit to enable clock of UART memory. + */ + +#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_M (SYSTEM_UART_MEM_CLK_EN_V << SYSTEM_UART_MEM_CLK_EN_S) +#define SYSTEM_UART_MEM_CLK_EN_V 0x00000001 +#define SYSTEM_UART_MEM_CLK_EN_S 24 + +/* SYSTEM_USB_CLK_EN : R/W; bitpos: [23]; default: 1; + * Set this bit to enable clock of USB. + */ + +#define SYSTEM_USB_CLK_EN (BIT(23)) +#define SYSTEM_USB_CLK_EN_M (SYSTEM_USB_CLK_EN_V << SYSTEM_USB_CLK_EN_S) +#define SYSTEM_USB_CLK_EN_V 0x00000001 +#define SYSTEM_USB_CLK_EN_S 23 + +/* SYSTEM_SPI2_DMA_CLK_EN : R/W; bitpos: [22]; default: 1; + * Set this bit to enable clock of SPI2 DMA. + */ + +#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_M (SYSTEM_SPI2_DMA_CLK_EN_V << SYSTEM_SPI2_DMA_CLK_EN_S) +#define SYSTEM_SPI2_DMA_CLK_EN_V 0x00000001 +#define SYSTEM_SPI2_DMA_CLK_EN_S 22 + +/* SYSTEM_I2S1_CLK_EN : R/W; bitpos: [21]; default: 0; + * Set this bit to enable clock of I2S1. + */ + +#define SYSTEM_I2S1_CLK_EN (BIT(21)) +#define SYSTEM_I2S1_CLK_EN_M (SYSTEM_I2S1_CLK_EN_V << SYSTEM_I2S1_CLK_EN_S) +#define SYSTEM_I2S1_CLK_EN_V 0x00000001 +#define SYSTEM_I2S1_CLK_EN_S 21 + +/* SYSTEM_PWM1_CLK_EN : R/W; bitpos: [20]; default: 0; + * Set this bit to enable clock of PWM1. + */ + +#define SYSTEM_PWM1_CLK_EN (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_M (SYSTEM_PWM1_CLK_EN_V << SYSTEM_PWM1_CLK_EN_S) +#define SYSTEM_PWM1_CLK_EN_V 0x00000001 +#define SYSTEM_PWM1_CLK_EN_S 20 + +/* SYSTEM_CAN_CLK_EN : R/W; bitpos: [19]; default: 0; + * Set this bit to enable clock of CAN. + */ + +#define SYSTEM_CAN_CLK_EN (BIT(19)) +#define SYSTEM_CAN_CLK_EN_M (SYSTEM_CAN_CLK_EN_V << SYSTEM_CAN_CLK_EN_S) +#define SYSTEM_CAN_CLK_EN_V 0x00000001 +#define SYSTEM_CAN_CLK_EN_S 19 + +/* SYSTEM_I2C_EXT1_CLK_EN : R/W; bitpos: [18]; default: 0; + * Set this bit to enable clock of I2C EXT1. + */ + +#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_M (SYSTEM_I2C_EXT1_CLK_EN_V << SYSTEM_I2C_EXT1_CLK_EN_S) +#define SYSTEM_I2C_EXT1_CLK_EN_V 0x00000001 +#define SYSTEM_I2C_EXT1_CLK_EN_S 18 + +/* SYSTEM_PWM0_CLK_EN : R/W; bitpos: [17]; default: 0; + * Set this bit to enable clock of PWM0. + */ + +#define SYSTEM_PWM0_CLK_EN (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_M (SYSTEM_PWM0_CLK_EN_V << SYSTEM_PWM0_CLK_EN_S) +#define SYSTEM_PWM0_CLK_EN_V 0x00000001 +#define SYSTEM_PWM0_CLK_EN_S 17 + +/* SYSTEM_SPI3_CLK_EN : R/W; bitpos: [16]; default: 1; + * Set this bit to enable clock of SPI3. + */ + +#define SYSTEM_SPI3_CLK_EN (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_M (SYSTEM_SPI3_CLK_EN_V << SYSTEM_SPI3_CLK_EN_S) +#define SYSTEM_SPI3_CLK_EN_V 0x00000001 +#define SYSTEM_SPI3_CLK_EN_S 16 + +/* SYSTEM_TIMERGROUP1_CLK_EN : R/W; bitpos: [15]; default: 1; + * Set this bit to enable clock of timer group1. + */ + +#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_M (SYSTEM_TIMERGROUP1_CLK_EN_V << SYSTEM_TIMERGROUP1_CLK_EN_S) +#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x00000001 +#define SYSTEM_TIMERGROUP1_CLK_EN_S 15 + +/* SYSTEM_EFUSE_CLK_EN : R/W; bitpos: [14]; default: 1; + * Set this bit to enable clock of eFuse. + */ + +#define SYSTEM_EFUSE_CLK_EN (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_M (SYSTEM_EFUSE_CLK_EN_V << SYSTEM_EFUSE_CLK_EN_S) +#define SYSTEM_EFUSE_CLK_EN_V 0x00000001 +#define SYSTEM_EFUSE_CLK_EN_S 14 + +/* SYSTEM_TIMERGROUP_CLK_EN : R/W; bitpos: [13]; default: 1; + * Set this bit to enable clock of timer group0. + */ + +#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_M (SYSTEM_TIMERGROUP_CLK_EN_V << SYSTEM_TIMERGROUP_CLK_EN_S) +#define SYSTEM_TIMERGROUP_CLK_EN_V 0x00000001 +#define SYSTEM_TIMERGROUP_CLK_EN_S 13 + +/* SYSTEM_UHCI1_CLK_EN : R/W; bitpos: [12]; default: 0; + * Set this bit to enable clock of UHCI1. + */ + +#define SYSTEM_UHCI1_CLK_EN (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_M (SYSTEM_UHCI1_CLK_EN_V << SYSTEM_UHCI1_CLK_EN_S) +#define SYSTEM_UHCI1_CLK_EN_V 0x00000001 +#define SYSTEM_UHCI1_CLK_EN_S 12 + +/* SYSTEM_LEDC_CLK_EN : R/W; bitpos: [11]; default: 0; + * Set this bit to enable clock of LED PWM. + */ + +#define SYSTEM_LEDC_CLK_EN (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_M (SYSTEM_LEDC_CLK_EN_V << SYSTEM_LEDC_CLK_EN_S) +#define SYSTEM_LEDC_CLK_EN_V 0x00000001 +#define SYSTEM_LEDC_CLK_EN_S 11 + +/* SYSTEM_PCNT_CLK_EN : R/W; bitpos: [10]; default: 0; + * Set this bit to enable clock of pulse count. + */ + +#define SYSTEM_PCNT_CLK_EN (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_M (SYSTEM_PCNT_CLK_EN_V << SYSTEM_PCNT_CLK_EN_S) +#define SYSTEM_PCNT_CLK_EN_V 0x00000001 +#define SYSTEM_PCNT_CLK_EN_S 10 + +/* SYSTEM_RMT_CLK_EN : R/W; bitpos: [9]; default: 0; + * Set this bit to enable clock of remote controller. + */ + +#define SYSTEM_RMT_CLK_EN (BIT(9)) +#define SYSTEM_RMT_CLK_EN_M (SYSTEM_RMT_CLK_EN_V << SYSTEM_RMT_CLK_EN_S) +#define SYSTEM_RMT_CLK_EN_V 0x00000001 +#define SYSTEM_RMT_CLK_EN_S 9 + +/* SYSTEM_UHCI0_CLK_EN : R/W; bitpos: [8]; default: 0; + * Set this bit to enable clock of UHCI0. + */ + +#define SYSTEM_UHCI0_CLK_EN (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_M (SYSTEM_UHCI0_CLK_EN_V << SYSTEM_UHCI0_CLK_EN_S) +#define SYSTEM_UHCI0_CLK_EN_V 0x00000001 +#define SYSTEM_UHCI0_CLK_EN_S 8 + +/* SYSTEM_I2C_EXT0_CLK_EN : R/W; bitpos: [7]; default: 0; + * Set this bit to enable clock of I2C EXT0. + */ + +#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_M (SYSTEM_I2C_EXT0_CLK_EN_V << SYSTEM_I2C_EXT0_CLK_EN_S) +#define SYSTEM_I2C_EXT0_CLK_EN_V 0x00000001 +#define SYSTEM_I2C_EXT0_CLK_EN_S 7 + +/* SYSTEM_SPI2_CLK_EN : R/W; bitpos: [6]; default: 1; + * Set this bit to enable clock of SPI2. + */ + +#define SYSTEM_SPI2_CLK_EN (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_M (SYSTEM_SPI2_CLK_EN_V << SYSTEM_SPI2_CLK_EN_S) +#define SYSTEM_SPI2_CLK_EN_V 0x00000001 +#define SYSTEM_SPI2_CLK_EN_S 6 + +/* SYSTEM_UART1_CLK_EN : R/W; bitpos: [5]; default: 1; + * Set this bit to enable clock of UART1. + */ + +#define SYSTEM_UART1_CLK_EN (BIT(5)) +#define SYSTEM_UART1_CLK_EN_M (SYSTEM_UART1_CLK_EN_V << SYSTEM_UART1_CLK_EN_S) +#define SYSTEM_UART1_CLK_EN_V 0x00000001 +#define SYSTEM_UART1_CLK_EN_S 5 + +/* SYSTEM_I2S0_CLK_EN : R/W; bitpos: [4]; default: 0; + * Set this bit to enable clock of I2S0. + */ + +#define SYSTEM_I2S0_CLK_EN (BIT(4)) +#define SYSTEM_I2S0_CLK_EN_M (SYSTEM_I2S0_CLK_EN_V << SYSTEM_I2S0_CLK_EN_S) +#define SYSTEM_I2S0_CLK_EN_V 0x00000001 +#define SYSTEM_I2S0_CLK_EN_S 4 + +/* SYSTEM_WDG_CLK_EN : R/W; bitpos: [3]; default: 1; + * Set this bit to enable clock of WDG. + */ + +#define SYSTEM_WDG_CLK_EN (BIT(3)) +#define SYSTEM_WDG_CLK_EN_M (SYSTEM_WDG_CLK_EN_V << SYSTEM_WDG_CLK_EN_S) +#define SYSTEM_WDG_CLK_EN_V 0x00000001 +#define SYSTEM_WDG_CLK_EN_S 3 + +/* SYSTEM_UART_CLK_EN : R/W; bitpos: [2]; default: 1; + * Set this bit to enable clock of UART0. + */ + +#define SYSTEM_UART_CLK_EN (BIT(2)) +#define SYSTEM_UART_CLK_EN_M (SYSTEM_UART_CLK_EN_V << SYSTEM_UART_CLK_EN_S) +#define SYSTEM_UART_CLK_EN_V 0x00000001 +#define SYSTEM_UART_CLK_EN_S 2 + +/* SYSTEM_SPI01_CLK_EN : R/W; bitpos: [1]; default: 1; + * Set this bit to enable clock of SPI0 and SPI1. + */ + +#define SYSTEM_SPI01_CLK_EN (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_M (SYSTEM_SPI01_CLK_EN_V << SYSTEM_SPI01_CLK_EN_S) +#define SYSTEM_SPI01_CLK_EN_V 0x00000001 +#define SYSTEM_SPI01_CLK_EN_S 1 + +/* SYSTEM_TIMERS_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set this bit to enable clock of timers. + */ + +#define SYSTEM_TIMERS_CLK_EN (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_M (SYSTEM_TIMERS_CLK_EN_V << SYSTEM_TIMERS_CLK_EN_S) +#define SYSTEM_TIMERS_CLK_EN_V 0x00000001 +#define SYSTEM_TIMERS_CLK_EN_S 0 + +/* SYSTEM_PERIP_CLK_EN1_REG register + * System peripheral clock (for hardware accelerators) enable register 1 + */ + +#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x44) + +/* SYSTEM_CRYPTO_DMA_CLK_EN : R/W; bitpos: [6]; default: 0; + * Set this bit to enable clock of cryptography DMA. + */ + +#define SYSTEM_CRYPTO_DMA_CLK_EN (BIT(6)) +#define SYSTEM_CRYPTO_DMA_CLK_EN_M (SYSTEM_CRYPTO_DMA_CLK_EN_V << SYSTEM_CRYPTO_DMA_CLK_EN_S) +#define SYSTEM_CRYPTO_DMA_CLK_EN_V 0x00000001 +#define SYSTEM_CRYPTO_DMA_CLK_EN_S 6 + +/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W; bitpos: [5]; default: 0; + * Set this bit to enable clock of cryptography HMAC. + */ + +#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (SYSTEM_CRYPTO_HMAC_CLK_EN_V << SYSTEM_CRYPTO_HMAC_CLK_EN_S) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x00000001 +#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 + +/* SYSTEM_CRYPTO_DS_CLK_EN : R/W; bitpos: [4]; default: 0; + * Set this bit to enable clock of cryptography Digital Signature. + */ + +#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_M (SYSTEM_CRYPTO_DS_CLK_EN_V << SYSTEM_CRYPTO_DS_CLK_EN_S) +#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x00000001 +#define SYSTEM_CRYPTO_DS_CLK_EN_S 4 + +/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable clock of cryptography RSA. + */ + +#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_M (SYSTEM_CRYPTO_RSA_CLK_EN_V << SYSTEM_CRYPTO_RSA_CLK_EN_S) +#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x00000001 +#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 + +/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to enable clock of cryptography SHA. + */ + +#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_M (SYSTEM_CRYPTO_SHA_CLK_EN_V << SYSTEM_CRYPTO_SHA_CLK_EN_S) +#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x00000001 +#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 + +/* SYSTEM_CRYPTO_AES_CLK_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable clock of cryptography AES. + */ + +#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_M (SYSTEM_CRYPTO_AES_CLK_EN_V << SYSTEM_CRYPTO_AES_CLK_EN_S) +#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x00000001 +#define SYSTEM_CRYPTO_AES_CLK_EN_S 1 + +/* SYSTEM_PERIP_RST_EN0_REG register + * System peripheral (hardware accelerators) reset register 0 + */ + +#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x48) + +/* SYSTEM_SPI4_RST : R/W; bitpos: [31]; default: 0; + * Set this bit to reset SPI4. + */ + +#define SYSTEM_SPI4_RST (BIT(31)) +#define SYSTEM_SPI4_RST_M (SYSTEM_SPI4_RST_V << SYSTEM_SPI4_RST_S) +#define SYSTEM_SPI4_RST_V 0x00000001 +#define SYSTEM_SPI4_RST_S 31 + +/* SYSTEM_ADC2_ARB_RST : R/W; bitpos: [30]; default: 0; + * Set this bit to reset aribiter of ADC2. + */ + +#define SYSTEM_ADC2_ARB_RST (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_M (SYSTEM_ADC2_ARB_RST_V << SYSTEM_ADC2_ARB_RST_S) +#define SYSTEM_ADC2_ARB_RST_V 0x00000001 +#define SYSTEM_ADC2_ARB_RST_S 30 + +/* SYSTEM_SYSTIMER_RST : R/W; bitpos: [29]; default: 0; + * Set this bit to reset system timer. + */ + +#define SYSTEM_SYSTIMER_RST (BIT(29)) +#define SYSTEM_SYSTIMER_RST_M (SYSTEM_SYSTIMER_RST_V << SYSTEM_SYSTIMER_RST_S) +#define SYSTEM_SYSTIMER_RST_V 0x00000001 +#define SYSTEM_SYSTIMER_RST_S 29 + +/* SYSTEM_APB_SARADC_RST : R/W; bitpos: [28]; default: 0; + * Set this bit to reset SAR ADC. + */ + +#define SYSTEM_APB_SARADC_RST (BIT(28)) +#define SYSTEM_APB_SARADC_RST_M (SYSTEM_APB_SARADC_RST_V << SYSTEM_APB_SARADC_RST_S) +#define SYSTEM_APB_SARADC_RST_V 0x00000001 +#define SYSTEM_APB_SARADC_RST_S 28 + +/* SYSTEM_SPI3_DMA_RST : R/W; bitpos: [27]; default: 0; + * Set this bit to reset SPI3 DMA. + */ + +#define SYSTEM_SPI3_DMA_RST (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_M (SYSTEM_SPI3_DMA_RST_V << SYSTEM_SPI3_DMA_RST_S) +#define SYSTEM_SPI3_DMA_RST_V 0x00000001 +#define SYSTEM_SPI3_DMA_RST_S 27 + +/* SYSTEM_PWM3_RST : R/W; bitpos: [26]; default: 0; + * Set this bit to reset PWM3. + */ + +#define SYSTEM_PWM3_RST (BIT(26)) +#define SYSTEM_PWM3_RST_M (SYSTEM_PWM3_RST_V << SYSTEM_PWM3_RST_S) +#define SYSTEM_PWM3_RST_V 0x00000001 +#define SYSTEM_PWM3_RST_S 26 + +/* SYSTEM_PWM2_RST : R/W; bitpos: [25]; default: 0; + * Set this bit to reset PWM2. + */ + +#define SYSTEM_PWM2_RST (BIT(25)) +#define SYSTEM_PWM2_RST_M (SYSTEM_PWM2_RST_V << SYSTEM_PWM2_RST_S) +#define SYSTEM_PWM2_RST_V 0x00000001 +#define SYSTEM_PWM2_RST_S 25 + +/* SYSTEM_UART_MEM_RST : R/W; bitpos: [24]; default: 0; + * Set this bit to reset UART memory. + */ + +#define SYSTEM_UART_MEM_RST (BIT(24)) +#define SYSTEM_UART_MEM_RST_M (SYSTEM_UART_MEM_RST_V << SYSTEM_UART_MEM_RST_S) +#define SYSTEM_UART_MEM_RST_V 0x00000001 +#define SYSTEM_UART_MEM_RST_S 24 + +/* SYSTEM_USB_RST : R/W; bitpos: [23]; default: 0; + * Set this bit to reset USB. + */ + +#define SYSTEM_USB_RST (BIT(23)) +#define SYSTEM_USB_RST_M (SYSTEM_USB_RST_V << SYSTEM_USB_RST_S) +#define SYSTEM_USB_RST_V 0x00000001 +#define SYSTEM_USB_RST_S 23 + +/* SYSTEM_SPI2_DMA_RST : R/W; bitpos: [22]; default: 0; + * Set this bit to reset SPI2 DMA. + */ + +#define SYSTEM_SPI2_DMA_RST (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_M (SYSTEM_SPI2_DMA_RST_V << SYSTEM_SPI2_DMA_RST_S) +#define SYSTEM_SPI2_DMA_RST_V 0x00000001 +#define SYSTEM_SPI2_DMA_RST_S 22 + +/* SYSTEM_I2S1_RST : R/W; bitpos: [21]; default: 0; + * Set this bit to reset I2S1. + */ + +#define SYSTEM_I2S1_RST (BIT(21)) +#define SYSTEM_I2S1_RST_M (SYSTEM_I2S1_RST_V << SYSTEM_I2S1_RST_S) +#define SYSTEM_I2S1_RST_V 0x00000001 +#define SYSTEM_I2S1_RST_S 21 + +/* SYSTEM_PWM1_RST : R/W; bitpos: [20]; default: 0; + * Set this bit to reset PWM1. + */ + +#define SYSTEM_PWM1_RST (BIT(20)) +#define SYSTEM_PWM1_RST_M (SYSTEM_PWM1_RST_V << SYSTEM_PWM1_RST_S) +#define SYSTEM_PWM1_RST_V 0x00000001 +#define SYSTEM_PWM1_RST_S 20 + +/* SYSTEM_CAN_RST : R/W; bitpos: [19]; default: 0; + * Set this bit to reset CAN. + */ + +#define SYSTEM_CAN_RST (BIT(19)) +#define SYSTEM_CAN_RST_M (SYSTEM_CAN_RST_V << SYSTEM_CAN_RST_S) +#define SYSTEM_CAN_RST_V 0x00000001 +#define SYSTEM_CAN_RST_S 19 + +/* SYSTEM_I2C_EXT1_RST : R/W; bitpos: [18]; default: 0; + * Set this bit to reset I2C EXT1. + */ + +#define SYSTEM_I2C_EXT1_RST (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_M (SYSTEM_I2C_EXT1_RST_V << SYSTEM_I2C_EXT1_RST_S) +#define SYSTEM_I2C_EXT1_RST_V 0x00000001 +#define SYSTEM_I2C_EXT1_RST_S 18 + +/* SYSTEM_PWM0_RST : R/W; bitpos: [17]; default: 0; + * Set this bit to reset PWM0. + */ + +#define SYSTEM_PWM0_RST (BIT(17)) +#define SYSTEM_PWM0_RST_M (SYSTEM_PWM0_RST_V << SYSTEM_PWM0_RST_S) +#define SYSTEM_PWM0_RST_V 0x00000001 +#define SYSTEM_PWM0_RST_S 17 + +/* SYSTEM_SPI3_RST : R/W; bitpos: [16]; default: 0; + * Set this bit to reset SPI3. + */ + +#define SYSTEM_SPI3_RST (BIT(16)) +#define SYSTEM_SPI3_RST_M (SYSTEM_SPI3_RST_V << SYSTEM_SPI3_RST_S) +#define SYSTEM_SPI3_RST_V 0x00000001 +#define SYSTEM_SPI3_RST_S 16 + +/* SYSTEM_TIMERGROUP1_RST : R/W; bitpos: [15]; default: 0; + * Set this bit to reset timer group1. + */ + +#define SYSTEM_TIMERGROUP1_RST (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_M (SYSTEM_TIMERGROUP1_RST_V << SYSTEM_TIMERGROUP1_RST_S) +#define SYSTEM_TIMERGROUP1_RST_V 0x00000001 +#define SYSTEM_TIMERGROUP1_RST_S 15 + +/* SYSTEM_EFUSE_RST : R/W; bitpos: [14]; default: 0; + * Set this bit to reset eFuse. + */ + +#define SYSTEM_EFUSE_RST (BIT(14)) +#define SYSTEM_EFUSE_RST_M (SYSTEM_EFUSE_RST_V << SYSTEM_EFUSE_RST_S) +#define SYSTEM_EFUSE_RST_V 0x00000001 +#define SYSTEM_EFUSE_RST_S 14 + +/* SYSTEM_TIMERGROUP_RST : R/W; bitpos: [13]; default: 0; + * Set this bit to reset timer group0. + */ + +#define SYSTEM_TIMERGROUP_RST (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_M (SYSTEM_TIMERGROUP_RST_V << SYSTEM_TIMERGROUP_RST_S) +#define SYSTEM_TIMERGROUP_RST_V 0x00000001 +#define SYSTEM_TIMERGROUP_RST_S 13 + +/* SYSTEM_UHCI1_RST : R/W; bitpos: [12]; default: 0; + * Set this bit to reset UHCI1. + */ + +#define SYSTEM_UHCI1_RST (BIT(12)) +#define SYSTEM_UHCI1_RST_M (SYSTEM_UHCI1_RST_V << SYSTEM_UHCI1_RST_S) +#define SYSTEM_UHCI1_RST_V 0x00000001 +#define SYSTEM_UHCI1_RST_S 12 + +/* SYSTEM_LEDC_RST : R/W; bitpos: [11]; default: 0; + * Set this bit to reset LED PWM. + */ + +#define SYSTEM_LEDC_RST (BIT(11)) +#define SYSTEM_LEDC_RST_M (SYSTEM_LEDC_RST_V << SYSTEM_LEDC_RST_S) +#define SYSTEM_LEDC_RST_V 0x00000001 +#define SYSTEM_LEDC_RST_S 11 + +/* SYSTEM_PCNT_RST : R/W; bitpos: [10]; default: 0; + * Set this bit to reset pulse count. + */ + +#define SYSTEM_PCNT_RST (BIT(10)) +#define SYSTEM_PCNT_RST_M (SYSTEM_PCNT_RST_V << SYSTEM_PCNT_RST_S) +#define SYSTEM_PCNT_RST_V 0x00000001 +#define SYSTEM_PCNT_RST_S 10 + +/* SYSTEM_RMT_RST : R/W; bitpos: [9]; default: 0; + * Set this bit to reset remote controller. + */ + +#define SYSTEM_RMT_RST (BIT(9)) +#define SYSTEM_RMT_RST_M (SYSTEM_RMT_RST_V << SYSTEM_RMT_RST_S) +#define SYSTEM_RMT_RST_V 0x00000001 +#define SYSTEM_RMT_RST_S 9 + +/* SYSTEM_UHCI0_RST : R/W; bitpos: [8]; default: 0; + * Set this bit to reset UHCI0. + */ + +#define SYSTEM_UHCI0_RST (BIT(8)) +#define SYSTEM_UHCI0_RST_M (SYSTEM_UHCI0_RST_V << SYSTEM_UHCI0_RST_S) +#define SYSTEM_UHCI0_RST_V 0x00000001 +#define SYSTEM_UHCI0_RST_S 8 + +/* SYSTEM_I2C_EXT0_RST : R/W; bitpos: [7]; default: 0; + * Set this bit to reset I2C EXT0. + */ + +#define SYSTEM_I2C_EXT0_RST (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_M (SYSTEM_I2C_EXT0_RST_V << SYSTEM_I2C_EXT0_RST_S) +#define SYSTEM_I2C_EXT0_RST_V 0x00000001 +#define SYSTEM_I2C_EXT0_RST_S 7 + +/* SYSTEM_SPI2_RST : R/W; bitpos: [6]; default: 0; + * Set this bit to reset SPI2. + */ + +#define SYSTEM_SPI2_RST (BIT(6)) +#define SYSTEM_SPI2_RST_M (SYSTEM_SPI2_RST_V << SYSTEM_SPI2_RST_S) +#define SYSTEM_SPI2_RST_V 0x00000001 +#define SYSTEM_SPI2_RST_S 6 + +/* SYSTEM_UART1_RST : R/W; bitpos: [5]; default: 0; + * Set this bit to reset UART1. + */ + +#define SYSTEM_UART1_RST (BIT(5)) +#define SYSTEM_UART1_RST_M (SYSTEM_UART1_RST_V << SYSTEM_UART1_RST_S) +#define SYSTEM_UART1_RST_V 0x00000001 +#define SYSTEM_UART1_RST_S 5 + +/* SYSTEM_I2S0_RST : R/W; bitpos: [4]; default: 0; + * Set this bit to reset I2S0. + */ + +#define SYSTEM_I2S0_RST (BIT(4)) +#define SYSTEM_I2S0_RST_M (SYSTEM_I2S0_RST_V << SYSTEM_I2S0_RST_S) +#define SYSTEM_I2S0_RST_V 0x00000001 +#define SYSTEM_I2S0_RST_S 4 + +/* SYSTEM_WDG_RST : R/W; bitpos: [3]; default: 0; + * Set this bit to reset WDG. + */ + +#define SYSTEM_WDG_RST (BIT(3)) +#define SYSTEM_WDG_RST_M (SYSTEM_WDG_RST_V << SYSTEM_WDG_RST_S) +#define SYSTEM_WDG_RST_V 0x00000001 +#define SYSTEM_WDG_RST_S 3 + +/* SYSTEM_UART_RST : R/W; bitpos: [2]; default: 0; + * Set this bit to reset UART0. + */ + +#define SYSTEM_UART_RST (BIT(2)) +#define SYSTEM_UART_RST_M (SYSTEM_UART_RST_V << SYSTEM_UART_RST_S) +#define SYSTEM_UART_RST_V 0x00000001 +#define SYSTEM_UART_RST_S 2 + +/* SYSTEM_SPI01_RST : R/W; bitpos: [1]; default: 0; + * Set this bit to reset SPI0 and SPI1. + */ + +#define SYSTEM_SPI01_RST (BIT(1)) +#define SYSTEM_SPI01_RST_M (SYSTEM_SPI01_RST_V << SYSTEM_SPI01_RST_S) +#define SYSTEM_SPI01_RST_V 0x00000001 +#define SYSTEM_SPI01_RST_S 1 + +/* SYSTEM_TIMERS_RST : R/W; bitpos: [0]; default: 0; + * Set this bit to reset timers. + */ + +#define SYSTEM_TIMERS_RST (BIT(0)) +#define SYSTEM_TIMERS_RST_M (SYSTEM_TIMERS_RST_V << SYSTEM_TIMERS_RST_S) +#define SYSTEM_TIMERS_RST_V 0x00000001 +#define SYSTEM_TIMERS_RST_S 0 + +/* SYSTEM_PERIP_RST_EN1_REG register + * System peripheral (hardware accelerators) reset register 1 + */ + +#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x4c) + +/* SYSTEM_CRYPTO_DMA_RST : R/W; bitpos: [6]; default: 1; + * Set this bit to reset cryptography DMA. + */ + +#define SYSTEM_CRYPTO_DMA_RST (BIT(6)) +#define SYSTEM_CRYPTO_DMA_RST_M (SYSTEM_CRYPTO_DMA_RST_V << SYSTEM_CRYPTO_DMA_RST_S) +#define SYSTEM_CRYPTO_DMA_RST_V 0x00000001 +#define SYSTEM_CRYPTO_DMA_RST_S 6 + +/* SYSTEM_CRYPTO_HMAC_RST : R/W; bitpos: [5]; default: 1; + * Set this bit to reset cryptography HMAC. + */ + +#define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_M (SYSTEM_CRYPTO_HMAC_RST_V << SYSTEM_CRYPTO_HMAC_RST_S) +#define SYSTEM_CRYPTO_HMAC_RST_V 0x00000001 +#define SYSTEM_CRYPTO_HMAC_RST_S 5 + +/* SYSTEM_CRYPTO_DS_RST : R/W; bitpos: [4]; default: 1; + * Set this bit to reset cryptography digital signature. + */ + +#define SYSTEM_CRYPTO_DS_RST (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_M (SYSTEM_CRYPTO_DS_RST_V << SYSTEM_CRYPTO_DS_RST_S) +#define SYSTEM_CRYPTO_DS_RST_V 0x00000001 +#define SYSTEM_CRYPTO_DS_RST_S 4 + +/* SYSTEM_CRYPTO_RSA_RST : R/W; bitpos: [3]; default: 1; + * Set this bit to reset cryptography RSA. + */ + +#define SYSTEM_CRYPTO_RSA_RST (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_M (SYSTEM_CRYPTO_RSA_RST_V << SYSTEM_CRYPTO_RSA_RST_S) +#define SYSTEM_CRYPTO_RSA_RST_V 0x00000001 +#define SYSTEM_CRYPTO_RSA_RST_S 3 + +/* SYSTEM_CRYPTO_SHA_RST : R/W; bitpos: [2]; default: 1; + * Set this bit to reset cryptography SHA. + */ + +#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_M (SYSTEM_CRYPTO_SHA_RST_V << SYSTEM_CRYPTO_SHA_RST_S) +#define SYSTEM_CRYPTO_SHA_RST_V 0x00000001 +#define SYSTEM_CRYPTO_SHA_RST_S 2 + +/* SYSTEM_CRYPTO_AES_RST : R/W; bitpos: [1]; default: 1; + * Set this bit to reset cryptography AES. + */ + +#define SYSTEM_CRYPTO_AES_RST (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_M (SYSTEM_CRYPTO_AES_RST_V << SYSTEM_CRYPTO_AES_RST_S) +#define SYSTEM_CRYPTO_AES_RST_V 0x00000001 +#define SYSTEM_CRYPTO_AES_RST_S 1 + +/* SYSTEM_LPCK_DIV_INT_REG register + * Low power clock divider integer register + */ + +#define SYSTEM_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x50) + +/* SYSTEM_LPCK_DIV_NUM : R/W; bitpos: [11:0]; default: 255; + * This register is used to set the integer number of divider. + */ + +#define SYSTEM_LPCK_DIV_NUM 0x00000FFF +#define SYSTEM_LPCK_DIV_NUM_M (SYSTEM_LPCK_DIV_NUM_V << SYSTEM_LPCK_DIV_NUM_S) +#define SYSTEM_LPCK_DIV_NUM_V 0x00000FFF +#define SYSTEM_LPCK_DIV_NUM_S 0 + +/* SYSTEM_BT_LPCK_DIV_FRAC_REG register + * Divider fraction configuration register for low-power clock + */ + +#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x54) + +/* SYSTEM_LPCLK_RTC_EN : R/W; bitpos: [28]; default: 0; + * Set this bit to enable the RTC low power clock. + */ + +#define SYSTEM_LPCLK_RTC_EN (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_M (SYSTEM_LPCLK_RTC_EN_V << SYSTEM_LPCLK_RTC_EN_S) +#define SYSTEM_LPCLK_RTC_EN_V 0x00000001 +#define SYSTEM_LPCLK_RTC_EN_S 28 + +/* SYSTEM_LPCLK_SEL_XTAL32K : R/W; bitpos: [27]; default: 0; + * Set this bit to select xtal32k clock as the low power clock. + */ + +#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_M (SYSTEM_LPCLK_SEL_XTAL32K_V << SYSTEM_LPCLK_SEL_XTAL32K_S) +#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x00000001 +#define SYSTEM_LPCLK_SEL_XTAL32K_S 27 + +/* SYSTEM_LPCLK_SEL_XTAL : R/W; bitpos: [26]; default: 0; + * Set this bit to select xtal clock as the low power clock. + */ + +#define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_M (SYSTEM_LPCLK_SEL_XTAL_V << SYSTEM_LPCLK_SEL_XTAL_S) +#define SYSTEM_LPCLK_SEL_XTAL_V 0x00000001 +#define SYSTEM_LPCLK_SEL_XTAL_S 26 + +/* SYSTEM_LPCLK_SEL_8M : R/W; bitpos: [25]; default: 1; + * Set this bit to select 8m clock as the low power clock. + */ + +#define SYSTEM_LPCLK_SEL_8M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_M (SYSTEM_LPCLK_SEL_8M_V << SYSTEM_LPCLK_SEL_8M_S) +#define SYSTEM_LPCLK_SEL_8M_V 0x00000001 +#define SYSTEM_LPCLK_SEL_8M_S 25 + +/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W; bitpos: [24]; default: 0; + * Set this bit to select RTC slow clock as the low power clock. + */ + +#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (SYSTEM_LPCLK_SEL_RTC_SLOW_V << SYSTEM_LPCLK_SEL_RTC_SLOW_S) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x00000001 +#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 + +/* SYSTEM_CPU_INTR_FROM_CPU_0_REG register + * CPU interrupt controlling register 0 + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x58) + +/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0; + * Set this bit to generate CPU interrupt 0. This bit needs to be reset by + * software in the ISR process. + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_M (SYSTEM_CPU_INTR_FROM_CPU_0_V << SYSTEM_CPU_INTR_FROM_CPU_0_S) +#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x00000001 +#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 + +/* SYSTEM_CPU_INTR_FROM_CPU_1_REG register + * CPU interrupt controlling register 1 + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x5c) + +/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0; + * Set this bit to generate CPU interrupt 1. This bit needs to be reset by + * software in the ISR process. + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_M (SYSTEM_CPU_INTR_FROM_CPU_1_V << SYSTEM_CPU_INTR_FROM_CPU_1_S) +#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x00000001 +#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 + +/* SYSTEM_CPU_INTR_FROM_CPU_2_REG register + * CPU interrupt controlling register 2 + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x60) + +/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0; + * Set this bit to generate CPU interrupt 2. This bit needs to be reset by + * software in the ISR process. + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_M (SYSTEM_CPU_INTR_FROM_CPU_2_V << SYSTEM_CPU_INTR_FROM_CPU_2_S) +#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x00000001 +#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 + +/* SYSTEM_CPU_INTR_FROM_CPU_3_REG register + * CPU interrupt controlling register 3 + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x64) + +/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0; + * Set this bit to generate CPU interrupt 3. This bit needs to be reset by + * software in the ISR process. + */ + +#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_M (SYSTEM_CPU_INTR_FROM_CPU_3_V << SYSTEM_CPU_INTR_FROM_CPU_3_S) +#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x00000001 +#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 + +/* SYSTEM_RSA_PD_CTRL_REG register + * RSA memory remapping register + */ + +#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x68) + +/* SYSTEM_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power down RSA memory. This bit has the highest + * priority. + */ + +#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_M (SYSTEM_RSA_MEM_FORCE_PD_V << SYSTEM_RSA_MEM_FORCE_PD_S) +#define SYSTEM_RSA_MEM_FORCE_PD_V 0x00000001 +#define SYSTEM_RSA_MEM_FORCE_PD_S 2 + +/* SYSTEM_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0; + * Set this bit to force power up RSA memory. This bit has the second + * highest priority. + */ + +#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_M (SYSTEM_RSA_MEM_FORCE_PU_V << SYSTEM_RSA_MEM_FORCE_PU_S) +#define SYSTEM_RSA_MEM_FORCE_PU_V 0x00000001 +#define SYSTEM_RSA_MEM_FORCE_PU_S 1 + +/* SYSTEM_RSA_MEM_PD : R/W; bitpos: [0]; default: 1; + * Set this bit to power down RSA memory. This bit has the lowest priority. + * When Digital Signature occupies the RSA, this bit is invalid. + */ + +#define SYSTEM_RSA_MEM_PD (BIT(0)) +#define SYSTEM_RSA_MEM_PD_M (SYSTEM_RSA_MEM_PD_V << SYSTEM_RSA_MEM_PD_S) +#define SYSTEM_RSA_MEM_PD_V 0x00000001 +#define SYSTEM_RSA_MEM_PD_S 0 + +/* SYSTEM_BUSTOEXTMEM_ENA_REG register + * EDMA enable register + */ + +#define SYSTEM_BUSTOEXTMEM_ENA_REG (DR_REG_SYSTEM_BASE + 0x6c) + +/* SYSTEM_BUSTOEXTMEM_ENA : R/W; bitpos: [0]; default: 1; + * Set this bit to enable bus to EDMA. + */ + +#define SYSTEM_BUSTOEXTMEM_ENA (BIT(0)) +#define SYSTEM_BUSTOEXTMEM_ENA_M (SYSTEM_BUSTOEXTMEM_ENA_V << SYSTEM_BUSTOEXTMEM_ENA_S) +#define SYSTEM_BUSTOEXTMEM_ENA_V 0x00000001 +#define SYSTEM_BUSTOEXTMEM_ENA_S 0 + +/* SYSTEM_CACHE_CONTROL_REG register + * Cache control register + */ + +#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x70) + +/* SYSTEM_PRO_CACHE_RESET : R/W; bitpos: [2]; default: 0; + * Set this bit to reset cache. + */ + +#define SYSTEM_PRO_CACHE_RESET (BIT(2)) +#define SYSTEM_PRO_CACHE_RESET_M (SYSTEM_PRO_CACHE_RESET_V << SYSTEM_PRO_CACHE_RESET_S) +#define SYSTEM_PRO_CACHE_RESET_V 0x00000001 +#define SYSTEM_PRO_CACHE_RESET_S 2 + +/* SYSTEM_PRO_DCACHE_CLK_ON : R/W; bitpos: [1]; default: 1; + * Set this bit to enable clock of d-cache. + */ + +#define SYSTEM_PRO_DCACHE_CLK_ON (BIT(1)) +#define SYSTEM_PRO_DCACHE_CLK_ON_M (SYSTEM_PRO_DCACHE_CLK_ON_V << SYSTEM_PRO_DCACHE_CLK_ON_S) +#define SYSTEM_PRO_DCACHE_CLK_ON_V 0x00000001 +#define SYSTEM_PRO_DCACHE_CLK_ON_S 1 + +/* SYSTEM_PRO_ICACHE_CLK_ON : R/W; bitpos: [0]; default: 1; + * Set this bit to enable clock of i-cache. + */ + +#define SYSTEM_PRO_ICACHE_CLK_ON (BIT(0)) +#define SYSTEM_PRO_ICACHE_CLK_ON_M (SYSTEM_PRO_ICACHE_CLK_ON_V << SYSTEM_PRO_ICACHE_CLK_ON_S) +#define SYSTEM_PRO_ICACHE_CLK_ON_V 0x00000001 +#define SYSTEM_PRO_ICACHE_CLK_ON_S 0 + +/* SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register + * External memory encrypt and decrypt controlling register + */ + +#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x74) + +/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0; + * Set this bit to enable Manual Encryption under Download Boot mode. + */ + +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001 +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 + +/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0; + * Set this bit to enable Auto Decryption under Download Boot mode. + */ + +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001 +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 + +/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0; + * Set this bit to enable Auto Encryption under Download Boot mode. + */ + +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001 +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 + +/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0; + * Set this bit to enable Manual Encryption under SPI Boot mode. + */ + +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001 +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 + +/* SYSTEM_RTC_FASTMEM_CONFIG_REG register + * RTC fast memory configuration register + */ + +#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x78) + +/* SYSTEM_RTC_MEM_CRC_FINISH : RO; bitpos: [31]; default: 0; + * This bit stores the status of RTC memory CRC. High level means finished + * while low level means not finished. + */ + +#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_M (SYSTEM_RTC_MEM_CRC_FINISH_V << SYSTEM_RTC_MEM_CRC_FINISH_S) +#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x00000001 +#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 + +/* SYSTEM_RTC_MEM_CRC_LEN : R/W; bitpos: [30:20]; default: 2047; + * This field is used to set length of RTC memory for CRC based on start + * address. + */ + +#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FF +#define SYSTEM_RTC_MEM_CRC_LEN_M (SYSTEM_RTC_MEM_CRC_LEN_V << SYSTEM_RTC_MEM_CRC_LEN_S) +#define SYSTEM_RTC_MEM_CRC_LEN_V 0x000007FF +#define SYSTEM_RTC_MEM_CRC_LEN_S 20 + +/* SYSTEM_RTC_MEM_CRC_ADDR : R/W; bitpos: [19:9]; default: 0; + * This field is used to set address of RTC memory for CRC. + */ + +#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FF +#define SYSTEM_RTC_MEM_CRC_ADDR_M (SYSTEM_RTC_MEM_CRC_ADDR_V << SYSTEM_RTC_MEM_CRC_ADDR_S) +#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x000007FF +#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 + +/* SYSTEM_RTC_MEM_CRC_START : R/W; bitpos: [8]; default: 0; + * Set this bit to start the CRC of RTC memory. + */ + +#define SYSTEM_RTC_MEM_CRC_START (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_M (SYSTEM_RTC_MEM_CRC_START_V << SYSTEM_RTC_MEM_CRC_START_S) +#define SYSTEM_RTC_MEM_CRC_START_V 0x00000001 +#define SYSTEM_RTC_MEM_CRC_START_S 8 + +/* SYSTEM_RTC_FASTMEM_CRC_REG register + * RTC fast memory CRC controlling register + */ + +#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x7c) + +/* SYSTEM_RTC_MEM_CRC_RES : RO; bitpos: [31:0]; default: 0; + * This field stores the CRC result of RTC memory. + */ + +#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF +#define SYSTEM_RTC_MEM_CRC_RES_M (SYSTEM_RTC_MEM_CRC_RES_V << SYSTEM_RTC_MEM_CRC_RES_S) +#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF +#define SYSTEM_RTC_MEM_CRC_RES_S 0 + +/* SYSTEM_Redundant_ECO_Ctrl_REG register + * Redundant ECO control register + */ + +#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x80) + +/* SYSTEM_REDUNDANT_ECO_RESULT : RO; bitpos: [1]; default: 0; + * The redundant ECO result bit to avoid optimization in circuits. + */ + +#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_M (SYSTEM_REDUNDANT_ECO_RESULT_V << SYSTEM_REDUNDANT_ECO_RESULT_S) +#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x00000001 +#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 + +/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W; bitpos: [0]; default: 0; + * The redundant ECO drive bit to avoid optimization in circuits. + */ + +#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_M (SYSTEM_REDUNDANT_ECO_DRIVE_V << SYSTEM_REDUNDANT_ECO_DRIVE_S) +#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x00000001 +#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 + +/* SYSTEM_CLOCK_GATE_REG register + * Clock gate control register + */ + +#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x84) + +/* SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set this bit to enable clock of this module. + */ + +#define SYSTEM_CLK_EN (BIT(0)) +#define SYSTEM_CLK_EN_M (SYSTEM_CLK_EN_V << SYSTEM_CLK_EN_S) +#define SYSTEM_CLK_EN_V 0x00000001 +#define SYSTEM_CLK_EN_S 0 + +/* SYSTEM_SRAM_CTRL_2_REG register + * System SRAM configuration register 2 + */ + +#define SYSTEM_SRAM_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x88) + +/* SYSTEM_SRAM_FORCE_PU : R/W; bitpos: [21:0]; default: 4194303; + * This field is used to power up internal SRAM. + */ + +#define SYSTEM_SRAM_FORCE_PU 0x003FFFFF +#define SYSTEM_SRAM_FORCE_PU_M (SYSTEM_SRAM_FORCE_PU_V << SYSTEM_SRAM_FORCE_PU_S) +#define SYSTEM_SRAM_FORCE_PU_V 0x003FFFFF +#define SYSTEM_SRAM_FORCE_PU_S 0 + +/* SYSTEM_SYSCLK_CONF_REG register + * SoC clock configuration register + */ + +#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x8c) + +/* SYSTEM_CLK_DIV_EN : RO; bitpos: [19]; default: 0; + * Not used, extends from ESP32. + */ + +#define SYSTEM_CLK_DIV_EN (BIT(19)) +#define SYSTEM_CLK_DIV_EN_M (SYSTEM_CLK_DIV_EN_V << SYSTEM_CLK_DIV_EN_S) +#define SYSTEM_CLK_DIV_EN_V 0x00000001 +#define SYSTEM_CLK_DIV_EN_S 19 + +/* SYSTEM_CLK_XTAL_FREQ : RO; bitpos: [18:12]; default: 0; + * This field is used to read XTAL frequency in MHz. + */ + +#define SYSTEM_CLK_XTAL_FREQ 0x0000007F +#define SYSTEM_CLK_XTAL_FREQ_M (SYSTEM_CLK_XTAL_FREQ_V << SYSTEM_CLK_XTAL_FREQ_S) +#define SYSTEM_CLK_XTAL_FREQ_V 0x0000007F +#define SYSTEM_CLK_XTAL_FREQ_S 12 + +/* SYSTEM_SOC_CLK_SEL : R/W; bitpos: [11:10]; default: 0; + * This field is used to select SOC clock. + */ + +#define SYSTEM_SOC_CLK_SEL 0x00000003 +#define SYSTEM_SOC_CLK_SEL_M (SYSTEM_SOC_CLK_SEL_V << SYSTEM_SOC_CLK_SEL_S) +#define SYSTEM_SOC_CLK_SEL_V 0x00000003 +#define SYSTEM_SOC_CLK_SEL_S 10 + +/* SYSTEM_PRE_DIV_CNT : R/W; bitpos: [9:0]; default: 1; + * This field is used to set the count of prescaler of XTAL\_CLK. + */ + +#define SYSTEM_PRE_DIV_CNT 0x000003FF +#define SYSTEM_PRE_DIV_CNT_M (SYSTEM_PRE_DIV_CNT_V << SYSTEM_PRE_DIV_CNT_S) +#define SYSTEM_PRE_DIV_CNT_V 0x000003FF +#define SYSTEM_PRE_DIV_CNT_S 0 + +/* SYSTEM_REG_DATE_REG register + * Version control register + */ + +#define SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc) + +/* SYSTEM_SYSTEM_REG_DATE : R/W; bitpos: [27:0]; default: 26247200; + * This is the date version register. + */ + +#define SYSTEM_SYSTEM_REG_DATE 0x0FFFFFFF +#define SYSTEM_SYSTEM_REG_DATE_M (SYSTEM_SYSTEM_REG_DATE_V << SYSTEM_SYSTEM_REG_DATE_S) +#define SYSTEM_SYSTEM_REG_DATE_V 0x0FFFFFFF +#define SYSTEM_SYSTEM_REG_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SYSTEM_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_tim.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_tim.h new file mode 100644 index 0000000000..7d6532b825 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_tim.h @@ -0,0 +1,1265 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_timg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_TIMG_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_TIMG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* TIMG_T0CONFIG_REG register + * Timer 0 configuration register + */ + +#define TIMG_T0CONFIG_REG (DR_REG_TIMG_BASE + 0x0) + +/* TIMG_T0_EN : R/W; bitpos: [31]; default: 0; + * When set, the timer 0 time-base counter is enabled. + */ + +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S) +#define TIMG_T0_EN_V 0x00000001 +#define TIMG_T0_EN_S 31 + +/* TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1; + * When set, the timer 0 time-base counter will increment every clock tick. + * When + * + * cleared, the timer 0 time-base counter will decrement. + */ + +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S) +#define TIMG_T0_INCREASE_V 0x00000001 +#define TIMG_T0_INCREASE_S 30 + +/* TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * When set, timer 0 auto-reload at alarm is enabled. + */ + +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S) +#define TIMG_T0_AUTORELOAD_V 0x00000001 +#define TIMG_T0_AUTORELOAD_S 29 + +/* TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Timer 0 clock (T0_clk) prescaler value. + */ + +#define TIMG_T0_DIVIDER 0x0000FFFF +#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S) +#define TIMG_T0_DIVIDER_V 0x0000FFFF +#define TIMG_T0_DIVIDER_S 13 + +/* TIMG_T0_EDGE_INT_EN : R/W; bitpos: [12]; default: 0; + * When set, an alarm will generate an edge type interrupt. + */ + +#define TIMG_T0_EDGE_INT_EN (BIT(12)) +#define TIMG_T0_EDGE_INT_EN_M (TIMG_T0_EDGE_INT_EN_V << TIMG_T0_EDGE_INT_EN_S) +#define TIMG_T0_EDGE_INT_EN_V 0x00000001 +#define TIMG_T0_EDGE_INT_EN_S 12 + +/* TIMG_T0_LEVEL_INT_EN : R/W; bitpos: [11]; default: 0; + * When set, an alarm will generate a level type interrupt. + */ + +#define TIMG_T0_LEVEL_INT_EN (BIT(11)) +#define TIMG_T0_LEVEL_INT_EN_M (TIMG_T0_LEVEL_INT_EN_V << TIMG_T0_LEVEL_INT_EN_S) +#define TIMG_T0_LEVEL_INT_EN_V 0x00000001 +#define TIMG_T0_LEVEL_INT_EN_S 11 + +/* TIMG_T0_ALARM_EN : R/W; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * + * alarm occurs. + */ + +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S) +#define TIMG_T0_ALARM_EN_V 0x00000001 +#define TIMG_T0_ALARM_EN_S 10 + +/* TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0; + * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the + * source clock of timer group. + */ + +#define TIMG_T0_USE_XTAL (BIT(9)) +#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S) +#define TIMG_T0_USE_XTAL_V 0x00000001 +#define TIMG_T0_USE_XTAL_S 9 + +/* TIMG_T0LO_REG register + * Timer 0 current value, low 32 bits + */ + +#define TIMG_T0LO_REG (DR_REG_TIMG_BASE + 0x4) + +/* TIMG_T0_LO : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base + * counter + * + * of timer 0 can be read here. + */ + +#define TIMG_T0_LO 0xFFFFFFFF +#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S) +#define TIMG_T0_LO_V 0xFFFFFFFF +#define TIMG_T0_LO_S 0 + +/* TIMG_T0HI_REG register + * Timer 0 current value, high 32 bits + */ + +#define TIMG_T0HI_REG (DR_REG_TIMG_BASE + 0x8) + +/* TIMG_T0_HI : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T0UPDATE_REG, the high 32 bits of the time-base + * counter + * + * of timer 0 can be read here. + */ + +#define TIMG_T0_HI 0xFFFFFFFF +#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S) +#define TIMG_T0_HI_V 0xFFFFFFFF +#define TIMG_T0_HI_S 0 + +/* TIMG_T0UPDATE_REG register + * Write to copy current timer value to TIMGn_T0_(LO/HI)_REG + */ + +#define TIMG_T0UPDATE_REG (DR_REG_TIMG_BASE + 0xc) + +/* TIMG_T0_UPDATE : R/W; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched. + */ + +#define TIMG_T0_UPDATE (BIT(31)) +#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S) +#define TIMG_T0_UPDATE_V 0x00000001 +#define TIMG_T0_UPDATE_S 31 + +/* TIMG_T0ALARMLO_REG register + * Timer 0 alarm value, low 32 bits + */ + +#define TIMG_T0ALARMLO_REG (DR_REG_TIMG_BASE + 0x10) + +/* TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Timer 0 alarm trigger time-base counter value, low 32 bits. + */ + +#define TIMG_T0_ALARM_LO 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_S 0 + +/* TIMG_T0ALARMHI_REG register + * Timer 0 alarm value, high bits + */ + +#define TIMG_T0ALARMHI_REG (DR_REG_TIMG_BASE + 0x14) + +/* TIMG_T0_ALARM_HI : R/W; bitpos: [31:0]; default: 0; + * + * + * Timer 0 alarm trigger time-base counter value, high 32 bits. + */ + +#define TIMG_T0_ALARM_HI 0xFFFFFFFF +#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S) +#define TIMG_T0_ALARM_HI_V 0xFFFFFFFF +#define TIMG_T0_ALARM_HI_S 0 + +/* TIMG_T0LOADLO_REG register + * Timer 0 reload value, low 32 bits + */ + +#define TIMG_T0LOADLO_REG (DR_REG_TIMG_BASE + 0x18) + +/* TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * + * + * Low 32 bits of the value that a reload will load onto timer 0 time-base + * + * Counter. + */ + +#define TIMG_T0_LOAD_LO 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_S 0 + +/* TIMG_T0LOADHI_REG register + * Timer 0 reload value, high 32 bits + */ + +#define TIMG_T0LOADHI_REG (DR_REG_TIMG_BASE + 0x1c) + +/* TIMG_T0_LOAD_HI : R/W; bitpos: [31:0]; default: 0; + * + * + * High 32 bits of the value that a reload will load onto timer 0 time-base + * + * counter. + */ + +#define TIMG_T0_LOAD_HI 0xFFFFFFFF +#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S) +#define TIMG_T0_LOAD_HI_V 0xFFFFFFFF +#define TIMG_T0_LOAD_HI_S 0 + +/* TIMG_T0LOAD_REG register + * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG + */ + +#define TIMG_T0LOAD_REG (DR_REG_TIMG_BASE + 0x20) + +/* TIMG_T0_LOAD : WO; bitpos: [31:0]; default: 0; + * + * + * Write any value to trigger a timer 0 time-base counter reload. + */ + +#define TIMG_T0_LOAD 0xFFFFFFFF +#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S) +#define TIMG_T0_LOAD_V 0xFFFFFFFF +#define TIMG_T0_LOAD_S 0 + +/* TIMG_T1CONFIG_REG register + * Timer 1 configuration register + */ + +#define TIMG_T1CONFIG_REG (DR_REG_TIMG_BASE + 0x24) + +/* TIMG_T1_EN : R/W; bitpos: [31]; default: 0; + * When set, the timer 1 time-base counter is enabled. + */ + +#define TIMG_T1_EN (BIT(31)) +#define TIMG_T1_EN_M (TIMG_T1_EN_V << TIMG_T1_EN_S) +#define TIMG_T1_EN_V 0x00000001 +#define TIMG_T1_EN_S 31 + +/* TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1; + * When set, the timer 1 time-base counter will increment every clock tick. + * When + * + * cleared, the timer 1 time-base counter will decrement. + */ + +#define TIMG_T1_INCREASE (BIT(30)) +#define TIMG_T1_INCREASE_M (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S) +#define TIMG_T1_INCREASE_V 0x00000001 +#define TIMG_T1_INCREASE_S 30 + +/* TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * When set, timer 1 auto-reload at alarm is enabled. + */ + +#define TIMG_T1_AUTORELOAD (BIT(29)) +#define TIMG_T1_AUTORELOAD_M (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S) +#define TIMG_T1_AUTORELOAD_V 0x00000001 +#define TIMG_T1_AUTORELOAD_S 29 + +/* TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Timer 1 clock (T1_clk) prescaler value. + */ + +#define TIMG_T1_DIVIDER 0x0000FFFF +#define TIMG_T1_DIVIDER_M (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S) +#define TIMG_T1_DIVIDER_V 0x0000FFFF +#define TIMG_T1_DIVIDER_S 13 + +/* TIMG_T1_EDGE_INT_EN : R/W; bitpos: [12]; default: 0; + * When set, an alarm will generate an edge type interrupt. + */ + +#define TIMG_T1_EDGE_INT_EN (BIT(12)) +#define TIMG_T1_EDGE_INT_EN_M (TIMG_T1_EDGE_INT_EN_V << TIMG_T1_EDGE_INT_EN_S) +#define TIMG_T1_EDGE_INT_EN_V 0x00000001 +#define TIMG_T1_EDGE_INT_EN_S 12 + +/* TIMG_T1_LEVEL_INT_EN : R/W; bitpos: [11]; default: 0; + * When set, an alarm will generate a level type interrupt. + */ + +#define TIMG_T1_LEVEL_INT_EN (BIT(11)) +#define TIMG_T1_LEVEL_INT_EN_M (TIMG_T1_LEVEL_INT_EN_V << TIMG_T1_LEVEL_INT_EN_S) +#define TIMG_T1_LEVEL_INT_EN_V 0x00000001 +#define TIMG_T1_LEVEL_INT_EN_S 11 + +/* TIMG_T1_ALARM_EN : R/W; bitpos: [10]; default: 0; + * When set, the alarm is enabled. This bit is automatically cleared once an + * + * alarm occurs. + */ + +#define TIMG_T1_ALARM_EN (BIT(10)) +#define TIMG_T1_ALARM_EN_M (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S) +#define TIMG_T1_ALARM_EN_V 0x00000001 +#define TIMG_T1_ALARM_EN_S 10 + +/* TIMG_T1_USE_XTAL : R/W; bitpos: [9]; default: 0; + * 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the + * source clock of timer group. + */ + +#define TIMG_T1_USE_XTAL (BIT(9)) +#define TIMG_T1_USE_XTAL_M (TIMG_T1_USE_XTAL_V << TIMG_T1_USE_XTAL_S) +#define TIMG_T1_USE_XTAL_V 0x00000001 +#define TIMG_T1_USE_XTAL_S 9 + +/* TIMG_T1LO_REG register + * Timer 1 current value, low 32 bits + */ + +#define TIMG_T1LO_REG (DR_REG_TIMG_BASE + 0x28) + +/* TIMG_T1_LO : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base + * counter + * + * of timer 1 can be read here. + */ + +#define TIMG_T1_LO 0xFFFFFFFF +#define TIMG_T1_LO_M (TIMG_T1_LO_V << TIMG_T1_LO_S) +#define TIMG_T1_LO_V 0xFFFFFFFF +#define TIMG_T1_LO_S 0 + +/* TIMG_T1HI_REG register + * Timer 1 current value, high 32 bits + */ + +#define TIMG_T1HI_REG (DR_REG_TIMG_BASE + 0x2c) + +/* TIMG_T1_HI : RO; bitpos: [31:0]; default: 0; + * After writing to TIMG_T1UPDATE_REG, the high 32 bits of the time-base + * counter + * + * of timer 1 can be read here. + */ + +#define TIMG_T1_HI 0xFFFFFFFF +#define TIMG_T1_HI_M (TIMG_T1_HI_V << TIMG_T1_HI_S) +#define TIMG_T1_HI_V 0xFFFFFFFF +#define TIMG_T1_HI_S 0 + +/* TIMG_T1UPDATE_REG register + * Write to copy current timer value to TIMGn_T1_(LO/HI)_REG + */ + +#define TIMG_T1UPDATE_REG (DR_REG_TIMG_BASE + 0x30) + +/* TIMG_T1_UPDATE : R/W; bitpos: [31]; default: 0; + * After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched. + */ + +#define TIMG_T1_UPDATE (BIT(31)) +#define TIMG_T1_UPDATE_M (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S) +#define TIMG_T1_UPDATE_V 0x00000001 +#define TIMG_T1_UPDATE_S 31 + +/* TIMG_T1ALARMLO_REG register + * Timer 1 alarm value, low 32 bits + */ + +#define TIMG_T1ALARMLO_REG (DR_REG_TIMG_BASE + 0x34) + +/* TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Timer 1 alarm trigger time-base counter value, low 32 bits. + */ + +#define TIMG_T1_ALARM_LO 0xFFFFFFFF +#define TIMG_T1_ALARM_LO_M (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S) +#define TIMG_T1_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T1_ALARM_LO_S 0 + +/* TIMG_T1ALARMHI_REG register + * Timer 1 alarm value, high bits + */ + +#define TIMG_T1ALARMHI_REG (DR_REG_TIMG_BASE + 0x38) + +/* TIMG_T1_ALARM_HI : R/W; bitpos: [31:0]; default: 0; + * + * + * Timer 1 alarm trigger time-base counter value, high 32 bits. + */ + +#define TIMG_T1_ALARM_HI 0xFFFFFFFF +#define TIMG_T1_ALARM_HI_M (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S) +#define TIMG_T1_ALARM_HI_V 0xFFFFFFFF +#define TIMG_T1_ALARM_HI_S 0 + +/* TIMG_T1LOADLO_REG register + * Timer 1 reload value, low 32 bits + */ + +#define TIMG_T1LOADLO_REG (DR_REG_TIMG_BASE + 0x3c) + +/* TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * + * + * Low 32 bits of the value that a reload will load onto timer 1 time-base + * + * Counter. + */ + +#define TIMG_T1_LOAD_LO 0xFFFFFFFF +#define TIMG_T1_LOAD_LO_M (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S) +#define TIMG_T1_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T1_LOAD_LO_S 0 + +/* TIMG_T1LOADHI_REG register + * Timer 1 reload value, high 32 bits + */ + +#define TIMG_T1LOADHI_REG (DR_REG_TIMG_BASE + 0x40) + +/* TIMG_T1_LOAD_HI : R/W; bitpos: [31:0]; default: 0; + * + * + * High 32 bits of the value that a reload will load onto timer 1 time-base + * + * counter. + */ + +#define TIMG_T1_LOAD_HI 0xFFFFFFFF +#define TIMG_T1_LOAD_HI_M (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S) +#define TIMG_T1_LOAD_HI_V 0xFFFFFFFF +#define TIMG_T1_LOAD_HI_S 0 + +/* TIMG_T1LOAD_REG register + * Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG + */ + +#define TIMG_T1LOAD_REG (DR_REG_TIMG_BASE + 0x44) + +/* TIMG_T1_LOAD : WO; bitpos: [31:0]; default: 0; + * + * + * Write any value to trigger a timer 1 time-base counter reload. + */ + +#define TIMG_T1_LOAD 0xFFFFFFFF +#define TIMG_T1_LOAD_M (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S) +#define TIMG_T1_LOAD_V 0xFFFFFFFF +#define TIMG_T1_LOAD_S 0 + +/* TIMG_WDTCONFIG0_REG register + * Watchdog timer configuration register + */ + +#define TIMG_WDTCONFIG0_REG (DR_REG_TIMG_BASE + 0x48) + +/* TIMG_WDT_EN : R/W; bitpos: [31]; default: 0; + * When set, MWDT is enabled. + */ + +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S) +#define TIMG_WDT_EN_V 0x00000001 +#define TIMG_WDT_EN_S 31 + +/* TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0; + * Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset + * system. + * + */ + +#define TIMG_WDT_STG0 0x00000003 +#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S) +#define TIMG_WDT_STG0_V 0x00000003 +#define TIMG_WDT_STG0_S 29 + +/* TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0; + * Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset + * system. + * + */ + +#define TIMG_WDT_STG1 0x00000003 +#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S) +#define TIMG_WDT_STG1_V 0x00000003 +#define TIMG_WDT_STG1_S 27 + +/* TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0; + * Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset + * system. + * + */ + +#define TIMG_WDT_STG2 0x00000003 +#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S) +#define TIMG_WDT_STG2_V 0x00000003 +#define TIMG_WDT_STG2_S 25 + +/* TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0; + * Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset + * system. + * + */ + +#define TIMG_WDT_STG3 0x00000003 +#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S) +#define TIMG_WDT_STG3_V 0x00000003 +#define TIMG_WDT_STG3_S 23 + +/* TIMG_WDT_EDGE_INT_EN : R/W; bitpos: [22]; default: 0; + * When set, an edge type interrupt will occur at the timeout of a stage + * + * configured to generate an interrupt. + */ + +#define TIMG_WDT_EDGE_INT_EN (BIT(22)) +#define TIMG_WDT_EDGE_INT_EN_M (TIMG_WDT_EDGE_INT_EN_V << TIMG_WDT_EDGE_INT_EN_S) +#define TIMG_WDT_EDGE_INT_EN_V 0x00000001 +#define TIMG_WDT_EDGE_INT_EN_S 22 + +/* TIMG_WDT_LEVEL_INT_EN : R/W; bitpos: [21]; default: 0; + * When set, a level type interrupt will occur at the timeout of a stage + * + * configured to generate an interrupt. + */ + +#define TIMG_WDT_LEVEL_INT_EN (BIT(21)) +#define TIMG_WDT_LEVEL_INT_EN_M (TIMG_WDT_LEVEL_INT_EN_V << TIMG_WDT_LEVEL_INT_EN_S) +#define TIMG_WDT_LEVEL_INT_EN_V 0x00000001 +#define TIMG_WDT_LEVEL_INT_EN_S 21 + +/* TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1; + * CPU reset signal length selection. 0: 100 ns, 1: 200 ns, + * + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007 +#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007 +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 + +/* TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1; + * System reset signal length selection. 0: 100 ns, 1: 200 ns, + * + * 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us. + */ + +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007 +#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007 +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 + +/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1; + * When set, Flash boot protection is enabled. + */ + +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001 +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 + +/* TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0; + * WDT reset CPU enable. + */ + +#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S) +#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001 +#define TIMG_WDT_PROCPU_RESET_EN_S 13 + +/* TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0; + * Reserved + */ + +#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S) +#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001 +#define TIMG_WDT_APPCPU_RESET_EN_S 12 + +/* TIMG_WDTCONFIG1_REG register + * Watchdog timer prescaler register + */ + +#define TIMG_WDTCONFIG1_REG (DR_REG_TIMG_BASE + 0x4c) + +/* TIMG_WDT_CLK_PRESCALER : R/W; bitpos: [31:16]; default: 1; + * MWDT clock prescaler value. MWDT clock period = 12.5 ns * + * + * TIMG_WDT_CLK_PRESCALE. + */ + +#define TIMG_WDT_CLK_PRESCALER 0x0000FFFF +#define TIMG_WDT_CLK_PRESCALER_M (TIMG_WDT_CLK_PRESCALER_V << TIMG_WDT_CLK_PRESCALER_S) +#define TIMG_WDT_CLK_PRESCALER_V 0x0000FFFF +#define TIMG_WDT_CLK_PRESCALER_S 16 + +/* TIMG_WDTCONFIG2_REG register + * Watchdog timer stage 0 timeout value + */ + +#define TIMG_WDTCONFIG2_REG (DR_REG_TIMG_BASE + 0x50) + +/* TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000; + * Stage 0 timeout value, in MWDT clock cycles. + */ + +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_S 0 + +/* TIMG_WDTCONFIG3_REG register + * Watchdog timer stage 1 timeout value + */ + +#define TIMG_WDTCONFIG3_REG (DR_REG_TIMG_BASE + 0x54) + +/* TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727; + * Stage 1 timeout value, in MWDT clock cycles. + */ + +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_S 0 + +/* TIMG_WDTCONFIG4_REG register + * Watchdog timer stage 2 timeout value + */ + +#define TIMG_WDTCONFIG4_REG (DR_REG_TIMG_BASE + 0x58) + +/* TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 2 timeout value, in MWDT clock cycles. + */ + +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_S 0 + +/* TIMG_WDTCONFIG5_REG register + * Watchdog timer stage 3 timeout value + */ + +#define TIMG_WDTCONFIG5_REG (DR_REG_TIMG_BASE + 0x5c) + +/* TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575; + * Stage 3 timeout value, in MWDT clock cycles. + */ + +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_S 0 + +/* TIMG_WDTFEED_REG register + * Write to feed the watchdog timer + */ + +#define TIMG_WDTFEED_REG (DR_REG_TIMG_BASE + 0x60) + +/* TIMG_WDT_FEED : WO; bitpos: [31:0]; default: 0; + * Write any value to feed the MWDT. (WO) + */ + +#define TIMG_WDT_FEED 0xFFFFFFFF +#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S) +#define TIMG_WDT_FEED_V 0xFFFFFFFF +#define TIMG_WDT_FEED_S 0 + +/* TIMG_WDTWPROTECT_REG register + * Watchdog write protect register + */ + +#define TIMG_WDTWPROTECT_REG (DR_REG_TIMG_BASE + 0x64) + +/* TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; + * If the register contains a different value than its reset value, write + * + * protection is enabled. + */ + +#define TIMG_WDT_WKEY 0xFFFFFFFF +#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S) +#define TIMG_WDT_WKEY_V 0xFFFFFFFF +#define TIMG_WDT_WKEY_S 0 + +/* TIMG_RTCCALICFG_REG register + * RTC calibration configuration register + */ + +#define TIMG_RTCCALICFG_REG (DR_REG_TIMG_BASE + 0x68) + +/* TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0; + * Reserved + */ + +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S) +#define TIMG_RTC_CALI_START_V 0x00000001 +#define TIMG_RTC_CALI_START_S 31 + +/* TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1; + * Reserved + */ + +#define TIMG_RTC_CALI_MAX 0x00007FFF +#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S) +#define TIMG_RTC_CALI_MAX_V 0x00007FFF +#define TIMG_RTC_CALI_MAX_S 16 + +/* TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0; + * Reserved + */ + +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S) +#define TIMG_RTC_CALI_RDY_V 0x00000001 +#define TIMG_RTC_CALI_RDY_S 15 + +/* TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 1; + * 0:rtcslowclock. 1:clk_80m. 2:xtal_32k. + */ + +#define TIMG_RTC_CALI_CLK_SEL 0x00000003 +#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S) +#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003 +#define TIMG_RTC_CALI_CLK_SEL_S 13 + +/* TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1; + * Reserved + */ + +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S) +#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001 +#define TIMG_RTC_CALI_START_CYCLING_S 12 + +/* TIMG_RTCCALICFG1_REG register + * RTC calibration configuration1 register + */ + +#define TIMG_RTCCALICFG1_REG (DR_REG_TIMG_BASE + 0x6c) + +/* TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0; + * Reserved + */ + +#define TIMG_RTC_CALI_VALUE 0x01FFFFFF +#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S) +#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFF +#define TIMG_RTC_CALI_VALUE_S 7 + +/* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0; + * Reserved + */ + +#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001 +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 + +/* TIMG_LACTCONFIG_REG register + * LACT configuration register + */ + +#define TIMG_LACTCONFIG_REG (DR_REG_TIMG_BASE + 0x70) + +/* TIMG_LACT_EN : R/W; bitpos: [31]; default: 0; + * Reserved + */ + +#define TIMG_LACT_EN (BIT(31)) +#define TIMG_LACT_EN_M (TIMG_LACT_EN_V << TIMG_LACT_EN_S) +#define TIMG_LACT_EN_V 0x00000001 +#define TIMG_LACT_EN_S 31 + +/* TIMG_LACT_INCREASE : R/W; bitpos: [30]; default: 1; + * Reserved + */ + +#define TIMG_LACT_INCREASE (BIT(30)) +#define TIMG_LACT_INCREASE_M (TIMG_LACT_INCREASE_V << TIMG_LACT_INCREASE_S) +#define TIMG_LACT_INCREASE_V 0x00000001 +#define TIMG_LACT_INCREASE_S 30 + +/* TIMG_LACT_AUTORELOAD : R/W; bitpos: [29]; default: 1; + * Reserved + */ + +#define TIMG_LACT_AUTORELOAD (BIT(29)) +#define TIMG_LACT_AUTORELOAD_M (TIMG_LACT_AUTORELOAD_V << TIMG_LACT_AUTORELOAD_S) +#define TIMG_LACT_AUTORELOAD_V 0x00000001 +#define TIMG_LACT_AUTORELOAD_S 29 + +/* TIMG_LACT_DIVIDER : R/W; bitpos: [28:13]; default: 1; + * Reserved + */ + +#define TIMG_LACT_DIVIDER 0x0000FFFF +#define TIMG_LACT_DIVIDER_M (TIMG_LACT_DIVIDER_V << TIMG_LACT_DIVIDER_S) +#define TIMG_LACT_DIVIDER_V 0x0000FFFF +#define TIMG_LACT_DIVIDER_S 13 + +/* TIMG_LACT_EDGE_INT_EN : R/W; bitpos: [12]; default: 0; + * Reserved + */ + +#define TIMG_LACT_EDGE_INT_EN (BIT(12)) +#define TIMG_LACT_EDGE_INT_EN_M (TIMG_LACT_EDGE_INT_EN_V << TIMG_LACT_EDGE_INT_EN_S) +#define TIMG_LACT_EDGE_INT_EN_V 0x00000001 +#define TIMG_LACT_EDGE_INT_EN_S 12 + +/* TIMG_LACT_LEVEL_INT_EN : R/W; bitpos: [11]; default: 0; + * Reserved + */ + +#define TIMG_LACT_LEVEL_INT_EN (BIT(11)) +#define TIMG_LACT_LEVEL_INT_EN_M (TIMG_LACT_LEVEL_INT_EN_V << TIMG_LACT_LEVEL_INT_EN_S) +#define TIMG_LACT_LEVEL_INT_EN_V 0x00000001 +#define TIMG_LACT_LEVEL_INT_EN_S 11 + +/* TIMG_LACT_ALARM_EN : R/W; bitpos: [10]; default: 0; + * Reserved + */ + +#define TIMG_LACT_ALARM_EN (BIT(10)) +#define TIMG_LACT_ALARM_EN_M (TIMG_LACT_ALARM_EN_V << TIMG_LACT_ALARM_EN_S) +#define TIMG_LACT_ALARM_EN_V 0x00000001 +#define TIMG_LACT_ALARM_EN_S 10 + +/* TIMG_LACT_LAC_EN : R/W; bitpos: [9]; default: 1; + * Reserved + */ + +#define TIMG_LACT_LAC_EN (BIT(9)) +#define TIMG_LACT_LAC_EN_M (TIMG_LACT_LAC_EN_V << TIMG_LACT_LAC_EN_S) +#define TIMG_LACT_LAC_EN_V 0x00000001 +#define TIMG_LACT_LAC_EN_S 9 + +/* TIMG_LACT_CPST_EN : R/W; bitpos: [8]; default: 1; + * Reserved + */ + +#define TIMG_LACT_CPST_EN (BIT(8)) +#define TIMG_LACT_CPST_EN_M (TIMG_LACT_CPST_EN_V << TIMG_LACT_CPST_EN_S) +#define TIMG_LACT_CPST_EN_V 0x00000001 +#define TIMG_LACT_CPST_EN_S 8 + +/* TIMG_LACT_RTC_ONLY : R/W; bitpos: [7]; default: 0; + * Reserved + */ + +#define TIMG_LACT_RTC_ONLY (BIT(7)) +#define TIMG_LACT_RTC_ONLY_M (TIMG_LACT_RTC_ONLY_V << TIMG_LACT_RTC_ONLY_S) +#define TIMG_LACT_RTC_ONLY_V 0x00000001 +#define TIMG_LACT_RTC_ONLY_S 7 + +/* TIMG_LACT_USE_REFTICK : R/W; bitpos: [6]; default: 0; + * Reserved + */ + +#define TIMG_LACT_USE_REFTICK (BIT(6)) +#define TIMG_LACT_USE_REFTICK_M (TIMG_LACT_USE_REFTICK_V << TIMG_LACT_USE_REFTICK_S) +#define TIMG_LACT_USE_REFTICK_V 0x00000001 +#define TIMG_LACT_USE_REFTICK_S 6 + +/* TIMG_LACTRTC_REG register + * LACT RTC register + */ + +#define TIMG_LACTRTC_REG (DR_REG_TIMG_BASE + 0x74) + +/* TIMG_LACT_RTC_STEP_LEN : R/W; bitpos: [31:6]; default: 0; + * Reserved + */ + +#define TIMG_LACT_RTC_STEP_LEN 0x03FFFFFF +#define TIMG_LACT_RTC_STEP_LEN_M (TIMG_LACT_RTC_STEP_LEN_V << TIMG_LACT_RTC_STEP_LEN_S) +#define TIMG_LACT_RTC_STEP_LEN_V 0x03FFFFFF +#define TIMG_LACT_RTC_STEP_LEN_S 6 + +/* TIMG_LACTLO_REG register + * LACT low register + */ + +#define TIMG_LACTLO_REG (DR_REG_TIMG_BASE + 0x78) + +/* TIMG_LACT_LO : RO; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_LO 0xFFFFFFFF +#define TIMG_LACT_LO_M (TIMG_LACT_LO_V << TIMG_LACT_LO_S) +#define TIMG_LACT_LO_V 0xFFFFFFFF +#define TIMG_LACT_LO_S 0 + +/* TIMG_LACTHI_REG register + * LACT high register + */ + +#define TIMG_LACTHI_REG (DR_REG_TIMG_BASE + 0x7c) + +/* TIMG_LACT_HI : RO; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_HI 0xFFFFFFFF +#define TIMG_LACT_HI_M (TIMG_LACT_HI_V << TIMG_LACT_HI_S) +#define TIMG_LACT_HI_V 0xFFFFFFFF +#define TIMG_LACT_HI_S 0 + +/* TIMG_LACTUPDATE_REG register + * LACT update register + */ + +#define TIMG_LACTUPDATE_REG (DR_REG_TIMG_BASE + 0x80) + +/* TIMG_LACT_UPDATE : WO; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_UPDATE 0xFFFFFFFF +#define TIMG_LACT_UPDATE_M (TIMG_LACT_UPDATE_V << TIMG_LACT_UPDATE_S) +#define TIMG_LACT_UPDATE_V 0xFFFFFFFF +#define TIMG_LACT_UPDATE_S 0 + +/* TIMG_LACTALARMLO_REG register + * LACT alarm low register + */ + +#define TIMG_LACTALARMLO_REG (DR_REG_TIMG_BASE + 0x84) + +/* TIMG_LACT_ALARM_LO : R/W; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_ALARM_LO 0xFFFFFFFF +#define TIMG_LACT_ALARM_LO_M (TIMG_LACT_ALARM_LO_V << TIMG_LACT_ALARM_LO_S) +#define TIMG_LACT_ALARM_LO_V 0xFFFFFFFF +#define TIMG_LACT_ALARM_LO_S 0 + +/* TIMG_LACTALARMHI_REG register + * LACT alarm high register + */ + +#define TIMG_LACTALARMHI_REG (DR_REG_TIMG_BASE + 0x88) + +/* TIMG_LACT_ALARM_HI : R/W; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_ALARM_HI 0xFFFFFFFF +#define TIMG_LACT_ALARM_HI_M (TIMG_LACT_ALARM_HI_V << TIMG_LACT_ALARM_HI_S) +#define TIMG_LACT_ALARM_HI_V 0xFFFFFFFF +#define TIMG_LACT_ALARM_HI_S 0 + +/* TIMG_LACTLOADLO_REG register + * LACT load low register + */ + +#define TIMG_LACTLOADLO_REG (DR_REG_TIMG_BASE + 0x8c) + +/* TIMG_LACT_LOAD_LO : R/W; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_LOAD_LO 0xFFFFFFFF +#define TIMG_LACT_LOAD_LO_M (TIMG_LACT_LOAD_LO_V << TIMG_LACT_LOAD_LO_S) +#define TIMG_LACT_LOAD_LO_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_LO_S 0 + +/* TIMG_LACTLOADHI_REG register + * Timer LACT load high register + */ + +#define TIMG_LACTLOADHI_REG (DR_REG_TIMG_BASE + 0x90) + +/* TIMG_LACT_LOAD_HI : R/W; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_LOAD_HI 0xFFFFFFFF +#define TIMG_LACT_LOAD_HI_M (TIMG_LACT_LOAD_HI_V << TIMG_LACT_LOAD_HI_S) +#define TIMG_LACT_LOAD_HI_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_HI_S 0 + +/* TIMG_LACTLOAD_REG register + * Timer LACT load register + */ + +#define TIMG_LACTLOAD_REG (DR_REG_TIMG_BASE + 0x94) + +/* TIMG_LACT_LOAD : WO; bitpos: [31:0]; default: 0; + * Reserved + */ + +#define TIMG_LACT_LOAD 0xFFFFFFFF +#define TIMG_LACT_LOAD_M (TIMG_LACT_LOAD_V << TIMG_LACT_LOAD_S) +#define TIMG_LACT_LOAD_V 0xFFFFFFFF +#define TIMG_LACT_LOAD_S 0 + +/* TIMG_INT_ENA_TIMERS_REG register + * Interrupt enable bits + */ + +#define TIMG_INT_ENA_TIMERS_REG (DR_REG_TIMG_BASE + 0x98) + +/* TIMG_LACT_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the TIMG_LACT_INT interrupt. + */ + +#define TIMG_LACT_INT_ENA (BIT(3)) +#define TIMG_LACT_INT_ENA_M (TIMG_LACT_INT_ENA_V << TIMG_LACT_INT_ENA_S) +#define TIMG_LACT_INT_ENA_V 0x00000001 +#define TIMG_LACT_INT_ENA_S 3 + +/* TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the TIMG_WDT_INT interrupt. + */ + +#define TIMG_WDT_INT_ENA (BIT(2)) +#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S) +#define TIMG_WDT_INT_ENA_V 0x00000001 +#define TIMG_WDT_INT_ENA_S 2 + +/* TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the TIMG_T1_INT interrupt. + */ + +#define TIMG_T1_INT_ENA (BIT(1)) +#define TIMG_T1_INT_ENA_M (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S) +#define TIMG_T1_INT_ENA_V 0x00000001 +#define TIMG_T1_INT_ENA_S 1 + +/* TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the TIMG_T0_INT interrupt. + */ + +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S) +#define TIMG_T0_INT_ENA_V 0x00000001 +#define TIMG_T0_INT_ENA_S 0 + +/* TIMG_INT_RAW_TIMERS_REG register + * Raw interrupt status + */ + +#define TIMG_INT_RAW_TIMERS_REG (DR_REG_TIMG_BASE + 0x9c) + +/* TIMG_LACT_INT_RAW : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the TIMG_LACT_INT interrupt. + */ + +#define TIMG_LACT_INT_RAW (BIT(3)) +#define TIMG_LACT_INT_RAW_M (TIMG_LACT_INT_RAW_V << TIMG_LACT_INT_RAW_S) +#define TIMG_LACT_INT_RAW_V 0x00000001 +#define TIMG_LACT_INT_RAW_S 3 + +/* TIMG_WDT_INT_RAW : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the TIMG_WDT_INT interrupt. + */ + +#define TIMG_WDT_INT_RAW (BIT(2)) +#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S) +#define TIMG_WDT_INT_RAW_V 0x00000001 +#define TIMG_WDT_INT_RAW_S 2 + +/* TIMG_T1_INT_RAW : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the TIMG_T1_INT interrupt. + */ + +#define TIMG_T1_INT_RAW (BIT(1)) +#define TIMG_T1_INT_RAW_M (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S) +#define TIMG_T1_INT_RAW_V 0x00000001 +#define TIMG_T1_INT_RAW_S 1 + +/* TIMG_T0_INT_RAW : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the TIMG_T0_INT interrupt. + */ + +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S) +#define TIMG_T0_INT_RAW_V 0x00000001 +#define TIMG_T0_INT_RAW_S 0 + +/* TIMG_INT_ST_TIMERS_REG register + * Masked interrupt status + */ + +#define TIMG_INT_ST_TIMERS_REG (DR_REG_TIMG_BASE + 0xa0) + +/* TIMG_LACT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the TIMG_LACT_INT interrupt. + */ + +#define TIMG_LACT_INT_ST (BIT(3)) +#define TIMG_LACT_INT_ST_M (TIMG_LACT_INT_ST_V << TIMG_LACT_INT_ST_S) +#define TIMG_LACT_INT_ST_V 0x00000001 +#define TIMG_LACT_INT_ST_S 3 + +/* TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for the TIMG_WDT_INT interrupt. + */ + +#define TIMG_WDT_INT_ST (BIT(2)) +#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S) +#define TIMG_WDT_INT_ST_V 0x00000001 +#define TIMG_WDT_INT_ST_S 2 + +/* TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for the TIMG_T1_INT interrupt. + */ + +#define TIMG_T1_INT_ST (BIT(1)) +#define TIMG_T1_INT_ST_M (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S) +#define TIMG_T1_INT_ST_V 0x00000001 +#define TIMG_T1_INT_ST_S 1 + +/* TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for the TIMG_T0_INT interrupt. + */ + +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S) +#define TIMG_T0_INT_ST_V 0x00000001 +#define TIMG_T0_INT_ST_S 0 + +/* TIMG_INT_CLR_TIMERS_REG register + * Interrupt clear bits + */ + +#define TIMG_INT_CLR_TIMERS_REG (DR_REG_TIMG_BASE + 0xa4) + +/* TIMG_LACT_INT_CLR : WO; bitpos: [3]; default: 0; + * Set this bit to clear the TIMG_LACT_INT interrupt. + */ + +#define TIMG_LACT_INT_CLR (BIT(3)) +#define TIMG_LACT_INT_CLR_M (TIMG_LACT_INT_CLR_V << TIMG_LACT_INT_CLR_S) +#define TIMG_LACT_INT_CLR_V 0x00000001 +#define TIMG_LACT_INT_CLR_S 3 + +/* TIMG_WDT_INT_CLR : WO; bitpos: [2]; default: 0; + * Set this bit to clear the TIMG_WDT_INT interrupt. + */ + +#define TIMG_WDT_INT_CLR (BIT(2)) +#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S) +#define TIMG_WDT_INT_CLR_V 0x00000001 +#define TIMG_WDT_INT_CLR_S 2 + +/* TIMG_T1_INT_CLR : WO; bitpos: [1]; default: 0; + * Set this bit to clear the TIMG_T1_INT interrupt. + */ + +#define TIMG_T1_INT_CLR (BIT(1)) +#define TIMG_T1_INT_CLR_M (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S) +#define TIMG_T1_INT_CLR_V 0x00000001 +#define TIMG_T1_INT_CLR_S 1 + +/* TIMG_T0_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to clear the TIMG_T0_INT interrupt. + */ + +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S) +#define TIMG_T0_INT_CLR_V 0x00000001 +#define TIMG_T0_INT_CLR_S 0 + +/* TIMG_RTCCALICFG2_REG register + * Timer group calibration register + */ + +#define TIMG_RTCCALICFG2_REG (DR_REG_TIMG_BASE + 0xa8) + +/* TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431; + * Threshold value for the RTC calibration timer. If the calibration timer's + * value exceeds this threshold, a timeout is triggered. + */ + +#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFF +#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S) +#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFF +#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 + +/* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3; + * Cycles that release calibration timeout reset + */ + +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000F +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S) +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000F +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 + +/* TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0; + * RTC calibration timeout indicator + */ + +#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S) +#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001 +#define TIMG_RTC_CALI_TIMEOUT_S 0 + +/* TIMG_TIMERS_DATE_REG register + * Version control register + */ + +#define TIMG_TIMERS_DATE_REG (DR_REG_TIMG_BASE + 0xf8) + +/* TIMG_TIMERS_DATE : R/W; bitpos: [27:0]; default: 26243681; + * Version control register. + */ + +#define TIMG_TIMERS_DATE 0x0FFFFFFF +#define TIMG_TIMERS_DATE_M (TIMG_TIMERS_DATE_V << TIMG_TIMERS_DATE_S) +#define TIMG_TIMERS_DATE_V 0x0FFFFFFF +#define TIMG_TIMERS_DATE_S 0 + +/* TIMG_REGCLK_REG register + * Timer group clock gate register + */ + +#define TIMG_REGCLK_REG (DR_REG_TIMG_BASE + 0xfc) + +/* TIMG_CLK_EN : R/W; bitpos: [31]; default: 0; + * Register clock gate signal. 1: Registers can be read and written to by + * software. 0: Registers can not be read or written to by software. + */ + +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S) +#define TIMG_CLK_EN_V 0x00000001 +#define TIMG_CLK_EN_S 31 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_TIMG_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_uart.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_uart.h new file mode 100644 index 0000000000..c9e5a01ffb --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_uart.h @@ -0,0 +1,1846 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_uart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_UART_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* UART_FIFO_REG register + * FIFO data register + */ + +#define UART_FIFO_REG(i) (REG_UART_AHB_BASE(i) + 0x0) + +/* UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; + * This register stores one byte data read from RX FIFO. + */ + +#define UART_RXFIFO_RD_BYTE 0x000000FF +#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) +#define UART_RXFIFO_RD_BYTE_V 0x000000FF +#define UART_RXFIFO_RD_BYTE_S 0 + +/* UART_INT_RAW_REG register + * Raw interrupt status + */ + +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) + +/* UART_WAKEUP_INT_RAW : RO; bitpos: [19]; default: 0; + * This interrupt raw bit turns to high level when input rxd edge changes + * more times than what UART_ACTIVE_THRESHOLD specifies in Light-sleep mode. + */ + +#define UART_WAKEUP_INT_RAW (BIT(19)) +#define UART_WAKEUP_INT_RAW_M (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S) +#define UART_WAKEUP_INT_RAW_V 0x00000001 +#define UART_WAKEUP_INT_RAW_S 19 + +/* UART_AT_CMD_CHAR_DET_INT_RAW : RO; bitpos: [18]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the + * configured UART_AT_CMD CHAR. + */ + +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001 +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 + +/* UART_RS485_CLASH_INT_RAW : RO; bitpos: [17]; default: 0; + * This interrupt raw bit turns to high level when detects a clash between + * transmitter and receiver in RS485 mode. + */ + +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S) +#define UART_RS485_CLASH_INT_RAW_V 0x00000001 +#define UART_RS485_CLASH_INT_RAW_S 17 + +/* UART_RS485_FRM_ERR_INT_RAW : RO; bitpos: [16]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data + * frame error from the echo of transmitter in RS485 mode. + */ + +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x00000001 +#define UART_RS485_FRM_ERR_INT_RAW_S 16 + +/* UART_RS485_PARITY_ERR_INT_RAW : RO; bitpos: [15]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity + * error from the echo of transmitter in RS485 mode. + */ + +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x00000001 +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 + +/* UART_TX_DONE_INT_RAW : RO; bitpos: [14]; default: 0; + * This interrupt raw bit turns to high level when transmitter has sent out + * all data in FIFO. + */ + +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S) +#define UART_TX_DONE_INT_RAW_V 0x00000001 +#define UART_TX_DONE_INT_RAW_S 14 + +/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO; bitpos: [13]; default: 0; + * This interrupt raw bit turns to high level when transmitter has kept the + * shortest duration after sending the last data. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001 +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 + +/* UART_TX_BRK_DONE_INT_RAW : RO; bitpos: [12]; default: 0; + * This interrupt raw bit turns to high level when transmitter completes + * sending NULL characters, after all data in TX FIFO are sent. + */ + +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S) +#define UART_TX_BRK_DONE_INT_RAW_V 0x00000001 +#define UART_TX_BRK_DONE_INT_RAW_S 12 + +/* UART_GLITCH_DET_INT_RAW : RO; bitpos: [11]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a glitch + * in the middle of a start bit. + */ + +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S) +#define UART_GLITCH_DET_INT_RAW_V 0x00000001 +#define UART_GLITCH_DET_INT_RAW_S 11 + +/* UART_SW_XOFF_INT_RAW : RO; bitpos: [10]; default: 0; + * This interrupt raw bit turns to high level when receiver receives XOFF + * character when UART_SW_FLOW_CON_EN is set to 1. + */ + +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S) +#define UART_SW_XOFF_INT_RAW_V 0x00000001 +#define UART_SW_XOFF_INT_RAW_S 10 + +/* UART_SW_XON_INT_RAW : RO; bitpos: [9]; default: 0; + * This interrupt raw bit turns to high level when receiver receives XON + * character when UART_SW_FLOW_CON_EN is set to 1. + */ + +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S) +#define UART_SW_XON_INT_RAW_V 0x00000001 +#define UART_SW_XON_INT_RAW_S 9 + +/* UART_RXFIFO_TOUT_INT_RAW : RO; bitpos: [8]; default: 0; + * This interrupt raw bit turns to high level when receiver takes more time + * than UART_RX_TOUT_THRHD to receive a byte. + */ + +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001 +#define UART_RXFIFO_TOUT_INT_RAW_S 8 + +/* UART_BRK_DET_INT_RAW : RO; bitpos: [7]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a 0 + * after the stop bit. + */ + +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S) +#define UART_BRK_DET_INT_RAW_V 0x00000001 +#define UART_BRK_DET_INT_RAW_S 7 + +/* UART_CTS_CHG_INT_RAW : RO; bitpos: [6]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge + * change of CTSn signal. + */ + +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S) +#define UART_CTS_CHG_INT_RAW_V 0x00000001 +#define UART_CTS_CHG_INT_RAW_S 6 + +/* UART_DSR_CHG_INT_RAW : RO; bitpos: [5]; default: 0; + * This interrupt raw bit turns to high level when receiver detects the edge + * change of DSRn signal. + */ + +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S) +#define UART_DSR_CHG_INT_RAW_V 0x00000001 +#define UART_DSR_CHG_INT_RAW_S 5 + +/* UART_RXFIFO_OVF_INT_RAW : RO; bitpos: [4]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more + * data than the FIFO can store. + */ + +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S) +#define UART_RXFIFO_OVF_INT_RAW_V 0x00000001 +#define UART_RXFIFO_OVF_INT_RAW_S 4 + +/* UART_FRM_ERR_INT_RAW : RO; bitpos: [3]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a data + * frame error. + */ + +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S) +#define UART_FRM_ERR_INT_RAW_V 0x00000001 +#define UART_FRM_ERR_INT_RAW_S 3 + +/* UART_PARITY_ERR_INT_RAW : RO; bitpos: [2]; default: 0; + * This interrupt raw bit turns to high level when receiver detects a parity + * error in the data. + */ + +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S) +#define UART_PARITY_ERR_INT_RAW_V 0x00000001 +#define UART_PARITY_ERR_INT_RAW_S 2 + +/* UART_TXFIFO_EMPTY_INT_RAW : RO; bitpos: [1]; default: 0; + * This interrupt raw bit turns to high level when the amount of data in TX + * FIFO is less than what UART_TXFIFO_EMPTY_THRHD specifies. + */ + +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001 +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 + +/* UART_RXFIFO_FULL_INT_RAW : RO; bitpos: [0]; default: 0; + * This interrupt raw bit turns to high level when receiver receives more + * data than what UART_RXFIFO_FULL_THRHD specifies. + */ + +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S) +#define UART_RXFIFO_FULL_INT_RAW_V 0x00000001 +#define UART_RXFIFO_FULL_INT_RAW_S 0 + +/* UART_INT_ST_REG register + * Masked interrupt status + */ + +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) + +/* UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; + * This is the status bit for UART_WAKEUP_INT_RAW when UART_WAKEUP_INT_ENA + * is set to 1. + */ + +#define UART_WAKEUP_INT_ST (BIT(19)) +#define UART_WAKEUP_INT_ST_M (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S) +#define UART_WAKEUP_INT_ST_V 0x00000001 +#define UART_WAKEUP_INT_ST_S 19 + +/* UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; + * This is the status bit for UART_AT_CMD_DET_INT_RAW when + * UART_AT_CMD_CHAR_DET_INT_ENA is set to 1. + */ + +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001 +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 + +/* UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0; + * This is the status bit for UART_RS485_CLASH_INT_RAW when + * UART_RS485_CLASH_INT_ENA is set to 1. + */ + +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S) +#define UART_RS485_CLASH_INT_ST_V 0x00000001 +#define UART_RS485_CLASH_INT_ST_S 17 + +/* UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * This is the status bit for UART_RS485_FRM_ERR_INT_RAW when + * UART_RS485_FM_ERR_INT_ENA is set to 1. + */ + +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S) +#define UART_RS485_FRM_ERR_INT_ST_V 0x00000001 +#define UART_RS485_FRM_ERR_INT_ST_S 16 + +/* UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * This is the status bit for UART_RS485_PARITY_ERR_INT_RAW when + * UART_RS485_PARITY_INT_ENA is set to 1. + */ + +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x00000001 +#define UART_RS485_PARITY_ERR_INT_ST_S 15 + +/* UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * This is the status bit for UART_TX_DONE_INT_RAW when UART_TX_DONE_INT_ENA + * is set to 1. + */ + +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S) +#define UART_TX_DONE_INT_ST_V 0x00000001 +#define UART_TX_DONE_INT_ST_S 14 + +/* UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * This is the status bit for UART_TX_BRK_IDLE_DONE_INT_RAW when + * UART_TX_BRK_IDLE_DONE_INT_ENA is set to 1. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001 +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 + +/* UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * This is the status bit for UART_TX_BRK_DONE_INT_RAW when + * UART_TX_BRK_DONE_INT_ENA is set to 1. + */ + +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S) +#define UART_TX_BRK_DONE_INT_ST_V 0x00000001 +#define UART_TX_BRK_DONE_INT_ST_S 12 + +/* UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; + * This is the status bit for UART_GLITCH_DET_INT_RAW when + * UART_GLITCH_DET_INT_ENA is set to 1. + */ + +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S) +#define UART_GLITCH_DET_INT_ST_V 0x00000001 +#define UART_GLITCH_DET_INT_ST_S 11 + +/* UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; + * This is the status bit for UART_SW_XOFF_INT_RAW when UART_SW_XOFF_INT_ENA + * is set to 1. + */ + +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S) +#define UART_SW_XOFF_INT_ST_V 0x00000001 +#define UART_SW_XOFF_INT_ST_S 10 + +/* UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; + * This is the status bit for UART_SW_XON_INT_RAW when UART_SW_XON_INT_ENA + * is set to 1. + */ + +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S) +#define UART_SW_XON_INT_ST_V 0x00000001 +#define UART_SW_XON_INT_ST_S 9 + +/* UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; + * This is the status bit for UART_RXFIFO_TOUT_INT_RAW when + * UART_RXFIFO_TOUT_INT_ENA is set to 1. + */ + +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S) +#define UART_RXFIFO_TOUT_INT_ST_V 0x00000001 +#define UART_RXFIFO_TOUT_INT_ST_S 8 + +/* UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; + * This is the status bit for UART_BRK_DET_INT_RAW when UART_BRK_DET_INT_ENA + * is set to 1. + */ + +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S) +#define UART_BRK_DET_INT_ST_V 0x00000001 +#define UART_BRK_DET_INT_ST_S 7 + +/* UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; + * This is the status bit for UART_CTS_CHG_INT_RAW when UART_CTS_CHG_INT_ENA + * is set to 1. + */ + +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S) +#define UART_CTS_CHG_INT_ST_V 0x00000001 +#define UART_CTS_CHG_INT_ST_S 6 + +/* UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; + * This is the status bit for UART_DSR_CHG_INT_RAW when UART_DSR_CHG_INT_ENA + * is set to 1. + */ + +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S) +#define UART_DSR_CHG_INT_ST_V 0x00000001 +#define UART_DSR_CHG_INT_ST_S 5 + +/* UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; + * This is the status bit for UART_RXFIFO_OVF_INT_RAW when + * UART_RXFIFO_OVF_INT_ENA is set to 1. + */ + +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S) +#define UART_RXFIFO_OVF_INT_ST_V 0x00000001 +#define UART_RXFIFO_OVF_INT_ST_S 4 + +/* UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; + * This is the status bit for UART_FRM_ERR_INT_RAW when UART_FRM_ERR_INT_ENA + * is set to 1. + */ + +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S) +#define UART_FRM_ERR_INT_ST_V 0x00000001 +#define UART_FRM_ERR_INT_ST_S 3 + +/* UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; + * This is the status bit for UART_PARITY_ERR_INT_RAW when + * UART_PARITY_ERR_INT_ENA is set to 1. + */ + +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S) +#define UART_PARITY_ERR_INT_ST_V 0x00000001 +#define UART_PARITY_ERR_INT_ST_S 2 + +/* UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; + * This is the status bit for UART_TXFIFO_EMPTY_INT_RAW when + * UART_TXFIFO_EMPTY_INT_ENA is set to 1. + */ + +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x00000001 +#define UART_TXFIFO_EMPTY_INT_ST_S 1 + +/* UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; + * This is the status bit for UART_RXFIFO_FULL_INT_RAW when + * UART_RXFIFO_FULL_INT_ENA is set to 1. + */ + +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S) +#define UART_RXFIFO_FULL_INT_ST_V 0x00000001 +#define UART_RXFIFO_FULL_INT_ST_S 0 + +/* UART_INT_ENA_REG register + * Interrupt enable bits + */ + +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc) + +/* UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; + * This is the enable bit for UART_WAKEUP_INT_ST register. + */ + +#define UART_WAKEUP_INT_ENA (BIT(19)) +#define UART_WAKEUP_INT_ENA_M (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S) +#define UART_WAKEUP_INT_ENA_V 0x00000001 +#define UART_WAKEUP_INT_ENA_S 19 + +/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; + * This is the enable bit for UART_AT_CMD_CHAR_DET_INT_ST register. + */ + +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001 +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 + +/* UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0; + * This is the enable bit for UART_RS485_CLASH_INT_ST register. + */ + +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S) +#define UART_RS485_CLASH_INT_ENA_V 0x00000001 +#define UART_RS485_CLASH_INT_ENA_S 17 + +/* UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * This is the enable bit for UART_RS485_PARITY_ERR_INT_ST register. + */ + +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x00000001 +#define UART_RS485_FRM_ERR_INT_ENA_S 16 + +/* UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * This is the enable bit for UART_RS485_PARITY_ERR_INT_ST register. + */ + +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x00000001 +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 + +/* UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * This is the enable bit for UART_TX_DONE_INT_ST register. + */ + +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S) +#define UART_TX_DONE_INT_ENA_V 0x00000001 +#define UART_TX_DONE_INT_ENA_S 14 + +/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * This is the enable bit for UART_TX_BRK_IDLE_DONE_INT_ST register. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001 +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 + +/* UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * This is the enable bit for UART_TX_BRK_DONE_INT_ST register. + */ + +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S) +#define UART_TX_BRK_DONE_INT_ENA_V 0x00000001 +#define UART_TX_BRK_DONE_INT_ENA_S 12 + +/* UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; + * This is the enable bit for UART_GLITCH_DET_INT_ST register. + */ + +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S) +#define UART_GLITCH_DET_INT_ENA_V 0x00000001 +#define UART_GLITCH_DET_INT_ENA_S 11 + +/* UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; + * This is the enable bit for UART_SW_XOFF_INT_ST register. + */ + +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S) +#define UART_SW_XOFF_INT_ENA_V 0x00000001 +#define UART_SW_XOFF_INT_ENA_S 10 + +/* UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; + * This is the enable bit for UART_SW_XON_INT_ST register. + */ + +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S) +#define UART_SW_XON_INT_ENA_V 0x00000001 +#define UART_SW_XON_INT_ENA_S 9 + +/* UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * This is the enable bit for UART_RXFIFO_TOUT_INT_ST register. + */ + +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x00000001 +#define UART_RXFIFO_TOUT_INT_ENA_S 8 + +/* UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; + * This is the enable bit for UART_BRK_DET_INT_ST register. + */ + +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S) +#define UART_BRK_DET_INT_ENA_V 0x00000001 +#define UART_BRK_DET_INT_ENA_S 7 + +/* UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; + * This is the enable bit for UART_CTS_CHG_INT_ST register. + */ + +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S) +#define UART_CTS_CHG_INT_ENA_V 0x00000001 +#define UART_CTS_CHG_INT_ENA_S 6 + +/* UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; + * This is the enable bit for UART_DSR_CHG_INT_ST register. + */ + +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S) +#define UART_DSR_CHG_INT_ENA_V 0x00000001 +#define UART_DSR_CHG_INT_ENA_S 5 + +/* UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; + * This is the enable bit for UART_RXFIFO_OVF_INT_ST register. + */ + +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S) +#define UART_RXFIFO_OVF_INT_ENA_V 0x00000001 +#define UART_RXFIFO_OVF_INT_ENA_S 4 + +/* UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; + * This is the enable bit for UART_FRM_ERR_INT_ST register. + */ + +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S) +#define UART_FRM_ERR_INT_ENA_V 0x00000001 +#define UART_FRM_ERR_INT_ENA_S 3 + +/* UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; + * This is the enable bit for UART_PARITY_ERR_INT_ST register. + */ + +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S) +#define UART_PARITY_ERR_INT_ENA_V 0x00000001 +#define UART_PARITY_ERR_INT_ENA_S 2 + +/* UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; + * This is the enable bit for UART_TXFIFO_EMPTY_INT_ST register. + */ + +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001 +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 + +/* UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; + * This is the enable bit for UART_RXFIFO_FULL_INT_ST register. + */ + +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S) +#define UART_RXFIFO_FULL_INT_ENA_V 0x00000001 +#define UART_RXFIFO_FULL_INT_ENA_S 0 + +/* UART_INT_CLR_REG register + * Interrupt clear bits + */ + +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) + +/* UART_WAKEUP_INT_CLR : WO; bitpos: [19]; default: 0; + * Set this bit to clear UART_WAKEUP_INT_RAW interrupt. + */ + +#define UART_WAKEUP_INT_CLR (BIT(19)) +#define UART_WAKEUP_INT_CLR_M (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S) +#define UART_WAKEUP_INT_CLR_V 0x00000001 +#define UART_WAKEUP_INT_CLR_S 19 + +/* UART_AT_CMD_CHAR_DET_INT_CLR : WO; bitpos: [18]; default: 0; + * Set this bit to clear UART_AT_CMD_CHAR_DET_INT_RAW interrupt. + */ + +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001 +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 + +/* UART_RS485_CLASH_INT_CLR : WO; bitpos: [17]; default: 0; + * Set this bit to clear UART_RS485_CLASH_INT_RAW interrupt. + */ + +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S) +#define UART_RS485_CLASH_INT_CLR_V 0x00000001 +#define UART_RS485_CLASH_INT_CLR_S 17 + +/* UART_RS485_FRM_ERR_INT_CLR : WO; bitpos: [16]; default: 0; + * Set this bit to clear UART_RS485_FRM_ERR_INT_RAW interrupt. + */ + +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x00000001 +#define UART_RS485_FRM_ERR_INT_CLR_S 16 + +/* UART_RS485_PARITY_ERR_INT_CLR : WO; bitpos: [15]; default: 0; + * Set this bit to clear UART_RS485_PARITY_ERR_INT_RAW interrupt. + */ + +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x00000001 +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 + +/* UART_TX_DONE_INT_CLR : WO; bitpos: [14]; default: 0; + * Set this bit to clear UART_TX_DONE_INT_RAW interrupt. + */ + +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S) +#define UART_TX_DONE_INT_CLR_V 0x00000001 +#define UART_TX_DONE_INT_CLR_S 14 + +/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO; bitpos: [13]; default: 0; + * Set this bit to clear UART_TX_BRK_IDLE_DONE_INT_RAW interrupt. + */ + +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001 +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 + +/* UART_TX_BRK_DONE_INT_CLR : WO; bitpos: [12]; default: 0; + * Set this bit to clear UART_TX_BRK_DONE_INT_RAW interrupt. + */ + +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S) +#define UART_TX_BRK_DONE_INT_CLR_V 0x00000001 +#define UART_TX_BRK_DONE_INT_CLR_S 12 + +/* UART_GLITCH_DET_INT_CLR : WO; bitpos: [11]; default: 0; + * Set this bit to clear UART_GLITCH_DET_INT_RAW interrupt. + */ + +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S) +#define UART_GLITCH_DET_INT_CLR_V 0x00000001 +#define UART_GLITCH_DET_INT_CLR_S 11 + +/* UART_SW_XOFF_INT_CLR : WO; bitpos: [10]; default: 0; + * Set this bit to clear UART_SW_XOFF_INT_RAW interrupt. + */ + +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S) +#define UART_SW_XOFF_INT_CLR_V 0x00000001 +#define UART_SW_XOFF_INT_CLR_S 10 + +/* UART_SW_XON_INT_CLR : WO; bitpos: [9]; default: 0; + * Set this bit to clear UART_SW_XON_INT_RAW interrupt. + */ + +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S) +#define UART_SW_XON_INT_CLR_V 0x00000001 +#define UART_SW_XON_INT_CLR_S 9 + +/* UART_RXFIFO_TOUT_INT_CLR : WO; bitpos: [8]; default: 0; + * Set this bit to clear UART_RXFIFO_TOUT_INT_RAW interrupt. + */ + +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x00000001 +#define UART_RXFIFO_TOUT_INT_CLR_S 8 + +/* UART_BRK_DET_INT_CLR : WO; bitpos: [7]; default: 0; + * Set this bit to clear UART_BRK_DET_INT_RAW interrupt. + */ + +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S) +#define UART_BRK_DET_INT_CLR_V 0x00000001 +#define UART_BRK_DET_INT_CLR_S 7 + +/* UART_CTS_CHG_INT_CLR : WO; bitpos: [6]; default: 0; + * Set this bit to clear UART_CTS_CHG_INT_RAW interrupt. + */ + +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S) +#define UART_CTS_CHG_INT_CLR_V 0x00000001 +#define UART_CTS_CHG_INT_CLR_S 6 + +/* UART_DSR_CHG_INT_CLR : WO; bitpos: [5]; default: 0; + * Set this bit to clear UART_DSR_CHG_INT_RAW interrupt. + */ + +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S) +#define UART_DSR_CHG_INT_CLR_V 0x00000001 +#define UART_DSR_CHG_INT_CLR_S 5 + +/* UART_RXFIFO_OVF_INT_CLR : WO; bitpos: [4]; default: 0; + * Set this bit to clear UART_UART_RXFIFO_OVF_INT_RAW interrupt. + */ + +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S) +#define UART_RXFIFO_OVF_INT_CLR_V 0x00000001 +#define UART_RXFIFO_OVF_INT_CLR_S 4 + +/* UART_FRM_ERR_INT_CLR : WO; bitpos: [3]; default: 0; + * Set this bit to clear UART_FRM_ERR_INT_RAW interrupt. + */ + +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S) +#define UART_FRM_ERR_INT_CLR_V 0x00000001 +#define UART_FRM_ERR_INT_CLR_S 3 + +/* UART_PARITY_ERR_INT_CLR : WO; bitpos: [2]; default: 0; + * Set this bit to clear UART_PARITY_ERR_INT_RAW interrupt. + */ + +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S) +#define UART_PARITY_ERR_INT_CLR_V 0x00000001 +#define UART_PARITY_ERR_INT_CLR_S 2 + +/* UART_TXFIFO_EMPTY_INT_CLR : WO; bitpos: [1]; default: 0; + * Set this bit to clear UART_TXFIFO_EMPTY_INT_RAW interrupt. + */ + +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001 +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 + +/* UART_RXFIFO_FULL_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to clear UART_THE RXFIFO_FULL_INT_RAW interrupt. + */ + +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S) +#define UART_RXFIFO_FULL_INT_CLR_V 0x00000001 +#define UART_RXFIFO_FULL_INT_CLR_S 0 + +/* UART_CLKDIV_REG register + * Clock divider configuration + */ + +#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) + +/* UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; + * The decimal part of the frequency divisor. + */ + +#define UART_CLKDIV_FRAG 0x0000000F +#define UART_CLKDIV_FRAG_M (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S) +#define UART_CLKDIV_FRAG_V 0x0000000F +#define UART_CLKDIV_FRAG_S 20 + +/* UART_CLKDIV : R/W; bitpos: [19:0]; default: 694; + * The integral part of the frequency divisor. + */ + +#define UART_CLKDIV 0x000FFFFF +#define UART_CLKDIV_M (UART_CLKDIV_V << UART_CLKDIV_S) +#define UART_CLKDIV_V 0x000FFFFF +#define UART_CLKDIV_S 0 + +/* UART_AUTOBAUD_REG register + * Autobaud configuration register + */ + +#define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18) + +/* UART_GLITCH_FILT : R/W; bitpos: [15:8]; default: 16; + * when input pulse width is lower than this value, the pulse is ignored. + * This register is used in autobaud detect process. + */ + +#define UART_GLITCH_FILT 0x000000FF +#define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S) +#define UART_GLITCH_FILT_V 0x000000FF +#define UART_GLITCH_FILT_S 8 + +/* UART_AUTOBAUD_EN : R/W; bitpos: [0]; default: 0; + * This is the enable bit for detecting baudrate. + */ + +#define UART_AUTOBAUD_EN (BIT(0)) +#define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S) +#define UART_AUTOBAUD_EN_V 0x00000001 +#define UART_AUTOBAUD_EN_S 0 + +/* UART_STATUS_REG register + * UART status register + */ + +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c) + +/* UART_TXD : RO; bitpos: [31]; default: 0; + * This bit represents the level of the internal UART TXD signal. + */ + +#define UART_TXD (BIT(31)) +#define UART_TXD_M (UART_TXD_V << UART_TXD_S) +#define UART_TXD_V 0x00000001 +#define UART_TXD_S 31 + +/* UART_RTSN : RO; bitpos: [30]; default: 0; + * This bit represents the level of the internal UART RTS signal. + */ + +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (UART_RTSN_V << UART_RTSN_S) +#define UART_RTSN_V 0x00000001 +#define UART_RTSN_S 30 + +/* UART_DTRN : RO; bitpos: [29]; default: 0; + * This bit represents the level of the internal UART DTR signal. + */ + +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (UART_DTRN_V << UART_DTRN_S) +#define UART_DTRN_V 0x00000001 +#define UART_DTRN_S 29 + +/* UART_TXFIFO_CNT : RO; bitpos: [25:16]; default: 0; + * Stores the byte number of data in TX FIFO. + */ + +#define UART_TXFIFO_CNT 0x000003FF +#define UART_TXFIFO_CNT_M (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S) +#define UART_TXFIFO_CNT_V 0x000003FF +#define UART_TXFIFO_CNT_S 16 + +/* UART_RXD : RO; bitpos: [15]; default: 0; + * This register represent the level value of the internal UART RXD signal. + */ + +#define UART_RXD (BIT(15)) +#define UART_RXD_M (UART_RXD_V << UART_RXD_S) +#define UART_RXD_V 0x00000001 +#define UART_RXD_S 15 + +/* UART_CTSN : RO; bitpos: [14]; default: 0; + * This register represent the level value of the internal UART CTS signal. + */ + +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (UART_CTSN_V << UART_CTSN_S) +#define UART_CTSN_V 0x00000001 +#define UART_CTSN_S 14 + +/* UART_DSRN : RO; bitpos: [13]; default: 0; + * The register represent the level value of the internal UART DSR signal. + */ + +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (UART_DSRN_V << UART_DSRN_S) +#define UART_DSRN_V 0x00000001 +#define UART_DSRN_S 13 + +/* UART_RXFIFO_CNT : RO; bitpos: [9:0]; default: 0; + * Stores the byte number of valid data in RX FIFO. + */ + +#define UART_RXFIFO_CNT 0x000003FF +#define UART_RXFIFO_CNT_M (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S) +#define UART_RXFIFO_CNT_V 0x000003FF +#define UART_RXFIFO_CNT_S 0 + +/* UART_CONF0_REG register + * Configuration register 0 + */ + +#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) + +/* UART_MEM_CLK_EN : R/W; bitpos: [28]; default: 1; + * UART memory clock gate enable signal. + * 1: UART memory powers on, the data of which can be read and written. + * 0: UART memory powers down. + */ + +#define UART_MEM_CLK_EN (BIT(28)) +#define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S) +#define UART_MEM_CLK_EN_V 0x00000001 +#define UART_MEM_CLK_EN_S 28 + +/* UART_TICK_REF_ALWAYS_ON : R/W; bitpos: [27]; default: 1; + * This register is used to select the clock. + * 1'h1: APB_CLK. + * 1'h0: REF_TICK. + */ + +#define UART_TICK_REF_ALWAYS_ON (BIT(27)) +#define UART_TICK_REF_ALWAYS_ON_M (UART_TICK_REF_ALWAYS_ON_V << UART_TICK_REF_ALWAYS_ON_S) +#define UART_TICK_REF_ALWAYS_ON_V 0x00000001 +#define UART_TICK_REF_ALWAYS_ON_S 27 + +/* UART_ERR_WR_MASK : R/W; bitpos: [26]; default: 0; + * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: + * Receiver stores the data even if the received data is wrong. + */ + +#define UART_ERR_WR_MASK (BIT(26)) +#define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S) +#define UART_ERR_WR_MASK_V 0x00000001 +#define UART_ERR_WR_MASK_S 26 + +/* UART_CLK_EN : R/W; bitpos: [25]; default: 0; + * 1'h1: Force clock on for register. 1'h0: Support clock only when + * application writes registers. + */ + +#define UART_CLK_EN (BIT(25)) +#define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S) +#define UART_CLK_EN_V 0x00000001 +#define UART_CLK_EN_S 25 + +/* UART_DTR_INV : R/W; bitpos: [24]; default: 0; + * Set this bit to inverse the level value of UART DTR signal. + */ + +#define UART_DTR_INV (BIT(24)) +#define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S) +#define UART_DTR_INV_V 0x00000001 +#define UART_DTR_INV_S 24 + +/* UART_RTS_INV : R/W; bitpos: [23]; default: 0; + * Set this bit to inverse the level value of UART RTS signal. + */ + +#define UART_RTS_INV (BIT(23)) +#define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S) +#define UART_RTS_INV_V 0x00000001 +#define UART_RTS_INV_S 23 + +/* UART_TXD_INV : R/W; bitpos: [22]; default: 0; + * Set this bit to inverse the level value of UART TXD signal. + */ + +#define UART_TXD_INV (BIT(22)) +#define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S) +#define UART_TXD_INV_V 0x00000001 +#define UART_TXD_INV_S 22 + +/* UART_DSR_INV : R/W; bitpos: [21]; default: 0; + * Set this bit to inverse the level value of UART DSR signal. + */ + +#define UART_DSR_INV (BIT(21)) +#define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S) +#define UART_DSR_INV_V 0x00000001 +#define UART_DSR_INV_S 21 + +/* UART_CTS_INV : R/W; bitpos: [20]; default: 0; + * Set this bit to inverse the level value of UART CTS signal. + */ + +#define UART_CTS_INV (BIT(20)) +#define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S) +#define UART_CTS_INV_V 0x00000001 +#define UART_CTS_INV_S 20 + +/* UART_RXD_INV : R/W; bitpos: [19]; default: 0; + * Set this bit to inverse the level value of UART RXD signal. + */ + +#define UART_RXD_INV (BIT(19)) +#define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S) +#define UART_RXD_INV_V 0x00000001 +#define UART_RXD_INV_S 19 + +/* UART_TXFIFO_RST : R/W; bitpos: [18]; default: 0; + * Set this bit to reset the UART TX FIFO. + */ + +#define UART_TXFIFO_RST (BIT(18)) +#define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S) +#define UART_TXFIFO_RST_V 0x00000001 +#define UART_TXFIFO_RST_S 18 + +/* UART_RXFIFO_RST : R/W; bitpos: [17]; default: 0; + * Set this bit to reset the UART RX FIFO. + */ + +#define UART_RXFIFO_RST (BIT(17)) +#define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S) +#define UART_RXFIFO_RST_V 0x00000001 +#define UART_RXFIFO_RST_S 17 + +/* UART_IRDA_EN : R/W; bitpos: [16]; default: 0; + * Set this bit to enable IrDA protocol. + */ + +#define UART_IRDA_EN (BIT(16)) +#define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S) +#define UART_IRDA_EN_V 0x00000001 +#define UART_IRDA_EN_S 16 + +/* UART_TX_FLOW_EN : R/W; bitpos: [15]; default: 0; + * Set this bit to enable flow control function for transmitter. + */ + +#define UART_TX_FLOW_EN (BIT(15)) +#define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S) +#define UART_TX_FLOW_EN_V 0x00000001 +#define UART_TX_FLOW_EN_S 15 + +/* UART_LOOPBACK : R/W; bitpos: [14]; default: 0; + * Set this bit to enable UART loopback test mode. + */ + +#define UART_LOOPBACK (BIT(14)) +#define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S) +#define UART_LOOPBACK_V 0x00000001 +#define UART_LOOPBACK_S 14 + +/* UART_IRDA_RX_INV : R/W; bitpos: [13]; default: 0; + * Set this bit to invert the level of IrDA receiver. + */ + +#define UART_IRDA_RX_INV (BIT(13)) +#define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S) +#define UART_IRDA_RX_INV_V 0x00000001 +#define UART_IRDA_RX_INV_S 13 + +/* UART_IRDA_TX_INV : R/W; bitpos: [12]; default: 0; + * Set this bit to invert the level of IrDA transmitter. + */ + +#define UART_IRDA_TX_INV (BIT(12)) +#define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S) +#define UART_IRDA_TX_INV_V 0x00000001 +#define UART_IRDA_TX_INV_S 12 + +/* UART_IRDA_WCTL : R/W; bitpos: [11]; default: 0; + * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set + * IrDA transmitter's 11th bit to 0. + */ + +#define UART_IRDA_WCTL (BIT(11)) +#define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S) +#define UART_IRDA_WCTL_V 0x00000001 +#define UART_IRDA_WCTL_S 11 + +/* UART_IRDA_TX_EN : R/W; bitpos: [10]; default: 0; + * This is the start enable bit for IrDA transmitter. + */ + +#define UART_IRDA_TX_EN (BIT(10)) +#define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S) +#define UART_IRDA_TX_EN_V 0x00000001 +#define UART_IRDA_TX_EN_S 10 + +/* UART_IRDA_DPLX : R/W; bitpos: [9]; default: 0; + * Set this bit to enable IrDA loopback mode. + */ + +#define UART_IRDA_DPLX (BIT(9)) +#define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S) +#define UART_IRDA_DPLX_V 0x00000001 +#define UART_IRDA_DPLX_S 9 + +/* UART_TXD_BRK : R/W; bitpos: [8]; default: 0; + * Set this bit to enable transmitter to send NULL when the process of + * sending data is done. + */ + +#define UART_TXD_BRK (BIT(8)) +#define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S) +#define UART_TXD_BRK_V 0x00000001 +#define UART_TXD_BRK_S 8 + +/* UART_SW_DTR : R/W; bitpos: [7]; default: 0; + * This register is used to configure the software DTR signal which is used + * in software flow control. + */ + +#define UART_SW_DTR (BIT(7)) +#define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S) +#define UART_SW_DTR_V 0x00000001 +#define UART_SW_DTR_S 7 + +/* UART_SW_RTS : R/W; bitpos: [6]; default: 0; + * This register is used to configure the software RTS signal which is used + * in software flow control. + */ + +#define UART_SW_RTS (BIT(6)) +#define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S) +#define UART_SW_RTS_V 0x00000001 +#define UART_SW_RTS_S 6 + +/* UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; + * This register is used to set the length of stop bit. + * 1: 1 bit 2: 1.5 bits 3: 2 bits. + */ + +#define UART_STOP_BIT_NUM 0x00000003 +#define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S) +#define UART_STOP_BIT_NUM_V 0x00000003 +#define UART_STOP_BIT_NUM_S 4 + +/* UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; + * This register is used to set the length of data. + * 0: 5 bits 1: 6 bits 2: 7 bits 3: 8 bits. + */ + +#define UART_BIT_NUM 0x00000003 +#define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S) +#define UART_BIT_NUM_V 0x00000003 +#define UART_BIT_NUM_S 2 + +/* UART_PARITY_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to enable UART parity check. + */ + +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S) +#define UART_PARITY_EN_V 0x00000001 +#define UART_PARITY_EN_S 1 + +/* UART_PARITY : R/W; bitpos: [0]; default: 0; + * This register is used to configure the parity check mode. + * 1'h0: even. 1'h1: odd. + */ + +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S) +#define UART_PARITY_V 0x00000001 +#define UART_PARITY_S 0 + +/* UART_CONF1_REG register + * Configuration register 1 + */ + +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) + +/* UART_RX_TOUT_EN : R/W; bitpos: [31]; default: 0; + * This is the enable bit for UART receiver's timeout function. + */ + +#define UART_RX_TOUT_EN (BIT(31)) +#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) +#define UART_RX_TOUT_EN_V 0x00000001 +#define UART_RX_TOUT_EN_S 31 + +/* UART_RX_FLOW_EN : R/W; bitpos: [30]; default: 0; + * This is the flow enable bit for UART receiver. + * 1'h1: Choose software flow control with configuring sw_rts signal. 1'h0: + * Disable software flow control. + */ + +#define UART_RX_FLOW_EN (BIT(30)) +#define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S) +#define UART_RX_FLOW_EN_V 0x00000001 +#define UART_RX_FLOW_EN_S 30 + +/* UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [29]; default: 0; + * Set this bit to stop accumulating idle_cnt when hardware flow control + * works. + */ + +#define UART_RX_TOUT_FLOW_DIS (BIT(29)) +#define UART_RX_TOUT_FLOW_DIS_M (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S) +#define UART_RX_TOUT_FLOW_DIS_V 0x00000001 +#define UART_RX_TOUT_FLOW_DIS_S 29 + +/* UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [17:9]; default: 96; + * It will produce UART_TXFIFO_EMPTY_INT interrupt when the data amount in + * TX FIFO is less than this register value. + */ + +#define UART_TXFIFO_EMPTY_THRHD 0x000001FF +#define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S) +#define UART_TXFIFO_EMPTY_THRHD_V 0x000001FF +#define UART_TXFIFO_EMPTY_THRHD_S 9 + +/* UART_RXFIFO_FULL_THRHD : R/W; bitpos: [8:0]; default: 96; + * It will produce UART_RXFIFO_FULL_INT interrupt when receiver receives + * more data than this register value. + */ + +#define UART_RXFIFO_FULL_THRHD 0x000001FF +#define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S) +#define UART_RXFIFO_FULL_THRHD_V 0x000001FF +#define UART_RXFIFO_FULL_THRHD_S 0 + +/* UART_LOWPULSE_REG register + * Autobaud minimum low pulse duration register + */ + +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) + +/* UART_LOWPULSE_MIN_CNT : RO; bitpos: [19:0]; default: 1048575; + * This register stores the value of the minimum duration time of the low + * level pulse. It is used in baud rate detection. + */ + +#define UART_LOWPULSE_MIN_CNT 0x000FFFFF +#define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S) +#define UART_LOWPULSE_MIN_CNT_V 0x000FFFFF +#define UART_LOWPULSE_MIN_CNT_S 0 + +/* UART_HIGHPULSE_REG register + * Autobaud minimum high pulse duration register + */ + +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2c) + +/* UART_HIGHPULSE_MIN_CNT : RO; bitpos: [19:0]; default: 1048575; + * This register stores the value of the maximum duration time for the high + * level pulse. It is used in baud rate detection. + */ + +#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF +#define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S) +#define UART_HIGHPULSE_MIN_CNT_V 0x000FFFFF +#define UART_HIGHPULSE_MIN_CNT_S 0 + +/* UART_RXD_CNT_REG register + * Autobaud edge change count register + */ + +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) + +/* UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; + * This register stores the count of rxd edge change. It is used in baud + * rate detection. + */ + +#define UART_RXD_EDGE_CNT 0x000003FF +#define UART_RXD_EDGE_CNT_M (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S) +#define UART_RXD_EDGE_CNT_V 0x000003FF +#define UART_RXD_EDGE_CNT_S 0 + +/* UART_FLOW_CONF_REG register + * Software flow control configuration + */ + +#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) + +/* UART_SEND_XOFF : R/W; bitpos: [5]; default: 0; + * Set this bit to send XOFF character. It is cleared by hardware + * automatically. + */ + +#define UART_SEND_XOFF (BIT(5)) +#define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S) +#define UART_SEND_XOFF_V 0x00000001 +#define UART_SEND_XOFF_S 5 + +/* UART_SEND_XON : R/W; bitpos: [4]; default: 0; + * Set this bit to send XON character. It is cleared by hardware + * automatically. + */ + +#define UART_SEND_XON (BIT(4)) +#define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S) +#define UART_SEND_XON_V 0x00000001 +#define UART_SEND_XON_S 4 + +/* UART_FORCE_XOFF : R/W; bitpos: [3]; default: 0; + * Set this bit to stop the transmitter from sending data. + */ + +#define UART_FORCE_XOFF (BIT(3)) +#define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S) +#define UART_FORCE_XOFF_V 0x00000001 +#define UART_FORCE_XOFF_S 3 + +/* UART_FORCE_XON : R/W; bitpos: [2]; default: 0; + * Set this bit to enable the transmitter to go on sending data. + */ + +#define UART_FORCE_XON (BIT(2)) +#define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S) +#define UART_FORCE_XON_V 0x00000001 +#define UART_FORCE_XON_S 2 + +/* UART_XONOFF_DEL : R/W; bitpos: [1]; default: 0; + * Set this bit to remove flow control character from the received data. + */ + +#define UART_XONOFF_DEL (BIT(1)) +#define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S) +#define UART_XONOFF_DEL_V 0x00000001 +#define UART_XONOFF_DEL_S 1 + +/* UART_SW_FLOW_CON_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to enable software flow control. It is used with register + * SW_XON or SW_XOFF. + */ + +#define UART_SW_FLOW_CON_EN (BIT(0)) +#define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S) +#define UART_SW_FLOW_CON_EN_V 0x00000001 +#define UART_SW_FLOW_CON_EN_S 0 + +/* UART_SLEEP_CONF_REG register + * Sleeping mode configuration + */ + +#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) + +/* UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; + * The UART is activated from light sleeping mode when the input rxd edge + * changes more times than this register value. + */ + +#define UART_ACTIVE_THRESHOLD 0x000003FF +#define UART_ACTIVE_THRESHOLD_M (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S) +#define UART_ACTIVE_THRESHOLD_V 0x000003FF +#define UART_ACTIVE_THRESHOLD_S 0 + +/* UART_SWFC_CONF0_REG register + * Software flow control character configuration + */ + +#define UART_SWFC_CONF0_REG(i) (REG_UART_BASE(i) + 0x3c) + +/* UART_XOFF_CHAR : R/W; bitpos: [16:9]; default: 19; + * This register stores the XOFF flow control character. + */ + +#define UART_XOFF_CHAR 0x000000FF +#define UART_XOFF_CHAR_M (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S) +#define UART_XOFF_CHAR_V 0x000000FF +#define UART_XOFF_CHAR_S 9 + +/* UART_XOFF_THRESHOLD : R/W; bitpos: [8:0]; default: 224; + * When the data amount in RX FIFO is more than this register value with + * UART_SW_FLOW_CON_EN set to 1, it will send a XOFF character. + */ + +#define UART_XOFF_THRESHOLD 0x000001FF +#define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S) +#define UART_XOFF_THRESHOLD_V 0x000001FF +#define UART_XOFF_THRESHOLD_S 0 + +/* UART_SWFC_CONF1_REG register + * Software flow-control character configuration + */ + +#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) + +/* UART_XON_CHAR : R/W; bitpos: [16:9]; default: 17; + * This register stores the XON flow control character. + */ + +#define UART_XON_CHAR 0x000000FF +#define UART_XON_CHAR_M (UART_XON_CHAR_V << UART_XON_CHAR_S) +#define UART_XON_CHAR_V 0x000000FF +#define UART_XON_CHAR_S 9 + +/* UART_XON_THRESHOLD : R/W; bitpos: [8:0]; default: 0; + * When the data amount in RX FIFO is less than this register value with + * UART_SW_FLOW_CON_EN set to 1, it will send a XON character. + */ + +#define UART_XON_THRESHOLD 0x000001FF +#define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S) +#define UART_XON_THRESHOLD_V 0x000001FF +#define UART_XON_THRESHOLD_S 0 + +/* UART_IDLE_CONF_REG register + * Frame-end idle configuration + */ + +#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x44) + +/* UART_TX_BRK_NUM : R/W; bitpos: [27:20]; default: 10; + * This register is used to configure the number of 0 to be sent after the + * process of sending data is done. It is active when UART_TXD_BRK is set to + * 1. + */ + +#define UART_TX_BRK_NUM 0x000000FF +#define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S) +#define UART_TX_BRK_NUM_V 0x000000FF +#define UART_TX_BRK_NUM_S 20 + +/* UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; + * This register is used to configure the duration time between transfers. + */ + +#define UART_TX_IDLE_NUM 0x000003FF +#define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S) +#define UART_TX_IDLE_NUM_V 0x000003FF +#define UART_TX_IDLE_NUM_S 10 + +/* UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; + * It will produce frame end signal when receiver takes more time to receive + * one byte data than this register value. + */ + +#define UART_RX_IDLE_THRHD 0x000003FF +#define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S) +#define UART_RX_IDLE_THRHD_V 0x000003FF +#define UART_RX_IDLE_THRHD_S 0 + +/* UART_RS485_CONF_REG register + * RS485 mode configuration + */ + +#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x48) + +/* UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0; + * This register is used to delay the transmitter's internal data signal. + */ + +#define UART_RS485_TX_DLY_NUM 0x0000000F +#define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S) +#define UART_RS485_TX_DLY_NUM_V 0x0000000F +#define UART_RS485_TX_DLY_NUM_S 6 + +/* UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0; + * This register is used to delay the receiver's internal data signal. + */ + +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S) +#define UART_RS485_RX_DLY_NUM_V 0x00000001 +#define UART_RS485_RX_DLY_NUM_S 5 + +/* UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0; + * 1'h1: enable RS485 transmitter to send data when RS485 receiver line is + * busy. + * 1'h0: RS485 transmitter should not send data when its receiver is busy. + */ + +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S) +#define UART_RS485RXBY_TX_EN_V 0x00000001 +#define UART_RS485RXBY_TX_EN_S 4 + +/* UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0; + * Set this bit to enable receiver could receive data when the transmitter + * is transmitting data in RS485 mode. + */ + +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S) +#define UART_RS485TX_RX_EN_V 0x00000001 +#define UART_RS485TX_RX_EN_S 3 + +/* UART_DL1_EN : R/W; bitpos: [2]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S) +#define UART_DL1_EN_V 0x00000001 +#define UART_DL1_EN_S 2 + +/* UART_DL0_EN : R/W; bitpos: [1]; default: 0; + * Set this bit to delay the stop bit by 1 bit. + */ + +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S) +#define UART_DL0_EN_V 0x00000001 +#define UART_DL0_EN_S 1 + +/* UART_RS485_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to choose the RS485 mode. + */ + +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S) +#define UART_RS485_EN_V 0x00000001 +#define UART_RS485_EN_S 0 + +/* UART_AT_CMD_PRECNT_REG register + * Pre-sequence timing configuration + */ + +#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x4c) + +/* UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the idle duration time before the + * first AT_CMD is received by receiver. + * It will not take the next data received as AT_CMD character when the + * duration is less than this register value. + */ + +#define UART_PRE_IDLE_NUM 0x0000FFFF +#define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S) +#define UART_PRE_IDLE_NUM_V 0x0000FFFF +#define UART_PRE_IDLE_NUM_S 0 + +/* UART_AT_CMD_POSTCNT_REG register + * Post-sequence timing configuration + */ + +#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x50) + +/* UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; + * This register is used to configure the duration time between the last + * AT_CMD and the next data. + * It will not take the previous data as AT_CMD character when the duration + * is less than this register value. + */ + +#define UART_POST_IDLE_NUM 0x0000FFFF +#define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S) +#define UART_POST_IDLE_NUM_V 0x0000FFFF +#define UART_POST_IDLE_NUM_S 0 + +/* UART_AT_CMD_GAPTOUT_REG register + * Timeout configuration + */ + +#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x54) + +/* UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; + * This register is used to configure the duration time between the AT_CMD + * chars. + * It will not take the data as continuous AT_CMD chars when the duration + * time is less than this register value. + */ + +#define UART_RX_GAP_TOUT 0x0000FFFF +#define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S) +#define UART_RX_GAP_TOUT_V 0x0000FFFF +#define UART_RX_GAP_TOUT_S 0 + +/* UART_AT_CMD_CHAR_REG register + * AT Escape Sequence Selection Configuration + */ + +#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x58) + +/* UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; + * This register is used to configure the number of continuous AT_CMD chars + * received by receiver. + */ + +#define UART_CHAR_NUM 0x000000FF +#define UART_CHAR_NUM_M (UART_CHAR_NUM_V << UART_CHAR_NUM_S) +#define UART_CHAR_NUM_V 0x000000FF +#define UART_CHAR_NUM_S 8 + +/* UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; + * This register is used to configure the content of AT_CMD character. + */ + +#define UART_AT_CMD_CHAR 0x000000FF +#define UART_AT_CMD_CHAR_M (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S) +#define UART_AT_CMD_CHAR_V 0x000000FF +#define UART_AT_CMD_CHAR_S 0 + +/* UART_MEM_CONF_REG register + * UART threshold and allocation configuration + */ + +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x5c) + +/* UART_MEM_FORCE_PU : R/W; bitpos: [27]; default: 0; + * Set this bit to force power up UART memory. + */ + +#define UART_MEM_FORCE_PU (BIT(27)) +#define UART_MEM_FORCE_PU_M (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S) +#define UART_MEM_FORCE_PU_V 0x00000001 +#define UART_MEM_FORCE_PU_S 27 + +/* UART_MEM_FORCE_PD : R/W; bitpos: [26]; default: 0; + * Set this bit to force power down UART memory. + */ + +#define UART_MEM_FORCE_PD (BIT(26)) +#define UART_MEM_FORCE_PD_M (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S) +#define UART_MEM_FORCE_PD_V 0x00000001 +#define UART_MEM_FORCE_PD_S 26 + +/* UART_RX_TOUT_THRHD : R/W; bitpos: [25:16]; default: 10; + * This register is used to configure the threshold time that receiver takes + * to receive one byte. + * The UART_RXFIFO_TOUT_INT interrupt will be triggered when the receiver + * takes more time to receive one byte with UART RX_TOUT_EN set to 1. + */ + +#define UART_RX_TOUT_THRHD 0x000003FF +#define UART_RX_TOUT_THRHD_M (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S) +#define UART_RX_TOUT_THRHD_V 0x000003FF +#define UART_RX_TOUT_THRHD_S 16 + +/* UART_RX_FLOW_THRHD : R/W; bitpos: [15:7]; default: 0; + * This register is used to configure the maximum amount of data that can be + * received when hardware flow control works. + */ + +#define UART_RX_FLOW_THRHD 0x000001FF +#define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S) +#define UART_RX_FLOW_THRHD_V 0x000001FF +#define UART_RX_FLOW_THRHD_S 7 + +/* UART_TX_SIZE : R/W; bitpos: [6:4]; default: 1; + * This register is used to configure the amount of mem allocated for TX + * FIFO. The default number is 128 bytes. + */ + +#define UART_TX_SIZE 0x00000007 +#define UART_TX_SIZE_M (UART_TX_SIZE_V << UART_TX_SIZE_S) +#define UART_TX_SIZE_V 0x00000007 +#define UART_TX_SIZE_S 4 + +/* UART_RX_SIZE : R/W; bitpos: [3:1]; default: 1; + * This register is used to configure the amount of mem allocated for RX + * FIFO. The default number is 128 bytes. + */ + +#define UART_RX_SIZE 0x00000007 +#define UART_RX_SIZE_M (UART_RX_SIZE_V << UART_RX_SIZE_S) +#define UART_RX_SIZE_V 0x00000007 +#define UART_RX_SIZE_S 1 + +/* UART_MEM_TX_STATUS_REG register + * TX FIFO write and read offset address + */ + +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60) + +/* UART_TX_RADDR : RO; bitpos: [20:11]; default: 0; + * This register stores the offset address in TX FIFO when TX FSM reads data + * via Tx_FIFO_Ctrl. + */ + +#define UART_TX_RADDR 0x000003FF +#define UART_TX_RADDR_M (UART_TX_RADDR_V << UART_TX_RADDR_S) +#define UART_TX_RADDR_V 0x000003FF +#define UART_TX_RADDR_S 11 + +/* UART_APB_TX_WADDR : RO; bitpos: [9:0]; default: 0; + * This register stores the offset address in TX FIFO when software writes + * TX FIFO via APB. + */ + +#define UART_APB_TX_WADDR 0x000003FF +#define UART_APB_TX_WADDR_M (UART_APB_TX_WADDR_V << UART_APB_TX_WADDR_S) +#define UART_APB_TX_WADDR_V 0x000003FF +#define UART_APB_TX_WADDR_S 0 + +/* UART_MEM_RX_STATUS_REG register + * RX FIFO write and read offset address + */ + +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) + +/* UART_RX_WADDR : RO; bitpos: [20:11]; default: 0; + * This register stores the offset address in RX FIFO when Rx_FIFO_Ctrl + * writes RX FIFO. + */ + +#define UART_RX_WADDR 0x000003FF +#define UART_RX_WADDR_M (UART_RX_WADDR_V << UART_RX_WADDR_S) +#define UART_RX_WADDR_V 0x000003FF +#define UART_RX_WADDR_S 11 + +/* UART_APB_RX_RADDR : RO; bitpos: [9:0]; default: 0; + * This register stores the offset address in RX_FIFO when software reads + * data from RX FIFO via APB. + */ + +#define UART_APB_RX_RADDR 0x000003FF +#define UART_APB_RX_RADDR_M (UART_APB_RX_RADDR_V << UART_APB_RX_RADDR_S) +#define UART_APB_RX_RADDR_V 0x000003FF +#define UART_APB_RX_RADDR_S 0 + +/* UART_FSM_STATUS_REG register + * UART transmit and receive status + */ + +#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) + +/* UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; + * This is the status register of transmitter. + */ + +#define UART_ST_UTX_OUT 0x0000000F +#define UART_ST_UTX_OUT_M (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S) +#define UART_ST_UTX_OUT_V 0x0000000F +#define UART_ST_UTX_OUT_S 4 + +/* UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; + * This is the status register of receiver. + */ + +#define UART_ST_URX_OUT 0x0000000F +#define UART_ST_URX_OUT_M (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S) +#define UART_ST_URX_OUT_V 0x0000000F +#define UART_ST_URX_OUT_S 0 + +/* UART_POSPULSE_REG register + * Autobaud high pulse register + */ + +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x6c) + +/* UART_POSEDGE_MIN_CNT : RO; bitpos: [19:0]; default: 1048575; + * This register stores the minimal input clock count between two positive + * edges. It is used in baud rate detection. + */ + +#define UART_POSEDGE_MIN_CNT 0x000FFFFF +#define UART_POSEDGE_MIN_CNT_M (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S) +#define UART_POSEDGE_MIN_CNT_V 0x000FFFFF +#define UART_POSEDGE_MIN_CNT_S 0 + +/* UART_NEGPULSE_REG register + * Autobaud low pulse register + */ + +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x70) + +/* UART_NEGEDGE_MIN_CNT : RO; bitpos: [19:0]; default: 1048575; + * This register stores the minimal input clock count between two negative + * edges. It is used in baud rate detection. + */ + +#define UART_NEGEDGE_MIN_CNT 0x000FFFFF +#define UART_NEGEDGE_MIN_CNT_M (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S) +#define UART_NEGEDGE_MIN_CNT_V 0x000FFFFF +#define UART_NEGEDGE_MIN_CNT_S 0 + +/* UART_DATE_REG register + * UART version control register + */ + +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x74) + +/* UART_DATE : R/W; bitpos: [31:0]; default: 403187712; + * This is the version control register. + */ + +#define UART_DATE 0xFFFFFFFF +#define UART_DATE_M (UART_DATE_V << UART_DATE_S) +#define UART_DATE_V 0xFFFFFFFF +#define UART_DATE_S 0 + +/* UART_ID_REG register + * UART ID register + */ + +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x78) + +/* UART_ID : R/W; bitpos: [31:0]; default: 1280; + * This register is used to configure the UART_ID. + */ + +#define UART_ID 0xFFFFFFFF +#define UART_ID_M (UART_ID_V << UART_ID_S) +#define UART_ID_V 0xFFFFFFFF +#define UART_ID_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_UART_H */ diff --git a/arch/xtensa/src/lx7/Kconfig b/arch/xtensa/src/lx7/Kconfig new file mode 100644 index 0000000000..78fc8a49e0 --- /dev/null +++ b/arch/xtensa/src/lx7/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_LX7 + +endif # ARCH_CHIP_LX7 diff --git a/arch/xtensa/src/lx7/Toolchain.defs b/arch/xtensa/src/lx7/Toolchain.defs new file mode 100644 index 0000000000..01d6d193ca --- /dev/null +++ b/arch/xtensa/src/lx7/Toolchain.defs @@ -0,0 +1,67 @@ +############################################################################ +# arch/xtensa/src/lx7/Toolchain.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Supported toolchains +# +# Each toolchain definition should set: +# +# CROSSDEV The GNU toolchain triple (command prefix) +# ARCHCPUFLAGS CPU-specific flags selecting the instruction set +# FPU options, etc. +# MAXOPTIMIZATION The maximum optimization level that results in +# reliable code generation. +# + +CROSSDEV = xtensa-esp32s2-elf- + +ARCHCPUFLAGS = + +ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) + MAXOPTIMIZATION := $(CONFIG_DEBUG_OPTLEVEL) +else + MAXOPTIMIZATION := -Os +endif + +# Default toolchain + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E -P -x c +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +# Add the builtin library + +EXTRA_LIBS += -lgcc +EXTRA_LIBPATHS += -L "${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name`"}" + +ifneq ($(CONFIG_LIBM),y) + EXTRA_LIBS += -lm + EXTRA_LIBPATHS += -L "${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a`"}" +endif + +ifeq ($(CONFIG_CXX_LIBSUPCXX),y) + EXTRA_LIBS += -lsupc++ + EXTRA_LIBPATHS += -L "${shell dirname "`$(CC) $(ARCHCPUFLAGS) --print-file-name=libsupc++.a`"}" +endif