From 7769266004e292902a9a0e946b7de9ccd2253f4b Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Thu, 12 Apr 2012 21:52:04 +0000
Subject: [PATCH] Kconfig update

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4597 42af7a65-404d-4744-a932-0658087f49c3
---
 arch/arm/src/stm32/chip/stm32_otgfs.h | 10 +++++-----
 arch/arm/src/stm32/stm32_otgfsdev.c   | 10 +++++-----
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/src/stm32/chip/stm32_otgfs.h b/arch/arm/src/stm32/chip/stm32_otgfs.h
index ccf7f29828..bb2cfa809b 100644
--- a/arch/arm/src/stm32/chip/stm32_otgfs.h
+++ b/arch/arm/src/stm32/chip/stm32_otgfs.h
@@ -166,10 +166,10 @@
 #define STM32_OTGFS_DIEPTSIZ3_OFFSET    0x0970 /* Device IN endpoint 3 transfer size register */
 
 #define STM32_OTGFS_DTXFSTS_OFFSET(n)   (0x0918 + ((n) << 5))
-#define STM32_OTGFS_DTXFSTS0_OFFSET     0x0918 /* Device OUT endpoint-0 transfer size register */
-#define STM32_OTGFS_DTXFSTS1_OFFSET     0x0938 /* Device OUT endpoint-1 transfer size register */
-#define STM32_OTGFS_DTXFSTS2_OFFSET     0x0958 /* Device OUT endpoint-2 transfer size register */
-#define STM32_OTGFS_DTXFSTS3_OFFSET     0x0978 /* Device OUT endpoint-3 transfer size register */
+#define STM32_OTGFS_DTXFSTS0_OFFSET     0x0918 /* Device OUT endpoint-0 TxFIFO status register */
+#define STM32_OTGFS_DTXFSTS1_OFFSET     0x0938 /* Device OUT endpoint-1 TxFIFO status register */
+#define STM32_OTGFS_DTXFSTS2_OFFSET     0x0958 /* Device OUT endpoint-2 TxFIFO status register */
+#define STM32_OTGFS_DTXFSTS3_OFFSET     0x0978 /* Device OUT endpoint-3 TxFIFO status register */
 
 #define STM32_OTGFS_DOEP_OFFSET(n)      (0x0b00 + ((n) << 5))
 #define STM32_OTGFS_DOEPCTL_EPOFFSET    0x0000 /* Device control OUT endpoint 0 control register */
@@ -894,7 +894,7 @@
 #define OTGFS_DIEPTSIZ_MCNT_SHIFT       (29)      /* Bits 29-30: Multi count */
 #define OTGFS_DIEPTSIZ_MCNT_MASK        (3 << OTGFS_DIEPTSIZ_MCNT_SHIFT)
                                                   /* Bit 31: Reserved, must be kept at reset value */
-/* Device OUT endpoint-0 transfer size register */
+/* Device OUT endpoint TxFIFO status register */
 
 #define OTGFS_DTXFSTS_MASK              (0xffff)
 
diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c
index 8f16f62052..e3b6b01421 100755
--- a/arch/arm/src/stm32/stm32_otgfsdev.c
+++ b/arch/arm/src/stm32/stm32_otgfsdev.c
@@ -1445,7 +1445,7 @@ static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt)
   /* Get the number of bytes to transfer from the RxFIFO */
 
   buflen  = privreq->req.len - privreq->req.xfrd;
-  DEBUGASSERT(buflen > 0 && buflen <= bcnt);
+  DEBUGASSERT(buflen > 0 && buflen >= bcnt);
   readlen = MIN(buflen, bcnt);
 
   /* Get the destination of the data transfer */
@@ -2470,7 +2470,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv)
            * used in polled mode by the endpoint disable logic).
            */
 #if 1
-#warning "REVISIT"
+          /* REVISIT: */
           if ((doepint & OTGFS_DOEPINT_EPDISD) != 0)
             {
               usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), (uint16_t)doepint);
@@ -3750,7 +3750,7 @@ static void stm32_epout_disable(FAR struct stm32_ep_s *privep)
   regaddr = STM32_OTGFS_DOEPINT(privep->epphy);
   while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0);
 #else
-# warning "REVISIT"
+  /* REVISIT: */
   up_mdelay(50);
 #endif
 
@@ -4135,7 +4135,7 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep)
   regaddr = STM32_OTGFS_DOEPINT(privep->epphy);
   while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0);
 #else
-# warning "REVISIT"
+  /* REVISIT: */
   up_mdelay(50);
 #endif
 
@@ -4149,7 +4149,7 @@ static int stm32_epout_setstall(FAR struct stm32_ep_s *privep)
   return OK;
 #else
   /* This implementation follows the STMicro code example. */
-#warning "REVISIT"
+  /* REVISIT: */
 
   uint32_t regaddr;
   uint32_t regval;