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Revert "arch/arm/src/xmc4: Serial fix... Cannot use SR1 for RXD. It will not work on this hardware. This means that no more than on UART can be configured per USIC."

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This reverts commit 88982df09c.
This commit is contained in:
Gregory Nutt 2017-11-25 09:45:12 -06:00
parent 3160613db4
commit 776b65bc90
4 changed files with 35 additions and 36 deletions
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12
arch/arm/src/xmc4/Kconfig
View File

@ -132,8 +132,7 @@ endchoice # USIC0 Channel 0 Configuration
choice
prompt "USIC0 Channel 1 Configuration"
default XMC4_USIC0_CHAN1_ISUART if !XMC4_USIC0_CHAN0_ISUART
default XMC4_USIC0_CHAN1_NONE if XMC4_USIC0_CHAN0_ISUART
default XMC4_USIC0_CHAN1_ISUART
depends on XMC4_USIC0
config XMC4_USIC0_CHAN1_NONE
@ -145,7 +144,6 @@ config XMC4_USIC0_CHAN1_ISUART
bool "UART1"
select UART1_SERIALDRIVER
select XMC4_USCI_UART
depends on !XMC4_USIC0_CHAN0_ISUART
---help---
Configure USIC0 Channel 1 as a UART
@ -220,8 +218,7 @@ endchoice # USIC1 Channel 0 Configuration
choice
prompt "USIC1 Channel 1 Configuration"
default XMC4_USIC1_CHAN1_ISUART if !XMC4_USIC1_CHAN0_ISUART
default XMC4_USIC1_CHAN1_NONE if XMC4_USIC1_CHAN0_ISUART
default XMC4_USIC1_CHAN1_ISUART
depends on XMC4_USIC1
config XMC4_USIC1_CHAN1_NONE
@ -233,7 +230,6 @@ config XMC4_USIC1_CHAN1_ISUART
bool "UART3"
select UART3_SERIALDRIVER
select XMC4_USCI_UART
depends on !XMC4_USIC1_CHAN0_ISUART
---help---
Configure USIC1 Channel 1 as a UART
@ -308,8 +304,7 @@ endchoice # USIC2 Channel 0 Configuration
choice
prompt "USIC2 Channel 1 Configuration"
default XMC4_USIC2_CHAN1_ISUART if !XMC4_USIC2_CHAN0_ISUART
default XMC4_USIC2_CHAN1_NONE if XMC4_USIC2_CHAN0_ISUART
default XMC4_USIC2_CHAN1_ISUART
depends on XMC4_USIC2
config XMC4_USIC2_CHAN1_NONE
@ -321,7 +316,6 @@ config XMC4_USIC2_CHAN1_ISUART
bool "UART5"
select UART5_SERIALDRIVER
select XMC4_USCI_UART
depends on !XMC4_USIC2_CHAN0_ISUART
---help---
Configure USIC2 Channel 1 as a UART

41
arch/arm/src/xmc4/xmc4_lowputc.c
View File

@ -205,24 +205,24 @@ void xmc4_lowsetup(void)
(void)xmc4_gpio_config(GPIO_UART0_TXD0);
#endif
#ifdef HAVE_UART1
(void)xmc4_gpio_config(GPIO_UART1_RXD);
(void)xmc4_gpio_config(GPIO_UART1_TXD);
(void)xmc4_gpio_config(GPIO_UART0_RXD1);
(void)xmc4_gpio_config(GPIO_UART0_TXD1);
#endif
#ifdef HAVE_UART2
(void)xmc4_gpio_config(GPIO_UART2_RXD);
(void)xmc4_gpio_config(GPIO_UART2_TXD);
(void)xmc4_gpio_config(GPIO_UART0_RXD2);
(void)xmc4_gpio_config(GPIO_UART0_TXD2);
#endif
#ifdef HAVE_UART3
(void)xmc4_gpio_config(GPIO_UART3_RXD);
(void)xmc4_gpio_config(GPIO_UART3_TXD);
(void)xmc4_gpio_config(GPIO_UART0_RXD3);
(void)xmc4_gpio_config(GPIO_UART0_TXD3);
#endif
#ifdef HAVE_UART4
(void)xmc4_gpio_config(GPIO_UART4_RXD);
(void)xmc4_gpio_config(GPIO_UART4_TXD);
(void)xmc4_gpio_config(GPIO_UART0_RXD4);
(void)xmc4_gpio_config(GPIO_UART0_TXD4);
#endif
#ifdef HAVE_UART5
(void)xmc4_gpio_config(GPIO_UART5_RXD);
(void)xmc4_gpio_config(GPIO_UART5_TXD);
(void)xmc4_gpio_config(GPIO_UART0_RXD5);
(void)xmc4_gpio_config(GPIO_UART0_TXD5);
#endif
#ifdef HAVE_UART_CONSOLE
@ -412,18 +412,23 @@ int xmc4_uart_configure(enum usic_channel_e channel,
/* Set service request for UART protocol, receiver, and transmitter events.
*
* Set channel 0/1 events on sevice request 0. Only SR0 can be used with
* RXD events. This precludes use of Channel 0 and Channel 1 concurrently
* for UARTs since both will map to the same interrupt request.
* Set channel 0 events on sevice request 0
* Set channel 1 events on sevice request 1
*/
regval = getreg32(base + XMC4_USIC_INPR_OFFSET);
regval &= ~(USIC_INPR_TBINP_MASK | USIC_INPR_RINP_MASK |
USIC_INPR_AINP_MASK | USIC_INPR_PINP_MASK);
regval |= (USIC_INPR_TBINP_SR0 | USIC_INPR_RINP_SR0 |
USIC_INPR_AINP_SR0 | USIC_INPR_PINP_SR0);
putreg32(regval, base + XMC4_USIC_INPR_OFFSET);
regval &= ~(USIC_INPR_TBINP_MASK | USIC_INPR_RINP_MASK | USIC_INPR_PINP_MASK);
if (((unsigned int)channel & 1) != 0)
{
regval |= (USIC_INPR_TBINP_SR1 | USIC_INPR_RINP_SR1 | USIC_INPR_PINP_SR1);
}
else
{
regval |= (USIC_INPR_TBINP_SR0 | USIC_INPR_RINP_SR0 | USIC_INPR_PINP_SR0);
}
putreg32(regval, base + XMC4_USIC_INPR_OFFSET);
return OK;
}
#endif

10
arch/arm/src/xmc4/xmc4_serial.c
View File

@ -226,9 +226,9 @@
/* Event sets */
#ifdef CONFIG_DEBUG_FEATURES
# define CCR_RX_EVENTS (USIC_CCR_RIEN | USIC_CCR_AIEN | USIC_CCR_DLIEN)
# define CCR_RX_EVENTS (USIC_CCR_RIEN | USIC_CCR_DLIEN)
#else
# define CCR_RX_EVENTS (USIC_CCR_RIEN | USIC_CCR_AIEN)
# define CCR_RX_EVENTS (USIC_CCR_RIEN)
#endif
#define CCR_TX_EVENTS (USIC_CCR_TBIEN)
@ -362,7 +362,7 @@ static struct xmc4_dev_s g_uart1priv =
{
.uartbase = XMC4_USIC0_CH1_BASE,
.channel = (uint8_t)USIC0_CHAN1,
.irq = XMC4_IRQ_USIC0_SR0,
.irq = XMC4_IRQ_USIC0_SR1,
.config =
{
.baud = CONFIG_UART1_BAUD,
@ -432,7 +432,7 @@ static struct xmc4_dev_s g_uart3priv =
{
.uartbase = XMC4_USIC1_CH1_BASE,
.channel = (uint8_t)USIC1_CHAN1,
.irq = XMC4_IRQ_USIC1_SR0,
.irq = XMC4_IRQ_USIC1_SR1,
.config =
{
.baud = CONFIG_UART3_BAUD,
@ -502,7 +502,7 @@ static struct xmc4_dev_s g_uart5priv =
{
.uartbase = XMC4_USIC2_CH1_BASE,
.channel = (uint8_t)USIC2_CHAN1,
.irq = XMC4_IRQ_USIC2_SR0,
.irq = XMC4_IRQ_USIC2_SR1,
.config =
{
.baud = CONFIG_UART5_BAUD,

8
configs/xmc4500-relax/include/board.h
View File

@ -327,8 +327,8 @@
*/
#define BOARD_UART0_DX USIC_DXB
#define GPIO_UART0_RXD GPIO_U0C0_DX0B
#define GPIO_UART0_TXD (GPIO_U0C0_DOUT0_3 | GPIO_PADA1P_STRONGSOFT | GPIO_OUTPUT_SET)
#define GPIO_UART0_RXD0 GPIO_U0C0_DX0B
#define GPIO_UART0_TXD0 (GPIO_U0C0_DOUT0_3 | GPIO_PADA1P_STRONGSOFT | GPIO_OUTPUT_SET)
/* USIC1 CH1 is used as UART3
*
@ -337,8 +337,8 @@
*/
#define BOARD_UART3_DX USIC_DXD
#define GPIO_UART3_RXD (GPIO_U1C1_DX0D | GPIO_INPUT_PULLUP)
#define GPIO_UART3_TXD (GPIO_U1C1_DOUT0_2 | GPIO_PADA1P_STRONGSOFT | GPIO_OUTPUT_SET)
#define GPIO_UART0_RXD3 (GPIO_U1C1_DX0D | GPIO_INPUT_PULLUP)
#define GPIO_UART0_TXD3 (GPIO_U1C1_DOUT0_2 | GPIO_PADA1P_STRONGSOFT | GPIO_OUTPUT_SET)
/************************************************************************************
* Public Data