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arch/arm/src/lpc54xx: Add EMC register definitions. Add basic build support for EMC and SDRAM.

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This commit is contained in:
Gregory Nutt 2017-12-10 12:40:01 -06:00
parent 66ee22f363
commit 77728f49f1
10 changed files with 757 additions and 33 deletions
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21
arch/arm/src/lpc54xx/Kconfig
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@ -165,6 +165,10 @@ config LPC54_FLEXCOMM9
menu "LPC54xx Peripheral Selection"
config LPC54_EMC
bool "External Memory Controller (EMC)"
default n
config LPC54_USART0
bool "USART0"
default n
@ -227,6 +231,8 @@ config LPC54_USART9
endmenu # LPC54xx Peripheral Selection
menu "GPIO Interrupt Configuration"
config LPC54_GPIOIRQ
bool "Support GPIO Interrupts"
default n
@ -235,3 +241,18 @@ config LPC54_GPIOIRQ_GROUPS
bool "Support GPIO Interrupt groupe"
default n
depends on LPC54_GPIOIRQ && EXPERIMENTAL
endmenu # LPC54xx Peripheral Selection
menu "EMC Configuration"
depends on LPC54_EMC
config LPC54_EMC_STATIC
bool "EMC static memory support"
default n
config LPC54_EMC_DYNAMIC
bool "EMC dynamic memory support"
default n
endmenu # LPC54xx Peripheral Selection

5
arch/arm/src/lpc54xx/Make.defs
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@ -101,3 +101,8 @@ endif
ifneq ($(CONFIG_LPC54_GPIOIRQ),y)
CHIP_CSRCS += lpc54_gpioirq.c
endif
ifneq ($(CONFIG_LPC54_EMC),y)
CHIP_CSRCS += lpc54_emc.c
endif

336
arch/arm/src/lpc54xx/chip/lpc54_emc.h Normal file
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@ -0,0 +1,336 @@
/****************************************************************************************************
* arch/arm/src/lpc54xx/lpc54_emc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_EMC_H
#define __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_EMC_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include "chip/lpc54_memorymap.h"
/****************************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
#define LPC54_EMC_CS0 0
#define LPC54_EMC_CS1 1
#define LPC54_EMC_CS2 2
#define LPC54_EMC_CS3 3
/* Register offsets *********************************************************************************/
#define LPC54_EMC_CONTROL_OFFSET 0x0000 /* Controls operation of the memory controller */
#define LPC54_EMC_STATUS_OFFSET 0x0004 /* Provides EMC status information */
#define LPC54_EMC_CONFIG_OFFSET 0x0008 /* Configures operation of the memory controller */
#define LPC54_EMC_DYNCONTROL_OFFSET 0x0020 /* Controls dynamic memory operation */
#define LPC54_EMC_DYNREFRESH_OFFSET 0x0024 /* Configures dynamic memory refresh */
#define LPC54_EMC_DYNREADCONFIG_OFFSET 0x0028 /* Configures dynamic memory read strategy */
#define LPC54_EMC_DYNRP_OFFSET 0x0030 /* Precharge command period */
#define LPC54_EMC_DYNRAS_OFFSET 0x0034 /* Active to precharge command period */
#define LPC54_EMC_DYNSREX_OFFSET 0x0038 /* Self-refresh exit time */
#define LPC54_EMC_DYNAPR_OFFSET 0x003c /* Last-data-out to active command time */
#define LPC54_EMC_DYNDAL_OFFSET 0x0040 /* Data-in to active command time */
#define LPC54_EMC_DYNWR_OFFSET 0x0044 /* Write recovery time */
#define LPC54_EMC_DYNRC_OFFSET 0x0048 /* Selects the active to active command period */
#define LPC54_EMC_DYNRFC_OFFSET 0x004c /* Selects the auto-refresh period */
#define LPC54_EMC_DYNXSR_OFFSET 0x0050 /* Time for exit self-refresh to active command */
#define LPC54_EMC_DYNRRD_OFFSET 0x0054 /* Latency for active bank A to active bank B */
#define LPC54_EMC_DYNMRD_OFFSET 0x0058 /* Time for load mode register to active command */
#define LPC54_EMC_STATEXTWAIT_OFFSET 0x0080 /* Time for long static memory read and write transfers */
/* Per-chip select dynamic memory registers */
#define LPC54_EMC_DYNCS_OFFSET(n) (0x0100 + (n) << 5)
#define LPC54_EMC_DYNCONFIG_OFFSET 0x0000 /* Configuration information for CSn */
#define LPC54_EMC_DYNRASCAS_OFFSET 0x0004 /* RAS and CAS latencies for CSn */
#define LPC54_EMC_DYNCONFIGn_OFFSET(n) (0x0100 + (n) << 5)
#define LPC54_EMC_DYNRASCASn_OFFSET(n) (0x0104 + (n) << 5)
/* Per-chip select static memory registers */
#define LPC54_EMC_STATCS_OFFSET(n) (0x0200 + (n) << 5)
#define LPC54_EMC_STATCONFIG_OFFSET 0x0000 /* Configuration for CSn */
#define LPC54_EMC_STATWAITWEN_OFFSET 0x0004 /* Delay to write enable */
#define LPC54_EMC_STATWAITOEN_OFFSET 0x0008 /* Delay to output enable */
#define LPC54_EMC_STATWAITRD_OFFSET 0x000c /* Delay to read access */
#define LPC54_EMC_STATWAITPAGE_OFFSET 0x0010 /* Delay for asynchronous page mode accesses */
#define LPC54_EMC_STATWAITWR_OFFSET 0x0014 /* Delay from EMC_CS0 to a write access */
#define LPC54_EMC_STATWAITTURN_OFFSET 0x0018 /* Number of bus turnaround cycles */
#define LPC54_EMC_STATCONFIGn_OFFSET(n) (0x0200 + (n) << 5)
#define LPC54_EMC_STATWAITWENn_OFFSET(n) (0x0204 + (n) << 5)
#define LPC54_EMC_STATWAITOENn_OFFSET(n) (0x0208 + (n) << 5)
#define LPC54_EMC_STATWAITRDn_OFFSET(n) (0x020c + (n) << 5)
#define LPC54_EMC_STATWAITPAGEn_OFFSET(n) (0x0210 + (n) << 5)
#define LPC54_EMC_STATWAITWRn_OFFSET(n) (0x0214 + (n) << 5)
#define LPC54_EMC_STATWAITTURNn_OFFSET(n) (0x0218 + (n) << 5)
/* Register addresses *******************************************************************************/
#define LPC54_EMC_CONTROL (LPC54_EMC_BASE + LPC54_EMC_CONTROL_OFFSET)
#define LPC54_EMC_STATUS (LPC54_EMC_BASE + LPC54_EMC_STATUS_OFFSET)
#define LPC54_EMC_CONFIG (LPC54_EMC_BASE + LPC54_EMC_CONFIG_OFFSET)
#define LPC54_EMC_DYNCONTROL (LPC54_EMC_BASE + LPC54_EMC_DYNCONTROL_OFFSET)
#define LPC54_EMC_DYNREFRESH (LPC54_EMC_BASE + LPC54_EMC_DYNREFRESH_OFFSET)
#define LPC54_EMC_DYNREADCONFIG (LPC54_EMC_BASE + LPC54_EMC_DYNREADCONFIG_OFFSET)
#define LPC54_EMC_DYNRP (LPC54_EMC_BASE + LPC54_EMC_DYNRP_OFFSET)
#define LPC54_EMC_DYNRAS (LPC54_EMC_BASE + LPC54_EMC_DYNRAS_OFFSET)
#define LPC54_EMC_DYNSREX (LPC54_EMC_BASE + LPC54_EMC_DYNSREX_OFFSET)
#define LPC54_EMC_DYNAPR (LPC54_EMC_BASE + LPC54_EMC_DYNAPR_OFFSET)
#define LPC54_EMC_DYNDAL (LPC54_EMC_BASE + LPC54_EMC_DYNDAL_OFFSET)
#define LPC54_EMC_DYNWR (LPC54_EMC_BASE + LPC54_EMC_DYNWR_OFFSET)
#define LPC54_EMC_DYNRC (LPC54_EMC_BASE + LPC54_EMC_DYNRC_OFFSET)
#define LPC54_EMC_DYNRFC (LPC54_EMC_BASE + LPC54_EMC_DYNRFC_OFFSET)
#define LPC54_EMC_DYNXSR (LPC54_EMC_BASE + LPC54_EMC_DYNXSR_OFFSET)
#define LPC54_EMC_DYNRRD (LPC54_EMC_BASE + LPC54_EMC_DYNRRD_OFFSET)
#define LPC54_EMC_DYNMRD (LPC54_EMC_BASE + LPC54_EMC_DYNMRD_OFFSET)
#define LPC54_EMC_STATEXTWAIT (LPC54_EMC_BASE + LPC54_EMC_STATEXTWAIT_OFFSET)
/* Per-chip select dynamic memory registers */
#define LPC54_EMC_DYNCS_BASE(n) (LPC54_EMC_BASE + LPC54_EMC_DYNCS_OFFSET(n))
#define LPC54_EMC_DYNCONFIG(n) (LPC54_EMC_DYNCS_BASE(n) + LPC54_EMC_DYNCONFIG_OFFSET)
#define LPC54_EMC_DYNRASCAS(n) (LPC54_EMC_DYNCS_BASE(n) + LPC54_EMC_DYNRASCAS_OFFSET)
/* Per-chip select static memory registers */
#define LPC54_EMC_STATCS_BASE(n) (LPC54_EMC_BASE + LPC54_EMC_STATCS_OFFSET(n))
#define LPC54_EMC_STATCONFIG(n) (LPC54_EMC_STATCS_BASE(n) + LPC54_EMC_STATCONFIG_OFFSET)
#define LPC54_EMC_STATWAITWEN(n) (LPC54_EMC_STATCS_BASE(n) + LPC54_EMC_STATWAITWEN_OFFSET)
#define LPC54_EMC_STATWAITOEN(n) (LPC54_EMC_STATCS_BASE(n) + LPC54_EMC_STATWAITOEN_OFFSET)
#define LPC54_EMC_STATWAITRD(n) (LPC54_EMC_STATCS_BASE(n) + LPC54_EMC_STATWAITRD_OFFSET)
#define LPC54_EMC_STATWAITPAGE(n) (LPC54_EMC_STATCS_BASE(n) + LPC54_EMC_STATWAITPAGE_OFFSET)
#define LPC54_EMC_STATWAITWR(n) (LPC54_EMC_STATCS_BASE(n) + LPC54_EMC_STATWAITWR_OFFSET)
#define LPC54_EMC_STATWAITTURN(n) (LPC54_EMC_STATCS_BASE(n) + LPC54_EMC_STATWAITTURN_OFFSET)
/* Register bit definitions *************************************************************************/
/* Controls operation of the memory controller */
#define EMC_CONTROL_E (1 << 0) /* Bit 0: EMC Enable */
#define EMC_CONTROL_M (1 << 1) /* Bit 1: Address mirror */
#define EMC_CONTROL_L (1 << 2) /* Bit 2: Low-power mode */
/* Provides EMC status information */
#define EMC_STATUS_B (1 << 0) /* Bit 0: Busy */
#define EMC_STATUS_S (1 << 1) /* Bit 1: Write buffer status */
#define EMC_STATUS_SA (1 << 2) /* Bit 2: Self-refresh acknowledge */
/* Configures operation of the memory controller */
#define EMC_CONFIG_EM (1 << 0) /* Bit 0: EM Endian mode */
#define EMC_CONFIG_CLKR (1 << 8) /* Bit 8: Must be zero */
/* Controls dynamic memory operation */
#define EMC_DYNCONTROL_CE (1 << 0) /* Bit 0: Dynamic memory clock enable */
#define EMC_DYNCONTROL_CS (1 << 1) /* Bit 1: Dynamic memory clock control */
#define EMC_DYNCONTROL_SR (1 << 2) /* Bit 2: Self-refresh request, EMCSREFREQ */
#define EMC_DYNCONTROL_MMC (1 << 5) /* Bit 5 Memory clock control */
#define EMC_DYNCONTROL_I_SHIFT (7) /* Bit 7-8: SDRAM initialization */ */
#define EMC_DYNCONTROL_I_MASK (3 << EMC_DYNCONTROL_I_SHIFT)
# define EMC_DYNCONTROL_I_NORMAL (0 << EMC_DYNCONTROL_I_SHIFT) /* Issue SDRAM NORMAL operation command */
# define EMC_DYNCONTROL_I_MODE (1 << EMC_DYNCONTROL_I_SHIFT) /* Issue SDRAM MODE command */
# define EMC_DYNCONTROL_I_PALL (2 << EMC_DYNCONTROL_I_SHIFT) /* Issue SDRAM PALL (precharge all) command */
# define EMC_DYNCONTROL_I_NOP (3 << EMC_DYNCONTROL_I_SHIFT) /* Issue SDRAM NOP (no operation) command */
/* Configures dynamic memory refresh */
#define EMC_DYNREFRESH_SHIFT (0) /* Bits 0-10: Refresh timer */
#define EMC_DYNREFRESH_MASK (0x7ff << EMC_DYNREFRESH_SHIFT)
# define EMC_DYNREFRESH_DISABLE(n) (0 << EMC_DYNREFRESH_SHIFT)
# define EMC_DYNREFRESH(n) ((uint32_t)((n) >> 4) << EMC_DYNREFRESH_SHIFT)
/* Configures dynamic memory read strategy */
#define EMC_DYNREADCONFIG_SHIFT (0) /* Bits 0-1: Read data strategy */
#define EMC_DYNREADCONFIG_MASK (3 << EMC_DYNREADCONFIG_SHIFT)
# define EMC_DYNREADCONFIG_PLUS0 (1 << EMC_DYNREADCONFIG_SHIFT) /* Using EMCCLKDELAY */
# define EMC_DYNREADCONFIG_PLUS1 (2 << EMC_DYNREADCONFIG_SHIFT) /* Plus one clock cycle using EMCCLKDELAY */
# define EMC_DYNREADCONFIG_PLUS2 (3 << EMC_DYNREADCONFIG_SHIFT) /* Plus two clock cycles using EMCCLKDELAY */
/* Precharge command period */
#define EMC_DYNRP_SHIFT (0) /* Bits 0-3: Precharge command period */
#define EMC_DYNRP_MASK (15 << EMC_DYNRP_SHIFT)
# define EMC_DYNRP(n) ((uint32_t)((n)-1) << EMC_DYNRP_SHIFT)
/* Active to precharge command period */
#define EMC_DYNRAS_SHIFT (0) /* Bits 0-3: Active to precharge command period */
#define EMC_DYNRAS_MASK (15 << EMC_DYNRAS_SHIFT)
# define EMC_DYNRAS(n) ((uint32_t)((n)-1) << EMC_DYNRAS_SHIFT)
/* Self-refresh exit time */
#define EMC_DYNSREX_SHIFT (0) /* Bits 0-3: Self-refresh exit time */
#define EMC_DYNSREX_MASK (15 << EMC_DYNSREX_SHIFT)
# define EMC_DYNSREX(n) ((uint32_t)((n)-1) << EMC_DYNSREX_SHIFT)
/* Last-data-out to active command time */
#define EMC_DYNAPR_SHIFT (0) /* Bits 0-3: Self-refresh exit time */
#define EMC_DYNAPR_MASK (15 << EMC_DYNAPR_SHIFT)
# define EMC_DYNAPR(n) ((uint32_t)((n)-1) << EMC_DYNAPR_SHIFT)
/* Data-in to active command time */
#define EMC_DYNDAL_SHIFT (0) /* Bits 0-3: Data-in to active command */
#define EMC_DYNDAL_MASK (15 << EMC_DYNDAL_SHIFT)
# define EMC_DYNDAL(n) ((uint32_t)((n)-1) << EMC_DYNDAL_SHIFT)
/* Write recovery time */
#define EMC_DYNWR_SHIFT (0) /* Bits 0-3: Data-in to active command */
#define EMC_DYNWR_MASK (15 << EMC_DYNWR_SHIFT)
# define EMC_DYNWR(n) ((uint32_t)((n)-1) << EMC_DYNWR_SHIFT)
/* Selects the active to active command period */
#define EMC_DYNRC_SHIFT (0) /* Bits 0-4: Data-in to active command */
#define EMC_DYNRC_MASK (31 << EMC_DYNRC_SHIFT)
# define EMC_DYNRC(n) ((uint32_t)((n)-1) << EMC_DYNRC_SHIFT)
/* Selects the auto-refresh period */
#define EMC_DYNRFC_SHIFT (0) /* Bits 0-4: Auto-refresh period and auto-refresh to active command period */
#define EMC_DYNRFC_MASK (31 << EMC_DYNRFC_SHIFT)
# define EMC_DYNRFC(n) ((uint32_t)((n)-1) << EMC_DYNRFC_SHIFT)
/* Time for exit self-refresh to active command */
#define EMC_DYNXSR_SHIFT (0) /* Bits 0-4: Exit self-refresh to active command time */
#define EMC_DYNXSR_MASK (31 << EMC_DYNXSR_SHIFT)
# define EMC_DYNXSR(n) ((uint32_t)((n)-1) << EMC_DYNXSR_SHIFT)
/* Latency for active bank A to active bank B */
#define EMC_DYNRRD_SHIFT (0) /* Bits 0-3: Active bank A to active bank B latency */
#define EMC_DYNRRD_MASK (15 << EMC_DYNRRD_SHIFT)
# define EMC_DYNRRD(n) ((uint32_t)((n)-1) << EMC_DYNRRD_SHIFT)
/* Time for load mode register to active command */
#define EMC_DYNMRD_SHIFT (0) /* Bits 0-3: Load mode register to active command time */
#define EMC_DYNMRD_MASK (15 << EMC_DYNMRD_SHIFT)
# define EMC_DYNMRD(n) ((uint32_t)((n)-1) << EMC_DYNMRD_SHIFT)
/* Time for long static memory read and write transfers */
#define EMC_STATEXTWAIT_SHIFT (0) /* Bits 0-9: Extended wait time out */
#define EMC_STATEXTWAIT_MASK (0x3ff << EMC_STATEXTWAIT_SHIFT)
# define EMC_STATEXTWAIT(n) ((uint32_t)((n)-1) << EMC_STATEXTWAIT_SHIFT)
/* Per-chip select dynamic memory registers */
/* Dynamic Memory Configuration registers */
#define EMC_DYNCONFIG_
#define EMC_DYNCONFIG_MD_SHIFT (3) /* Bits 3-4: Memory device */
#define EMC_DYNCONFIG_MD_MASK (3 << EMC_DYNCONFIG_MD_SHIFT)
# define EMC_DYNCONFIG_MD_SDRAM (0 << EMC_DYNCONFIG_MD_SHIFT) /* SDRAM */
# define EMC_DYNCONFIG_MD_LPDRAM (1 << EMC_DYNCONFIG_MD_SHIFT) /* Low-power SDRAM */
#define EMC_DYNCONFIG_AM0_SHIFT (7) /* Bits 7-12: See Table 656 in User Manual */
#define EMC_DYNCONFIG_AM0_MASK (0x3f << EMC_DYNCONFIG_AM0_SHIFT)
# define EMC_DYNCONFIG_AM0(n) ((uint32_t)(n) << EMC_DYNCONFIG_AM0_SHIFT)
#define EMC_DYNCONFIG_AM1 (1 << 14) /* Bit 14: See Table 656 in User Manual */
#define EMC_DYNCONFIG_B (1 << 19) /* Bit 19: Buffer enable */
#define EMC_DYNCONFIG_P (1 << 20) /* Bit 20: Write protect */
/* Dynamic Memory RAS and CAS Delay registers */
#define EMC_DYNRASCAS_RAS_SHIFT (0) /* Bits 0-1: RAS latency */
#define EMC_DYNRASCAS_RAS_MASK (3 << EMC_DYNRASCAS_RAS_SHIFT)
# define EMC_DYNRASCAS_RAS(n) ((uint32_t)(n) << EMC_DYNRASCAS_RAS_SHIFT)
#define EMC_DYNRASCAS_CAS_SHIFT (8) /* Bits 9-9: CAS latency */
#define EMC_DYNRASCAS_CAS_MASK (3 << EMC_DYNRASCAS_CAS_SHIFT)
# define EMC_DYNRASCAS_CAS(n) ((uint32_t)(n) << EMC_DYNRASCAS_CAS_SHIFT)
/* Per-chip select static memory registers */
/* Static Memory Configuration registers */
#define EMC_STATCONFIG_MW_SHIFT (0) /* Bits 0-1: Memory width */
#define EMC_STATCONFIG_MW_MASK (3 << EMC_STATCONFIG_MW_SHIFT)
# define EMC_STATCONFIG_MW_8BIT (0 << EMC_STATCONFIG_MW_SHIFT) /* 8 bit */
# define EMC_STATCONFIG_MW_16BIT (1 << EMC_STATCONFIG_MW_SHIFT) /* 16 bit */
# define EMC_STATCONFIG_MW_32BIT (2 << EMC_STATCONFIG_MW_SHIFT) /* 32 bit */
#define EMC_STATCONFIG_PM (1 << 3) /* Bit 3: Page mode */
#define EMC_STATCONFIG_PC (1 << 6) /* Bit 6: Chip select polarity */
#define EMC_STATCONFIG_PB (1 << 7) /* Bit 7: Byte lane state */
#define EMC_STATCONFIG_EW (1 << 8) /* Bit 8: Extended wait */
#define EMC_STATCONFIG_B (1 << 19) /* Bit 19: Buffer enable */
#define EMC_STATCONFIG_P (1 << 20) /* Bit 20: Write protect */
/* Static Memory Write Enable Delay registers */
#define EMC_STATWAITWEN_SHIFT (0) /* Bits 0-3: Wait write enable */
#define EMC_STATWAITWEN_MASK (15 << EMC_STATWAITWEN_SHIFT)
# define EMC_STATWAITWEN(n) ((uint32_t)((n)-1) << EMC_STATWAITWEN_SHIFT)
/* Static Memory Output Enable delay registers */
#define EMC_STATWAITOEN_SHIFT (0) /* Bits 0-3: Wait output enable */
#define EMC_STATWAITOEN_MASK (15 << EMC_STATWAITOEN_SHIFT)
# define EMC_STATWAITOEN_NONE (0 << EMC_STATWAITOEN_SHIFT)
# define EMC_STATWAITOEN(n) ((uint32_t)(n) << EMC_STATWAITOEN_SHIFT)
/* Static Memory Read Delay registers */
#define EMC_STATWAITRD_SHIFT (0) /* Bits 0-4: Non-page mode read wait states */
#define EMC_STATWAITRD_MASK (31 << EMC_STATWAITRD_SHIFT)
# define EMC_STATWAITRD(n) ((uint32_t)((n)-1) << EMC_STATWAITRD_SHIFT)
/* Static Memory Page Mode Read Delay registers */
#define EMC_STATWAITPAGE_SHIFT (0) /* Bits 0-4: Page mode erad wait states */
#define EMC_STATWAITPAGE_MASK (31 << EMC_STATWAITPAGE_SHIFT)
# define EMC_STATWAITPAGE(n) ((uint32_t)((n)-1) << EMC_STATWAITPAGE_SHIFT)
/* Static Memory Write Delay registers */
#define EMC_STATWAITWR_SHIFT (0) /* Bits 0-4: Write wait states */
#define EMC_STATWAITWR_MASK (31 << EMC_STATWAITWR_SHIFT)
# define EMC_STATWAITWR(n) ((uint32_t)((n)-2) << EMC_STATWAITWR_SHIFT)
/* Static Memory Turn-around Delay registers */
#define EMC_STATWAITTURN_SHIFT (0) /* Bits 0-3: Bus turn-around cycles */
#define EMC_STATWAITTURN_MASK (15 << EMC_STATWAITTURN_SHIFT)
# define EMC_STATWAITTURN(n) ((uint32_t)((n)-1) << EMC_STATWAITTURN_SHIFT)
#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_EMC_H */

103
arch/arm/src/lpc54xx/chip/lpc54_syscon.h
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@ -347,24 +347,69 @@
#define SYSCON_PIORESCAP0_
/* Reset captured value of port 1 */
#define SYSCON_PIORESCAP1_
/* Peripheral reset control 0 */
#define SYSCON_PRESETCTRL0_
/* Peripheral reset control 1 */
#define SYSCON_PRESETCTRL1_
/* Peripheral reset control 2 */
#define SYSCON_PRESETCTRL2_
/* Set bits in PRESETCTRL0 */
#define SYSCON_PRESETCTRLSET0_
/* Set bits in PRESETCTRL1 */
#define SYSCON_PRESETCTRLSET1_
/* Set bits in PRESETCTRL2 */
#define SYSCON_PRESETCTRLSET2_
/* Clear bits in PRESETCTRL0 */
#define SYSCON_PRESETCTRLCLR0_
/* Clear bits in PRESETCTRL1 */
#define SYSCON_PRESETCTRLCLR1_
/* Clear bits in PRESETCTRL2 */
#define SYSCON_PRESETCTRLCLR2_
/* Peripheral reset control 0: PRESETCTRL0, PRESETCTRLSET0, and PRESETCTRLCLR0 */
#define SYSCON_PRESETCTRL0_FLASH (1 << 7) /* Bit 7: Reset the flash controller */
#define SYSCON_PRESETCTRL0_FMC (1 << 8) /* Bit 8: Reset the Flash accelerator */
#define SYSCON_PRESETCTRL0_EEPROM (1 << 9) /* Bit 9: Reset EEPROM */
#define SYSCON_PRESETCTRL0_SPIFI (1 << 10) /* Bit 10: Reset the SPIFI */
#define SYSCON_PRESETCTRL0_INPUTMUX (1 << 11) /* Bit 11: Reset the input muxes */
#define SYSCON_PRESETCTRL0_IOCON (1 << 13) /* Bit 13: Reset the IOCON block */
#define SYSCON_PRESETCTRL0_GPIO0 (1 << 14) /* Bit 14: Reset the GPIO0 port registers */
#define SYSCON_PRESETCTRL0_GPIO1 (1 << 15) /* Bit 15: Reset the GPIO1 port registers */
#define SYSCON_PRESETCTRL0_GPIO2 (1 << 16) /* Bit 16: Reset the GPIO2 port registers */
#define SYSCON_PRESETCTRL0_GPIO3 (1 << 17) /* Bit 17: Reset the GPIO3 port registers */
#define SYSCON_PRESETCTRL0_PINT (1 << 18) /* Bit 18: Reset the pin interrupt block */
#define SYSCON_PRESETCTRL0_GINT (1 << 19) /* Bit 19: Reset the grouped pin interrupt block */
#define SYSCON_PRESETCTRL0_DMA (1 << 20) /* Bit 20: Reset the DMA controller */
#define SYSCON_PRESETCTRL0_CRC (1 << 21) /* Bit 21: Reset the CRC engine */
#define SYSCON_PRESETCTRL0_WWDT (1 << 22) /* Bit 22: Reset the Watchdog Timer */
#define SYSCON_PRESETCTRL0_RTC (1 << 23) /* Bit 23: Enables the bus clock for the RTC */
#define SYSCON_PRESETCTRL0_ADC0 (1 << 27) /* Bit 27: Reset the ADC0 register interface */
/* Peripheral reset control 2: PRESETCTRL1, PRESETCTRLSET1, and PRESETCTRLCLR1 */
#define SYSCON_PRESETCTRL1_MRT (1 << 0) /* Bit 0: Reset the Multi-Rate Timer */
#define SYSCON_PRESETCTRL1_SCT0 (1 << 2) /* Bit 2: Reset SCT0 */
#define SYSCON_PRESETCTRL1_MCAN0 (1 << 7) /* Bit 7: Reset MCAN0 */
#define SYSCON_PRESETCTRL1_MCAN1 (1 << 8) /* Bit 8: Reset MCAN1 */
#define SYSCON_PRESETCTRL1_UTICK (1 << 10) /* Bit 10: Reset the Micro-tick Timer */
#define SYSCON_PRESETCTRL1_FLEXCOMM0 (1 << 11) /* Bit 11: Reset Flexcomm Interface 0 */
#define SYSCON_PRESETCTRL1_FLEXCOMM1 (1 << 12) /* Bit 12: Reset Flexcomm Interface 1 */
#define SYSCON_PRESETCTRL1_FLEXCOMM2 (1 << 13) /* Bit 13: Reset Flexcomm Interface 2 */
#define SYSCON_PRESETCTRL1_FLEXCOMM3 (1 << 14) /* Bit 14: Reset Flexcomm Interface 3 */
#define SYSCON_PRESETCTRL1_FLEXCOMM4 (1 << 15) /* Bit 15: Reset Flexcomm Interface 4 */
#define SYSCON_PRESETCTRL1_FLEXCOMM5 (1 << 16) /* Bit 16: Reset Flexcomm Interface 5 */
#define SYSCON_PRESETCTRL1_FLEXCOMM6 (1 << 17) /* Bit 17: Reset Flexcomm Interface 6 */
#define SYSCON_PRESETCTRL1_FLEXCOMM7 (1 << 18) /* Bit 18: Reset Flexcomm Interface 7 */
#define SYSCON_PRESETCTRL1_DMIC (1 << 19) /* Bit 19: Reset the digital microphone interface */
#define SYSCON_PRESETCTRL1_CTIMER2 (1 << 22) /* Bit 22: Reset CTIMER 2 */
#define SYSCON_PRESETCTRL1_USB0D (1 << 25) /* Bit 25: Reset the USB0 device interface */
#define SYSCON_PRESETCTRL1_CTIMER0 (1 << 26) /* Bit 26: Reset timer CTIMER0 */
#define SYSCON_PRESETCTRL1_CTIMER1 (1 << 27) /* Bit 27: Reset timer CTIMER1 */
/* Peripheral reset control 2: PRESETCTRL2, PRESETCTRL2, and PRESETCTRLCLR2 */
#define SYSCON_PRESETCTRL2_LCD (1 << 2) /* Bit 2: Reset the LCD interface */
#define SYSCON_PRESETCTRL2_SDIO (1 << 3) /* Bit 3: Reset the SDIO interface */
#define SYSCON_PRESETCTRL2_USB1H (1 << 4) /* Bit 4: Reset the USB1 host interface */
#define SYSCON_PRESETCTRL2_USB1D (1 << 5) /* Bit 5: Reset the USB1 device interface */
#define SYSCON_PRESETCTRL2_USB1RAM (1 << 6) /* Bit 6: Reset the USB1 RAM interface */
#define SYSCON_PRESETCTRL2_EMC (1 << 7) /* Bit 7: Reset the EMC interface */
#define SYSCON_PRESETCTRL2_ETH (1 << 8) /* Bit 8: Reset the ethernet interface */
#define SYSCON_PRESETCTRL2_GPIO4 (1 << 9) /* Bit 9: Reset the GPIO4 interface */
#define SYSCON_PRESETCTRL2_GPIO5 (1 << 10) /* Bit 10: Reset the GPIO5 interface */
#define SYSCON_PRESETCTRL2_OTP (1 << 12) /* Bit 12: Reset the OTP interface */
#define SYSCON_PRESETCTRL2_RNG (1 << 13) /* Bit 13: Reset the RNG interface */
#define SYSCON_PRESETCTRL2_FLEXCOMM8 (1 << 14) /* Bit 14: Reset the Flexcomm Interface 8 */
#define SYSCON_PRESETCTRL2_FLEXCOMM9 (1 << 15) /* Bit 15: Reset the Flexcomm Interface 9 */
#define SYSCON_PRESETCTRL2_USB0HMR (1 << 16) /* Bit 16: Reset the USB host master interface */
#define SYSCON_PRESETCTRL2_USB0HSL (1 << 17) /* Bit 17: Reset the USB host slave interface */
#define SYSCON_PRESETCTRL2_SHA (1 << 18) /* Bit 18: Reset the SHA interface */
#define SYSCON_PRESETCTRL2_SC0 (1 << 19) /* Bit 19: Reset the Smart card0 interface */
#define SYSCON_PRESETCTRL2_SC1 (1 << 20) /* Bit 20: Reset the Smart card1 interface */
/* System reset status register */
#define SYSCON_SYSRSTSTAT_
@ -558,8 +603,8 @@
#define SYSCON_FRGCTRL_DIV_MASK (0xff << SYSCON_FRGCTRL_DIV_SHIFT)
# define SYSCON_FRGCTRL_DIV(n) ((uint32_t)((n)-1) << SYSCON_FRGCTRL_DIV_SHIFT)
#define SYSCON_FRGCTRL_MULT_SHIFT (8) /* Bit 8-15: Numerator of the fractional divider */
#define SYSCON_FRGCTRL_MULT_MASK (0xff << SYSCON_FRGCTRL_MULT_SHIFT)
# define SYSCON_FRGCTRL_MULT(n) ((uint32_t)(n) << SYSCON_FRGCTRL_MULT_SHIFT)
#define SYSCON_FRGCTRL_MULT_MASK (0xff << SYSCON_FRGCTRL_MULT_SHIFT)
# define SYSCON_FRGCTRL_MULT(n) ((uint32_t)(n) << SYSCON_FRGCTRL_MULT_SHIFT)
/* DMIC clock divider */
#define SYSCON_DMICCLKDIV_
@ -569,8 +614,16 @@
#define SYSCON_LCDCLKDIV_
/* SCT/PWM clock divider */
#define SYSCON_SCTCLKDIV_
/* EMC clock divider */
#define SYSCON_EMCCLKDIV_
#define SYSCON_EMCCLKDIV_DIV_SHIFT (9) /* Bits 0-7: Clock divider value */
#define SYSCON_EMCCLKDIV_DIV_MASK (0xff <<SYSCON_EMCCLKDIV_DIV_SHIFT)
# define SYSCON_EMCCLKDIV_DIV(n) ((uint32)((n)-1) <<SYSCON_EMCCLKDIV_DIV_SHIFT)
#define SYSCON_EMCCLKDIV_RESET (1 << 29) /* Bit 29: Resets the divider counter */
#define SYSCON_EMCCLKDIV_ HALT (1 << 30) /* Bit 30: Halts the divider counter */
#define SYSCON_EMCCLKDIV_REQFLAG (1 << 31) /* Bit 31: Divider status flag */
/* SDIO clock divider */
#define SYSCON_SDIOCLKDIV_
@ -605,8 +658,14 @@
#define SYSCON_USB1CLKCTRL_
/* USB1 clock status */
#define SYSCON_USB1CLKSTAT_
/* EMC system control */
#define SYSCON_EMCSYSCTRL_
#define SYSCON_EMCSYSCTRL_SC (1 << 0) /* Bit 0: EMC Shift Control */
#define SYSCON_EMCSYSCTRL_RD (1 << 1) /* Bit 1: EMC Reset Disable */
#define SYSCON_EMCSYSCTRL_BC (1 << 2) /* Bit 2: External Memory Controller burst control */
#define SYSCON_EMCSYSCTRL_FBCLKINSEL (1 << 3) /* Bit 3: External Memory Controller clock select */
/* EMC clock delay control */
#define SYSCON_EMCDLYCTRL_
/* EMC delay chain calibration control */

99
arch/arm/src/lpc54xx/lpc54_emc.c Normal file
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@ -0,0 +1,99 @@
/****************************************************************************
* arch/arm/src/lpc54/lpc54_clrpend.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Parts of this file were adapted from sample code provided for the LPC54xx
* family from NXP which has a compatible BSD license.
*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2016 - 2017 , NXP
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "up_arch.h"
#include "chip/lpc54_emc.h"
#include "lpc54_emc.h"
#ifdef CONFIG_LPC54_EMC
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: lpc54_emc_initialize
*
* Description:
* This function enables the EMC clock, initializes the emc system
* configuration, and enable the EMC module.
*
****************************************************************************/
void lpc54_emc_initialize(uintptr_t base,
FAR const struct emc_config_s *config)
{
uint32_t regval;
/* Enable EMC clock */
putreg32(SYSCON_AHBCLKCTRL2_EMC, LPC54_SYSCON_AHBCLKCTRLSET2);
/* Reset the EMC */
putreg32(SYSCON_PRESETCTRL2_EMC, LPC54_SYSCON_PRESETCTRLSET2);
putreg32(SYSCON_PRESETCTRL2_EMC, LPC54_SYSCON_PRESETCTRLCLR2);
/* Set the EMC sytem configure */
putreg32(SYSCON_EMCCLKDIV_DIV(config->clkdiv), LPC54_SYSCON_EMCCLKDIV);
regval = config->clksrc ? SYSCON_EMCSYSCTRL_FBCLKINSEL : 0;
putreg32(regval, LPC54_SYSCON_EMCSYSCTRL);
/* Set the endian mode */
regval = config->endian ? EMC_CONFIG_EM : 0;
putreg32(regval, LPC54_EMC_CONFIG);
/* Enable the EMC module with normal memory map mode and normal work mode. */
putreg32(EMC_CONTROL_E, LPC54_EMC_CONTROL);
}
#endif /* CONFIG_LPC54_EMC */

92
arch/arm/src/lpc54xx/lpc54_emc.h Normal file
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@ -0,0 +1,92 @@
/****************************************************************************
* arch/arm/src/lpc54xx/lpc54_emc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Parts of this file were adapted from sample code provided for the LPC54xx
* family from NXP which has a compatible BSD license.
*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2016 - 2017 , NXP
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_EMC_H
#define __ARCH_ARM_SRC_LPC54XX_LPC54_EMC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "lpc54_config.h"
#ifdef CONFIG_LPC54_EMC
/****************************************************************************
* Public Types
****************************************************************************/
/* EMC Feedback clock input source selection */
enum _emc_fbclk_src_e
{
EMC_INTLOOPBACK = 0, /* Use the internal loop back from EMC_CLK output */
EMC_FBCLLK /* Use the external EMC_FBCLK input */
};
/* EMC module basic configuration structure */
struct emc_config_s
{
bool bigendian; /* True: Memory is big-endian */
uint8_t clksrc; /* The feedback clock source. */
uint8_t clkdiv; /* EMC_CLK = AHB_CLK / (emc_clkDiv + 1). */
};
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: lpc54_emc_initialize
*
* Description:
* This function enables the EMC clock, initializes the emc system
* configuration, and enable the EMC module.
*
****************************************************************************/
void lpc54_emc_initialize(uintptr_t base,
FAR const struct emc_config_s *config);
#endif /* CONFIG_LPC54_EMC */
#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_EMC_H */

6
configs/lpcxpresso-lpc54628/src/lpc54_boot.c
View File

@ -65,6 +65,12 @@ void lpc54_board_initialize(void)
board_autoled_initialize();
#endif
#ifdef CONFIG_LPC54_EMC
/* Initialize SDRAM */
lpc54_sdram_initialize();
#endif
}
/****************************************************************************

94
configs/lpcxpresso-lpc54628/src/lpc54_sdram.c Normal file
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@ -0,0 +1,94 @@
/****************************************************************************
* configs/lpcxpresso-lpc54628/src/lpc54_bringup.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "lpc54_emc.h.h"
#include "lpcxpresso-lpc54628.h"
#include <arch/board/board.h>
#ifdef CONFIG_LPC54_EMC
/****************************************************************************
* Private Data
****************************************************************************/
/* EMC basic configuration. */
static const struct emc_config_s g_emc_config =
{
.bigendian = false, /* Little endian */
.clksrc = EMC_INTLOOPBACK; /* Internal loop back from EMC_CLK output */
#ifdef BOARD_220MHz
.clkdiv = 3; /* EMC Clock = CPU FREQ/3 */
#else /* if BOARD_180MHz */
.clkdiv = 2; /* EMC Clock = CPU FREQ/2 */
#endif
};
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: lpc54_sdram_initialize
*
* Description:
* Initialize external SDRAM
*
****************************************************************************/
void lpc54_sdram_initialize(void)
{
/* Dynamic memory timing configuration. */
#warning Missing logic
/* Dynamic memory chip specific configuration: Chip 0 - MTL48LC8M16A2B4-6A */
#warning Missing logic
/* EMC Basic configuration. */
lpc54_emc_initialize(EMC, &g_emc_config);
/* EMC Dynamc memory configuration. */
#warning Missing logic
}
#endif /* CONFIG_LPC54_EMC */

12
configs/lpcxpresso-lpc54628/src/lpcxpresso-lpc54628.h
View File

@ -99,5 +99,17 @@
int lpc54_bringup(void);
/****************************************************************************
* Name: lpc54_sdram_initialize
*
* Description:
* Initialize external SDRAM
*
****************************************************************************/
#ifdef CONFIG_LPC54_EMC
void lpc54_sdram_initialize(void);
#endif
#endif /* __ASSEMBLY__ */
#endif /* _CONFIGS_LPCXPRESSO_LPC54628_SRC_LPCXPRESSO_LPC54628_H */

22
configs/xmc4500-relax/README.txt
View File

@ -128,21 +128,21 @@ Configurations
CONFIG_UART0_2STOP=0
3. All of these configurations are set up to build under Windows using the
"GNU Tools for ARM Embedded Processors" that is maintained by ARM
(unless stated otherwise in the description of the configuration).
3. All of these configurations are set up to build under Windows using
the "GNU Tools for ARM Embedded Processors" that is maintained by
ARM (unless stated otherwise in the description of the configuration).
https://developer.arm.com/open-source/gnu-toolchain/gnu-rm
https://developer.arm.com/open-source/gnu-toolchain/gnu-rm
That toolchain selection can easily be reconfigured using
'make menuconfig'. Here are the relevant current settings:
That toolchain selection can easily be reconfigured using
'make menuconfig'. Here are the relevant current settings:
Build Setup:
CONFIG_HOST_WINDOWS=y : Window environment
CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows
Build Setup:
CONFIG_HOST_WINDOWS=y : Window environment
CONFIG_WINDOWS_CYGWIN=y : Cywin under Windows
System Type -> Toolchain:
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain
System Type -> Toolchain:
CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y : GNU ARM EABI toolchain
Configuration sub-directories
-----------------------------