diff --git a/arch/arm/src/common/arm_initialize.c b/arch/arm/src/common/arm_initialize.c
index 25d56955d4..b5962e0e36 100644
--- a/arch/arm/src/common/arm_initialize.c
+++ b/arch/arm/src/common/arm_initialize.c
@@ -68,11 +68,7 @@ static inline void up_color_intstack(void)
 #endif
   ssize_t size;
 
-#ifdef CONFIG_SMP
   for (size = ((CONFIG_ARCH_INTERRUPTSTACK & ~3) * CONFIG_SMP_NCPUS);
-#else
-  for (size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
-#endif
        size > 0;
        size -= sizeof(uint32_t))
     {
diff --git a/arch/arm/src/common/arm_internal.h b/arch/arm/src/common/arm_internal.h
index 9d78e24552..ec1076d2ba 100644
--- a/arch/arm/src/common/arm_internal.h
+++ b/arch/arm/src/common/arm_internal.h
@@ -29,6 +29,7 @@
 
 #ifndef __ASSEMBLY__
 #  include <nuttx/compiler.h>
+#  include <nuttx/arch.h>
 #  include <sys/types.h>
 #  include <stdint.h>
 #endif
@@ -194,21 +195,12 @@ extern "C"
  * CURRENT_REGS for portability.
  */
 
-#ifdef CONFIG_SMP
 /* For the case of architectures with multiple CPUs, then there must be one
  * such value for each processor that can receive an interrupt.
  */
 
-int up_cpu_index(void); /* See include/nuttx/arch.h */
 EXTERN volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-#  define CURRENT_REGS (g_current_regs[up_cpu_index()])
-
-#else
-
-EXTERN volatile uint32_t *g_current_regs[1];
-#  define CURRENT_REGS (g_current_regs[0])
-
-#endif
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
 
 /* This is the beginning of heap as provided from arm_head.S.
  * This is the first address in DRAM after the loaded
diff --git a/arch/arm/src/cxd56xx/cxd56_irq.c b/arch/arm/src/cxd56xx/cxd56_irq.c
index 4b9cfa7227..06e80b2190 100644
--- a/arch/arm/src/cxd56xx/cxd56_irq.c
+++ b/arch/arm/src/cxd56xx/cxd56_irq.c
@@ -72,15 +72,11 @@
  * CURRENT_REGS for portability.
  */
 
-#ifdef CONFIG_SMP
 /* For the case of configurations with multiple CPUs, then there must be one
  * such value for each processor that can receive an interrupt.
  */
 
 volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-#else
-volatile uint32_t *g_current_regs[1];
-#endif
 
 #ifdef CONFIG_SMP
 static volatile int8_t g_cpu_for_irq[CXD56_IRQ_NIRQS];
diff --git a/arch/arm/src/imx6/imx_irq.c b/arch/arm/src/imx6/imx_irq.c
index d746985e3b..18bd80e2a7 100644
--- a/arch/arm/src/imx6/imx_irq.c
+++ b/arch/arm/src/imx6/imx_irq.c
@@ -51,15 +51,11 @@
  * CURRENT_REGS for portability.
  */
 
-#ifdef CONFIG_SMP
 /* For the case of configurations with multiple CPUs, then there must be one
  * such value for each processor that can receive an interrupt.
  */
 
 volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-#else
-volatile uint32_t *g_current_regs[1];
-#endif
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
 /* In the SMP configuration, we will need custom IRQ and FIQ stacks.
diff --git a/arch/arm/src/lc823450/lc823450_dvfs2.c b/arch/arm/src/lc823450/lc823450_dvfs2.c
index fabc4c06ac..3b2e3bdeb1 100644
--- a/arch/arm/src/lc823450/lc823450_dvfs2.c
+++ b/arch/arm/src/lc823450/lc823450_dvfs2.c
@@ -55,10 +55,6 @@
 #define UP_THRESHOLD 20
 #define DN_THRESHOLD 60
 
-#ifndef CONFIG_SMP_NCPUS
-#  define CONFIG_SMP_NCPUS 1
-#endif
-
 #ifdef CONFIG_DVFS_CHANGE_VOLTAGE
 #  define CORE12V_PIN (GPIO_PORT2 | GPIO_PIN1)
 #endif
diff --git a/arch/arm/src/lc823450/lc823450_irq.c b/arch/arm/src/lc823450/lc823450_irq.c
index f49d2e2a90..03a301e8bc 100644
--- a/arch/arm/src/lc823450/lc823450_irq.c
+++ b/arch/arm/src/lc823450/lc823450_irq.c
@@ -75,15 +75,11 @@
  * Public Data
  ****************************************************************************/
 
-#ifdef CONFIG_SMP
 /* For the case of configurations with multiple CPUs, then there must be one
  * such value for each processor that can receive an interrupt.
  */
 
 volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-#else
-volatile uint32_t *g_current_regs[1];
-#endif
 
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
 /* In the SMP configuration, we will need two custom interrupt stacks.
diff --git a/arch/arm/src/lc823450/lc823450_procfs_dvfs.c b/arch/arm/src/lc823450/lc823450_procfs_dvfs.c
index 810ebc15ac..71d14b3090 100644
--- a/arch/arm/src/lc823450/lc823450_procfs_dvfs.c
+++ b/arch/arm/src/lc823450/lc823450_procfs_dvfs.c
@@ -59,10 +59,6 @@
 #  define MIN(a,b) ((a) < (b) ? (a) : (b))
 #endif
 
-#ifndef CONFIG_SMP_NCPUS
-#  define CONFIG_SMP_NCPUS 1
-#endif
-
 /****************************************************************************
  * Private Types
  ****************************************************************************/
diff --git a/arch/arm/src/rp2040/rp2040_irq.c b/arch/arm/src/rp2040/rp2040_irq.c
index 8cdd838279..3349012475 100644
--- a/arch/arm/src/rp2040/rp2040_irq.c
+++ b/arch/arm/src/rp2040/rp2040_irq.c
@@ -63,15 +63,11 @@
  * CURRENT_REGS for portability.
  */
 
-#ifdef CONFIG_SMP
 /* For the case of configurations with multiple CPUs, then there must be one
  * such value for each processor that can receive an interrupt.
  */
 
 volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-#else
-volatile uint32_t *g_current_regs[1];
-#endif
 
 #ifdef CONFIG_SMP
 extern void rp2040_send_irqreq(int irqreq);
diff --git a/arch/arm/src/rtl8720c/ameba_nvic.c b/arch/arm/src/rtl8720c/ameba_nvic.c
index 0366ba567f..2369cd400a 100644
--- a/arch/arm/src/rtl8720c/ameba_nvic.c
+++ b/arch/arm/src/rtl8720c/ameba_nvic.c
@@ -62,11 +62,8 @@
  * processing.  Access to g_current_regs[] must be through the macro
  * CURRENT_REGS for portability.
  */
-#ifdef CONFIG_SMP
+
 volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-#else
-volatile uint32_t *g_current_regs[1];
-#endif
 
 /* extern int32_t    __StackLimit; */
 
diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c
index 018e0c5112..3f27430c06 100644
--- a/arch/arm/src/sam34/sam_irq.c
+++ b/arch/arm/src/sam34/sam_irq.c
@@ -71,11 +71,7 @@
  * CURRENT_REGS for portability.
  */
 
-#ifdef CONFIG_SMP
 volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-#else
-volatile uint32_t *g_current_regs[1];
-#endif
 
 /* This is the address of the  exception vector table (determined by the
  * linker script).
diff --git a/arch/arm/src/samd5e5/sam_irq.c b/arch/arm/src/samd5e5/sam_irq.c
index 506038fa38..a364a1d4c8 100644
--- a/arch/arm/src/samd5e5/sam_irq.c
+++ b/arch/arm/src/samd5e5/sam_irq.c
@@ -71,11 +71,7 @@
  * CURRENT_REGS for portability.
  */
 
-#ifdef CONFIG_SMP
 volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-#else
-volatile uint32_t *g_current_regs[1];
-#endif
 
 /* This is the address of the  exception vector table (determined by the
  * linker script).
diff --git a/arch/ceva/src/common/up_doirq.c b/arch/ceva/src/common/up_doirq.c
index 101fe96b96..1bab68b323 100644
--- a/arch/ceva/src/common/up_doirq.c
+++ b/arch/ceva/src/common/up_doirq.c
@@ -39,11 +39,7 @@
  * CURRENT_REGS for portability.
  */
 
-#ifdef CONFIG_SMP
 uint32_t *volatile g_current_regs[CONFIG_SMP_NCPUS];
-#else
-uint32_t *volatile g_current_regs[1];
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/arch/ceva/src/common/up_internal.h b/arch/ceva/src/common/up_internal.h
index b4efc8baaf..1c03809c7b 100644
--- a/arch/ceva/src/common/up_internal.h
+++ b/arch/ceva/src/common/up_internal.h
@@ -28,6 +28,7 @@
 #include <nuttx/config.h>
 
 #ifndef __ASSEMBLY__
+#  include <nuttx/arch.h>
 #  include <sys/types.h>
 #  include <stdint.h>
 #endif
@@ -110,22 +111,12 @@ extern "C"
  * CURRENT_REGS for portability.
  */
 
-#ifdef CONFIG_SMP
 /* For the case of architectures with multiple CPUs, then there must be one
  * such value for each processor that can receive an interrupt.
  */
 
-int up_cpu_index(void); /* See include/nuttx/arch.h */
-
 EXTERN uint32_t *volatile g_current_regs[CONFIG_SMP_NCPUS];
-#  define CURRENT_REGS (g_current_regs[up_cpu_index()])
-
-#else
-
-EXTERN uint32_t *volatile g_current_regs[1];
-#  define CURRENT_REGS (g_current_regs[0])
-
-#endif
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
 
 /* This is the beginning of heap as provided from up_head.S.
  * This is the first address in DRAM after the loaded
diff --git a/arch/mips/src/common/mips_internal.h b/arch/mips/src/common/mips_internal.h
index 1de13199f1..79207cd9a3 100644
--- a/arch/mips/src/common/mips_internal.h
+++ b/arch/mips/src/common/mips_internal.h
@@ -26,6 +26,7 @@
  ****************************************************************************/
 
 #ifndef __ASSEMBLY__
+#  include <nuttx/arch.h>
 #  include <stdint.h>
 #  include <stdbool.h>
 #endif
@@ -94,21 +95,12 @@ typedef void (*up_vector_t)(void);
  * CURRENT_REGS for portability.
  */
 
-#ifdef CONFIG_SMP
 /* For the case of architectures with multiple CPUs, then there must be one
  * such value for each processor that can receive an interrupt.
  */
 
-int up_cpu_index(void); /* See include/nuttx/arch.h */
 extern volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-#  define CURRENT_REGS (g_current_regs[up_cpu_index()])
-
-#else
-
-extern volatile uint32_t *g_current_regs[1];
-#  define CURRENT_REGS (g_current_regs[0])
-
-#endif
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
 
 /* This is the beginning of heap as provided from up_head.S. This is the
  * first address in DRAM after the loaded program+bss+idle stack.  The end
diff --git a/arch/or1k/src/common/up_internal.h b/arch/or1k/src/common/up_internal.h
index e14dd2c7f1..311ffb2421 100644
--- a/arch/or1k/src/common/up_internal.h
+++ b/arch/or1k/src/common/up_internal.h
@@ -29,6 +29,7 @@
 
 #ifndef __ASSEMBLY__
 #  include <nuttx/compiler.h>
+#  include <nuttx/arch.h>
 #  include <sys/types.h>
 #  include <stdint.h>
 #endif
@@ -117,21 +118,12 @@ extern "C"
  * CURRENT_REGS for portability.
  */
 
-#ifdef CONFIG_SMP
 /* For the case of architectures with multiple CPUs, then there must be one
  * such value for each processor that can receive an interrupt.
  */
 
-int up_cpu_index(void); /* See include/nuttx/arch.h */
 EXTERN volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-#  define CURRENT_REGS (g_current_regs[up_cpu_index()])
-
-#else
-
-EXTERN volatile uint32_t *g_current_regs[1];
-#  define CURRENT_REGS (g_current_regs[0])
-
-#endif
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
 
 /* This is the beginning of heap as provided from up_head.S.
  * This is the first address in DRAM after the loaded
diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h
index 1e69f5b109..e020568a72 100644
--- a/arch/risc-v/src/common/riscv_internal.h
+++ b/arch/risc-v/src/common/riscv_internal.h
@@ -29,6 +29,7 @@
 
 #ifndef __ASSEMBLY__
 #  include <nuttx/compiler.h>
+#  include <nuttx/arch.h>
 #  include <sys/types.h>
 #  include <stdint.h>
 #endif
@@ -104,13 +105,8 @@ extern "C"
 #endif
 
 #ifndef __ASSEMBLY__
-#ifdef CONFIG_SMP
 EXTERN volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS];
-#  define CURRENT_REGS (g_current_regs[up_cpu_index()])
-#else
-EXTERN volatile uintptr_t *g_current_regs[1];
-#  define CURRENT_REGS (g_current_regs[0])
-#endif
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
 EXTERN uintptr_t g_idle_topstack;
 
 /* Address of the saved user stack pointer */
diff --git a/arch/risc-v/src/k210/k210_irq.c b/arch/risc-v/src/k210/k210_irq.c
index 61c08f95ef..4cf4431add 100644
--- a/arch/risc-v/src/k210/k210_irq.c
+++ b/arch/risc-v/src/k210/k210_irq.c
@@ -41,15 +41,11 @@
  * Public Data
  ****************************************************************************/
 
-#ifdef CONFIG_SMP
 /* For the case of configurations with multiple CPUs, then there must be one
  * such value for each processor that can receive an interrupt.
  */
 
 volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS];
-#else
-volatile uintptr_t *g_current_regs[1];
-#endif
 
 #ifdef CONFIG_SMP
 extern int riscv_pause_handler(int irq, void *c, void *arg);
@@ -83,11 +79,7 @@ void up_irqinitialize(void)
 
 #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15
   size_t intstack_size = 0;
-#ifndef CONFIG_SMP
-  intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~15);
-#else
   intstack_size = ((CONFIG_ARCH_INTERRUPTSTACK * CONFIG_SMP_NCPUS) & ~15);
-#endif
   riscv_stack_color((void *)&g_intstackalloc, intstack_size);
 #endif
 
diff --git a/arch/sim/src/sim/up_heap.c b/arch/sim/src/sim/up_heap.c
index 84b881c01d..196c6aa9d4 100644
--- a/arch/sim/src/sim/up_heap.c
+++ b/arch/sim/src/sim/up_heap.c
@@ -50,11 +50,7 @@ struct mm_delaynode_s
 
 struct mm_heap_s
 {
-#ifdef CONFIG_SMP
   struct mm_delaynode_s *mm_delaylist[CONFIG_SMP_NCPUS];
-#else
-  struct mm_delaynode_s *mm_delaylist[1];
-#endif
 
 #if defined(CONFIG_FS_PROCFS) && !defined(CONFIG_FS_PROCFS_EXCLUDE_MEMINFO)
   struct procfs_meminfo_entry_s mm_procfs;
diff --git a/arch/sim/src/sim/up_hostirq.c b/arch/sim/src/sim/up_hostirq.c
index 68173ad016..2e05b94f4e 100644
--- a/arch/sim/src/sim/up_hostirq.c
+++ b/arch/sim/src/sim/up_hostirq.c
@@ -33,11 +33,7 @@
  * Public Data
  ****************************************************************************/
 
-#ifdef CONFIG_SMP
 volatile void *g_current_regs[CONFIG_SMP_NCPUS];
-#else
-volatile void *g_current_regs[1];
-#endif
 
 /****************************************************************************
  * Private Types
diff --git a/arch/sim/src/sim/up_internal.h b/arch/sim/src/sim/up_internal.h
index 77391879ad..3d4db6248d 100644
--- a/arch/sim/src/sim/up_internal.h
+++ b/arch/sim/src/sim/up_internal.h
@@ -26,7 +26,7 @@
  ****************************************************************************/
 
 #ifdef __SIM__
-#include "config.h"
+#  include "config.h"
 #endif
 
 #ifndef __ASSEMBLY__
@@ -39,6 +39,10 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+#ifndef CONFIG_SMP_NCPUS
+#  define CONFIG_SMP_NCPUS 1
+#endif
+
 /* Determine which (if any) console driver to use */
 
 #ifndef CONFIG_DEV_CONSOLE
@@ -103,21 +107,12 @@ struct i2c_master_s;
  * CURRENT_REGS for portability.
  */
 
-#ifdef CONFIG_SMP
 /* For the case of architectures with multiple CPUs, then there must be one
  * such value for each processor that can receive an interrupt.
  */
 
-int up_cpu_index(void); /* See include/nuttx/arch.h */
 extern volatile void *g_current_regs[CONFIG_SMP_NCPUS];
-#  define CURRENT_REGS (g_current_regs[up_cpu_index()])
-
-#else
-
-extern volatile void *g_current_regs[1];
-#  define CURRENT_REGS (g_current_regs[0])
-
-#endif
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
 
 /* The command line  arguments passed to simulator */
 
diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h
index eb53489ba3..b20a52c941 100644
--- a/arch/xtensa/src/common/xtensa.h
+++ b/arch/xtensa/src/common/xtensa.h
@@ -28,6 +28,7 @@
 #include <nuttx/config.h>
 
 #ifndef __ASSEMBLY__
+#  include <nuttx/arch.h>
 #  include <stdint.h>
 #  include <sys/types.h>
 #  include <stdbool.h>
@@ -151,21 +152,12 @@
  * CURRENT_REGS for portability.
  */
 
-#ifdef CONFIG_SMP
 /* For the case of architectures with multiple CPUs, then there must be one
  * such value for each processor that can receive an interrupt.
  */
 
-int up_cpu_index(void); /* See include/nuttx/arch.h */
 extern volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
-#  define CURRENT_REGS (g_current_regs[up_cpu_index()])
-
-#else
-
-extern volatile uint32_t *g_current_regs[1];
-#  define CURRENT_REGS (g_current_regs[0])
-
-#endif
+#define CURRENT_REGS (g_current_regs[up_cpu_index()])
 
 #if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
 /* The (optional) interrupt stack */
diff --git a/arch/xtensa/src/common/xtensa_initialize.c b/arch/xtensa/src/common/xtensa_initialize.c
index de33c4c67e..4daacf8bfc 100644
--- a/arch/xtensa/src/common/xtensa_initialize.c
+++ b/arch/xtensa/src/common/xtensa_initialize.c
@@ -67,11 +67,7 @@ static inline void xtensa_color_intstack(void)
 #endif
   ssize_t size;
 
-#ifdef CONFIG_SMP
   for (size = INTSTACK_SIZE * CONFIG_SMP_NCPUS;
-#else
-  for (size = INTSTACK_SIZE;
-#endif
        size > 0; size -= sizeof(uint32_t))
     {
       *ptr++ = INTSTACK_COLOR;
@@ -104,20 +100,16 @@ static inline void xtensa_color_intstack(void)
 
 void up_initialize(void)
 {
-  xtensa_color_intstack();
-
-#ifdef CONFIG_SMP
   int i;
 
+  xtensa_color_intstack();
+
   /* Initialize global variables */
 
   for (i = 0; i < CONFIG_SMP_NCPUS; i++)
     {
       g_current_regs[i] = NULL;
     }
-#else
-  CURRENT_REGS = NULL;
-#endif
 
   /* Add any extra memory fragments to the memory manager */
 
diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c
index ea0eabe375..d12dcbc280 100644
--- a/arch/xtensa/src/esp32/esp32_gpio.c
+++ b/arch/xtensa/src/esp32/esp32_gpio.c
@@ -56,11 +56,7 @@
  ****************************************************************************/
 
 #ifdef CONFIG_ESP32_GPIO_IRQ
-#ifdef CONFIG_SMP
 static int g_gpio_cpuint[CONFIG_SMP_NCPUS];
-#else
-static int g_gpio_cpuint[1];
-#endif
 #endif
 
 static const uint8_t g_pin2func[40] =
diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c
index efd1c43861..0388b24df6 100644
--- a/arch/xtensa/src/esp32/esp32_irq.c
+++ b/arch/xtensa/src/esp32/esp32_irq.c
@@ -122,19 +122,12 @@
  * CURRENT_REGS for portability.
  */
 
-#ifdef CONFIG_SMP
 /* For the case of architectures with multiple CPUs, then there must be one
  * such value for each processor that can receive an interrupt.
  */
 
 volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS];
 
-#else
-
-volatile uint32_t *g_current_regs[1];
-
-#endif
-
 #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
 /* In the SMP configuration, we will need custom interrupt stacks.
  * These definitions provide the aligned stack allocations.
@@ -170,11 +163,7 @@ static volatile uint8_t g_irqmap[NR_IRQS];
  * content.
  */
 
-#ifdef CONFIG_SMP
 static uint32_t g_intenable[CONFIG_SMP_NCPUS];
-#else
-static uint32_t g_intenable[1];
-#endif
 
 /* Bitsets for free, unallocated CPU interrupts available to peripheral
  * devices.
@@ -530,11 +519,7 @@ void up_disable_irq(int irq)
     }
 
   DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX);
-#ifdef CONFIG_SMP
   DEBUGASSERT(cpu >= 0 && cpu <= CONFIG_SMP_NCPUS);
-#else
-  DEBUGASSERT(cpu == 0);
-#endif
 
   if (irq < XTENSA_NIRQ_INTERNAL)
     {
@@ -595,11 +580,7 @@ void up_enable_irq(int irq)
   int cpuint = IRQ_GETCPUINT(g_irqmap[irq]);
 
   DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX);
-#ifdef CONFIG_SMP
   DEBUGASSERT(cpu >= 0 && cpu <= CONFIG_SMP_NCPUS);
-#else
-  DEBUGASSERT(cpu == 0);
-#endif
 
   if (irq < XTENSA_NIRQ_INTERNAL)
     {
diff --git a/arch/xtensa/src/esp32/esp32_spiflash.c b/arch/xtensa/src/esp32/esp32_spiflash.c
index e0a1a7bf87..ba44ea26c7 100644
--- a/arch/xtensa/src/esp32/esp32_spiflash.c
+++ b/arch/xtensa/src/esp32/esp32_spiflash.c
@@ -61,10 +61,6 @@
 
 /* Used in spiflash_cachestate_s structure even when SMP is disabled. */
 
-#ifndef CONFIG_SMP_NCPUS
-#  define CONFIG_SMP_NCPUS 1
-#endif
-
 #define SPI_FLASH_WRITE_BUF_SIZE    (32)
 #define SPI_FLASH_READ_BUF_SIZE     (64)
 
diff --git a/fs/procfs/fs_procfscritmon.c b/fs/procfs/fs_procfscritmon.c
index b17d1079df..fa40c72944 100644
--- a/fs/procfs/fs_procfscritmon.c
+++ b/fs/procfs/fs_procfscritmon.c
@@ -258,9 +258,7 @@ static ssize_t critmon_read(FAR struct file *filep, FAR char *buffer,
   FAR struct critmon_file_s *attr;
   off_t offset;
   ssize_t ret;
-#ifdef CONFIG_SMP
   int cpu;
-#endif
 
   finfo("buffer=%p buflen=%d\n", buffer, (int)buflen);
 
@@ -272,7 +270,6 @@ static ssize_t critmon_read(FAR struct file *filep, FAR char *buffer,
   ret    = 0;
   offset = filep->f_pos;
 
-#ifdef CONFIG_SMP
   /* Get the status for each CPU  */
 
   for (cpu = 0; cpu < CONFIG_SMP_NCPUS; cpu++)
@@ -289,12 +286,6 @@ static ssize_t critmon_read(FAR struct file *filep, FAR char *buffer,
       offset += nbytes;
     }
 
-#else
-  /* Get status for the single CPU */
-
-  ret = critmon_read_cpu(attr, buffer + ret, buflen -ret, &offset, 0);
-#endif
-
   if (ret > 0)
     {
       filep->f_pos += ret;
diff --git a/include/nuttx/sched.h b/include/nuttx/sched.h
index 09c5109eb3..bee03da488 100644
--- a/include/nuttx/sched.h
+++ b/include/nuttx/sched.h
@@ -807,13 +807,8 @@ extern "C"
 #ifdef CONFIG_SCHED_CRITMONITOR
 /* Maximum time with pre-emption disabled or within critical section. */
 
-#ifdef CONFIG_SMP_NCPUS
 EXTERN uint32_t g_premp_max[CONFIG_SMP_NCPUS];
 EXTERN uint32_t g_crit_max[CONFIG_SMP_NCPUS];
-#else
-EXTERN uint32_t g_premp_max[1];
-EXTERN uint32_t g_crit_max[1];
-#endif
 #endif /* CONFIG_SCHED_CRITMONITOR */
 
 #ifdef CONFIG_DEBUG_TCBINFO
diff --git a/include/sys/types.h b/include/sys/types.h
index 0c1f9b3ebc..c06d57b20a 100644
--- a/include/sys/types.h
+++ b/include/sys/types.h
@@ -60,6 +60,10 @@
 #  endif
 #endif
 
+#ifndef CONFIG_SMP_NCPUS
+#  define CONFIG_SMP_NCPUS 1
+#endif
+
 /* Scheduling Priorities.
  *
  * NOTES:
@@ -244,7 +248,6 @@ typedef uint32_t     clock_t;
 typedef uint32_t     useconds_t;
 typedef int32_t      suseconds_t;
 
-#ifdef CONFIG_SMP
 /* This is the smallest integer type that will hold a bitset of all CPUs */
 
 #if (CONFIG_SMP_NCPUS <= 8)
@@ -256,9 +259,6 @@ typedef volatile uint32_t cpu_set_t;
 #else
 #  error SMP: Extensions needed to support this number of CPUs
 #endif
-#else
-typedef volatile uint8_t cpu_set_t;
-#endif /* CONFIG_SMP */
 
 /* BSD types provided only to support porting to NuttX. */
 
diff --git a/libs/libc/unistd/lib_sysconf.c b/libs/libc/unistd/lib_sysconf.c
index 0ace24d78f..a35c1b7604 100644
--- a/libs/libc/unistd/lib_sysconf.c
+++ b/libs/libc/unistd/lib_sysconf.c
@@ -222,11 +222,7 @@ long sysconf(int name)
 
       case _SC_NPROCESSORS_CONF:
       case _SC_NPROCESSORS_ONLN:
-#ifdef CONFIG_SMP_NCPUS
         return CONFIG_SMP_NCPUS;
-#else
-        return 1;
-#endif
 
       case _SC_MONOTONIC_CLOCK:
 #ifdef CONFIG_CLOCK_MONOTONIC
diff --git a/mm/mm_heap/mm.h b/mm/mm_heap/mm.h
index a68775ed82..5c7d727522 100644
--- a/mm/mm_heap/mm.h
+++ b/mm/mm_heap/mm.h
@@ -202,11 +202,7 @@ struct mm_heap_s
    * immdiately.
    */
 
-#ifdef CONFIG_SMP
   FAR struct mm_delaynode_s *mm_delaylist[CONFIG_SMP_NCPUS];
-#else
-  FAR struct mm_delaynode_s *mm_delaylist[1];
-#endif
 
 #if defined(CONFIG_FS_PROCFS) && !defined(CONFIG_FS_PROCFS_EXCLUDE_MEMINFO)
   struct procfs_meminfo_entry_s mm_procfs;
diff --git a/sched/init/nx_start.c b/sched/init/nx_start.c
index 9ea049e8c0..a5ce3bbe0b 100644
--- a/sched/init/nx_start.c
+++ b/sched/init/nx_start.c
@@ -62,10 +62,6 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-#ifndef CONFIG_SMP_NCPUS
-#  define CONFIG_SMP_NCPUS       1
-#endif
-
 /* This set of all CPUs */
 
 #define SCHED_ALL_CPUS           ((1 << CONFIG_SMP_NCPUS) - 1)
diff --git a/sched/sched/sched.h b/sched/sched/sched.h
index 4543a2a1ae..3735663895 100644
--- a/sched/sched/sched.h
+++ b/sched/sched/sched.h
@@ -155,6 +155,7 @@ extern volatile dq_queue_t g_readytorun;
  */
 
 extern volatile dq_queue_t g_assignedtasks[CONFIG_SMP_NCPUS];
+#endif
 
 /* g_running_tasks[] holds a references to the running task for each cpu.
  * It is valid only when up_interrupt_context() returns true.
@@ -162,12 +163,6 @@ extern volatile dq_queue_t g_assignedtasks[CONFIG_SMP_NCPUS];
 
 extern FAR struct tcb_s *g_running_tasks[CONFIG_SMP_NCPUS];
 
-#else
-
-extern FAR struct tcb_s *g_running_tasks[1];
-
-#endif
-
 /* This is the list of all tasks that are ready-to-run, but cannot be placed
  * in the g_readytorun list because:  (1) They are higher priority than the
  * currently active task at the head of the g_readytorun list, and (2) the
diff --git a/sched/sched/sched_cpuload.c b/sched/sched/sched_cpuload.c
index de841de8eb..03088251d1 100644
--- a/sched/sched/sched_cpuload.c
+++ b/sched/sched/sched_cpuload.c
@@ -56,16 +56,10 @@
  * will be incremented multiple times per tick.
  */
 
-#ifdef CONFIG_SMP
-#  define CPULOAD_TIMECONSTANT \
+#define CPULOAD_TIMECONSTANT \
      (CONFIG_SMP_NCPUS * \
       CONFIG_SCHED_CPULOAD_TIMECONSTANT * \
       CPULOAD_TICKSPERSEC)
-#else
-#  define CPULOAD_TIMECONSTANT \
-     (CONFIG_SCHED_CPULOAD_TIMECONSTANT * \
-      CPULOAD_TICKSPERSEC)
-#endif
 
 /****************************************************************************
  * Private Data
@@ -157,19 +151,11 @@ void weak_function nxsched_process_cpuload(void)
 
   flags = enter_critical_section();
 
-#ifdef CONFIG_SMP
   for (i = 0; i < CONFIG_SMP_NCPUS; i++)
     {
       nxsched_cpu_process_cpuload(i);
     }
 
-#else
-  /* Perform scheduler operations on the single CPU. */
-
-  nxsched_cpu_process_cpuload(0);
-
-#endif
-
   /* If the accumulated tick value exceed a time constant, then shift the
    * accumulators and recalculate the total.
    */
diff --git a/sched/sched/sched_critmonitor.c b/sched/sched/sched_critmonitor.c
index 76a1656456..0fa2fb3a7c 100644
--- a/sched/sched/sched_critmonitor.c
+++ b/sched/sched/sched_critmonitor.c
@@ -102,13 +102,8 @@
 
 /* Start time when pre-emption disabled or critical section entered. */
 
-#ifdef CONFIG_SMP_NCPUS
 static uint32_t g_premp_start[CONFIG_SMP_NCPUS];
 static uint32_t g_crit_start[CONFIG_SMP_NCPUS];
-#else
-static uint32_t g_premp_start[1];
-static uint32_t g_crit_start[1];
-#endif
 
 /****************************************************************************
  * Public Data
@@ -116,13 +111,8 @@ static uint32_t g_crit_start[1];
 
 /* Maximum time with pre-emption disabled or within critical section. */
 
-#ifdef CONFIG_SMP_NCPUS
 uint32_t g_premp_max[CONFIG_SMP_NCPUS];
 uint32_t g_crit_max[CONFIG_SMP_NCPUS];
-#else
-uint32_t g_premp_max[1];
-uint32_t g_crit_max[1];
-#endif
 
 /****************************************************************************
  * Public Functions
diff --git a/sched/sched/sched_note.c b/sched/sched/sched_note.c
index 7406e72045..aeaaa2fd18 100644
--- a/sched/sched/sched_note.c
+++ b/sched/sched/sched_note.c
@@ -100,11 +100,7 @@ static struct note_filter_s g_note_filter =
 };
 
 #ifdef CONFIG_SCHED_INSTRUMENTATION_IRQHANDLER
-#ifdef CONFIG_SMP
 static unsigned int g_note_disabled_irq_nest[CONFIG_SMP_NCPUS];
-#else
-static unsigned int g_note_disabled_irq_nest[1];
-#endif
 #endif
 #endif