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Add a skeleton configuration that will eventually support the SAM4L Xplained Pro board

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This commit is contained in:
Gregory Nutt 2013-06-03 15:11:56 -06:00
parent 9e8ed732da
commit 77f84ae94d
6 changed files with 229 additions and 9 deletions
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8
arch/arm/Kconfig
View File

@ -46,6 +46,7 @@ config ARCH_CHIP_KINETIS
bool "Freescale Kinetis"
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
select ARCH_HAVE_FPU
select ARCH_HAVE_RAMFUNCS
select ARCH_RAMFUNCS
---help---
@ -100,6 +101,7 @@ config ARCH_CHIP_LPC43XX
select ARCH_HAVE_CMNVECTOR
select ARMV7M_CMNVECTOR
select ARCH_HAVE_MPU
select ARCH_HAVE_FPU
---help---
NPX LPC43XX architectures (ARM Cortex-M4).
@ -205,10 +207,14 @@ config ARMV7M_CMNVECTOR
logic or the common vector logic. This applies only to ARMv7-M
architectures.
config ARCH_HAVE_FPU
bool
default n
config ARCH_FPU
bool "FPU support"
default y
depends on ARCH_CORTEXM4
depends on ARCH_HAVE_FPU
---help---
Build in support for the ARM Cortex-M4 Floating Point Unit (FPU).
Check your chip specifications first; not all Cortex-M4 chips support the FPU.

51
arch/arm/include/sam34/chip.h
View File

@ -118,7 +118,8 @@
* Packages TQFP/VFBGA TQFP/QFN TQFP/QFN
*/
#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LC2)
#elif defined(CONFIG_ARCH_CHIP_ATSAM4LC2C) || defined (CONFIG_ARCH_CHIP_ATSAM4LC2B) || \
defined(CONFIG_ARCH_CHIP_ATSAM4LC2A)
/* Internal memory */
@ -137,7 +138,8 @@
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LC4)
#elif defined(CONFIG_ARCH_CHIP_ATSAM4LC4C) || defined (CONFIG_ARCH_CHIP_ATSAM4LC4B) || \
defined(CONFIG_ARCH_CHIP_ATSAM4LC4A)
/* Internal memory */
@ -156,7 +158,8 @@
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LS2)
#elif defined(CONFIG_ARCH_CHIP_ATSAM4LS2C) || defined (CONFIG_ARCH_CHIP_ATSAM4LS2B) || \
defined(CONFIG_ARCH_CHIP_ATSAM4LS2A)
/* Internal memory */
@ -175,7 +178,8 @@
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LS4)
#elif defined(CONFIG_ARCH_CHIP_ATSAM4LS4C) || defined (CONFIG_ARCH_CHIP_ATSAM4LS4B) || \
defined(CONFIG_ARCH_CHIP_ATSAM4LS4A)
/* Internal memory */
@ -194,6 +198,45 @@
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
/* AT91SAM4S Family *****************************************************************/
/*
* FEATURE SAM4SD32C SAM4SD32B SAM4SD16C SAM4SD16B SAM4SA16C SAM4SA16B SAM4S16C SAM4S16B SAM4S8C SAM4S8B
* Flash 2x1MB 2x1MB 2x512KB 1x1MB 1x1MB 1x1MB 1x1MB 1x1MB 1x512KB 1x512KB
* SRAM 160KB 160KB 160KB 160KB 160KB 160KB 128KB 128KB 128KB 128KB
* HCACHE 2KB 2KB 2KB 2KB 2KB 2KB - - - -
* Pins 100 64 100 64 100 64 100 64 100 64
* No. PIOs 79 47 79 47 79 47 79 47 79 47
* Ext. BUS Yes No Yes No Yes No Yes No Yes No
* 12-bit ADC 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch
* 12-bit DAC 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch
* Timer Counter 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch
* PDC 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch
* USART 2 2 2 2 2 2 2 2 2 2
* UART 2 2 2 2 2 2 2 2 2 2
* HSMCI Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
*/
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD32C)
# error To be provided
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD32B)
# error To be provided
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD16C)
# error To be provided
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD16B)
# error To be provided
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SA16C)
# error To be provided
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SA16B)
# error To be provided
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S16C)
# error To be provided
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S16B)
# error To be provided
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S8C)
# error To be provided
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S8B)
# error To be provided
#else
# error "Unknown SAM3/4 chip type"
#endif

1
arch/arm/src/lm/Kconfig
View File

@ -40,6 +40,7 @@ config ARCH_CHIP_LM4F120
bool "LM4F120"
select ARCH_CORTEXM4
select ARCH_CHIP_LM4F
select ARCH_HAVE_FPU
endchoice

119
arch/arm/src/sam34/Kconfig
View File

@ -15,10 +15,129 @@ config ARCH_CHIP_AT91SAM3U4E
select ARCH_CORTEXM3
select ARCH_CHIP_SAM3U
config ARCH_CHIP_SAM34_NDMACHANC2C
bool "ATSAM4LC2C"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4L
config ARCH_CHIP_ATSAM4LC2B
bool "ATSAM4LC2B"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4L
config ARCH_CHIP_ATSAM4LC2A
bool "ATSAM4LC2A"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4L
config ARCH_CHIP_ATSAM4LC4C
bool "ATSAM4LC4C"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4L
config ARCH_CHIP_ATSAM4LC4B
bool "ATSAM4LC4B"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4L
config ARCH_CHIP_ATSAM4LC4A
bool "ATSAM4LC4A"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4L
config ARCH_CHIP_ATSAM4LS2C
bool "ATSAM4LS2C"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4L
config ARCH_CHIP_ATSAM4LS2B
bool "ATSAM4LS2B"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4L
config ARCH_CHIP_ATSAM4LS2A
bool "ATSAM4LS2A"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4L
config ARCH_CHIP_ATSAM4LS4C
bool "ATSAM4LS4C"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4L
config ARCH_CHIP_ATSAM4LS4B
bool "ATSAM4LS4B"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4L
config ARCH_CHIP_ATSAM4LS4A
bool "ATSAM4LS4A"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4L
config CONFIG_ARCH_CHIP_ATSAM4SD32C
bool "ATSAM4SD32C"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4S
config CONFIG_ARCH_CHIP_ATSAM4SD32B
bool "ATSAM4SD32B"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4S
config CONFIG_ARCH_CHIP_ATSAM4SD16C
bool "ATSAM4SD16C"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4S
config CONFIG_ARCH_CHIP_ATSAM4SD16B
bool "ATSAM4SD16B"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4S
config CONFIG_ARCH_CHIP_ATSAM4SA16C
bool "ATSAM4SA16C"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4S
config CONFIG_ARCH_CHIP_ATSAM4SA16B
bool "ATSAM4SA16B"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4S
config CONFIG_ARCH_CHIP_ATSAM4S16C
bool "ATSAM4S16C"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4S
config CONFIG_ARCH_CHIP_ATSAM4S16B
bool "ATSAM4S16B"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4S
config CONFIG_ARCH_CHIP_ATSAM4S8C
bool "ATSAM4S8C"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4S
config CONFIG_ARCH_CHIP_ATSAM4S8B
bool "ATSAM4S8B"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4S
endchoice
config ARCH_CHIP_SAM3U
bool
default n
config ARCH_CHIP_SAM4L
bool
default n
config ARCH_CHIP_SAM4S
bool
default n
menu "AT91SAM3 Peripheral Support"

35
arch/arm/src/sam34/chip/sam_chipid.h
View File

@ -51,13 +51,13 @@
/* CHIPID register offsets **************************************************************/
#define SAM_CHIPID_CIDR 0x00 /* Chip ID Register */
#define SAM_CHIPID_EXID 0x04 /* Chip ID Extension Register */
#define SAM_CHIPID_CIDR 0x00 /* Chip ID Register */
#define SAM_CHIPID_EXID 0x04 /* Chip ID Extension Register */
/* CHIPID register adresses *************************************************************/
#define SAM_CHIPID_CIDR (SAM_CHIPID_BASE+SAM_CHIPID_CIDR)
#define SAM_CHIPID_EXID (SAM_CHIPID_BASE+SAM_CHIPID_EXID)
#define SAM_CHIPID_CIDR (SAM_CHIPID_BASE+SAM_CHIPID_CIDR)
#define SAM_CHIPID_EXID (SAM_CHIPID_BASE+SAM_CHIPID_EXID)
/* CHIPID register bit definitions ******************************************************/
@ -70,6 +70,8 @@
# define CHIPID_CIDR_EPROC_CORTEXM3 (3 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-M3 */
# define CHIPID_CIDR_EPROC_ARM920T (4 << CHIPID_CIDR_EPROC_SHIFT) /* ARM920T */
# define CHIPID_CIDR_EPROC_ARM926EJS (5 << CHIPID_CIDR_EPROC_SHIFT) /* ARM926EJ-S */
# define CHIPID_CIDR_EPROC_CORTEXA5 (6 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-A5 */
# define CHIPID_CIDR_EPROC_CORTEXM4 (7 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-M4 */
#define CHIPID_CIDR_NVPSIZ_SHIFT (8) /* Bits 8-11: Nonvolatile Program Memory Size */
#define CHIPID_CIDR_NVPSIZ_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT)
# define CHIPID_CIDR_NVPSIZ_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */
@ -101,6 +103,7 @@
# define CHIPID_CIDR_SRAMSIZ_2KB (2 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 2K bytes */
# define CHIPID_CIDR_SRAMSIZ_6KB (3 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 6K bytes */
# define CHIPID_CIDR_SRAMSIZ_112KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 112K bytes */
# define CHIPID_CIDR_SRAMSIZ_24KB (4 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 24K bytes */
# define CHIPID_CIDR_SRAMSIZ_4KB (5 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 4K bytes */
# define CHIPID_CIDR_SRAMSIZ_80KB (6 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 80K bytes */
# define CHIPID_CIDR_SRAMSIZ_160KB (7 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 160K bytes */
@ -142,6 +145,13 @@
# define CHIPID_CIDR_ARCH_SAM3SXB (0x89 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxB Series (64-pin version) */
# define CHIPID_CIDR_ARCH_SAM3SXC (0x8a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SxC Series (100-pin version) */
# define CHIPID_CIDR_ARCH_AT91X92 (0x92 << CHIPID_CIDR_ARCH_SHIFT) /* AT91x92 Series */
# define CHIPID_CIDR_ARCH_SAM3NXA (0x93 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxA Series (48-pin version) */
# define CHIPID_CIDR_ARCH_SAM3NXB (0x94 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxB Series (64-pin version) */
# define CHIPID_CIDR_ARCH_SAM3NxC (0x95 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3NxC Series (100-pin version) */
# define CHIPID_CIDR_ARCH_SAM3NXC (0x99 << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SDxB SAM3SDxB Series (64-pin version) */
# define CHIPID_CIDR_ARCH_SAM3SDXC (0x9a << CHIPID_CIDR_ARCH_SHIFT) /* SAM3SDxC Series (100-pin version) */
# define CHIPID_CIDR_ARCH_SAM5A (0xa5 << CHIPID_CIDR_ARCH_SHIFT) /* SAM5A */
# define CHIPID_CIDR_ARCH_SAM4L (0xb0 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4Lxx Series */
# define CHIPID_CIDR_ARCH_AT75CXX (0xf0 << CHIPID_CIDR_ARCH_SHIFT) /* AT75Cxx Series */
#define CHIPID_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */
#define CHIPID_CIDR_NVPTYP_MASK (7 << CHIPID_CIDR_NVPTYP_SHIFT)
@ -152,6 +162,23 @@
# define CHIPID_CIDR_NVPTYP REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */
#define CHIPID_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */
/* Chip ID Extension Register */
#ifdef CONFIG_ARCH_CHIP_SAM4L
# define CHIPID_EXID_AES (1 << 0) /* Bit 0: AES Option */
# define CHIPID_EXID_USB (1 << 1) /* Bit 1: USB Configuration */
# define CHIPID_EXID_USBFULL (1 << 2) /* Bit 2: USB Option */
# define CHIPID_EXID_LCD (1 << 3) /* Bit 3: LCD Option */
# define CHIPID_EXID_PACKAGE_SHIFT (24) /* Bits 24-26: Package Type */
# define CHIPID_EXID_PACKAGE_MASK (7 << CHIPID_EXID_PACKAGE_SHIFT)
# define CHIPID_EXID_PACKAGE_24PIN (0 << CHIPID_EXID_PACKAGE_SHIFT) /* 24-pin package */
# define CHIPID_EXID_PACKAGE_32PIN (1 << CHIPID_EXID_PACKAGE_SHIFT) /* 32-pin package */
# define CHIPID_EXID_PACKAGE_48PIN (2 << CHIPID_EXID_PACKAGE_SHIFT) /* 48-pin package */
# define CHIPID_EXID_PACKAGE_64PIN (3 << CHIPID_EXID_PACKAGE_SHIFT) /* 64-pin package */
# define CHIPID_EXID_PACKAGE_100PIN (4 << CHIPID_EXID_PACKAGE_SHIFT) /* 100-pin package */
# define CHIPID_EXID_PACKAGE_144PIN (5 << CHIPID_EXID_PACKAGE_SHIFT) /* 144-pin package */
#endif
/****************************************************************************************
* Public Types
****************************************************************************************/

24
arch/arm/src/stm32/Kconfig
View File

@ -304,124 +304,148 @@ config ARCH_CHIP_STM32F302CB
bool "STM32F302CB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F302CC
bool "STM32F302CC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F302RB
bool "STM32F302RB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F302RC
bool "STM32F302RC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F302VB
bool "STM32F302VB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F302VC
bool "STM32F302VC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303CB
bool "STM32F303CB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303CC
bool "STM32F303CC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303RB
bool "STM32F303RB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303RC
bool "STM32F303RC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303VB
bool "STM32F303VB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F303VC
bool "STM32F303VC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F405RG
bool "STM32F405RG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F405VG
bool "STM32F405VG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F405ZG
bool "STM32F405ZG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407VE
bool "STM32F407VE"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407VG
bool "STM32F407VG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407ZE
bool "STM32F407ZE"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407ZG
bool "STM32F407ZG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407IE
bool "STM32F407IE"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F407IG
bool "STM32F407IG"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F427V
bool "STM32F427V"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F427
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F427Z
bool "STM32F427Z"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F427
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F427I
bool "STM32F427I"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F427
select ARCH_HAVE_FPU
endchoice