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Fixes timer interrupts

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3071 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-11-03 00:38:55 +00:00
parent e977b06239
commit 780464c28d
3 changed files with 60 additions and 47 deletions
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78
arch/avr/include/at32uc3/irq.h
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@ -162,116 +162,116 @@
/* Group 3 */ /* Group 3 */
#define AVR32_IRQ_BASEIRQGRP3 39 #define AVR32_IRQ_BASEIRQGRP3 39
#define AVR32_IRQ_NREQGRP3 6 #define AVR32_IRQ_NREQGRP3 7
#define AVR32_IRQ_PDCA0 40 /* 0 Peripheral DMA Controller 0 */ #define AVR32_IRQ_PDCA0 39 /* 0 Peripheral DMA Controller 0 */
#define AVR32_IRQ_PDCA1 41 /* 1 Peripheral DMA Controller 1 */ #define AVR32_IRQ_PDCA1 40 /* 1 Peripheral DMA Controller 1 */
#define AVR32_IRQ_PDCA2 42 /* 2 Peripheral DMA Controller 2 */ #define AVR32_IRQ_PDCA2 41 /* 2 Peripheral DMA Controller 2 */
#define AVR32_IRQ_PDCA3 43 /* 3 Peripheral DMA Controller 3 */ #define AVR32_IRQ_PDCA3 42 /* 3 Peripheral DMA Controller 3 */
#define AVR32_IRQ_PDCA4 44 /* 4 Peripheral DMA Controller 4 */ #define AVR32_IRQ_PDCA4 43 /* 4 Peripheral DMA Controller 4 */
#define AVR32_IRQ_PDCA5 45 /* 5 Peripheral DMA Controller 5 */ #define AVR32_IRQ_PDCA5 44 /* 5 Peripheral DMA Controller 5 */
#define AVR32_IRQ_PDCA6 46 /* 6 Peripheral DMA Controller 6 */ #define AVR32_IRQ_PDCA6 45 /* 6 Peripheral DMA Controller 6 */
/* Group 4 */ /* Group 4 */
#define AVR32_IRQ_BASEIRQGRP4 47 #define AVR32_IRQ_BASEIRQGRP4 46
#define AVR32_IRQ_NREQGRP4 1 #define AVR32_IRQ_NREQGRP4 1
#define AVR32_IRQ_FLASHC 47 /* 0 Flash Controller */ #define AVR32_IRQ_FLASHC 46 /* 0 Flash Controller */
/* Group 5 */ /* Group 5 */
#define AVR32_IRQ_BASEIRQGRP5 48 #define AVR32_IRQ_BASEIRQGRP5 47
#define AVR32_IRQ_NREQGRP5 1 #define AVR32_IRQ_NREQGRP5 1
#define AVR32_IRQ_USART0 48 /* 0 Universal Synchronous/Asynchronous #define AVR32_IRQ_USART0 47 /* 0 Universal Synchronous/Asynchronous
* Receiver/Transmitter 0 */ * Receiver/Transmitter 0 */
/* Group 6 */ /* Group 6 */
#define AVR32_IRQ_BASEIRQGRP6 49 #define AVR32_IRQ_BASEIRQGRP6 48
#define AVR32_IRQ_NREQGRP6 1 #define AVR32_IRQ_NREQGRP6 1
#define AVR32_IRQ_USART1 49 /* 0 Universal Synchronous/Asynchronous #define AVR32_IRQ_USART1 48 /* 0 Universal Synchronous/Asynchronous
* Receiver/Transmitter 1 */ * Receiver/Transmitter 1 */
/* Group 7 */ /* Group 7 */
#define AVR32_IRQ_BASEIRQGRP7 50 #define AVR32_IRQ_BASEIRQGRP7 49
#define AVR32_IRQ_NREQGRP7 1 #define AVR32_IRQ_NREQGRP7 1
#define AVR32_IRQ_USART2 50 /* 0 Universal Synchronous/Asynchronous #define AVR32_IRQ_USART2 49 /* 0 Universal Synchronous/Asynchronous
* Receiver/Transmitter 2 */ * Receiver/Transmitter 2 */
#define AVR32_IRQ_BASEIRQGRP8 51 #define AVR32_IRQ_BASEIRQGRP8 50
#define AVR32_IRQ_NREQGRP8 0 #define AVR32_IRQ_NREQGRP8 0
/* Group 9 */ /* Group 9 */
#define AVR32_IRQ_BASEIRQGRP9 51 #define AVR32_IRQ_BASEIRQGRP9 50
#define AVR32_IRQ_NREQGRP9 1 #define AVR32_IRQ_NREQGRP9 1
#define AVR32_IRQ_SPI 51 /* 0 Serial Peripheral Interface */ #define AVR32_IRQ_SPI 50 /* 0 Serial Peripheral Interface */
#define AVR32_IRQ_BASEIRQGRP10 52 #define AVR32_IRQ_BASEIRQGRP10 51
#define AVR32_IRQ_NREQGRP10 0 #define AVR32_IRQ_NREQGRP10 0
/* Group 11 */ /* Group 11 */
#define AVR32_IRQ_BASEIRQGRP11 52 #define AVR32_IRQ_BASEIRQGRP11 51
#define AVR32_IRQ_NREQGRP11 1 #define AVR32_IRQ_NREQGRP11 1
#define AVR32_IRQ_TWI 52 /* 0 Two-wire Interface TWI */ #define AVR32_IRQ_TWI 51 /* 0 Two-wire Interface TWI */
/* Group 12 */ /* Group 12 */
#define AVR32_IRQ_BASEIRQGRP12 53 #define AVR32_IRQ_BASEIRQGRP12 52
#define AVR32_IRQ_NREQGRP12 1 #define AVR32_IRQ_NREQGRP12 1
#define AVR32_IRQ_PWM 53 /* 0 Pulse Width Modulation Controller */ #define AVR32_IRQ_PWM 52 /* 0 Pulse Width Modulation Controller */
/* Group 13 */ /* Group 13 */
#define AVR32_IRQ_BASEIRQGRP13 54 #define AVR32_IRQ_BASEIRQGRP13 53
#define AVR32_IRQ_NREQGRP13 1 #define AVR32_IRQ_NREQGRP13 1
#define AVR32_IRQ_SSC 54 /* 0 Synchronous Serial Controller */ #define AVR32_IRQ_SSC 53 /* 0 Synchronous Serial Controller */
/* Group 14 */ /* Group 14 */
#define AVR32_IRQ_BASEIRQGRP14 55 #define AVR32_IRQ_BASEIRQGRP14 54
#define AVR32_IRQ_NREQGRP14 3 #define AVR32_IRQ_NREQGRP14 3
#define AVR32_IRQ_TC0 55 /* 0 Timer/Counter 0 */ #define AVR32_IRQ_TC0 54 /* 0 Timer/Counter 0 */
#define AVR32_IRQ_TC1 56 /* 1 Timer/Counter 1 */ #define AVR32_IRQ_TC1 55 /* 1 Timer/Counter 1 */
#define AVR32_IRQ_TC2 57 /* 2 Timer/Counter 2 */ #define AVR32_IRQ_TC2 56 /* 2 Timer/Counter 2 */
/* Group 15 */ /* Group 15 */
#define AVR32_IRQ_BASEIRQGRP15 58 #define AVR32_IRQ_BASEIRQGRP15 57
#define AVR32_IRQ_NREQGRP15 1 #define AVR32_IRQ_NREQGRP15 1
#define AVR32_IRQ_ADC 58 /* 0 Analog to Digital Converter */ #define AVR32_IRQ_ADC 57 /* 0 Analog to Digital Converter */
#define AVR32_IRQ_BASEIRQGRP16 59 #define AVR32_IRQ_BASEIRQGRP16 58
#define AVR32_IRQ_NREQGRP16 0 #define AVR32_IRQ_NREQGRP16 0
/* Group 17 */ /* Group 17 */
#define AVR32_IRQ_BASEIRQGRP17 59 #define AVR32_IRQ_BASEIRQGRP17 58
#define AVR32_IRQ_NREQGRP17 1 #define AVR32_IRQ_NREQGRP17 1
#define AVR32_IRQ_USBB 59 /* 0 USB 2.0 Interface USBB */ #define AVR32_IRQ_USBB 58 /* 0 USB 2.0 Interface USBB */
/* Group 18 */ /* Group 18 */
#define AVR32_IRQ_BASEIRQGRP18 60 #define AVR32_IRQ_BASEIRQGRP18 59
#define AVR32_IRQ_NREQGRP18 1 #define AVR32_IRQ_NREQGRP18 1
#define AVR32_IRQ_ABDAC 60 /* 0 Audio Bitstream DAC */ #define AVR32_IRQ_ABDAC 59 /* 0 Audio Bitstream DAC */
/* Total number of IRQ numbers */ /* Total number of IRQ numbers */
#define AVR32_IRQ_BADVECTOR 61 /* Not a real IRQ number */ #define AVR32_IRQ_BADVECTOR 60 /* Not a real IRQ number */
#define NR_IRQS 61 #define NR_IRQS 60
/* GPIO IRQ Numbers *********************************************************/ /* GPIO IRQ Numbers *********************************************************/
/* These numbers correspond to GPIO port numbers that have interrupts /* These numbers correspond to GPIO port numbers that have interrupts

13
arch/avr/include/avr32/irq.h
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@ -146,6 +146,19 @@ static inline uint32_t avr32_sr(void)
return sr; return sr;
} }
/* Read the interrupt vector base address */
static inline uint32_t avr32_evba(void)
{
uint32_t evba;
__asm__ __volatile__ (
"mfsr\t%0,%1\n\t"
: "=r" (evba)
: "i" (AVR32_EVBA)
);
return evba;
}
/* Save the current interrupt enable state & disable all interrupts */ /* Save the current interrupt enable state & disable all interrupts */
static inline irqstate_t irqsave(void) static inline irqstate_t irqsave(void)

16
arch/avr/src/at32uc3/at32uc3_irq.c
View File

@ -133,10 +133,10 @@ static const struct irq_groups_s g_grpirqs[AVR32_IRQ_NGROUPS] =
#if 0 /* REVISIT -- Can we come up with a way to statically initialize? */ #if 0 /* REVISIT -- Can we come up with a way to statically initialize? */
static const uint32_t g_ipr[AVR32_IRQ_INTPRIOS] = static const uint32_t g_ipr[AVR32_IRQ_INTPRIOS] =
{ {
((AVR32_INT0_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT0), ((AVR32_INT0_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) | INTC_IPR_INTLEVEL_INT0),
((AVR32_INT1_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT1), ((AVR32_INT1_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) | INTC_IPR_INTLEVEL_INT1),
((AVR32_INT2_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT2), ((AVR32_INT2_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) | INTC_IPR_INTLEVEL_INT2),
((AVR32_INT3_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT3), ((AVR32_INT3_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) | INTC_IPR_INTLEVEL_INT3),
}; };
#else #else
static uint32_t g_ipr[AVR32_IRQ_INTPRIOS]; static uint32_t g_ipr[AVR32_IRQ_INTPRIOS];
@ -201,10 +201,10 @@ void up_irqinitialize(void)
*/ */
#if 1 /* REVISIT -- Can we come up with a way to statically initialize? */ #if 1 /* REVISIT -- Can we come up with a way to statically initialize? */
g_ipr[0] = ((AVR32_INT0_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT0); g_ipr[0] = ((AVR32_INT0_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) | INTC_IPR_INTLEVEL_INT0);
g_ipr[1] = ((AVR32_INT1_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT1); g_ipr[1] = ((AVR32_INT1_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) | INTC_IPR_INTLEVEL_INT1);
g_ipr[2] = ((AVR32_INT2_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT2); g_ipr[2] = ((AVR32_INT2_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) | INTC_IPR_INTLEVEL_INT2);
g_ipr[3] = ((AVR32_INT3_RADDR << INTC_IPR_INTLEVEL_SHIFT) | INTC_IPR_INTLEVEL_INT3); g_ipr[3] = ((AVR32_INT3_RADDR << INTC_IPR_AUTOVECTOR_SHIFT) | INTC_IPR_INTLEVEL_INT3);
#endif #endif
/* Set the interrupt group priority to a default value. All are linked to /* Set the interrupt group priority to a default value. All are linked to