From 7816ba9a7be42bf359a746c7884adac2da76d0f4 Mon Sep 17 00:00:00 2001 From: Jari van Ewijk Date: Fri, 22 Jul 2022 10:29:40 +0200 Subject: [PATCH] NXP S32K3XX: add initial support for NXP S32K344EVB board Co-authored-by: Peter van der Perk --- boards/Kconfig | 45 ++- boards/arm/s32k3xx/s32k344evb/Kconfig | 8 + boards/arm/s32k3xx/s32k344evb/README.txt | 134 +++++++ .../s32k3xx/s32k344evb/configs/nsh/defconfig | 44 +++ boards/arm/s32k3xx/s32k344evb/include/board.h | 168 ++++++++ .../arm/s32k3xx/s32k344evb/scripts/Make.defs | 49 +++ .../arm/s32k3xx/s32k344evb/scripts/flash.ld | 156 ++++++++ boards/arm/s32k3xx/s32k344evb/src/Makefile | 50 +++ .../arm/s32k3xx/s32k344evb/src/s32k344evb.h | 133 +++++++ .../s32k3xx/s32k344evb/src/s32k3xx_appinit.c | 82 ++++ .../s32k3xx/s32k344evb/src/s32k3xx_autoleds.c | 166 ++++++++ .../arm/s32k3xx/s32k344evb/src/s32k3xx_boot.c | 77 ++++ .../s32k3xx/s32k344evb/src/s32k3xx_bringup.c | 122 ++++++ .../s32k3xx/s32k344evb/src/s32k3xx_buttons.c | 154 ++++++++ .../s32k344evb/src/s32k3xx_clockconfig.c | 157 ++++++++ .../arm/s32k3xx/s32k344evb/src/s32k3xx_i2c.c | 104 +++++ .../s32k344evb/src/s32k3xx_periphclocks.c | 250 ++++++++++++ .../arm/s32k3xx/s32k344evb/src/s32k3xx_spi.c | 366 ++++++++++++++++++ .../s32k3xx/s32k344evb/src/s32k3xx_userleds.c | 124 ++++++ 19 files changed, 2373 insertions(+), 16 deletions(-) create mode 100644 boards/arm/s32k3xx/s32k344evb/Kconfig create mode 100644 boards/arm/s32k3xx/s32k344evb/README.txt create mode 100644 boards/arm/s32k3xx/s32k344evb/configs/nsh/defconfig create mode 100644 boards/arm/s32k3xx/s32k344evb/include/board.h create mode 100644 boards/arm/s32k3xx/s32k344evb/scripts/Make.defs create mode 100644 boards/arm/s32k3xx/s32k344evb/scripts/flash.ld create mode 100644 boards/arm/s32k3xx/s32k344evb/src/Makefile create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k344evb.h create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_autoleds.c create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_boot.c create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_bringup.c create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_buttons.c create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_i2c.c create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_periphclocks.c create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_spi.c create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c diff --git a/boards/Kconfig b/boards/Kconfig index 01b502fb45..63b5baf381 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -1580,16 +1580,6 @@ config ARCH_BOARD_S32K144EVB This options selects support for NuttX on the NXP S32K144EVB board featuring the S32K144 Cortex-M4F. -config ARCH_BOARD_UCANS32K146 - bool "NXP UCANS32K146" - depends on ARCH_CHIP_S32K146 - select ARCH_HAVE_LEDS - select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS - ---help--- - This options selects support for NuttX on the NXP UCANS32K board - featuring the S32K146 Cortex-M4F. - config ARCH_BOARD_S32K146EVB bool "NXP S32K146EVB" depends on ARCH_CHIP_S32K146 @@ -1600,6 +1590,16 @@ config ARCH_BOARD_S32K146EVB This options selects support for NuttX on the NXP S32K146EVB board featuring the S32K146 Cortex-M4F. +config ARCH_BOARD_UCANS32K146 + bool "NXP UCANS32K146" + depends on ARCH_CHIP_S32K146 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + This options selects support for NuttX on the NXP UCANS32K1 board + featuring the S32K146 Cortex-M4F. + config ARCH_BOARD_S32K148EVB bool "NXP S32K148EVB" depends on ARCH_CHIP_S32K148 @@ -1610,6 +1610,16 @@ config ARCH_BOARD_S32K148EVB This options selects support for NuttX on the NXP S32K148EVB board featuring the S32K148 Cortex-M4F. +config ARCH_BOARD_S32K344EVB + bool "NXP S32K344EVB" + depends on ARCH_CHIP_S32K344 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + This options selects support for NuttX on the NXP S32K344EVB board + featuring the S32K344 Cortex-M7. + config ARCH_BOARD_SABRE_6QUAD bool "NXP/Freescale i.MX6 Sabre-6Quad board" depends on ARCH_CHIP_IMX6_6QUAD @@ -1620,7 +1630,6 @@ config ARCH_BOARD_SABRE_6QUAD This options selects support for NuttX on the NXP/Freescale Sabre board featuring the iMX 6Quad CPU. - config ARCH_BOARD_QEMU_A53 bool "Qemu A53 board" depends on ARCH_CHIP_QEMU_A53 @@ -2667,11 +2676,12 @@ config ARCH_BOARD default "rx65n-grrose" if ARCH_BOARD_RX65N_GRROSE default "s32k118evb" if ARCH_BOARD_S32K118EVB default "s32k144evb" if ARCH_BOARD_S32K144EVB + default "s32k146evb" if ARCH_BOARD_S32K146EVB default "ucans32k146" if ARCH_BOARD_UCANS32K146 + default "s32k148evb" if ARCH_BOARD_S32K148EVB + default "s32k344evb" if ARCH_BOARD_S32K344EVB default "rv32m1-vega" if ARCH_BOARD_RV32M1_VEGA default "rv-virt" if ARCH_BOARD_QEMU_RV_VIRT - default "s32k146evb" if ARCH_BOARD_S32K146EVB - default "s32k148evb" if ARCH_BOARD_S32K148EVB default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD default "qemu-a53" if ARCH_BOARD_QEMU_A53 default "sama5d2-xult" if ARCH_BOARD_SAMA5D2_XULT @@ -2834,15 +2844,18 @@ endif if ARCH_BOARD_S32K144EVB source "boards/arm/s32k1xx/s32k144evb/Kconfig" endif -if ARCH_BOARD_UCANS32K146 -source "boards/arm/s32k1xx/ucans32k146/Kconfig" -endif if ARCH_BOARD_S32K146EVB source "boards/arm/s32k1xx/s32k146evb/Kconfig" endif +if ARCH_BOARD_UCANS32K146 +source "boards/arm/s32k1xx/ucans32k146/Kconfig" +endif if ARCH_BOARD_S32K148EVB source "boards/arm/s32k1xx/s32k148evb/Kconfig" endif +if ARCH_BOARD_S32K344EVB +source "boards/arm/s32k3xx/s32k344evb/Kconfig" +endif if ARCH_BOARD_SABRE_6QUAD source "boards/arm/imx6/sabre-6quad/Kconfig" endif diff --git a/boards/arm/s32k3xx/s32k344evb/Kconfig b/boards/arm/s32k3xx/s32k344evb/Kconfig new file mode 100644 index 0000000000..beb7e5752f --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_S32K344EVB + +endif # ARCH_BOARD_S32K344EVB diff --git a/boards/arm/s32k3xx/s32k344evb/README.txt b/boards/arm/s32k3xx/s32k344evb/README.txt new file mode 100644 index 0000000000..6dc6f5679d --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/README.txt @@ -0,0 +1,134 @@ +README +====== + +This directory holds the port to the NXP S32K344EVB-Q257 development board. + +Contents +======== + + o Status + o Serial Console + o LEDs and Buttons + o OpenSDA Notes + o Configurations + +Status +====== + + 2021-07-05: Configuration created. + + TODO: Need to calibrate the delay loop. The current value of + CONFIG_BOARD_LOOPSPERMSEC is a bogus value retained from a copy-paste + (see apps/examples/calib_udelay). + +Serial Console +============== + + By default, the serial console will be provided on the OpenSDA VCOM port: + + OpenSDA UART RX PTA15 (LPUART6_RX) + OpenSDA UART TX PTA16 (LPUART6_TX) + + USB drivers for the PEmicro CDC Serial Port are available here: + http://www.pemicro.com/opensda/ + +LEDs and Buttons +================ + + LEDs + ---- + The S32K344EVB has two RGB LEDs: + + RedLED0 PTA29 (EMIOS1 CH12 / EMIOS2 CH12) + GreenLED0 PTA30 (EMIOS1 CH13 / EMIOS2 CH13) + BlueLED0 PTA31 (EMIOS1 CH14 / FXIO D0) + + RedLED1 PTB18 (EMIOS1 CH15 / EMIOS2 CH14 / FXIO D1) + GreenLED1 PTB25 (EMIOS1 CH21 / EMIOS2 CH21 / FXIO D6) + BlueLED1 PTE12 (EMIOS1 CH5 / FXIO D8) + + An output of '1' illuminates the LED. + + If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + any way. The following definitions are used to access individual RGB + components (see s32k344evb.h): + + GPIO_LED0_R + GPIO_LED0_G + GPIO_LED0_B + + GPIO_LED1_R + GPIO_LED1_G + GPIO_LED1_B + + The RGB components could, alternatively, be controlled through PWM using + the common RGB LED driver. + + If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board + the S32K344EVB. The following definitions describe how NuttX controls the + LEDs: + + ==========================================+========+========+========= + RED GREEN BLUE + ==========================================+========+========+========= + + LED_STARTED NuttX has been started OFF OFF OFF + LED_HEAPALLOCATE Heap has been allocated OFF OFF ON + LED_IRQSENABLED Interrupts enabled OFF OFF ON + LED_STACKCREATED Idle stack created OFF ON OFF + LED_INIRQ In an interrupt (no change) + LED_SIGNAL In a signal handler (no change) + LED_ASSERTION An assertion failed (no change) + LED_PANIC The system has crashed FLASH OFF OFF + LED_IDLE S32K344 in sleep mode (no change) + ==========================================+========+========+========= + + Buttons + ------- + The S32K344EVB supports two buttons: + + SW0 PTB26 (EIRQ13 / WKPU41) + SW1 PTB19 (WKPU38) + +OpenSDA Notes +============= + + - USB drivers for the PEmicro CDC Serial Port are available here: + http://www.pemicro.com/opensda/ + + - The drag'n'drog interface expects files in .srec format. + +Configurations +============== + + Common Information + ------------------ + Each S32K344EVB configuration is maintained in a sub-directory and can be + selected as follows: + + tools/configure.sh s32k344evb: + + Where is one of the sub-directories listed in the next paragraph. + + NOTES (common for all configurations): + + 1. This configuration uses the mconf-based configuration tool. To change + this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt. + Also see additional README.txt files in the NuttX tools repository. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Unless otherwise stated, the serial console used is LPUART1 at + 115,200 8N1. This corresponds to the OpenSDA VCOM port. + + Configuration Sub-directories + ----------------------------- + + nsh: + --- + Configures the NuttShell (nsh) located at apps/examples/nsh. Support + for builtin applications is enabled, but in the base configuration the + only application selected is the "Hello, World!" example. diff --git a/boards/arm/s32k3xx/s32k344evb/configs/nsh/defconfig b/boards/arm/s32k3xx/s32k344evb/configs/nsh/defconfig new file mode 100644 index 0000000000..36bacd0f87 --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/configs/nsh/defconfig @@ -0,0 +1,44 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_CMDPARMS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="s32k344evb" +CONFIG_ARCH_BOARD_S32K344EVB=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="s32k3xx" +CONFIG_ARCH_CHIP_S32K344=y +CONFIG_ARCH_CHIP_S32K3XX=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=14539 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LPUART13_SERIAL_CONSOLE=y +CONFIG_MOTOROLA_SREC=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=288000 +CONFIG_RAM_START=0x20408000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_S32K3XX_LPUART13=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=30 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2022 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/s32k3xx/s32k344evb/include/board.h b/boards/arm/s32k3xx/s32k344evb/include/board.h new file mode 100644 index 0000000000..a6d8d0623c --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/include/board.h @@ -0,0 +1,168 @@ +/**************************************************************************** + * boards/arm/s32k3xx/s32k344evb/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +#ifndef __BOARDS_ARM_S32K3XX_S32K344EVB_INCLUDE_BOARD_H +#define __BOARDS_ARM_S32K3XX_S32K344EVB_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The S32K344EVB is fitted with a 16 MHz crystal */ + +#define BOARD_XTAL_FREQUENCY 16000000 + +/* The S32K344 will run at 160 MHz */ + +/* LED definitions **********************************************************/ + +/* The S32K344EVB has two RGB LEDs: + * + * RedLED0 PTA29 (EMIOS1 CH12 / EMIOS2 CH12) + * GreenLED0 PTA30 (EMIOS1 CH13 / EMIOS2 CH13) + * BlueLED0 PTA31 (EMIOS1 CH14 / FXIO D0) + * + * RedLED1 PTB18 (EMIOS1 CH15 / EMIOS2 CH14 / FXIO D1) + * GreenLED1 PTB25 (EMIOS1 CH21 / EMIOS2 CH21 / FXIO D6) + * BlueLED1 PTE12 (EMIOS1 CH5 / FXIO D8) + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual RGB + * components. + * + * The RGB components could, alternatively be controlled through PWM using + * the common RGB LED driver. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED0_R 0 +#define BOARD_LED0_G 1 +#define BOARD_LED0_B 2 + +#define BOARD_LED1_R 3 +#define BOARD_LED1_G 4 +#define BOARD_LED1_B 5 + +#define BOARD_NLEDS 6 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED0_R_BIT (1 << BOARD_LED0_R) +#define BOARD_LED0_G_BIT (1 << BOARD_LED0_G) +#define BOARD_LED0_B_BIT (1 << BOARD_LED0_B) + +#define BOARD_LED1_R_BIT (1 << BOARD_LED1_R) +#define BOARD_LED1_G_BIT (1 << BOARD_LED1_G) +#define BOARD_LED1_B_BIT (1 << BOARD_LED1_B) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board + * the S32K344EVB. The following definitions describe how NuttX controls the + * LEDs: + * + * SYMBOL Meaning LED state + * RED GREEN BLUE + * ---------------- ----------------------------- ------------------- + */ + +#define LED_STARTED 1 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 2 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF ON */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON OFF */ +#define LED_INIRQ 0 /* In an interrupt (No change) */ +#define LED_SIGNAL 0 /* In a signal handler (No change) */ +#define LED_ASSERTION 0 /* An assertion failed (No change) */ +#define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */ +#undef LED_IDLE /* S32K344 is in sleep mode (Not used) */ + +/* Button definitions *******************************************************/ + +/* The S32K344EVB supports two buttons: + * + * SW0 PTB26 (EIRQ13 / WKPU41) + * SW1 PTB19 (WKPU38) + */ + +#define BUTTON_SW0 0 +#define BUTTON_SW1 1 +#define NUM_BUTTONS 2 + +#define BUTTON_SW0_BIT (1 << BUTTON_SW0) +#define BUTTON_SW1_BIT (1 << BUTTON_SW1) + +/* UART selections **********************************************************/ + +/* By default, the serial console will be provided on the OpenSDA VCOM port: + * + * OpenSDA UART RX PTA15 (LPUART6_RX) + * OpenSDA UART TX PTA16 (LPUART6_TX) + */ + +#define PIN_LPUART6_RX PIN_LPUART6_RX_1 /* PTA15 */ +#define PIN_LPUART6_TX PIN_LPUART6_TX_1 /* PTA16 */ + +/* LPUART13 J58 USB-UART */ + +#define PIN_LPUART13_RX PIN_LPUART13_RX_2 /* PTC27 */ +#define PIN_LPUART13_TX PIN_LPUART13_TX_2 /* PTC26 */ + +/* SPI selections ***********************************************************/ + +/* LPSPI0 FS26 Safety SBC */ + +#define PIN_LPSPI0_SCK PIN_LPSPI0_SCK_1 /* PTC8 */ +#define PIN_LPSPI0_MISO PIN_LPSPI0_SIN_1 /* PTC9 */ +#define PIN_LPSPI0_MOSI PIN_LPSPI0_SOUT_2 /* PTB1 */ + +#define PIN_LPSPI0_PCS (PIN_PTB0 | GPIO_LOWDRIVE | GPIO_OUTPUT_ONE) /* PTB0 */ + +/* LPSPI1 J353 Arduino Header */ + +#define PIN_LPSPI1_SCK PIN_LPSPI1_SCK_4 /* PTB14 */ +#define PIN_LPSPI1_MISO PIN_LPSPI1_SIN_4 /* PTB15 */ +#define PIN_LPSPI1_MOSI PIN_LPSPI1_SOUT_3 /* PTB16 */ + +#define PIN_LPSPI1_PCS PIN_LPSPI1_PCS3_2 /* PTB17 */ + +/* I2C selections ***********************************************************/ + +/* LPI2C1 J353 Arduino Header / J63 ENET PHY / MMA8452Q Accelerometer + * / SGTL5000 Audio Codec + */ + +#define PIN_LPI2C1_SCL PIN_LPI2C1_SCL_1 /* PTC7 */ +#define PIN_LPI2C1_SDA PIN_LPI2C1_SDA_1 /* PTC6 */ + +/* FLEXCAN selections *******************************************************/ + +#define PIN_CAN0_TX PIN_CAN0_TX_1 /* PTA7 */ +#define PIN_CAN0_RX PIN_CAN0_RX_1 /* PTA6 */ + +#endif /* __BOARDS_ARM_S32K3XX_S32K344EVB_INCLUDE_BOARD_H */ diff --git a/boards/arm/s32k3xx/s32k344evb/scripts/Make.defs b/boards/arm/s32k3xx/s32k344evb/scripts/Make.defs new file mode 100644 index 0000000000..19a99cd837 --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/scripts/Make.defs @@ -0,0 +1,49 @@ +############################################################################ +# boards/arm/s32k3xx/s32k344evb/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Copyright 2022 NXP + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y) + LDSCRIPT = flash.ld +else ifeq ($(CONFIG_BOOT_RUNFROMISRAM),y) + LDSCRIPT = sram.ld +endif + +$(warning, LDSCRIPT is $(LDSCRIPT)) +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +$(warning, LDSCRIPT is $(LDSCRIPT)) +$(warning, ARCHSCRIPT is $(ARCHSCRIPT)) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/s32k3xx/s32k344evb/scripts/flash.ld b/boards/arm/s32k3xx/s32k344evb/scripts/flash.ld new file mode 100644 index 0000000000..5822d4865b --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/scripts/flash.ld @@ -0,0 +1,156 @@ +/**************************************************************************** + * boards/arm/s32k3xx/s32k344evb/scripts/flash.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +/* TO DO: ADD DESCRIPTION + * + * 0x00400000 - 0x007fffff 4194304 Program Flash (last 64K sBAF) + * 0x10000000 - 0x1003ffff 262144 Data Flash (last 32K HSE_NVM) + * 0x20400000 - 0x20408000 32768 Standby RAM_0 (32K) + * 0x20400000 - 0x20427fff 163840 SRAM_0 + * 0x20428000 - 0x2044ffff 163840 SRAM_1 + * + * Last 48 KB of SRAM_1 reserved by HSE Firmware + * Last 128 KB of CODE_FLASH_3 reserved by HSE Firmware + * Last 128 KB of DATA_FLASH reserved by HSE Firmware (not supported in this linker file) + */ + +MEMORY +{ + BOOT_HEADER (R) : ORIGIN = 0x00400000, LENGTH = 0x00001000 /* 0x00400000 - 0x00400fff */ + flash (rx) : ORIGIN = 0x00401000, LENGTH = 0x003cffff /* 0x00401000 - (0x007fffff - 0x20000 (128 KB) = 0x007dffff) */ + sram0_stdby (rwx) : ORIGIN = 0x20400000, LENGTH = 32K + sram (rwx) : ORIGIN = 0x20408000, LENGTH = 240K + itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K + dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +EXTERN(boot_header) +ENTRY(_stext) + +SECTIONS +{ + + .boot_header : + { + KEEP(*(.boot_header)) + } > BOOT_HEADER + + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text.__start) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } >flash + + .ARM.exidx : + { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } >flash + + /* Due ECC initialization sequence __data_start__ and __data_end__ should be aligned on 8 bytes */ + .data : + { + . = ALIGN(8); + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(8); + _edata = ABSOLUTE(.); + } > sram AT > flash + + _eronly = LOADADDR(.data); + + .ramfunc ALIGN(8): + { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > sram AT > flash + + _framfuncs = LOADADDR(.ramfunc); + + /* Due ECC initialization sequence __bss_start__ and __bss_end__ should be aligned on 8 bytes */ + .bss : + { + . = ALIGN(8); + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > sram + + CM7_0_START_ADDRESS = ORIGIN(flash); + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + SRAM_BASE_ADDR = ORIGIN(sram); + SRAM_END_ADDR = ORIGIN(sram) + LENGTH(sram); + SRAM_STDBY_BASE_ADDR = ORIGIN(sram0_stdby); + SRAM_STDBY_END_ADDR = ORIGIN(sram0_stdby) + LENGTH(sram0_stdby); + ITCM_BASE_ADDR = ORIGIN(itcm); + ITCM_END_ADDR = ORIGIN(itcm) + LENGTH(itcm); + DTCM_BASE_ADDR = ORIGIN(dtcm); + DTCM_END_ADDR = ORIGIN(dtcm) + LENGTH(dtcm); +} diff --git a/boards/arm/s32k3xx/s32k344evb/src/Makefile b/boards/arm/s32k3xx/s32k344evb/src/Makefile new file mode 100644 index 0000000000..325b455763 --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/src/Makefile @@ -0,0 +1,50 @@ +############################################################################ +# boards/arm/s32k3xx/s32k344evb/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Copyright 2022 NXP + +include $(TOPDIR)/Make.defs + +CSRCS = s32k3xx_boot.c s32k3xx_bringup.c s32k3xx_clockconfig.c +CSRCS += s32k3xx_periphclocks.c + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += s32k3xx_buttons.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += s32k3xx_autoleds.c +else +CSRCS += s32k3xx_userleds.c +endif + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += s32k3xx_appinit.c +endif + +ifeq ($(CONFIG_S32K3XX_LPI2C),y) +CSRCS += s32k3xx_i2c.c +endif + +ifeq ($(CONFIG_S32K3XX_LPSPI),y) +CSRCS += s32k3xx_spi.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k344evb.h b/boards/arm/s32k3xx/s32k344evb/src/s32k344evb.h new file mode 100644 index 0000000000..abe697c6fc --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/src/s32k344evb.h @@ -0,0 +1,133 @@ +/**************************************************************************** + * boards/arm/s32k3xx/s32k344evb/src/s32k344evb.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +#ifndef __BOARDS_ARM_S32K3XX_S32K344EVB_SRC_S32K344EVB_H +#define __BOARDS_ARM_S32K3XX_S32K344EVB_SRC_S32K344EVB_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "hardware/s32k344_pinmux.h" +#include "s32k3xx_periphclocks.h" +#include "s32k3xx_pin.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* S32K344EVB GPIOs *********************************************************/ + +/* LEDs. The S32K344EVB has two RGB LEDs: + * + * RedLED0 PTA29 (EMIOS1 CH12 / EMIOS2 CH12) + * GreenLED0 PTA30 (EMIOS1 CH13 / EMIOS2 CH13) + * BlueLED0 PTA31 (EMIOS1 CH14 / FXIO D0) + * + * RedLED1 PTB18 (EMIOS1 CH15 / EMIOS2 CH14 / FXIO D1) + * GreenLED1 PTB25 (EMIOS1 CH21 / EMIOS2 CH21 / FXIO D6) + * BlueLED1 PTE12 (EMIOS1 CH5 / FXIO D8) + * + * An output of '1' illuminates the LED. + */ + +#define GPIO_LED0_R (PIN_PTA29 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) +#define GPIO_LED0_G (PIN_PTA30 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) +#define GPIO_LED0_B (PIN_PTA31 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) + +#define GPIO_LED1_R (PIN_PTB18 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) +#define GPIO_LED1_G (PIN_PTB25 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) +#define GPIO_LED1_B (PIN_PTE12 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO) + +/* Buttons. The S32K344EVB supports two buttons: + * + * SW0 PTB26 (EIRQ13 / WKPU41) + * SW1 PTB19 (WKPU38) + */ + +#define GPIO_SW0 (PIN_WKPU41 | PIN_INT_BOTH) +#define GPIO_SW1 (PIN_WKPU38 | PIN_INT_BOTH) + +/* Count of peripheral clock user configurations */ + +#define NUM_OF_PERIPHERAL_CLOCKS_0 25 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* User peripheral configuration structure 0 */ + +extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[]; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k3xx_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int s32k3xx_bringup(void); + +/**************************************************************************** + * Name: s32k3xx_i2cdev_initialize + * + * Description: + * Initialize I2C driver and register /dev/i2cN devices. + * + ****************************************************************************/ + +int s32k3xx_i2cdev_initialize(void); + +/**************************************************************************** + * Name: s32k3xx_spidev_initialize + * + * Description: + * Configure chip select pins, initialize the SPI driver and register + * /dev/spiN devices. + * + ****************************************************************************/ + +int s32k3xx_spidev_initialize(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_S32K3XX_S32K344EVB_SRC_S32K344EVB_H */ diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c new file mode 100644 index 0000000000..efbe5b9aa4 --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "s32k344evb.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef OK +# define OK 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no meaning + * to NuttX; the meaning of the argument is a contract between the + * board-specific initialization logic and the matching application + * logic. The value could be such things as a mode enumeration + * value, a set of DIP switch settings, a pointer to configuration + * data read from a file or serial FLASH, or whatever you would like + * to do with it. Every implementation should accept zero/NULL as a + * default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return s32k3xx_bringup(); +#endif +} diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_autoleds.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_autoleds.c new file mode 100644 index 0000000000..3d4b584c66 --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_autoleds.c @@ -0,0 +1,166 @@ +/**************************************************************************** + * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +/* The S32K344EVB has two RGB LEDs: + * + * RedLED0 PTA29 (EMIOS1 CH12 / EMIOS2 CH12) + * GreenLED0 PTA30 (EMIOS1 CH13 / EMIOS2 CH13) + * BlueLED0 PTA31 (EMIOS1 CH14 / FXIO D0) + * + * RedLED1 PTB18 (EMIOS1 CH15 / EMIOS2 CH14 / FXIO D1) + * GreenLED1 PTB25 (EMIOS1 CH21 / EMIOS2 CH21 / FXIO D6) + * BlueLED1 PTE12 (EMIOS1 CH5 / FXIO D8) + * + * An output of '1' illuminates the LED. + * + * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the S32K344EVB. The following definitions describe how NuttX controls the + * LEDs: + * + * SYMBOL Meaning LED state + * RED GREEN BLUE + * ---------------- ------------------------ -------------------- + * LED_STARTED NuttX has been started OFF OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON + * LED_IRQSENABLED Interrupts enabled OFF OFF ON + * LED_STACKCREATED Idle stack created OFF ON OFF + * LED_INIRQ In an interrupt (No change) + * LED_SIGNAL In a signal handler (No change) + * LED_ASSERTION An assertion failed (No change) + * LED_PANIC The system has crashed FLASH OFF OFF + * LED_IDLE S32K344 is in sleep mode (Optional, not used) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "s32k3xx_pin.h" + +#include "s32k344evb.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Summary of all possible settings */ + +#define LED_NOCHANGE 0 /* LED_IRQSENABLED, LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ +#define LED_OFF_OFF_OFF 1 /* LED_STARTED */ +#define LED_OFF_OFF_ON 2 /* LED_HEAPALLOCATE */ +#define LED_OFF_ON_OFF 3 /* LED_STACKCREATED */ +#define LED_ON_OFF_OFF 4 /* LED_PANIC */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + s32k3xx_pinconfig(GPIO_LED0_R); + s32k3xx_pinconfig(GPIO_LED0_G); + s32k3xx_pinconfig(GPIO_LED0_B); + + s32k3xx_pinconfig(GPIO_LED1_R); + s32k3xx_pinconfig(GPIO_LED1_G); + s32k3xx_pinconfig(GPIO_LED1_B); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led != LED_NOCHANGE) + { + bool redon = false; + bool greenon = false; + bool blueon = false; + + switch (led) + { + default: + case LED_OFF_OFF_OFF: + break; + + case LED_OFF_OFF_ON: + blueon = true; + break; + + case LED_OFF_ON_OFF: + greenon = true; + break; + + case LED_ON_OFF_OFF: + redon = true; + break; + } + + /* An output of '1' illuminates the LED */ + + s32k3xx_gpiowrite(GPIO_LED0_R, redon); + s32k3xx_gpiowrite(GPIO_LED0_G, greenon); + s32k3xx_gpiowrite(GPIO_LED0_B, blueon); + + s32k3xx_gpiowrite(GPIO_LED1_R, redon); + s32k3xx_gpiowrite(GPIO_LED1_G, greenon); + s32k3xx_gpiowrite(GPIO_LED1_B, blueon); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_ON_OFF_OFF) + { + /* An output of '1' illuminates the LED */ + + s32k3xx_gpiowrite(GPIO_LED0_R, true); + s32k3xx_gpiowrite(GPIO_LED0_G, false); + s32k3xx_gpiowrite(GPIO_LED0_B, false); + + s32k3xx_gpiowrite(GPIO_LED1_R, true); + s32k3xx_gpiowrite(GPIO_LED1_G, false); + s32k3xx_gpiowrite(GPIO_LED1_B, false); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_boot.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_boot.c new file mode 100644 index 0000000000..40c4305a3d --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_boot.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "s32k344evb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k3xx_board_initialize + * + * Description: + * All S32K3XX architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void s32k3xx_board_initialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + s32k3xx_bringup(); +} +#endif diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_bringup.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_bringup.c new file mode 100644 index 0000000000..14915834a5 --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_bringup.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_FS_PROCFS +# include +#endif + +#include "s32k344evb.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k3xx_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int s32k3xx_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_S32K3XX_LPI2C + /* Initialize I2C driver */ + + ret = s32k3xx_i2cdev_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: s32k3xx_i2cdev_initialize() failed: %d\n", + ret); + } +#endif + +#ifdef CONFIG_S32K3XX_LPSPI + /* Initialize SPI driver */ + + ret = s32k3xx_spidev_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: s32k3xx_spidev_initialize() failed: %d\n", + ret); + } +#endif + + return ret; +} diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_buttons.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_buttons.c new file mode 100644 index 0000000000..b4e0d7e9cc --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_buttons.c @@ -0,0 +1,154 @@ +/**************************************************************************** + * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_buttons.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +/* The S32K344EVB supports two buttons: + * + * SW0 PTB26 (EIRQ13 / WKPU41) + * SW1 PTB19 (WKPU38) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "s32k3xx_pin.h" + +#include + +#include "s32k344evb.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + /* Configure the GPIO pins as interrupting inputs */ + + s32k3xx_pinconfig(GPIO_SW0); + s32k3xx_pinconfig(GPIO_SW1); + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + + if (s32k3xx_gpioread(GPIO_SW0)) + { + ret |= BUTTON_SW0_BIT; + } + + if (s32k3xx_gpioread(GPIO_SW1)) + { + ret |= BUTTON_SW1_BIT; + } + + return ret; +} + +#ifdef CONFIG_ARCH_IRQBUTTONS +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns a + * 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is pressed or released. The ID value is a + * button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + uint32_t pinset; + int ret; + + /* Map the button id to the GPIO bit set */ + + if (id == BUTTON_SW0) + { + pinset = GPIO_SW0; + } + else if (id == BUTTON_SW1) + { + pinset = GPIO_SW1; + } + else + { + return -EINVAL; + } + + /* The button has already been configured as an interrupting input (by + * board_button_initialize() above). + * + * Attach the new button handler. + */ + + ret = s32k3xx_pinirqattach(pinset, irqhandler, NULL); + if (ret >= 0) + { + /* Then make sure that interrupts are enabled on the pin */ + + s32k3xx_pinirqenable(pinset); + } + + return ret; +} +#endif /* CONFIG_ARCH_IRQBUTTONS */ +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c new file mode 100644 index 0000000000..b52e88670c --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c @@ -0,0 +1,157 @@ +/**************************************************************************** + * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "s32k3xx_clockconfig.h" +#include "s32k3xx_start.h" + +#include "s32k344evb.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each S32K3XX board must provide the following initialized structure. + * This is needed to establish the initial board clocking. + */ + +const struct clock_configuration_s g_initial_clkconfig = +{ + .cgm = + { + .sirc = + { + .range = CGM_FIRC_RANGE_32K, /* Slow IRC is trimmed to 32 kHz */ + }, + .firc = + { + .range = CGM_FIRC_RANGE_HIGH, /* RANGE */ + .div = CGM_CLOCK_DIV_BY_1, /* FIRCDIV1 */ + }, + .scs = + { + .scs_source = CGM_SCS_SOURCE_PLL_PHI0, + .core_clk = + { + .div = CGM_MUX_DIV_BY_1, + .trigger = false, + }, + .aips_plat_clk = + { + .div = CGM_MUX_DIV_BY_2, + .trigger = false, + }, + .aips_slow_clk = + { + .div = CGM_MUX_DIV_SLOW_BY_4, + .trigger = false, + }, + .hse_clk = + { + .div = CGM_MUX_DIV_BY_1, + .trigger = false, + }, + .dcm_clk = + { + .div = CGM_MUX_DIV_BY_1, + .trigger = false, + }, + .lbist_clk = + { + .div = CGM_MUX_DIV_BY_1, + .trigger = false, + }, +#ifdef CONFIG_S32K3XX_QSPI + .qspi_mem_clk = + { + .div = CGM_MUX_DIV_BY_1, + .trigger = false, + }, +#endif + .mux_3 = + { + .source = CGM_CLK_SRC_AIPS_PLAT_CLK, + .div = CGM_MUX_DIV_BY_2, + }, +#ifdef CONFIG_S32K3XX_ENET + .mux_7_emac_rx = + { + .source = CGM_CLK_SRC_EMAC_RMII_TX_CLK, + .div = CGM_MUX_DIV_BY_2, + }, + .mux_8_emac_tx = + { + .source = CGM_CLK_SRC_EMAC_RMII_TX_CLK, + .div = CGM_MUX_DIV_BY_2, + }, + .mux_9_emac_ts = + { + .source = CGM_CLK_SRC_EMAC_RMII_TX_CLK, + .div = CGM_MUX_DIV_BY_2, /* FIXME check div value */ + }, +#endif +#ifdef CONFIG_S32K3XX_QSPI + .mux_10_qspi_sfck = + { + .source = CGM_CLK_SRC_PLL_PHI1_CLK, + .div = CGM_MUX_DIV_BY_2, + }, +#endif + }, + .pll = + { + .modul_freq = 0, + .modul_depth = 0, + .core_pll_power = true, + .modulation_type = false, + .sigma_delta = CGM_PLL_SIGMA_DELTA, + .enable_dither = false, + .mode = CGM_PLL_INTEGER_MODE, + .prediv = 4, + .mult = 240, + .postdiv = 2, + .phi0 = CGM_PLL_PHI_DIV_BY_3, + .phi1 = CGM_PLL_PHI_DIV_BY_3, + }, + .clkout = + { + .source = CGM_CLK_SRC_AIPS_SLOW_CLK, + .div = CGM_CLKOUT_DIV_BY_1, + } + }, + .pcc = + { + .count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number of peripheral clock configurations */ + .pclks = g_peripheral_clockconfig0, /* Peripheral clock configurations */ + }, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_i2c.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_i2c.c new file mode 100644 index 0000000000..727c1bd711 --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_i2c.c @@ -0,0 +1,104 @@ +/**************************************************************************** + * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_i2c.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include + +#include + +#include "s32k3xx_lpi2c.h" + +#include "s32k344evb.h" + +#ifdef CONFIG_S32K3XX_LPI2C + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k3xx_i2cdev_initialize + * + * Description: + * Initialize I2C driver and register /dev/i2cN devices. + * + ****************************************************************************/ + +int weak_function s32k3xx_i2cdev_initialize(void) +{ + int ret = OK; + +#if defined(CONFIG_S32K3XX_LPI2C0) && defined(CONFIG_I2C_DRIVER) + /* LPI2C0 *****************************************************************/ + + /* Initialize the I2C driver for LPI2C0 */ + + struct i2c_master_s *lpi2c0 = s32k3xx_i2cbus_initialize(0); + if (lpi2c0 == NULL) + { + i2cerr("ERROR: FAILED to initialize LPI2C0\n"); + return -ENODEV; + } + + ret = i2c_register(lpi2c0, 0); + if (ret < 0) + { + i2cerr("ERROR: FAILED to register LPI2C0 driver\n"); + s32k3xx_i2cbus_uninitialize(lpi2c0); + return ret; + } +#endif /* CONFIG_S32K3XX_LPI2C0 && CONFIG_I2C_DRIVER */ + +#if defined(CONFIG_S32K3XX_LPI2C1) && defined(CONFIG_I2C_DRIVER) + /* LPI2C1 *****************************************************************/ + + /* Initialize the I2C driver for LPI2C1 */ + + struct i2c_master_s *lpi2c1 = s32k3xx_i2cbus_initialize(1); + if (lpi2c1 == NULL) + { + i2cerr("ERROR: FAILED to initialize LPI2C1\n"); + return -ENODEV; + } + + ret = i2c_register(lpi2c1, 0); + if (ret < 0) + { + i2cerr("ERROR: FAILED to register LPI2C1 driver\n"); + s32k3xx_i2cbus_uninitialize(lpi2c1); + return ret; + } +#endif /* CONFIG_S32K3XX_LPI2C1 && CONFIG_I2C_DRIVER */ + + return ret; +} + +#endif /* CONFIG_S32K3XX_LPI2C */ diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_periphclocks.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_periphclocks.c new file mode 100644 index 0000000000..85a3ad1469 --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_periphclocks.c @@ -0,0 +1,250 @@ +/**************************************************************************** + * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_periphclocks.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "s32k3xx_clocknames.h" +#include "s32k3xx_periphclocks.h" + +#include "s32k344evb.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Each S32K3XX board must provide the following initialized structure. + * This is needed to establish the initial peripheral clocking. + */ + +const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = +{ + { + .clkname = LPI2C0_CLK, +#ifdef CONFIG_S32K3XX_LPI2C0 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPI2C1_CLK, +#ifdef CONFIG_S32K3XX_LPI2C1 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPSPI0_CLK, +#ifdef CONFIG_S32K3XX_LPSPI0 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPSPI1_CLK, +#ifdef CONFIG_S32K3XX_LPSPI1 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPSPI2_CLK, +#ifdef CONFIG_S32K3XX_LPSPI2 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPSPI3_CLK, +#ifdef CONFIG_S32K3XX_LPSPI3 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPSPI4_CLK, +#ifdef CONFIG_S32K3XX_LPSPI4 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPSPI5_CLK, +#ifdef CONFIG_S32K3XX_LPSPI5 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART0_CLK, +#ifdef CONFIG_S32K3XX_LPUART0 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART1_CLK, +#ifdef CONFIG_S32K3XX_LPUART1 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART2_CLK, +#ifdef CONFIG_S32K3XX_LPUART2 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART3_CLK, +#ifdef CONFIG_S32K3XX_LPUART3 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART4_CLK, +#ifdef CONFIG_S32K3XX_LPUART4 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART5_CLK, +#ifdef CONFIG_S32K3XX_LPUART5 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART6_CLK, +#ifdef CONFIG_S32K3XX_LPUART6 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART7_CLK, +#ifdef CONFIG_S32K3XX_LPUART7 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART8_CLK, +#ifdef CONFIG_S32K3XX_LPUART8 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART9_CLK, +#ifdef CONFIG_S32K3XX_LPUART9 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART10_CLK, +#ifdef CONFIG_S32K3XX_LPUART10 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART11_CLK, +#ifdef CONFIG_S32K3XX_LPUART11 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART12_CLK, +#ifdef CONFIG_S32K3XX_LPUART12 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART13_CLK, +#ifdef CONFIG_S32K3XX_LPUART13 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART14_CLK, +#ifdef CONFIG_S32K3XX_LPUART14 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = LPUART15_CLK, +#ifdef CONFIG_S32K3XX_LPUART15 + .clkgate = true, +#else + .clkgate = false, +#endif + }, + { + .clkname = WKPU_CLK, +#ifdef CONFIG_S32K3XX_WKPUINTS + .clkgate = true, +#else + .clkgate = false, +#endif + }, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_spi.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_spi.c new file mode 100644 index 0000000000..a9db32aa1e --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_spi.c @@ -0,0 +1,366 @@ +/**************************************************************************** + * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "s32k3xx_pin.h" +#include "s32k3xx_lpspi.h" + +#include + +#include "s32k344evb.h" + +#ifdef CONFIG_S32K3XX_FS26 +#include "s32k3xx_fs26.h" +#endif + +#ifdef CONFIG_S32K3XX_LPSPI + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: s32k3xx_spidev_initialize + * + * Description: + * Configure chip select pins, initialize the SPI driver and register + * /dev/spiN devices. + * + ****************************************************************************/ + +int weak_function s32k3xx_spidev_initialize(void) +{ + int ret = OK; + +#ifdef CONFIG_S32K3XX_LPSPI0 + /* LPSPI0 *****************************************************************/ + + /* Configure LPSPI0 peripheral chip select */ + + s32k3xx_pinconfig(PIN_LPSPI0_PCS); + + /* Initialize the SPI driver for LPSPI0 */ + + struct spi_dev_s *g_lpspi0 = s32k3xx_lpspibus_initialize(0); + if (g_lpspi0 == NULL) + { + spierr("ERROR: FAILED to initialize LPSPI0\n"); + return -ENODEV; + } + +# ifdef CONFIG_SPI_DRIVER + ret = spi_register(g_lpspi0, 0); + if (ret < 0) + { + spierr("ERROR: FAILED to register LPSPI0 driver\n"); + return ret; + } +# endif /* CONFIG_SPI_DRIVER */ + +# ifdef CONFIG_S32K3XX_FS26 + fs26_initialize(g_lpspi0); +# endif + +#endif /* CONFIG_S32K3XX_LPSPI0 */ + +#ifdef CONFIG_S32K3XX_LPSPI1 + /* LPSPI1 *****************************************************************/ + + /* Configure LPSPI1 peripheral chip select */ + + s32k3xx_pinconfig(PIN_LPSPI1_PCS); + + /* Initialize the SPI driver for LPSPI1 */ + + struct spi_dev_s *g_lpspi1 = s32k3xx_lpspibus_initialize(1); + if (g_lpspi1 == NULL) + { + spierr("ERROR: FAILED to initialize LPSPI1\n"); + return -ENODEV; + } + +# ifdef CONFIG_SPI_DRIVER + ret = spi_register(g_lpspi1, 1); + if (ret < 0) + { + spierr("ERROR: FAILED to register LPSPI1 driver\n"); + return ret; + } +# endif /* CONFIG_SPI_DRIVER */ +#endif /* CONFIG_S32K3XX_LPSPI1 */ + +#ifdef CONFIG_S32K3XX_LPSPI2 + /* LPSPI2 *****************************************************************/ + + /* Configure LPSPI2 peripheral chip select */ + + s32k3xx_pinconfig(PIN_LPSPI2_PCS); + + /* Initialize the SPI driver for LPSPI2 */ + + struct spi_dev_s *g_lpspi2 = s32k3xx_lpspibus_initialize(2); + if (g_lpspi2 == NULL) + { + spierr("ERROR: FAILED to initialize LPSPI2\n"); + return -ENODEV; + } + +# ifdef CONFIG_SPI_DRIVER + ret = spi_register(g_lpspi2, 2); + if (ret < 0) + { + spierr("ERROR: FAILED to register LPSPI2 driver\n"); + return ret; + } +# endif /* CONFIG_SPI_DRIVER */ +#endif /* CONFIG_S32K3XX_LPSPI2 */ + +#ifdef CONFIG_S32K3XX_LPSPI3 + /* LPSPI3 *****************************************************************/ + + /* Configure LPSPI3 peripheral chip select */ + + s32k3xx_pinconfig(PIN_LPSPI3_PCS); + + /* Initialize the SPI driver for LPSPI3 */ + + struct spi_dev_s *g_lpspi3 = s32k3xx_lpspibus_initialize(3); + if (g_lpspi3 == NULL) + { + spierr("ERROR: FAILED to initialize LPSPI3\n"); + return -ENODEV; + } + +# ifdef CONFIG_SPI_DRIVER + ret = spi_register(g_lpspi3, 3); + if (ret < 0) + { + spierr("ERROR: FAILED to register LPSPI3 driver\n"); + return ret; + } +# endif /* CONFIG_SPI_DRIVER */ +#endif /* CONFIG_S32K3XX_LPSPI3 */ + +#ifdef CONFIG_S32K3XX_LPSPI4 + /* LPSPI4 *****************************************************************/ + + /* Configure LPSPI4 peripheral chip select */ + + s32k3xx_pinconfig(PIN_LPSPI4_PCS); + + /* Initialize the SPI driver for LPSPI4 */ + + struct spi_dev_s *g_lpspi4 = s32k3xx_lpspibus_initialize(4); + if (g_lpspi4 == NULL) + { + spierr("ERROR: FAILED to initialize LPSPI4\n"); + return -ENODEV; + } + +# ifdef CONFIG_SPI_DRIVER + ret = spi_register(g_lpspi4, 4); + if (ret < 0) + { + spierr("ERROR: FAILED to register LPSPI4 driver\n"); + return ret; + } +# endif /* CONFIG_SPI_DRIVER */ +#endif /* CONFIG_S32K3XX_LPSPI4 */ + +#ifdef CONFIG_S32K3XX_LPSPI5 + /* LPSPI5 *****************************************************************/ + + /* Configure LPSPI5 peripheral chip select */ + + s32k3xx_pinconfig(PIN_LPSPI5_PCS); + + /* Initialize the SPI driver for LPSPI5 */ + + struct spi_dev_s *g_lpspi5 = s32k3xx_lpspibus_initialize(5); + if (g_lpspi5 == NULL) + { + spierr("ERROR: FAILED to initialize LPSPI5\n"); + return -ENODEV; + } + +# ifdef CONFIG_SPI_DRIVER + ret = spi_register(g_lpspi5, 5); + if (ret < 0) + { + spierr("ERROR: FAILED to register LPSPI5 driver\n"); + return ret; + } +# endif /* CONFIG_SPI_DRIVER */ +#endif /* CONFIG_S32K3XX_LPSPI5 */ + + return ret; +} + +/**************************************************************************** + * Name: s32k3xx_lpspiNselect and s32k3xx_lpspiNstatus + * + * Description: + * The external functions, s32k3xx_lpspiNselect and s32k3xx_lpspiNstatus + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * s32k3xx_lpspibus_initialize()) are provided by common logic. To use + * this common SPI logic on your board: + * + * 1. Provide logic in s32k3xx_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide s32k3xx_lpspiNselect() and s32k3xx_lpspiNstatus() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to s32k3xx_lpspibus_initialize() in your low level + * application initialization logic. + * 4. The handle returned by s32k3xx_lpspibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_S32K3XX_LPSPI0 +/* LPSPI0 *******************************************************************/ + +void s32k3xx_lpspi0select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %" PRId32 ", CS: %s\n", devid, + selected ? "assert" : "de-assert"); + + s32k3xx_gpiowrite(PIN_LPSPI0_PCS, !selected); +} + +uint8_t s32k3xx_lpspi0status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif /* CONFIG_S32K3XX_LPSPI0 */ + +#ifdef CONFIG_S32K3XX_LPSPI1 +/* LPSPI1 *******************************************************************/ + +void s32k3xx_lpspi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %" PRId32 ", CS: %s\n", devid, + selected ? "assert" : "de-assert"); + + s32k3xx_gpiowrite(PIN_LPSPI1_PCS, !selected); +} + +uint8_t s32k3xx_lpspi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif /* CONFIG_S32K3XX_LPSPI1 */ + +#ifdef CONFIG_S32K3XX_LPSPI2 +/* LPSPI2 *******************************************************************/ + +void s32k3xx_lpspi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %" PRId32 ", CS: %s\n", devid, + selected ? "assert" : "de-assert"); + + s32k3xx_gpiowrite(PIN_LPSPI2_PCS, !selected); +} + +uint8_t s32k3xx_lpspi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif /* CONFIG_S32K3XX_LPSPI2 */ + +#ifdef CONFIG_S32K3XX_LPSPI3 +/* LPSPI3 *******************************************************************/ + +void s32k3xx_lpspi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %" PRId32 ", CS: %s\n", devid, + selected ? "assert" : "de-assert"); + + s32k3xx_gpiowrite(PIN_LPSPI3_PCS, !selected); +} + +uint8_t s32k3xx_lpspi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif /* CONFIG_S32K3XX_LPSPI3 */ + +#ifdef CONFIG_S32K3XX_LPSPI4 +/* LPSPI4 *******************************************************************/ + +void s32k3xx_lpspi4select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %" PRId32 ", CS: %s\n", devid, + selected ? "assert" : "de-assert"); + + s32k3xx_gpiowrite(PIN_LPSPI4_PCS, !selected); +} + +uint8_t s32k3xx_lpspi4status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif /* CONFIG_S32K3XX_LPSPI4 */ + +#ifdef CONFIG_S32K3XX_LPSPI5 +/* LPSPI5 *******************************************************************/ + +void s32k3xx_lpspi5select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %" PRId32 ", CS: %s\n", devid, + selected ? "assert" : "de-assert"); + + s32k3xx_gpiowrite(PIN_LPSPI5_PCS, !selected); +} + +uint8_t s32k3xx_lpspi5status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif /* CONFIG_S32K3XX_LPSPI5 */ +#endif /* CONFIG_S32K3XX_LPSPI */ diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c new file mode 100644 index 0000000000..daceb4fb28 --- /dev/null +++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c @@ -0,0 +1,124 @@ +/**************************************************************************** + * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "s32k3xx_pin.h" + +#include + +#include "s32k344evb.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIOs for output */ + + s32k3xx_pinconfig(GPIO_LED0_R); + s32k3xx_pinconfig(GPIO_LED0_G); + s32k3xx_pinconfig(GPIO_LED0_B); + + s32k3xx_pinconfig(GPIO_LED1_R); + s32k3xx_pinconfig(GPIO_LED1_G); + s32k3xx_pinconfig(GPIO_LED1_B); + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_LED0_R) + { + ledcfg = GPIO_LED0_R; + } + else if (led == BOARD_LED0_G) + { + ledcfg = GPIO_LED0_G; + } + else if (led == BOARD_LED0_B) + { + ledcfg = GPIO_LED0_B; + } + else if (led == BOARD_LED1_R) + { + ledcfg = GPIO_LED1_R; + } + else if (led == BOARD_LED1_G) + { + ledcfg = GPIO_LED1_G; + } + else if (led == BOARD_LED1_B) + { + ledcfg = GPIO_LED1_B; + } + else + { + return; + } + + /* An output of '1' illuminates the LED */ + + s32k3xx_gpiowrite(ledcfg, ledon); +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + /* An output of '1' illuminates the LED */ + + s32k3xx_gpiowrite(GPIO_LED0_R, (ledset & BOARD_LED0_R_BIT) != 0); + s32k3xx_gpiowrite(GPIO_LED0_G, (ledset & BOARD_LED0_G_BIT) != 0); + s32k3xx_gpiowrite(GPIO_LED0_B, (ledset & BOARD_LED0_B_BIT) != 0); + + s32k3xx_gpiowrite(GPIO_LED1_R, (ledset & BOARD_LED1_R_BIT) != 0); + s32k3xx_gpiowrite(GPIO_LED1_G, (ledset & BOARD_LED1_G_BIT) != 0); + s32k3xx_gpiowrite(GPIO_LED1_B, (ledset & BOARD_LED1_B_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */