From 7835e5bde84da9e26f03ec319e0c574eb9241407 Mon Sep 17 00:00:00 2001 From: ahb Date: Thu, 9 Mar 2017 11:33:09 +0100 Subject: [PATCH] actually write modified value to register --- arch/arm/src/lpc43xx/lpc43_ssp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/lpc43xx/lpc43_ssp.c b/arch/arm/src/lpc43xx/lpc43_ssp.c index 49f7c5781f..3d623ea4d0 100644 --- a/arch/arm/src/lpc43xx/lpc43_ssp.c +++ b/arch/arm/src/lpc43xx/lpc43_ssp.c @@ -380,6 +380,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode) if (mode != priv->mode) { + spiinfo("Setting mode to %d.\n", mode); /* Yes... Set CR0 appropriately */ regval = ssp_getreg(priv, LPC43_SSP_CR0_OFFSET); @@ -442,12 +443,14 @@ static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits) if (nbits != priv->nbits) { + spiinfo("Settings bits per word to %d.\n", nbits); /* Yes... Set CR1 appropriately */ regval = ssp_getreg(priv, LPC43_SSP_CR0_OFFSET); regval &= ~SSP_CR0_DSS_MASK; regval |= ((nbits - 1) << SSP_CR0_DSS_SHIFT); - regval = ssp_getreg(priv, LPC43_SSP_CR0_OFFSET); + ssp_putreg(priv, LPC43_SSP_CR0_OFFSET, regval); + spiinfo("SSP Control Register 0 (CR0) after setting DSS: 0x%08X.\n", regval); /* Save the selection so the subsequence re-configurations will be faster */