arch/z80/src/ez80/ez80_spi.c: Correct oversight in previous commit
Commit 797e45d6bf
attempted to reduce the frequency of SPI reconfiguration by keeping track of the current frequency and mode settings and changing these settings only when the new settings differ from the old settings.
However, the original commit neglected to save the new frequency setting and, hence, was not effective in what it was trying to do: Every time the SPI setfrequency() method was called, it still looked like a new frequency and the frequency was still reconfigured, even though it hadn't really changed.
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@ -236,7 +236,8 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
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outp(EZ80_SPI_BRG_L, brg & 0xff);
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outp(EZ80_SPI_BRG_H, (brg >> 8) & 0xff);
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g_spi_actual = ((EZ80_SYS_CLK_FREQ + 1) / 2 + brg - 1) / brg;
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g_spi_frequency = frequency;
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g_spi_actual = ((EZ80_SYS_CLK_FREQ + 1) / 2 + brg - 1) / brg;
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finfo("BRG=%lu Actual=%lu\n",
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(unsigned long)brg, (unsigned long)g_spi_actual);
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@ -580,10 +581,10 @@ static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
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* prior to calling this function. Specifically: GPIOs should have
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* been configured for output, and all chip selects disabled.
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*
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* One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select. However,
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* If multiple devices on on the bus, then multiple chip selects will be
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* required. Therefore, all GPIO chip management is deferred to board-
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* specific logic.
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* One GPIO, SS (PB2 on the eZ8F091) is reserved as a chip select.
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* However, if multiple devices on on the bus, then multiple chip
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* selects will be required. Therefore, all GPIO chip management is
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* deferred to board-specific logic.
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*
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* Input Parameters:
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* Port number (for hardware that has multiple SPI interfaces)
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@ -86,10 +86,6 @@
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* Chip select 3 is not used
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*/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* RAM Memory map
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*
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* 040000 Beginning of RAM
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