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arch: arm: xmc4: fix nxstyle errors

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Fix nxstyle errors to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea 2021-03-24 09:39:01 +01:00 committed by Xiang Xiao
parent f2f0193960
commit 7869b7185b
13 changed files with 394 additions and 179 deletions
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23
arch/arm/src/xmc4/chip.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/xmc4/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,33 +16,34 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_CHIP_H
#define __ARCH_ARM_SRC_XMC4_CHIP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/* Include the memory map and the chip definitions file. Other chip hardware files
* should then include this file for the proper setup.
/* Include the memory map and the chip definitions file.
* Other chip hardware files should then include this file for the proper
* setup.
*/
#include <arch/irq.h>
#include <arch/xmc4/chip.h>
#include "hardware/xmc4_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* If the common ARMv7-M vector handling logic is used, then it expects the
* following definition in this file that provides the number of supported external
* interrupts which, for this architecture, is provided in the arch/xmc4/chip.h
* header file.
* following definition in this file that provides the number of supported
* external interrupts which, for this architecture, is provided in the
* arch/xmc4/chip.h header file.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS XMC4_IRQ_NEXTINTS

167
arch/arm/src/xmc4/hardware/xmc4_ethernet.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************************************
/****************************************************************************
* arch/arm/src/xmc4/hardware/xmc4_ethernet.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
@ -37,34 +37,34 @@
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
* Infineon Technologies AG (Infineon) is supplying this software for use
* with Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS
* SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
********************************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_ETHERNET_H
#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_ETHERNET_H
/********************************************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/xmc4_memorymap.h"
/********************************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************************************/
****************************************************************************/
/* Register Offsets *************************************************************************************************/
/* Register Offsets *********************************************************/
/* MAC Configuration Registers */
@ -195,7 +195,7 @@
#define XMC4_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_OFFSET 0x0724 /* System Time - Higher Word Seconds Register */
#define XMC4_ETH_TIMESTAMP_STATUS_OFFSET 0x0728 /* Timestamp Status Register */
/* DMA Registers*/
/* DMA Registers */
#define XMC4_ETH_BUS_MODE_OFFSET 0x1000 /* Bus Mode Register */
#define XMC4_ETH_TRANSMIT_POLL_DEMAND_OFFSET 0x1004 /* Transmit Poll Demand Register */
@ -214,7 +214,7 @@
#define XMC4_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_OFFSET 0x1054 /* Current Host Receive Buffer Address Register */
#define XMC4_ETH_HW_FEATURE_OFFSET 0x1058 /* HW Feature Register */
/* Register Addresses ***********************************************************************************************/
/* Register Addresses *******************************************************/
/* MAC Configuration Registers */
@ -344,7 +344,7 @@
#define XMC4_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS (XMC4_ETH0_BASE+XMC4_ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_OFFSET)
#define XMC4_ETH_TIMESTAMP_STATUS (XMC4_ETH0_BASE+XMC4_ETH_TIMESTAMP_STATUS_OFFSET)
/* DMA Registers*/
/* DMA Registers */
#define XMC4_ETH_BUS_MODE (XMC4_ETH0_BASE+XMC4_ETH_BUS_MODE_OFFSET)
#define XMC4_ETH_TRANSMIT_POLL_DEMAND (XMC4_ETH0_BASE+XMC4_ETH_TRANSMIT_POLL_DEMAND_OFFSET)
@ -363,50 +363,70 @@
#define XMC4_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS (XMC4_ETH0_BASE+XMC4_ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_OFFSET)
#define XMC4_ETH_HW_FEATURE (XMC4_ETH0_BASE+XMC4_ETH_HW_FEATURE_OFFSET)
/* Register Bit-Field Definitions ***********************************************************************************/
/* Register Bit-Field Definitions *******************************************/
/* MAC Configuration Registers */
/* MAC Configuration Register */
#define ETH_MAC_CONFIGURATION_
/* MAC Frame Filter */
#define ETH_MAC_FRAME_FILTER_
/* Hash Table High Register */
#define ETH_HASH_TABLE_LOW_
/* MII Address Register */
#define ETH_GMII_ADDRESS_
/* MII Data Register */
#define ETH_GMII_DATA_
/* Flow Control Register */
#define ETH_FLOW_CONTROL_
/* VLAN Tag Register */
#define ETH_VLAN_TAG_
/* Version Register */
#define ETH_VERSION_
/* Debug Register */
#define ETH_DEBUG_
/* Remote Wake Up Frame Filter Register */
#define ETH_REMOTE_WAKE_UP_FRAME_FILTER_
/* PMT Control and Status Register */
#define ETH_PMT_CONTROL_STATUS_
/* Interrupt Register */
#define ETH_INTERRUPT_STATUS_
/* Interrupt Mask Register */
#define ETH_INTERRUPT_MASK_
/* MAC Address0 High Register */
#define ETH_MAC_ADDRESS0_HIGH_
/* MAC Address0 Low Register */
#define ETH_MAC_ADDRESS0_LOW_
/* MAC Address1 High Register */
#define ETH_MAC_ADDRESS1_HIGH_
/* MAC Address1 Low Register */
#define ETH_MAC_ADDRESS1_LOW_
/* MAC Address2 High Register */
#define ETH_MAC_ADDRESS2_HIGH_
/* MAC Address2 Low Register */
#define ETH_MAC_ADDRESS2_LOW_
/* MAC Address3 High Register */
#define ETH_MAC_ADDRESS3_HIGH_
/* MAC Address3 Low Register */
#define ETH_MAC_ADDRESS3_LOW_
@ -414,176 +434,262 @@
/* MMC Control Register */
#define ETH_MMC_CONTROL_
/* MMC Receive Interrupt Register */
#define ETH_MMC_RECEIVE_INTERRUPT_
/* MMC Transmit Interrupt Register */
#define ETH_MMC_TRANSMIT_INTERRUPT_
/* MMC Receive Interrupt Mask Register */
#define ETH_MMC_RECEIVE_INTERRUPT_MASK_
/* MMC Transmit Interrupt Mask Register */
#define ETH_MMC_TRANSMIT_INTERRUPT_MASK_
/* Transmit Octet Count for Good and Bad Frames Register */
#define ETH_TX_OCTET_GOODBAD_COUNT_
/* Transmit Frame Count for Goodand Bad Frames Register */
#define ETH_TX_FRAME_GOODBAD_COUNT_
/* Transmit Frame Count for Good Broadcast Frames */
#define ETH_TX_BROADCAST_GOOD_FRAMES_
/* Transmit Frame Count for Good Multicast Frames */
#define ETH_TX_MULTICAST_GOOD_FRAMES_
/* Transmit Octet Count for Good and Bad 64 Byte Frames */
#define ETH_TX_64OCTETS_FRAMES_
/* Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames */
#define ETH_TX_65TO127OCTETS_FRAMES_
/* Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames */
#define ETH_TX_128TO255OCTETS_FRAMES_
/* Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames */
#define ETH_TX_256TO511OCTETS_FRAMES_
/* Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames */
#define ETH_TX_512TO1023OCTETS_FRAMES_
/* Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames */
#define ETH_TX_1024TOMAXOCTETS_FRAMES_
/* Transmit Frame Count for Good and Bad Unicast Frames */
#define ETH_TX_UNICAST_FRAMES_
/* Transmit Frame Count for Good and Bad Multicast Frames */
#define ETH_TX_MULTICAST_GOODBAD_FRAMES_
/* Transmit Frame Count for Good and Bad Broadcast Frames */
#define ETH_TX_BROADCAST_GOODBAD_FRAMES_
/* Transmit Frame Count for Underflow Error Frames */
#define ETH_TX_UNDERFLOW_ERROR_FRAMES_
/* Transmit Frame Count for Frames Transmitted after Single Collision */
#define ETH_TX_SINGLE_COLLISION_FRAMES_
/* Transmit Frame Count for Frames Transmitted after Multiple Collision */
#define ETH_TX_MULTIPLE_COLLISION_FRAMES_
/* Tx Deferred Frames Register */
#define ETH_TX_DEFERRED_FRAMES_
/* Transmit Frame Count for Late Collision Error Frames */
#define ETH_TX_LATE_COLLISION_FRAMES_
/* Transmit Frame Count for Excessive Collision Error Frames */
#define ETH_TX_EXCESSIVE_COLLISION_FRAMES_
/* Transmit Frame Count for Carrier Sense Error Frames */
#define ETH_TX_CARRIER_ERROR_FRAMES_
/* Tx Octet Count Good Register */
#define ETH_TX_OCTET_GOOD_COUNT_
/* Tx Frame Count Good Register */
#define ETH_TX_FRAME_GOOD_COUNT_
/* Transmit Frame Count for Excessive Deferral Error Frames */
#define ETH_TX_EXCESSIVE_DEFERRAL_ERROR_
/* Transmit Frame Count for Good PAUSE Frames */
#define ETH_TX_PAUSE_FRAMES_
/* Transmit Frame Count for Good VLAN Frames */
#define ETH_TX_VLAN_FRAMES_
/* Transmit Frame Count for Good Oversize Frames */
#define ETH_TX_OSIZE_FRAMES_
/* Receive Frame Count for Goand Bad Frames */
#define ETH_RX_FRAMES_COUNT_
/* Receive Octet Count for Good and Bad Frames */
#define ETH_RX_OCTET_GOODBAD_COUNT_
/* Rx Octet Count Good Register */
#define ETH_RX_OCTET_GOOD_COUNT_
/* Receive Frame Count for Good Broadcast Frames */
#define ETH_RX_BROADCAST_FRAMES_
/* Receive Frame Count for Good Multicast Frames */
#define ETH_RX_MULTICAST_FRAMES_
/* Receive Frame Count for CRC Error Frames */
#define ETH_RX_CRC_ERROR_FRAMES_
/* Receive Frame Count for Alignment Error Frames */
#define ETH_RX_ALIGNMENT_ERROR_FRAMES_
/* Receive Frame Count for Runt Error Frames */
#define ETH_RX_RUNT_ERROR_FRAMES_
/* Receive Frame Count for Jabber Error Frames */
#define ETH_RX_JABBER_ERROR_FRAMES_
/* Receive Frame Count for Undersize Frames */
#define ETH_RX_UNDERSIZE_FRAMES_
/* Rx Oversize Frames Good Register */
#define ETH_RX_OVERSIZE_FRAMES_
/* Receive Frame Count for Good and Bad 64 Byte Frames */
#define ETH_RX_64OCTETS_FRAMES_
/* Receive Frame Count for Good and Bad 65 to 127 Bytes Frames */
#define ETH_RX_65TO127OCTETS_FRAMES_
/* Receive Frame Count for Good and Bad 128 to 255 Bytes Frames */
#define ETH_RX_128TO255OCTETS_FRAMES_
/* Receive Frame Count for Good and Bad 256 to 511 Bytes Frames */
#define ETH_RX_256TO511OCTETS_FRAMES_
/* Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames */
#define ETH_RX_512TO1023OCTETS_FRAMES_
/* Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames */
#define ETH_RX_1024TOMAXOCTETS_FRAMES_
/* Receive Frame Count for Good Unicast Frames */
#define ETH_RX_UNICAST_FRAMES_
/* Receive Frame Count for Length Error Frames */
#define ETH_RX_LENGTH_ERROR_FRAMES_
/* Receive Frame Count for Out of Range Frames */
#define ETH_RX_OUT_OF_RANGE_TYPE_FRAMES_
/* Receive Frame Count for PAUSE Frames */
#define ETH_RX_PAUSE_FRAMES_
/* Receive Frame Count for FIFO Overflow Frames */
#define ETH_RX_FIFO_OVERFLOW_FRAMES_
/* Receive Frame Count for Good and Bad VLAN Frames */
#define ETH_RX_VLAN_FRAMES_
/* Receive Frame Count for Watchdog Error Frames */
#define ETH_RX_WATCHDOG_ERROR_FRAMES_
/* Receive Frame Count for Receive Error Frames */
#define ETH_RX_RECEIVE_ERROR_FRAMES_
/* Receive Frame Count for Good Control Frames Frames */
#define ETH_RX_CONTROL_FRAMES_
/* MMC Receive Checksum Offload Interrupt Mask Register */
#define ETH_MMC_IPC_RECEIVE_INTERRUPT_MASK_
/* MMC Receive Checksum Offload Interrupt Register */
#define ETH_MMC_IPC_RECEIVE_INTERRUPT_
/* RxIPv4 Good Frames Register */
#define ETH_RXIPV4_GOOD_FRAMES_
/* Receive IPV4 Header Error Frame Counter Register */
#define ETH_RXIPV4_HEADER_ERROR_FRAMES_
/* Receive IPV4 No Payload Frame Counter Register */
#define ETH_RXIPV4_NO_PAYLOAD_FRAMES_
/* Receive IPV4 Fragmented Frame Counter Register */
#define ETH_RXIPV4_FRAGMENTED_FRAMES_
/* Receive IPV4 UDP Checksum Disabled Frame Counter Register */
#define ETH_RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES_
/* RxIPv6 Good Frames Register */
#define ETH_RXIPV6_GOOD_FRAMES_
/* Receive IPV6 Header Error Frame Counter Register */
#define ETH_RXIPV6_HEADER_ERROR_FRAMES_
/* Receive IPV6 No Payload Frame Counter Register */
#define ETH_RXIPV6_NO_PAYLOAD_FRAMES_
/* RxUDP Good Frames Register */
#define ETH_RXUDP_GOOD_FRAMES_
/* RxUDP Error Frames Register */
#define ETH_RXUDP_ERROR_FRAMES_
/* RxTCP Good Frames Register */
#define ETH_RXTCP_GOOD_FRAMES_
/* RxTCP Error Frames Register */
#define ETH_RXTCP_ERROR_FRAMES_
/* RxICMP Good Frames Register */
#define ETH_RXICMP_GOOD_FRAMES_
/* RxICMP Error Frames Register */
#define ETH_RXICMP_ERROR_FRAMES_
/* RxIPv4 Good Octets Register */
#define ETH_RXIPV4_GOOD_OCTETS_
/* Receive IPV4 Header Error Octet Counter Register */
#define ETH_RXIPV4_HEADER_ERROR_OCTETS_
/* Receive IPV4 No Payload Octet Counter Register */
#define ETH_RXIPV4_NO_PAYLOAD_OCTETS_
/* Receive IPV4 Fragmented Octet Counter Register */
#define ETH_RXIPV4_FRAGMENTED_OCTETS_
/* Receive IPV4 Fragmented Octet Counter Register */
#define ETH_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_
/* RxIPv6 Good Octets Register */
#define ETH_RXIPV6_GOOD_OCTETS_
/* Receive IPV6 Header Error Octet Counter Register */
#define ETH_RXIPV6_HEADER_ERROR_OCTETS_
/* Receive IPV6 No Payload Octet Counter Register */
#define ETH_RXIPV6_NO_PAYLOAD_OCTETS_
/* Receive UDP Good Octets Register */
#define ETH_RXUDP_GOOD_OCTETS_
/* Receive UDP Error Octets Register */
#define ETH_RXUDP_ERROR_OCTETS_
/* Receive TCP Good Octets Register */
#define ETH_RXTCP_GOOD_OCTETS_
/* Receive TCP Error Octets Register */
#define ETH_RXTCP_ERROR_OCTETS_
/* Receive ICMP Good Octets Register */
#define ETH_RXICMP_GOOD_OCTETS_
/* Receive ICMP Error Octets Register */
#define ETH_RXICMP_ERROR_OCTETS_
@ -591,59 +697,84 @@
/* Timestamp Control Register */
#define ETH_TIMESTAMP_CONTROL_
/* Sub-Second Increment Register */
#define ETH_SUB_SECOND_INCREMENT_
/* System Time - Seconds Register */
#define ETH_SYSTEM_TIME_SECONDS_
/* System Time Nanoseconds Register */
#define ETH_SYSTEM_TIME_NANOSECONDS_
/* System Time - Seconds Update Register */
#define ETH_SYSTEM_TIME_SECONDS_UPDATE_
/* System Time Nanoseconds Update Register */
#define ETH_SYSTEM_TIME_NANOSECONDS_UPDATE_
/* Timestamp Addend Register */
#define ETH_TIMESTAMP_ADDEND_
/* Target Time Seconds Register */
#define ETH_TARGET_TIME_SECONDS_
/* Target Time Nanoseconds Register */
#define ETH_TARGET_TIME_NANOSECONDS_
/* System Time - Higher Word Seconds Register */
#define ETH_SYSTEM_TIME_HIGHER_WORD_SECONDS_
/* Timestamp Status Register */
#define ETH_TIMESTAMP_STATUS_
/* DMA Registers*/
/* DMA Registers */
/* Bus Mode Register */
#define ETH_BUS_MODE_
/* Transmit Poll Demand Register */
#define ETH_TRANSMIT_POLL_DEMAND_
/* Receive Poll Demand Register */
#define ETH_RECEIVE_POLL_DEMAND_
/* Receive Descriptor Address Register */
#define ETH_RECEIVE_DESCRIPTOR_LIST_ADDRESS_
/* Transmit descripter Address Register */
#define ETH_TRANSMIT_DESCRIPTOR_LIST_ADDRESS_
/* Status Register */
#define ETH_STATUS_
/* Operation Mode Register */
#define ETH_OPERATION_MODE_
/* Interrupt Enable Register */
#define ETH_INTERRUPT_ENABLE_
/* Missed Frame and Buffer Overflow Counter Register */
#define ETH_MISSED_FRAME_BUFFER_OVERFLOW_COUNTER_
/* Receive Interrupt Watchdog Timer Register */
#define ETH_RECEIVE_INTERRUPT_WATCHDOG_TIMER_
/* AHB Status Register */
#define ETH_AHB_STATUS_
/* Current Host Transmit Descriptor Register */
#define ETH_CURRENT_HOST_TRANSMIT_DESCRIPTOR_
/* Current Host Receive Descriptor Register */
#define ETH_CURRENT_HOST_RECEIVE_DESCRIPTOR_
/* Current Host Transmit Buffer Address Register */
#define ETH_CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS_
/* Current Host Receive Buffer Address Register */
#define ETH_CURRENT_HOST_RECEIVE_BUFFER_ADDRESS_
/* HW Feature Register */
#define ETH_HW_FEATURE_

31
arch/arm/src/xmc4/hardware/xmc4_flash.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/xmc4/hardware/xmc4_flash.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
@ -37,36 +37,37 @@
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
* Infineon Technologies AG (Infineon) is supplying this software for use
* with Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS
* SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_FLASH_H
#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_FLASH_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/xmc4_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
/* PMU Registers -- See ID register */
/* Prefetch Registers -- See PCON register */
/* FLASH Registers */
@ -79,7 +80,7 @@
#define XMC4_FLASH_PROCON1_OFFSET 0x1024 /* Flash Protection Configuration User 1 */
#define XMC4_FLASH_PROCON2_OFFSET 0x1028 /* Flash Protection Configuration User 2 */
/* Register Addresses ****************************************************************/
/* Register Addresses *******************************************************/
/* FLASH Registers */
@ -91,7 +92,7 @@
#define XMC4_FLASH_PROCON1 (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON1_OFFSET)
#define XMC4_FLASH_PROCON2 (XMC4_FLASH0_BASE+XMC4_FLASH_PROCON2_OFFSET)
/* Register Bit-Field Definitions **************************************************/
/* Register Bit-Field Definitions *******************************************/
/* FLASH Registers */

27
arch/arm/src/xmc4/hardware/xmc4_memorymap.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/xmc4/hardware/xmc4_memorymap.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
@ -37,32 +37,33 @@
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
* Infineon Technologies AG (Infineon) is supplying this software for use
* with Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS
* SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_MEMORYMAP_H
#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Peripheral Memory Map ****************************************************/
/* Peripheral Memory Map ************************************************************/
/* Acronyms:
* ADC - Analog to Digital Converter
* CCU - Capture Compare Unit

33
arch/arm/src/xmc4/hardware/xmc4_pinmux.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/xmc4/hardware/xmc4_pinmux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,40 +16,43 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
/* Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. */
#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_PINMUX_H
#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_PINMUX_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Alternate Pin Functions. All members of the XMC4xxx family share the same
* pin multiplexing (although they may differ in the pins physically available).
* pin multiplexing (although they may differ in the pins physically
* available).
*
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Alternative pin selections are provided with a numeric suffix like _1, _2,
* etc. Drivers, however, will use the pin selection without the numeric
* suffix.
* Additional definitions are required in the board.h file. For example, if
* CAN_N2TXD connects vis P1.9 on some board, then the following definition should
* appear in the board.h header file for that board:
* CAN_N2TXD connects vis P1.9 on some board, then the following definition
* should appear in the board.h header file for that board:
*
* #define GPIO_CAN_N2TXD GPIO_CAN_N2TXD_1
*
* The driver will then automatically configure PA11 as the CAN1 RX pin.
*/
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in this file.
/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down! Just the basics are
* defined for most pins in this file.
*/
#define GPIO_CAN_N0RXDA (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN5)

37
arch/arm/src/xmc4/hardware/xmc4_ports.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/xmc4/hardware/xmc4_ports.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
@ -37,34 +37,34 @@
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
* Infineon Technologies AG (Infineon) is supplying this software for use
* with Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS
* SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_PORTS_H
#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_PORTS_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/xmc4_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
/* PORTS Registers */
@ -87,7 +87,7 @@
#define XMC4_PORT_PPS_OFFSET 0x0070 /* Port Pin Power Save Register */
#define XMC4_PORT_HWSEL_OFFSET 0x0074 /* Port Pin Hardware Select Register */
/* Register Addresses ****************************************************************/
/* Register Addresses *******************************************************/
#define XMC4_PORT0_OUT (XMC4_PORT0_BASE+XMC4_PORT_OUT_OFFSET)
#define XMC4_PORT0_OMR (XMC4_PORT0_BASE+XMC4_PORT_OMR_OFFSET)
@ -245,9 +245,10 @@
#define XMC4_PORT15_PPS (XMC4_PORT15_BASE+XMC4_PORT_PPS_OFFSET)
#define XMC4_PORT15_HWSEL (XMC4_PORT15_BASE+XMC4_PORT_HWSEL_OFFSET)
/* Register Bit-Field Definitions **************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Port Output Register, , Port Input Register, Port Pin Function Decision Control
/* Port Output Register, , Port Input Register,
* Port Pin Function Decision Control
* Register, Port Pin Power Save Register.
*/
@ -266,6 +267,7 @@
#define OMR_PR(n) (1 << ((n) + 16))
/* Basic port input/output field values */
/* Direct Input */
#define IOCR_INPUT_NOPULL 0 /* No internal pull device active */
@ -275,6 +277,7 @@
* continuously samples the input value */
/* Any of the above input configurations may be OR'ed with */
/* Inverted Input */
#define IOCR_INPUT_INVERT 4 /* Inverted input modifier */
@ -288,6 +291,7 @@
#define IOCR_OUTPUT_ALT4 20 /* Alternate output function 4 */
/* Any of the above may be OR'ed with */
/* Open drain output */
#define IOCR_OUTPUT_OPENDRAIN 8 /* Output drain output modifier */
@ -365,6 +369,7 @@
# define PORT_IOCR12_PC15(n) ((uint32_t)(n) << PORT_IOCR12_PC15_SHIFT)
/* Pad driver field values */
/* Pad class A1: */
#define PDR_PADA1_MEDIUM 0 /* Medium driver */

101
arch/arm/src/xmc4/hardware/xmc4_scu.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/xmc4/hardware/xmc4_scu.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
@ -35,35 +35,36 @@
*
* May include some logic from sample code provided by Infineon:
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
* Infineon Technologies AG (Infineon) is supplying this software for use
* with Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS
* SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_SCU_H
#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_SCU_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/xmc4_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************/
/* Register Offsets *****************************************************************/
/* General SCU Registers */
#define XMC4_SCU_ID_OFFSET 0x0000 /* Module Identification Register */
@ -194,7 +195,8 @@
#define XMC4_SCU_USBPLLCON_OFFSET 0x0014 /* USB PLL Control Register */
#define XMC4_SCU_CLKMXSTAT_OFFSET 0x0028 /* Clock Multiplexing Status Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
/* General SCU Registers */
#define XMC4_SCU_ID (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ID_OFFSET)
@ -325,7 +327,7 @@
#define XMC4_SCU_USBPLLCON (XMC4_SCU_PLL_BASE+XMC4_SCU_USBPLLCON_OFFSET)
#define XMC4_SCU_CLKMXSTAT (XMC4_SCU_PLL_BASE+XMC4_SCU_CLKMXSTAT_OFFSET)
/* Register Bit-Field Definitions ***************************************************/
/* Register Bit-Field Definitions *******************************************/
/* General SCU Registers */
@ -355,6 +357,7 @@
# define SCU_STCON_HWCON_ACBSL (1 << SCU_STCON_HWCON_SHIFT) /* ASC BSL enabled */
# define SCU_STCON_HWCON_BMI (2 << SCU_STCON_HWCON_SHIFT) /* BMI customized boot enabled */
# define SCU_STCON_HWCON_CANBSL (3 << SCU_STCON_HWCON_SHIFT) /* CAN BSL enabled */
#define SCU_STCON_SWCON_SHIFT (8) /* Bits 8-11: SW Configuration */
#define SCU_STCON_SWCON_MASK (15 << SCU_STCON_SWCON_SHIFT)
# define SCU_STCON_SWCON_ ROM (0 << SCU_STCON_SWCON_SHIFT) /* Normal boot from Boot ROM */
@ -376,66 +379,77 @@
# define SCU_ETH0CON_RXD0B (1 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0B is selected */
# define SCU_ETH0CON_RXD0C (2 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0C is selected */
# define SCU_ETH0CON_RXD0D (3 << SCU_ETH0CON_RXD0_SHIFT) /* Data input RXD0D is selected */
#define SCU_ETH0CON_RXD1_SHIFT (2) /* Bits 2-3: MAC Receive Input 1 */
#define SCU_ETH0CON_RXD1_MASK (3 << SCU_ETH0CON_RXD1_SHIFT)
# define SCU_ETH0CON_RXD1A (0 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1A is selected */
# define SCU_ETH0CON_RXD1B (1 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1B is selected */
# define SCU_ETH0CON_RXD1C (2 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1C is selected */
# define SCU_ETH0CON_RXD1D (3 << SCU_ETH0CON_RXD1_SHIFT) /* Data input RXD1D is selected */
#define SCU_ETH0CON_RXD2_SHIFT (4) /* Bits 4-5: MAC Receive Input 2 */
#define SCU_ETH0CON_RXD2_MASK (3 << SCU_ETH0CON_RXD2_SHIFT)
# define SCU_ETH0CON_RXD2A (0 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2A is selected */
# define SCU_ETH0CON_RXD2B (1 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2B is selected */
# define SCU_ETH0CON_RXD2C (2 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2C is selected */
# define SCU_ETH0CON_RXD2D (3 << SCU_ETH0CON_RXD2_SHIFT) /* Data input RXD2D is selected */
#define SCU_ETH0CON_RXD3_SHIFT (6) /* Bits 6-7: MAC Receive Input 3 */
#define SCU_ETH0CON_RXD3_MASK (3 << SCU_ETH0CON_RXD3_SHIFT)
# define SCU_ETH0CON_RXD3A (0 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3A is selected */
# define SCU_ETH0CON_RXD3B (1 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3B is selected */
# define SCU_ETH0CON_RXD3C (2 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3C is selected */
# define SCU_ETH0CON_RXD3D (3 << SCU_ETH0CON_RXD3_SHIFT) /* Data input RXD3D is selected */
#define SCU_ETH0CON_CLKRMII_SHIFT (8) /* Bits 8-9: RMII clock input */
#define SCU_ETH0CON_CLKRMII_MASK (3 << SCU_ETH0CON_CLKRMII_SHIFT)
# define SCU_ETH0CON_CLKRMIIA (0 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIIA is selected */
# define SCU_ETH0CON_CLKRMIIB (1 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIIB is selected */
# define SCU_ETH0CON_CLKRMIIC (2 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIIC is selected */
# define SCU_ETH0CON_CLKRMIID (3 << SCU_ETH0CON_CLKRMII_SHIFT) /* Data input RMIID is selected */
#define SCU_ETH0CON_CRSDV_SHIFT (10) /* Bits 10-11: CRS_DV input */
#define SCU_ETH0CON_CRSDV_MASK (3 << SCU_ETH0CON_CRSDV_SHIFT)
# define SCU_ETH0CON_CRSDVA (0 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVA is selected */
# define SCU_ETH0CON_CRSDVB (1 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVB is selected */
# define SCU_ETH0CON_CRSDVC (2 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVC is selected */
# define SCU_ETH0CON_CRSDVD (3 << SCU_ETH0CON_CRSDV_SHIFT) /* Data input CRS_DVD is selected */
#define SCU_ETH0CON_CRS_SHIFT (12) /* Bits 12-13: CRS input */
#define SCU_ETH0CON_CRS_MASK (3 << SCU_ETH0CON_CRS_SHIFT)
# define SCU_ETH0CON_CRSA (0 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSA is selected */
# define SCU_ETH0CON_CRSB (1 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSB is selected */
# define SCU_ETH0CON_CRSC (2 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSC is selected */
# define SCU_ETH0CON_CRSD (3 << SCU_ETH0CON_CRS_SHIFT) /* Data input CRSD is selected */
#define SCU_ETH0CON_RXER_SHIFT (14) /* Bits 14-15: RXER Input */
#define SCU_ETH0CON_RXER_MASK (3 << SCU_ETH0CON_RXER_SHIFT)
# define SCU_ETH0CON_RXERA (0 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERA is selected */
# define SCU_ETH0CON_RXERB (1 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERB is selected */
# define SCU_ETH0CON_RXERC (2 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERC is selected */
# define SCU_ETH0CON_RXERD (3 << SCU_ETH0CON_RXER_SHIFT) /* Data input RXERD is selected */
#define SCU_ETH0CON_COL_SHIFT (16) /* Bits 16-17: COL input */
#define SCU_ETH0CON_COL_MASK (3 << SCU_ETH0CON_COL_SHIFT)
# define SCU_ETH0CON_COLA (0 << SCU_ETH0CON_COL_SHIFT) /* Data input COLA is selected */
# define SCU_ETH0CON_COLB (1 << SCU_ETH0CON_COL_SHIFT) /* Data input COLB is selected */
# define SCU_ETH0CON_COLC (2 << SCU_ETH0CON_COL_SHIFT) /* Data input COLC is selected */
# define SCU_ETH0CON_COLD (3 << SCU_ETH0CON_COL_SHIFT) /* Data input COLD is selected */
#define SCU_ETH0CON_CLKTX_SHIFT (18) /* Bits 18-19: CLK_TX input */
#define SCU_ETH0CON_CLKTX_MASK (3 << SCU_ETH0CON_CLKTX_SHIFT)
# define SCU_ETH0CON_CLKTXA (0 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXA is selected */
# define SCU_ETH0CON_CLKTXB (1 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXB is selected */
# define SCU_ETH0CON_CLKTXC (2 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXC is selected */
# define SCU_ETH0CON_CLKTXD (3 << SCU_ETH0CON_CLKTX_SHIFT) /* Data input CLK_TXD is selected */
#define SCU_ETH0CON_MDIO_SHIFT (22) /* Bits 22-23: MDIO Input Select */
#define SCU_ETH0CON_MDIO_MASK (3 << SCU_ETH0CON_MDIO_SHIFT)
# define SCU_ETH0CON_MDIOA (0 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOA is selected */
# define SCU_ETH0CON_MDIOB (1 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOB is selected */
# define SCU_ETH0CON_MDIOC (2 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOC is selected */
# define SCU_ETH0CON_MDIOD (3 << SCU_ETH0CON_MDIO_SHIFT) /* Data input MDIOD is selected */
#define SCU_ETH0CON_INFSEL (1 << 26) /* Bit 26: Ethernet MAC Interface Selection */
# define SCU_ETH0CON_INFSEL_MII (0) /* 0=MII */
# define SCU_ETH0CON_INFSEL_RMII (1 << 26) /* 1=RMII */
@ -480,7 +494,9 @@
#define SCU_SDMMCDEL_TAPDEL_MASK (15 << SCU_SDMMCDEL_TAPDEL_SHIFT)
# define SCU_SDMMCDEL_TAPDEL(n) ((uint32_t)((n)-1) << SCU_SDMMCDEL_TAPDEL_SHIFT)
/* Out-Of-Range Comparator Enable Register 0 and Out-Of-Range Comparator Enable Register 1 */
/* Out-Of-Range Comparator Enable Register 0 and
* Out-Of-Range Comparator Enable Register 1
*/
#define SCU_GORCEN_ENORC6 (1 << 6) /* Bit 6: Enable Out of Range Comparator, Channel 6 */
#define SCU_GORCEN_ENORC7 (1 << 7) /* Bit 7: Enable Out of Range Comparator, Channel 7 */
@ -511,8 +527,8 @@
/* Interrupt Control SCU Registers */
/* Service Request Status, RAW Service Request Status, Service Request Mask, Service
* Request Clear, Service Request Set
/* Service Request Status, RAW Service Request Status,
* Service Request Mask, Service Request Clear, Service Request Set
*/
#define SCU_INT_PRWARN (1 << 0) /* Bit 0: WDT pre-warning Interrupt */
@ -649,8 +665,8 @@
/* Trap Control Registers */
/* Trap Status Register, Trap Raw Status Register, Trap Mask Register, Trap Clear
* Register, and Trap Set Register
/* Trap Status Register, Trap Raw Status Register,
* Trap Mask Register, Trap Clear Register, and Trap Set Register
*/
#define SCU_TRAP_SOSCWDGT (1 << 0) /* Bit 0: OSC_HP Oscillator Watchdog Trap */
@ -695,6 +711,7 @@
#define SCU_PWRMON_ENB (1 << 16) /* Bit 16: Enable */
/* Hibernation SCU Registers */
/* Hibernate Domain Status Register */
#define SCU_HDSTAT_EPEV (1 << 0) /* Bit 0: Wake-up Pin Event Positive Edge Status */
@ -753,6 +770,7 @@
# define SCU_HDCR_HIBIO0SEL_OD (12 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Open-drain HIB Control output */
# define SCU_HDCR_HIBIO0SEL_ODWDT (13 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Open-drain WDT service output */
# define SCU_HDCR_HIBIO0SEL_ODGPIO (14 << SCU_HDCR_HIBIO0SEL_SHIFT) /* Open-drain GPIO output */
#define SCU_HDCR_HIBIO1SEL_SHIFT (20) /* Bits 20-23: HIB_IO_1 Pin I/O Control */
#define SCU_HDCR_HIBIO1SEL_MASK (15 << SCU_HDCR_HIBIO1SEL_SHIFT)
# define SCU_HDCR_HIBIO1SEL_DIR (0 << SCU_HDCR_HIBIO1SEL_SHIFT) /* Direct input */
@ -814,8 +832,8 @@
#define SCU_RSTCLR_HIBRS (1 << 9) /* Bit 9: Clear Hibernate Reset */
#define SCU_RSTCLR_LCKEN (1 << 10) /* Bit 10: Clear Hibernate Reset */
/* Peripheral Reset Status Register 0, Peripheral Reset Set Register 0, Peripheral
* Reset Clear Register 0
/* Peripheral Reset Status Register 0, Peripheral Reset Set Register 0,
* Peripheral Reset Clear Register 0
*/
#define SCU_PR0_VADCRS (1 << 0) /* Bit 0: VADC Reset */
@ -830,8 +848,8 @@
#define SCU_PR0_USIC0RS (1 << 11) /* Bit 11: USIC0 Reset */
#define SCU_PR0_ERU1RS (1 << 16) /* Bit 16: ERU1 Reset */
/* Peripheral Reset Status Register 1, Peripheral Reset Set Register 1, Peripheral
* Reset Clear Register 1
/* Peripheral Reset Status Register 1, Peripheral Reset Set Register 1,
* Peripheral Reset Clear Register 1
*/
#define SCU_PR1_CCU43RS (1 << 0) /* Bit 0: CCU43 Reset */
@ -843,8 +861,8 @@
#define SCU_PR1_USIC2RS (1 << 8) /* Bit 8: USIC2 Reset */
#define SCU_PR1_PPORTSRS (1 << 9) /* Bit 9: PORTS Reset */
/* Peripheral Reset Status Register 1, Peripheral Reset Set Register 1, Peripheral
* Reset Clear Register 1
/* Peripheral Reset Status Register 1, Peripheral Reset Set Register 1,
* Peripheral Reset Clear Register 1
*/
#define SCU_PR2_WDTRS (1 << 1) /* Bit 1: WDT Reset */
@ -854,15 +872,17 @@
#define SCU_PR2_FCERS (1 << 6) /* Bit 6: FCE Reset */
#define SCU_PR2_USBRS (1 << 7) /* Bit 7: USB Reset */
/* Peripheral Reset Status Register 3, Peripheral Reset Set Register 3, Peripheral
* Reset Clear Register 3
/* Peripheral Reset Status Register 3, Peripheral Reset Set Register 3,
* Peripheral Reset Clear Register 3
*/
#define SCU_PR3_EBURS (1 << 2) /* Bit 2: EBU Reset */
/* Clock Control SCU Registers */
/* Clock Status Register, Clock Set Control Register, Clock clear Control Register */
/* Clock Status Register, Clock Set Control Register,
* Clock clear Control Register
*/
#define SCU_CLK_USBC (1 << 0) /* Bit 0: USB Clock */
#define SCU_CLK_MMCC (1 << 1) /* Bit 1: MMC Clock */
@ -930,6 +950,7 @@
# define SCU_EXTCLKCR_ECKSEL_FSYS (0 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fSYS clock */
# define SCU_EXTCLKCR_ECKSEL_FUSB (2 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fUSB clock divided by ECKDIV */
# define SCU_EXTCLKCR_ECKSEL_FPLL (3 << SCU_EXTCLKCR_ECKSEL_SHIFT) /* fPLL clock divided by ECKDIV */
#define SCU_EXTCLKCR_ECKDIV_SHIFT (16) /* Bits 16-24: External Clock Divider Value */
#define SCU_EXTCLKCR_ECKDIV_MASK (0x1ff << SCU_EXTCLKCR_ECKDIV_SHIFT)
# define SCU_EXTCLKCR_ECKDIV(n) ((uint32_t)((n)-1) << SCU_EXTCLKCR_ECKDIV_SHIFT)
@ -961,7 +982,9 @@
#define SCU_DSLEEPCR_CCUCR (1 << 20) /* Bit 20: CCU Clock Control in Deep Sleep Mod */
#define SCU_DSLEEPCR_WDTCR (1 << 21) /* Bit 21: WDT Clock Control in Deep Sleep Mode */
/* Peripheral 0 Clock Gating Status, Peripheral 0 Clock Gating Set, Peripheral 0 Clock Gating Clear */
/* Peripheral 0 Clock Gating Status, Peripheral 0 Clock Gating Set,
* Peripheral 0 Clock Gating Clear
*/
#ifdef XMC4_SCU_GATING
# define SCU_CGAT0_VADC (1 << 0) /* Bit 0: VADC Gating Status */
@ -977,7 +1000,9 @@
# define SCU_CGAT0_ERU1 (1 << 16) /* Bit 16: ERU1 Gating Status */
#endif
/* Peripheral 1 Clock Gating Status, Peripheral 1 Clock Gating Set, Peripheral 1 Clock Gating Clear */
/* Peripheral 1 Clock Gating Status, Peripheral 1 Clock Gating Set,
* Peripheral 1 Clock Gating Clear
*/
#ifdef XMC4_SCU_GATING
# define SCU_CGAT1_CCU43 (1 << 0) /* Bit 0: CCU43 Gating Status */
@ -990,7 +1015,9 @@
# define SCU_CGAT1_PPORTS (1 << 9) /* Bit 9: PORTS Gating Status */
#endif
/* Peripheral 2 Clock Gating Status, Peripheral 2 Clock Gating Set, Peripheral 2 Clock Gating Clear */
/* Peripheral 2 Clock Gating Status, Peripheral 2 Clock Gating Set,
* Peripheral 2 Clock Gating Clear
*/
#ifdef XMC4_SCU_GATING
# define SCU_CGAT2_WDT (1 << 1) /* Bit 1: WDT Gating Status */
@ -1002,7 +1029,9 @@
# define SCU_CGAT2_ECAT (1 << 10) /* Bit 10: ECAT Gating Status */
#endif
/* Peripheral 3 Clock Gating Status, Peripheral 3 Clock Gating Set, Peripheral 3 Clock Gating Clear */
/* Peripheral 3 Clock Gating Status, Peripheral 3 Clock Gating Set,
* Peripheral 3 Clock Gating Clear
*/
#ifdef XMC4_SCU_GATING
# define SCU_CGAT3_EBU (1 << 2) /* Bit 2: EBU Gating Status */

80
arch/arm/src/xmc4/hardware/xmc4_usic.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/xmc4/hardware/xmc4_usic.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
@ -37,36 +37,37 @@
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
* Infineon Technologies AG (Infineon) is supplying this software for use
* with Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS
* SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
* INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_USIC_H
#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_USIC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/xmc4_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
/* PMU Registers -- See ID register */
/* Prefetch Registers -- See PCON register */
/* Kernel Registers */
@ -115,9 +116,10 @@
#define XMC4_USIC_OUTDR_OFFSET 0x0120 /* Receiver Buffer Output Register L for Debugger */
#define XMC4_USIC_IN_OFFSET 0x0180 /* Transmit FIFO Buffer (32 x 4-bytes) */
/* Register Addresses ****************************************************************/
/* Register Addresses *******************************************************/
/* USIC0 Registers */
/* Kernel Registers */
#define XMC4_USIC0_ID (XMC4_USIC0_BASE+XMC4_USIC_ID_OFFSET)
@ -207,6 +209,7 @@
#define XMC4_USIC01_IN (XMC4_USIC0_CH1_BASE+XMC4_USIC_IN_OFFSET)
/* USIC1 Registers */
/* Kernel Registers */
#define XMC4_USIC1_ID (XMC4_USIC1_BASE+XMC4_USIC_ID_OFFSET)
@ -296,6 +299,7 @@
#define XMC4_USCI11_IN (XMC4_USIC1_CH1_BASE+XMC4_USIC_IN_OFFSET)
/* USCI2 Registers */
/* Kernel Registers */
#define XMC4_USCI2_ID (XMC4_USCI2_BASE+XMC4_USIC_ID_OFFSET)
@ -384,9 +388,10 @@
#define XMC4_USCI21_OUTDR (XMC4_USCI2_CH1_BASE+XMC4_USIC_OUTDR_OFFSET)
#define XMC4_USCI21_IN (XMC4_USCI2_CH1_BASE+XMC4_USIC_IN_OFFSET)
/* Register Bit-Field Definitions **************************************************/
/* Register Bit-Field Definitions *******************************************/
/* Kernel Registers */
/* Kernel State Configuration Register */
#define USIC_ID_MOD_REV_SHIFT (0) /* Bits 0-7: Module Revision Number */
@ -417,6 +422,7 @@
# define USIC_KSCFG_NOMCFG_RUN1 (1 << USIC_KSCFG_NOMCFG_SHIFT) /* Run mode 1 selected */
# define USIC_KSCFG_NOMCFG_STOP0 (2 << USIC_KSCFG_NOMCFG_SHIFT) /* Stop mode 0 selected */
# define USIC_KSCFG_NOMCFG_STOP1 (3 << USIC_KSCFG_NOMCFG_SHIFT) /* Stop mode 1 selected */
#define USIC_KSCFG_BPNOM (1 << 7) /* Bit 7: Bit Protection for NOMCFG */
#define USIC_KSCFG_SUMCFG_SHIFT (8) /* Bits 8-9: Suspend Mode Configuration */
#define USIC_KSCFG_SUMCFG_MASK (3 << USIC_KSCFG_SUMCFG_SHIFT)
@ -424,6 +430,7 @@
# define USIC_KSCFG_SUMCFG_RUN1 (1 << USIC_KSCFG_SUMCFG_SHIFT) /* Run mode 1 selected */
# define USIC_KSCFG_SUMCFG_STOP0 (2 << USIC_KSCFG_SUMCFG_SHIFT) /* Stop mode 0 selected */
# define USIC_KSCFG_SUMCFG_STOP1 (3 << USIC_KSCFG_SUMCFG_SHIFT) /* Stop mode 1 selected */
#define USIC_KSCFG_BPSUM (1 << 11) /* Bit 11: Bit Protection for SUMCFG */
/* Fractional Divider Register */
@ -436,6 +443,7 @@
# define USIC_FDR_DM_OFF (0 << USIC_FDR_DM_SHIFT) /* Divider switched off */
# define USIC_FDR_DM_NORMAL (1 << USIC_FDR_DM_SHIFT) /* Normal divider mode selected */
# define USIC_FDR_DM_FRACTIONAL (2 << USIC_FDR_DM_SHIFT) /* Fractional divider mode selected */
#define USIC_FDR_RESULT_SHIFT (16) /* Bits 16-25: Result Value */
#define USIC_FDR_RESULT_MASK (0x3ff << USIC_FDR_RESULT_SHIFT)
@ -446,6 +454,7 @@
# define USIC_BRG_CLKSEL_FRAC (0 << USIC_BRG_CLKSEL_SHIFT) /* Fractional divider frequency fFD */
# define USIC_BRG_CLKSEL_DX1T (2 << USIC_BRG_CLKSEL_SHIFT) /* Trigger signal DX1T defines fPIN */
# define USIC_BRG_CLKSEL_DX1S (3 << USIC_BRG_CLKSEL_SHIFT) /* Frequency fPIN is derived from DX1S */
#define USIC_BRG_TMEN (1 << 3) /* Bit 3: Timing Measurement Enable */
#define USIC_BRG_PPPEN (1 << 4) /* Bit 4: Enable 2:1 Divider for fPPP */
#define USIC_BRG_CTQSEL_SHIFT (6) /* Bits 6-7: Input Selection for CTQ */
@ -454,6 +463,7 @@
# define USIC_BRG_CTQSEL_FPPP (1 << USIC_BRG_CTQSEL_SHIFT) /* fCTQIN = fPPP */
# define USIC_BRG_CTQSEL_FSCLK (2 << USIC_BRG_CTQSEL_SHIFT) /* fCTQIN = fSCLK */
# define USIC_BRG_CTQSEL_FMCLK (3 << USIC_BRG_CTQSEL_SHIFT) /* fCTQIN = fMCLK */
#define USIC_BRG_PCTQ_SHIFT (8) /* Bits 8-9: Pre-Divider for Time Quanta Counter */
#define USIC_BRG_PCTQ_MASK (3 << USIC_BRG_PCTQ_SHIFT)
# define USIC_BRG_PCTQ(n) ((uint32_t)((n)-1) << USIC_BRG_PCTQ_SHIFT)
@ -482,6 +492,7 @@
# define USIC_INPR_TSINP_SR3 (3 << USIC_INPR_TSINP_SHIFT) /* Output SR3 activated */
# define USIC_INPR_TSINP_SR4 (4 << USIC_INPR_TSINP_SHIFT) /* Output SR4 activated */
# define USIC_INPR_TSINP_SR5 (5 << USIC_INPR_TSINP_SHIFT) /* Output SR5 activated */
#define USIC_INPR_TBINP_SHIFT (4) /* Bits 4-6: Transmit Buffer Interrupt Node Pointer */
#define USIC_INPR_TBINP_MASK (7 << USIC_INPR_TBINP_SHIFT)
# define USIC_INPR_TBINP_SR0 (0 << USIC_INPR_TBINP_SHIFT) /* Output SR0 activated */
@ -490,6 +501,7 @@
# define USIC_INPR_TBINP_SR3 (3 << USIC_INPR_TBINP_SHIFT) /* Output SR3 activated */
# define USIC_INPR_TBINP_SR4 (4 << USIC_INPR_TBINP_SHIFT) /* Output SR4 activated */
# define USIC_INPR_TBINP_SR5 (5 << USIC_INPR_TBINP_SHIFT) /* Output SR5 activated */
#define USIC_INPR_RINP_SHIFT (8) /* Bits 8-10: Receive Interrupt Node Pointer */
#define USIC_INPR_RINP_MASK (7 << USIC_INPR_RINP_SHIFT)
# define USIC_INPR_RINP_SR0 (0 << USIC_INPR_RINP_SHIFT) /* Output SR0 activated */
@ -498,6 +510,7 @@
# define USIC_INPR_RINP_SR3 (3 << USIC_INPR_RINP_SHIFT) /* Output SR3 activated */
# define USIC_INPR_RINP_SR4 (4 << USIC_INPR_RINP_SHIFT) /* Output SR4 activated */
# define USIC_INPR_RINP_SR5 (5 << USIC_INPR_RINP_SHIFT) /* Output SR5 activated */
#define USIC_INPR_AINP_SHIFT (12) /* Bits 12-14: Alternative Receive Interrupt Node Pointer */
#define USIC_INPR_AINP_MASK (7 << USIC_INPR_AINP_SHIFT)
# define USIC_INPR_AINP_SR0 (0 << USIC_INPR_AINP_SHIFT) /* Output SR0 activated */
@ -506,6 +519,7 @@
# define USIC_INPR_AINP_SR3 (3 << USIC_INPR_AINP_SHIFT) /* Output SR3 activated */
# define USIC_INPR_AINP_SR4 (4 << USIC_INPR_AINP_SHIFT) /* Output SR4 activated */
# define USIC_INPR_AINP_SR5 (5 << USIC_INPR_AINP_SHIFT) /* Output SR5 activated */
#define USIC_INPR_PINP_SHIFT (16) /* Bits 16-18: Protocol Interrupt Node Pointer */
#define USIC_INPR_PINP_MASK (7 << USIC_INPR_PINP_SHIFT)
# define USIC_INPR_PINP_SR0 (0 << USIC_INPR_PINP_SHIFT) /* Output SR0 activated */
@ -515,13 +529,15 @@
# define USIC_INPR_PINP_SR4 (4 << USIC_INPR_PINP_SHIFT) /* Output SR4 activated */
# define USIC_INPR_PINP_SR5 (5 << USIC_INPR_PINP_SHIFT) /* Output SR5 activated */
/* Input Control Register 0, Input Control Register 1, Input Control Register 2,
* Input Control Register 3, Input Control Register 4, Input Control Register 5
/* Input Control Register 0, Input Control Register 1,
* Input Control Register 2, Input Control Register 3,
* Input Control Register 4, Input Control Register 5
*/
#define USIC_DXCR_DSEL_SHIFT (0) /* Bits 0-2: Data Selection for Input Signal */
#define USIC_DXCR_DSEL_MASK (7 << USIC_DXCR_DSEL_SHIFT)
# define USIC_DXCR_DSEL_DX(m) ((uint32_t)(m) << USIC_DXCR_DSEL_SHIFT) /* Data input DXnm selected */
# define USIC_DXCR_DSEL_DXA (0 << USIC_DXCR_DSEL_SHIFT) /* Data input DXnA selected */
# define USIC_DXCR_DSEL_DXB (1 << USIC_DXCR_DSEL_SHIFT) /* Data input DXnB selected */
# define USIC_DXCR_DSEL_DXC (2 << USIC_DXCR_DSEL_SHIFT) /* Data input DXnC selected */
@ -530,6 +546,7 @@
# define USIC_DXCR_DSEL_DXF (5 << USIC_DXCR_DSEL_SHIFT) /* Data input DXnF selected */
# define USIC_DXCR_DSEL_DXG (6 << USIC_DXCR_DSEL_SHIFT) /* Data input DXnG selected */
# define USIC_DXCR_DSEL_ONE (7 << USIC_DXCR_DSEL_SHIFT) /* Data input is always 1 */
#define USIC_DX1CR_DCEN (1 << 3) /* Bit 3: Delay Compensation Enable (DX1CR only) */
#define USIC_DXCR_INSW (1 << 4) /* Bit 4: Input Switch */
#define USIC_DXCR_DFEN (1 << 5) /* Bit 5: Digital Filter Enable */
@ -542,6 +559,7 @@
# define USIC_DXCR_CM_RISING (1 << USIC_DXCR_CM_SHIFT) /* Rising edge activates DXnT */
# define USIC_DXCR_CM_FALLING (2 << USIC_DXCR_CM_SHIFT) /* Falling edge activates DXnT */
# define USIC_DXCR_CM_BOTH (3 << USIC_DXCR_CM_SHIFT) /* Both edges activate DXnT */
#define USIC_DXCR_DXS (1 << 15) /* Bit 15: Synchronized Data Value */
/* Shift Control Register */
@ -555,17 +573,20 @@
# define USIC_SCTR_DSM_1BIT (0 << USIC_SCTR_DSM_SHIFT) /* Data is shifted one bit at a time */
# define USIC_SCTR_DSM_2BITS (2 << USIC_SCTR_DSM_SHIFT) /* Data is shifted two bits at a time */
# define USIC_SCTR_DSM_4BITS (3 << USIC_SCTR_DSM_SHIFT) /* Data is shifted four bits at a time */
#define USIC_SCTR_HPCDIR (1 << 4) /* Bit 4: Port Control Direction */
#define USIC_SCTR_DOCFG_SHIFT (6) /* Bits 6-7: Data Output Configuration */
#define USIC_SCTR_DOCFG_MASK (3 << USIC_SCTR_DOCFG_SHIFT)
#define USIC_SCTR_DOCFG_NORMAL (0 << USIC_SCTR_DOCFG_SHIFT) /* DOUTx = shift data value */
#define USIC_SCTR_DOCFG_INVERT (1 << USIC_SCTR_DOCFG_SHIFT) /* DOUTx = inverted shift data value */
# define USIC_SCTR_DOCFG_NORMAL (0 << USIC_SCTR_DOCFG_SHIFT) /* DOUTx = shift data value */
# define USIC_SCTR_DOCFG_INVERT (1 << USIC_SCTR_DOCFG_SHIFT) /* DOUTx = inverted shift data value */
#define USIC_SCTR_TRM_SHIFT (8) /* Bits 8-9: Transmission Mode */
#define USIC_SCTR_TRM_MASK (3 << USIC_SCTR_TRM_SHIFT)
# define USIC_SCTR_TRM_INACTIVE (0 << USIC_SCTR_TRM_SHIFT) /* Inactive */
# define USIC_SCTR_TRM_1LEVEL (1 << USIC_SCTR_TRM_SHIFT) /* Active at 1-level */
# define USIC_SCTR_TRM_0LEVEL (2 << USIC_SCTR_TRM_SHIFT) /* Active at 0-level */
# define USIC_SCTR_TRM_ACTIVE (3 << USIC_SCTR_TRM_SHIFT) /* Active without regard to signal level */
#define USIC_SCTR_FLE_SHIFT (16) /* Bits 16-21: Frame Length */
#define USIC_SCTR_FLE_MASK (0x3f << USIC_SCTR_FLE_SHIFT)
# define USIC_SCTR_FLE(n) ((uint32_t)((n)-1) << USIC_SCTR_FLE_SHIFT)
@ -590,6 +611,7 @@
# define USIC_TCSR_TDEN_TDIV (1 << USIC_TCSR_TDEN_SHIFT) /* Transmission of data word if TDV = 1 */
# define USIC_TCSR_TDEN_TDIVDX2S0 (2 << USIC_TCSR_TDEN_SHIFT) /* Transmission of data word if TDV = 1 while DX2S = 0 */
# define USIC_TCSR_TDEN_TDIVDX2S1 (3 << USIC_TCSR_TDEN_SHIFT) /* Transmission of data word if TDV = 1 while DX2S = 1 */
#define USIC_TCSR_TDVTR (1 << 12) /* Bit 12: TBUF Data Valid Trigger */
#define USIC_TCSR_WA (1 << 13) /* Bit 13: Word Addre */
#define USIC_TCSR_TSOF (1 << 24) /* Bit 24: Transmitted Start Of Frame */
@ -646,8 +668,9 @@
# define USIC_PCR_ASCMODE_SP(n) ((uint32_t)(n) << USIC_PCR_ASCMODE_SP_SHIFT)
#define USIC_PCR_ASCMODE_PL_SHIFT (13) /* Bits 13-15: Pulse Length */
#define USIC_PCR_ASCMODE_PL_MASK (7 << USIC_PCR_ASCMODE_PL_SHIFT)
#define USIC_PCR_ASCMODE_PLBIT (0 << USIC_PCR_ASCMODE_PL_SHIFT) /* Pulse length = bit length */
#define USIC_PCR_ASCMODE_PL(n) ((uint32_t)((n)-1) << USIC_PCR_ASCMODE_PL_SHIFT) /* Pulse length = n quanta */
# define USIC_PCR_ASCMODE_PLBIT (0 << USIC_PCR_ASCMODE_PL_SHIFT) /* Pulse length = bit length */
# define USIC_PCR_ASCMODE_PL(n) ((uint32_t)((n)-1) << USIC_PCR_ASCMODE_PL_SHIFT) /* Pulse length = n quanta */
#define USIC_PCR_ASCMODE_RSTEN (1 << 16) /* Bit 16: Receiver Status Enable */
#define USIC_PCR_ASCMODE_TSTEN (1 << 17) /* Bit 17: Transmitter Status Enable */
#define USIC_PCR_ASCMODE_MCLK (1 << 31) /* Bit 31: Master Clock Enable */
@ -662,6 +685,7 @@
# define USIC_PCR_SSCMODE_CTQSEL1_FPPP (1 << USIC_PCR_SSCMODE_CTQSEL1_SHIFT) /* fCTQIN = fPPP */
# define USIC_PCR_SSCMODE_CTQSEL1_FSCLK (2 << USIC_PCR_SSCMODE_CTQSEL1_SHIFT) /* fCTQIN = fSCLK */
# define USIC_PCR_SSCMODE_CTQSEL1_FMCLK (3 << USIC_PCR_SSCMODE_CTQSEL1_SHIFT) /* fCTQIN = fMCLK */
#define USIC_PCR_SSCMODE_PCTQ1_SHIFT (6) /* Bits 6-7: Divider Factor PCTQ1 for Tiw and Tnf */
#define USIC_PCR_SSCMODE_PCTQ1_MASK (3 << USIC_PCR_SSCMODE_PCTQ1_SHIFT)
# define USIC_PCR_SSCMODE_PCTQ1(n) ((uint32_t)((n)-1) << USIC_PCR_SSCMODE_PCTQ1_SHIFT)
@ -718,17 +742,20 @@
# define USIC_CCR_MODE_ASC (2 << USIC_CCR_MODE_SHIFT) /* ASC (SCI, UART) protocol is selected */
# define USIC_CCR_MODE_I2S (3 << USIC_CCR_MODE_SHIFT) /* IIS protocol is selected */
# define USIC_CCR_MODE_I2C (4 << USIC_CCR_MODE_SHIFT) /* IIC protocol is selected */
#define USIC_CCR_HPCEN_SHIFT (6) /* Bits 6-7: Hardware Port Control Enable */
#define USIC_CCR_HPCEN_MASK (3 << USIC_CCR_HPCEN_SHIFT)
# define USIC_CCR_HPCEN_DISABLE (0 << USIC_CCR_HPCEN_SHIFT) /* Port control disabled */
# define USIC_CCR_HPCEN_DX0_1 (1 << USIC_CCR_HPCEN_SHIFT) /* Port control enabled for DX0 and DOUT0 */
# define USIC_CCR_HPCEN_DX3 (2 << USIC_CCR_HPCEN_SHIFT) /* Port control enabled for DX3, DX0 and DOUT[1:0] */
# define USIC_CCR_HPCEN_DX0_2 (3 << USIC_CCR_HPCEN_SHIFT) /* Port control enabled for DX0, DX[5:3] and DOUT[3:0] */
#define USIC_CCR_PM_SHIFT (8) /* Bits 8-9: Parity Mode */
#define USIC_CCR_PM_MASK (3 << USIC_CCR_PM_SHIFT)
# define USIC_CCR_PM_NONE (0 << USIC_CCR_PM_SHIFT) /* Parity generation is disabled */
# define USIC_CCR_PM_EVEN (2 << USIC_CCR_PM_SHIFT) /* Even parity is selected */
# define USIC_CCR_PM_ODD (3 << USIC_CCR_PM_SHIFT) /* Odd parity is selected */
#define USIC_CCR_RSIEN (1 << 10) /* Bit 10: Receiver Start Interrupt Enable */
#define USIC_CCR_DLIEN (1 << 11) /* Bit 11: Data Lost Interrupt Enable */
#define USIC_CCR_TSIEN (1 << 12) /* Bit 12: Transmit Shift Interrupt Enable */
@ -904,6 +931,7 @@
# define USIC_FMR_MTDV_NOACTION (0 << USIC_FMR_MTDV_SHIFT) /* No action */
# define USIC_FMR_MTDV_TDV (1 << USIC_FMR_MTDV_SHIFT) /* Bit TDV is set, TE is unchanged */
# define USIC_FMR_MTDV_TDVTE (2 << USIC_FMR_MTDV_SHIFT) /* Bits TDV and TE are cleared */
#define USIC_FMR_ATVC (1 << 4) /* Bit 4: Activate Bit TVC */
#define USIC_FMR_CRDV0 (1 << 14) /* Bit 14: Clear Bits RDV for RBUF0 */
#define USIC_FMR_CRDV1 (1 << 15) /* Bit 15: Clear Bit RDV for RBUF1 */
@ -930,7 +958,7 @@
#define USIC_BYPCR_BWLE_SHIFT (0) /* Bits 0-3: Bypass Word Length */
#define USIC_BYPCR_BWLE_MASK (15 << USIC_BYPCR_BWLE_SHIFT)
#define USIC_BYPCR_BWLE(n) ((uint32_t)((n)-1) << USIC_BYPCR_BWLE_SHIFT)
# define USIC_BYPCR_BWLE(n) ((uint32_t)((n)-1) << USIC_BYPCR_BWLE_SHIFT)
#define USIC_BYPCR_BDSSM (1 << 8) /* Bit 8: Bypass Data Single Shot Mode */
#define USIC_BYPCR_BDEN_SHIFT (10) /* Bits 10-11: Bypass Data Enable */
#define USIC_BYPCR_BDEN_MASK (3 << USIC_BYPCR_BDEN_SHIFT)
@ -938,6 +966,7 @@
# define USIC_BYPCR_BDEN_ENABLED (1 << USIC_BYPCR_BDEN_SHIFT) /* Transfer of bypass data to TBUF if BDV = 1 */
# define USIC_BYPCR_BDEN_GATED0 (2 << USIC_BYPCR_BDEN_SHIFT) /* Bypass data transferred if BDV = 1 and DX2S = 0 */
# define USIC_BYPCR_BDEN_GATED1 (3 << USIC_BYPCR_BDEN_SHIFT) /* Bypass data transferred if BDV = 1 and DX2S = 1 */
#define USIC_BYPCR_BDVTR (1 << 12) /* Bit 12: Bypass Data Valid Trigger */
#define USIC_BYPCR_BPRIO (1 << 13) /* Bit 13: Bypass Priority */
#define USIC_BYPCR_BDV (1 << 15) /* Bit 15: Bypass Data Valid */
@ -966,6 +995,7 @@
# define USIC_TBCTR_STBINP_SR3 (3 << USIC_TBCTR_STBINP_SHIFT) /* Output SR3 becomes activated */
# define USIC_TBCTR_STBINP_SR4 (4 << USIC_TBCTR_STBINP_SHIFT) /* Output SR4 becomes activated */
# define USIC_TBCTR_STBINP_SR5 (5 << USIC_TBCTR_STBINP_SHIFT) /* Output SR5 becomes activated */
#define USIC_TBCTR_ATBINP_SHIFT (19) /* Bits 19-21: Alternative Transmit Buffer Interrupt Node Pointer */
#define USIC_TBCTR_ATBINP_MASK (7 << USIC_TBCTR_ATBINP_SHIFT)
# define USIC_TBCTR_ATBINP_SR0 (0 << USIC_TBCTR_ATBINP_SHIFT) /* Output SR0 becomes activated */
@ -974,6 +1004,7 @@
# define USIC_TBCTR_ATBINP_SR3 (3 << USIC_TBCTR_ATBINP_SHIFT) /* Output SR3 becomes activated */
# define USIC_TBCTR_ATBINP_SR4 (4 << USIC_TBCTR_ATBINP_SHIFT) /* Output SR4 becomes activated */
# define USIC_TBCTR_ATBINP_SR5 (5 << USIC_TBCTR_ATBINP_SHIFT) /* Output SR5 becomes activated */
#define USIC_TBCTR_SIZE_SHIFT (24) /* Bits 24-26: Buffer Size */
#define USIC_TBCTR_SIZE_MASK (7 << USIC_TBCTR_SIZE_SHIFT)
# define USIC_TBCTR_SIZE_DISABLE (0 << USIC_TBCTR_SIZE_SHIFT) /* FIFO mechanism is disabled */
@ -983,6 +1014,7 @@
# define USIC_TBCTR_SIZE_16 (4 << USIC_TBCTR_SIZE_SHIFT) /* FIFO buffer contains 16 entries */
# define USIC_TBCTR_SIZE_32 (5 << USIC_TBCTR_SIZE_SHIFT) /* FIFO buffer contains 32 entries */
# define USIC_TBCTR_SIZE_64 (6 << USIC_TBCTR_SIZE_SHIFT) /* FIFO buffer contains 64 entries */
#define USIC_TBCTR_LOF (1 << 28) /* Bit 28: Buffer Event on Limit Overflow */
#define USIC_TBCTR_STBIEN (1 << 30) /* Bit 30: Standard Transmit Buffer Interrupt Enable */
#define USIC_TBCTR_TBERIEN (1 << 31) /* Bit 31: Transmit Buffer Error Interrupt Enable */
@ -1005,6 +1037,7 @@
# define USIC_RBCTR_SRBINP_SR3 (3 << USIC_RBCTR_SRBINP_SHIFT) /* Output SR3 becomes activated */
# define USIC_RBCTR_SRBINP_SR4 (4 << USIC_RBCTR_SRBINP_SHIFT) /* Output SR4 becomes activated */
# define USIC_RBCTR_SRBINP_SR5 (5 << USIC_RBCTR_SRBINP_SHIFT) /* Output SR5 becomes activated */
#define USIC_RBCTR_ARBINP_SHIFT (19) /* Bits 19-21: Alternative Receive Buffer Interrupt Node Pointer */
#define USIC_RBCTR_ARBINP_MASK (7 << USIC_RBCTR_ARBINP_SHIFT)
# define USIC_RBCTR_ARBINP_SR0 (0 << USIC_RBCTR_ARBINP_SHIFT) /* Output SR0 becomes activated */
@ -1013,6 +1046,7 @@
# define USIC_RBCTR_ARBINP_SR3 (3 << USIC_RBCTR_ARBINP_SHIFT) /* Output SR3 becomes activated */
# define USIC_RBCTR_ARBINP_SR4 (4 << USIC_RBCTR_ARBINP_SHIFT) /* Output SR4 becomes activated */
# define USIC_RBCTR_ARBINP_SR5 (5 << USIC_RBCTR_ARBINP_SHIFT) /* Output SR5 becomes activated */
#define USIC_RBCTR_RCIM_SHIFT (22) /* Bits 22-23: Receiver Control Information Mode */
#define USIC_RBCTR_RCIM_MASK (3 << USIC_RBCTR_RCIM_SHIFT)
# define USIC_RBCTR_RCIM_MODE0 (0 << USIC_RBCTR_RCIM_SHIFT) /* RCI[4] = PERR, RCI[3:0] = WLEN */
@ -1020,6 +1054,7 @@
# define USIC_RBCTR_RCIM_MODE2 (2 << USIC_RBCTR_RCIM_SHIFT) /* RCI[4] = 0, RCI[3:0] = WLEN */
# define USIC_RBCTR_RCIM_MODE3 (3 << USIC_RBCTR_RCIM_SHIFT) /* RCI[4] = PERR, RCI[3] = PAR,
* RCI[2:1] = 0, RCI[0] = SOF */
#define USIC_RBCTR_SIZE_SHIFT (24) /* Bits 24-26: Buffer Size */
#define USIC_RBCTR_SIZE_MASK (7 << USIC_RBCTR_SIZE_SHIFT)
# define USIC_RBCTR_SIZE_DISABLE (0 << USIC_RBCTR_SIZE_SHIFT) /* FIFO mechanism is disabled */
@ -1029,6 +1064,7 @@
# define USIC_RBCTR_SIZE_16 (4 << USIC_RBCTR_SIZE_SHIFT) /* FIFO buffer contains 16 entries */
# define USIC_RBCTR_SIZE_32 (5 << USIC_RBCTR_SIZE_SHIFT) /* FIFO buffer contains 32 entries */
# define USIC_RBCTR_SIZE_64 (6 << USIC_RBCTR_SIZE_SHIFT) /* FIFO buffer contains 64 entries */
#define USIC_RBCTR_RNM (1 << 27) /* Bit 27: Receiver Notification Mode */
#define USIC_RBCTR_LOF (1 << 28) /* Bit 28: Buffer Event on Limit Overflow */
#define USIC_RBCTR_ARBIEN (1 << 29) /* Bit 29: Alternative Receive Buffer Interrupt Enable */

4
arch/arm/src/xmc4/xmc4_dma.h
View File

@ -41,7 +41,9 @@
typedef FAR void *DMA_HANDLE;
typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is
* selected
*/
#ifdef CONFIG_DEBUG_DMA
struct xmc4_dmaglobalregs_s

9
arch/arm/src/xmc4/xmc4_gpio.h
View File

@ -38,7 +38,6 @@
* TTTT TMPD DDCC VO... .... .... PPPP BBBB
*/
/* This identifies the GPIO pint type:
*
* TTTT T... .... .... .... .... .... ....
@ -48,6 +47,7 @@
#define GPIO_PINTYPE_MASK (31 << GPIO_PINTYPE_SHIFT)
/* See chip/xmc4_ports.h for the IOCR definitions */
/* Direct input */
# define GPIO_INPUT (IOCR_INPUT_NOPULL << GPIO_PINTYPE_SHIFT)
@ -97,6 +97,7 @@
#define GPIO_PADTYPE_MASK (7 << GPIO_PADTYPE_SHIFT)
/* See chip/xmc4_ports.h for the PDR definitions */
/* Pad class A1: */
# define GPIO_PADA1_MEDIUM (PDR_PADA1_MEDIUM << GPIO_PADTYPE_SHIFT)
@ -131,7 +132,8 @@
# define GPIO_PINCTRL_HW0 (HWSEL_HW0 << GPIO_PINCTRL_SHIFT)
# define GPIO_PINCTRL_HW1 (HWSEL_HW1 << GPIO_PINCTRL_SHIFT)
/* If the pin is an GPIO output, then this identifies the initial output value:
/* If the pin is an GPIO output, then this identifies the initial output
* value:
*
* .... .... .... V.... .... .... PPPP BBBB
*/
@ -183,7 +185,6 @@
#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
/****************************************************************************
* Public Types
****************************************************************************/
@ -193,7 +194,7 @@
typedef uint32_t gpioconfig_t;
/****************************************************************************
* Public Functions
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************

8
arch/arm/src/xmc4/xmc4_lowputc.c
View File

@ -141,7 +141,9 @@ void arm_lowputc(char ch)
uintptr_t base;
uint32_t regval;
/* Get the base address of the USIC registers associated with this channel */
/* Get the base address of the USIC registers associated with this
* channel
*/
base = xmc4_channel_baseaddress(CONSOLE_CHAN);
DEBUGASSERT(base != 0);
@ -241,7 +243,9 @@ int xmc4_uart_configure(enum usic_channel_e channel,
uint32_t regval;
int ret;
/* Get the base address of the USIC registers associated with this channel */
/* Get the base address of the USIC registers associated with this
* channel
*/
base = xmc4_channel_baseaddress(channel);
if (base == 0)

30
arch/arm/src/xmc4/xmc4_pwm.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/xmc4/xmc4_pwm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,32 +16,32 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_XMC4_PWM_H
#define __ARCH_ARM_SRC_XMC4_XMC4_PWM_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Configuration ********************************************************************/
/* Configuration ************************************************************/
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
@ -54,11 +54,11 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: xmc4_pwm_initialize
*
* Description:
@ -71,7 +71,7 @@ extern "C"
* On success, a pointer to the kinetis lower half PWM driver is returned.
* NULL is returned on any failure.
*
************************************************************************************/
****************************************************************************/
FAR struct pwm_lowerhalf_s *xmc4_pwm_initialize(int timer);

23
arch/arm/src/xmc4/xmc4_start.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/xmc4/xmc4_start.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,30 +16,31 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_XMC4_XMC4_START_H
#define __ARCH_ARM_SRC_XMC4_XMC4_START_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
/****************************************************************************
* Public Function Prototypes
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: xmc4_board_initialize
*
* Description:
* All XMC4xxx architectures must provide the following entry point. This entry
* point is called early in the initialization -- after all memory has been
* configured and mapped but before any devices have been initialized.
* All XMC4xxx architectures must provide the following entry point. This
* entry point is called early in the initialization -- after all memory
* has been configured and mapped but before any devices have been
* initialized.
*
************************************************************************************/
****************************************************************************/
void xmc4_board_initialize(void);