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Merged in david_s5/nuttx/master_f7_eth (pull request #970)

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stm32f7:ethernet add timeout on MAC reset

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
David Sidrane 2019-08-08 16:17:57 +00:00 committed by Gregory Nutt
parent 8f3e024ef7
commit 786d3453a2
1 changed files with 21 additions and 12 deletions
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33
arch/arm/src/stm32f7/stm32_ethernet.c
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@ -316,6 +316,10 @@
#define PHY_WRITE_TIMEOUT (0x0004ffff)
#define PHY_RETRY_TIMEOUT (0x0004ffff)
/* MAC reset ready delays in loop counts */
#define MAC_READY_USTIMEOUT (100)
/* Register values **********************************************************/
/* Clear the MACCR bits that will be setup during MAC initialization (or that
@ -3531,7 +3535,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
/* Set up the MII interface */
#if defined(CONFIG_STM32F7_MII)
# if defined(CONFIG_STM32F7_MII)
/* Select the MII interface */
@ -3546,7 +3550,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
* PLLI2S clock (through a configurable prescaler) on PC9 pin."
*/
# if defined(CONFIG_STM32F7_MII_MCO1)
# if defined(CONFIG_STM32F7_MII_MCO1)
/* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking
* info.
*/
@ -3554,7 +3558,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
stm32_configgpio(GPIO_MCO1);
stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER);
# elif defined(CONFIG_STM32F7_MII_MCO2)
# elif defined(CONFIG_STM32F7_MII_MCO2)
/* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking
* info.
*/
@ -3562,12 +3566,12 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
stm32_configgpio(GPIO_MCO2);
stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER);
# elif defined(CONFIG_STM32F7_MII_MCO)
# elif defined(CONFIG_STM32F7_MII_MCO)
/* Setup MCO pin for alternative usage */
stm32_configgpio(GPIO_MCO);
stm32_mcoconfig(BOARD_CFGR_MCO_SOURCE);
# endif
# endif
/* MII interface pins (17):
*
@ -3593,7 +3597,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
/* Set up the RMII interface. */
#elif defined(CONFIG_STM32F7_RMII)
# elif defined(CONFIG_STM32F7_RMII)
/* Select the RMII interface */
@ -3608,7 +3612,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
* PLLI2S clock (through a configurable prescaler) on PC9 pin."
*/
# if defined(CONFIG_STM32F7_RMII_MCO1)
# if defined(CONFIG_STM32F7_RMII_MCO1)
/* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking
* info.
*/
@ -3616,7 +3620,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
stm32_configgpio(GPIO_MCO1);
stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER);
# elif defined(CONFIG_STM32F7_RMII_MCO2)
# elif defined(CONFIG_STM32F7_RMII_MCO2)
/* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking
* info.
*/
@ -3624,12 +3628,12 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
stm32_configgpio(GPIO_MCO2);
stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER);
# elif defined(CONFIG_STM32F7_RMII_MCO)
# elif defined(CONFIG_STM32F7_RMII_MCO)
/* Setup MCO pin for alternative usage */
stm32_configgpio(GPIO_MCO);
stm32_mcoconfig(BOARD_CFGR_MCO_SOURCE);
# endif
# endif
/* RMII interface pins (7):
*
@ -3645,7 +3649,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
stm32_configgpio(GPIO_ETH_RMII_TXD1);
stm32_configgpio(GPIO_ETH_RMII_TX_EN);
#endif
# endif
#endif
#ifdef CONFIG_STM32F7_ETH_PTP
@ -3674,6 +3678,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
static void stm32_ethreset(struct stm32_ethmac_s *priv)
{
uint32_t regval;
volatile uint32_t timeout;
/* Reset the Ethernet on the AHB bus (F1 Connectivity Line) or AHB1 bus (F2
* and F4)
@ -3699,7 +3704,11 @@ static void stm32_ethreset(struct stm32_ethmac_s *priv)
* after the reset operation has completed in all of the core clock domains.
*/
while ((stm32_getreg(STM32_ETH_DMABMR) & ETH_DMABMR_SR) != 0);
timeout = MAC_READY_USTIMEOUT;
while (timeout-- && (stm32_getreg(STM32_ETH_DMABMR) & ETH_DMABMR_SR) != 0)
{
up_udelay(1);
}
}
/****************************************************************************