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SAM4E: Fix some errors in AFEC header file.

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OrbitalFox 2016-06-10 09:56:35 -06:00 committed by Gregory Nutt
parent c98f00a93b
commit 78a2465af4
2 changed files with 4 additions and 4 deletions
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2
Documentation/NuttXCCodingStandard.html
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@ -248,7 +248,7 @@
<p> <p>
<b>Deoxygen Information</b>. <b>Deoxygen Information</b>.
NuttX does not use Deoxygen for documentation and no file should contain Doxygen tags. NuttX does not use Deoxygen for documentation and no file should contain Doxygen tags or Doxygen style comments.
</p> </p>
<p> <p>

6
arch/arm/src/sam34/chip/sam_afec.h
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@ -211,8 +211,8 @@
# define AFEC_EMR_CMPMODE_HIGH (1 << AFEC_EMR_CMPMODE_SHIFT) /* Event when higher than high window threshold */ # define AFEC_EMR_CMPMODE_HIGH (1 << AFEC_EMR_CMPMODE_SHIFT) /* Event when higher than high window threshold */
# define AFEC_EMR_CMPMODE_IN (2 << AFEC_EMR_CMPMODE_SHIFT) /* Event when in comparison window */ # define AFEC_EMR_CMPMODE_IN (2 << AFEC_EMR_CMPMODE_SHIFT) /* Event when in comparison window */
# define AFEC_EMR_CMPMODE_OUT (3 << AFEC_EMR_CMPMODE_SHIFT) /* Event when out of comparison window */ # define AFEC_EMR_CMPMODE_OUT (3 << AFEC_EMR_CMPMODE_SHIFT) /* Event when out of comparison window */
#define AFEC_EMR_CMPSEL_SHIFT (4) /* Bit 4-7: Comparison Selected Channel */ #define AFEC_EMR_CMPSEL_SHIFT (3) /* Bit 3-7: Comparison Selected Channel */
#define AFEC_EMR_CMPSEL_MASK (15 << AFEC_EMR_CMPSEL_SHIFT) #define AFEC_EMR_CMPSEL_MASK (31 << AFEC_EMR_CMPSEL_SHIFT)
# define AFEC_EMR_CMPSEL(n) ((uint32_t)(n) << AFEC_EMR_CMPSEL_SHIFT) # define AFEC_EMR_CMPSEL(n) ((uint32_t)(n) << AFEC_EMR_CMPSEL_SHIFT)
#define AFEC_EMR_CMPALL (1 << 9) /* Bit 9: Compare All Channels */ #define AFEC_EMR_CMPALL (1 << 9) /* Bit 9: Compare All Channels */
#define AFEC_EMR_CMPFILTER_SHIFT (12) /* Bits 12-13: Compare Event Filtering */ #define AFEC_EMR_CMPFILTER_SHIFT (12) /* Bits 12-13: Compare Event Filtering */
@ -375,7 +375,7 @@
# define AFEC_CWR_LOWTHRES(n) ((uint32_t)(n) << AFEC_CWR_LOWTHRES_SHIFT) # define AFEC_CWR_LOWTHRES(n) ((uint32_t)(n) << AFEC_CWR_LOWTHRES_SHIFT)
#define AFEC_CWR_HIGHTHRES_SHIFT (16) /* Bits 16-27: High Threshold */ #define AFEC_CWR_HIGHTHRES_SHIFT (16) /* Bits 16-27: High Threshold */
#define AFEC_CWR_HIGHTHRES_MASK (0xfff << AFEC_CWR_LOWTHRES_SHIFT) #define AFEC_CWR_HIGHTHRES_MASK (0xfff << AFEC_CWR_LOWTHRES_SHIFT)
# define AFEC_CWR_HIGHTHRES(n)K ((uint32_t)(n) << AFEC_CWR_LOWTHRES_SHIFT) # define AFEC_CWR_HIGHTHRES(n) ((uint32_t)(n) << AFEC_CWR_LOWTHRES_SHIFT)
/* Channel Gain Register */ /* Channel Gain Register */