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stm32l5: Remove unused CACHE_LINESIZE defines

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Cortex-M33 does neither have an I- nor a D-Cache.  Both defines are not
used across the stm32l5 architecture code.  Thus, just remove them.

_Originally posted by @acassis in https://github.com/apache/incubator-nuttx/pull/2974#discussion_r588224862_

Signed-off-by: Michael Jung <mijung@gmx.net>
This commit is contained in:
Michael Jung 2021-03-05 12:45:57 +01:00 committed by Xiang Xiao
parent 33892dcc54
commit 78a69a89d8
1 changed files with 0 additions and 5 deletions
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5
arch/arm/src/stm32l5/chip.h
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@ -48,9 +48,4 @@
#define ARMV8M_PERIPHERAL_INTERRUPTS STM32L5_IRQ_NEXTINTS
/* Cache line sizes (in bytes) for the STM32L5 */
#define ARMV8M_DCACHE_LINESIZE 0 /* no cache */
#define ARMV8M_ICACHE_LINESIZE 0 /* no cache */
#endif /* __ARCH_ARM_SRC_STM32L5_CHIP_H */