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SAMA5 LCDC: Back out the delay kludge. Increase the LCDC input clock from MCK to 2*MCK was sufficient for all timing instbility problems

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This commit is contained in:
Gregory Nutt 2014-07-12 11:24:14 -06:00
parent 6298ead42c
commit 78adc980e6
1 changed files with 0 additions and 13 deletions
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13
configs/sama5d4-ek/include/board.h
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@ -203,19 +203,6 @@
#define BOARD_LCDC_PIXELCLOCK \
(BOARD_LCDC_HSPERIOD * BOARD_LCDC_VSPERIOD * BOARD_LCDC_FRAMERATE)
/* This specifies a delay after enabling the LCDC. This was found
* experimentally and is very much a kludge. I presume that a delay of a
* couple of frame times allows some unstable clocking to synchronize before
* we start thrashing the framebuffer? But I am not sure why this is
* necessary and, in fact, is certainly not necessary in other LCDC
* configurations. Perhaps the delay would not be necessary if timings were
* more precise?
*
* Delays are in units of microseconds.
*/
#define BOARD_LCDC_ENABLE_DELAY (50*1000)
/* Backlight prescaler value and PWM output polarity */
#define BOARD_LCDC_PWMPS LCDC_LCDCFG6_PWMPS_DIV1