kinetis:Replace DMA
Kinetis:DMAMUX use hex in mask
This commit is contained in:
David Sidrane
Xiang Xiao
parent
3439c40044
commit
78bf264af0
@ -751,7 +751,7 @@ config KINETIS_FTFL
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---help---
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Support FLASH
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config KINETIS_DMA
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config KINETIS_EDMA
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bool "DMA"
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default n
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depends on KINETIS_HAVE_DMA
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@ -1114,6 +1114,96 @@ config KINETIS_SD4BIT_FREQ
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endif
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endmenu # Kinetis SDHC Configuration
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menu "eDMA Configuration"
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depends on KINETIS_EDMA
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config KINETIS_EDMA_NTCD
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int "Number of transfer descriptors"
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default 0
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---help---
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Number of pre-allocated transfer descriptors. Needed for scatter-
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gather DMA. Make to be set to zero to disable in-memory TCDs in
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which case only the TCD channel registers will be used and scatter-
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will not be supported.
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config KINETIS_EDMA_ELINK
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bool "Channeling Linking"
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default n
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---help---
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This option enables optional minor or major loop channel linking:
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Minor loop channel linking: As the channel completes the minor
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loop, this flag enables linking to another channel. The link target
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channel initiates a channel service request via an internal
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mechanism that sets the TCDn_CSR[START] bit of the specified
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channel.
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If minor loop channel linking is disabled, this link mechanism is
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suppressed in favor of the major loop channel linking.
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Major loop channel linking: As the channel completes the minor
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loop, this option enables the linking to another channel. The link
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target channel initiates a channel service request via an internal
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mechanism that sets the TCDn_CSR[START] bit of the linked channel.
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config KINETIS_EDMA_ERCA
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bool "Round Robin Channel Arbitration"
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default n
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---help---
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Normally, a fixed priority arbitration is used for channel
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selection. If this option is selected, round robin arbitration is
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used for channel selection.
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config KINETIS_EDMA_ERGA
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bool "Round Robin Group Arbitration"
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default n
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---help---
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Normally, a fixed priority arbitration is used for channel
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selection among the groups. If this option is selected,
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round Round robin arbitration is used for selection among
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the groups.
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config KINETIS_EDMA_HOE
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bool "Halt On Error"
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default y
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---help---
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Any error causes the HALT bit to set. Subsequently, all service
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requests are ignored until the HALT bit is cleared.
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config KINETIS_EDMA_CLM
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bool "Continuous Link Mode"
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default n
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---help---
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By default, A minor loop channel link made to itself goes through
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channel arbitration before being activated again. If this option is
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selected, a minor loop channel link made to itself does not go
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through channel arbitration before being activated again. Upon minor
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loop completion, the channel activates again if that channel has a
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minor loop channel link enabled and the link channel is itself. This
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effectively applies the minor loop offsets and restarts the next
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minor loop.
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config KINETIS_EDMA_EMLIM
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bool "Minor Loop Mapping"
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default n
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---help---
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Normally TCD word 2 is a 32-bit NBYTES field. When this option is
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enabled, TCD word 2 is redefined to include individual enable fields,
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an offset field, and the NBYTES field. The individual enable fields
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allow the minor loop offset to be applied to the source address, the
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destination address, or both. The NBYTES field is reduced when either
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offset is enabled.
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config KINETIS_EDMA_EDBG
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bool "Enable Debug"
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default n
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---help---
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When in debug mode, the DMA stalls the start of a new channel. Executing
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channels are allowed to complete. Channel execution resumes when the
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system exits debug mode or the EDBG bit is cleared
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endmenu # eDMA Global Configuration
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if KINETIS_USBHS && USBHOST
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menu "USB host controller driver (HCD) options"
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@ -1208,42 +1298,42 @@ config KINETIS_UARTFIFOS
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config KINETIS_UART0_RXDMA
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bool "UART0 Rx DMA"
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default n
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depends on KINETIS_UART0 && KINETIS_DMA
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depends on KINETIS_UART0 && KINETIS_EDMA
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---help---
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In high data rate usage, Rx DMA may eliminate Rx overrun errors
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config KINETIS_UART1_RXDMA
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bool "UART1 Rx DMA"
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default n
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depends on KINETIS_UART1 && KINETIS_DMA
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depends on KINETIS_UART1 && KINETIS_EDMA
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---help---
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In high data rate usage, Rx DMA may eliminate Rx overrun errors
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config KINETIS_UART2_RXDMA
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bool "UART2 Rx DMA"
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default n
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depends on KINETIS_UART2 && KINETIS_DMA
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depends on KINETIS_UART2 && KINETIS_EDMA
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---help---
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In high data rate usage, Rx DMA may eliminate Rx overrun errors
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config KINETIS_UART3_RXDMA
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bool "UART3 Rx DMA"
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default n
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depends on KINETIS_UART3 && KINETIS_DMA
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depends on KINETIS_UART3 && KINETIS_EDMA
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---help---
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In high data rate usage, Rx DMA may eliminate Rx overrun errors
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config KINETIS_UART4_RXDMA
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bool "UART4 Rx DMA"
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default n
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depends on KINETIS_UART4 && KINETIS_DMA
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depends on KINETIS_UART4 && KINETIS_EDMA
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---help---
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In high data rate usage, Rx DMA may eliminate Rx overrun errors
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config KINETIS_UART5_RXDMA
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bool "UART5 Rx DMA"
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default n
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depends on KINETIS_UART5 && KINETIS_DMA
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depends on KINETIS_UART5 && KINETIS_EDMA
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---help---
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In high data rate usage, Rx DMA may eliminate Rx overrun errors
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@ -140,8 +140,8 @@ CHIP_CSRCS += kinetis_usbhshost.c
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endif
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endif
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ifeq ($(CONFIG_KINETIS_DMA),y)
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CHIP_CSRCS += kinetis_dma.c kinetis_pindma.c
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ifeq ($(CONFIG_KINETIS_EDMA),y)
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CHIP_CSRCS += kinetis_edma.c kinetis_pindma.c
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endif
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ifeq ($(CONFIG_PWM),y)
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@ -1,776 +0,0 @@
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/****************************************************************************
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* arch/arm/src/kinetis/hardware/kinetis_dma.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMA_H
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#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMA_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define KINETIS_DMA_CR_OFFSET 0x0000 /* Control Register */
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#define KINETIS_DMA_ES_OFFSET 0x0004 /* Error Status Register */
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#define KINETIS_DMA_ERQ_OFFSET 0x000c /* Enable Request Register */
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#define KINETIS_DMA_EEI_OFFSET 0x0014 /* Enable Error Interrupt Register */
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#define KINETIS_DMA_CEEI_OFFSET 0x0018 /* Clear Enable Error Interrupt Register */
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#define KINETIS_DMA_SEEI_OFFSET 0x0019 /* Set Enable Error Interrupt Register */
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#define KINETIS_DMA_CERQ_OFFSET 0x001a /* Clear Enable Request Register */
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#define KINETIS_DMA_SERQ_OFFSET 0x001b /* Set Enable Request Register */
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#define KINETIS_DMA_CDNE_OFFSET 0x001c /* Clear DONE Status Bit Register */
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#define KINETIS_DMA_SSRT_OFFSET 0x001d /* Set START Bit Register */
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#define KINETIS_DMA_CERR_OFFSET 0x001e /* Clear Error Register */
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#define KINETIS_DMA_CINT_OFFSET 0x001f /* Clear Interrupt Request Register */
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#define KINETIS_DMA_INT_OFFSET 0x0024 /* Interrupt Request Register */
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#define KINETIS_DMA_ERR_OFFSET 0x002c /* Error Register */
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#define KINETIS_DMA_HRS_OFFSET 0x0034 /* Hardware Request Status Register */
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#define KINETIS_DMA_DCHPRI3_OFFSET 0x0100 /* Channel 3 Priority Register */
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#define KINETIS_DMA_DCHPRI2_OFFSET 0x0101 /* Channel 2 Priority Register */
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#define KINETIS_DMA_DCHPRI1_OFFSET 0x0102 /* Channel 1 Priority Register */
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#define KINETIS_DMA_DCHPRI0_OFFSET 0x0103 /* Channel 0 Priority Register */
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#define KINETIS_DMA_DCHPRI7_OFFSET 0x0104 /* Channel 7 Priority Register */
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#define KINETIS_DMA_DCHPRI6_OFFSET 0x0105 /* Channel 6 Priority Register */
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#define KINETIS_DMA_DCHPRI5_OFFSET 0x0106 /* Channel 5 Priority Register */
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#define KINETIS_DMA_DCHPRI4_OFFSET 0x0107 /* Channel 4 Priority Register */
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#define KINETIS_DMA_DCHPRI11_OFFSET 0x0108 /* Channel 11 Priority Register */
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#define KINETIS_DMA_DCHPRI10_OFFSET 0x0109 /* Channel 10 Priority Register */
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#define KINETIS_DMA_DCHPRI9_OFFSET 0x010a /* Channel 9 Priority Register */
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#define KINETIS_DMA_DCHPRI8_OFFSET 0x010b /* Channel 8 Priority Register */
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#define KINETIS_DMA_DCHPRI15_OFFSET 0x010c /* Channel 15 Priority Register */
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#define KINETIS_DMA_DCHPRI14_OFFSET 0x010d /* Channel 14 Priority Register */
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#define KINETIS_DMA_DCHPRI13_OFFSET 0x010e /* Channel 13 Priority Register */
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#define KINETIS_DMA_DCHPRI12_OFFSET 0x010f /* Channel 12 Priority Register */
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#define KINETIS_DMA_DCHPRI_OFFSET(n) 0x0100 + (n - (n % 4)) + (3 - (n % 4)) /* Channel n Priority Register */
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#define KINETIS_DMA_TCD_OFFSET(n) (0x0000 + ((n) << 5))
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#define KINETIS_DMA_TCD_SADDR_OFFSET 0x0000 /* TCD Source Address */
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#define KINETIS_DMA_TCD_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */
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#define KINETIS_DMA_TCD_ATTR_OFFSET 0x0006 /* TCD Transfer Attributes */
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#define KINETIS_DMA_TCD_NBYTES_OFFSET 0x0008 /* TCD Minor Byte Count */
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#define KINETIS_DMA_TCD_SLAST_OFFSET 0x000c /* TCD Last Source Address Adjustment */
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#define KINETIS_DMA_TCD_DADDR_OFFSET 0x0010 /* TCD Destination Address */
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#define KINETIS_DMA_TCD_DOFF_OFFSET 0x0014 /* TCD Signed Destination Address Offset */
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#define KINETIS_DMA_TCD_CITER_OFFSET 0x0016 /* TCD Current Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD_DLASTSGA_OFFSET 0x0018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
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#define KINETIS_DMA_TCD_CSR_OFFSET 0x001c /* TCD Control and Status */
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#define KINETIS_DMA_TCD_BITER_OFFSET 0x001e /* TCD Beginning Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD0_SADDR_OFFSET 0x0000 /* TCD Source Address */
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#define KINETIS_DMA_TCD0_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */
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#define KINETIS_DMA_TCD0_ATTR_OFFSET 0x0006 /* TCD Transfer Attributes */
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#define KINETIS_DMA_TCD0_NBYTES_OFFSET 0x0008 /* TCD Minor Byte Count */
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#define KINETIS_DMA_TCD0_SLAST_OFFSET 0x000c /* TCD Last Source Address Adjustment */
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#define KINETIS_DMA_TCD0_DADDR_OFFSET 0x0010 /* TCD Destination Address */
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#define KINETIS_DMA_TCD0_DOFF_OFFSET 0x0014 /* TCD Signed Destination Address Offset */
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#define KINETIS_DMA_TCD0_CITER_OFFSET 0x0016 /* TCD Current Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD0_DLASTSGA_OFFSET 0x0018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
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#define KINETIS_DMA_TCD0_CSR_OFFSET 0x001c /* TCD Control and Status */
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#define KINETIS_DMA_TCD0_BITER_OFFSET 0x001e /* TCD Beginning Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD1_SADDR_OFFSET 0x0020 /* TCD Source Address */
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#define KINETIS_DMA_TCD1_SOFF_OFFSET 0x0024 /* TCD Signed Source Address Offset */
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#define KINETIS_DMA_TCD1_ATTR_OFFSET 0x0026 /* TCD Transfer Attributes */
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#define KINETIS_DMA_TCD1_NBYTES_OFFSET 0x0028 /* TCD Minor Byte Count */
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#define KINETIS_DMA_TCD1_SLAST_OFFSET 0x002c /* TCD Last Source Address Adjustment */
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#define KINETIS_DMA_TCD1_DADDR_OFFSET 0x0030 /* TCD Destination Address */
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#define KINETIS_DMA_TCD1_DOFF_OFFSET 0x0034 /* TCD Signed Destination Address Offset */
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#define KINETIS_DMA_TCD1_CITER_OFFSET 0x0036 /* TCD Current Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD1_DLASTSGA_OFFSET 0x0038 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
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#define KINETIS_DMA_TCD1_CSR_OFFSET 0x003c /* TCD Control and Status */
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#define KINETIS_DMA_TCD1_BITER_OFFSET 0x003e /* TCD Beginning Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD2_SADDR_OFFSET 0x0040 /* TCD Source Address */
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#define KINETIS_DMA_TCD2_SOFF_OFFSET 0x0044 /* TCD Signed Source Address Offset */
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#define KINETIS_DMA_TCD2_ATTR_OFFSET 0x0046 /* TCD Transfer Attributes */
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#define KINETIS_DMA_TCD2_NBYTES_OFFSET 0x0048 /* TCD Minor Byte Count */
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#define KINETIS_DMA_TCD2_SLAST_OFFSET 0x004c /* TCD Last Source Address Adjustment */
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#define KINETIS_DMA_TCD2_DADDR_OFFSET 0x0050 /* TCD Destination Address */
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#define KINETIS_DMA_TCD2_DOFF_OFFSET 0x0054 /* TCD Signed Destination Address Offset */
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#define KINETIS_DMA_TCD2_CITER_OFFSET 0x0056 /* TCD Current Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD2_DLASTSGA_OFFSET 0x0058 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
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#define KINETIS_DMA_TCD2_CSR_OFFSET 0x005c /* TCD Control and Status */
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#define KINETIS_DMA_TCD2_BITER_OFFSET 0x005e /* TCD Beginning Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD3_SADDR_OFFSET 0x0060 /* TCD Source Address */
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#define KINETIS_DMA_TCD3_SOFF_OFFSET 0x0064 /* TCD Signed Source Address Offset */
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#define KINETIS_DMA_TCD3_ATTR_OFFSET 0x0066 /* TCD Transfer Attributes */
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#define KINETIS_DMA_TCD3_NBYTES_OFFSET 0x0068 /* TCD Minor Byte Count */
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#define KINETIS_DMA_TCD3_SLAST_OFFSET 0x006c /* TCD Last Source Address Adjustment */
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#define KINETIS_DMA_TCD3_DADDR_OFFSET 0x0070 /* TCD Destination Address */
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#define KINETIS_DMA_TCD3_DOFF_OFFSET 0x0074 /* TCD Signed Destination Address Offset */
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#define KINETIS_DMA_TCD3_CITER_OFFSET 0x0076 /* TCD Current Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD3_DLASTSGA_OFFSET 0x0078 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
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#define KINETIS_DMA_TCD3_CSR_OFFSET 0x007c /* TCD Control and Status */
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#define KINETIS_DMA_TCD3_BITER_OFFSET 0x007e /* TCD Beginning Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD4_SADDR_OFFSET 0x0080 /* TCD Source Address */
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#define KINETIS_DMA_TCD4_SOFF_OFFSET 0x0084 /* TCD Signed Source Address Offset */
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#define KINETIS_DMA_TCD4_ATTR_OFFSET 0x0086 /* TCD Transfer Attributes */
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#define KINETIS_DMA_TCD4_NBYTES_OFFSET 0x0088 /* TCD Minor Byte Count */
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#define KINETIS_DMA_TCD4_SLAST_OFFSET 0x008c /* TCD Last Source Address Adjustment */
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#define KINETIS_DMA_TCD4_DADDR_OFFSET 0x0090 /* TCD Destination Address */
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#define KINETIS_DMA_TCD4_DOFF_OFFSET 0x0094 /* TCD Signed Destination Address Offset */
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#define KINETIS_DMA_TCD4_CITER_OFFSET 0x0096 /* TCD Current Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD4_DLASTSGA_OFFSET 0x0098 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
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#define KINETIS_DMA_TCD4_CSR_OFFSET 0x009c /* TCD Control and Status */
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#define KINETIS_DMA_TCD4_BITER_OFFSET 0x009e /* TCD Beginning Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD5_SADDR_OFFSET 0x00a0 /* TCD Source Address */
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#define KINETIS_DMA_TCD5_SOFF_OFFSET 0x00a4 /* TCD Signed Source Address Offset */
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#define KINETIS_DMA_TCD5_ATTR_OFFSET 0x00a6 /* TCD Transfer Attributes */
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#define KINETIS_DMA_TCD5_NBYTES_OFFSET 0x00a8 /* TCD Minor Byte Count */
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#define KINETIS_DMA_TCD5_SLAST_OFFSET 0x00ac /* TCD Last Source Address Adjustment */
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#define KINETIS_DMA_TCD5_DADDR_OFFSET 0x00b0 /* TCD Destination Address */
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#define KINETIS_DMA_TCD5_DOFF_OFFSET 0x00b4 /* TCD Signed Destination Address Offset */
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#define KINETIS_DMA_TCD5_CITER_OFFSET 0x00b6 /* TCD Current Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD5_DLASTSGA_OFFSET 0x00b8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
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#define KINETIS_DMA_TCD5_CSR_OFFSET 0x00bc /* TCD Control and Status */
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#define KINETIS_DMA_TCD5_BITER_OFFSET 0x00be /* TCD Beginning Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD6_SADDR_OFFSET 0x00c0 /* TCD Source Address */
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#define KINETIS_DMA_TCD6_SOFF_OFFSET 0x00c4 /* TCD Signed Source Address Offset */
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#define KINETIS_DMA_TCD6_ATTR_OFFSET 0x00c6 /* TCD Transfer Attributes */
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#define KINETIS_DMA_TCD6_NBYTES_OFFSET 0x00c8 /* TCD Minor Byte Count */
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#define KINETIS_DMA_TCD6_SLAST_OFFSET 0x00cc /* TCD Last Source Address Adjustment */
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#define KINETIS_DMA_TCD6_DADDR_OFFSET 0x00d0 /* TCD Destination Address */
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#define KINETIS_DMA_TCD6_DOFF_OFFSET 0x00d4 /* TCD Signed Destination Address Offset */
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#define KINETIS_DMA_TCD6_CITER_OFFSET 0x00d6 /* TCD Current Minor Loop Link, Major Loop Count */
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#define KINETIS_DMA_TCD6_DLASTSGA_OFFSET 0x00d8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
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#define KINETIS_DMA_TCD6_CSR_OFFSET 0x00dc /* TCD Control and Status */
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#define KINETIS_DMA_TCD6_BITER_OFFSET 0x00de /* TCD Beginning Minor Loop Link, Major Loop Count */
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|
||||
#define KINETIS_DMA_TCD7_SADDR_OFFSET 0x00e0 /* TCD Source Address */
|
||||
#define KINETIS_DMA_TCD7_SOFF_OFFSET 0x00e4 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_DMA_TCD7_ATTR_OFFSET 0x00e6 /* TCD Transfer Attributes */
|
||||
#define KINETIS_DMA_TCD7_NBYTES_OFFSET 0x00e8 /* TCD Minor Byte Count */
|
||||
#define KINETIS_DMA_TCD7_SLAST_OFFSET 0x00ec /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_DMA_TCD7_DADDR_OFFSET 0x00f0 /* TCD Destination Address */
|
||||
#define KINETIS_DMA_TCD7_DOFF_OFFSET 0x00f4 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_DMA_TCD7_CITER_OFFSET 0x00f6 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_DMA_TCD7_DLASTSGA_OFFSET 0x00f8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_DMA_TCD7_CSR_OFFSET 0x00fc /* TCD Control and Status */
|
||||
#define KINETIS_DMA_TCD7_BITER_OFFSET 0x00fe /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_DMA_TCD8_SADDR_OFFSET 0x0100 /* TCD Source Address */
|
||||
#define KINETIS_DMA_TCD8_SOFF_OFFSET 0x0104 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_DMA_TCD8_ATTR_OFFSET 0x0106 /* TCD Transfer Attributes */
|
||||
#define KINETIS_DMA_TCD8_NBYTES_OFFSET 0x0108 /* TCD Minor Byte Count */
|
||||
#define KINETIS_DMA_TCD8_SLAST_OFFSET 0x010c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_DMA_TCD8_DADDR_OFFSET 0x0110 /* TCD Destination Address */
|
||||
#define KINETIS_DMA_TCD8_DOFF_OFFSET 0x0114 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_DMA_TCD8_CITER_OFFSET 0x0116 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_DMA_TCD8_DLASTSGA_OFFSET 0x0118 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_DMA_TCD8_CSR_OFFSET 0x011c /* TCD Control and Status */
|
||||
#define KINETIS_DMA_TCD8_BITER_OFFSET 0x011e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_DMA_TCD9_SADDR_OFFSET 0x0120 /* TCD Source Address */
|
||||
#define KINETIS_DMA_TCD9_SOFF_OFFSET 0x0124 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_DMA_TCD9_ATTR_OFFSET 0x0126 /* TCD Transfer Attributes */
|
||||
#define KINETIS_DMA_TCD9_NBYTES_OFFSET 0x0128 /* TCD Minor Byte Count */
|
||||
#define KINETIS_DMA_TCD9_SLAST_OFFSET 0x012c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_DMA_TCD9_DADDR_OFFSET 0x0130 /* TCD Destination Address */
|
||||
#define KINETIS_DMA_TCD9_DOFF_OFFSET 0x0134 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_DMA_TCD9_CITER_OFFSET 0x0136 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_DMA_TCD9_DLASTSGA_OFFSET 0x0138 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_DMA_TCD9_CSR_OFFSET 0x013c /* TCD Control and Status */
|
||||
#define KINETIS_DMA_TCD9_BITER_OFFSET 0x013e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_DMA_TCD10_SADDR_OFFSET 0x0140 /* TCD Source Address */
|
||||
#define KINETIS_DMA_TCD10_SOFF_OFFSET 0x0144 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_DMA_TCD10_ATTR_OFFSET 0x0146 /* TCD Transfer Attributes */
|
||||
#define KINETIS_DMA_TCD10_NBYTES_OFFSET 0x0148 /* TCD Minor Byte Count */
|
||||
#define KINETIS_DMA_TCD10_SLAST_OFFSET 0x014c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_DMA_TCD10_DADDR_OFFSET 0x0150 /* TCD Destination Address */
|
||||
#define KINETIS_DMA_TCD10_DOFF_OFFSET 0x0154 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_DMA_TCD10_CITER_OFFSET 0x0156 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_DMA_TCD10_DLASTSGA_OFFSET 0x0158 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_DMA_TCD10_CSR_OFFSET 0x015c /* TCD Control and Status */
|
||||
#define KINETIS_DMA_TCD10_BITER_OFFSET 0x015e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_DMA_TCD11_SADDR_OFFSET 0x0160 /* TCD Source Address */
|
||||
#define KINETIS_DMA_TCD11_SOFF_OFFSET 0x0164 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_DMA_TCD11_ATTR_OFFSET 0x0166 /* TCD Transfer Attributes */
|
||||
#define KINETIS_DMA_TCD11_NBYTES_OFFSET 0x0168 /* TCD Minor Byte Count */
|
||||
#define KINETIS_DMA_TCD11_SLAST_OFFSET 0x016c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_DMA_TCD11_DADDR_OFFSET 0x0170 /* TCD Destination Address */
|
||||
#define KINETIS_DMA_TCD11_DOFF_OFFSET 0x0174 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_DMA_TCD11_CITER_OFFSET 0x0176 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_DMA_TCD11_DLASTSGA_OFFSET 0x0178 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_DMA_TCD11_CSR_OFFSET 0x017c /* TCD Control and Status */
|
||||
#define KINETIS_DMA_TCD11_BITER_OFFSET 0x017e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_DMA_TCD12_SADDR_OFFSET 0x0180 /* TCD Source Address */
|
||||
#define KINETIS_DMA_TCD12_SOFF_OFFSET 0x0184 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_DMA_TCD12_ATTR_OFFSET 0x0186 /* TCD Transfer Attributes */
|
||||
#define KINETIS_DMA_TCD12_NBYTES_OFFSET 0x0188 /* TCD Minor Byte Count */
|
||||
#define KINETIS_DMA_TCD12_SLAST_OFFSET 0x018c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_DMA_TCD12_DADDR_OFFSET 0x0190 /* TCD Destination Address */
|
||||
#define KINETIS_DMA_TCD12_DOFF_OFFSET 0x0194 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_DMA_TCD12_CITER_OFFSET 0x0196 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_DMA_TCD12_DLASTSGA_OFFSET 0x0198 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_DMA_TCD12_CSR_OFFSET 0x019c /* TCD Control and Status */
|
||||
#define KINETIS_DMA_TCD12_BITER_OFFSET 0x019e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_DMA_TCD13_SADDR_OFFSET 0x01a0 /* TCD Source Address */
|
||||
#define KINETIS_DMA_TCD13_SOFF_OFFSET 0x01a4 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_DMA_TCD13_ATTR_OFFSET 0x01a6 /* TCD Transfer Attributes */
|
||||
#define KINETIS_DMA_TCD13_NBYTES_OFFSET 0x01a8 /* TCD Minor Byte Count */
|
||||
#define KINETIS_DMA_TCD13_SLAST_OFFSET 0x01ac /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_DMA_TCD13_DADDR_OFFSET 0x01b0 /* TCD Destination Address */
|
||||
#define KINETIS_DMA_TCD13_DOFF_OFFSET 0x01b4 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_DMA_TCD13_CITER_OFFSET 0x01b6 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_DMA_TCD13_DLASTSGA_OFFSET 0x01b8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_DMA_TCD13_CSR_OFFSET 0x01bc /* TCD Control and Status */
|
||||
#define KINETIS_DMA_TCD13_BITER_OFFSET 0x01be /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_DMA_TCD14_SADDR_OFFSET 0x01c0 /* TCD Source Address */
|
||||
#define KINETIS_DMA_TCD14_SOFF_OFFSET 0x01c4 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_DMA_TCD14_ATTR_OFFSET 0x01c6 /* TCD Transfer Attributes */
|
||||
#define KINETIS_DMA_TCD14_NBYTES_OFFSET 0x01c8 /* TCD Minor Byte Count */
|
||||
#define KINETIS_DMA_TCD14_SLAST_OFFSET 0x01cc /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_DMA_TCD14_DADDR_OFFSET 0x01d0 /* TCD Destination Address */
|
||||
#define KINETIS_DMA_TCD14_DOFF_OFFSET 0x01d4 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_DMA_TCD14_CITER_OFFSET 0x01d6 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_DMA_TCD14_DLASTSGA_OFFSET 0x01d8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_DMA_TCD14_CSR_OFFSET 0x01dc /* TCD Control and Status */
|
||||
#define KINETIS_DMA_TCD14_BITER_OFFSET 0x01de /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_DMA_TCD15_SADDR_OFFSET 0x01e0 /* TCD Source Address */
|
||||
#define KINETIS_DMA_TCD15_SOFF_OFFSET 0x01e4 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_DMA_TCD15_ATTR_OFFSET 0x01e6 /* TCD Transfer Attributes */
|
||||
#define KINETIS_DMA_TCD15_NBYTES_OFFSET 0x01e8 /* TCD Minor Byte Count */
|
||||
#define KINETIS_DMA_TCD15_SLAST_OFFSET 0x01ec /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_DMA_TCD15_DADDR_OFFSET 0x01f0 /* TCD Destination Address */
|
||||
#define KINETIS_DMA_TCD15_DOFF_OFFSET 0x01f4 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_DMA_TCD15_CITER_OFFSET 0x01f6 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_DMA_TCD15_DLASTSGA_OFFSET 0x01f8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_DMA_TCD15_CSR_OFFSET 0x01fc /* TCD Control and Status */
|
||||
#define KINETIS_DMA_TCD15_BITER_OFFSET 0x01fe /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
/* Register Addresses *******************************************************/
|
||||
|
||||
#define KINETIS_DMA_CR (KINETIS_DMAC_BASE + KINETIS_DMA_CR_OFFSET)
|
||||
#define KINETIS_DMA_ES (KINETIS_DMAC_BASE + KINETIS_DMA_ES_OFFSET)
|
||||
#define KINETIS_DMA_ERQ (KINETIS_DMAC_BASE + KINETIS_DMA_ERQ_OFFSET)
|
||||
#define KINETIS_DMA_EEI (KINETIS_DMAC_BASE + KINETIS_DMA_EEI_OFFSET)
|
||||
#define KINETIS_DMA_CEEI (KINETIS_DMAC_BASE + KINETIS_DMA_CEEI_OFFSET)
|
||||
#define KINETIS_DMA_SEEI (KINETIS_DMAC_BASE + KINETIS_DMA_SEEI_OFFSET)
|
||||
#define KINETIS_DMA_CERQ (KINETIS_DMAC_BASE + KINETIS_DMA_CERQ_OFFSET)
|
||||
#define KINETIS_DMA_SERQ (KINETIS_DMAC_BASE + KINETIS_DMA_SERQ_OFFSET)
|
||||
#define KINETIS_DMA_CDNE (KINETIS_DMAC_BASE + KINETIS_DMA_CDNE_OFFSET)
|
||||
#define KINETIS_DMA_SSRT (KINETIS_DMAC_BASE + KINETIS_DMA_SSRT_OFFSET)
|
||||
#define KINETIS_DMA_CERR (KINETIS_DMAC_BASE + KINETIS_DMA_CERR_OFFSET)
|
||||
#define KINETIS_DMA_CINT (KINETIS_DMAC_BASE + KINETIS_DMA_CINT_OFFSET)
|
||||
#define KINETIS_DMA_INT (KINETIS_DMAC_BASE + KINETIS_DMA_INT_OFFSET)
|
||||
#define KINETIS_DMA_ERR (KINETIS_DMAC_BASE + KINETIS_DMA_ERR_OFFSET)
|
||||
#define KINETIS_DMA_HRS (KINETIS_DMAC_BASE + KINETIS_DMA_HRS_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_DCHPRI(n) (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI_OFFSET(n))
|
||||
|
||||
#define KINETIS_DMA_DCHPRI3 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI3_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI2 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI2_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI1 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI1_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI0 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI0_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI7 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI7_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI6 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI6_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI5 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI5_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI4 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI4_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI11 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI11_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI10 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI10_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI9 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI9_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI8 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI8_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI15 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI15_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI14 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI14_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI13 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI13_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI12 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI12_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD_BASE(n) (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD_OFFSET(n))
|
||||
|
||||
#define KINETIS_DMA_TCD_SADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD_SOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD_ATTR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD_NBYTES(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD_SLAST(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD_DADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD_DOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD_CITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD_DLASTSGA(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD_CSR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD_BITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD0_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD1_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD2_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_CSR_ (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD3_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_DLASTSGA_OFFSET
|
||||
#define KINETIS_DMA_TCD3_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD4_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_ATTR_OFFSET0)
|
||||
#define KINETIS_DMA_TCD4_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD5_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD6_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD7_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_DLASTSGA_ (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD8_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD9_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD10_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD11_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD12_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD13_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD14_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD15_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_BITER_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *************************************************/
|
||||
|
||||
/* Control Register (32-bit) */
|
||||
|
||||
/* Bit 0: Reserved */
|
||||
#define DMA_CR_EDBG (1 << 1) /* Bit 1: Enable debug */
|
||||
#define DMA_CR_ERCA (1 << 2) /* Bit 2: Enable round robin channel arbitration */
|
||||
#if defined KINETIS_DMA_HAS_CR_ERGA
|
||||
# define DMA_CR_ERGA (1 << 3) /* Bit 3: Enable round robin group arbitration */
|
||||
#endif
|
||||
#define DMA_CR_HOE (1 << 4) /* Bit 4: Halt on error */
|
||||
#define DMA_CR_HALT (1 << 5) /* Bit 5: Halt DMA operations */
|
||||
#define DMA_CR_CLM (1 << 6) /* Bit 6: Continuous link mode */
|
||||
#define DMA_CR_EMLM (1 << 7) /* Bit 7: Enable minor loop mapping */
|
||||
#ifdef KINETIS_DMA_HAS_CR_GRP0PRI
|
||||
# define DMA_CR_GRP0PRI (1 << 8) /* Bit 8: Channel Group 0 Priority */
|
||||
#endif
|
||||
/* Bit 9: Reserved */
|
||||
#ifdef KINETIS_DMA_HAS_CR_GRP1PRI
|
||||
# define DMA_CR_GRP1PRI (1 << 10) /* Bit 10: Channel Group 1 Priority */
|
||||
#endif
|
||||
/* Bits 11-15: Reserved */
|
||||
#define DMA_CR_ECX (1 << 16) /* Bit 16: Error cancel transfer */
|
||||
#define DMA_CR_CX (1 << 17) /* Bit 17: Cancel transfer */
|
||||
/* Bits 18-31: Reserved */
|
||||
|
||||
/* Error Status Register */
|
||||
|
||||
#define DMA_ES_DBE (1 << 0) /* Bit 0: Destination bus error */
|
||||
#define DMA_ES_SBE (1 << 1) /* Bit 1: Source bus error */
|
||||
#define DMA_ES_SGE (1 << 2) /* Bit 2: Scatter/gather configuration error */
|
||||
#define DMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER configuration error */
|
||||
#define DMA_ES_DOE (1 << 4) /* Bit 4: Destination offset error */
|
||||
#define DMA_ES_DAE (1 << 5) /* Bit 5: Destination address error */
|
||||
#define DMA_ES_SOE (1 << 6) /* Bit 6: Source offset error */
|
||||
#define DMA_ES_SAE (1 << 7) /* Bit 7: Source address error */
|
||||
#define DMA_ES_ERRCHN_SHIFT (8) /* Bits 8-11/12: Error channel number or cancelled channel number */
|
||||
#define DMA_ES_ERRCHN_MASK (((1 << KINETIS_DMA_HAS_ES_ERRCHN_BITS) - 1) << DMA_ES_ERRCHN_SHIFT)
|
||||
/* Bits 13: Reserved */
|
||||
#define DMA_ES_CPE (1 << 14) /* Bit 14: Channel priority error */
|
||||
#ifdef KINETIS_DMA_HAS_ES_GPE
|
||||
# define DMA_ES_GPE (1 << 15) /* Bit 15: Group priority error */
|
||||
#endif
|
||||
#define DMA_ES_ECX (1 << 16) /* Bit 16: Transfer cancelled */
|
||||
/* Bits 17-30: Reserved */
|
||||
#define DMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status bits */
|
||||
|
||||
/* Enable Request Register (ERQ), Enable Error Interrupt Register (EEI),
|
||||
* Interrupt Request Register (INT), Error Register (ERR),
|
||||
* Hardware Request Status Register (HRS) common bit definitions
|
||||
*/
|
||||
|
||||
#define DMA_REQ(n) (1 << (n)) /* Bit n: DMA Request n, n=0..<KINETIS_NDMACH */
|
||||
/* Bits KINETIS_NDMACH-31: Reserved */
|
||||
|
||||
/* Clear Enable Error Interrupt Register (8-bit) */
|
||||
|
||||
#define DMA_CEEI_SHIFT (0) /* Bits 0-3/4: Clear enable error interrupt */
|
||||
#define DMA_CEEI_MASK (((1 << KINETIS_DMA_HAS_CEEI_CEEI_BITS) - 1) << DMA_CEEI_SHIFT)
|
||||
/* Bits 5: Reserved */
|
||||
#define DMA_CEEI_CAEE (1 << 6) /* Bit 6: Clear all enable error interrupts */
|
||||
#define DMA_CEEI_NOP (1 << 7) /* Bit 7: No operation */
|
||||
|
||||
/* Set Enable Error Interrupt Register (8-bit) */
|
||||
|
||||
#define DMA_SEEI_SHIFT (0) /* Bits 0-3/4: Set enable error interrupt */
|
||||
#define DMA_SEEI_MASK (((1 << KINETIS_DMA_HAS_SEEI_SEEI_BITS) - 1) << DMA_SEEI_SHIFT)
|
||||
/* Bits 5: Reserved */
|
||||
#define DMA_SEEI_SAEE (1 << 6) /* Bit 6: Set all enable error interrupts */
|
||||
#define DMA_SEEI_NOP (1 << 7) /* Bit 7: No operation */
|
||||
|
||||
/* Clear Enable Request Register (8-bit) */
|
||||
|
||||
#define DMA_CERQ_SHIFT (0) /* Bits 0-3: Clear enable request */
|
||||
#define DMA_CERQ_MASK (((1 << KINETIS_DMA_HAS_CERQ_CERQ_BITS) - 1) << DMA_CERQ_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_CERQ_CAER (1 << 6) /* Bit 6: Clear all enable requests */
|
||||
#define DMA_CERQ_NOP (1 << 7) /* Bit 7: No operation */
|
||||
|
||||
/* Set Enable Request Register (8-bit) */
|
||||
|
||||
#define DMA_SERQ_SHIFT (0) /* Bits 0-3: Set enable request */
|
||||
#define DMA_SERQ_MASK (((1 << KINETIS_DMA_HAS_SERQ_SERQ_BITS) - 1) << DMA_SERQ_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_SERQ_SAER (1 << 6) /* Bit 6: Set all enable requests */
|
||||
#define DMA_SERQ_NOP (1 << 7) /* Bit 7: No operation */
|
||||
|
||||
/* Clear DONE Status Bit Register (8-bit) */
|
||||
#define DMA_CDNE_SHIFT (0) /* Bits 0-3: Clear DONE bit */
|
||||
#define DMA_CDNE_MASK (((1 << KINETIS_DMA_HAS_CDNE_CDNE_BITS) - 1) << DMA_CDNE_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_CDNE_CADN (1 << 6) /* Bit 6: Clears all DONE bits */
|
||||
#define DMA_CDNE_NOP (1 << 7) /* Bit 7: No operation */
|
||||
|
||||
/* Set START Bit Register (8-bit) */
|
||||
|
||||
#define DMA_SSRT_SHIFT (0) /* Bits 0-3: Set START bit */
|
||||
#define DMA_SSRT_MASK (((1 << KINETIS_DMA_HAS_SSRT_SSRT_BITS) - 1) << DMA_SSRT_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_SSRT_SAST (1 << 6) /* Bit 6: Set all START bits (activates all channels) */
|
||||
#define DMA_SSRT_NOP (1 << 7) /* Bit 7: No operation */
|
||||
|
||||
/* Clear Error Register (8-bit) */
|
||||
|
||||
#define DMA_CERR_SHIFT (0) /* Bits 0-3: Clear error indicator */
|
||||
#define DMA_CERR_MASK (((1 << KINETIS_DMA_HAS_CERR_CERR_BITS) - 1) << DMA_CERR_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_CERR_CAEI (1 << 6) /* Bit 6: Clear all error indicators */
|
||||
#define DMA_CERR_NOP (1 << 7) /* Bit 7: No operation */
|
||||
|
||||
/* Clear Interrupt Request Register (8-bit) */
|
||||
|
||||
#define DMA_CINT_SHIFT (0) /* Bits 0-3: Clear interrupt request */
|
||||
#define DMA_CINT_MASK (((1 << KINETIS_DMA_HAS_CINT_CINT_BITS) - 1) << DMA_CINT_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_CINT_CAIR (1 << 6) /* Bit 6: Clear all interrupt requests */
|
||||
#define DMA_CINT_NOP (1 << 7) /* Bit 7: No operation */
|
||||
|
||||
/* Channel n Priority Register (8-bit) */
|
||||
|
||||
#define DMA_DCHPR_SHIFT (0) /* Bits 0-3: Channel n arbitration priority */
|
||||
#define DMA_DCHPR_MASK (((1 << KINETIS_DMA_HAS_DCHPRI_CHPRI_BITS) - 1) << DMA_DCHPR_SHIFT)
|
||||
#ifdef KINETIS_DMA_HAS_DCHPRI_GRPPRI
|
||||
# define DMA_DCHPR_GRPPRI (1 << 4) /* Bits 4-5: Channel n Current Group Priority */
|
||||
#endif
|
||||
#define DMA_DCHPR_DPA (1 << 6) /* Bit 6: Disable preempt ability */
|
||||
#define DMA_DCHPR_ECP (1 << 7) /* Bit 7: Enable channel preemption */
|
||||
|
||||
/* Enable Asynchronous Request in Stop Register (32-bit) */
|
||||
|
||||
#ifdef KINETIS_DMA_HAS_EARS
|
||||
# define DMA_EARS(n) (1 << (n)) /* Bit n: DMA EARS n, n=0..<KINETIS_NDMACH */
|
||||
#endif
|
||||
|
||||
/* TCD Source Address. 32-bit address value. */
|
||||
|
||||
/* TCD Signed Source Address Offset. 32-bit offset value. */
|
||||
|
||||
/* TCD Transfer Attributes (16-bit) */
|
||||
|
||||
#define DMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination data transfer size */
|
||||
#define DMA_TCD_ATTR_DSIZE_MASK (7 << DMA_TCD_ATTR_DSIZE_SHIFT)
|
||||
# define DMA_TCD_ATTR_DSIZE_8BIT (0 << DMA_TCD_ATTR_DSIZE_SHIFT) /* 8-bit */
|
||||
# define DMA_TCD_ATTR_DSIZE_16BIT (1 << DMA_TCD_ATTR_DSIZE_SHIFT) /* 16-bit */
|
||||
# define DMA_TCD_ATTR_DSIZE_32BIT (2 << DMA_TCD_ATTR_DSIZE_SHIFT) /* 32-bit */
|
||||
# define DMA_TCD_ATTR_DSIZE_16BYTE (4 << DMA_TCD_ATTR_DSIZE_SHIFT) /* 16-byte */
|
||||
|
||||
#define DMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination address modulo */
|
||||
#define DMA_TCD_ATTR_DMOD_MASK (31 << DMA_TCD_ATTR_DMOD_SHIFT)
|
||||
#define DMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source data transfer size */
|
||||
#define DMA_TCD_ATTR_SSIZE_MASK (7 << DMA_TCD_ATTR_SSIZE_SHIFT)
|
||||
# define DMA_TCD_ATTR_SSIZE_8BIT (0 << DMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
|
||||
# define DMA_TCD_ATTR_SSIZE_16BIT (1 << DMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
|
||||
# define DMA_TCD_ATTR_SSIZE_32BIT (2 << DMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
|
||||
# define DMA_TCD_ATTR_SSIZE_16BYTE (4 << DMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */
|
||||
|
||||
#define DMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source address modulo */
|
||||
#define DMA_TCD_ATTR_SMOD_MASK (31 << DMA_TCD_ATTR_SMOD_SHIFT)
|
||||
|
||||
/* TCD Minor Byte Count.
|
||||
* Case 1: Minor Loop Disabled.
|
||||
* In this case, the register holds a simple 32-bit count value.
|
||||
* Case 2: Minor Loop Enabled and Offset Disabled:
|
||||
*/
|
||||
|
||||
#define DMA_TCD_NBYTES2_SHIFT (0) /* Bits 0-29: Minor byte transfer count */
|
||||
#define DMA_TCD_NBYTES2_MASK (0x3fffffff)
|
||||
#define DMA_TCD_NBYTES_DMLOE (1 << 30) /* Bit 30: Destination minor loop offset enable (Case 2&3) */
|
||||
#define DMA_TCD_NBYTES_SMLOE (1 << 31) /* Bit 31: Source minor loop offset enable (Case 2&3) */
|
||||
|
||||
/* Case 3: (Minor Loop and Offset Enabled): */
|
||||
|
||||
#define DMA_TCD_NBYTES3_SHIFT (0) /* Bits 0-9: Minor byte transfer count */
|
||||
#define DMA_TCD_NBYTES3_MASK (0x3ff << DMA_TCD_NBYTES3_SHIFT)
|
||||
#define DMA_TCD_NBYTES_MLOFF_SHIFT (10) /* Bits 10-29: Sign-extended address offset */
|
||||
#define DMA_TCD_NBYTES_MLOFF_MASK (0xfffff << DMA_TCD_NBYTES_MLOFF_SHIFT)
|
||||
/* Bit 30: Same as Case 2 */
|
||||
/* Bit 31: Same as Case 2 */
|
||||
|
||||
/* TCD Last Source Address Adjustment. 32-bit address value. */
|
||||
|
||||
/* TCD Destination Address. 32-bit address value. */
|
||||
|
||||
/* TCD Signed Destination Address Offset. 32-bit offset value. */
|
||||
|
||||
/* TCD Current Minor Loop Link, Major Loop Count. 16-bit.
|
||||
* Case 1: Channel Linking Enabled:
|
||||
*/
|
||||
|
||||
#define DMA_TCD_CITER1_SHIFT (0) /* Bits 0-8: Current major iteration count */
|
||||
#define DMA_TCD_CITER1_MASK (0x1ff << DMA_TCD_CITER1_SHIFT)
|
||||
#define DMA_TCD_CITER1_LINKCH_SHIFT (9) /* Bits 9-12/13: Link channel number */
|
||||
#define DMA_TCD_CITER1_LINKCH_MASK (((1 << KINETIS_DMA_HAS_TCD_CITER1_LINKCH_BITS) - 1) << DMA_TCD_CITER1_LINKCH_SHIFT)
|
||||
/* Bits 14: Reserved */
|
||||
#define DMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking on minor-loop complete (Case 1&2) */
|
||||
|
||||
/* Case 2: Channel Linking Disabled: */
|
||||
|
||||
#define DMA_TCD_CITER2_SHIFT (0) /* Bits 0-14: Current major iteration count */
|
||||
#define DMA_TCD_CITER2_MASK (0x7fff << DMA_TCD_CITER2_SHIFT)
|
||||
/* Bits 15: Same as Case 1 */
|
||||
|
||||
/* TCD Last Destination Address Adjustment/Scatter Gather Address.
|
||||
* 32-bit address value.
|
||||
*/
|
||||
|
||||
/* TCD Control and Status (16-bit) */
|
||||
|
||||
#define DMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel start */
|
||||
#define DMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable an interrupt when major iteration count completes */
|
||||
#define DMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable an interrupt when major counter is half complete */
|
||||
#define DMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable request */
|
||||
#define DMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable scatter/gather processing */
|
||||
#define DMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable channel-to-channel linking on major loop complete */
|
||||
#define DMA_TCD_CSR_ACTIVE (1 << 6) /* Bit 6: Channel active */
|
||||
#define DMA_TCD_CSR_DONE (1 << 7) /* Bit 7: Channel done */
|
||||
#define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-11/12: Link channel number */
|
||||
#define DMA_TCD_CSR_MAJORLINKCH_MASK (((1 << KINETIS_DMA_HAS_TCD_CSR_MAJORLINKCH_BITS) - 1) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)
|
||||
/* Bits 13: Reserved */
|
||||
#define DMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth control */
|
||||
#define DMA_TCD_CSR_BWC_MASK (3 << DMA_TCD_CSR_BWC_SHIFT)
|
||||
# define DMA_TCD_CSR_BWC_NOSTALLS (0 << DMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */
|
||||
# define DMA_TCD_CSR_BWC_4CYCLES (2 << DMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls 4 cycles after each R/W */
|
||||
# define DMA_TCD_CSR_BWC_8CYCLES (3 << DMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls 8 cycles after each R/W */
|
||||
|
||||
/* TCD Beginning Minor Loop Link, Major Loop Count (16-bit).
|
||||
*
|
||||
* Case 1: Channel Linking Enabled:
|
||||
*/
|
||||
|
||||
#define DMA_TCD_BITER1_SHIFT (0) /* Bits 0-8: Starting major iteration count */
|
||||
#define DMA_TCD_BITER1_MASK (0x1ff << DMA_TCD_BITER1_SHIFT)
|
||||
#define DMA_TCD_BITER1_LINKCH_SHIFT (9) /* Bits 9-12: Link channel number */
|
||||
#define DMA_TCD_BITER1_LINKCH_MASK (((1 << KINETIS_DMA_HAS_TCD_BITER1_LINKCH_BITS) - 1) << DMA_TCD_BITER1_LINKCH_SHIFT)
|
||||
/* Bits 13-14: Reserved */
|
||||
#define DMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking on minor-loop complete (Case 1&2) */
|
||||
|
||||
/* Case 2: Channel Linking Disabled: */
|
||||
|
||||
#define DMA_TCD_BITER2_SHIFT (0) /* Bits 0-14: Starting major iteration count */
|
||||
#define DMA_TCD_BITER2_MASK (0x7fff << DMA_TCD_CITER2_SHIFT)
|
||||
/* Bits 15: Same as Case 1 */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_DMA_H */
|
||||
@ -56,7 +56,7 @@
|
||||
/* Channel n Configuration Register */
|
||||
|
||||
#define DMAMUX_CHCFG_SOURCE_SHIFT (0) /* Bits 0-5: DMA Channel Source (slot) */
|
||||
#define DMAMUX_CHCFG_SOURCE_MASK (63 << DMAMUX_CHCFG_SOURCE_SHIFT)
|
||||
#define DMAMUX_CHCFG_SOURCE_MASK (0x3f << DMAMUX_CHCFG_SOURCE_SHIFT)
|
||||
#define DMAMUX_CHCFG_TRIG (1 << 6) /* Bit 6: DMA Channel Trigger Enable */
|
||||
#define DMAMUX_CHCFG_ENBL (1 << 7) /* Bit 7: DMA Channel Enable */
|
||||
|
||||
|
||||
855
arch/arm/src/kinetis/hardware/kinetis_edma.h
Normal file
855
arch/arm/src/kinetis/hardware/kinetis_edma.h
Normal file
@ -0,0 +1,855 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/kinetis/hardware/kinetis_edma.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EDMA_H
|
||||
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EDMA_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/kinetis_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define KINETIS_EDMA_NCHANNELS 16
|
||||
|
||||
/* eDMA Register Offsets ****************************************************/
|
||||
|
||||
#define KINETIS_EDMA_CR_OFFSET 0x0000 /* Control */
|
||||
#define KINETIS_EDMA_ES_OFFSET 0x0004 /* Error Status */
|
||||
#define KINETIS_EDMA_ERQ_OFFSET 0x000c /* Enable Request */
|
||||
#define KINETIS_EDMA_EEI_OFFSET 0x0014 /* Enable Error Interrupt */
|
||||
#define KINETIS_EDMA_CEEI_OFFSET 0x0018 /* Clear Enable Error Interrupt */
|
||||
#define KINETIS_EDMA_SEEI_OFFSET 0x0019 /* Set Enable Error Interrupt */
|
||||
#define KINETIS_EDMA_CERQ_OFFSET 0x001a /* Clear Enable Request */
|
||||
#define KINETIS_EDMA_SERQ_OFFSET 0x001b /* Set Enable Request */
|
||||
#define KINETIS_EDMA_CDNE_OFFSET 0x001c /* Clear DONE Status Bit */
|
||||
#define KINETIS_EDMA_SSRT_OFFSET 0x001d /* Set START Bit */
|
||||
#define KINETIS_EDMA_CERR_OFFSET 0x001e /* Clear Error */
|
||||
#define KINETIS_EDMA_CINT_OFFSET 0x001f /* Clear Interrupt Request */
|
||||
#define KINETIS_EDMA_INT_OFFSET 0x0024 /* Interrupt Request */
|
||||
#define KINETIS_EDMA_ERR_OFFSET 0x002c /* Error */
|
||||
#define KINETIS_EDMA_HRS_OFFSET 0x0034 /* Hardware Request Status */
|
||||
#define KINETIS_EDMA_EARS_OFFSET 0x0044 /* Enable Asynchronous Request in Stop */
|
||||
|
||||
#define KINETIS_EDMA_DCHPRI_OFFSET(n) (0x0100 + ((n) & ~3) + (3 - ((n) & 3)))
|
||||
|
||||
#define KINETIS_EDMA_DCHPRI3_OFFSET 0x0100 /* Channel 3 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI2_OFFSET 0x0101 /* Channel 2 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI1_OFFSET 0x0102 /* Channel 1 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI0_OFFSET 0x0103 /* Channel 0 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI7_OFFSET 0x0104 /* Channel 7 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI6_OFFSET 0x0105 /* Channel 6 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI5_OFFSET 0x0106 /* Channel 5 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI4_OFFSET 0x0107 /* Channel 4 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI11_OFFSET 0x0108 /* Channel 11 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI10_OFFSET 0x0109 /* Channel 10 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI9_OFFSET 0x010a /* Channel 9 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI8_OFFSET 0x010b /* Channel 8 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI15_OFFSET 0x010c /* Channel 15 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI14_OFFSET 0x010d /* Channel 14 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI13_OFFSET 0x010e /* Channel 13 Priority */
|
||||
#define KINETIS_EDMA_DCHPRI12_OFFSET 0x010f /* Channel 12 Priority */
|
||||
|
||||
/* Transfer Control Descriptor (TCD) */
|
||||
|
||||
#define KINETIS_EDMA_TCD_OFFSET(n) (0x1000 + ((n) << 5))
|
||||
#define KINETIS_EDMA_TCD_SADDR_OFFSET 0x0000 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD_ATTR_OFFSET 0x0006 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD_NBYTES_ML_OFFSET 0x0008 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD_SLAST_OFFSET 0x000c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD_DADDR_OFFSET 0x0010 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD_DOFF_OFFSET 0x0014 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD_CITER_ELINK_OFFSET 0x0016 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD_DLASTSGA_OFFSET 0x0018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD_CSR_OFFSET 0x001c /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD_BITER_ELINK_OFFSET 0x001e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD0_SADDR_OFFSET 0x1000 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD0_SOFF_OFFSET 0x1004 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD0_ATTR_OFFSET 0x1006 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD0_NBYTES_ML_OFFSET 0x1008 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD0_SLAST_OFFSET 0x100c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD0_DADDR_OFFSET 0x1010 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD0_DOFF_OFFSET 0x1014 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD0_CITER_ELINK_OFFSET 0x1016 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD0_DLASTSGA_OFFSET 0x1018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD0_CSR_OFFSET 0x101c /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD0_BITER_ELINK_OFFSET 0x101e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD1_SADDR_OFFSET 0x1020 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD1_SOFF_OFFSET 0x1024 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD1_ATTR_OFFSET 0x1026 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD1_NBYTES_ML_OFFSET 0x1028 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD1_SLAST_OFFSET 0x102c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD1_DADDR_OFFSET 0x1030 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD1_DOFF_OFFSET 0x1034 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD1_CITER_ELINK_OFFSET 0x1036 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD1_DLASTSGA_OFFSET 0x1038 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD1_CSR_OFFSET 0x103c /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD1_BITER_ELINK_OFFSET 0x103e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD1_SADDR_OFFSET 0x1020 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD1_SOFF_OFFSET 0x1024 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD1_ATTR_OFFSET 0x1026 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD1_NBYTES_ML_OFFSET 0x1028 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD1_SLAST_OFFSET 0x102c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD1_DADDR_OFFSET 0x1030 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD1_DOFF_OFFSET 0x1034 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD1_CITER_ELINK_OFFSET 0x1036 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD1_DLASTSGA_OFFSET 0x1038 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD1_CSR_OFFSET 0x103c /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD1_BITER_ELINK_OFFSET 0x103e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD2_SADDR_OFFSET 0x1040 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD2_SOFF_OFFSET 0x1044 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD2_ATTR_OFFSET 0x1046 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD2_NBYTES_ML_OFFSET 0x1048 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD2_SLAST_OFFSET 0x104c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD2_DADDR_OFFSET 0x1050 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD2_DOFF_OFFSET 0x1054 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD2_CITER_ELINK_OFFSET 0x1056 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD2_DLASTSGA_OFFSET 0x1058 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD2_CSR_OFFSET 0x105c /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD2_BITER_ELINK_OFFSET 0x105e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD3_SADDR_OFFSET 0x1060 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD3_SOFF_OFFSET 0x1064 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD3_ATTR_OFFSET 0x1066 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD3_NBYTES_ML_OFFSET 0x1068 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD3_SLAST_OFFSET 0x106c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD3_DADDR_OFFSET 0x1070 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD3_DOFF_OFFSET 0x1074 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD3_CITER_ELINK_OFFSET 0x1076 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD3_DLASTSGA_OFFSET 0x1078 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD3_CSR_OFFSET 0x107c /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD3_BITER_ELINK_OFFSET 0x107e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD4_SADDR_OFFSET 0x1080 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD4_SOFF_OFFSET 0x1084 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD4_ATTR_OFFSET 0x1086 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD4_NBYTES_ML_OFFSET 0x1088 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD4_SLAST_OFFSET 0x108c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD4_DADDR_OFFSET 0x1090 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD4_DOFF_OFFSET 0x1094 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD4_CITER_ELINK_OFFSET 0x1096 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD4_DLASTSGA_OFFSET 0x1098 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD4_CSR_OFFSET 0x109c /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD4_BITER_ELINK_OFFSET 0x109e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD5_SADDR_OFFSET 0x10a0 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD5_SOFF_OFFSET 0x10a4 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD5_ATTR_OFFSET 0x10a6 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD5_NBYTES_ML_OFFSET 0x10a8 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD5_SLAST_OFFSET 0x10ac /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD5_DADDR_OFFSET 0x10b0 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD5_DOFF_OFFSET 0x10b4 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD5_CITER_ELINK_OFFSET 0x10b6 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD5_DLASTSGA_OFFSET 0x10b8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD5_CSR_OFFSET 0x10bc /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD5_BITER_ELINK_OFFSET 0x10be /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD6_SADDR_OFFSET 0x10c0 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD6_SOFF_OFFSET 0x10c4 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD6_ATTR_OFFSET 0x10c6 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD6_NBYTES_ML_OFFSET 0x10c8 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD6_SLAST_OFFSET 0x10cc /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD6_DADDR_OFFSET 0x10d0 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD6_DOFF_OFFSET 0x10d4 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD6_CITER_ELINK_OFFSET 0x10d6 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD6_DLASTSGA_OFFSET 0x10d8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD6_CSR_OFFSET 0x10dc /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD6_BITER_ELINK_OFFSET 0x10de /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD7_SADDR_OFFSET 0x10e0 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD7_SOFF_OFFSET 0x10e4 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD7_ATTR_OFFSET 0x10e6 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD7_NBYTES_ML_OFFSET 0x10e8 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD7_SLAST_OFFSET 0x10ec /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD7_DADDR_OFFSET 0x10f0 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD7_DOFF_OFFSET 0x10f4 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD7_CITER_ELINK_OFFSET 0x10f6 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD7_DLASTSGA_OFFSET 0x10f8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD7_CSR_OFFSET 0x10fc /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD7_BITER_ELINK_OFFSET 0x10fe /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD8_SADDR_OFFSET 0x1100 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD8_SOFF_OFFSET 0x1104 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD8_ATTR_OFFSET 0x1106 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD8_NBYTES_ML_OFFSET 0x1108 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD8_SLAST_OFFSET 0x110c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD8_DADDR_OFFSET 0x1110 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD8_DOFF_OFFSET 0x1114 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD8_CITER_ELINK_OFFSET 0x1116 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD8_DLASTSGA_OFFSET 0x1118 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD8_CSR_OFFSET 0x111c /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD8_BITER_ELINK_OFFSET 0x111e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD9_SADDR_OFFSET 0x1120 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD9_SOFF_OFFSET 0x1124 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD9_ATTR_OFFSET 0x1126 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD9_NBYTES_ML_OFFSET 0x1128 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD9_SLAST_OFFSET 0x112c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD9_DADDR_OFFSET 0x1130 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD9_DOFF_OFFSET 0x1134 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD9_CITER_ELINK_OFFSET 0x1136 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD9_DLASTSGA_OFFSET 0x1138 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD9_CSR_OFFSET 0x113c /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD9_BITER_ELINK_OFFSET 0x113e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD10_SADDR_OFFSET 0x1140 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD10_SOFF_OFFSET 0x1144 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD10_ATTR_OFFSET 0x1146 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD10_NBYTES_ML_OFFSET 0x1148 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD10_SLAST_OFFSET 0x114c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD10_DADDR_OFFSET 0x1150 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD10_DOFF_OFFSET 0x1154 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD10_CITER_ELINK_OFFSET 0x1156 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD10_DLASTSGA_OFFSET 0x1158 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD10_CSR_OFFSET 0x115c /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD10_BITER_ELINK_OFFSET 0x115e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD11_SADDR_OFFSET 0x1160 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD11_SOFF_OFFSET 0x1164 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD11_ATTR_OFFSET 0x1166 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD11_NBYTES_ML_OFFSET 0x1168 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD11_SLAST_OFFSET 0x116c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD11_DADDR_OFFSET 0x1170 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD11_DOFF_OFFSET 0x1174 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD11_CITER_ELINK_OFFSET 0x1176 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD11_DLASTSGA_OFFSET 0x1178 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD11_CSR_OFFSET 0x117c /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD11_BITER_ELINK_OFFSET 0x117e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD12_SADDR_OFFSET 0x1180 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD12_SOFF_OFFSET 0x1184 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD12_ATTR_OFFSET 0x1186 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD12_NBYTES_ML_OFFSET 0x1188 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD12_SLAST_OFFSET 0x118c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD12_DADDR_OFFSET 0x1190 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD12_DOFF_OFFSET 0x1194 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD12_CITER_ELINK_OFFSET 0x1196 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD12_DLASTSGA_OFFSET 0x1198 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD12_CSR_OFFSET 0x119c /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD12_BITER_ELINK_OFFSET 0x119e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD13_SADDR_OFFSET 0x11a0 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD13_SOFF_OFFSET 0x11a4 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD13_ATTR_OFFSET 0x11a6 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD13_NBYTES_ML_OFFSET 0x11a8 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD13_SLAST_OFFSET 0x11ac /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD13_DADDR_OFFSET 0x11b0 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD13_DOFF_OFFSET 0x11b4 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD13_CITER_ELINK_OFFSET 0x11b6 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD13_DLASTSGA_OFFSET 0x11b8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD13_CSR_OFFSET 0x11bc /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD13_BITER_ELINK_OFFSET 0x11be /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD14_SADDR_OFFSET 0x11c0 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD14_SOFF_OFFSET 0x11c4 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD14_ATTR_OFFSET 0x11c6 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD14_NBYTES_ML_OFFSET 0x11c8 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD14_SLAST_OFFSET 0x11cc /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD14_DADDR_OFFSET 0x11d0 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD14_DOFF_OFFSET 0x11d4 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD14_CITER_ELINK_OFFSET 0x11d6 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD14_DLASTSGA_OFFSET 0x11d8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD14_CSR_OFFSET 0x11dc /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD14_BITER_ELINK_OFFSET 0x11de /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_EDMA_TCD15_SADDR_OFFSET 0x11e0 /* TCD Source Address */
|
||||
#define KINETIS_EDMA_TCD15_SOFF_OFFSET 0x11e4 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_EDMA_TCD15_ATTR_OFFSET 0x11e6 /* TCD Transfer Attributes */
|
||||
#define KINETIS_EDMA_TCD15_NBYTES_ML_OFFSET 0x11e8 /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
#define KINETIS_EDMA_TCD15_SLAST_OFFSET 0x11ec /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_EDMA_TCD15_DADDR_OFFSET 0x11f0 /* TCD Destination Address */
|
||||
#define KINETIS_EDMA_TCD15_DOFF_OFFSET 0x11f4 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_EDMA_TCD15_CITER_ELINK_OFFSET 0x11f6 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_EDMA_TCD15_DLASTSGA_OFFSET 0x11f8 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_EDMA_TCD15_CSR_OFFSET 0x11fc /* TCD Control and Status */
|
||||
#define KINETIS_EDMA_TCD15_BITER_ELINK_OFFSET 0x11fe /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
/* eDMA Register Addresses **************************************************/
|
||||
|
||||
#define KINETIS_EDMA_CR (KINETIS_DMAC_BASE + KINETIS_EDMA_CR_OFFSET)
|
||||
#define KINETIS_EDMA_ES (KINETIS_DMAC_BASE + KINETIS_EDMA_ES_OFFSET)
|
||||
#define KINETIS_EDMA_ERQ (KINETIS_DMAC_BASE + KINETIS_EDMA_ERQ_OFFSET)
|
||||
#define KINETIS_EDMA_EEI (KINETIS_DMAC_BASE + KINETIS_EDMA_EEI_OFFSET)
|
||||
#define KINETIS_EDMA_CEEI (KINETIS_DMAC_BASE + KINETIS_EDMA_CEEI_OFFSET)
|
||||
#define KINETIS_EDMA_SEEI (KINETIS_DMAC_BASE + KINETIS_EDMA_SEEI_OFFSET)
|
||||
#define KINETIS_EDMA_CERQ (KINETIS_DMAC_BASE + KINETIS_EDMA_CERQ_OFFSET)
|
||||
#define KINETIS_EDMA_SERQ (KINETIS_DMAC_BASE + KINETIS_EDMA_SERQ_OFFSET)
|
||||
#define KINETIS_EDMA_CDNE (KINETIS_DMAC_BASE + KINETIS_EDMA_CDNE_OFFSET)
|
||||
#define KINETIS_EDMA_SSRT (KINETIS_DMAC_BASE + KINETIS_EDMA_SSRT_OFFSET)
|
||||
#define KINETIS_EDMA_CERR (KINETIS_DMAC_BASE + KINETIS_EDMA_CERR_OFFSET)
|
||||
#define KINETIS_EDMA_CINT (KINETIS_DMAC_BASE + KINETIS_EDMA_CINT_OFFSET)
|
||||
#define KINETIS_EDMA_INT (KINETIS_DMAC_BASE + KINETIS_EDMA_INT_OFFSET)
|
||||
#define KINETIS_EDMA_ERR (KINETIS_DMAC_BASE + KINETIS_EDMA_ERR_OFFSET)
|
||||
#define KINETIS_EDMA_HRS (KINETIS_DMAC_BASE + KINETIS_EDMA_HRS_OFFSET)
|
||||
#define KINETIS_EDMA_EARS (KINETIS_DMAC_BASE + KINETIS_EDMA_EARS_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_DCHPRI(n) (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI_OFFSET(n))
|
||||
|
||||
#define KINETIS_EDMA_DCHPRI0 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI0_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI1 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI1_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI2 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI2_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI3 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI3_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI4 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI4_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI5 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI5_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI6 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI6_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI7 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI7_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI8 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI8_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI9 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI9_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI10 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI10_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI11 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI11_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI12 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI12_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI13 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI13_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI14 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI14_OFFSET)
|
||||
#define KINETIS_EDMA_DCHPRI15 (KINETIS_DMAC_BASE + KINETIS_EDMA_DCHPRI15_OFFSET)
|
||||
|
||||
/* Transfer Control Descriptor (TCD) */
|
||||
|
||||
#define KINETIS_EDMA_TCD_BASE(n) (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD_OFFSET(n))
|
||||
#define KINETIS_EDMA_TCD_SADDR(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD_SOFF(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD_ATTR(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD_NBYTES_ML(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD_SLAST(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD_DADDR(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD_DOFF(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD_CITER_ELINK(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD_DLASTSGA(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD_CSR(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD_BITER_ELINK(n) (KINETIS_EDMA_TCD_BASE(n) + KINETIS_EDMA_TCD_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD0_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD0_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD0_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD0_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD0_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD0_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD0_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD0_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD0_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD0_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD0_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD0_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD1_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD1_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD1_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD1_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD1_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD1_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD1_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD1_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD1_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD1_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD1_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD1_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD2_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD2_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD2_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD2_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD2_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD2_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD2_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD2_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD2_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD2_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD2_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD2_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD3_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD3_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD3_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD3_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD3_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD3_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD3_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD3_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD3_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD3_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD3_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD3_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD4_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD4_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD4_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD4_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD4_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD4_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD4_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD4_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD4_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD4_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD4_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD4_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD5_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD5_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD5_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD5_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD5_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD5_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD5_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD5_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD5_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD5_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD5_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD5_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD6_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD6_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD6_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD6_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD6_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD6_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD6_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD6_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD6_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD6_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD6_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD6_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD7_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD7_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD7_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD7_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD7_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD7_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD7_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD7_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD7_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD7_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD7_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD7_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD8_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD8_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD8_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD8_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD8_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD8_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD8_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD8_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD8_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD8_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD8_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD8_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD9_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD9_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD9_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD9_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD9_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD9_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD9_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD9_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD9_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD9_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD9_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD9_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD10_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD10_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD10_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD10_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD10_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD10_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD10_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD10_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD10_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD10_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD10_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD10_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD11_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD11_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD11_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD11_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD11_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD11_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD11_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD11_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD11_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD11_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD11_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD11_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD12_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD12_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD12_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD12_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD12_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD12_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD12_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD12_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD12_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD12_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD12_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD12_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD13_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD13_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD13_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD13_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD13_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD13_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD13_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD13_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD13_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD13_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD13_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD13_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD14_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD14_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD14_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD14_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD14_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD14_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD14_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD14_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD14_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD14_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD14_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD14_BITER_ELINK_OFFSET)
|
||||
|
||||
#define KINETIS_EDMA_TCD15_SADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_SADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD15_SOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_SOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD15_ATTR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_ATTR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD15_NBYTES_ML (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_NBYTES_ML_OFFSET)
|
||||
#define KINETIS_EDMA_TCD15_SLAST (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_SLAST_OFFSET)
|
||||
#define KINETIS_EDMA_TCD15_DADDR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_DADDR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD15_DOFF (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_DOFF_OFFSET)
|
||||
#define KINETIS_EDMA_TCD15_CITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_CITER_ELINK_OFFSET)
|
||||
#define KINETIS_EDMA_TCD15_DLASTSGA (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_DLASTSGA_OFFSET)
|
||||
#define KINETIS_EDMA_TCD15_CSR (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_CSR_OFFSET)
|
||||
#define KINETIS_EDMA_TCD15_BITER_ELINK (KINETIS_DMAC_BASE + KINETIS_EDMA_TCD15_BITER_ELINK_OFFSET)
|
||||
|
||||
/* eDMA Bit-Field Definitions ***********************************************/
|
||||
|
||||
/* Control */
|
||||
|
||||
/* Bit 0: Reserved */
|
||||
#define EDMA_CR_EDBG (1 << 1) /* Bit 1: Enable Debug */
|
||||
#define EDMA_CR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration */
|
||||
#define EDMA_CR_ERGA (1 << 3) /* Bit 3: Enable Round Robin Group Arbitration */
|
||||
#define EDMA_CR_HOE (1 << 4) /* Bit 4: Halt On Error */
|
||||
#define EDMA_CR_HALT (1 << 5) /* Bit 5: Halt DMA Operations */
|
||||
#define EDMA_CR_CLM (1 << 6) /* Bit 6: Continuous Link Mode */
|
||||
#define EDMA_CR_EMLM (1 << 7) /* Bit 7: Enable Minor Loop Mapping */
|
||||
/* Bit 8-15: Reserved */
|
||||
#define EDMA_CR_ECX (1 << 16) /* Bit 16: Error Cancel Transfer */
|
||||
#define EDMA_CR_CX (1 << 17) /* Bit 17: Cancel Transfer */
|
||||
/* Bits 18-23: Reserved */
|
||||
/* Bits 24-30: eDMA version number (reserved) */
|
||||
#define EDMA_CR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status */
|
||||
|
||||
/* Error Status */
|
||||
|
||||
#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error */
|
||||
#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error */
|
||||
#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error */
|
||||
#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error */
|
||||
#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error */
|
||||
#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error */
|
||||
#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error */
|
||||
#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error */
|
||||
#define EDMA_ES_ERRCHN_SHIFT (8) /* Bits 8-11: Error Channel Number or
|
||||
* Canceled Channel Number */
|
||||
#define EDMA_ES_ERRCHN_MASK (15 << EDMA_ES_ERRCHN_SHIFT)
|
||||
/* Bits 23-13: Reserved */
|
||||
#define EDMA_ES_CPE (1 << 14) /* Bit 14: Channel Priority Error */
|
||||
/* Bit 15: Reserved */
|
||||
#define EDMA_ES_ECX (1 << 16) /* Bit 16: Transfer Canceled */
|
||||
/* Bits 17-30: Reserved */
|
||||
#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status bits */
|
||||
|
||||
/* Enable Request */
|
||||
|
||||
#define EDMA_ERQ(n) ((uint32_t)1 << (n)) /* Bit n: Enable DMA request n */
|
||||
|
||||
/* Enable Error Interrupt */
|
||||
|
||||
#define EDMA_EEI(n) ((uint32_t)1 << (n)) /* Bit n: Enable error interrupt n */
|
||||
|
||||
/* Clear Enable Error Interrupt */
|
||||
|
||||
#define EDMA_CEEI_SHIFT (0) /* Bits 0-3: Clear Enable Error Interrupt */
|
||||
#define EDMA_CEEI_MASK (15 << EDMA_CEEI_SHIFT)
|
||||
# define EDMA_CEEI(n) ((uint32_t)(n) << EDMA_CEEI_SHIFT)
|
||||
/* Bit 54-: Reserved */
|
||||
#define EDMA_CEEI_CAEE (1 << 6) /* Bit 6: Clear All Enable Error Interrupts */
|
||||
#define EDMA_CEEI_NOP (1 << 7) /* Bit 7: No Op enable */
|
||||
|
||||
/* Set Enable Error Interrupt */
|
||||
|
||||
#define EDMA_SEEI_SHIFT (0) /* Bits 0-3: Set Enable Error Interrupt */
|
||||
#define EDMA_SEEI_MASK (15 << EDMA_SEEI_SHIFT)
|
||||
# define EDMA_SEEI(n) ((uint32_t)(n) << EDMA_SEEI_SHIFT)
|
||||
/* Bit 54-: Reserved */
|
||||
#define EDMA_SEEI_SAEE (1 << 6) /* Bit 6: Set All Enable Error Interrupts */
|
||||
#define EDMA_SEEI_NOP (1 << 7) /* Bit 7: No Op enable */
|
||||
|
||||
/* Clear Enable Request */
|
||||
|
||||
#define EDMA_CERQ_SHIFT (0) /* Bits 0-3: Clear Enable Request */
|
||||
#define EDMA_CERQ_MASK (15 << EDMA_CERQ_SHIFT)
|
||||
# define EDMA_CERQ(n) ((uint32_t)(n) << EDMA_CERQ_SHIFT)
|
||||
/* Bit 4-5: Reserved */
|
||||
#define EDMA_CERQ_CAER (1 << 6) /* Bit 6: Clear All Enable Requests */
|
||||
#define EDMA_CERQ_NOP (1 << 7) /* Bit 7: No Op enable */
|
||||
|
||||
/* Set Enable Request */
|
||||
|
||||
#define EDMA_SERQ_SHIFT (0) /* Bits 0-3: Set Enable Request */
|
||||
#define EDMA_SERQ_MASK (15 << EDMA_SERQ_SHIFT)
|
||||
# define EDMA_SERQ(n) ((uint32_t)(n) << EDMA_SERQ_SHIFT)
|
||||
/* Bit 4-5: Reserved */
|
||||
#define EDMA_SERQ_SAER (1 << 6) /* Bit 6: Set All Enable Requests */
|
||||
#define EDMA_SERQ_NOP (1 << 7) /* Bit 7: No Op enable */
|
||||
|
||||
/* Clear DONE Status Bit */
|
||||
|
||||
#define EDMA_CDNE_SHIFT (0) /* Bits 0-3: Clear DONE Bit */
|
||||
#define EDMA_CDNE_MASK (15 << EDMA_CDNE_SHIFT)
|
||||
# define EDMA_CDNE(n) ((uint32_t)(n) << EDMA_CDNE_SHIFT)
|
||||
/* Bit 4-5: Reserved */
|
||||
#define EDMA_CDNE_CADN (1 << 6) /* Bit 6: Clears All DONE Bits */
|
||||
#define EDMA_CDNE_NOP (1 << 7) /* Bit 7: No Op enable */
|
||||
|
||||
/* Set START Bit */
|
||||
|
||||
#define EDMA_SSRT_SHIFT (0) /* Bits 0-3: Set START Bit */
|
||||
#define EDMA_SSRT_MASK (15 << EDMA_SSRT_SHIFT)
|
||||
# define EDMA_SSRT(n) ((uint32_t)(n) << EDMA_SSRT_SHIFT)
|
||||
/* Bit 4-5: Reserved */
|
||||
#define EDMA_SSRT_SAST (1 << 6) /* Bit 6: Set All START Bits (activates all channels) */
|
||||
#define EDMA_SSRT_NOP (1 << 7) /* Bit 7: No Op enable */
|
||||
|
||||
/* Clear Error */
|
||||
|
||||
#define EDMA_CERR_SHIFT (0) /* Bits 0-3: Clear Error Indicator */
|
||||
#define EDMA_CERR_MASK (15 << EDMA_CERR_SHIFT)
|
||||
# define EDMA_CERR(n) ((uint32_t)(n) << EDMA_CERR_SHIFT)
|
||||
/* Bit 4-5: Reserved */
|
||||
#define EDMA_CERR_CAEI (1 << 6) /* Bit 6: Clear All Error Indicators */
|
||||
#define EDMA_CERR_NOP (1 << 7) /* Bit 7: No Op enable */
|
||||
|
||||
/* Clear Interrupt Request */
|
||||
|
||||
#define EDMA_CINT_SHIFT (0) /* Bits 0-3: Clear Interrupt Request */
|
||||
#define EDMA_CINT_MASK (15 << EDMA_CINT_SHIFT)
|
||||
# define EDMA_CINT(n) ((uint32_t)(n) << EDMA_CINT_SHIFT)
|
||||
/* Bit 4-5: Reserved */
|
||||
#define EDMA_CINT_CAIR (1 << 6) /* Bit 6: Clear All Interrupt Requests */
|
||||
#define EDMA_CINT_NOP (1 << 7) /* Bit 7: No Op enable */
|
||||
|
||||
/* Interrupt Request */
|
||||
|
||||
#define EDMA_INT(n) ((uint32_t)1 << (n)) /* Bit n: Interrupt Request n */
|
||||
|
||||
/* Error */
|
||||
|
||||
#define EDMA_ERR(n) ((uint32_t)1 << (n)) /* Bit n: Error In Channel n */
|
||||
|
||||
/* Hardware Request Status */
|
||||
|
||||
#define EDMA_HRS(n) ((uint32_t)1 << (n)) /* Bit n: Hardware Request Status
|
||||
* Channel n */
|
||||
|
||||
/* Enable Asynchronous Request in Stop */
|
||||
|
||||
#define EDMA_EARS(n) ((uint32_t)1 << (n)) /* Bit n: Enable asynchronous DMA
|
||||
* request in stop mode for channel n */
|
||||
|
||||
/* Channel n Priority */
|
||||
|
||||
#define EDMA_DCHPRI_CHPRI_SHIFT (0) /* Bits 0-3: Channel n Arbitration Priority */
|
||||
#define EDMA_DCHPRI_CHPRI_MASK (15 << EDMA_DCHPRI_CHPRI_SHIFT)
|
||||
# define EDMA_DCHPRI_CHPRI(n) ((uint32_t)(n) << EDMA_DCHPRI_CHPRI_SHIFT)
|
||||
/* Bit 4-5: Reserved */
|
||||
#define EDMA_DCHPRI_DPA (1 << 6) /* Bit 6: Disable Preempt Ability */
|
||||
#define EDMA_DCHPRI_ECP (1 << 7) /* Bit 7: Enable Channel Preemption */
|
||||
|
||||
/* TCD Source Address (32-bit address) */
|
||||
|
||||
/* TCD Signed Source Address Offset (16-bit offset) */
|
||||
|
||||
/* TCD Transfer Attributes */
|
||||
|
||||
#define TCD_ATTR_SIZE_8BIT (0) /* 8-bit */
|
||||
#define TCD_ATTR_SIZE_16BIT (1) /* 16-bit */
|
||||
#define TCD_ATTR_SIZE_32BIT (2) /* 32-bit */
|
||||
#define TCD_ATTR_SIZE_64BIT (3) /* 64-bit */
|
||||
#define TCD_ATTR_SIZE_256BIT (5) /* 32-byte burst (4 beats of 64 bits) */
|
||||
|
||||
#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination data transfer size */
|
||||
#define EDMA_TCD_ATTR_DSIZE_MASK (7 << EDMA_TCD_ATTR_DSIZE_SHIFT)
|
||||
# define EDMA_TCD_ATTR_DSIZE(n) ((uint32_t)(n) << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 8-bit */
|
||||
# define EDMA_TCD_ATTR_DSIZE_8BIT (TCD_ATTR_SIZE_8BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 8-bit */
|
||||
# define EDMA_TCD_ATTR_DSIZE_16BIT (TCD_ATTR_SIZE_16BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 16-bit */
|
||||
# define EDMA_TCD_ATTR_DSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-bit */
|
||||
# define EDMA_TCD_ATTR_DSIZE_64BIT (TCD_ATTR_SIZE_64BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 64-bit */
|
||||
# define EDMA_TCD_ATTR_DSIZE_256BIT (TCD_ATTR_SIZE_256BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-byte burst */
|
||||
|
||||
#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo */
|
||||
#define EDMA_TCD_ATTR_DMOD_MASK (31 << EDMA_TCD_ATTR_DMOD_SHIFT)
|
||||
# define EDMA_TCD_ATTR_DMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_DMOD_SHIFT)
|
||||
#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source data transfer size */
|
||||
#define EDMA_TCD_ATTR_SSIZE_MASK (7 << EDMA_TCD_ATTR_SSIZE_SHIFT)
|
||||
# define EDMA_TCD_ATTR_SSIZE(n) ((uint32_t)(n) << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
|
||||
# define EDMA_TCD_ATTR_SSIZE_8BIT (TCD_ATTR_SIZE_8BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
|
||||
# define EDMA_TCD_ATTR_SSIZE_16BIT (TCD_ATTR_SIZE_16BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
|
||||
# define EDMA_TCD_ATTR_SSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
|
||||
# define EDMA_TCD_ATTR_SSIZE_64BIT (TCD_ATTR_SIZE_64BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */
|
||||
# define EDMA_TCD_ATTR_SSIZE_256BIT (TCD_ATTR_SIZE_256BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte burst */
|
||||
|
||||
#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo */
|
||||
#define EDMA_TCD_ATTR_SMOD_MASK (31 << EDMA_TCD_ATTR_SMOD_SHIFT)
|
||||
# define EDMA_TCD_ATTR_SMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_SMOD_SHIFT)
|
||||
|
||||
/* TCD Signed Minor Loop Offset / Byte Count */
|
||||
|
||||
/* Minor Byte Count (Minor Loop Mapping Disabled -- 32-bit byte count) */
|
||||
|
||||
/* TCD Signed Minor Loop Offset / Byte Count */
|
||||
|
||||
/* Minor Byte Count (Minor Loop Mapping Enabled, offset disabled) */
|
||||
|
||||
#define EDMA_TCD_NBYTES_ML_NBYTES_SHIFT (0) /* Bits 0-29: Minor Byte Transfer Count */
|
||||
#define EDMA_TCD_NBYTES_ML_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_ML_NBYTES_SHIFT)
|
||||
# define EDMA_TCD_NBYTES_ML_NBYTES(n) ((uint32_t)(n) << EDMA_TCD_NBYTES_ML_NBYTES_SHIFT)
|
||||
#define EDMA_TCD_NBYTES_ML_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset enable */
|
||||
#define EDMA_TCD_NBYTES_ML_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable */
|
||||
|
||||
/* TCD Signed Minor Loop Offset / Byte Count */
|
||||
|
||||
/* Minor Byte Count (Minor Loop Mapping Enabled, offset enabled) */
|
||||
|
||||
#define EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT (0) /* Bits 0-9: Minor Byte Transfer Count */
|
||||
#define EDMA_TCD_NBYTES_MLOFF_NBYTES_MASK (0x3ff << EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT)
|
||||
# define EDMA_TCD_NBYTES_MLOFF_NBYTES(n) ((uint32_t)(n) << EDMA_TCD_NBYTES_MLOFF_NBYTES_SHIFT)
|
||||
#define EDMA_TCD_NBYTES_MLOFF_MLOFF_SHIFT (10) /* Bits 10-29: Minor Byte Transfer Count */
|
||||
#define EDMA_TCD_NBYTES_MLOFF_MLOFF_MASK (0xfffff << EDMA_TCD_NBYTES_MLOFF_MLOFF_SHIFT)
|
||||
# define EDMA_TCD_NBYTES_MLOFF_MLOFF(n) ((uint32_t)(n) << EDMA_TCD_NBYTES_MLOFF_MLOFF_SHIFT)
|
||||
#define EDMA_TCD_NBYTES_MLOFF_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset enable */
|
||||
#define EDMA_TCD_NBYTES_MLOFF_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable */
|
||||
|
||||
/* TCD Last Source Address Adjustment (32-bit address adjustment) */
|
||||
|
||||
/* TCD Destination Address (32-bit address) */
|
||||
|
||||
/* TCD Signed Destination Address Offset (16-bit signed address offset) */
|
||||
|
||||
/* TCD Current Minor Loop Link, Major Loop Count (Channel linking disabled) */
|
||||
|
||||
#define EDMA_TCD_CITER_CITER_SHIFT (0) /* Bit 0-14: Starting Major Iteration Count */
|
||||
#define EDMA_TCD_CITER_CITER_MASK (0x7fff << EDMA_TCD_CITER_CITER_SHIFT)
|
||||
# define EDMA_TCD_CITER_CITER(n) ((uint32_t)(n) << EDMA_TCD_CITER_CITER_SHIFT)
|
||||
#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking
|
||||
* on minor-loop complete */
|
||||
|
||||
/* TCD Current Minor Loop Link, Major Loop Count
|
||||
* (Channel linking enabled)
|
||||
*/
|
||||
|
||||
#define EDMA_TCD_CITER_ELINK_CITER_SHIFT (0) /* Bit 0-8: Current major iteration count */
|
||||
#define EDMA_TCD_CITER_ELINK_CITER_MASK (0x1ff << EDMA_TCD_CITER_ELINK_CITER_SHIFT)
|
||||
# define EDMA_TCD_CITER_ELINK_CITER(n) ((uint32_t)(n) << EDMA_TCD_CITER_ELINK_CITER_SHIFT)
|
||||
#define EDMA_TCD_CITER_ELINK_LINKCH_SHIFT (9) /* Bit 9-12: Minor Loop Link Channel Number */
|
||||
#define EDMA_TCD_CITER_ELINK_LINKCH_MASK (15 << EDMA_TCD_CITER_ELINK_LINKCH_SHIFT)
|
||||
# define EDMA_TCD_CITER_ELINK_LINKCH(n) ((uint32_t)(n) << EDMA_TCD_CITER_ELINK_LINKCH_SHIFT)
|
||||
/* Bit 13-14: Reserved */
|
||||
#define EDMA_TCD_CITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking
|
||||
* on minor-loop complete */
|
||||
|
||||
/* TCD Last Destination Address Adjustment/Scatter Gather Address
|
||||
* (32-bit address)
|
||||
*/
|
||||
|
||||
/* TCD Control and Status */
|
||||
|
||||
#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start */
|
||||
#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable an interrupt when major
|
||||
* iteration count completes */
|
||||
#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable an interrupt when major
|
||||
* counter is half complete */
|
||||
#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request */
|
||||
#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing */
|
||||
#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable channel-to-channel linking
|
||||
* on major loop complete */
|
||||
#define EDMA_TCD_CSR_ACTIVE (1 << 6) /* Bit 6: Channel Active */
|
||||
#define EDMA_TCD_CSR_DONE (1 << 7) /* Bit 7: Channel Done */
|
||||
#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-11: Major Loop Link Channel Number */
|
||||
#define EDMA_TCD_CSR_MAJORLINKCH_MASK (15 << EDMA_TCD_CSR_MAJORLINKCH_SHIFT)
|
||||
# define EDMA_TCD_CSR_MAJORLINKCH(n) ((uint32_t)(n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT)
|
||||
/* Bit 112-3: Reserved */
|
||||
#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control */
|
||||
#define EDMA_TCD_CSR_BWC_MASK (3 << EDMA_TCD_CSR_BWC_SHIFT)
|
||||
# define EDMA_TCD_CSR_BWC_NONE (0 << EDMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */
|
||||
# define EDMA_TCD_CSR_BWC_4CYCLES (2 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 4
|
||||
* cycles after each R/W */
|
||||
# define EDMA_TCD_CSR_BWC_8CYCLES (3 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8
|
||||
* cycles after each R/W */
|
||||
|
||||
/* TCD Beginning Minor Loop Link, Major Loop Count
|
||||
* (Channel linking disabled)
|
||||
*/
|
||||
|
||||
#define EDMA_TCD_BITER_BITER_SHIFT (0) /* Bit 0-14: Starting Major Iteration Count */
|
||||
#define EDMA_TCD_BITER_BITER_MASK (0x7fff << EDMA_TCD_BITER_BITER_SHIFT)
|
||||
# define EDMA_TCD_BITER_BITER(n) ((uint32_t)(n) << EDMA_TCD_BITER_BITER_SHIFT)
|
||||
#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking
|
||||
* on minor-loop complete */
|
||||
|
||||
/* TCD Beginning Minor Loop Link, Major Loop Count
|
||||
* (Channel linking enabled)
|
||||
*/
|
||||
|
||||
#define EDMA_TCD_BITER_ELINK_BITER_SHIFT (0) /* Bit 0-8: Current major iteration count */
|
||||
#define EDMA_TCD_BITER_ELINK_BITER_MASK (0x1ff << EDMA_TCD_BITER_ELINK_BITER_SHIFT)
|
||||
# define EDMA_TCD_BITER_ELINK_BITER(n) ((uint32_t)(n) << EDMA_TCD_BITER_ELINK_BITER_SHIFT)
|
||||
#define EDMA_TCD_BITER_ELINK_LINKCH_SHIFT (9) /* Bit 9-12: Link Channel Number */
|
||||
#define EDMA_TCD_BITER_ELINK_LINKCH_MASK (15 << EDMA_TCD_BITER_ELINK_LINKCH_SHIFT)
|
||||
# define EDMA_TCD_BITER_ELINK_LINKCH(n) ((uint32_t)(n) << EDMA_TCD_BITER_ELINK_LINKCH_SHIFT)
|
||||
/* Bit 13-4: Reserved */
|
||||
#define EDMA_TCD_BITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking
|
||||
* on minor-loop complete */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/* In-memory representation of the 32-byte Transfer Control Descriptor
|
||||
* (TCD)
|
||||
*/
|
||||
|
||||
struct kinetis_edmatcd_s
|
||||
{
|
||||
sq_entry_t node;
|
||||
uint8_t flags; /* See EDMA_CONFIG_* definitions */
|
||||
uint32_t saddr; /* Offset: 0x0000 TCD Source Address */
|
||||
uint16_t soff; /* Offset: 0x0004 TCD Signed Source Address Offset */
|
||||
uint16_t attr; /* Offset: 0x0006 TCD Transfer Attributes */
|
||||
uint32_t nbytes; /* Offset: 0x0008 TCD Signed Minor Loop Offset / Byte Count */
|
||||
uint32_t slast; /* Offset: 0x000c TCD Last Source Address Adjustment */
|
||||
uint32_t daddr; /* Offset: 0x0010 TCD Destination Address */
|
||||
uint16_t doff; /* Offset: 0x0014 TCD Signed Destination Address Offset */
|
||||
uint16_t citer; /* Offset: 0x0016 TCD Current Minor Loop Link, Major Loop Count */
|
||||
uint32_t dlastsga; /* Offset: 0x0018 TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
uint16_t csr; /* Offset: 0x001c TCD Control and Status */
|
||||
uint16_t biter; /* Offset: 0x001e TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
};
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_EDMA_H */
|
||||
@ -1,455 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/kinetis/kinetis_dma.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "arm_arch.h"
|
||||
#include "arm_internal.h"
|
||||
|
||||
#include "kinetis_config.h"
|
||||
#include "chip.h"
|
||||
#include "kinetis_dma.h"
|
||||
#include "hardware/kinetis_dmamux.h"
|
||||
#include "hardware/kinetis_sim.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef DMA_CHN_PER_GROUP
|
||||
# define DMA_CHN_PER_GROUP KINETIS_NDMACH /* Number of channels per group */
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
struct kinetis_dma_ch
|
||||
{
|
||||
bool used;
|
||||
uint8_t ind;
|
||||
uint8_t irq;
|
||||
enum kinetis_dma_direction_e dir;
|
||||
enum kinetis_dma_data_sz_e data_sz;
|
||||
dma_callback_t callback;
|
||||
void *arg;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static struct kinetis_dma_ch g_channels[KINETIS_NDMACH];
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
static int kinetis_dmainterrupt_int(int irq, void *context,
|
||||
struct kinetis_dma_ch *ch)
|
||||
{
|
||||
/* Clear bit in the interrupt */
|
||||
|
||||
putreg8(ch->ind, KINETIS_DMA_CINT);
|
||||
|
||||
/* Invoke the callback */
|
||||
|
||||
if (ch->callback)
|
||||
{
|
||||
ch->callback((DMA_HANDLE)&ch, ch->arg, 0);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
static int kinetis_dmainterrupt(int irq, void *context, void *arg)
|
||||
{
|
||||
uint8_t irq_int = *(uint8_t *)arg;
|
||||
uint32_t regval;
|
||||
regval = getreg32(KINETIS_DMA_INT);
|
||||
|
||||
/* Channel irq_int and irq_int + DMA_CHN_PER_GROUP use the same arg. Check
|
||||
* which one requested an interrupt
|
||||
*/
|
||||
|
||||
if ((regval & (1 << irq_int)) != 0)
|
||||
{
|
||||
kinetis_dmainterrupt_int(irq, context, &g_channels[irq_int]);
|
||||
}
|
||||
|
||||
if ((regval & (1 << (irq_int + DMA_CHN_PER_GROUP))) != 0)
|
||||
{
|
||||
kinetis_dmainterrupt_int(irq, context,
|
||||
&g_channels[irq_int + DMA_CHN_PER_GROUP]);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
size_t kinetis_dmaresidual(DMA_HANDLE handle)
|
||||
{
|
||||
struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle;
|
||||
|
||||
/* Channel Linking Disabled */
|
||||
|
||||
return ((getreg16(KINETIS_DMA_TCD_CITER(ch->ind)) >>
|
||||
DMA_TCD_CITER2_SHIFT) & DMA_TCD_CITER2_MASK);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmainitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the DMA subsystem.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void weak_function arm_dma_initialize(void)
|
||||
{
|
||||
int i;
|
||||
uint32_t regval;
|
||||
int ret;
|
||||
|
||||
for (i = KINETIS_NDMACH - 1; i >= 0; i--)
|
||||
{
|
||||
g_channels[i].ind = i;
|
||||
g_channels[i].used = false;
|
||||
g_channels[i].irq = KINETIS_IRQ_FIRST + (i % DMA_CHN_PER_GROUP);
|
||||
|
||||
if (i < DMA_CHN_PER_GROUP)
|
||||
{
|
||||
/* Attach DMA interrupt */
|
||||
|
||||
ret = irq_attach(g_channels[i].irq, kinetis_dmainterrupt,
|
||||
(void *)&g_channels[i].ind);
|
||||
|
||||
if (ret == OK)
|
||||
{
|
||||
/* Enable the IRQ at the NVIC (still disabled at the DMA
|
||||
* controller)
|
||||
*/
|
||||
|
||||
up_enable_irq(g_channels[i].irq);
|
||||
}
|
||||
else
|
||||
{
|
||||
g_channels[i].used = true;
|
||||
g_channels[i + DMA_CHN_PER_GROUP].used = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable clocking for DMA */
|
||||
|
||||
regval = getreg32(KINETIS_SIM_SCGC7);
|
||||
regval |= SIM_SCGC7_DMA;
|
||||
putreg32(regval, KINETIS_SIM_SCGC7);
|
||||
|
||||
/* Configure DMA for round robin arbitration */
|
||||
|
||||
regval = 0;
|
||||
regval |= DMA_CR_ERCA | DMA_CR_ERGA;
|
||||
putreg32(regval, KINETIS_DMA_CR);
|
||||
|
||||
/* Enable clocking for the DMA mux */
|
||||
|
||||
regval = getreg32(KINETIS_SIM_SCGC6);
|
||||
regval |= SIM_SCGC6_DMAMUX0;
|
||||
putreg32(regval, KINETIS_SIM_SCGC6);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmachannel
|
||||
*
|
||||
* Description:
|
||||
* Allocate a DMA channel. This function sets aside a DMA channel and
|
||||
* gives the caller exclusive access to the DMA channel.
|
||||
*
|
||||
* Returned Value:
|
||||
* On success, this function returns a non-NULL, void* DMA channel handle.
|
||||
* NULL is returned on any failure. This function can fail only if no DMA
|
||||
* channel is available.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
DMA_HANDLE kinetis_dmachannel(uint8_t src, uint32_t per_addr,
|
||||
enum kinetis_dma_data_sz_e per_data_sz,
|
||||
enum kinetis_dma_direction_e dir)
|
||||
{
|
||||
int i;
|
||||
int ch_ind;
|
||||
uint8_t regval8;
|
||||
uint16_t regval16;
|
||||
irqstate_t flags;
|
||||
struct kinetis_dma_ch *ch;
|
||||
|
||||
/* Find available channel */
|
||||
|
||||
ch_ind = -1;
|
||||
flags = enter_critical_section();
|
||||
for (i = 0; i < KINETIS_NDMACH; i++)
|
||||
{
|
||||
if (!g_channels[i].used)
|
||||
{
|
||||
ch_ind = i;
|
||||
g_channels[ch_ind].used = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
if (ch_ind == -1)
|
||||
{
|
||||
/* No available channel */
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
ch = &g_channels[ch_ind];
|
||||
|
||||
/* Copy arguments */
|
||||
|
||||
ch->dir = dir;
|
||||
ch->data_sz = per_data_sz;
|
||||
|
||||
/* DMAMUX Set DMA channel source and enable it */
|
||||
|
||||
regval8 = ((((uint8_t)src) << DMAMUX_CHCFG_SOURCE_SHIFT) &
|
||||
DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_ENBL;
|
||||
putreg8(regval8, KINETIS_DMAMUX_CHCFG(ch_ind));
|
||||
|
||||
/* DMA Set peripheral address in TCD */
|
||||
|
||||
if (ch->dir == KINETIS_DMA_DIRECTION_PERIPHERAL_TO_MEMORY)
|
||||
{
|
||||
putreg32(per_addr, KINETIS_DMA_TCD_SADDR(ch->ind));
|
||||
putreg16(0, KINETIS_DMA_TCD_SOFF(ch->ind));
|
||||
putreg32(0, KINETIS_DMA_TCD_SLAST(ch->ind));
|
||||
}
|
||||
else if (ch->dir == KINETIS_DMA_DIRECTION_MEMORY_TO_PERIPHERAL)
|
||||
{
|
||||
putreg32(per_addr, KINETIS_DMA_TCD_DADDR(ch->ind));
|
||||
putreg16(0, KINETIS_DMA_TCD_DOFF(ch->ind));
|
||||
putreg32(0, KINETIS_DMA_TCD_DLASTSGA(ch->ind));
|
||||
}
|
||||
else
|
||||
{
|
||||
ch->used = false;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Set data sizes */
|
||||
|
||||
regval16 = (DMA_TCD_ATTR_SSIZE_MASK & ((uint16_t)per_data_sz) <<
|
||||
DMA_TCD_ATTR_SSIZE_SHIFT);
|
||||
regval16 |= (DMA_TCD_ATTR_DSIZE_MASK & ((uint16_t)per_data_sz) <<
|
||||
DMA_TCD_ATTR_DSIZE_SHIFT);
|
||||
putreg16(regval16, KINETIS_DMA_TCD_ATTR(ch->ind));
|
||||
|
||||
/* Set minor loop count */
|
||||
|
||||
putreg32(1 << (uint8_t)per_data_sz, KINETIS_DMA_TCD_NBYTES(ch->ind));
|
||||
return (DMA_HANDLE)ch;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmafree
|
||||
*
|
||||
* Description:
|
||||
* Release a DMA channel. NOTE: The 'handle' used in this argument must
|
||||
* NEVER be used again until kinetis_dmachannel() is called again to
|
||||
* re-gain a valid handle.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kinetis_dmafree(DMA_HANDLE handle)
|
||||
{
|
||||
struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle;
|
||||
irqstate_t flags;
|
||||
|
||||
DEBUGASSERT(handle != NULL);
|
||||
|
||||
/* Disable DMA channel in the dmamux */
|
||||
|
||||
putreg8(0, KINETIS_DMAMUX_CHCFG(ch->ind));
|
||||
|
||||
flags = enter_critical_section();
|
||||
ch->used = false;
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmasetup
|
||||
*
|
||||
* Description:
|
||||
* Configure DMA for one transfer.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int kinetis_dmasetup(DMA_HANDLE handle, uint32_t mem_addr, size_t ntransfers,
|
||||
uint16_t control)
|
||||
{
|
||||
struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle;
|
||||
uint16_t regval = 0;
|
||||
uint32_t nbytes;
|
||||
|
||||
if (ntransfers > (DMA_TCD_CITER2_MASK >> DMA_TCD_CITER2_SHIFT))
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
DEBUGASSERT(handle != NULL);
|
||||
|
||||
nbytes = (uint32_t)ntransfers * (uint32_t)(1 << (uint8_t)ch->data_sz);
|
||||
|
||||
if (ch->dir == KINETIS_DMA_DIRECTION_PERIPHERAL_TO_MEMORY)
|
||||
{
|
||||
putreg32(mem_addr, KINETIS_DMA_TCD_DADDR(ch->ind));
|
||||
putreg16(1 << (uint8_t)ch->data_sz, KINETIS_DMA_TCD_DOFF(ch->ind));
|
||||
putreg32(-nbytes, KINETIS_DMA_TCD_DLASTSGA(ch->ind));
|
||||
}
|
||||
else if (ch->dir == KINETIS_DMA_DIRECTION_MEMORY_TO_PERIPHERAL)
|
||||
{
|
||||
putreg32(mem_addr, KINETIS_DMA_TCD_SADDR(ch->ind));
|
||||
putreg16(1 << (uint8_t)ch->data_sz, KINETIS_DMA_TCD_SOFF(ch->ind));
|
||||
putreg32(-nbytes, KINETIS_DMA_TCD_SLAST(ch->ind));
|
||||
}
|
||||
else
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Set up channel with control word */
|
||||
|
||||
regval = (control & DMA_TCD_CSR_MAJORELINK) ? ch->ind : 0;
|
||||
regval <<= DMA_TCD_CSR_MAJORLINKCH_SHIFT;
|
||||
regval &= DMA_TCD_CSR_MAJORLINKCH_MASK;
|
||||
regval |= (DMA_TCD_CSR_INTMAJOR |
|
||||
(control & (DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_MAJORELINK)));
|
||||
putreg16(regval, KINETIS_DMA_TCD_CSR(ch->ind));
|
||||
|
||||
/* Set major loop count */
|
||||
|
||||
putreg16(ntransfers, KINETIS_DMA_TCD_BITER(ch->ind));
|
||||
putreg16(ntransfers, KINETIS_DMA_TCD_CITER(ch->ind));
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmastart
|
||||
*
|
||||
* Description:
|
||||
* Start the DMA transfer
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int kinetis_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
|
||||
{
|
||||
struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle;
|
||||
|
||||
DEBUGASSERT(handle != NULL);
|
||||
|
||||
ch->callback = callback;
|
||||
ch->arg = arg;
|
||||
|
||||
/* Enable request register for this channel */
|
||||
|
||||
putreg8(ch->ind, KINETIS_DMA_SERQ);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmastop
|
||||
*
|
||||
* Description:
|
||||
* Cancel the DMA. After kinetis_dmastop() is called, the DMA channel is
|
||||
* reset and kinetis_dmasetup() must be called before kinetis_dmastart()
|
||||
* can be called again
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kinetis_dmastop(DMA_HANDLE handle)
|
||||
{
|
||||
struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle;
|
||||
|
||||
DEBUGASSERT(handle != NULL);
|
||||
|
||||
putreg8(ch->ind, KINETIS_DMA_CERQ);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmasample
|
||||
*
|
||||
* Description:
|
||||
* Sample DMA register contents
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
void kinetis_dmasample(DMA_HANDLE handle, struct kinetis_dmaregs_s *regs)
|
||||
{
|
||||
DEBUGASSERT(handle != NULL);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmadump
|
||||
*
|
||||
* Description:
|
||||
* Dump previously sampled DMA register contents
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
void kinetis_dmadump(DMA_HANDLE handle, const struct kinetis_dmaregs_s *regs,
|
||||
const char *msg)
|
||||
{
|
||||
DEBUGASSERT(handle != NULL);
|
||||
}
|
||||
#endif
|
||||
@ -1,250 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/kinetis/kinetis_dma.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KINETEIS_KINETEIS_DMA_H
|
||||
#define __ARCH_ARM_SRC_KINETEIS_KINETEIS_DMA_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "hardware/kinetis_dma.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Declarations
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
typedef FAR void *DMA_HANDLE;
|
||||
typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
|
||||
|
||||
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is
|
||||
* selected.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
struct kinetis_dmaglobalregs_s
|
||||
{
|
||||
#warning "Missing logic"
|
||||
/* Global Registers */
|
||||
};
|
||||
|
||||
struct kinetis_dmachanregs_s
|
||||
{
|
||||
#warning "Missing logic"
|
||||
/* Channel Registers */
|
||||
};
|
||||
|
||||
struct kinetis_dmaregs_s
|
||||
{
|
||||
/* Global Registers */
|
||||
|
||||
struct kinetis_dmaglobalregs_s gbl;
|
||||
|
||||
/* Channel Registers */
|
||||
|
||||
struct kinetis_dmachanregs_s ch;
|
||||
};
|
||||
#endif
|
||||
|
||||
enum kinetis_dma_direction_e
|
||||
{
|
||||
KINETIS_DMA_DIRECTION_PERIPHERAL_TO_MEMORY,
|
||||
KINETIS_DMA_DIRECTION_MEMORY_TO_PERIPHERAL
|
||||
};
|
||||
|
||||
/* Kinetis data transfer size */
|
||||
|
||||
enum kinetis_dma_data_sz_e
|
||||
{
|
||||
KINETIS_DMA_DATA_SZ_8BIT = 0,
|
||||
KINETIS_DMA_DATA_SZ_16BIT = 1,
|
||||
KINETIS_DMA_DATA_SZ_32BIT = 2,
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmainitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the GPDMA subsystem.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kinetis_dmainitialize(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmachannel
|
||||
*
|
||||
* Description:
|
||||
* Allocate a DMA channel. This function sets aside a DMA channel and
|
||||
* gives the caller exclusive access to the DMA channel.
|
||||
*
|
||||
* Input Parameters:
|
||||
* src - DMA request source
|
||||
* per_addr - Address of the peripheral data
|
||||
* per_data_sz - Peripheral data size (register size). Note that if this
|
||||
* does not agree with the peripheral register size, DMA
|
||||
* transfers will silently fail during operation.
|
||||
* dir - transfer direction
|
||||
*
|
||||
* Returned Value:
|
||||
* On success, this function returns a non-NULL, void* DMA channel handle.
|
||||
* NULL is returned on any failure. This function can fail only if no DMA
|
||||
* channel is available.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
DMA_HANDLE kinetis_dmachannel(uint8_t src,
|
||||
uint32_t per_addr,
|
||||
enum kinetis_dma_data_sz_e per_data_sz,
|
||||
enum kinetis_dma_direction_e dir);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmafree
|
||||
*
|
||||
* Description:
|
||||
* Release a DMA channel. NOTE: The 'handle' used in this argument must
|
||||
* NEVER be used again until kinetis_dmachannel() is called again to re-
|
||||
* gain a valid handle.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kinetis_dmafree(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmasetup
|
||||
*
|
||||
* Description:
|
||||
* Configure DMA for one transfer.
|
||||
*
|
||||
* Input Parameters:
|
||||
* mem_addr - Memory address
|
||||
* ntransfers - Number of transfers. Must be 0<= ntransfers <= 0x7FFF
|
||||
* control - Channel control configuration
|
||||
*
|
||||
* Returned Value:
|
||||
* result: 0 if ok, negative else
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int kinetis_dmasetup(DMA_HANDLE handle, uint32_t mem_addr,
|
||||
size_t ntransfers, uint16_t control);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmastart
|
||||
*
|
||||
* Description:
|
||||
* Start the DMA transfer
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int kinetis_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmastop
|
||||
*
|
||||
* Description:
|
||||
* Cancel the DMA. After kinetis_dmastop() is called, the DMA channel is
|
||||
* reset and kinetis_dmasetup() must be called before kinetis_dmastart()
|
||||
* can be called again
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kinetis_dmastop(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmaresidual
|
||||
*
|
||||
* Description:
|
||||
* Returns the number of transfers left
|
||||
*
|
||||
* Returned Value:
|
||||
* Residual transfers
|
||||
****************************************************************************/
|
||||
|
||||
size_t kinetis_dmaresidual(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmasample
|
||||
*
|
||||
* Description:
|
||||
* Sample DMA register contents
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
void kinetis_dmasample(DMA_HANDLE handle, struct kinetis_dmaregs_s *regs);
|
||||
#else
|
||||
# define kinetis_dmasample(handle,regs)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmadump
|
||||
*
|
||||
* Description:
|
||||
* Dump previously sampled DMA register contents
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
void kinetis_dmadump(DMA_HANDLE handle, const struct kinetis_dmaregs_s *regs,
|
||||
const char *msg);
|
||||
#else
|
||||
# define kinetis_dmadump(handle,regs,msg)
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_KINETEIS_KINETEIS_DMA_H */
|
||||
1464
arch/arm/src/kinetis/kinetis_edma.c
Normal file
1464
arch/arm/src/kinetis/kinetis_edma.c
Normal file
File diff suppressed because it is too large
Load Diff
455
arch/arm/src/kinetis/kinetis_edma.h
Normal file
455
arch/arm/src/kinetis/kinetis_edma.h
Normal file
@ -0,0 +1,455 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/kinetis/kinetis_edma.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* This file was leveraged from the NuttX i.MXRT port.
|
||||
* Portions of that eDMA logic derived from NXP sample code which has
|
||||
* a compatible BSD 3-clause license:
|
||||
*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* All rights reserved
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_EDMAC_H
|
||||
#define __ARCH_ARM_SRC_KINETIS_KINETIS_EDMAC_H
|
||||
|
||||
/* General Usage:
|
||||
*
|
||||
* 1. Allocate a DMA channel
|
||||
*
|
||||
* DMACH_HANDLE handle;
|
||||
* handle = edma_dmach_alloc(dmamux, dchpri);
|
||||
*
|
||||
* Where 'dmamux' is the channel DMAMUX configuration register setting and
|
||||
* 'dchpri' is the channel DCHPRIO priority register setting.
|
||||
*
|
||||
* 2. Create the transfer configuration:
|
||||
*
|
||||
* struct kinetis_edma_xfrconfig_s config;
|
||||
* config.saddr = ..;
|
||||
* config.daddr = ..;
|
||||
* etc.
|
||||
*
|
||||
* 3. Setup the transfer in hardware:
|
||||
*
|
||||
* int ret;
|
||||
* ret = kinetis_dmach_xfrsetup(handle, &config);
|
||||
*
|
||||
* 4. If you are setting up a scatter gather DMA
|
||||
* (with CONFIG_KINETIS_EDMA_NTCD > 0), then repeat steps 2 and 3 for
|
||||
* each segment of the transfer.
|
||||
*
|
||||
* 5. Start the DMA:
|
||||
*
|
||||
* ret = kinetis_dmach_start(handle, my_callback_func, priv);
|
||||
*
|
||||
* Where my_callback_func() is called when the DMA completes or an error
|
||||
* occurs. 'priv' represents some internal driver state that will be
|
||||
* provided with the callback.
|
||||
*
|
||||
* 6. If you need to stop the DMA and free resources (such as if a timeout
|
||||
* occurs), then:
|
||||
*
|
||||
* i mxrt_dmach_stop(handle);
|
||||
*
|
||||
* 7. The callback will be received when the DMA completes (or an error
|
||||
* occurs). After that, you may free the DMA channel, or re-use it on
|
||||
* subsequent DMAs.
|
||||
*
|
||||
* kinetis_dmach_free(handle);
|
||||
*
|
||||
* Almost non-invasive debug instrumentation is available. You may call
|
||||
* kinetis_dmasample() to save the current state of the eDMA registers at
|
||||
* any given point in time. At some later, postmortem analysis, you can
|
||||
* dump the content of the buffered registers with kinetis_dmadump().
|
||||
* kinetis_dmasample() is also available for monitoring DMA progress.
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include "hardware/kinetis_edma.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration flags.
|
||||
*
|
||||
* REVISIT: Many missing options that should be represented as flags:
|
||||
* 1. Bandwidth
|
||||
* 2. Source/Destination modulo
|
||||
*/
|
||||
|
||||
#define EDMA_CONFIG_LINKTYPE_SHIFT (0) /* Bits 0-1: Link type */
|
||||
#define EDMA_CONFIG_LINKTYPE_MASK (3 << EDMA_CONFIG_LINKTYPE_SHIFT)
|
||||
# define EDMA_CONFIG_LINKTYPE_LINKNONE (0 << EDMA_CONFIG_LINKTYPE_SHIFT) /* No channel link */
|
||||
# define EDMA_CONFIG_LINKTYPE_MINORLINK (1 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link after each minor loop */
|
||||
# define EDMA_CONFIG_LINKTYPE_MAJORLINK (2 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link when major loop count exhausted */
|
||||
|
||||
#define EDMA_CONFIG_LOOP_SHIFT (2) /* Bits 2: Loop type */
|
||||
#define EDMA_CONFIG_LOOP_MASK (3 << EDMA_CONFIG_LOOP_SHIFT)
|
||||
# define EDMA_CONFIG_LOOPNONE (0 << EDMA_CONFIG_LOOP_SHIFT) /* No looping */
|
||||
# define EDMA_CONFIG_LOOPSRC (1 << EDMA_CONFIG_LOOP_SHIFT) /* Source looping */
|
||||
# define EDMA_CONFIG_LOOPDEST (2 << EDMA_CONFIG_LOOP_SHIFT) /* Dest looping */
|
||||
|
||||
#define EDMA_CONFIG_INTHALF (1 << 3) /* Bits 3: Int on HALF */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
typedef FAR void *DMACH_HANDLE;
|
||||
typedef void (*edma_callback_t)(DMACH_HANDLE handle,
|
||||
void *arg, bool done, int result);
|
||||
|
||||
/* eDMA transfer type */
|
||||
|
||||
enum kinetis_edma_xfrtype_e
|
||||
{
|
||||
EDMA_MEM2MEM = 0, /* Transfer from memory to memory */
|
||||
EDMA_PERIPH2MEM, /* Transfer from peripheral to memory */
|
||||
EDMA_MEM2PERIPH, /* Transfer from memory to peripheral */
|
||||
};
|
||||
|
||||
/* eDMA transfer sises */
|
||||
|
||||
enum kinetis_edma_sizes_e
|
||||
{
|
||||
EDMA_8BIT = 0, /* Transfer data size 8 */
|
||||
EDMA_16BIT = 1, /* Transfer data size 16 */
|
||||
EDMA_32BIT = 2, /* Transfer data size 32 */
|
||||
};
|
||||
|
||||
/* This structure holds the source/destination transfer attribute
|
||||
* configuration.
|
||||
*/
|
||||
|
||||
struct kinetis_edma_xfrconfig_s
|
||||
{
|
||||
uint32_t saddr; /* Source data address. */
|
||||
uint32_t daddr; /* Destination data address. */
|
||||
int16_t soff; /* Sign-extended offset for current source address. */
|
||||
int16_t doff; /* Sign-extended offset for current destination address. */
|
||||
uint16_t iter; /* Major loop iteration count. */
|
||||
uint8_t flags; /* See EDMA_CONFIG_* definitions */
|
||||
uint8_t ssize; /* Source data transfer size (see TCD_ATTR_SIZE_* definitions in rdware/. */
|
||||
uint8_t dsize; /* Destination data transfer size. */
|
||||
uint8_t ttype; /* Transfer type (see enum kinetis_edma_xfrtype_e). */
|
||||
#ifdef CONFIG_KINETIS_EDMA_EMLIM
|
||||
uint16_t nbytes; /* Bytes to transfer in a minor loop */
|
||||
#else
|
||||
uint32_t nbytes; /* Bytes to transfer in a minor loop */
|
||||
#endif
|
||||
#ifdef CONFIG_KINETIS_EDMA_ELINK
|
||||
DMACH_HANDLE linkch; /* Link channel (With EDMA_CONFIG_LINKTYPE_* flags) */
|
||||
#endif
|
||||
};
|
||||
|
||||
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA
|
||||
* is selected
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
struct kinetis_dmaregs_s
|
||||
{
|
||||
uint8_t chan; /* Sampled channel */
|
||||
|
||||
/* eDMA Global Registers */
|
||||
|
||||
uint32_t cr; /* Control */
|
||||
uint32_t es; /* Error Status */
|
||||
uint32_t erq; /* Enable Request */
|
||||
uint32_t req; /* Interrupt Request */
|
||||
uint32_t err; /* Error */
|
||||
uint32_t hrs; /* Hardware Request Status */
|
||||
uint32_t ears; /* Enable Asynchronous Request in Stop */
|
||||
|
||||
/* eDMA Channel registers */
|
||||
|
||||
uint8_t dchpri; /* Channel priority */
|
||||
|
||||
/* eDMA TCD */
|
||||
|
||||
uint32_t saddr; /* TCD Source Address */
|
||||
uint16_t soff; /* TCD Signed Source Address Offset */
|
||||
uint16_t attr; /* TCD Transfer Attributes */
|
||||
uint32_t nbml; /* TCD Signed Minor Loop Offset / Byte Count */
|
||||
uint32_t slast; /* TCD Last Source Address Adjustment */
|
||||
uint32_t daddr; /* TCD Destination Address */
|
||||
uint16_t doff; /* TCD Signed Destination Address Offset */
|
||||
uint16_t citer; /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
uint32_t dlastsga; /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
uint16_t csr; /* TCD Control and Status */
|
||||
uint16_t biter; /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
/* DMAMUX registers */
|
||||
|
||||
uint32_t dmamux; /* Channel configuration */
|
||||
};
|
||||
#endif /* CONFIG_DEBUG_DMA */
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmach_alloc
|
||||
*
|
||||
* Allocate a DMA channel. This function sets aside a DMA channel,
|
||||
* initializes the DMAMUX for the channel, then gives the caller exclusive
|
||||
* access to the DMA channel.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dmamux - DMAMUX configuration see DMAMUX channel configuration register
|
||||
* bit-field definitions in hardware/kinetis_dmamux.h.
|
||||
* Settings include:
|
||||
*
|
||||
* DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required)
|
||||
* DMAMUX_CHCFG_TRIG DMA Channel Trigger Enable (optional)
|
||||
* DMAMUX_CHCFG_ENBL DMA Mux Channel Enable (required)
|
||||
*
|
||||
* A value of zero will disable the DMAMUX channel.
|
||||
* dchpri - DCHPRI channel priority configuration. See DCHPRI channel
|
||||
* configuration register bit-field definitions in
|
||||
* hardware/kinetis_edma.h. Meaningful settings include:
|
||||
*
|
||||
* EDMA_DCHPRI_CHPRI Channel Arbitration Priority
|
||||
* DCHPRI_DPA Disable Preempt Ability
|
||||
* DCHPRI_ECP Enable Channel Preemption
|
||||
*
|
||||
* The power-on default, 0x05, is a reasonable choice.
|
||||
*
|
||||
* Returned Value:
|
||||
* If a DMA channel is available, this function returns a non-NULL, void*
|
||||
* DMA channel handle. NULL is returned on any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
DMACH_HANDLE kinetis_dmach_alloc(uint8_t dmamux, uint8_t dchpri);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmach_free
|
||||
*
|
||||
* Description:
|
||||
* Release a DMA channel.
|
||||
* NOTE: The 'handle' used in this argument must NEVER be used again
|
||||
* until kinetis_dmach_alloc() is called again to re-gain a valid handle.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kinetis_dmach_free(DMACH_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmach_xfrsetup
|
||||
*
|
||||
* Description:
|
||||
* This function adds the eDMA transfer to the DMA sequence. The request
|
||||
* is setup according to the content of the transfer configuration
|
||||
* structure. For "normal" DMA, kinetis_dmach_xfrsetup is called only
|
||||
* once.
|
||||
* Scatter/gather DMA is accomplished by calling this function repeatedly,
|
||||
* once for each transfer in the sequence. Scatter/gather DMA processing
|
||||
* is enabled automatically when the second transfer configuration is
|
||||
* received.
|
||||
*
|
||||
* This function may be called multiple times to handle multiple,
|
||||
* discontinuous transfers (scatter-gather)
|
||||
*
|
||||
* Input Parameters:
|
||||
* handle - DMA channel handle created by kinetis_dmach_alloc()
|
||||
* config - A DMA transfer configuration instance, populated by the
|
||||
* The content of 'config' describes the transfer
|
||||
*
|
||||
* Returned Value
|
||||
* Zero (OK) is returned on success; a negated errno value is returned on
|
||||
* any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int kinetis_dmach_xfrsetup(DMACH_HANDLE *handle,
|
||||
const struct kinetis_edma_xfrconfig_s *config);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmach_start
|
||||
*
|
||||
* Description:
|
||||
* Start the DMA transfer by enabling the channel DMA request.
|
||||
* This function should be called after the final call to
|
||||
* kinetis_dmasetup() in order to avoid race conditions.
|
||||
*
|
||||
* At the conclusion of each major DMA loop, a callback to the
|
||||
* user-provided function is made: |For "normal" DMAs, this will
|
||||
* correspond to the DMA DONE interrupt; for scatter gather DMAs, multiple
|
||||
* interrupts will be generated with the final being the DONE interrupt.
|
||||
*
|
||||
* At the conclusion of the DMA, the DMA channel is reset, all TCDs are
|
||||
* freed, and the callback function is called with the the success/fail
|
||||
* result of the DMA.
|
||||
*
|
||||
* NOTE:
|
||||
* On Rx DMAs (peripheral-to-memory or memory-to-memory), it is necessary
|
||||
* to invalidate the destination memory. That is not done automatically
|
||||
* by the DMA module. Invalidation of the destination memory regions is
|
||||
* the responsibility of the caller.
|
||||
*
|
||||
* Input Parameters:
|
||||
* handle - DMA channel handle created by kinetis_dmach_alloc()
|
||||
* callback - The callback to be invoked when the DMA is completes or is
|
||||
* aborted.
|
||||
* arg - An argument that accompanies the callback
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success; a negated errno value is returned on
|
||||
* any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int kinetis_dmach_start(DMACH_HANDLE handle,
|
||||
edma_callback_t callback, void *arg);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmach_stop
|
||||
*
|
||||
* Description:
|
||||
* Cancel the DMA. After kinetis_dmach_stop() is called, the DMA channel
|
||||
* is reset, all TCDs are freed, and kinetis_dmarx/txsetup() must be called
|
||||
* before kinetis_dmach_start() can be called again
|
||||
*
|
||||
* Input Parameters:
|
||||
* handle - DMA channel handle created by kinetis_dmach_alloc()
|
||||
*
|
||||
* Returned Value:
|
||||
* None.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kinetis_dmach_stop(DMACH_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmach_getcount
|
||||
*
|
||||
* Description:
|
||||
* This function checks the TCD (Task Control Descriptor) status for a
|
||||
* specified eDMA channel and returns the the number of major loop counts
|
||||
* that have not finished.
|
||||
*
|
||||
* NOTES:
|
||||
* 1. This function can only be used to get unfinished major loop count of
|
||||
* transfer without the next TCD, or it might be inaccuracy.
|
||||
* 2. The unfinished/remaining transfer bytes cannot be obtained directly
|
||||
* from registers while the channel is running.
|
||||
*
|
||||
* Because to calculate the remaining bytes, the initial NBYTES configured
|
||||
* in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not
|
||||
* support getting it while a channel is active. In another words, the
|
||||
* NBYTES value reading is always the actual (decrementing) NBYTES value
|
||||
* the dma_engine is working with while a channel is running.
|
||||
* Consequently, to get the remaining transfer bytes, a software-saved
|
||||
* initial value of NBYTES (for example copied before enabling the channel)
|
||||
* is needed. The formula to calculate it is shown below:
|
||||
*
|
||||
* RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)
|
||||
*
|
||||
* Input Parameters:
|
||||
* handle - DMA channel handle created by kinetis_dmach_alloc()
|
||||
*
|
||||
* Returned Value:
|
||||
* Major loop count which has not been transferred yet for the current TCD.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
unsigned int kinetis_dmach_getcount(DMACH_HANDLE *handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmasample
|
||||
*
|
||||
* Description:
|
||||
* Sample DMA register contents
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
void kinetis_dmasample(DMACH_HANDLE handle, struct kinetis_dmaregs_s *regs);
|
||||
#else
|
||||
# define kinetis_dmasample(handle,regs)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmadump
|
||||
*
|
||||
* Description:
|
||||
* Dump previously sampled DMA register contents
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
void kinetis_dmadump(const struct kinetis_dmaregs_s *regs, const char *msg);
|
||||
#else
|
||||
# define kinetis_dmadump(handle,regs,msg)
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_EDMAC_H */
|
||||
Loading…
Reference in New Issue
Block a user