From 79574c18d84ffdd65935030773c38228467e01c9 Mon Sep 17 00:00:00 2001 From: simbit18 <101105604+simbit18@users.noreply.github.com> Date: Tue, 2 May 2023 16:28:49 +0200 Subject: [PATCH] arch: Fix nxstyle errors error: Long line found --- arch/misoc/src/lm32/lm32_config.h | 30 +- arch/renesas/src/m16c/chip.h | 30 +- arch/renesas/src/m16c/m16c_timer.h | 18 +- arch/renesas/src/m16c/m16c_uart.h | 22 +- arch/renesas/src/sh1/sh1_703x.h | 28 +- arch/x86/src/qemu/chip.h | 28 +- arch/x86/src/qemu/qemu_memorymap.h | 28 +- arch/x86_64/src/intel64/chip.h | 24 +- arch/x86_64/src/intel64/intel64.h | 50 +- arch/x86_64/src/intel64/intel64_rtc.c | 64 +- arch/xtensa/src/esp32/hardware/esp32_tim.h | 657 ++++++++++++--------- 11 files changed, 556 insertions(+), 423 deletions(-) diff --git a/arch/misoc/src/lm32/lm32_config.h b/arch/misoc/src/lm32/lm32_config.h index 9bce5ae88c..7d323b8826 100644 --- a/arch/misoc/src/lm32/lm32_config.h +++ b/arch/misoc/src/lm32/lm32_config.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/misoc/src/lm32/lm32_config.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,25 +16,25 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_MISOC_SRC_LM32_LM32_CONFIG_H #define __ARCH_MISOC_SRC_LM32_LM32_CONFIG_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* UARTs ****************************************************************************/ +/* UARTs ********************************************************************/ /* Are any UARTs enabled? */ @@ -59,20 +59,20 @@ # undef HAVE_SERIAL_CONSOLE #endif -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Functions Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_MISOC_SRC_LM32_LM32_CONFIG_H */ diff --git a/arch/renesas/src/m16c/chip.h b/arch/renesas/src/m16c/chip.h index 1772cf06f5..38424d7bf3 100644 --- a/arch/renesas/src/m16c/chip.h +++ b/arch/renesas/src/m16c/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/renesas/src/m16c/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,23 +16,23 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_RENESAS_SRC_M16C_CHIP_H #define __ARCH_RENESAS_SRC_M16C_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #ifndef __ASSEMBLY__ # include #endif -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ /* FLG register bits */ @@ -54,8 +54,8 @@ #define M16C_SFR_BASE 0x00000 /* 00000-003ff: Special Function Registers */ -/* Internal, on-chip SRAM begins at address 0x00400 for all chips, regardless of the - * size of the on-chip SRAM. +/* Internal, on-chip SRAM begins at address 0x00400 for all chips, + * regardless of the size of the on-chip SRAM. */ #define M16C_IRAM_BASE 0x00400 /* 00400-00xxx: Internal RAM */ @@ -72,13 +72,13 @@ #define M16C_VEEPROM1_BASE 0x0f000 /* 0f000-0f7fff: Virtual EEPPROM block 1 */ #define M16C_VEEPROM2_BASE 0x0f800 /* 0f800-0fffff: Virtual EEPPROM block 2 */ -/* If there were external, "far" RAM, it would be begin at 0x10000. However, these - * specific chips do not support external RAM. +/* If there were external, "far" RAM, it would be begin at 0x10000. + * However, thesespecific chips do not support external RAM. */ -/* Each part has a different amount of on-chip FLASH. The ending FLASH address is - * 0xfffff for all chips, but the starting address varies depending on the amount - * of on-chip FLASH. +/* Each part has a different amount of on-chip FLASH. + * The ending FLASH address is0xfffff for all chips, but the starting address + * varies depending on the amount of on-chip FLASH. */ #if defined(CONFIG_ARCH_CHIP_M30262F3) @@ -233,9 +233,9 @@ #define M16C_PUR2 0x003fe /* Pull-up control 2 */ #define M16C_PCR 0x003ff /* Port control */ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ diff --git a/arch/renesas/src/m16c/m16c_timer.h b/arch/renesas/src/m16c/m16c_timer.h index c6b28afbc7..9b459c6e89 100644 --- a/arch/renesas/src/m16c/m16c_timer.h +++ b/arch/renesas/src/m16c/m16c_timer.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/renesas/src/m16c/m16c_timer.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_RENESAS_SRC_M16C_M16C_TIMER_H #define __ARCH_RENESAS_SRC_M16C_M16C_TIMER_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Register Bit Definitions *********************************************************/ +/* Register Bit Definitions *************************************************/ #define M16C_TA0IC 0x00055 /* Timer A0 interrupt control */ #define M16C_TA1IC 0x00056 /* Timer A1 interrupt control */ @@ -202,9 +202,9 @@ #define TBnMR_TCK_PMF32 0x80 /* 10: f32 */ #define TBnMR_TCK_PMFC32 0xc0 /* 11: fc32 */ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ diff --git a/arch/renesas/src/m16c/m16c_uart.h b/arch/renesas/src/m16c/m16c_uart.h index 2268e6e8df..5a149e4439 100644 --- a/arch/renesas/src/m16c/m16c_uart.h +++ b/arch/renesas/src/m16c/m16c_uart.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/renesas/src/m16c/m16c_uart.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,28 +16,28 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_RENESAS_SRC_M16C_M16C_UART_H #define __ARCH_RENESAS_SRC_M16C_M16C_UART_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* UART Register Block Base Addresses ***********************************************/ +/* UART Register Block Base Addresses ***************************************/ #define M16C_UART0_BASE 0x003a0 /* First UART0 register */ #define M16C_UART1_BASE 0x003a8 /* First UART1 register */ #define M16C_UART2_BASE 0x00378 /* First UART2 register (ignoring special regs) */ -/* UART Register Offsets ************************************************************/ +/* UART Register Offsets ****************************************************/ #define M16C_UART_MR 0x00 /* 8-bit UART transmit/receive mode */ #define M16C_UART_BRG 0x01 /* 8-bit UART bit rate generator */ @@ -46,7 +46,7 @@ #define M16C_UART_C1 0x05 /* 8-bit UART transmit/receive control 1 */ #define M16C_UART_RB 0x06 /* 16-bit UART receive buffer */ -/* UART Register Bit Definitions ****************************************************/ +/* UART Register Bit Definitions ********************************************/ /* UART transmit/receive mode */ @@ -120,9 +120,9 @@ /* UART2 special mode register 4 (to be provided) */ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ diff --git a/arch/renesas/src/sh1/sh1_703x.h b/arch/renesas/src/sh1/sh1_703x.h index 457a47681b..c27b9e3d53 100644 --- a/arch/renesas/src/sh1/sh1_703x.h +++ b/arch/renesas/src/sh1/sh1_703x.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/renesas/src/sh1/sh1_703x.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,22 +16,22 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_RENESAS_SRC_SH1_SH1_703X_H #define __ARCH_RENESAS_SRC_SH1_SH1_703X_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Memory-mapped register addresses *************************************************/ +/* Memory-mapped register addresses *****************************************/ /* Serial Communications interface (SCI) */ @@ -253,7 +253,7 @@ #define SH1_TPC_NDRB1 (0x05fffff6) /* 8-bits wide */ #define SH1_TPC_NDRA1 (0x05fffff7) /* 8-bits wide */ -/* Register bit definitions *********************************************************/ +/* Register bit definitions *************************************************/ /* Serial Communications interface (SCI) */ @@ -432,16 +432,16 @@ #define SH1_ICR_NMIE (0x0100) /* Bits 8: Interrupt on rising edge of NMI input */ #define SH1_ICR_NMIL (0x8000) /* Bits 15: NMI input level high */ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Functions Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_RENESAS_SRC_SH1_SH1_703X_H */ diff --git a/arch/x86/src/qemu/chip.h b/arch/x86/src/qemu/chip.h index a7065e0701..f39fc18abf 100644 --- a/arch/x86/src/qemu/chip.h +++ b/arch/x86/src/qemu/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/x86/src/qemu/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_X86_SRC_QEMU_CHIP_H #define __ARCH_X86_SRC_QEMU_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -34,26 +34,26 @@ # error "Unsupported I486 chip" #endif -/* Include only the memory map. Other chip hardware files should then include this - * file for the proper setup +/* Include only the memory map. Other chip hardware files should then + * include this file for the proper setup */ #include "qemu_memorymap.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Functions Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_X86_SRC_QEMU_CHIP_H */ diff --git a/arch/x86/src/qemu/qemu_memorymap.h b/arch/x86/src/qemu/qemu_memorymap.h index 02b08191a1..e8424c6ba3 100644 --- a/arch/x86/src/qemu/qemu_memorymap.h +++ b/arch/x86/src/qemu/qemu_memorymap.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/x86/src/qemu/qemu_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,37 +16,37 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_X86_SRC_QEMU_QEMU_MEMORYMAP_H #define __ARCH_X86_SRC_QEMU_QEMU_MEMORYMAP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Memory Map ***********************************************************************/ +/* Memory Map ***************************************************************/ -/* Peripheral Base Addresses ********************************************************/ +/* Peripheral Base Addresses ************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Functions Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_X86_SRC_QEMU_QEMU_MEMORYMAP_H */ diff --git a/arch/x86_64/src/intel64/chip.h b/arch/x86_64/src/intel64/chip.h index 07f62a9668..5b34bc4161 100644 --- a/arch/x86_64/src/intel64/chip.h +++ b/arch/x86_64/src/intel64/chip.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/x86_64/src/intel64/chip.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,31 +16,31 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_X86_64_SRC_INTEL64_CHIP_H #define __ARCH_X86_64_SRC_INTEL64_CHIP_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #endif /* __ARCH_X86_64_SRC_INTEL64_CHIP_H */ diff --git a/arch/x86_64/src/intel64/intel64.h b/arch/x86_64/src/intel64/intel64.h index 0d0ae4aa8c..b8d644038e 100644 --- a/arch/x86_64/src/intel64/intel64.h +++ b/arch/x86_64/src/intel64/intel64.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/x86_64/src/intel64/intel64.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_X86_64_SRC_INTEL64_INTEL64_H #define __ARCH_X86_64_SRC_INTEL64_INTEL64_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -35,25 +35,25 @@ #include "x86_64_internal.h" #include "chip.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Configuration ********************************************************************/ +/* Configuration ************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Inline Functions - ************************************************************************************/ + ****************************************************************************/ #ifndef __ASSEMBLY__ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #undef EXTERN #if defined(__cplusplus) @@ -64,31 +64,33 @@ extern "C" #define EXTERN extern #endif -/************************************************************************************ +/**************************************************************************** * Public Function Prototypes - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: intel64_lowsetup * * Description: - * Called at the very beginning of _start. Performs low level initialization - * including setup of the console UART. This UART done early so that the serial - * console is available for debugging very early in the boot sequence. + * Called at the very beginning of _start. + * Performs low level initializationincluding setup of the console UART. + * This UART done early so that the serial console is available for + * debugging very early in the boot sequence. * - ************************************************************************************/ + ****************************************************************************/ void intel64_lowsetup(void); -/************************************************************************************ +/**************************************************************************** * Name: vector_* * * Description: * These are the various ISR/IRQ vector address exported from - * intel64_vectors.S. These addresses need to have global scope so that they - * can be known to the interrupt initialization logic in intel64_irq.c. + * intel64_vectors.S. These addresses need to have global scope + * so that they can be known to the interrupt initialization logic in + * intel64_irq.c. * - ************************************************************************************/ + ****************************************************************************/ void vector_isr0(void); void vector_isr1(void); diff --git a/arch/x86_64/src/intel64/intel64_rtc.c b/arch/x86_64/src/intel64/intel64_rtc.c index 58ed8bc0cb..11dc83a8a6 100644 --- a/arch/x86_64/src/intel64/intel64_rtc.c +++ b/arch/x86_64/src/intel64/intel64_rtc.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/x86_64/src/intel64/intel64_rtc.c * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -36,11 +36,11 @@ #include "x86_64_internal.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/* Configuration ********************************************************************/ +/* Configuration ************************************************************/ /* This is a hacky implementation based on TSC, we only support Hi-RES mode */ @@ -54,33 +54,33 @@ #define NS_PER_MSEC 1000000UL #define NS_PER_SEC 1000000000UL -/************************************************************************************ +/**************************************************************************** * Private Types - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_HIRES volatile bool g_rtc_enabled = false; -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ static unsigned long rtc_freq; static unsigned long rtc_overflow; static unsigned long rtc_last; static unsigned long rtc_overflows; -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ static unsigned long rtc_read(void) { @@ -96,16 +96,16 @@ static unsigned long rtc_read(void) return tmr; } -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_initialize * * Description: - * Initialize the hardware RTC per the selected configuration. This function is - * called once during the OS initialization sequence + * Initialize the hardware RTC per the selected configuration. + * This function is called once during the OS initialization sequence. * * Input Parameters: * None @@ -113,7 +113,7 @@ static unsigned long rtc_read(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_initialize(void) { @@ -123,13 +123,13 @@ int up_rtc_initialize(void) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_gettime * * Description: - * Get the current time from the high resolution RTC clock/counter. This interface - * is only supported by the high-resolution RTC/counter hardware implementation. - * It is used to replace the system timer. + * Get the current time from the high resolution RTC clock/counter. + * This interface is only supported by the high-resolution RTC/counter + * hardware implementation. It is used to replace the system timer. * * Input Parameters: * tp - The location to return the high resolution time value. @@ -137,7 +137,7 @@ int up_rtc_initialize(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_gettime(struct timespec *tp) { @@ -150,12 +150,12 @@ int up_rtc_gettime(struct timespec *tp) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_settime * * Description: - * Set the RTC to the provided time. All RTC implementations must be able to - * set their time based on a standard timespec. + * Set the RTC to the provided time. All RTC implementations must be able + * to set their time based on a standard timespec. * * Input Parameters: * tp - the time to use @@ -163,7 +163,7 @@ int up_rtc_gettime(struct timespec *tp) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_settime(const struct timespec *tp) { diff --git a/arch/xtensa/src/esp32/hardware/esp32_tim.h b/arch/xtensa/src/esp32/hardware/esp32_tim.h index dca6de9c02..c09203d145 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_tim.h +++ b/arch/xtensa/src/esp32/hardware/esp32_tim.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/xtensa/src/esp32/hardware/esp32_tim.h * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,14 +16,14 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_TIM_H #define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_TIM_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include "esp32_soc.h" @@ -66,18 +66,24 @@ #define MWDT_FEED_OFFSET 0x0018 #define MWDT_INT_ENA_REG_OFFSET 0x0050 #define MWDT_INT_CLR_REG_OFFSET 0x005c -/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt - * registers + +/* The value that needs to be written to TIMG_WDT_WKEY + * to write-enable the wdt registers. */ + #define TIMG_WDT_WKEY_VALUE 0x50D83AA1 /* Possible values for TIMG_WDT_STGx */ + #define TIMG_WDT_STG_SEL_OFF 0 #define TIMG_WDT_STG_SEL_INT 1 #define TIMG_WDT_STG_SEL_RESET_CPU 2 #define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 -/* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */ +/* Possible values for TIMG_WDT_CPU_RESET_LENGTH + * and TIMG_WDT_SYS_RESET_LENGTH + */ + #define TIMG_WDT_RESET_LENGTH_100_NS 0 #define TIMG_WDT_RESET_LENGTH_200_NS 1 #define TIMG_WDT_RESET_LENGTH_300_NS 2 @@ -90,58 +96,68 @@ #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000) #define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000) -/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; - *description: When set timer 0 time-base counter is enabled - */ + +/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +/* Description: When set timer 0 time-base counter is enabled. */ #define TIMG_T0_EN (BIT(31)) #define TIMG_T0_EN_M (BIT(31)) #define TIMG_T0_EN_V 0x1 #define TIMG_T0_EN_S 31 -/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; - * description: When set timer 0 time-base counter increment. When cleared timer - * 0 time-base counter decrement. + +/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ + +/* Description: When set timer 0 time-base counter increment. + * When cleared timer 0 time-base counter decrement. */ #define TIMG_T0_INCREASE (BIT(30)) #define TIMG_T0_INCREASE_M (BIT(30)) #define TIMG_T0_INCREASE_V 0x1 #define TIMG_T0_INCREASE_S 30 -/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; - * description: When set timer 0 auto-reload at alarming is enabled - */ + +/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ + +/* Description: When set timer 0 auto-reload at alarming is enabled. */ #define TIMG_T0_AUTORELOAD (BIT(29)) #define TIMG_T0_AUTORELOAD_M (BIT(29)) #define TIMG_T0_AUTORELOAD_V 0x1 #define TIMG_T0_AUTORELOAD_S 29 -/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; - *description: Timer 0 clock (T0_clk) prescale value. - */ + +/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ + +/* Description: Timer 0 clock (T0_clk) prescale value. */ #define TIMG_T0_DIVIDER 0x0000FFFF #define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S)) #define TIMG_T0_DIVIDER_V 0xFFFF #define TIMG_T0_DIVIDER_S 13 -/* TIMG_T0_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; - * description: When set edge type interrupt will be generated during alarm - */ + +/* TIMG_T0_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ + +/* Description: When set edge type interrupt will be generated during alarm */ #define TIMG_T0_EDGE_INT_EN (BIT(12)) #define TIMG_T0_EDGE_INT_EN_M (BIT(12)) #define TIMG_T0_EDGE_INT_EN_V 0x1 #define TIMG_T0_EDGE_INT_EN_S 12 -/* TIMG_T0_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; - * description: When set level type interrupt will be generated during alarm + +/* TIMG_T0_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */ + +/* Description: When set level type interrupt + * will be generated during alarm */ #define TIMG_T0_LEVEL_INT_EN (BIT(11)) #define TIMG_T0_LEVEL_INT_EN_M (BIT(11)) #define TIMG_T0_LEVEL_INT_EN_V 0x1 #define TIMG_T0_LEVEL_INT_EN_S 11 -/* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; - * description: When set alarm is enabled - */ + +/* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +/* Description: When set alarm is enabled */ #define TIMG_T0_ALARM_EN (BIT(10)) #define TIMG_T0_ALARM_EN_M (BIT(10)) @@ -149,8 +165,10 @@ #define TIMG_T0_ALARM_EN_S 10 #define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004) -/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; - * description: Register to store timer 0 time-base counter current + +/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Register to store timer 0 time-base counter current * value lower 32 bits. */ @@ -160,8 +178,10 @@ #define TIMG_T0_LO_S 0 #define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008) -/* TIMG_T0_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; - * description: Register to store timer 0 time-base counter current value + +/* TIMG_T0_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Register to store timer 0 time-base counter current value * higher 32 bits. */ @@ -171,9 +191,12 @@ #define TIMG_T0_HI_S 0 #define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c) -/* TIMG_T0_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; - * description: Write any value will trigger a timer 0 time-base counter value - * update (timer 0 current value will be stored in registers above) + +/* TIMG_T0_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Write any value will trigger + * a timer 0 time-base counter value update + * (timer 0 current value will be stored in registers above). */ #define TIMG_T0_UPDATE 0xFFFFFFFF @@ -182,9 +205,11 @@ #define TIMG_T0_UPDATE_S 0 #define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010) -/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * description: Timer 0 time-base counter value lower 32 bits that - * will trigger the alarm + +/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Timer 0 time-base counter value lower 32 bits that + * will trigger the alarm. */ #define TIMG_T0_ALARM_LO 0xFFFFFFFF @@ -193,9 +218,11 @@ #define TIMG_T0_ALARM_LO_S 0 #define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014) -/* TIMG_T0_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * description: Timer 0 time-base counter value higher 32 bits that - * will trigger the alarm + +/* TIMG_T0_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Timer 0 time-base counter value higher 32 bits that + * will trigger the alarm. */ #define TIMG_T0_ALARM_HI 0xFFFFFFFF @@ -204,9 +231,11 @@ #define TIMG_T0_ALARM_HI_S 0 #define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018) -/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * description: Lower 32 bits of the value that will load into timer 0 - * time-base counter + +/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Lower 32 bits of the value that will load into timer 0 + * time-base counter. */ #define TIMG_T0_LOAD_LO 0xFFFFFFFF @@ -215,9 +244,11 @@ #define TIMG_T0_LOAD_LO_S 0 #define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c) -/* TIMG_T0_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * description: higher 32 bits of the value that will load into timer 0 - * time-base counter + +/* TIMG_T0_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Higher 32 bits of the value that will load into timer 0 + * time-base counter. */ #define TIMG_T0_LOAD_HI 0xFFFFFFFF @@ -226,8 +257,11 @@ #define TIMG_T0_LOAD_HI_S 0 #define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020) -/* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; - * description: Write any value will trigger timer 0 time-base counter reload + +/* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Write any value will trigger timer 0 + * time-base counter reload. */ #define TIMG_T0_LOAD 0xFFFFFFFF @@ -236,58 +270,70 @@ #define TIMG_T0_LOAD_S 0 #define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0024) -/* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; - *description: When set timer 1 time-base counter is enabled - */ + +/* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +/* Description: When set timer 1 time-base counter is enabled. */ #define TIMG_T1_EN (BIT(31)) #define TIMG_T1_EN_M (BIT(31)) #define TIMG_T1_EN_V 0x1 #define TIMG_T1_EN_S 31 -/* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; - * description: When set timer 1 time-base counter increment. When cleared timer - * 1 time-base counter decrement. + +/* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ + +/* Description: When set timer 1 time-base counter increment. + * When cleared timer 1 time-base counter decrement. */ #define TIMG_T1_INCREASE (BIT(30)) #define TIMG_T1_INCREASE_M (BIT(30)) #define TIMG_T1_INCREASE_V 0x1 #define TIMG_T1_INCREASE_S 30 -/* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; - * description: When set timer 1 auto-reload at alarming is enabled - */ + +/* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ + +/* Description: When set timer 1 auto-reload at alarming is enabled. */ #define TIMG_T1_AUTORELOAD (BIT(29)) #define TIMG_T1_AUTORELOAD_M (BIT(29)) #define TIMG_T1_AUTORELOAD_V 0x1 #define TIMG_T1_AUTORELOAD_S 29 -/* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; - * description: Timer 1 clock (T1_clk) prescale value. - */ + +/* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ + +/* Description: Timer 1 clock (T1_clk) prescale value. */ #define TIMG_T1_DIVIDER 0x0000FFFF #define TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S)) #define TIMG_T1_DIVIDER_V 0xFFFF #define TIMG_T1_DIVIDER_S 13 -/* TIMG_T1_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; - * description: When set edge type interrupt will be generated during alarm + +/* TIMG_T1_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ + +/* Description: When set edge type interrupt + * will be generated during alarm. */ #define TIMG_T1_EDGE_INT_EN (BIT(12)) #define TIMG_T1_EDGE_INT_EN_M (BIT(12)) #define TIMG_T1_EDGE_INT_EN_V 0x1 #define TIMG_T1_EDGE_INT_EN_S 12 -/* TIMG_T1_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; - * description: When set level type interrupt will be generated during alarm + +/* TIMG_T1_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */ + +/* Description: When set level type interrupt will be generated + * during alarm. */ #define TIMG_T1_LEVEL_INT_EN (BIT(11)) #define TIMG_T1_LEVEL_INT_EN_M (BIT(11)) #define TIMG_T1_LEVEL_INT_EN_V 0x1 #define TIMG_T1_LEVEL_INT_EN_S 11 -/* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; - * description: When set alarm is enabled - */ + +/* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +/* Description: When set alarm is enabled. */ #define TIMG_T1_ALARM_EN (BIT(10)) #define TIMG_T1_ALARM_EN_M (BIT(10)) @@ -295,8 +341,10 @@ #define TIMG_T1_ALARM_EN_S 10 #define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x0028) -/* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; - * description: Register to store timer 1 time-base counter current + +/* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Register to store timer 1 time-base counter current * value lower 32 bits. */ @@ -306,8 +354,10 @@ #define TIMG_T1_LO_S 0 #define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x002c) -/* TIMG_T1_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; - * description: Register to store timer 1 time-base counter current value + +/* TIMG_T1_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Register to store timer 1 time-base counter current value * higher 32 bits. */ @@ -317,9 +367,12 @@ #define TIMG_T1_HI_S 0 #define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0030) -/* TIMG_T1_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; - * description: Write any value will trigger a timer 1 time-base counter value - * update (timer 1 current value will be stored in registers above) + +/* TIMG_T1_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Write any value will trigger + * a timer 1 time-base counter value update + * (timer 1 current value will be stored in registers above). */ #define TIMG_T1_UPDATE 0xFFFFFFFF @@ -328,9 +381,11 @@ #define TIMG_T1_UPDATE_S 0 #define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0034) -/* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; - *description: Timer 1 time-base counter value lower 32 bits that will - *trigger the alarm + +/* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Timer 1 time-base counter value lower 32 bits that will + * trigger the alarm */ #define TIMG_T1_ALARM_LO 0xFFFFFFFF @@ -339,9 +394,11 @@ #define TIMG_T1_ALARM_LO_S 0 #define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0038) -/* TIMG_T1_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * description: Timer 1 time-base counter value higher 32 bits that will - * trigger the alarm + +/* TIMG_T1_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Timer 1 time-base counter value higher 32 bits that will + * trigger the alarm. */ #define TIMG_T1_ALARM_HI 0xFFFFFFFF @@ -350,9 +407,11 @@ #define TIMG_T1_ALARM_HI_S 0 #define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x003c) -/* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * description: Lower 32 bits of the value that will load into - * timer 1 time-base counter + +/* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Lower 32 bits of the value that will load into + * timer 1 time-base counter. */ #define TIMG_T1_LOAD_LO 0xFFFFFFFF @@ -361,9 +420,11 @@ #define TIMG_T1_LOAD_LO_S 0 #define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0040) -/* TIMG_T1_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * description: higher 32 bits of the value that will load into timer 1 - * time-base counter + +/* TIMG_T1_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: higher 32 bits of the value that will load into timer 1 + * time-base counter. */ #define TIMG_T1_LOAD_HI 0xFFFFFFFF @@ -372,8 +433,11 @@ #define TIMG_T1_LOAD_HI_S 0 #define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0044) -/* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; - * description: Write any value will trigger timer 1 time-base counter reload + +/* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Write any value will trigger + * timer 1 time-base counter reload. */ #define TIMG_T1_LOAD 0xFFFFFFFF @@ -382,68 +446,81 @@ #define TIMG_T1_LOAD_S 0 #define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048) -/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; - * description: When set SWDT is enabled - */ + +/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +/* Description: When set SWDT is enabled. */ #define TIMG_WDT_EN (BIT(31)) #define TIMG_WDT_EN_M (BIT(31)) #define TIMG_WDT_EN_V 0x1 #define TIMG_WDT_EN_S 31 -/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 1'd0 ; - * description: Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: - * reset system + +/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 1'd0 ; */ + +/* Description: Stage 0 configuration. + * 0: off 1: interrupt 2: reset CPU 3: reset system */ #define TIMG_WDT_STG0 0x00000003 #define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S)) #define TIMG_WDT_STG0_V 0x3 #define TIMG_WDT_STG0_S 29 -/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 1'd0 ; - * description: Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: - * reset system + +/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 1'd0 ; */ + +/* Description: Stage 1 configuration. + * 0: off 1: interrupt 2: reset CPU 3: reset system */ #define TIMG_WDT_STG1 0x00000003 #define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S)) #define TIMG_WDT_STG1_V 0x3 #define TIMG_WDT_STG1_S 27 -/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 1'd0 ; - * description: Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: - * reset system + +/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 1'd0 ; */ + +/* Description: Stage 2 configuration. + * 0: off 1: interrupt 2: reset CPU 3: reset system */ #define TIMG_WDT_STG2 0x00000003 #define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S)) #define TIMG_WDT_STG2_V 0x3 #define TIMG_WDT_STG2_S 25 -/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 1'd0 ; - * description: Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: - * reset system + +/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 1'd0 ; */ + +/* Description: Stage 3 configuration. + * 0: off 1: interrupt 2: reset CPU 3: reset system */ #define TIMG_WDT_STG3 0x00000003 #define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S)) #define TIMG_WDT_STG3_V 0x3 #define TIMG_WDT_STG3_S 23 -/* TIMG_WDT_EDGE_INT_EN : R/W ;bitpos:[22] ;default: 1'h0 ; - * description: When set edge type interrupt generation is enabled - */ + +/* TIMG_WDT_EDGE_INT_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */ + +/* Description: When set edge type interrupt generation is enabled. */ #define TIMG_WDT_EDGE_INT_EN (BIT(22)) #define TIMG_WDT_EDGE_INT_EN_M (BIT(22)) #define TIMG_WDT_EDGE_INT_EN_V 0x1 #define TIMG_WDT_EDGE_INT_EN_S 22 -/* TIMG_WDT_LEVEL_INT_EN : R/W ;bitpos:[21] ;default: 1'h0 ; - * description: When set level type interrupt generation is enabled - */ + +/* TIMG_WDT_LEVEL_INT_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */ + +/* Description: When set level type interrupt generation is enabled. */ #define TIMG_WDT_LEVEL_INT_EN (BIT(21)) #define TIMG_WDT_LEVEL_INT_EN_M (BIT(21)) #define TIMG_WDT_LEVEL_INT_EN_V 0x1 #define TIMG_WDT_LEVEL_INT_EN_S 21 -/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; - * description: length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns + +/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */ + +/* Description: length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns * 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us */ @@ -451,18 +528,22 @@ #define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S)) #define TIMG_WDT_CPU_RESET_LENGTH_V 0x7 #define TIMG_WDT_CPU_RESET_LENGTH_S 18 -/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; - * description: length of system reset selection. 0: 100ns 1: 200ns 2: 300ns - * 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us + +/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */ + +/* Description: length of system reset selection. + * 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us + * 7: 3.2us */ #define TIMG_WDT_SYS_RESET_LENGTH 0x00000007 #define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S)) #define TIMG_WDT_SYS_RESET_LENGTH_V 0x7 #define TIMG_WDT_SYS_RESET_LENGTH_S 15 -/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; - * description: When set flash boot protection is enabled - */ + +/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ + +/* Description: When set flash boot protection is enabled. */ #define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) #define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14)) @@ -470,9 +551,11 @@ #define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 #define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c) -/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; - * description: SWDT clock prescale value. Period = 12.5ns * value stored in - * this register + +/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */ + +/* Description: SWDT clock prescale value. Period = 12.5ns * value + * stored in this register. */ #define TIMG_WDT_CLK_PRESCALE 0x0000FFFF @@ -481,9 +564,10 @@ #define TIMG_WDT_CLK_PRESCALE_S 16 #define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050) -/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; - *description: Stage 0 timeout value in SWDT clock cycles - */ + +/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */ + +/* Description: Stage 0 timeout value in SWDT clock cycles. */ #define TIMG_WDT_STG0_HOLD 0xFFFFFFFF #define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S)) @@ -491,9 +575,10 @@ #define TIMG_WDT_STG0_HOLD_S 0 #define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054) -/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; - * description: Stage 1 timeout value in SWDT clock cycles - */ + +/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */ + +/* Description: Stage 1 timeout value in SWDT clock cycles. */ #define TIMG_WDT_STG1_HOLD 0xFFFFFFFF #define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S)) @@ -501,9 +586,10 @@ #define TIMG_WDT_STG1_HOLD_S 0 #define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058) -/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; - *description: Stage 2 timeout value in SWDT clock cycles - */ + +/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ + +/* Description: Stage 2 timeout value in SWDT clock cycles */ #define TIMG_WDT_STG2_HOLD 0xFFFFFFFF #define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S)) @@ -511,9 +597,10 @@ #define TIMG_WDT_STG2_HOLD_S 0 #define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c) -/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; - * description: Stage 3 timeout value in SWDT clock cycles - */ + +/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ + +/* Description: Stage 3 timeout value in SWDT clock cycles. */ #define TIMG_WDT_STG3_HOLD 0xFFFFFFFF #define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S)) @@ -521,9 +608,10 @@ #define TIMG_WDT_STG3_HOLD_S 0 #define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060) -/* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; - * description: Write any value will feed SWDT - */ + +/* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: Write any value will feed SWDT. */ #define TIMG_WDT_FEED 0xFFFFFFFF #define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S)) @@ -531,8 +619,10 @@ #define TIMG_WDT_FEED_S 0 #define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064) -/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; - *description: If change its value from default then write + +/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ + +/* Description: If change its value from default then write * protection is on. */ @@ -542,32 +632,34 @@ #define TIMG_WDT_WKEY_S 0 #define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) -/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; - * description: - */ + +/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +/* Description: */ #define TIMG_RTC_CALI_START (BIT(31)) #define TIMG_RTC_CALI_START_M (BIT(31)) #define TIMG_RTC_CALI_START_V 0x1 #define TIMG_RTC_CALI_START_S 31 -/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; - * description: - */ +/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */ + +/* Description: */ #define TIMG_RTC_CALI_RDY (BIT(15)) #define TIMG_RTC_CALI_RDY_M (BIT(15)) #define TIMG_RTC_CALI_RDY_V 0x1 #define TIMG_RTC_CALI_RDY_S 15 -/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; - * description: - */ + +/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ + +/* Description: */ #define TIMG_RTC_CALI_CLK_SEL 0x00000003 -/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; - * description: - */ +/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */ + +/* Description: */ #define TIMG_RTC_CALI_START_CYCLING (BIT(12)) #define TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) @@ -575,85 +667,97 @@ #define TIMG_RTC_CALI_START_CYCLING_S 12 #define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c) -/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; - * description: - */ + +/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */ + +/* Description: */ #define TIMG_LACTCONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0070) -/* TIMG_LACT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; - * description: - */ + +/* TIMG_LACT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +/* Description: */ + #define TIMG_LACT_EN (BIT(31)) #define TIMG_LACT_EN_M (BIT(31)) #define TIMG_LACT_EN_V 0x1 #define TIMG_LACT_EN_S 31 -/* TIMG_LACT_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; - * description: - */ + +/* TIMG_LACT_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ + +/* Description: */ #define TIMG_LACT_INCREASE (BIT(30)) #define TIMG_LACT_INCREASE_M (BIT(30)) #define TIMG_LACT_INCREASE_V 0x1 #define TIMG_LACT_INCREASE_S 30 -/* TIMG_LACT_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; - * description: - */ + +/* TIMG_LACT_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ + +/* Description: */ #define TIMG_LACT_AUTORELOAD (BIT(29)) #define TIMG_LACT_AUTORELOAD_M (BIT(29)) #define TIMG_LACT_AUTORELOAD_V 0x1 #define TIMG_LACT_AUTORELOAD_S 29 -/* TIMG_LACT_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; - *description: - */ + +/* TIMG_LACT_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ + +/* Description: */ #define TIMG_LACT_DIVIDER 0x0000FFFF #define TIMG_LACT_DIVIDER_M ((TIMG_LACT_DIVIDER_V)<<(TIMG_LACT_DIVIDER_S)) #define TIMG_LACT_DIVIDER_V 0xFFFF #define TIMG_LACT_DIVIDER_S 13 -/* TIMG_LACT_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; - * description: - */ + +/* TIMG_LACT_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ + +/* Description: */ #define TIMG_LACT_EDGE_INT_EN (BIT(12)) #define TIMG_LACT_EDGE_INT_EN_M (BIT(12)) #define TIMG_LACT_EDGE_INT_EN_V 0x1 #define TIMG_LACT_EDGE_INT_EN_S 12 -/* TIMG_LACT_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; - * description: - */ + +/* TIMG_LACT_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */ + +/* Description: */ #define TIMG_LACT_LEVEL_INT_EN (BIT(11)) #define TIMG_LACT_LEVEL_INT_EN_M (BIT(11)) #define TIMG_LACT_LEVEL_INT_EN_V 0x1 #define TIMG_LACT_LEVEL_INT_EN_S 11 -/* TIMG_LACT_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; - * description: - */ + +/* TIMG_LACT_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +/* Description: */ #define TIMG_LACT_ALARM_EN (BIT(10)) #define TIMG_LACT_ALARM_EN_M (BIT(10)) #define TIMG_LACT_ALARM_EN_V 0x1 #define TIMG_LACT_ALARM_EN_S 10 -/* TIMG_LACT_LAC_EN : R/W ;bitpos:[9] ;default: 1'h1 ; - * description: - */ + +/* TIMG_LACT_LAC_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */ + +/* Description: */ #define TIMG_LACT_LAC_EN (BIT(9)) #define TIMG_LACT_LAC_EN_M (BIT(9)) #define TIMG_LACT_LAC_EN_V 0x1 #define TIMG_LACT_LAC_EN_S 9 -/* TIMG_LACT_CPST_EN : R/W ;bitpos:[8] ;default: 1'h1 ; - * description: - */ + +/* TIMG_LACT_CPST_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */ + +/* Description: */ #define TIMG_LACT_CPST_EN (BIT(8)) #define TIMG_LACT_CPST_EN_M (BIT(8)) #define TIMG_LACT_CPST_EN_V 0x1 #define TIMG_LACT_CPST_EN_S 8 -/* TIMG_LACT_RTC_ONLY : R/W ;bitpos:[7] ;default: 1'h0 ; - * description: - */ + +/* TIMG_LACT_RTC_ONLY : R/W ;bitpos:[7] ;default: 1'h0 ; */ + +/* Description: */ #define TIMG_LACT_RTC_ONLY (BIT(7)) #define TIMG_LACT_RTC_ONLY_M (BIT(7)) @@ -661,9 +765,10 @@ #define TIMG_LACT_RTC_ONLY_S 7 #define TIMG_LACTRTC_REG(i) (REG_TIMG_BASE(i) + 0x0074) -/* TIMG_LACT_RTC_STEP_LEN : R/W ;bitpos:[31:6] ;default: 26'h0 ; - * description: - */ + +/* TIMG_LACT_RTC_STEP_LEN : R/W ;bitpos:[31:6] ;default: 26'h0 ; */ + +/* Description: */ #define TIMG_LACT_RTC_STEP_LEN 0x03FFFFFF #define TIMG_LACT_RTC_STEP_LEN_M ((TIMG_LACT_RTC_STEP_LEN_V)<<(TIMG_LACT_RTC_STEP_LEN_S)) @@ -671,9 +776,10 @@ #define TIMG_LACT_RTC_STEP_LEN_S 6 #define TIMG_LACTLO_REG(i) (REG_TIMG_BASE(i) + 0x0078) -/* TIMG_LACT_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; - * description: - */ + +/* TIMG_LACT_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: */ #define TIMG_LACT_LO 0xFFFFFFFF #define TIMG_LACT_LO_M ((TIMG_LACT_LO_V)<<(TIMG_LACT_LO_S)) @@ -681,9 +787,10 @@ #define TIMG_LACT_LO_S 0 #define TIMG_LACTHI_REG(i) (REG_TIMG_BASE(i) + 0x007c) -/* TIMG_LACT_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; - * description: - */ + +/* TIMG_LACT_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: */ #define TIMG_LACT_HI 0xFFFFFFFF #define TIMG_LACT_HI_M ((TIMG_LACT_HI_V)<<(TIMG_LACT_HI_S)) @@ -691,9 +798,10 @@ #define TIMG_LACT_HI_S 0 #define TIMG_LACTUPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0080) -/* TIMG_LACT_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; - * description: - */ + +/* TIMG_LACT_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: */ #define TIMG_LACT_UPDATE 0xFFFFFFFF #define TIMG_LACT_UPDATE_M ((TIMG_LACT_UPDATE_V)<<(TIMG_LACT_UPDATE_S)) @@ -701,9 +809,10 @@ #define TIMG_LACT_UPDATE_S 0 #define TIMG_LACTALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0084) -/* TIMG_LACT_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * description: - */ + +/* TIMG_LACT_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: */ #define TIMG_LACT_ALARM_LO 0xFFFFFFFF #define TIMG_LACT_ALARM_LO_M ((TIMG_LACT_ALARM_LO_V)<<(TIMG_LACT_ALARM_LO_S)) @@ -711,9 +820,10 @@ #define TIMG_LACT_ALARM_LO_S 0 #define TIMG_LACTALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0088) -/* TIMG_LACT_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * description: - */ + +/* TIMG_LACT_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: */ #define TIMG_LACT_ALARM_HI 0xFFFFFFFF #define TIMG_LACT_ALARM_HI_M ((TIMG_LACT_ALARM_HI_V)<<(TIMG_LACT_ALARM_HI_S)) @@ -721,9 +831,10 @@ #define TIMG_LACT_ALARM_HI_S 0 #define TIMG_LACTLOADLO_REG(i) (REG_TIMG_BASE(i) + 0x008c) -/* TIMG_LACT_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * description: - */ + +/* TIMG_LACT_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: */ #define TIMG_LACT_LOAD_LO 0xFFFFFFFF #define TIMG_LACT_LOAD_LO_M ((TIMG_LACT_LOAD_LO_V)<<(TIMG_LACT_LOAD_LO_S)) @@ -731,9 +842,10 @@ #define TIMG_LACT_LOAD_LO_S 0 #define TIMG_LACTLOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0090) -/* TIMG_LACT_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * description: - */ + +/* TIMG_LACT_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: */ #define TIMG_LACT_LOAD_HI 0xFFFFFFFF #define TIMG_LACT_LOAD_HI_M ((TIMG_LACT_LOAD_HI_V)<<(TIMG_LACT_LOAD_HI_S)) @@ -741,9 +853,10 @@ #define TIMG_LACT_LOAD_HI_S 0 #define TIMG_LACTLOAD_REG(i) (REG_TIMG_BASE(i) + 0x0094) -/* TIMG_LACT_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; - * description: - */ + +/* TIMG_LACT_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ + +/* Description: */ #define TIMG_LACT_LOAD 0xFFFFFFFF #define TIMG_LACT_LOAD_M ((TIMG_LACT_LOAD_V)<<(TIMG_LACT_LOAD_S)) @@ -751,33 +864,37 @@ #define TIMG_LACT_LOAD_S 0 #define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0098) -/* TIMG_LACT_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; - * description: - */ + +/* TIMG_LACT_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */ + +/* Description: */ #define TIMG_LACT_INT_ENA (BIT(3)) #define TIMG_LACT_INT_ENA_M (BIT(3)) #define TIMG_LACT_INT_ENA_V 0x1 #define TIMG_LACT_INT_ENA_S 3 -/* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; - * description: Interrupt when an interrupt stage timeout - */ + +/* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +/* Description: Interrupt when an interrupt stage timeout */ #define TIMG_WDT_INT_ENA (BIT(2)) #define TIMG_WDT_INT_ENA_M (BIT(2)) #define TIMG_WDT_INT_ENA_V 0x1 #define TIMG_WDT_INT_ENA_S 2 -/* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; - *description: interrupt when timer1 alarm - */ + +/* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ + +/* Description: interrupt when timer1 alarm */ #define TIMG_T1_INT_ENA (BIT(1)) #define TIMG_T1_INT_ENA_M (BIT(1)) #define TIMG_T1_INT_ENA_V 0x1 #define TIMG_T1_INT_ENA_S 1 -/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; - *description: interrupt when timer0 alarm - */ + +/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ + +/* Description: interrupt when timer0 alarm */ #define TIMG_T0_INT_ENA (BIT(0)) #define TIMG_T0_INT_ENA_M (BIT(0)) @@ -785,33 +902,37 @@ #define TIMG_T0_INT_ENA_S 0 #define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x009c) -/* TIMG_LACT_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; - *description: - */ + +/* TIMG_LACT_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */ + +/* Description: */ #define TIMG_LACT_INT_RAW (BIT(3)) #define TIMG_LACT_INT_RAW_M (BIT(3)) #define TIMG_LACT_INT_RAW_V 0x1 #define TIMG_LACT_INT_RAW_S 3 -/* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; - *description: Interrupt when an interrupt stage timeout - */ + +/* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */ + +/* Description: Interrupt when an interrupt stage timeout */ #define TIMG_WDT_INT_RAW (BIT(2)) #define TIMG_WDT_INT_RAW_M (BIT(2)) #define TIMG_WDT_INT_RAW_V 0x1 #define TIMG_WDT_INT_RAW_S 2 -/* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; - *description: interrupt when timer1 alarm - */ + +/* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ + +/* Description: Interrupt when timer1 alarm */ #define TIMG_T1_INT_RAW (BIT(1)) #define TIMG_T1_INT_RAW_M (BIT(1)) #define TIMG_T1_INT_RAW_V 0x1 #define TIMG_T1_INT_RAW_S 1 -/* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; - * description: interrupt when timer0 alarm - */ + +/* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ + +/* Description: Interrupt when timer0 alarm */ #define TIMG_T0_INT_RAW (BIT(0)) #define TIMG_T0_INT_RAW_M (BIT(0)) @@ -819,33 +940,37 @@ #define TIMG_T0_INT_RAW_S 0 #define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a0) -/* TIMG_LACT_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; - *description: - */ + +/* TIMG_LACT_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */ + +/* Description: */ #define TIMG_LACT_INT_ST (BIT(3)) #define TIMG_LACT_INT_ST_M (BIT(3)) #define TIMG_LACT_INT_ST_V 0x1 #define TIMG_LACT_INT_ST_S 3 -/* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; - * description: Interrupt when an interrupt stage timeout - */ + +/* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */ + +/* Description: Interrupt when an interrupt stage timeout */ #define TIMG_WDT_INT_ST (BIT(2)) #define TIMG_WDT_INT_ST_M (BIT(2)) #define TIMG_WDT_INT_ST_V 0x1 #define TIMG_WDT_INT_ST_S 2 -/* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; - * description: interrupt when timer1 alarm - */ + +/* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ + +/* Description: Interrupt when timer1 alarm */ #define TIMG_T1_INT_ST (BIT(1)) #define TIMG_T1_INT_ST_M (BIT(1)) #define TIMG_T1_INT_ST_V 0x1 #define TIMG_T1_INT_ST_S 1 -/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; - * description: interrupt when timer0 alarm - */ + +/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ + +/* Description: Interrupt when timer0 alarm */ #define TIMG_T0_INT_ST (BIT(0)) #define TIMG_T0_INT_ST_M (BIT(0)) @@ -853,33 +978,37 @@ #define TIMG_T0_INT_ST_S 0 #define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a4) -/* TIMG_LACT_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; - * description: - */ + +/* TIMG_LACT_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */ + +/* Description: */ #define TIMG_LACT_INT_CLR (BIT(3)) #define TIMG_LACT_INT_CLR_M (BIT(3)) #define TIMG_LACT_INT_CLR_V 0x1 #define TIMG_LACT_INT_CLR_S 3 -/* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; - *description: Interrupt when an interrupt stage timeout - */ + +/* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */ + +/* Description: Interrupt when an interrupt stage timeout */ #define TIMG_WDT_INT_CLR (BIT(2)) #define TIMG_WDT_INT_CLR_M (BIT(2)) #define TIMG_WDT_INT_CLR_V 0x1 #define TIMG_WDT_INT_CLR_S 2 -/* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; - *description: interrupt when timer1 alarm - */ + +/* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ + +/* Description: interrupt when timer1 alarm */ #define TIMG_T1_INT_CLR (BIT(1)) #define TIMG_T1_INT_CLR_M (BIT(1)) #define TIMG_T1_INT_CLR_V 0x1 #define TIMG_T1_INT_CLR_S 1 -/* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; - * description: interrupt when timer0 alarm - */ + +/* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ + +/* Description: Interrupt when timer0 alarm */ #define TIMG_T0_INT_CLR (BIT(0)) #define TIMG_T0_INT_CLR_M (BIT(0)) @@ -887,9 +1016,10 @@ #define TIMG_T0_INT_CLR_S 0 #define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8) -/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604290 ; - * description: Version of this regfile - */ + +/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604290 ; */ + +/* Description: Version of this regfile */ #define TIMG_NTIMERS_DATE 0x0FFFFFFF #define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S)) @@ -897,9 +1027,10 @@ #define TIMG_NTIMERS_DATE_S 0 #define TIMGCLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc) -/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; - *description: Force clock enable for this regfile - */ + +/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +/* Description: Force clock enable for this regfile */ #define TIMG_CLK_EN (BIT(31)) #define TIMG_CLK_EN_M (BIT(31))