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PIC32 start kit port builds successfully

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4037 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-10-10 22:40:59 +00:00
parent 6baab020a0
commit 797f84a9ed
3 changed files with 901 additions and 903 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

104
arch/mips/include/pic32mx/chip.h
View File

@ -67,7 +67,7 @@
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -97,7 +97,7 @@
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -127,7 +127,7 @@
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -154,10 +154,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -184,10 +183,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -214,10 +212,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -244,10 +241,9 @@
# define CHIP_NDMACH 0 /* No programmable DMA channels */
# define CHIP_NUSBDMACHAN 0
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -274,10 +270,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -304,10 +299,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -334,10 +328,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 0
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -364,10 +357,9 @@
# define CHIP_NDMACH 0 /* No programmable DMA channels */
# define CHIP_NUSBDMACHAN 2
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 1 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -394,10 +386,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 1 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -424,10 +415,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 1 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -454,10 +444,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 1 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -484,10 +473,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -514,10 +502,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -544,10 +531,9 @@
# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
# define CHIP_NUSBDMACHAN 2
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 2 /* 2 UARTS */
# define CHIP_UARTFIFOD 4
# define CHIP_UARTFIFOD 8 /* 4 level deep UART FIFOs */
# define CHIP_NSPI 2 /* 2 SPI interfaces */
# define CHIP_NI2C 2 /* 2 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -576,7 +562,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -605,7 +591,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -634,7 +620,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -663,7 +649,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -692,7 +678,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -721,7 +707,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -750,7 +736,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -779,7 +765,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -808,7 +794,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -837,7 +823,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -866,7 +852,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -895,7 +881,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -924,7 +910,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -953,7 +939,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -982,7 +968,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -1011,7 +997,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -1040,7 +1026,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -1069,7 +1055,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -1098,7 +1084,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -1127,7 +1113,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 0 /* No CAN interface */
@ -1156,7 +1142,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -1185,7 +1171,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 2 /* 2 CAN interfaces */
@ -1214,7 +1200,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 2 /* 2 CAN interfaces */
@ -1243,7 +1229,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# undef CHIP_TRACE /* No trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 3 /* 3 SPI interfaces */
# define CHIP_NI2C 4 /* 4 I2C interfaces */
# define CHIP_NCAN 2 /* 2 CAN interfaces */
@ -1272,7 +1258,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 1 /* 1 CAN interface */
@ -1301,7 +1287,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 2 /* 2 CAN interfaces */
@ -1330,7 +1316,7 @@
# undef CHIP_VRFSEL /* No comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 2 /* 2 CAN interfaces */
@ -1359,7 +1345,7 @@
# define CHIP_VRFSEL 1 /* Have comparator voltage reference selection */
# define CHIP_TRACE 1 /* Have trace capability */
# define CHIP_NUARTS 6 /* 6 UARTS */
# define CHIP_UARTFIFOD tbd
# define CHIP_UARTFIFOD 8 /* 8 level deep UART FIFOs */
# define CHIP_NSPI 4 /* 4 SPI interfaces */
# define CHIP_NI2C 5 /* 5 I2C interfaces */
# define CHIP_NCAN 2 /* 2 CAN interfaces */

1
arch/mips/src/pic32mx/pic32mx-config.h
View File

@ -551,7 +551,6 @@
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_PIC32MX_UART2)
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE

15
arch/mips/src/pic32mx/pic32mx-lowconsole.c
View File

@ -243,8 +243,21 @@ void pic32mx_uartconfigure(uintptr_t uart_base, uint32_t baudrate,
UART_MODE_RXINV | UART_MODE_WAKE | UART_MODE_LPBACK |
UART_MODE_UEN_MASK | UART_MODE_RTSMD | UART_MODE_IREN |
UART_MODE_SIDL | UART_MODE_ON);
/* Configure the FIFOs:
*
* RX: Interrupt at 6 of 8 (for 8-deep FIFO) or 3 o 4 (4-deep FIFO)
* TX: Interrupt on FIFO not full
* Invert transmit polarity.
*/
#ifdef UART_STA_URXISEL_RXB6
pic32mx_putreg(uart_base, PIC32MX_UART_STACLR_OFFSET,
UART_STA_UTXINV | UART_STA_UTXISEL_MASK | UART_STA_URXISEL_RXBF);
UART_STA_UTXINV | UART_STA_UTXISEL_TXBNF | UART_STA_URXISEL_RXB6);
#else
pic32mx_putreg(uart_base, PIC32MX_UART_STACLR_OFFSET,
UART_STA_UTXINV | UART_STA_UTXISEL_TXBNF | UART_STA_URXISEL_RXB3);
#endif
/* Configure the FIFO interrupts */