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Indent the define statement by two spaces

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follow the code style convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2023-05-20 06:32:34 +08:00 committed by Alan Carvalho de Assis
parent ae1fd83a46
commit 7990f90915
390 changed files with 4060 additions and 4063 deletions
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4
arch/arm/src/arm/arm_initialstate.c
View File

@ -141,9 +141,9 @@ void up_initial_state(struct tcb_s *tcb)
/* Enable or disable interrupts, based on user configuration */
# ifdef CONFIG_SUPPRESS_INTERRUPTS
#ifdef CONFIG_SUPPRESS_INTERRUPTS
cpsr |= PSR_I_BIT;
# endif
#endif
#ifdef CONFIG_ARM_THUMB
cpsr |= PSR_T_BIT;

8
arch/arm/src/armv6-m/arm_hardfault.c
View File

@ -39,15 +39,15 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_HARDFAULT_ALERT
# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define hfalert(x...)
# define hfalert(x...)
#endif
#ifdef CONFIG_DEBUG_HARDFAULT_INFO
# define hfinfo(format, ...) _info(format, ##__VA_ARGS__)
# define hfinfo(format, ...) _info(format, ##__VA_ARGS__)
#else
# define hfinfo(x...)
# define hfinfo(x...)
#endif
#define INSN_SVC0 0xdf00 /* insn: svc 0 */

26
arch/arm/src/armv6-m/arm_svcall.c
View File

@ -127,9 +127,9 @@ int arm_svcall(int irq, void *context, void *arg)
*/
#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# endif
# endif
{
svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
@ -138,13 +138,13 @@ int arm_svcall(int irq, void *context, void *arg)
svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
# ifdef CONFIG_BUILD_PROTECTED
# ifdef CONFIG_BUILD_PROTECTED
svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]);
# else
# else
svcinfo(" PSR: %08x PRIMASK: %08x\n",
regs[REG_XPSR], regs[REG_PRIMASK]);
# endif
# endif
}
#endif
@ -429,11 +429,11 @@ int arm_svcall(int irq, void *context, void *arg)
*/
#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# else
# else
if (regs != CURRENT_REGS)
# endif
# endif
{
svcinfo("SVCall Return:\n");
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
@ -446,21 +446,21 @@ int arm_svcall(int irq, void *context, void *arg)
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
#ifdef CONFIG_BUILD_PROTECTED
# ifdef CONFIG_BUILD_PROTECTED
svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
CURRENT_REGS[REG_EXC_RETURN]);
#else
# else
svcinfo(" PSR: %08x PRIMASK: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
#endif
# endif
}
# ifdef CONFIG_DEBUG_SVCALL
# ifdef CONFIG_DEBUG_SVCALL
else
{
svcinfo("SVCall Return: %d\n", regs[REG_R0]);
}
# endif
# endif
#endif
return OK;

4
arch/arm/src/armv7-m/arm_busfault.c
View File

@ -39,9 +39,9 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_BUSFAULT
# define bfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define bfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define bfalert(x...)
# define bfalert(x...)
#endif
/****************************************************************************

8
arch/arm/src/armv7-m/arm_hardfault.c
View File

@ -45,15 +45,15 @@
*/
#ifdef CONFIG_DEBUG_HARDFAULT_ALERT
# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define hfalert(x...)
# define hfalert(x...)
#endif
#ifdef CONFIG_DEBUG_HARDFAULT_INFO
# define hfinfo(format, ...) _info(format, ##__VA_ARGS__)
# define hfinfo(format, ...) _info(format, ##__VA_ARGS__)
#else
# define hfinfo(x...)
# define hfinfo(x...)
#endif
#define INSN_SVC0 0xdf00 /* insn: svc 0 */

4
arch/arm/src/armv7-m/arm_memfault.c
View File

@ -38,9 +38,9 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_MEMFAULT
# define mfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define mfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define mfalert(x...)
# define mfalert(x...)
#endif
/****************************************************************************

26
arch/arm/src/armv7-m/arm_svcall.c
View File

@ -135,9 +135,9 @@ int arm_svcall(int irq, void *context, void *arg)
*/
#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# endif
# endif
{
svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
@ -146,12 +146,12 @@ int arm_svcall(int irq, void *context, void *arg)
svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
# ifdef REG_EXC_RETURN
# ifdef REG_EXC_RETURN
svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
regs[REG_XPSR], regs[REG_EXC_RETURN]);
# else
# else
svcinfo(" PSR: %08x\n", regs[REG_XPSR]);
# endif
# endif
}
#endif
@ -437,11 +437,11 @@ int arm_svcall(int irq, void *context, void *arg)
*/
#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# else
# else
if (regs != CURRENT_REGS)
# endif
# endif
{
svcinfo("SVCall Return:\n");
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
@ -454,19 +454,19 @@ int arm_svcall(int irq, void *context, void *arg)
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
# ifdef REG_EXC_RETURN
# ifdef REG_EXC_RETURN
svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]);
# else
# else
svcinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]);
# endif
# endif
}
# ifdef CONFIG_DEBUG_SVCALL
# ifdef CONFIG_DEBUG_SVCALL
else
{
svcinfo("SVCall Return: %d\n", regs[REG_R0]);
}
# endif
# endif
#endif
return OK;

4
arch/arm/src/armv7-m/arm_usagefault.c
View File

@ -39,9 +39,9 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_USAGEFAULT
# define ufalert(format, ...) _alert(format, ##__VA_ARGS__)
# define ufalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define ufalert(x...)
# define ufalert(x...)
#endif
/****************************************************************************

4
arch/arm/src/armv8-m/arm_busfault.c
View File

@ -39,9 +39,9 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_BUSFAULT
# define bfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define bfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define bfalert(x...)
# define bfalert(x...)
#endif
/****************************************************************************

8
arch/arm/src/armv8-m/arm_hardfault.c
View File

@ -45,15 +45,15 @@
*/
#ifdef CONFIG_DEBUG_HARDFAULT_ALERT
# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define hfalert(x...)
# define hfalert(x...)
#endif
#ifdef CONFIG_DEBUG_HARDFAULT_INFO
# define hfinfo(format, ...) _info(format, ##__VA_ARGS__)
# define hfinfo(format, ...) _info(format, ##__VA_ARGS__)
#else
# define hfinfo(x...)
# define hfinfo(x...)
#endif
#define INSN_SVC0 0xdf00 /* insn: svc 0 */

4
arch/arm/src/armv8-m/arm_memfault.c
View File

@ -38,9 +38,9 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_MEMFAULT
# define mfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define mfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define mfalert(x...)
# define mfalert(x...)
#endif
/****************************************************************************

26
arch/arm/src/armv8-m/arm_svcall.c
View File

@ -134,9 +134,9 @@ int arm_svcall(int irq, void *context, void *arg)
*/
#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# endif
# endif
{
svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
@ -145,12 +145,12 @@ int arm_svcall(int irq, void *context, void *arg)
svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
# ifdef REG_EXC_RETURN
# ifdef REG_EXC_RETURN
svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
regs[REG_XPSR], regs[REG_EXC_RETURN]);
# else
# else
svcinfo(" PSR: %08x\n", regs[REG_XPSR]);
# endif
# endif
}
#endif
@ -437,11 +437,11 @@ int arm_svcall(int irq, void *context, void *arg)
*/
#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# else
# else
if (regs != CURRENT_REGS)
# endif
# endif
{
svcinfo("SVCall Return:\n");
svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
@ -454,19 +454,19 @@ int arm_svcall(int irq, void *context, void *arg)
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
# ifdef REG_EXC_RETURN
# ifdef REG_EXC_RETURN
svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]);
# else
# else
svcinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]);
# endif
# endif
}
# ifdef CONFIG_DEBUG_SVCALL
# ifdef CONFIG_DEBUG_SVCALL
else
{
svcinfo("SVCall Return: %d\n", regs[REG_R0]);
}
# endif
# endif
#endif
return OK;

4
arch/arm/src/armv8-m/arm_usagefault.c
View File

@ -39,9 +39,9 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_USAGEFAULT
# define ufalert(format, ...) _alert(format, ##__VA_ARGS__)
# define ufalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define ufalert(x...)
# define ufalert(x...)
#endif
/****************************************************************************

6
arch/arm/src/c5471/c5471_ethernet.c
View File

@ -80,7 +80,7 @@
*/
#ifndef CONFIG_C5471_NET_NINTERFACES
# define CONFIG_C5471_NET_NINTERFACES 1
# define CONFIG_C5471_NET_NINTERFACES 1
#endif
/* CONFIG_C5471_NET_STATS will enabled collection of driver statistics.
@ -99,7 +99,7 @@
# undef CONFIG_C5471_AUTONEGOTIATION
# undef CONFIG_C5471_BASET100
#else
# define CONFIG_C5471_AUTONEGOTIATION 1
# define CONFIG_C5471_AUTONEGOTIATION 1
# undef CONFIG_C5471_BASET100
# undef CONFIG_C5471_BASET10
#endif
@ -435,7 +435,7 @@ static inline void c5471_dumpbuffer(const char *msg, const uint8_t *buffer,
ninfodumpbuffer(msg, buffer, nbytes);
}
#else
# define c5471_dumpbuffer(msg, buffer,nbytes)
# define c5471_dumpbuffer(msg, buffer,nbytes)
#endif
/****************************************************************************

14
arch/arm/src/c5471/c5471_serial.c
View File

@ -48,7 +48,7 @@
#define BASE_BAUD 115200
#if defined(CONFIG_UART_IRDA_HWFLOWCONTROL) || defined(CONFIG_UART_MODEM_HWFLOWCONTROL)
# define CONFIG_UART_HWFLOWCONTROL
# define CONFIG_UART_HWFLOWCONTROL
#endif
/****************************************************************************
@ -203,13 +203,13 @@ static uart_dev_t g_modemport =
/* Now, which one with be tty0/console and which tty1? */
#ifdef CONFIG_SERIAL_IRDA_CONSOLE
# define CONSOLE_DEV g_irdaport
# define TTYS0_DEV g_irdaport
# define TTYS1_DEV g_modemport
# define CONSOLE_DEV g_irdaport
# define TTYS0_DEV g_irdaport
# define TTYS1_DEV g_modemport
#else
# define CONSOLE_DEV g_modemport
# define TTYS0_DEV g_modemport
# define TTYS1_DEV g_irdaport
# define CONSOLE_DEV g_modemport
# define TTYS0_DEV g_modemport
# define TTYS1_DEV g_irdaport
#endif
/****************************************************************************

12
arch/arm/src/common/arm_internal.h
View File

@ -356,7 +356,7 @@ uint32_t *arm_doirq(int irq, uint32_t *regs);
void arm_pginitialize(void);
uint32_t *arm_va2pte(uintptr_t vaddr);
#else /* CONFIG_PAGING */
# define arm_pginitialize()
# define arm_pginitialize()
#endif /* CONFIG_PAGING */
/* Exception Handlers */
@ -382,7 +382,7 @@ void arm_pginitialize(void);
uint32_t *arm_va2pte(uintptr_t vaddr);
void arm_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr);
#else /* CONFIG_PAGING */
# define arm_pginitialize()
# define arm_pginitialize()
void arm_dataabort(uint32_t *regs);
#endif /* CONFIG_PAGING */
@ -442,7 +442,7 @@ void arm_l2ccinitialize(void);
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void);
#else
# define arm_addregion()
# define arm_addregion()
#endif
/* Networking ***************************************************************/
@ -461,7 +461,7 @@ void arm_addregion(void);
#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT)
void arm_netinitialize(void);
#else
# define arm_netinitialize()
# define arm_netinitialize()
#endif
/* USB **********************************************************************/
@ -470,8 +470,8 @@ void arm_netinitialize(void);
void arm_usbinitialize(void);
void arm_usbuninitialize(void);
#else
# define arm_usbinitialize()
# define arm_usbuninitialize()
# define arm_usbinitialize()
# define arm_usbuninitialize()
#endif
/* Debug ********************************************************************/

12
arch/arm/src/dm320/dm320_serial.c
View File

@ -171,13 +171,13 @@ static uart_dev_t g_uart1port =
/* Now, which one with be tty0/console and which tty1? */
#ifdef CONFIG_SERIAL_IRDA_CONSOLE
# define CONSOLE_DEV g_uart1port
# define TTYS0_DEV g_uart1port
# define TTYS1_DEV g_uart0port
# define CONSOLE_DEV g_uart1port
# define TTYS0_DEV g_uart1port
# define TTYS1_DEV g_uart0port
#else
# define CONSOLE_DEV g_uart0port
# define TTYS0_DEV g_uart0port
# define TTYS1_DEV g_uart1port
# define CONSOLE_DEV g_uart0port
# define TTYS0_DEV g_uart0port
# define TTYS1_DEV g_uart1port
#endif
/****************************************************************************

8
arch/arm/src/dm320/dm320_timer.h
View File

@ -60,9 +60,9 @@
#define DM320_TMR_MODE_TEST_MASK 0x00fc /* Bits 7:2=Test */
#define DM320_TMR_MODE_MODE_MASK 0x0003 /* Bits 1:0=timer mode */
# define DM320_TMR_MODE_STOP 0x0000 /* Stop Timer */
# define DM320_TMR_MODE_ONESHOT 0x0001 /* Start one-shot timer */
# define DM320_TMR_MODE_FREERUN 0x0002 /* Start free-running timer */
# define DM320_TMR_MODE_STOP 0x0000 /* Stop Timer */
# define DM320_TMR_MODE_ONESHOT 0x0001 /* Start one-shot timer */
# define DM320_TMR_MODE_FREERUN 0x0002 /* Start free-running timer */
/* Timer 0,1,2,3 Clock Select Register Bits: */
@ -76,7 +76,7 @@
#define DM320_TMR_TMTRG_MASK 0x0001 /* Bit 0=One short trigger */
# define DM320_TMR_TMTRG_START 0x0001 /* 1 starts one shot timer */
# define DM320_TMR_TMTRG_START 0x0001 /* 1 starts one shot timer */
/* Timer 0,1,2,3 Timer Counter Register Bits: */

12
arch/arm/src/dm320/dm320_usbdev.c
View File

@ -261,12 +261,12 @@ static void dm320_putreg8(uint8_t val, uint32_t addr);
static void dm320_putreg16(uint16_t val, uint32_t addr);
static void dm320_putreg32(uint32_t val, uint32_t addr);
#else
# define dm320_getreg8(addr) getreg8(addr)
# define dm320_getreg16(addr) getreg16(addr)
# define dm320_getreg32(addr) getreg32(addr)
# define dm320_putreg8(val,addr) putreg8(val,addr)
# define dm320_putreg16(val,addr) putreg16(val,addr)
# define dm320_putreg32(val,addr) putreg32(val,addr)
# define dm320_getreg8(addr) getreg8(addr)
# define dm320_getreg16(addr) getreg16(addr)
# define dm320_getreg32(addr) getreg32(addr)
# define dm320_putreg8(val,addr) putreg8(val,addr)
# define dm320_putreg16(val,addr) putreg16(val,addr)
# define dm320_putreg32(val,addr) putreg32(val,addr)
#endif
/* Request queue operations *************************************************/

4
arch/arm/src/efm32/efm32_usbdev.c
View File

@ -465,8 +465,8 @@ struct efm32_usbdev_s
static uint32_t efm32_getreg(uint32_t addr);
static void efm32_putreg(uint32_t val, uint32_t addr);
#else
# define efm32_getreg(addr) getreg32(addr)
# define efm32_putreg(val,addr) putreg32(val,addr)
# define efm32_getreg(addr) getreg32(addr)
# define efm32_putreg(val,addr) putreg32(val,addr)
#endif
/* Request queue operations *************************************************/

4
arch/arm/src/efm32/efm32_usbhost.c
View File

@ -284,8 +284,8 @@ static void efm32_checkreg(uint32_t addr, uint32_t val, bool iswrite);
static uint32_t efm32_getreg(uint32_t addr);
static void efm32_putreg(uint32_t addr, uint32_t value);
#else
# define efm32_getreg(addr) getreg32(addr)
# define efm32_putreg(addr,val) putreg32(val,addr)
# define efm32_getreg(addr) getreg32(addr)
# define efm32_putreg(addr,val) putreg32(val,addr)
#endif
static inline void efm32_modifyreg(uint32_t addr, uint32_t clrbits,

2
arch/arm/src/efm32/hardware/efm32gg_memorymap.h
View File

@ -68,7 +68,7 @@
#define EFM32_FLASH_MEM_BASE 0x00000000 /* FLASH base address */
# define EFM32_FLASH_MEM_BITS 0x00000028 /* FLASH used bits */
#define EFM32_RAM_CODE_MEM_BASE 0x10000000 /* RAM_CODE base address */
# define EFM32_RAM_CODE_MEM_BITS 0x00000014 /* RAM_CODE used bits */
# define EFM32_RAM_CODE_MEM_BITS 0x00000014 /* RAM_CODE used bits */
#define EFM32_RAM_MEM_BASE 0x20000000 /* RAM base address */
# define EFM32_RAM_MEM_BITS 0x00000018 /* RAM used bits */
#define EFM32_PER_MEM_BASE 0x40000000 /* PER base address */

14
arch/arm/src/gd32f4/gd32f4xx_enet.c
View File

@ -3295,7 +3295,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv)
* CK_PLLP clock (through a configurable prescaler) on PC9 pin."
*/
# if defined(CONFIG_GD32F4_MII_CKOUT0)
# if defined(CONFIG_GD32F4_MII_CKOUT0)
/* Configure CKOUT0 to drive the PHY. Board logic must provide
* CKOUT0 clocking info.
*/
@ -3303,14 +3303,14 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv)
gd32_gpio_config(GPIO_CKOUT0);
gd32_rcu_ckout0_config(BOARD_CFG_CKOUT0_SOURCE, BOARD_CFG_CKOUT0_DIVIDER);
# elif defined(CONFIG_GD32F4_MII_CKOUT1)
# elif defined(CONFIG_GD32F4_MII_CKOUT1)
/* Configure CKOUT1 to drive the PHY. Board logic must provide
* CKOUT1 clocking info.
*/
gd32_gpio_config(GPIO_CKOUT1);
gd32_rcu_ckout1_config(BOARD_CFG_CKOUT1_SOURCE, BOARD_CFG_CKOUT1_DIVIDER);
# endif
# endif
/* MII interface pins (17):
*
@ -3351,7 +3351,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv)
* CK_PLLP clock (through a configurable prescaler) on PC9 pin."
*/
# if defined(CONFIG_GD32F4_RMII_CKOUT0)
# if defined(CONFIG_GD32F4_RMII_CKOUT0)
/* Configure CKOUT0 to drive the PHY. Board logic must provide
* CKOUT0 clocking info.
*/
@ -3359,7 +3359,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv)
gd32_gpio_config(GPIO_CKOUT0);
gd32_rcu_ckout0_config(BOARD_CFG_CKOUT0_SOURCE, BOARD_CFG_CKOUT0_DIV);
# elif defined(CONFIG_GD32F4_RMII_CKOUT1)
# elif defined(CONFIG_GD32F4_RMII_CKOUT1)
/* Configure CKOUT1 to drive the PHY. Board logic must provide
* CKOUT1 clocking info.
*/
@ -3367,7 +3367,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv)
gd32_gpio_config(GPIO_CKOUT1);
gd32_rcu_ckout1_config(BOARD_CFG_CKOUT1_SOURCE, BOARD_CFG_CKOUT1_DIVIDER);
# endif
# endif
/* RMII interface pins (7):
*
@ -3383,7 +3383,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv)
gd32_gpio_config(GPIO_ENET_RMII_TXD0);
gd32_gpio_config(GPIO_ENET_RMII_TXD1);
#endif
# endif
#endif
#ifdef CONFIG_GD32F4_ENET_PTP

16
arch/arm/src/gd32f4/gd32f4xx_i2c.c
View File

@ -130,14 +130,14 @@
# error "Now I2C DMA has not ready"
# if defined(CONFIG_I2C_DMAPRIO)
# if (CONFIG_I2C_DMAPRIO & ~DMA_CHXCTL_PRIO_MASK) != 0
# error "Illegal value for CONFIG_I2C_DMAPRIO"
# endif
# define I2C_DMA_PRIO CONFIG_I2C_DMAPRIO
# else
# define I2C_DMA_PRIO DMA_PRIO_HIGH_SELECT
# endif
# if defined(CONFIG_I2C_DMAPRIO)
# if (CONFIG_I2C_DMAPRIO & ~DMA_CHXCTL_PRIO_MASK) != 0
# error "Illegal value for CONFIG_I2C_DMAPRIO"
# endif
# define I2C_DMA_PRIO CONFIG_I2C_DMAPRIO
# else
# define I2C_DMA_PRIO DMA_PRIO_HIGH_SELECT
# endif
#endif
/* Debug ********************************************************************/

32
arch/arm/src/gd32f4/gd32f4xx_serial.c
View File

@ -356,65 +356,65 @@ static const struct uart_ops_s g_uart_ops_no_dma =
#ifdef CONFIG_GD32F4_USART0_SERIALDRIVER
static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE];
static char g_usart0txbuffer[CONFIG_USART0_TXBUFSIZE];
# ifdef CONFIG_GD32F4_USART0_RXDMA
# ifdef CONFIG_GD32F4_USART0_RXDMA
static char g_usart0rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
#ifdef CONFIG_GD32F4_USART1_SERIALDRIVER
static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
# ifdef CONFIG_GD32F4_USART1_RXDMA
# ifdef CONFIG_GD32F4_USART1_RXDMA
static char g_usart1rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
#ifdef CONFIG_GD32F4_USART2_SERIALDRIVER
static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
# ifdef CONFIG_GD32F4_USART2_RXDMA
# ifdef CONFIG_GD32F4_USART2_RXDMA
static char g_usart2rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
#ifdef CONFIG_GD32F4_UART3_SERIALDRIVER
static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE];
static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE];
# ifdef CONFIG_GD32F4_UART3_RXDMA
# ifdef CONFIG_GD32F4_UART3_RXDMA
static char g_uart3rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
#ifdef CONFIG_GD32F4_UART4_SERIALDRIVER
static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE];
static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE];
# ifdef CONFIG_GD32F4_UART4_RXDMA
# ifdef CONFIG_GD32F4_UART4_RXDMA
static char g_uart4rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
#ifdef CONFIG_GD32F4_USART5_SERIALDRIVER
static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE];
static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE];
# ifdef CONFIG_GD32F4_USART5_RXDMA
# ifdef CONFIG_GD32F4_USART5_RXDMA
static char g_usart5rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
#ifdef CONFIG_GD32F4_UART6_SERIALDRIVER
static char g_uart6rxbuffer[CONFIG_UART6_RXBUFSIZE];
static char g_uart6txbuffer[CONFIG_UART6_TXBUFSIZE];
# ifdef CONFIG_GD32F4_UART6_RXDMA
# ifdef CONFIG_GD32F4_UART6_RXDMA
static char g_uart6rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
#ifdef CONFIG_GD32F4_UART7_SERIALDRIVER
static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE];
static char g_uart7txbuffer[CONFIG_UART7_TXBUFSIZE];
# ifdef CONFIG_GD32F4_UART7_RXDMA
# ifdef CONFIG_GD32F4_UART7_RXDMA
static char g_uart7rxfifo[RXDMA_BUFFER_SIZE];
# endif
# endif
#endif
/* This describes the state of the GD32 USART0 ports. */

4
arch/arm/src/gd32f4/hardware/gd32f4xx_rcu.h
View File

@ -236,7 +236,7 @@
#define RCU_CFG0_CKOUT0DIV_SHIFT (24) /* Bits 24-26: The CK_OUT0 divider */
#define RCU_CFG0_CKOUT0DIV_MASK (7 << RCU_CFG0_CKOUT0DIV_SHIFT)
# define RCU_CFG0_CKOUT0DIV(n) ((n) << RCU_CFG0_CKOUT0DIV_SHIFT)
# define RCU_CFG0_CKOUT0DIV(n) ((n) << RCU_CFG0_CKOUT0DIV_SHIFT)
# define RCU_CFG0_CKOUT0_DIV1 RCU_CFG0_CKOUT0DIV(0) /* CK_OUT0 is divided by 1, n=0..3 */
# define RCU_CFG0_CKOUT0_DIV2 RCU_CFG0_CKOUT0DIV(4) /* CK_OUT0 is divided by 2 */
# define RCU_CFG0_CKOUT0_DIV3 RCU_CFG0_CKOUT0DIV(5) /* CK_OUT0 is divided by 3 */
@ -245,7 +245,7 @@
#define RCU_CFG0_CKOUT1DIV_SHIFT (27) /* Bits 27-29: The CK_OUT1 divider */
#define RCU_CFG0_CKOUT1DIV_MASK (7 << RCU_CFG0_CKOUT1DIV_SHIFT)
# define RCU_CFG0_CKOUT1DIV(n) ((n) << RCU_CFG0_CKOUT1DIV_SHIFT)
# define RCU_CFG0_CKOUT1DIV(n) ((n) << RCU_CFG0_CKOUT1DIV_SHIFT)
# define RCU_CFG0_CKOUT1_DIV1 RCU_CFG0_CKOUT1DIV(0) /* CK_OUT1 is divided by 1, n=0..3 */
# define RCU_CFG0_CKOUT1_DIV2 RCU_CFG0_CKOUT1DIV(4) /* CK_OUT1 is divided by 2 */
# define RCU_CFG0_CKOUT1_DIV3 RCU_CFG0_CKOUT1DIV(5) /* CK_OUT1 is divided by 3 */

184
arch/arm/src/imx1/imx_serial.c
View File

@ -251,107 +251,107 @@ static struct uart_dev_s g_uart3port =
/* Now, which one with be tty0/console and which tty1 and tty2? */
#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART1)
# define CONSOLE_DEV g_uart1port /* UART1 is /dev/console */
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# define TTYS0_DEV g_uart1port /* UART1 is /dev/ttyS0 */
# if defined(CONFIG_IMX1_UART2)
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
# if defined(CONFIG_IMX1_UART3)
# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */
# else
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART3)
# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART2)
# define CONSOLE_DEV g_uart2port /* UART2 is /dev/console */
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# define TTYS0_DEV g_uart2port /* UART2 is /dev/ttyS0 */
# if defined(CONFIG_IMX1_UART1)
# define TTYS1_DEV g_uart1port /* UART1 is /dev/ttyS1 */
# if defined(CONFIG_IMX1_UART3)
# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */
# else
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART3)
# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART3)
# define CONSOLE_DEV g_uart3port /* UART3 is /dev/console */
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# define TTYS0_DEV g_uart3port /* UART3 is /dev/ttyS0 */
# if defined(CONFIG_IMX1_UART1)
# define TTYS1_DEV g_uart1port /* UART1 is /dev/ttyS1 */
# if defined(CONFIG_IMX1_UART2)
# define TTYS2_DEV g_uart2port /* UART2 is /dev/ttyS2 */
# else
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART2)
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
#else
# undef CONSOLE_DEV g_uart1port /* No /dev/console */
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# if defined(CONFIG_IMX1_UART1)
# define TTYS0_DEV g_uart1port /* UART1 is /dev/ttyS0 */
# define CONSOLE_DEV g_uart1port /* UART1 is /dev/console */
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# define TTYS0_DEV g_uart1port /* UART1 is /dev/ttyS0 */
# if defined(CONFIG_IMX1_UART2)
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
# if defined(CONFIG_IMX1_UART3)
# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */
# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */
# else
# undef TTYS2_DEV /* No /dev/ttyS2 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART3)
# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART2)
# define TTYS0_DEV g_uart2port /* UART2 is /dev/ttyS0 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# if defined(CONFIG_IMX1_UART3)
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART2)
# define CONSOLE_DEV g_uart2port /* UART2 is /dev/console */
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# define TTYS0_DEV g_uart2port /* UART2 is /dev/ttyS0 */
# if defined(CONFIG_IMX1_UART1)
# define TTYS1_DEV g_uart1port /* UART1 is /dev/ttyS1 */
# if defined(CONFIG_IMX1_UART3)
# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */
# else
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART3)
# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART3)
# define TTYS0_DEV g_uart3port /* UART3 is /dev/ttyS0 */
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART3)
# define CONSOLE_DEV g_uart3port /* UART3 is /dev/console */
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# define TTYS0_DEV g_uart3port /* UART3 is /dev/ttyS0 */
# if defined(CONFIG_IMX1_UART1)
# define TTYS1_DEV g_uart1port /* UART1 is /dev/ttyS1 */
# if defined(CONFIG_IMX1_UART2)
# define TTYS2_DEV g_uart2port /* UART2 is /dev/ttyS2 */
# else
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART2)
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# else
# error "No UARTs enabled"
# undef TTYS0_DEV /* No /dev/ttyS0 */
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
#else
# undef CONSOLE_DEV g_uart1port /* No /dev/console */
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# if defined(CONFIG_IMX1_UART1)
# define TTYS0_DEV g_uart1port /* UART1 is /dev/ttyS0 */
# if defined(CONFIG_IMX1_UART2)
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
# if defined(CONFIG_IMX1_UART3)
# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */
# else
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART3)
# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
# elif defined(CONFIG_IMX1_UART2)
# define TTYS0_DEV g_uart2port /* UART2 is /dev/ttyS0 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# if defined(CONFIG_IMX1_UART3)
# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */
# else
# undef TTYS1_DEV /* No /dev/ttyS1 */
# endif
# elif defined(CONFIG_IMX1_UART3)
# define TTYS0_DEV g_uart3port /* UART3 is /dev/ttyS0 */
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# else
# error "No UARTs enabled"
# undef TTYS0_DEV /* No /dev/ttyS0 */
# undef TTYS1_DEV /* No /dev/ttyS1 */
# undef TTYS2_DEV /* No /dev/ttyS2 */
# endif
#endif
/****************************************************************************
@ -1140,12 +1140,12 @@ void arm_serialinit(void)
#ifdef TTYS0_DEV
uart_register("/dev/ttyS0", &TTYS0_DEV);
# ifdef TTYS1_DEV
# ifdef TTYS1_DEV
uart_register("/dev/ttyS1", &TTYS1_DEV);
# ifdef TTYS2_DEV
# ifdef TTYS2_DEV
uart_register("/dev/ttyS2", &TTYS2_DEV);
# endif
# endif
# endif
#endif
}

12
arch/arm/src/imx6/hardware/imx_enet.h
View File

@ -515,13 +515,13 @@
*/
#ifdef IMX_ENET_HAS_DBSWAP
# ifndef CONFIG_ENDIAN_BIG
# define IMX_USE_DBSWAP
# endif
# ifndef CONFIG_ENDIAN_BIG
# define IMX_USE_DBSWAP
# endif
#else
# ifndef CONFIG_ENDIAN_BIG
# define IMX_BUFFERS_SWAP
# endif
# ifndef CONFIG_ENDIAN_BIG
# define IMX_BUFFERS_SWAP
# endif
#endif
#ifndef IMX_BUFFERS_SWAP

10
arch/arm/src/imx6/imx_serial.c
View File

@ -1090,18 +1090,18 @@ void arm_serialinit(void)
#ifdef TTYS0_DEV
uart_register("/dev/ttyS0", &TTYS0_DEV);
# ifdef TTYS1_DEV
# ifdef TTYS1_DEV
uart_register("/dev/ttyS1", &TTYS1_DEV);
# ifdef TTYS2_DEV
# ifdef TTYS2_DEV
uart_register("/dev/ttyS2", &TTYS2_DEV);
# ifdef TTYS3_DEV
# ifdef TTYS3_DEV
uart_register("/dev/ttyS3", &TTYS2_DEV);
# ifdef TTYS4_DEV
# ifdef TTYS4_DEV
uart_register("/dev/ttyS4", &TTYS2_DEV);
# endif
# endif
# endif
# endif
# endif
#endif
}

12
arch/arm/src/imxrt/hardware/imxrt_enet.h
View File

@ -509,13 +509,13 @@
*/
#ifdef IMXRT_ENET_HAS_DBSWAP
# ifndef CONFIG_ENDIAN_BIG
# define IMXRT_USE_DBSWAP
# endif
# ifndef CONFIG_ENDIAN_BIG
# define IMXRT_USE_DBSWAP
# endif
#else
# ifndef CONFIG_ENDIAN_BIG
# define IMXRT_BUFFERS_SWAP
# endif
# ifndef CONFIG_ENDIAN_BIG
# define IMXRT_BUFFERS_SWAP
# endif
#endif
#ifndef IMXRT_BUFFERS_SWAP

2
arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h
View File

@ -200,7 +200,7 @@
/* Bits 13-15: Reserved */
#define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */
#define CCM_CBCDR_SEMC_PODF_MASK (0x7 << CCM_CBCDR_SEMC_PODF_SHIFT)
# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT)
# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT)
/* Bits 19-24: Reserved */
#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */
#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)

2
arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h
View File

@ -1012,7 +1012,7 @@
#define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP (1 << 14)
#define GPR_GPR2_MQS_CLK_DIV_SHIFT (16)
#define GPR_GPR2_MQS_CLK_DIV_MASK (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT)
# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT)
# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT)
#define GPR_GPR2_MQS_SW_RST_EN (1 << 24)
#define GPR_GPR2_MQS_EN (1 << 25)
#define GPR_GPR2_MQS_OVERSAMPLE32 (0 << 26)

4
arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h
View File

@ -209,7 +209,7 @@
/* Bits 13-15: Reserved */
#define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */
#define CCM_CBCDR_SEMC_PODF_MASK (0x3 << CCM_CBCDR_SEMC_PODF_SHIFT)
# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT)
# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT)
/* Bits 19-24: Reserved */
#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */
#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)
@ -262,7 +262,7 @@
/* Bits 20-22: Reserved */
#define CCM_CBCMR_LCDIF_PODF_SHIFT (23) /* Bits 23-25: Post-divider for LCDIF clock */
#define CCM_CBCMR_LCDIF_PODF_MASK (0x7 << CCM_CBCMR_LCDIF_PODF_SHIFT)
# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT)
# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT)
#define CCM_CBCMR_LPSPI_PODF_SHIFT (26) /* Bits 26-28: Divider for LPSPI */
#define CCM_CBCMR_LPSPI_PODF_MASK (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT)
# define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT)

2
arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h
View File

@ -1288,7 +1288,7 @@
#define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP (1 << 14)
#define GPR_GPR2_MQS_CLK_DIV_SHIFT (16)
#define GPR_GPR2_MQS_CLK_DIV_MASK (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT)
# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT)
# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT)
#define GPR_GPR2_MQS_SW_RST_EN (1 << 24)
#define GPR_GPR2_MQS_EN (1 << 25)
#define GPR_GPR2_MQS_OVERSAMPLE32 (0 << 26)

4
arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h
View File

@ -205,7 +205,7 @@
/* Bits 13-15: Reserved */
#define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */
#define CCM_CBCDR_SEMC_PODF_MASK (0x3 << CCM_CBCDR_SEMC_PODF_SHIFT)
# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT)
# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT)
/* Bits 19-24: Reserved */
#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */
#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)
@ -268,7 +268,7 @@
/* Bits 20-22: Reserved */
#define CCM_CBCMR_LCDIF_PODF_SHIFT (23) /* Bits 23-25: Post-divider for LCDIF clock */
#define CCM_CBCMR_LCDIF_PODF_MASK (0x7 << CCM_CBCMR_LCDIF_PODF_SHIFT)
# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT)
# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT)
#define CCM_CBCMR_LPSPI_PODF_SHIFT (26) /* Bits 26-28: Divider for LPSPI */
#define CCM_CBCMR_LPSPI_PODF_MASK (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT)
# define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT)

4
arch/arm/src/imxrt/imxrt_allocateheap.c
View File

@ -121,9 +121,9 @@
*/
#if defined(IMXRT_OCRAM2_BASE)
# define _IMXRT_OCRAM_BASE IMXRT_OCRAM2_BASE
# define _IMXRT_OCRAM_BASE IMXRT_OCRAM2_BASE
#else
# define _IMXRT_OCRAM_BASE IMXRT_OCRAM_BASE
# define _IMXRT_OCRAM_BASE IMXRT_OCRAM_BASE
#endif
#define CONFIG_ITCM_USED 0

24
arch/arm/src/imxrt/imxrt_enc.c
View File

@ -77,7 +77,7 @@
#endif
#ifndef CONFIG_ENC1_HNE
# define CONFIG_ENC1_HNE 0
# define CONFIG_ENC1_HNE 0
#endif
#ifndef CONFIG_ENC1_XIE
@ -89,7 +89,7 @@
#endif
#ifndef CONFIG_ENC1_XNE
# define CONFIG_ENC1_XNE 0
# define CONFIG_ENC1_XNE 0
#endif
#ifndef CONFIG_ENC1_MOD
@ -97,7 +97,7 @@
#endif
#ifndef CONFIG_ENC1_MODULUS
# define CONFIG_ENC1_MODULUS 0
# define CONFIG_ENC1_MODULUS 0
#endif
#if defined(CONFIG_DEBUG_SENSORS)
@ -122,7 +122,7 @@
#endif
#ifndef CONFIG_ENC2_HNE
# define CONFIG_ENC2_HNE 0
# define CONFIG_ENC2_HNE 0
#endif
#ifndef CONFIG_ENC2_XIE
@ -134,7 +134,7 @@
#endif
#ifndef CONFIG_ENC2_XNE
# define CONFIG_ENC2_XNE 0
# define CONFIG_ENC2_XNE 0
#endif
#ifndef CONFIG_ENC2_MOD
@ -142,7 +142,7 @@
#endif
#ifndef CONFIG_ENC2_MODULUS
# define CONFIG_ENC2_MODULUS 0
# define CONFIG_ENC2_MODULUS 0
#endif
#if defined(CONFIG_DEBUG_SENSORS)
@ -167,7 +167,7 @@
#endif
#ifndef CONFIG_ENC3_HNE
# define CONFIG_ENC3_HNE 0
# define CONFIG_ENC3_HNE 0
#endif
#ifndef CONFIG_ENC3_XIE
@ -179,7 +179,7 @@
#endif
#ifndef CONFIG_ENC3_XNE
# define CONFIG_ENC3_XNE 0
# define CONFIG_ENC3_XNE 0
#endif
#ifndef CONFIG_ENC3_MOD
@ -187,7 +187,7 @@
#endif
#ifndef CONFIG_ENC3_MODULUS
# define CONFIG_ENC3_MODULUS 0
# define CONFIG_ENC3_MODULUS 0
#endif
#if defined(CONFIG_DEBUG_SENSORS)
@ -212,7 +212,7 @@
#endif
#ifndef CONFIG_ENC4_HNE
# define CONFIG_ENC4_HNE 0
# define CONFIG_ENC4_HNE 0
#endif
#ifndef CONFIG_ENC4_XIE
@ -224,7 +224,7 @@
#endif
#ifndef CONFIG_ENC4_XNE
# define CONFIG_ENC4_XNE 0
# define CONFIG_ENC4_XNE 0
#endif
#ifndef CONFIG_ENC4_MOD
@ -232,7 +232,7 @@
#endif
#ifndef CONFIG_ENC4_MODULUS
# define CONFIG_ENC4_MODULUS 0
# define CONFIG_ENC4_MODULUS 0
#endif
#if defined(CONFIG_DEBUG_SENSORS)

4
arch/arm/src/imxrt/imxrt_flexcan.c
View File

@ -821,10 +821,10 @@ static void imxrt_receive(struct imxrt_driver_s *priv,
uint32_t mbi;
uint32_t mbj;
struct mb_s *rf;
# ifdef CONFIG_NET_CAN_CANFD
#ifdef CONFIG_NET_CAN_CANFD
uint32_t *frame_data_word;
uint32_t i;
# endif
#endif
uint32_t f;
while ((f = flags) != 0)

4
arch/arm/src/imxrt/imxrt_flexpwm.c
View File

@ -52,9 +52,9 @@
#ifdef CONFIG_IMXRT_FLEXPWM
#ifdef CONFIG_PWM_NCHANNELS
# define PWM_NCHANNELS CONFIG_PWM_NCHANNELS
# define PWM_NCHANNELS CONFIG_PWM_NCHANNELS
#else
# define PWM_NCHANNELS 1
# define PWM_NCHANNELS 1
#endif
#define MODULE_OFFSET 0x60

316
arch/arm/src/imxrt/imxrt_serial.c
View File

@ -804,15 +804,15 @@ static struct imxrt_uart_s g_lpuart1priv =
.size = CONFIG_LPUART1_TXBUFSIZE,
.buffer = g_lpuart1txbuffer,
},
#if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA)
# if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA)
.ops = &g_lpuart_rxtxdma_ops,
#elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA)
# elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA)
.ops = &g_lpuart_rxdma_ops,
#elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA)
# elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA)
.ops = &g_lpuart_txdma_ops,
#else
# else
.ops = &g_lpuart_ops,
#endif
# endif
.priv = &g_lpuart1priv,
},
@ -822,38 +822,38 @@ static struct imxrt_uart_s g_lpuart1priv =
.parity = CONFIG_LPUART1_PARITY,
.bits = CONFIG_LPUART1_BITS,
.stopbits2 = CONFIG_LPUART1_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
.iflow = 1,
#endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) \
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART1_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART1_TX,
#endif
# endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART1_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART1_TXDMA
# ifdef CONFIG_LPUART1_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART1_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART1_RXDMA
# endif
# ifdef CONFIG_LPUART1_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART1_RX,
.rxfifo = g_lpuart1rxfifo,
#endif
# endif
};
#endif
@ -892,37 +892,37 @@ static struct imxrt_uart_s g_lpuart2priv =
.parity = CONFIG_LPUART2_PARITY,
.bits = CONFIG_LPUART2_BITS,
.stopbits2 = CONFIG_LPUART2_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART2_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)
.iflow = 1,
#endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) \
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART2_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART2_TX,
#endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# endif
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART2_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART2_TXDMA
# ifdef CONFIG_LPUART2_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART2_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART2_RXDMA
# endif
# ifdef CONFIG_LPUART2_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART2_RX,
.rxfifo = g_lpuart2rxfifo,
#endif
# endif
};
#endif
@ -941,15 +941,15 @@ static struct imxrt_uart_s g_lpuart3priv =
.size = CONFIG_LPUART3_TXBUFSIZE,
.buffer = g_lpuart3txbuffer,
},
#if defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA)
# if defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA)
.ops = &g_lpuart_rxtxdma_ops,
#elif defined(CONFIG_LPUART3_RXDMA) && !defined(CONFIG_LPUART3_TXDMA)
# elif defined(CONFIG_LPUART3_RXDMA) && !defined(CONFIG_LPUART3_TXDMA)
.ops = &g_lpuart_rxdma_ops,
#elif !defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA)
# elif !defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA)
.ops = &g_lpuart_txdma_ops,
#else
# else
.ops = &g_lpuart_ops,
#endif
# endif
.priv = &g_lpuart3priv,
},
@ -959,37 +959,37 @@ static struct imxrt_uart_s g_lpuart3priv =
.parity = CONFIG_LPUART3_PARITY,
.bits = CONFIG_LPUART3_BITS,
.stopbits2 = CONFIG_LPUART3_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART3_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART3_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART3_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)
.iflow = 1,
#endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) \
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART3_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART3_TX,
#endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# endif
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART3_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART3_TXDMA
# ifdef CONFIG_LPUART3_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART3_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART3_RXDMA
# endif
# ifdef CONFIG_LPUART3_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART3_RX,
.rxfifo = g_lpuart3rxfifo,
#endif
# endif
};
#endif
@ -1026,37 +1026,37 @@ static struct imxrt_uart_s g_lpuart4priv =
.parity = CONFIG_LPUART4_PARITY,
.bits = CONFIG_LPUART4_BITS,
.stopbits2 = CONFIG_LPUART4_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART4_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART4_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART4_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)
.iflow = 1,
#endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) \
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART4_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART4_TX,
#endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# endif
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART4_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART4_TXDMA
# ifdef CONFIG_LPUART4_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART4_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART4_RXDMA
# endif
# ifdef CONFIG_LPUART4_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART4_RX,
.rxfifo = g_lpuart4rxfifo,
#endif
# endif
};
#endif
@ -1075,15 +1075,15 @@ static struct imxrt_uart_s g_lpuart5priv =
.size = CONFIG_LPUART5_TXBUFSIZE,
.buffer = g_lpuart5txbuffer,
},
#if defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA)
# if defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA)
.ops = &g_lpuart_rxtxdma_ops,
#elif defined(CONFIG_LPUART5_RXDMA) && !defined(CONFIG_LPUART5_TXDMA)
# elif defined(CONFIG_LPUART5_RXDMA) && !defined(CONFIG_LPUART5_TXDMA)
.ops = &g_lpuart_rxdma_ops,
#elif !defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA)
# elif !defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA)
.ops = &g_lpuart_txdma_ops,
#else
# else
.ops = &g_lpuart_ops,
#endif
# endif
.priv = &g_lpuart5priv,
},
@ -1093,37 +1093,37 @@ static struct imxrt_uart_s g_lpuart5priv =
.parity = CONFIG_LPUART5_PARITY,
.bits = CONFIG_LPUART5_BITS,
.stopbits2 = CONFIG_LPUART5_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART5_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART5_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART5_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)
.iflow = 1,
#endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) \
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART5_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART5_TX,
#endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# endif
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART5_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART5_TXDMA
# ifdef CONFIG_LPUART5_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART5_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART5_RXDMA
# endif
# ifdef CONFIG_LPUART5_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART5_RX,
.rxfifo = g_lpuart5rxfifo,
#endif
# endif
};
#endif
@ -1142,15 +1142,15 @@ static struct imxrt_uart_s g_lpuart6priv =
.size = CONFIG_LPUART6_TXBUFSIZE,
.buffer = g_lpuart6txbuffer,
},
#if defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA)
# if defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA)
.ops = &g_lpuart_rxtxdma_ops,
#elif defined(CONFIG_LPUART6_RXDMA) && !defined(CONFIG_LPUART6_TXDMA)
# elif defined(CONFIG_LPUART6_RXDMA) && !defined(CONFIG_LPUART6_TXDMA)
.ops = &g_lpuart_rxdma_ops,
#elif !defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA)
# elif !defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA)
.ops = &g_lpuart_txdma_ops,
#else
# else
.ops = &g_lpuart_ops,
#endif
# endif
.priv = &g_lpuart6priv,
},
@ -1160,37 +1160,37 @@ static struct imxrt_uart_s g_lpuart6priv =
.parity = CONFIG_LPUART6_PARITY,
.bits = CONFIG_LPUART6_BITS,
.stopbits2 = CONFIG_LPUART6_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART6_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART6_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART6_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)
.iflow = 1,
#endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) \
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART6_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART6_TX,
#endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# endif
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART6_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART6_TXDMA
# ifdef CONFIG_LPUART6_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART6_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART6_RXDMA
# endif
# ifdef CONFIG_LPUART6_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART6_RX,
.rxfifo = g_lpuart6rxfifo,
#endif
# endif
};
#endif
@ -1209,15 +1209,15 @@ static struct imxrt_uart_s g_lpuart7priv =
.size = CONFIG_LPUART7_TXBUFSIZE,
.buffer = g_lpuart7txbuffer,
},
#if defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA)
# if defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA)
.ops = &g_lpuart_rxtxdma_ops,
#elif defined(CONFIG_LPUART7_RXDMA) && !defined(CONFIG_LPUART7_TXDMA)
# elif defined(CONFIG_LPUART7_RXDMA) && !defined(CONFIG_LPUART7_TXDMA)
.ops = &g_lpuart_rxdma_ops,
#elif !defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA)
# elif !defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA)
.ops = &g_lpuart_txdma_ops,
#else
# else
.ops = &g_lpuart_ops,
#endif
# endif
.priv = &g_lpuart7priv,
},
@ -1227,37 +1227,37 @@ static struct imxrt_uart_s g_lpuart7priv =
.parity = CONFIG_LPUART7_PARITY,
.bits = CONFIG_LPUART7_BITS,
.stopbits2 = CONFIG_LPUART7_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART7_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART7_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART7_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)
.iflow = 1,
#endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) \
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART7_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART7_TX,
#endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# endif
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART7_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART7_TXDMA
# ifdef CONFIG_LPUART7_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART7_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART7_RXDMA
# endif
# ifdef CONFIG_LPUART7_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART7_RX,
.rxfifo = g_lpuart7rxfifo,
#endif
# endif
};
#endif
@ -1276,15 +1276,15 @@ static struct imxrt_uart_s g_lpuart8priv =
.size = CONFIG_LPUART8_TXBUFSIZE,
.buffer = g_lpuart8txbuffer,
},
#if defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA)
# if defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA)
.ops = &g_lpuart_rxtxdma_ops,
#elif defined(CONFIG_LPUART8_RXDMA) && !defined(CONFIG_LPUART8_TXDMA)
# elif defined(CONFIG_LPUART8_RXDMA) && !defined(CONFIG_LPUART8_TXDMA)
.ops = &g_lpuart_rxdma_ops,
#elif !defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA)
# elif !defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA)
.ops = &g_lpuart_txdma_ops,
#else
# else
.ops = &g_lpuart_ops,
#endif
# endif
.priv = &g_lpuart8priv,
},
@ -1294,37 +1294,37 @@ static struct imxrt_uart_s g_lpuart8priv =
.parity = CONFIG_LPUART8_PARITY,
.bits = CONFIG_LPUART8_BITS,
.stopbits2 = CONFIG_LPUART8_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART8_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART8_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART8_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)
.iflow = 1,
#endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) \
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART8_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART8_TX,
#endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# endif
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART8_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART8_TXDMA
# ifdef CONFIG_LPUART8_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART8_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART8_RXDMA
# endif
# ifdef CONFIG_LPUART8_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART8_RX,
.rxfifo = g_lpuart8rxfifo,
#endif
# endif
};
#endif

4
arch/arm/src/imxrt/imxrt_usbdev.c
View File

@ -408,8 +408,8 @@ struct imxrt_usbdev_s
static uint32_t imxrt_getreg(uint32_t addr);
static void imxrt_putreg(uint32_t val, uint32_t addr);
#else
# define imxrt_getreg(addr) getreg32(addr)
# define imxrt_putreg(val,addr) putreg32(val,addr)
# define imxrt_getreg(addr) getreg32(addr)
# define imxrt_putreg(val,addr) putreg32(val,addr)
#endif
static inline void imxrt_clrbits(uint32_t mask, uint32_t addr);

8
arch/arm/src/kinetis/hardware/kinetis_adc.h
View File

@ -183,10 +183,10 @@
#define ADC_CFG1_MODE_SHIFT (2) /* Bits 2-3: Conversion mode selection */
#define ADC_CFG1_MODE_MASK (3 << ADC_CFG1_MODE_SHIFT)
# define ADC_CFG1_MODE_89BIT (0 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 8-bit; DIFF=1 9-bit */
# define ADC_CFG1_MODE_1213BIT (1 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 12-bit; DIFF=1 13-bit */
# define ADC_CFG1_MODE_1011BIT (2 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 10-bit; DIFF=1 11-bit */
# define ADC_CFG1_MODE_1616BIT (3 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 16-bit; DIFF=1 16-bit */
# define ADC_CFG1_MODE_89BIT (0 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 8-bit; DIFF=1 9-bit */
# define ADC_CFG1_MODE_1213BIT (1 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 12-bit; DIFF=1 13-bit */
# define ADC_CFG1_MODE_1011BIT (2 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 10-bit; DIFF=1 11-bit */
# define ADC_CFG1_MODE_1616BIT (3 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 16-bit; DIFF=1 16-bit */
#define ADC_CFG1_ADLSMP (1 << 4) /* Bit 4: Sample time configuration */
#define ADC_CFG1_ADIV_SHIFT (5) /* Bits 5-6: Clock divide select */

12
arch/arm/src/kinetis/hardware/kinetis_enet.h
View File

@ -489,13 +489,13 @@
*/
#ifdef KINETIS_ENET_HAS_DBSWAP
# ifndef CONFIG_ENDIAN_BIG
# define KINETIS_USE_DBSWAP
# endif
# ifndef CONFIG_ENDIAN_BIG
# define KINETIS_USE_DBSWAP
# endif
#else
# ifndef CONFIG_ENDIAN_BIG
# define KINETIS_BUFFERS_SWAP
# endif
# ifndef CONFIG_ENDIAN_BIG
# define KINETIS_BUFFERS_SWAP
# endif
#endif
#ifndef KINETIS_BUFFERS_SWAP

2
arch/arm/src/kinetis/hardware/kinetis_flexbus.h
View File

@ -68,8 +68,6 @@
/* Register Addresses *******************************************************/
# define 0x4000c000 /* FlexBus */
#define KINETIS_FB_CS_BASE(n) (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CS_OFFSET(n))
#define KINETIS_FB_CSAR(n) (KINETIS_FB_CS_BASE(n)+KINETIS_FB_CSAR_OFFSET)
#define KINETIS_FB_CSMR(n) (KINETIS_FB_CS_BASE(n)+KINETIS_FB_CSMR_OFFSET)

4
arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h
View File

@ -46,10 +46,10 @@
#define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
# if !defined(KINETIS_FLEXMEM_SIZE)
#if !defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
# endif
#endif
#define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
#define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband

196
arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h
View File

@ -48,135 +48,135 @@
defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || \
defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
# define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
# define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
# if !defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
# endif
# define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
# if !defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
# endif
# define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * -0x21ffffff Reserved */
# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * -0x3fffffff Reserved */
# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
* bridge 1 (AIPS-Lite1) */
# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * -0x41ffffff Reserved */
# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * -0x5fffffff Reserved */
# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */
# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */
# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
/* 0xe0100000 * -0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map *******************************************/
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */
# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */
# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
# define KINETIS_CRC_BASE 0x40032000 /* CRC */
# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
# define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */
# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
# define KINETIS_I2C2_BASE 0x400E6000 /* I2C 2 */
# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */
# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */
# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
# define KINETIS_CRC_BASE 0x40032000 /* CRC */
# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
# define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */
# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */
# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */
# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
# define KINETIS_I2C2_BASE 0x400E6000 /* I2C 2 */
# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
/* Peripheral Bridge 1 Memory Map *******************************************/
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */
# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer 2 */
# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */
# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */
# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */
# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer 2 */
# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */
# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */
# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
* purpose input/output module that shares the
* crossbar switch slave port with the AIPS-Lite
* is accessed at this address. */
# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map **********************************/
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
#else
/* The memory map for other parts is defined in other documents and may or

236
arch/arm/src/kinetis/hardware/kinetis_k66memorymap.h
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@ -46,164 +46,164 @@
#if defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)
# define KINETIS_FLASH_BASE 0x00000000 /* -0x07ffffff Program flash and read-
# define KINETIS_FLASH_BASE 0x00000000 /* -0x07ffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
# define KINETIS_SDRAMALIAS_BASE 0x08000000 /* -0x0fffffff SDRAM (Aliased area). mapped
# define KINETIS_SDRAMALIAS_BASE 0x08000000 /* -0x0fffffff SDRAM (Aliased area). mapped
* to same space of 0x88000000 -
* 0x8FFF_FFFF. See bit31 of
* SDRAMC */
# if defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
# else
# define KINETIS_PRGACCLRAM_BASE 0x14000000 /* -0x17ffffff For devices with program flash
# if defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
# else
# define KINETIS_PRGACCLRAM_BASE 0x14000000 /* -0x17ffffff For devices with program flash
* only: Programming acceleration
* RAM */
# endif
# define KINETIS_FBALIAS_BASE 0x18000000 /* -0x1bffffff FlexBus (Aliased Area). mapped
# endif
# define KINETIS_FBALIAS_BASE 0x18000000 /* -0x1bffffff FlexBus (Aliased Area). mapped
* to same space of 0x9800_0000 -
* 0x9BFF_FFFF. See bit31 of
* FlexBus chip select */
# define KINETIS_SRAML_BASE 0x1c000000 /* -0x1fffffff SRAM_L: Lower SRAM
# define KINETIS_SRAML_BASE 0x1c000000 /* -0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * -0x21ffffff Reserved */
# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * -0x2fffffff Reserved */
# define KINETIS_FDATALIAS_BASE 0x30000000 /* -0x33ffffff Flash Data Alias */
# define KINETIS_FLEXNVMCO_BASE 0x34000000 /* -0x3fffffff FlexNVM Cortex-M4 core only */
# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
# define KINETIS_FDATALIAS_BASE 0x30000000 /* -0x33ffffff Flash Data Alias */
# define KINETIS_FLEXNVMCO_BASE 0x34000000 /* -0x3fffffff FlexNVM Cortex-M4 core only */
# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral
* bridge 0 (AIPS-Lite0) */
# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral
* bridge 1 (AIPS-Lite1) */
# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * -0x41ffffff Reserved */
# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * -0x5fffffff Reserved */
# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus (External Memory - Write-back) */
# define KINETIS_SDRAMWB_BASE 0x70000000 /* -0x7fffffff SDRAM (External RAM - Write-back) */
# define KINETIS_SDRAMWT_BASE 0x80000000 /* -0x8fffffff SDRAM (External RAM - Write-through) */
# define KINETIS_FLEXBUSWT_BASE 0x90000000 /* -0x9fffffff FlexBus (External RAM - Write-through) */
# define KINETIS_FLEXBUSEP_BASE 0xa0000000 /* -0xdfffffff FlexBus External Peripheral - Not executable)*/
# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus (External Memory - Write-back) */
# define KINETIS_SDRAMWB_BASE 0x70000000 /* -0x7fffffff SDRAM (External RAM - Write-back) */
# define KINETIS_SDRAMWT_BASE 0x80000000 /* -0x8fffffff SDRAM (External RAM - Write-through) */
# define KINETIS_FLEXBUSWT_BASE 0x90000000 /* -0x9fffffff FlexBus (External RAM - Write-through) */
# define KINETIS_FLEXBUSEP_BASE 0xa0000000 /* -0xdfffffff FlexBus External Peripheral - Not executable)*/
# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
/* 0xe0100000 * -0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map *******************************************/
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
# define KINETIS_SDRAMC_BASE 0x4000f000 /* SDRAMC */
# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */
# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */
# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
# define KINETIS_RNGA_BASE 0x40029000 /* Random Number Generator (RNGA) */
# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
# define KINETIS_CRC_BASE 0x40032000 /* CRC */
# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer (FTM) 2 */
# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
# define KINETIS_DAC0_BASE 0x4003f000 /* DAC0 */
# define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */
# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
# define KINETIS_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */
# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */
# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */
# define KINETIS_MPU_BASE 0x4000d000 /* MPU */
# define KINETIS_SDRAMC_BASE 0x4000f000 /* SDRAMC */
# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */
# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */
# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */
# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */
# define KINETIS_RNGA_BASE 0x40029000 /* Random Number Generator (RNGA) */
# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */
# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */
# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
# define KINETIS_CRC_BASE 0x40032000 /* CRC */
# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer (FTM) 2 */
# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */
# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */
# define KINETIS_DAC0_BASE 0x4003f000 /* DAC0 */
# define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */
# define KINETIS_SYSR_BASE 0x40041000 /* System register file */
# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */
# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */
# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */
# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12))
# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */
# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */
# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */
# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */
# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */
# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */
# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */
# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */
# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */
# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */
# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */
# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */
# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
# define KINETIS_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */
/* Peripheral Bridge 1 Memory Map *******************************************/
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_RNGA_ALT_BASE 0x400a0000 /* Alternate address Random number generator (RNGA) */
# define KINETIS_USBHS_BASE 0x400a1000 /* USB OTG HS/FS/LS */
# define KINETIS_USBHSPHY_BASE 0x400a2000 /* USBHS PHY */
# define KINETIS_USBHSDCD_BASE 0x400a3000 /* USBHS DCD */
# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
# define KINETIS_SDHC_BASE 0x400b1000 /* eSDHC */
# define KINETIS_FTM2_ALT_BASE 0x400b8000 /* Alternate address FlexTimer 2 */
# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */
# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
# define KINETIS_LPUART0_BASE 0x400c4000 /* LPUART0 */
# define KINETIS_TPM1_BASE 0x400c9000 /* TPM1 */
# define KINETIS_TPM2_BASE 0x400ca000 /* TPM2 */
# define KINETIS_DAC0_ALT_BASE 0x400cc000 /* Alternate address 12-bit digital-to-analog converter (DAC) 0 */
# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
# define KINETIS_I2C2_BASE 0x400e6000 /* I2C 2 */
# define KINETIS_I2C3_BASE 0x400e7000 /* I2C 3 */
# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_RNGA_ALT_BASE 0x400a0000 /* Alternate address Random number generator (RNGA) */
# define KINETIS_USBHS_BASE 0x400a1000 /* USB OTG HS/FS/LS */
# define KINETIS_USBHSPHY_BASE 0x400a2000 /* USBHS PHY */
# define KINETIS_USBHSDCD_BASE 0x400a3000 /* USBHS DCD */
# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */
# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */
# define KINETIS_SDHC_BASE 0x400b1000 /* eSDHC */
# define KINETIS_FTM2_ALT_BASE 0x400b8000 /* Alternate address FlexTimer 2 */
# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */
# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */
# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */
# define KINETIS_LPUART0_BASE 0x400c4000 /* LPUART0 */
# define KINETIS_TPM1_BASE 0x400c9000 /* TPM1 */
# define KINETIS_TPM2_BASE 0x400ca000 /* TPM2 */
# define KINETIS_DAC0_ALT_BASE 0x400cc000 /* Alternate address 12-bit digital-to-analog converter (DAC) 0 */
# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
# define KINETIS_I2C2_BASE 0x400e6000 /* I2C 2 */
# define KINETIS_I2C3_BASE 0x400e7000 /* I2C 3 */
# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
* purpose input/output module that shares the
* crossbar switch slave port with the AIPS-Lite
* is accessed at this address. */
# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map **********************************/
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
# define KINETIS_CACHECTL_BASE 0xe0082000 /* Cache Controller */
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */
# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */
# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */
# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */
# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */
# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */
# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */
# define KINETIS_CACHECTL_BASE 0xe0082000 /* Cache Controller */
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
#else
/* The memory map for other parts is defined in other documents and may or

64
arch/arm/src/kinetis/hardware/kinetis_kx6tpm.h
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@ -81,20 +81,20 @@
#define TPM_SC_PS_SHIFT 0 /* Bits 0-2: Prescale Factor Selection */
#define TPM_SC_PS_MASK (7 << TPM_SC_PS_SHIFT)
# define TPM_SC_PS_DIV1 (0 << TPM_SC_PS_SHIFT) /* Divide Clock by 1 */
# define TPM_SC_PS_DIV2 (1 << TPM_SC_PS_SHIFT) /* Divide Clock by 2 */
# define TPM_SC_PS_DIV4 (2 << TPM_SC_PS_SHIFT) /* Divide Clock by 4 */
# define TPM_SC_PS_DIV8 (3 << TPM_SC_PS_SHIFT) /* Divide Clock by 8 */
# define TPM_SC_PS_DIV16 (4 << TPM_SC_PS_SHIFT) /* Divide Clock by 16 */
# define TPM_SC_PS_DIV32 (5 << TPM_SC_PS_SHIFT) /* Divide Clock by 32 */
# define TPM_SC_PS_DIV64 (6 << TPM_SC_PS_SHIFT) /* Divide Clock by 64 */
# define TPM_SC_PS_DIV128 (7 << TPM_SC_PS_SHIFT) /* Divide Clock by 128 */
# define TPM_SC_PS_DIV1 (0 << TPM_SC_PS_SHIFT) /* Divide Clock by 1 */
# define TPM_SC_PS_DIV2 (1 << TPM_SC_PS_SHIFT) /* Divide Clock by 2 */
# define TPM_SC_PS_DIV4 (2 << TPM_SC_PS_SHIFT) /* Divide Clock by 4 */
# define TPM_SC_PS_DIV8 (3 << TPM_SC_PS_SHIFT) /* Divide Clock by 8 */
# define TPM_SC_PS_DIV16 (4 << TPM_SC_PS_SHIFT) /* Divide Clock by 16 */
# define TPM_SC_PS_DIV32 (5 << TPM_SC_PS_SHIFT) /* Divide Clock by 32 */
# define TPM_SC_PS_DIV64 (6 << TPM_SC_PS_SHIFT) /* Divide Clock by 64 */
# define TPM_SC_PS_DIV128 (7 << TPM_SC_PS_SHIFT) /* Divide Clock by 128 */
#define TPM_SC_CMOD_SHIFT 3 /* Bits 3-4: Clock Mode Selection */
#define TPM_SC_CMOD_MASK (3 << TPM_SC_CMOD_SHIFT)
# define TPM_SC_CMOD_DIS (0 << TPM_SC_CMOD_SHIFT) /* TPM counter is disabled */
# define TPM_SC_CMOD_LPTPM_CLK (1 << TPM_SC_CMOD_SHIFT) /* TPM increments on every counter clock */
# define TPM_SC_CMOD_LPTPM_EXTCLK (2 << TPM_SC_CMOD_SHIFT) /* TPM increments on rising edge of EXTCLK */
# define TPM_SC_CMOD_DIS (0 << TPM_SC_CMOD_SHIFT) /* TPM counter is disabled */
# define TPM_SC_CMOD_LPTPM_CLK (1 << TPM_SC_CMOD_SHIFT) /* TPM increments on every counter clock */
# define TPM_SC_CMOD_LPTPM_EXTCLK (2 << TPM_SC_CMOD_SHIFT) /* TPM increments on rising edge of EXTCLK */
#define TPM_SC_CPWMS (1 << 5) /* Bit 5: Center-aligned PWM Select */
#define TPM_SC_TOIE (1 << 6) /* Bit 6: Timer Overflow Interrupt Enable */
@ -162,8 +162,8 @@
#define TPM_CONF_DBGMODE_SHIFT 6 /* Bits 6-7: Debug Mode */
#define TPM_CONF_DBGMODE_MASK (3 << TPM_CONF_DBGMODE_SHIFT)
# define TPM_CONF_DBGMODE_PAUSE (0 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter will pause during DEBUG mode */
# define TPM_CONF_DBGMODE_CONT (3 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter continue working in DEBUG mode */
# define TPM_CONF_DBGMODE_PAUSE (0 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter will pause during DEBUG mode */
# define TPM_CONF_DBGMODE_CONT (3 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter continue working in DEBUG mode */
#define TPM_CONF_GTBSYNC (1 << 8) /* Bit 8: Global Time Base Synchronization */
#define TPM_CONF_GTBEEN (1 << 9) /* Bit 9: Global Time Base Enable */
@ -179,25 +179,25 @@
#define TPM_CONF_TRGSEL_SHIFT 24 /* Bits 24-27: Trigger Select */
#define TPM_CONF_TRGSEL_MASK (0xf << TPM_CONF_TRGSEL_SHIFT)
/* Internal TPM_CONF_TRGSRC set */
# define TPM_CONF_TRGSEL_INTC0 (0 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 0 pin input capture */
# define TPM_CONF_TRGSEL_INTC1 (2 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 1 pin input capture */
# define TPM_CONF_TRGSEL_INTC01 (3 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 0 or 1 pin input capture */
# define TPM_CONF_TRGSEL_INTC0 (0 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 0 pin input capture */
# define TPM_CONF_TRGSEL_INTC1 (2 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 1 pin input capture */
# define TPM_CONF_TRGSEL_INTC01 (3 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 0 or 1 pin input capture */
# define TPM_CONF_TRGSEL_EXTRG_IN (0 << TPM_CONF_TRGSEL_SHIFT) /* External trigger pin input */
# define TPM_CONF_TRGSEL_CMP0 (1 << TPM_CONF_TRGSEL_SHIFT) /* CPM0 output */
# define TPM_CONF_TRGSEL_CMP1 (2 << TPM_CONF_TRGSEL_SHIFT) /* CPM1 output */
# define TPM_CONF_TRGSEL_CMP2 (3 << TPM_CONF_TRGSEL_SHIFT) /* CPM2 output */
# define TPM_CONF_TRGSEL_PIT0 (4 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 0 */
# define TPM_CONF_TRGSEL_PIT1 (5 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 1 */
# define TPM_CONF_TRGSEL_PIT2 (6 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 2 */
# define TPM_CONF_TRGSEL_PIT3 (7 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 3 */
# define TPM_CONF_TRGSEL_FTM0 (8 << TPM_CONF_TRGSEL_SHIFT) /* FTM0 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM1 (9 << TPM_CONF_TRGSEL_SHIFT) /* FTM1 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM2 (10 << TPM_CONF_TRGSEL_SHIFT) /* FTM2 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM3 (11 << TPM_CONF_TRGSEL_SHIFT) /* FTM3 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_RTC_ALRM (12 << TPM_CONF_TRGSEL_SHIFT) /* RTC Alarm */
# define TPM_CONF_TRGSEL_RTC_SECS (13 << TPM_CONF_TRGSEL_SHIFT) /* RTC Seconds */
# define TPM_CONF_TRGSEL_LPTMR (14 << TPM_CONF_TRGSEL_SHIFT) /* LPTMR trigger */
# define TPM_CONF_TRGSEL_SW (15 << TPM_CONF_TRGSEL_SHIFT) /* Software Trigger */
# define TPM_CONF_TRGSEL_EXTRG_IN (0 << TPM_CONF_TRGSEL_SHIFT) /* External trigger pin input */
# define TPM_CONF_TRGSEL_CMP0 (1 << TPM_CONF_TRGSEL_SHIFT) /* CPM0 output */
# define TPM_CONF_TRGSEL_CMP1 (2 << TPM_CONF_TRGSEL_SHIFT) /* CPM1 output */
# define TPM_CONF_TRGSEL_CMP2 (3 << TPM_CONF_TRGSEL_SHIFT) /* CPM2 output */
# define TPM_CONF_TRGSEL_PIT0 (4 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 0 */
# define TPM_CONF_TRGSEL_PIT1 (5 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 1 */
# define TPM_CONF_TRGSEL_PIT2 (6 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 2 */
# define TPM_CONF_TRGSEL_PIT3 (7 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 3 */
# define TPM_CONF_TRGSEL_FTM0 (8 << TPM_CONF_TRGSEL_SHIFT) /* FTM0 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM1 (9 << TPM_CONF_TRGSEL_SHIFT) /* FTM1 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM2 (10 << TPM_CONF_TRGSEL_SHIFT) /* FTM2 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_FTM3 (11 << TPM_CONF_TRGSEL_SHIFT) /* FTM3 initialization trigger and channel triggers */
# define TPM_CONF_TRGSEL_RTC_ALRM (12 << TPM_CONF_TRGSEL_SHIFT) /* RTC Alarm */
# define TPM_CONF_TRGSEL_RTC_SECS (13 << TPM_CONF_TRGSEL_SHIFT) /* RTC Seconds */
# define TPM_CONF_TRGSEL_LPTMR (14 << TPM_CONF_TRGSEL_SHIFT) /* LPTMR trigger */
# define TPM_CONF_TRGSEL_SW (15 << TPM_CONF_TRGSEL_SHIFT) /* Software Trigger */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_KX6TPM_H */

2
arch/arm/src/kinetis/hardware/kinetis_sim.h
View File

@ -639,7 +639,7 @@
#endif
/* Bits 13-14: Reserved */
#if defined(KINETIS_SIM_SOPT7_ADC1ALTTRGEN)
# define SIM_SOPT7_ADC1ALTTRGEN (1 << 15) /* Bit 15: ADC1 alternate trigger enable */
# define SIM_SOPT7_ADC1ALTTRGEN (1 << 15) /* Bit 15: ADC1 alternate trigger enable */
#endif
/* Bits 16-31: Reserved */
#if defined(KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL)

22
arch/arm/src/kinetis/kinetis_clockconfig.c
View File

@ -68,15 +68,15 @@
/* A board may provide BOARD_EXTAL_LP to not choose MCG_C2_HGO */
# if defined(BOARD_EXTAL_LP)
# define BOARD_MGC_C2_HGO 0 /* Do not use MCG_C2_HGO */
# else
# if !defined(KINETIS_MCG_HAS_C2_HGO)
# error BOARD_EXTAL_LP is not defined and MCG_C2_HGO is not supported on this SoC!
# else
# define BOARD_MGC_C2_HGO MCG_C2_HGO
# endif
# endif
# if defined(BOARD_EXTAL_LP)
# define BOARD_MGC_C2_HGO 0 /* Do not use MCG_C2_HGO */
# else
# if !defined(KINETIS_MCG_HAS_C2_HGO)
# error BOARD_EXTAL_LP is not defined and MCG_C2_HGO is not supported on this SoC!
# else
# define BOARD_MGC_C2_HGO MCG_C2_HGO
# endif
# endif
/* A board must provide BOARD_MCG_C2_FCFTRIM when SoC has the setting */
@ -97,11 +97,11 @@
/* A board must provide BOARD_MCG_C2_LOCRE0 when SoC has the setting */
# if defined(KINETIS_MCG_HAS_C2_LOCRE0) && !defined(BOARD_MCG_C2_LOCRE0)
# error MCG_C2_LOCRE0 is supported on this SoC and BOARD_MCG_C2_LOCRE0 is not defined!
# error MCG_C2_LOCRE0 is supported on this SoC and BOARD_MCG_C2_LOCRE0 is not defined!
# endif
# if !defined(KINETIS_MCG_HAS_C2_LOCRE0) && defined(BOARD_MCG_C2_LOCRE0)
# error BOARD_MCG_C2_LOCRE0 is defined but MCG_C2_LOCRE0 is not supported on this SoC!
# error BOARD_MCG_C2_LOCRE0 is defined but MCG_C2_LOCRE0 is not supported on this SoC!
# endif
/* Provide the 0 default */

2
arch/arm/src/kinetis/kinetis_config.h
View File

@ -334,7 +334,7 @@
#endif
#ifndef CONFIG_ENETNETHIFS
# define CONFIG_ENETNETHIFS 1
# define CONFIG_ENETNETHIFS 1
#endif
/****************************************************************************

156
arch/arm/src/kinetis/kinetis_serial.c
View File

@ -405,55 +405,55 @@ static const struct uart_ops_s g_uart_dma_ops =
#ifdef CONFIG_KINETIS_UART0
static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
# ifdef CONFIG_KINETIS_UART0_RXDMA
# ifdef CONFIG_KINETIS_UART0_RXDMA
static char g_uart0rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
# endif
#endif
#ifdef CONFIG_KINETIS_UART1
static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
# ifdef CONFIG_KINETIS_UART1_RXDMA
# ifdef CONFIG_KINETIS_UART1_RXDMA
static char g_uart1rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
# endif
#endif
#ifdef CONFIG_KINETIS_UART2
static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
# ifdef CONFIG_KINETIS_UART2_RXDMA
# ifdef CONFIG_KINETIS_UART2_RXDMA
static char g_uart2rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
# endif
#endif
#ifdef CONFIG_KINETIS_UART3
static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE];
static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE];
# ifdef CONFIG_KINETIS_UART3_RXDMA
# ifdef CONFIG_KINETIS_UART3_RXDMA
static char g_uart3rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
# endif
#endif
#ifdef CONFIG_KINETIS_UART4
static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE];
static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE];
# ifdef CONFIG_KINETIS_UART4_RXDMA
# ifdef CONFIG_KINETIS_UART4_RXDMA
static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
# endif
#endif
#ifdef CONFIG_KINETIS_UART5
static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE];
static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE];
# ifdef CONFIG_KINETIS_UART5_RXDMA
# ifdef CONFIG_KINETIS_UART5_RXDMA
static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
# endif
# endif
#endif
/* This describes the state of the Kinetis UART0 port. */
@ -464,25 +464,25 @@ static struct up_dev_s g_uart0priv =
.uartbase = KINETIS_UART0_BASE,
.clock = BOARD_CORECLK_FREQ,
.baud = CONFIG_UART0_BAUD,
#ifdef CONFIG_DEBUG_FEATURES
# ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART0E,
#endif
# endif
.irqs = KINETIS_IRQ_UART0S,
.parity = CONFIG_UART0_PARITY,
.bits = CONFIG_UART0_BITS,
.stop2 = CONFIG_UART0_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART0_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART0_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART0_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART0_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART0_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART0_RTS,
#endif
#ifdef CONFIG_KINETIS_UART0_RXDMA
# endif
# ifdef CONFIG_KINETIS_UART0_RXDMA
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART0_RX,
.rxfifo = g_uart0rxfifo,
#endif
# endif
};
static uart_dev_t g_uart0port =
@ -497,11 +497,11 @@ static uart_dev_t g_uart0port =
.size = CONFIG_UART0_TXBUFSIZE,
.buffer = g_uart0txbuffer,
},
#ifdef CONFIG_KINETIS_UART0_RXDMA
# ifdef CONFIG_KINETIS_UART0_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart0priv,
};
#endif
@ -514,25 +514,25 @@ static struct up_dev_s g_uart1priv =
.uartbase = KINETIS_UART1_BASE,
.clock = BOARD_CORECLK_FREQ,
.baud = CONFIG_UART1_BAUD,
#ifdef CONFIG_DEBUG_FEATURES
# ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART1E,
#endif
# endif
.irqs = KINETIS_IRQ_UART1S,
.parity = CONFIG_UART1_PARITY,
.bits = CONFIG_UART1_BITS,
.stop2 = CONFIG_UART1_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART1_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART1_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART1_RTS,
#endif
#ifdef CONFIG_KINETIS_UART1_RXDMA
# endif
# ifdef CONFIG_KINETIS_UART1_RXDMA
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART1_RX,
.rxfifo = g_uart1rxfifo,
#endif
# endif
};
static uart_dev_t g_uart1port =
@ -547,11 +547,11 @@ static uart_dev_t g_uart1port =
.size = CONFIG_UART1_TXBUFSIZE,
.buffer = g_uart1txbuffer,
},
#ifdef CONFIG_KINETIS_UART1_RXDMA
# ifdef CONFIG_KINETIS_UART1_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart1priv,
};
#endif
@ -564,25 +564,25 @@ static struct up_dev_s g_uart2priv =
.uartbase = KINETIS_UART2_BASE,
.clock = BOARD_BUS_FREQ,
.baud = CONFIG_UART2_BAUD,
#ifdef CONFIG_DEBUG_FEATURES
# ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART2E,
#endif
# endif
.irqs = KINETIS_IRQ_UART2S,
.parity = CONFIG_UART2_PARITY,
.bits = CONFIG_UART2_BITS,
.stop2 = CONFIG_UART2_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART2_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART2_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART2_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART2_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART2_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART2_RTS,
#endif
#ifdef CONFIG_KINETIS_UART2_RXDMA
# endif
# ifdef CONFIG_KINETIS_UART2_RXDMA
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART2_RX,
.rxfifo = g_uart2rxfifo,
#endif
# endif
};
static uart_dev_t g_uart2port =
@ -597,11 +597,11 @@ static uart_dev_t g_uart2port =
.size = CONFIG_UART2_TXBUFSIZE,
.buffer = g_uart2txbuffer,
},
#ifdef CONFIG_KINETIS_UART2_RXDMA
# ifdef CONFIG_KINETIS_UART2_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart2priv,
};
#endif
@ -614,25 +614,25 @@ static struct up_dev_s g_uart3priv =
.uartbase = KINETIS_UART3_BASE,
.clock = BOARD_BUS_FREQ,
.baud = CONFIG_UART3_BAUD,
#ifdef CONFIG_DEBUG_FEATURES
# ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART3E,
#endif
# endif
.irqs = KINETIS_IRQ_UART3S,
.parity = CONFIG_UART3_PARITY,
.bits = CONFIG_UART3_BITS,
.stop2 = CONFIG_UART3_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART3_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART3_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART3_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART3_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART3_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART3_RTS,
#endif
#ifdef CONFIG_KINETIS_UART3_RXDMA
# endif
# ifdef CONFIG_KINETIS_UART3_RXDMA
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART3_RX,
.rxfifo = g_uart3rxfifo,
#endif
# endif
};
static uart_dev_t g_uart3port =
@ -647,11 +647,11 @@ static uart_dev_t g_uart3port =
.size = CONFIG_UART3_TXBUFSIZE,
.buffer = g_uart3txbuffer,
},
#ifdef CONFIG_KINETIS_UART3_RXDMA
# ifdef CONFIG_KINETIS_UART3_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart3priv,
};
#endif
@ -664,25 +664,25 @@ static struct up_dev_s g_uart4priv =
.uartbase = KINETIS_UART4_BASE,
.clock = BOARD_BUS_FREQ,
.baud = CONFIG_UART4_BAUD,
#ifdef CONFIG_DEBUG_FEATURES
# ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART4E,
#endif
# endif
.irqs = KINETIS_IRQ_UART4S,
.parity = CONFIG_UART4_PARITY,
.bits = CONFIG_UART4_BITS,
.stop2 = CONFIG_UART4_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART4_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART4_RTS,
#endif
#ifdef CONFIG_KINETIS_UART4_RXDMA
# endif
# ifdef CONFIG_KINETIS_UART4_RXDMA
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART4_RXTX,
.rxfifo = g_uart4rxfifo,
#endif
# endif
};
static uart_dev_t g_uart4port =
@ -697,11 +697,11 @@ static uart_dev_t g_uart4port =
.size = CONFIG_UART4_TXBUFSIZE,
.buffer = g_uart4txbuffer,
},
#ifdef CONFIG_KINETIS_UART4_RXDMA
# ifdef CONFIG_KINETIS_UART4_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart4priv,
};
#endif
@ -714,25 +714,25 @@ static struct up_dev_s g_uart5priv =
.uartbase = KINETIS_UART5_BASE,
.clock = BOARD_BUS_FREQ,
.baud = CONFIG_UART5_BAUD,
#ifdef CONFIG_DEBUG_FEATURES
# ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART5E,
#endif
# endif
.irqs = KINETIS_IRQ_UART5S,
.parity = CONFIG_UART5_PARITY,
.bits = CONFIG_UART5_BITS,
.stop2 = CONFIG_UART5_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART5_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART5_RTS,
#endif
#ifdef CONFIG_KINETIS_UART5_RXDMA
# endif
# ifdef CONFIG_KINETIS_UART5_RXDMA
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART5_RX,
.rxfifo = g_uart5rxfifo,
#endif
# endif
};
static uart_dev_t g_uart5port =
@ -747,11 +747,11 @@ static uart_dev_t g_uart5port =
.size = CONFIG_UART5_TXBUFSIZE,
.buffer = g_uart5txbuffer,
},
#ifdef CONFIG_KINETIS_UART5_RXDMA
# ifdef CONFIG_KINETIS_UART5_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart5priv,
};
#endif

104
arch/arm/src/kl/hardware/kl_memorymap.h
View File

@ -41,81 +41,81 @@
* K40P144M100SF2RM
*/
# define KL_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
# define KL_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
# define KL_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
# define KL_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
# define KL_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
# define KL_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * -0x3fffffff Reserved */
# define KIP_AIPS_BASE 0x40000000 /* -0x4007ffff AIPS Peripherals */
# define KIP_AIPS_BASE 0x40000000 /* -0x4007ffff AIPS Peripherals */
/* 0x40080000 * -0x400fffff Reserved */
# define KL_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
# define KL_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
/* 0x40100000 * -0x43ffffff Reserved */
# define KL_BME_BASE 0x44000000 /* -0x5fffffff Bit Manipulation Engine (BME) access
# define KL_BME_BASE 0x44000000 /* -0x5fffffff Bit Manipulation Engine (BME) access
* to AIPS Peripherals for slots 0-127 */
/* 0x60000000 * -0xdfffffff Reserved */
# define KL_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
# define KL_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
/* 0xe0100000 * -0xefffffff Reserved */
# define KL_MTB_BASE 0xf0000000 /* -0xffffffff Micro Trace Buffer (MTB) registers */
# define KL_MTB_BASE 0xf0000000 /* -0xffffffff Micro Trace Buffer (MTB) registers */
/* AIPS Memory Map **********************************************************/
# define KL_DMAC_BASE 0x40008000 /* DMA controller */
# define KL_AIPSGPIO_BASE 0x4000f000 /* GPIO controller (aliased to 0x400ff000) */
# define KL_FTFL_BASE 0x40020000 /* Flash memory */
# define KL_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */
# define KL_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
# define KL_TPM0_BASE 0x40038000 /* Timer/PWM (TPM) 0 */
# define KL_TPM1_BASE 0x40039000 /* Timer/PWM (TPM) 1 */
# define KL_TPM2_BASE 0x4003a000 /* Timer/PWM (TPM) 2 */
# define KL_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KL_RTC_BASE 0x4003d000 /* Real time clock */
# define KL_DAC0_BASE 0x4003f000 /* Digital-to-analog convert (DAC) 0 */
# define KL_LPTMR_BASE 0x40040000 /* Low power timer */
# define KL_TSI_BASE 0x40045000 /* Touch sense interface */
# define KL_SIMLP_BASE 0x40047000 /* SIM low-power logic */
# define KL_SIM_BASE 0x40048000 /* System integration module (SIM) */
# define KL_PORT_BASE(n) (0x40049000 + ((n) << 12))
# define KL_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define KL_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define KL_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define KL_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define KL_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define KL_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
# define KL_OSC_BASE 0x40065000 /* System oscillator (OSC) */
# define KL_I2C0_BASE 0x40066000 /* I2C 0 */
# define KL_I2C1_BASE 0x40067000 /* I2C 1 */
# define KL_UART0_BASE 0x4006a000 /* UART0 */
# define KL_UART1_BASE 0x4006b000 /* UART1 */
# define KL_UART2_BASE 0x4006c000 /* UART2 */
# define KL_USB0_BASE 0x40072000 /* USB OTG FS/LS */
# define KL_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
# define KL_SPI0_BASE 0x40076000 /* SPI 0 */
# define KL_SPI1_BASE 0x40077000 /* SPI 1 */
# define KL_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
# define KL_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KL_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
# define KL_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */
# define KL_DMAC_BASE 0x40008000 /* DMA controller */
# define KL_AIPSGPIO_BASE 0x4000f000 /* GPIO controller (aliased to 0x400ff000) */
# define KL_FTFL_BASE 0x40020000 /* Flash memory */
# define KL_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */
# define KL_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
# define KL_TPM0_BASE 0x40038000 /* Timer/PWM (TPM) 0 */
# define KL_TPM1_BASE 0x40039000 /* Timer/PWM (TPM) 1 */
# define KL_TPM2_BASE 0x4003a000 /* Timer/PWM (TPM) 2 */
# define KL_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */
# define KL_RTC_BASE 0x4003d000 /* Real time clock */
# define KL_DAC0_BASE 0x4003f000 /* Digital-to-analog convert (DAC) 0 */
# define KL_LPTMR_BASE 0x40040000 /* Low power timer */
# define KL_TSI_BASE 0x40045000 /* Touch sense interface */
# define KL_SIMLP_BASE 0x40047000 /* SIM low-power logic */
# define KL_SIM_BASE 0x40048000 /* System integration module (SIM) */
# define KL_PORT_BASE(n) (0x40049000 + ((n) << 12))
# define KL_PORTA_BASE 0x40049000 /* Port A multiplexing control */
# define KL_PORTB_BASE 0x4004a000 /* Port B multiplexing control */
# define KL_PORTC_BASE 0x4004b000 /* Port C multiplexing control */
# define KL_PORTD_BASE 0x4004c000 /* Port D multiplexing control */
# define KL_PORTE_BASE 0x4004d000 /* Port E multiplexing control */
# define KL_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */
# define KL_OSC_BASE 0x40065000 /* System oscillator (OSC) */
# define KL_I2C0_BASE 0x40066000 /* I2C 0 */
# define KL_I2C1_BASE 0x40067000 /* I2C 1 */
# define KL_UART0_BASE 0x4006a000 /* UART0 */
# define KL_UART1_BASE 0x4006b000 /* UART1 */
# define KL_UART2_BASE 0x4006c000 /* UART2 */
# define KL_USB0_BASE 0x40072000 /* USB OTG FS/LS */
# define KL_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */
# define KL_SPI0_BASE 0x40076000 /* SPI 0 */
# define KL_SPI1_BASE 0x40077000 /* SPI 1 */
# define KL_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */
# define KL_PMC_BASE 0x4007d000 /* Power management controller (PMC) */
# define KL_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
# define KL_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */
/* 0x400ff000 * GPIO Controller */
# define KL_GPIOn_BASE(n) (0x400ff000 + ((n) << 6))
# define KL_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
# define KL_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
# define KL_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
# define KL_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KL_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
# define KL_GPIOn_BASE(n) (0x400ff000 + ((n) << 6))
# define KL_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
# define KL_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
# define KL_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
# define KL_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KL_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map **********************************/
# define KL_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
# define KL_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
# define KL_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */
# define KL_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
/****************************************************************************
* Public Types

54
arch/arm/src/kl/hardware/kl_tpm.h
View File

@ -114,22 +114,22 @@
#define TPM_SC_PS_SHIFT 0 /* Bits 0-2: Prescale Factor Selection */
#define TPM_SC_PS_MASK (7 << TPM_SC_PS_SHIFT)
# define TPM_SC_PS_DIV1 (0 << TPM_SC_PS_SHIFT) /* Divide Clock by 1 */
# define TPM_SC_PS_DIV2 (1 << TPM_SC_PS_SHIFT) /* Divide Clock by 2 */
# define TPM_SC_PS_DIV4 (2 << TPM_SC_PS_SHIFT) /* Divide Clock by 4 */
# define TPM_SC_PS_DIV8 (3 << TPM_SC_PS_SHIFT) /* Divide Clock by 8 */
# define TPM_SC_PS_DIV16 (4 << TPM_SC_PS_SHIFT) /* Divide Clock by 16 */
# define TPM_SC_PS_DIV32 (5 << TPM_SC_PS_SHIFT) /* Divide Clock by 32 */
# define TPM_SC_PS_DIV64 (6 << TPM_SC_PS_SHIFT) /* Divide Clock by 64 */
# define TPM_SC_PS_DIV128 (7 << TPM_SC_PS_SHIFT) /* Divide Clock by 128 */
# define TPM_SC_PS_DIV1 (0 << TPM_SC_PS_SHIFT) /* Divide Clock by 1 */
# define TPM_SC_PS_DIV2 (1 << TPM_SC_PS_SHIFT) /* Divide Clock by 2 */
# define TPM_SC_PS_DIV4 (2 << TPM_SC_PS_SHIFT) /* Divide Clock by 4 */
# define TPM_SC_PS_DIV8 (3 << TPM_SC_PS_SHIFT) /* Divide Clock by 8 */
# define TPM_SC_PS_DIV16 (4 << TPM_SC_PS_SHIFT) /* Divide Clock by 16 */
# define TPM_SC_PS_DIV32 (5 << TPM_SC_PS_SHIFT) /* Divide Clock by 32 */
# define TPM_SC_PS_DIV64 (6 << TPM_SC_PS_SHIFT) /* Divide Clock by 64 */
# define TPM_SC_PS_DIV128 (7 << TPM_SC_PS_SHIFT) /* Divide Clock by 128 */
#define TPM_SC_CMOD_SHIFT 3 /* Bits 3-4: Clock Mode Selection */
#define TPM_SC_CMOD_MASK (3 << TPM_SC_CMOD_SHIFT)
# define TPM_SC_CMOD_DIS (0 << TPM_SC_CMOD_SHIFT) /* TPM counter is disabled */
# define TPM_SC_CMOD_LPTPM_CLK (1 << TPM_SC_CMOD_SHIFT) /* TPM increments on every counter clock */
# define TPM_SC_CMOD_LPTPM_EXTCLK (2 << TPM_SC_CMOD_SHIFT) /* TPM increments on rising edge of EXTCLK */
# define TPM_SC_CMOD_RESERV (3 << TPM_SC_CMOD_SHIFT) /* Reserved */
#define TPM_SC_CMOD_MASK (3 << TPM_SC_CMOD_SHIFT)
# define TPM_SC_CMOD_DIS (0 << TPM_SC_CMOD_SHIFT) /* TPM counter is disabled */
# define TPM_SC_CMOD_LPTPM_CLK (1 << TPM_SC_CMOD_SHIFT) /* TPM increments on every counter clock */
# define TPM_SC_CMOD_LPTPM_EXTCLK (2 << TPM_SC_CMOD_SHIFT) /* TPM increments on rising edge of EXTCLK */
# define TPM_SC_CMOD_RESERV (3 << TPM_SC_CMOD_SHIFT) /* Reserved */
#define TPM_SC_CPWMS (1 << 5) /* Bit 5: Center-aligned PWM Select */
#define TPM_SC_TOIE (1 << 6) /* Bit 6: Timer Overflow Interrupt Enable */
@ -158,8 +158,8 @@
#define TPM_CONF_DOZEEN 5 /* Bit 5: Doze Enable */
#define TPM_CONF_DBGMODE_SHIFT 6 /* Bits 6-7: Debug Mode */
#define TPM_CONF_DBGMODE_MASK (3 << TPM_DBGMODE_SHIFT)
# define TPM_CONF_DBGMODE_PAUSE (0 << TPM_DBGMODE_SHIFT) /* TPM counter will pause during DEBUG mode */
# define TPM_CONF_DBGMODE_CONT (3 << TPM_DBGMODE_SHIFT) /* TPM counter continue working in DEBUG mode */
# define TPM_CONF_DBGMODE_PAUSE (0 << TPM_DBGMODE_SHIFT) /* TPM counter will pause during DEBUG mode */
# define TPM_CONF_DBGMODE_CONT (3 << TPM_DBGMODE_SHIFT) /* TPM counter continue working in DEBUG mode */
/* Bit 8: Reserved */
#define TPM_CONF_GTBEEN (1 << 9) /* Bit 9: Global Time Base Enable */
@ -168,31 +168,31 @@
#define TPM_CONF_CSOO (1 << 17) /* Bit 17: Counter Stop On Overflow */
#define TPM_CONF_CROT (1 << 18) /* Bit 18: Counter Reload On Trigger */
/* Bits 19-23: Reserved */
#define TPM_CONF_TRGSEL_SHIFT 24
#define TPM_CONF_TRGSEL_MASK (15 << TPM_CONF_TRGSEL_SHIFT)
# define TPM_CONF_TRGSEL_EXTRG_IN (0 << TPM_CONF_TRGSEL_SHIFT) /* External trigger pin input */
# define TPM_CONF_TRGSEL_CMP0 (1 << TPM_CONF_TRGSEL_SHIFT) /* CPM0 output */
#define TPM_CONF_TRGSEL_SHIFT 24
#define TPM_CONF_TRGSEL_MASK (15 << TPM_CONF_TRGSEL_SHIFT)
# define TPM_CONF_TRGSEL_EXTRG_IN (0 << TPM_CONF_TRGSEL_SHIFT) /* External trigger pin input */
# define TPM_CONF_TRGSEL_CMP0 (1 << TPM_CONF_TRGSEL_SHIFT) /* CPM0 output */
/* (2 << TPM_CONF_TRGSEL_SHIFT) Reserved */
/* (3 << TPM_CONF_TRGSEL_SHIFT) Reserved */
# define TPM_CONF_TRGSEL_PIT0 (4 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 0 */
# define TPM_CONF_TRGSEL_PIT1 (5 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 1 */
# define TPM_CONF_TRGSEL_PIT0 (4 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 0 */
# define TPM_CONF_TRGSEL_PIT1 (5 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 1 */
/* (6 << TPM_CONF_TRGSEL_SHIFT) Reserved */
/* (7 << TPM_CONF_TRGSEL_SHIFT) Reserved */
# define TPM_CONF_TRGSEL_TPM0 (8 << TPM_CONF_TRGSEL_SHIFT) /* TPM0 Overflow */
# define TPM_CONF_TRGSEL_TPM1 (9 << TPM_CONF_TRGSEL_SHIFT) /* TPM1 Overflow */
# define TPM_CONF_TRGSEL_TPM2 (10 << TPM_CONF_TRGSEL_SHIFT) /* TPM1 Overflow */
# define TPM_CONF_TRGSEL_TPM0 (8 << TPM_CONF_TRGSEL_SHIFT) /* TPM0 Overflow */
# define TPM_CONF_TRGSEL_TPM1 (9 << TPM_CONF_TRGSEL_SHIFT) /* TPM1 Overflow */
# define TPM_CONF_TRGSEL_TPM2 (10 << TPM_CONF_TRGSEL_SHIFT) /* TPM1 Overflow */
/* (11 << TPM_CONF_TRGSEL_SHIFT) Reserved */
# define TPM_CONF_TRGSEL_RTC_ALRM (12 << TPM_CONF_TRGSEL_SHIFT) /* RTC Alarm */
# define TPM_CONF_TRGSEL_RTC_SECS (13 << TPM_CONF_TRGSEL_SHIFT) /* RTC Seconds */
# define TPM_CONF_TRGSEL_LPTMR (14 << TPM_CONF_TRGSEL_SHIFT) /* LPTMR trigger */
# define TPM_CONF_TRGSEL_RTC_ALRM (12 << TPM_CONF_TRGSEL_SHIFT) /* RTC Alarm */
# define TPM_CONF_TRGSEL_RTC_SECS (13 << TPM_CONF_TRGSEL_SHIFT) /* RTC Seconds */
# define TPM_CONF_TRGSEL_LPTMR (14 << TPM_CONF_TRGSEL_SHIFT) /* LPTMR trigger */
/* (15 << TPM_CONF_TRGSEL_SHIFT) Reserved */

4
arch/arm/src/lc823450/lc823450_syscontrol.h
View File

@ -277,8 +277,8 @@ void lc823450_clock_dump(void);
void mod_stby_regs(uint32_t clearbits, uint32_t setbits);
void lc823450_mod_stby_regs(uint32_t clearbits, uint32_t setbits);
#else
# define mod_stby_regs(...)
# define lc823450_mod_stby_regs(...)
# define mod_stby_regs(...)
# define lc823450_mod_stby_regs(...)
#endif
#if defined(__cplusplus)

16
arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_memorymap.h
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@ -50,15 +50,15 @@
/* Off chip Memory via External Memory Interface */
#define LPC17_40_EXTRAM_BASE 0x80000000 /* */
# define LPC17_40_EXTSRAM_CS0 0x80000000 /* Chip select 0 /up to 64MB/ */
# define LPC17_40_EXTSRAM_CS1 0x90000000 /* Chip select 1 /up to 64MB/ */
# define LPC17_40_EXTSRAM_CS2 0x98000000 /* Chip select 2 /up to 64MB/ */
# define LPC17_40_EXTSRAM_CS3 0x9c000000 /* Chip select 3 /up to 64MB/ */
# define LPC17_40_EXTSRAM_CS0 0x80000000 /* Chip select 0 /up to 64MB/ */
# define LPC17_40_EXTSRAM_CS1 0x90000000 /* Chip select 1 /up to 64MB/ */
# define LPC17_40_EXTSRAM_CS2 0x98000000 /* Chip select 2 /up to 64MB/ */
# define LPC17_40_EXTSRAM_CS3 0x9c000000 /* Chip select 3 /up to 64MB/ */
# define LPC17_40_EXTDRAM_CS0 0xa0000000 /* Chip select 0 /up to 256MB/ */
# define LPC17_40_EXTDRAM_CS1 0xb0000000 /* Chip select 1 /up to 256MB/ */
# define LPC17_40_EXTDRAM_CS2 0xc0000000 /* Chip select 2 /up to 256MB/ */
# define LPC17_40_EXTDRAM_CS3 0xd0000000 /* Chip select 3 /up to 256MB/ */
# define LPC17_40_EXTDRAM_CS0 0xa0000000 /* Chip select 0 /up to 256MB/ */
# define LPC17_40_EXTDRAM_CS1 0xb0000000 /* Chip select 1 /up to 256MB/ */
# define LPC17_40_EXTDRAM_CS2 0xc0000000 /* Chip select 2 /up to 256MB/ */
# define LPC17_40_EXTDRAM_CS3 0xd0000000 /* Chip select 3 /up to 256MB/ */
#define LPC17_40_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
#define LPC17_40_SCS_BASE 0xe000e000

16
arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h
View File

@ -373,7 +373,7 @@
#define SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT (0) /* Bits 0-4: divide value for SPIFI clock */
#define SYSCON_SPIFICLKSEL_SPIFIDIV_MASK (0x1f << SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT)
# define SYSCON_SPIFICLKSEL_SPIFIDIV(n) ((n-1) << SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT) /* n = 2 - 31 */
# define SYSCON_SPIFICLKSEL_SPIFIDIV(n) ((n-1) << SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT) /* n = 2 - 31 */
/* Bits 5-7: Reserved */
#define SYSCON_SPIFICLKSEL_SPIFISEL_SHIFT (8) /* Bits 8-9: Selects input clock for SPIFI clock divider */
@ -509,10 +509,10 @@
/* System control registers -- Matrix Arbitration Priorities */
# define SYSCON_MATRIXARB_PRI_LOWEST (0)
# define SYSCON_MATRIXARB_PRI_LOW (1)
# define SYSCON_MATRIXARB_PRI_HIGH (2)
# define SYSCON_MATRIXARB_PRI_HIGHEST (3)
# define SYSCON_MATRIXARB_PRI_LOWEST (0)
# define SYSCON_MATRIXARB_PRI_LOW (1)
# define SYSCON_MATRIXARB_PRI_HIGH (2)
# define SYSCON_MATRIXARB_PRI_HIGHEST (3)
#define SYSCON_MATRIXARB_PRI_ICODE_SHIFT (0) /* Bits 0-1: I-Code bus priority (should be lower than D-Code) */
#define SYSCON_MATRIXARB_PRI_ICODE_MASK (3 << SYSCON_MATRIXARB_PRI_ICODE_SHIFT)
@ -642,7 +642,7 @@
/* Delay values multiplied by 250 picoseconds */
#define SYSCON_EMCDLYCTL_CMDDLY_SHIFT (0) /* Bits 0-4: Delay value for EMC outputs in command delayed mode */
#define SYSCON_EMCDLYCTL_CMDDLY_MASK (0x1f << SYSCON_EMCDLYCTL_CMDDLY_SHIFT)
# define SYSCON_EMCDLYCTL_CMDDLY(n) ((n-1) << SYSCON_EMCDLYCTL_CMDDLY_SHIFT) /* n = 3 - 32 */
# define SYSCON_EMCDLYCTL_CMDDLY(n) ((n-1) << SYSCON_EMCDLYCTL_CMDDLY_SHIFT) /* n = 3 - 32 */
/* Bits 5-7: Reserved */
#define SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT (8) /* Bits 8-12: Delay value for the feedback clock that controls input data sampling */
@ -652,12 +652,12 @@
/* Bits 13-15: Reserved */
#define SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT (16) /* Bits 16-20: Delay value for the CLKOUT0 output */
#define SYSCON_EMCDLYCTL_CLKOUT0DLY_MASK (0x1f << SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT)
# define SYSCON_EMCDLYCTL_CLKOUT0DLY(n) ((n-1) << SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT) /* n = 3 - 32 */
# define SYSCON_EMCDLYCTL_CLKOUT0DLY(n) ((n-1) << SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT) /* n = 3 - 32 */
/* Bits 21-23: Reserved */
#define SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT (24) /* Bits 24-28: Delay value for the CLKOUT1 output */
#define SYSCON_EMCDLYCTL_CLKOUT1DLY_MASK (0x1f << SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT)
# define SYSCON_EMCDLYCTL_CLKOUT1DLY(n) ((n-1) << SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT) /* n = 3 - 32 */
# define SYSCON_EMCDLYCTL_CLKOUT1DLY(n) ((n-1) << SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT) /* n = 3 - 32 */
/* Bits 29-31: Reserved */

44
arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_can.h
View File

@ -321,28 +321,28 @@
/* Bits 11-15: Reserved */
#define CAN_ICR_ERRBIT_SHIFT (16) /* Bits 16-20: Error Code Capture */
#define CAN_ICR_ERRBIT_MASK (0x1f << CAN_ICR_ERRBIT_SHIFT)
# define CAN_ICR_ERRBIT_SOF (3 << CAN_ICR_ERRBIT_SHIFT) /* Start of Frame */
# define CAN_ICR_ERRBIT_ID28 (2 << CAN_ICR_ERRBIT_SHIFT) /* ID28 ... ID21 */
# define CAN_ICR_ERRBIT_SRTR (4 << CAN_ICR_ERRBIT_SHIFT) /* SRTR Bit */
# define CAN_ICR_ERRBIT_IDE (5 << CAN_ICR_ERRBIT_SHIFT) /* DE bit */
# define CAN_ICR_ERRBIT_ID20 (6 << CAN_ICR_ERRBIT_SHIFT) /* ID20 ... ID18 */
# define CAN_ICR_ERRBIT_ID17 (7 << CAN_ICR_ERRBIT_SHIFT) /* ID17 ... 13 */
# define CAN_ICR_ERRBIT_CRC (8 << CAN_ICR_ERRBIT_SHIFT) /* CRC Sequence */
# define CAN_ICR_ERRBIT_DATA (10 << CAN_ICR_ERRBIT_SHIFT) /* Data Field */
# define CAN_ICR_ERRBIT_LEN (11 << CAN_ICR_ERRBIT_SHIFT) /* Data Length Code */
# define CAN_ICR_ERRBIT_ RTR (12 << CAN_ICR_ERRBIT_SHIFT) /* RTR Bit */
# define CAN_ICR_ERRBIT_ID4 (14 << CAN_ICR_ERRBIT_SHIFT) /* ID4 ... ID0 */
# define CAN_ICR_ERRBIT_ID12 (15 << CAN_ICR_ERRBIT_SHIFT) /* ID12 ... ID5 */
# define CAN_ICR_ERRBIT_AERR (17 << CAN_ICR_ERRBIT_SHIFT) /* Active Error Flag */
# define CAN_ICR_ERRBIT_INTERMSN (18 << CAN_ICR_ERRBIT_SHIFT) /* Intermission */
# define CAN_ICR_ERRBIT_DOM (19 << CAN_ICR_ERRBIT_SHIFT) /* Tolerate Dominant Bits */
# define CAN_ICR_ERRBIT_PERR (22 << CAN_ICR_ERRBIT_SHIFT) /* Passive Error Flag */
# define CAN_ICR_ERRBIT_ERRDLM (23 << CAN_ICR_ERRBIT_SHIFT) /* Error Delimiter */
# define CAN_ICR_ERRBIT_CRCDLM (24 << CAN_ICR_ERRBIT_SHIFT) /* CRC Delimiter */
# define CAN_ICR_ERRBIT_ACKSLT (25 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Slot */
# define CAN_ICR_ERRBIT_EOF (26 << CAN_ICR_ERRBIT_SHIFT) /* End of Frame */
# define CAN_ICR_ERRBIT_ACKDLM (27 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Delimiter */
# define CAN_ICR_ERRBIT_OVLD (28 << CAN_ICR_ERRBIT_SHIFT) /* Overload flag */
# define CAN_ICR_ERRBIT_SOF (3 << CAN_ICR_ERRBIT_SHIFT) /* Start of Frame */
# define CAN_ICR_ERRBIT_ID28 (2 << CAN_ICR_ERRBIT_SHIFT) /* ID28 ... ID21 */
# define CAN_ICR_ERRBIT_SRTR (4 << CAN_ICR_ERRBIT_SHIFT) /* SRTR Bit */
# define CAN_ICR_ERRBIT_IDE (5 << CAN_ICR_ERRBIT_SHIFT) /* DE bit */
# define CAN_ICR_ERRBIT_ID20 (6 << CAN_ICR_ERRBIT_SHIFT) /* ID20 ... ID18 */
# define CAN_ICR_ERRBIT_ID17 (7 << CAN_ICR_ERRBIT_SHIFT) /* ID17 ... 13 */
# define CAN_ICR_ERRBIT_CRC (8 << CAN_ICR_ERRBIT_SHIFT) /* CRC Sequence */
# define CAN_ICR_ERRBIT_DATA (10 << CAN_ICR_ERRBIT_SHIFT) /* Data Field */
# define CAN_ICR_ERRBIT_LEN (11 << CAN_ICR_ERRBIT_SHIFT) /* Data Length Code */
# define CAN_ICR_ERRBIT_ RTR (12 << CAN_ICR_ERRBIT_SHIFT) /* RTR Bit */
# define CAN_ICR_ERRBIT_ID4 (14 << CAN_ICR_ERRBIT_SHIFT) /* ID4 ... ID0 */
# define CAN_ICR_ERRBIT_ID12 (15 << CAN_ICR_ERRBIT_SHIFT) /* ID12 ... ID5 */
# define CAN_ICR_ERRBIT_AERR (17 << CAN_ICR_ERRBIT_SHIFT) /* Active Error Flag */
# define CAN_ICR_ERRBIT_INTERMSN (18 << CAN_ICR_ERRBIT_SHIFT) /* Intermission */
# define CAN_ICR_ERRBIT_DOM (19 << CAN_ICR_ERRBIT_SHIFT) /* Tolerate Dominant Bits */
# define CAN_ICR_ERRBIT_PERR (22 << CAN_ICR_ERRBIT_SHIFT) /* Passive Error Flag */
# define CAN_ICR_ERRBIT_ERRDLM (23 << CAN_ICR_ERRBIT_SHIFT) /* Error Delimiter */
# define CAN_ICR_ERRBIT_CRCDLM (24 << CAN_ICR_ERRBIT_SHIFT) /* CRC Delimiter */
# define CAN_ICR_ERRBIT_ACKSLT (25 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Slot */
# define CAN_ICR_ERRBIT_EOF (26 << CAN_ICR_ERRBIT_SHIFT) /* End of Frame */
# define CAN_ICR_ERRBIT_ACKDLM (27 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Delimiter */
# define CAN_ICR_ERRBIT_OVLD (28 << CAN_ICR_ERRBIT_SHIFT) /* Overload flag */
#define CAN_ICR_ERRDIR (1 << 21) /* Bit 21: Direction bit at time of error */
#define CAN_ICR_ERRC_SHIFT (22) /* Bits 22-23: Type of error */

4
arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_wdt.h
View File

@ -121,14 +121,14 @@
/* Watchdog timer warning interrupt register */
#ifdef LPC178x_40xx
# define WDT_WARNINT (0x3ff) /* Bits 0-9: Warning Interrupt compare value */
# define WDT_WARNINT (0x3ff) /* Bits 0-9: Warning Interrupt compare value */
/* Bits 10-31: Reserved */
#endif
/* Watchdog timer value register */
#ifdef LPC178x_40xx
# define WDT_WINDOW (0xffffff) /* Bits 0-23: Watchdog window value */
# define WDT_WINDOW (0xffffff) /* Bits 0-23: Watchdog window value */
/* Bits 24-31: Reserved */
#endif

12
arch/arm/src/lpc17xx_40xx/lpc17_40_can.c
View File

@ -51,11 +51,11 @@
#include <nuttx/config.h>
#if defined(CONFIG_CAN)
# define CHRDEV_CAN
# define CHRDEV_CAN
#endif
#if defined(CONFIG_NET_CAN)
# define SOCKET_CAN
# define SOCKET_CAN
#endif
#include <stdio.h>
@ -343,13 +343,13 @@ static struct up_dev_s g_can1priv =
.baud = CONFIG_LPC17_40_CAN1_BAUD,
.base = LPC17_40_CAN1_BASE,
};
# if defined(CHRDEV_CAN)
# if defined(CHRDEV_CAN)
static struct lpc17_40_can_s g_can1dev =
{
.cd_ops = &g_canops,
.cd_priv = &g_can1priv,
};
# endif
# endif
#endif
#ifdef CONFIG_LPC17_40_CAN2
@ -360,13 +360,13 @@ static struct up_dev_s g_can2priv =
.baud = CONFIG_LPC17_40_CAN2_BAUD,
.base = LPC17_40_CAN2_BASE,
};
# if defined(CHRDEV_CAN)
# if defined(CHRDEV_CAN)
static struct lpc17_40_can_s g_can2dev =
{
.cd_ops = &g_canops,
.cd_priv = &g_can2priv,
};
# endif
# endif
#endif
#if defined(SOCKET_CAN)

10
arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c
View File

@ -340,8 +340,8 @@ static void lpc17_40_checkreg(uint32_t addr, uint32_t val, bool iswrite);
static uint32_t lpc17_40_getreg(uint32_t addr);
static void lpc17_40_putreg(uint32_t val, uint32_t addr);
#else
# define lpc17_40_getreg(addr) getreg32(addr)
# define lpc17_40_putreg(val,addr) putreg32(val,addr)
# define lpc17_40_getreg(addr) getreg32(addr)
# define lpc17_40_putreg(val,addr) putreg32(val,addr)
#endif
/* Common TX logic */
@ -1264,11 +1264,11 @@ static int lpc17_40_interrupt(int irq, void *context, void *arg)
/* Clear the pending interrupt */
#if 0 /* Apparently not necessary */
# if CONFIG_LPC17_40_NINTERFACES > 1
# if CONFIG_LPC17_40_NINTERFACES > 1
lpc17_40_clrpend(priv->irq);
# else
# else
lpc17_40_clrpend(LPC17_40_IRQ_ETH);
# endif
# endif
#endif
return OK;

2
arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c
View File

@ -142,7 +142,7 @@
#ifdef LPC178x_40xx
/* Use the global PCLK frequency */
# define CONSOLE_NUMERATOR BOARD_PCLK_FREQUENCY
# define CONSOLE_NUMERATOR BOARD_PCLK_FREQUENCY
#else
# ifdef CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER

4
arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c
View File

@ -365,8 +365,8 @@ static void lpc17_40_checkreg(uint32_t addr, uint32_t val, bool iswrite);
static uint32_t lpc17_40_getreg(uint32_t addr);
static void lpc17_40_putreg(uint32_t val, uint32_t addr);
#else
# define lpc17_40_getreg(addr) getreg32(addr)
# define lpc17_40_putreg(val,addr) putreg32(val,addr)
# define lpc17_40_getreg(addr) getreg32(addr)
# define lpc17_40_putreg(val,addr) putreg32(val,addr)
#endif
/* Command operations *******************************************************/

4
arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c
View File

@ -269,8 +269,8 @@ static void lpc17_40_checkreg(uint32_t addr, uint32_t val, bool iswrite);
static uint32_t lpc17_40_getreg(uint32_t addr);
static void lpc17_40_putreg(uint32_t val, uint32_t addr);
#else
# define lpc17_40_getreg(addr) getreg32(addr)
# define lpc17_40_putreg(val,addr) putreg32(val,addr)
# define lpc17_40_getreg(addr) getreg32(addr)
# define lpc17_40_putreg(val,addr) putreg32(val,addr)
#endif
/* Semaphores ***************************************************************/

4
arch/arm/src/lpc214x/lpc214x_usbdev.c
View File

@ -371,8 +371,8 @@ struct lpc214x_usbdev_s
static uint32_t lpc214x_getreg(uint32_t addr);
static void lpc214x_putreg(uint32_t val, uint32_t addr);
#else
# define lpc214x_getreg(addr) getreg32(addr)
# define lpc214x_putreg(val,addr) putreg32(val,addr)
# define lpc214x_getreg(addr) getreg32(addr)
# define lpc214x_putreg(val,addr) putreg32(val,addr)
#endif
/* Command operations *******************************************************/

28
arch/arm/src/lpc2378/lpc23xx_uart.h
View File

@ -91,26 +91,26 @@
/* PCKLSEL0 bits 7:6, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */
#ifdef U0_PCLKDIV
# if U0_PCLKDIV == 1
# define U0_PCLKSEL (0x00000040)
# elif U0_PCLKDIV == 2
# define U0_PCLKSEL (0x00000080)
# elif U0_PCLKDIV == 4
# define U0_PCLKSEL (0x00000000)
# endif
# if U0_PCLKDIV == 1
# define U0_PCLKSEL (0x00000040)
# elif U0_PCLKDIV == 2
# define U0_PCLKSEL (0x00000080)
# elif U0_PCLKDIV == 4
# define U0_PCLKSEL (0x00000000)
# endif
#else
# error "UART0 PCLK divider not set"
#endif
/* PCKLSEL1 bits 17:16, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */
#ifdef U2_PCLKDIV
# if U2_PCLKDIV == 1
# define U2_PCLKSEL (0x00010000)
# elif U2_PCLKDIV == 2
# define U2_PCLKSEL (0x00020000)
# elif U2_PCLKDIV == 4
# define U2_PCLKSEL (0x00000000)
# endif
# if U2_PCLKDIV == 1
# define U2_PCLKSEL (0x00010000)
# elif U2_PCLKDIV == 2
# define U2_PCLKSEL (0x00020000)
# elif U2_PCLKDIV == 4
# define U2_PCLKSEL (0x00000000)
# endif
#else
# error "UART2 PCLK divider not set"
#endif

2
arch/arm/src/lpc31xx/lpc31_memorymap.h
View File

@ -199,7 +199,7 @@
*/
#ifndef CONFIG_ARCH_ROMPGTABLE
# define LPC31_FIRST_VSECTION 0x00000000 /* Beginning of the virtual address space */
# define LPC31_FIRST_VSECTION 0x00000000 /* Beginning of the virtual address space */
# define LPC31_SHADOWSPACE_VSECTION 0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */
# define LPC31_INTSRAM_VSECTION 0x11028000 /* Internal SRAM 96Kb-192Kb */
# define LPC31_INTSRAM0_VADDR 0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */

4
arch/arm/src/lpc31xx/lpc31_usbdev.c
View File

@ -340,8 +340,8 @@ struct lpc31_usbdev_s
static uint32_t lpc31_getreg(uint32_t addr);
static void lpc31_putreg(uint32_t val, uint32_t addr);
#else
# define lpc31_getreg(addr) getreg32(addr)
# define lpc31_putreg(val,addr) putreg32(val,addr)
# define lpc31_getreg(addr) getreg32(addr)
# define lpc31_putreg(val,addr) putreg32(val,addr)
#endif
static inline void lpc31_clrbits(uint32_t mask, uint32_t addr);

8
arch/arm/src/lpc43xx/hardware/lpc43_gpdma.h
View File

@ -318,13 +318,13 @@
#define GPDMA_CONTROL_S_SHIFT (24) /* Bit 24: Source AHB master select */
# define GPDMA_CONTROL_S0 (0 << GPDMA_CONTROL_S_SHIFT) /* AHB Master 0 selected for source transfer. */
# define GPDMA_CONTROL_S1 (1 << GPDMA_CONTROL_S_SHIFT) /* AHB Master 1 selected for source transfer. */
# define GPDMA_CONTROL_S0 (0 << GPDMA_CONTROL_S_SHIFT) /* AHB Master 0 selected for source transfer. */
# define GPDMA_CONTROL_S1 (1 << GPDMA_CONTROL_S_SHIFT) /* AHB Master 1 selected for source transfer. */
#define GPDMA_CONTROL_D_SHIFT (25) /* Bit 25: Destination AHB master select */
# define GPDMA_CONTROL_D0 (0 << GPDMA_CONTROL_D_SHIFT) /* AHB Master 0 selected for destination transfer. */
# define GPDMA_CONTROL_D1 (1 << GPDMA_CONTROL_D_SHIFT) /* AHB Master 1 selected for destination transfer. */
# define GPDMA_CONTROL_D0 (0 << GPDMA_CONTROL_D_SHIFT) /* AHB Master 0 selected for destination transfer. */
# define GPDMA_CONTROL_D1 (1 << GPDMA_CONTROL_D_SHIFT) /* AHB Master 1 selected for destination transfer. */
#define GPDMA_CONTROL_SI (1 << 26) /* Bit 26: Source increment */
#define GPDMA_CONTROL_DI (1 << 27) /* Bit 27: Destination increment */

32
arch/arm/src/lpc43xx/hardware/lpc43_sct.h
View File

@ -1081,22 +1081,22 @@
#define SCT_CONFIG_CLKSEL_SHIFT (3) /* Bits 3-6: SCT clock select */
#define SCT_CONFIG_CLKSEL_MASK (15 << SCT_CONFIG_CLKSEL_SHIFT)
# define SCT_CONFIG_CLKSEL_REDGE0 (0 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 0 */
# define SCT_CONFIG_CLKSEL_FEDGE0 (1 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 0 */
# define SCT_CONFIG_CLKSEL_REDGE1 (2 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 1 */
# define SCT_CONFIG_CLKSEL_FEDGE1 (3 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 1 */
# define SCT_CONFIG_CLKSEL_REDGE2 (4 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 2 */
# define SCT_CONFIG_CLKSEL_FEDGE2 (5 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 2 */
# define SCT_CONFIG_CLKSEL_REDGE3 (6 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 3 */
# define SCT_CONFIG_CLKSEL_FEDGE3 (7 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 3 */
# define SCT_CONFIG_CLKSEL_REDGE4 (8 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 4 */
# define SCT_CONFIG_CLKSEL_FEDGE4 (9 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 4 */
# define SCT_CONFIG_CLKSEL_REDGE5 (10 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 5 */
# define SCT_CONFIG_CLKSEL_FEDGE5 (11 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 5 */
# define SCT_CONFIG_CLKSEL_REDGE6 (12 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 6 */
# define SCT_CONFIG_CLKSEL_FEDGE6 (13 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 6 */
# define SCT_CONFIG_CLKSEL_REDGE7 (14 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 7 */
# define SCT_CONFIG_CLKSEL_FEDGE7 (15 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 7 */
# define SCT_CONFIG_CLKSEL_REDGE0 (0 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 0 */
# define SCT_CONFIG_CLKSEL_FEDGE0 (1 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 0 */
# define SCT_CONFIG_CLKSEL_REDGE1 (2 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 1 */
# define SCT_CONFIG_CLKSEL_FEDGE1 (3 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 1 */
# define SCT_CONFIG_CLKSEL_REDGE2 (4 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 2 */
# define SCT_CONFIG_CLKSEL_FEDGE2 (5 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 2 */
# define SCT_CONFIG_CLKSEL_REDGE3 (6 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 3 */
# define SCT_CONFIG_CLKSEL_FEDGE3 (7 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 3 */
# define SCT_CONFIG_CLKSEL_REDGE4 (8 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 4 */
# define SCT_CONFIG_CLKSEL_FEDGE4 (9 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 4 */
# define SCT_CONFIG_CLKSEL_REDGE5 (10 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 5 */
# define SCT_CONFIG_CLKSEL_FEDGE5 (11 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 5 */
# define SCT_CONFIG_CLKSEL_REDGE6 (12 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 6 */
# define SCT_CONFIG_CLKSEL_FEDGE6 (13 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 6 */
# define SCT_CONFIG_CLKSEL_REDGE7 (14 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 7 */
# define SCT_CONFIG_CLKSEL_FEDGE7 (15 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 7 */
#define SCT_CONFIG_NORELOADU (1 << 7) /* Bit 7: Disable unified match register reload */
#define SCT_CONFIG_NORELOADL (1 << 7) /* Bit 7: Disable lower match registers reload */

6
arch/arm/src/lpc43xx/lpc43_ethernet.c
View File

@ -552,9 +552,9 @@ static uint32_t lpc43_getreg(uint32_t addr);
static void lpc43_putreg(uint32_t val, uint32_t addr);
static void lpc43_checksetup(void);
#else
# define lpc43_getreg(addr) getreg32(addr)
# define lpc43_putreg(val,addr) putreg32(val,addr)
# define lpc43_checksetup()
# define lpc43_getreg(addr) getreg32(addr)
# define lpc43_putreg(val,addr) putreg32(val,addr)
# define lpc43_checksetup()
#endif
/* Free buffer management */

4
arch/arm/src/lpc43xx/lpc43_sdmmc.c
View File

@ -245,8 +245,8 @@ struct lpc43_dev_s
static uint32_t lpc43_getreg(uint32_t addr);
static void lpc43_putreg(uint32_t val, uint32_t addr);
#else
# define lpc43_getreg(addr) getreg32(addr)
# define lpc43_putreg(val,addr) putreg32(val,addr)
# define lpc43_getreg(addr) getreg32(addr)
# define lpc43_putreg(val,addr) putreg32(val,addr)
#endif
/* Low-level helpers ********************************************************/

4
arch/arm/src/lpc43xx/lpc43_serial.c
View File

@ -341,7 +341,7 @@ static uart_dev_t g_usart3port =
# define CONSOLE_DEV g_usart3port /* USART3=console */
# define TTYS0_DEV g_usart3port /* USART3=ttyS0 */
# define USART3_ASSIGNED 1
# endif
# endif
#else
/* No console, assign only ttyS0 */
@ -357,7 +357,7 @@ static uart_dev_t g_usart3port =
# else /* elif defined(CONFIG_LPC43_USART3) */
# define TTYS0_DEV g_usart3port /* USART3=ttyS0 */
# define USART3_ASSIGNED 1
# endif
# endif
#endif
/* Assign ttyS1 */

4
arch/arm/src/lpc43xx/lpc43_timer.c
View File

@ -96,8 +96,8 @@ struct lpc43_lowerhalf_s
static uint32_t lpc43_getreg(uint32_t addr);
static void lpc43_putreg(uint32_t val, uint32_t addr);
#else
# define lpc43_getreg(addr) getreg32(addr)
# define lpc43_putreg(val,addr) putreg32(val,addr)
# define lpc43_getreg(addr) getreg32(addr)
# define lpc43_putreg(val,addr) putreg32(val,addr)
#endif
/* Interrupt handling *******************************************************/

4
arch/arm/src/lpc43xx/lpc43_usb0dev.c
View File

@ -344,8 +344,8 @@ struct lpc43_usbdev_s
static uint32_t lpc43_getreg(uint32_t addr);
static void lpc43_putreg(uint32_t val, uint32_t addr);
#else
# define lpc43_getreg(addr) getreg32(addr)
# define lpc43_putreg(val,addr) putreg32(val,addr)
# define lpc43_getreg(addr) getreg32(addr)
# define lpc43_putreg(val,addr) putreg32(val,addr)
#endif
static inline void lpc43_clrbits(uint32_t mask, uint32_t addr);

22
arch/arm/src/lpc54xx/hardware/lpc54_dma.h
View File

@ -134,17 +134,17 @@
#define DMA_CFG_TRIGBURST (1 << 6) /* Bit 6: Trigger Burst */
#define DMA_CFG_BURSTPOWER_SHIFT (8) /* Bits 8-11: Burst Power */
#define DMA_CFG_BURSTPOWER_MASK (15 << DMA_CFG_BURSTPOWER_SHIFT)
# define DMA_CFG_BURSTPOWER_1 (0 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 1 (2^0) */
# define DMA_CFG_BURSTPOWER_2 (1 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 2 (2^1) */
# define DMA_CFG_BURSTPOWER_3 (2 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 4 (2^2) */
# define DMA_CFG_BURSTPOWER_8 (3 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 8 (2^2) */
# define DMA_CFG_BURSTPOWER_16 (4 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 16 (2^2) */
# define DMA_CFG_BURSTPOWER_32 (5 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 32 (2^2) */
# define DMA_CFG_BURSTPOWER_64 (6 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 64 (2^2) */
# define DMA_CFG_BURSTPOWER_128 (7 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 128 (2^2) */
# define DMA_CFG_BURSTPOWER_256 (8 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 256 (2^2) */
# define DMA_CFG_BURSTPOWER_512 (9 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 256 (2^2) */
# define DMA_CFG_BURSTPOWER_1024 (10 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 1024 (2^10) */
# define DMA_CFG_BURSTPOWER_1 (0 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 1 (2^0) */
# define DMA_CFG_BURSTPOWER_2 (1 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 2 (2^1) */
# define DMA_CFG_BURSTPOWER_3 (2 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 4 (2^2) */
# define DMA_CFG_BURSTPOWER_8 (3 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 8 (2^2) */
# define DMA_CFG_BURSTPOWER_16 (4 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 16 (2^2) */
# define DMA_CFG_BURSTPOWER_32 (5 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 32 (2^2) */
# define DMA_CFG_BURSTPOWER_64 (6 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 64 (2^2) */
# define DMA_CFG_BURSTPOWER_128 (7 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 128 (2^2) */
# define DMA_CFG_BURSTPOWER_256 (8 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 256 (2^2) */
# define DMA_CFG_BURSTPOWER_512 (9 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 256 (2^2) */
# define DMA_CFG_BURSTPOWER_1024 (10 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 1024 (2^10) */
#define DMA_CFG_SRCBURSTWRAP (1 << 14) /* Bit 14: Source Burst Wrap */
#define DMA_CFG_DSTBURSTWRAP (1 << 15) /* Bit 15: Destination Burst Wrap */

14
arch/arm/src/lpc54xx/hardware/lpc54_ethernet.h
View File

@ -571,13 +571,13 @@
#define ETH_DMA_MODE_TXPR (1 << 11) /* Bit 11: Transmit priority */
#define ETH_DMA_MODE_PR_SHIFT (12) /* Bits 12-14: Priority ratio */
#define ETH_DMA_MODE_PR_MASK (7 << ETH_DMA_MODE_PR_SHIFT)
# define ETH_DMA_MODE_PR_1TO1 (0 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 1:1 */
# define ETH_DMA_MODE_PR_3TO1 (2 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 3:1 */
# define ETH_DMA_MODE_PR_4TO1 (3 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 4:1 */
# define ETH_DMA_MODE_PR_5TO1 (4 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 5:1 */
# define ETH_DMA_MODE_PR_6TO1 (5 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 6:1 */
# define ETH_DMA_MODE_PR_7TO1 (6 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 7:1 */
# define ETH_DMA_MODE_PR_8TO1 (7 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 8:1 */
# define ETH_DMA_MODE_PR_1TO1 (0 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 1:1 */
# define ETH_DMA_MODE_PR_3TO1 (2 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 3:1 */
# define ETH_DMA_MODE_PR_4TO1 (3 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 4:1 */
# define ETH_DMA_MODE_PR_5TO1 (4 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 5:1 */
# define ETH_DMA_MODE_PR_6TO1 (5 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 6:1 */
# define ETH_DMA_MODE_PR_7TO1 (6 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 7:1 */
# define ETH_DMA_MODE_PR_8TO1 (7 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 8:1 */
/* DMA system bus mode */

4
arch/arm/src/lpc54xx/lpc54_ethernet.c
View File

@ -370,8 +370,8 @@ static uint32_t *g_txbuffers1[CONFIG_LPC54_ETH_NTXDESC1];
static uint32_t lpc54_getreg(uintptr_t addr);
static void lpc54_putreg(uint32_t val, uintptr_t addr);
#else
# define lpc54_getreg(addr) getreg32(addr)
# define lpc54_putreg(val,addr) putreg32(val,addr)
# define lpc54_getreg(addr) getreg32(addr)
# define lpc54_putreg(val,addr) putreg32(val,addr)
#endif
/* Common TX logic */

4
arch/arm/src/lpc54xx/lpc54_sdmmc.c
View File

@ -245,8 +245,8 @@ struct lpc54_dev_s
static uint32_t lpc54_getreg(uint32_t addr);
static void lpc54_putreg(uint32_t val, uint32_t addr);
#else
# define lpc54_getreg(addr) getreg32(addr)
# define lpc54_putreg(val,addr) putreg32(val,addr)
# define lpc54_getreg(addr) getreg32(addr)
# define lpc54_putreg(val,addr) putreg32(val,addr)
#endif
/* Low-level helpers ********************************************************/

4
arch/arm/src/lpc54xx/lpc54_usb0_ohci.c
View File

@ -364,8 +364,8 @@ static void lpc54_checkreg(uint32_t addr, uint32_t val, bool iswrite);
static uint32_t lpc54_getreg(uint32_t addr);
static void lpc54_putreg(uint32_t val, uint32_t addr);
#else
# define lpc54_getreg(addr) getreg32(addr)
# define lpc54_putreg(val,addr) putreg32(val,addr)
# define lpc54_getreg(addr) getreg32(addr)
# define lpc54_putreg(val,addr) putreg32(val,addr)
#endif
/* Byte stream access helper functions **************************************/

8
arch/arm/src/phy62xx/phy62xx_hardfault.c
View File

@ -42,15 +42,15 @@ extern uint8_t _stextram[];
extern uint8_t _etextram[];
#ifdef CONFIG_DEBUG_HARDFAULT_ALERT
# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
# define hfalert(x...)
# define hfalert(x...)
#endif
#ifdef CONFIG_DEBUG_HARDFAULT_INFO
# define hfinfo(format, ...) _info(format, ##__VA_ARGS__)
# define hfinfo(format, ...) _info(format, ##__VA_ARGS__)
#else
# define hfinfo(x...)
# define hfinfo(x...)
#endif
#define INSN_SVC0 0xdf00 /* insn: svc 0 */

8
arch/arm/src/rp2040/hardware/rp2040_memorymap.h
View File

@ -113,10 +113,10 @@
#ifndef __ASSEMBLY__
# define xorbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_XOR_REG_OFFSET)
# define setbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_SET_REG_OFFSET)
# define clrbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_CLR_REG_OFFSET)
# define modbits_reg32(v,m,a) xorbits_reg32((getreg32(a) ^ (v)) & (m), a)
# define xorbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_XOR_REG_OFFSET)
# define setbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_SET_REG_OFFSET)
# define clrbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_CLR_REG_OFFSET)
# define modbits_reg32(v,m,a) xorbits_reg32((getreg32(a) ^ (v)) & (m), a)
/****************************************************************************
* Public Function Prototypes

12
arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h
View File

@ -514,13 +514,13 @@
*/
#ifdef S32K1XX_ENET_HAS_DBSWAP
# ifndef CONFIG_ENDIAN_BIG
# define S32K1XX_USE_DBSWAP
# endif
# ifndef CONFIG_ENDIAN_BIG
# define S32K1XX_USE_DBSWAP
# endif
#else
# ifndef CONFIG_ENDIAN_BIG
# define S32K1XX_BUFFERS_SWAP
# endif
# ifndef CONFIG_ENDIAN_BIG
# define S32K1XX_BUFFERS_SWAP
# endif
#endif
#ifndef S32K1XX_BUFFERS_SWAP

8
arch/arm/src/s32k1xx/hardware/s32k1xx_sim.h
View File

@ -190,8 +190,8 @@
/* ADC Options Register */
#define SIM_ADCOPT_ADC0TRGSEL (1 << 0) /* Bit 0: ADC0 trigger source select */
# define SIM_ADCOPT_ADC0TRGSEL_PDB (0) /* PDB output */
# define SIM_ADCOPT_ADC0TRGSEL_TRGMUX (1 << 0) /* TRGMUX output */
# define SIM_ADCOPT_ADC0TRGSEL_PDB (0) /* PDB output */
# define SIM_ADCOPT_ADC0TRGSEL_TRGMUX (1 << 0) /* TRGMUX output */
#define SIM_ADCOPT_ADC0SWPRETRG_SHIFT (1) /* Bits 1-3: ADC0 software pretrigger sources */
#define SIM_ADCOPT_ADC0SWPRETRG_MASK (7 << SIM_ADCOPT_ADC0SWPRETRG_SHIFT)
# define SIM_ADCOPT_ADC0SWPRETRG_DISABLED (0 << SIM_ADCOPT_ADC0SWPRETRG_SHIFT) /* Software pretrigger disabled */
@ -207,8 +207,8 @@
# define SIM_ADCOPT_ADC0PRETRGSEL_SW (2 << SIM_ADCOPT_ADC0PRETRGSEL_SHIFT) /* Software pretrigger */
#define SIM_ADCOPT_ADC1TRGSEL (1 << 8) /* Bit 8: ADC1 trigger source select */
# define SIM_ADCOPT_ADC1TRGSEL_PDB (0) /* PDB output */
# define SIM_ADCOPT_ADC1TRGSEL_TRGMUX (1 << 8) /* TRGMUX output */
# define SIM_ADCOPT_ADC1TRGSEL_PDB (0) /* PDB output */
# define SIM_ADCOPT_ADC1TRGSEL_TRGMUX (1 << 8) /* TRGMUX output */
#define SIM_ADCOPT_ADC1SWPRETRG_SHIFT (9) /* Bits 9-11: ADC1 software pretrigger sources */
#define SIM_ADCOPT_ADC1SWPRETRG_MASK (7 << SIM_ADCOPT_ADC1SWPRETRG_SHIFT)
# define SIM_ADCOPT_ADC1SWPRETRG_DISABLED (0 << SIM_ADCOPT_ADC1SWPRETRG_SHIFT) /* Software pretrigger disabled */

86
arch/arm/src/s32k1xx/s32k1xx_lpspi.c
View File

@ -1917,7 +1917,7 @@ static void s32k1xx_lpspi_bus_initialize(struct s32k1xx_lpspidev_s *priv)
static void up_pm_notify(struct pm_callback_s *cb, int domain,
enum pm_state_e pmstate)
{
# ifdef CONFIG_PM_SPI0
# ifdef CONFIG_PM_SPI0
struct s32k1xx_lpspidev_s *priv0 = NULL;
@ -1925,8 +1925,8 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain,
priv0 = &g_lpspi0dev;
# endif
# ifdef CONFIG_PM_SPI1
# endif
# ifdef CONFIG_PM_SPI1
struct s32k1xx_lpspidev_s *priv1 = NULL;
@ -1934,7 +1934,7 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain,
priv1 = &g_lpspi1dev;
# endif
# endif
unsigned int count = 0; /* the amount of peripheral clocks to change */
@ -1967,19 +1967,19 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain,
clock_source = CLK_SRC_SPLL_DIV2;
# ifdef CONFIG_PM_SPI0
# ifdef CONFIG_PM_SPI0
/* add 1 to count to do it for SPI0 */
count++;
# endif
# endif
# ifdef CONFIG_PM_SPI1
# ifdef CONFIG_PM_SPI1
/* add 1 to count to do it for SPI1 */
count++;
# endif
# endif
}
break;
@ -1998,7 +1998,7 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain,
const struct peripheral_clock_config_s clock_config[] =
{
# ifdef CONFIG_PM_SPI0
# ifdef CONFIG_PM_SPI0
{
.clkname = LPSPI0_CLK,
@ -2007,8 +2007,8 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain,
.frac = MULTIPLY_BY_ONE,
.divider = 1,
},
# endif
# ifdef CONFIG_PM_SPI1
# endif
# ifdef CONFIG_PM_SPI1
{
.clkname = LPSPI1_CLK,
@ -2017,45 +2017,45 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain,
.frac = MULTIPLY_BY_ONE,
.divider = 1,
}
# endif
# endif
};
# ifdef CONFIG_PM_SPI0
# ifdef CONFIG_PM_SPI0
/* disable LPSP0 */
s32k1xx_lpspi_modifyreg32(priv0, S32K1XX_LPSPI_CR_OFFSET, 0,
!LPSPI_CR_MEN);
# endif
# ifdef CONFIG_PM_SPI1
# endif
# ifdef CONFIG_PM_SPI1
/* disable LPSPI */
s32k1xx_lpspi_modifyreg32(priv1, S32K1XX_LPSPI_CR_OFFSET, 0,
!LPSPI_CR_MEN);
# endif
# endif
/* change the clock config for the new mode */
s32k1xx_periphclocks(count, clock_config);
# ifdef CONFIG_PM_SPI0
# ifdef CONFIG_PM_SPI0
/* Enable LPSP0 */
s32k1xx_lpspi_modifyreg32(priv0, S32K1XX_LPSPI_CR_OFFSET, 0,
LPSPI_CR_MEN);
# endif
# ifdef CONFIG_PM_SPI1
# endif
# ifdef CONFIG_PM_SPI1
/* Enable LPSPI */
s32k1xx_lpspi_modifyreg32(priv1, S32K1XX_LPSPI_CR_OFFSET, 0,
LPSPI_CR_MEN);
# endif
# endif
/* get the clock freq */
}
@ -2276,14 +2276,14 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain,
/* make the private struct for lpspi bus 0 */
priv0 = &g_lpspi0dev;
# endif
# ifdef CONFIG_PM_SPI1
# endif
# ifdef CONFIG_PM_SPI1
struct s32k1xx_lpspidev_s *priv1 = NULL;
/* make the private struct for lpspi bus 1 */
priv1 = &g_lpspi1dev;
# endif
# endif
unsigned int count = 0; /* the amount of peripheral clocks to change */
@ -2312,20 +2312,20 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain,
clock_source = CLK_SRC_SIRC_DIV2;
# ifdef CONFIG_PM_SPI0_STANDBY
# ifdef CONFIG_PM_SPI0_STANDBY
/* increase count to change the SPI0 */
count++;
# endif
# ifdef CONFIG_PM_SPI1_STANDBY
# endif
# ifdef CONFIG_PM_SPI1_STANDBY
/* increase count to change the SPI1 */
count++;
# endif
# endif
}
break;
@ -2339,20 +2339,20 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain,
clock_source = CLK_SRC_SIRC_DIV2;
# ifdef CONFIG_PM_SPI0_SLEEP
# ifdef CONFIG_PM_SPI0_SLEEP
/* increase count to change the SPI0 */
count++;
# endif
# ifdef CONFIG_PM_SPI1_SLEEP
# endif
# ifdef CONFIG_PM_SPI1_SLEEP
/* increase count to change the SPI1 */
count++;
# endif
# endif
}
break;
@ -2371,7 +2371,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain,
const struct peripheral_clock_config_s clock_config[] =
{
# ifdef CONFIG_PM_SPI0
# ifdef CONFIG_PM_SPI0
{
.clkname = LPSPI0_CLK,
.clkgate = true,
@ -2379,8 +2379,8 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain,
.frac = MULTIPLY_BY_ONE,
.divider = 1,
},
# endif
# ifdef CONFIG_PM_SPI1
# endif
# ifdef CONFIG_PM_SPI1
{
.clkname = LPSPI1_CLK,
.clkgate = true,
@ -2388,46 +2388,46 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain,
.frac = MULTIPLY_BY_ONE,
.divider = 1,
}
# endif
# endif
};
# ifdef CONFIG_PM_SPI0
# ifdef CONFIG_PM_SPI0
/* disable LPSPI0 */
s32k1xx_lpspi_modifyreg32(priv0, S32K1XX_LPSPI_CR_OFFSET, 0,
!LPSPI_CR_MEN);
# endif
# ifdef CONFIG_PM_SPI1
# endif
# ifdef CONFIG_PM_SPI1
/* disable LPSPI1 */
s32k1xx_lpspi_modifyreg32(priv1, S32K1XX_LPSPI_CR_OFFSET, 0,
!LPSPI_CR_MEN);
# endif
# endif
/* change the clock config for the new mode */
s32k1xx_periphclocks(count, clock_config);
# ifdef CONFIG_PM_SPI0
# ifdef CONFIG_PM_SPI0
/* Enable LPSPI */
s32k1xx_lpspi_modifyreg32(priv0, S32K1XX_LPSPI_CR_OFFSET, 0,
LPSPI_CR_MEN);
# endif
# ifdef CONFIG_PM_SPI1
# endif
# ifdef CONFIG_PM_SPI1
/* Enable LPSPI */
s32k1xx_lpspi_modifyreg32(priv1, S32K1XX_LPSPI_CR_OFFSET, 0,
LPSPI_CR_MEN);
# endif
# endif
}
/* get the clock freq */

2
arch/arm/src/s32k1xx/s32k1xx_serial.c
View File

@ -608,7 +608,7 @@ static struct s32k1xx_uart_s g_lpuart2priv =
# ifdef CONFIG_LPUART2_RXDMA
.dma_rxreqsrc = S32K1XX_DMACHAN_LPUART2_RX,
.rxfifo = g_lpuart2rxfifo,
# endif
# endif
};
#endif

2
arch/arm/src/s32k3xx/s32k3xx_qspi.c
View File

@ -151,7 +151,7 @@ static void qspi_resetregisters(void);
#if defined(CONFIG_DEBUG_SPI_INFO) && defined(CONFIG_DEBUG_GPIO)
static void qspi_dumpgpioconfig(const char *msg);
#else
# define qspi_dumpgpioconfig(msg)
# define qspi_dumpgpioconfig(msg)
#endif
static inline uint32_t qspi_isbusy(void);

662
arch/arm/src/s32k3xx/s32k3xx_serial.c
View File

File diff suppressed because it is too large Load Diff

8
arch/arm/src/sam34/hardware/sam4l_bpm.h
View File

@ -105,10 +105,10 @@
#define BPM_PMCON_RET (1 << 9) /* Bit 9: RETENTION Mode */
#define BPM_PMCON_SLEEP_SHIFT (12) /* Bits 12-13: SLEEP mode Configuration */
#define BPM_PMCON_SLEEP_MASK (3 << BPM_PMCON_SLEEP_SHIFT)
# define BPM_PMCON_SLEEP_SLEEP0 (0 << BPM_PMCON_SLEEP_SHIFT) /* CPU clock stopped */
# define BPM_PMCON_SLEEP_SLEEP1 (1 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB clocks stopped */
# define BPM_PMCON_SLEEP_SLEEP2 (2 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK clocks stopped */
# define BPM_PMCON_SLEEP_SLEEP3 (3 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK+sources stopped */
# define BPM_PMCON_SLEEP_SLEEP0 (0 << BPM_PMCON_SLEEP_SHIFT) /* CPU clock stopped */
# define BPM_PMCON_SLEEP_SLEEP1 (1 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB clocks stopped */
# define BPM_PMCON_SLEEP_SLEEP2 (2 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK clocks stopped */
# define BPM_PMCON_SLEEP_SLEEP3 (3 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK+sources stopped */
#define BPM_PMCON_CK32S (1 << 16) /* Bit 16: 32kHz-1kHz Clock Source Selection */
#define BPM_PMCON_FASTWKUP (1 << 24) /* Bit 24: Fast Wakeup */

8
arch/arm/src/sam34/hardware/sam4l_picouart.h
View File

@ -66,10 +66,10 @@
#define PICOUART_CFG_SOURCE_SHIFT (0) /* Bit 0-1: Source Enable Mode */
#define PICOUART_CFG_SOURCE_MASK (3 << PICOUART_CFG_SOURCE_SHIFT)
# define PICOUART_CFG_SOURCE_WE (0 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up and event disable */
# define PICOUART_CFG_SOURCE_WESB (1 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on start bit detection */
# define PICOUART_CFG_SOURCE_WEFF (2 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on full frame reception */
# define PICOUART_CFG_SOURCE_WECH (3 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on character recognition */
# define PICOUART_CFG_SOURCE_WE (0 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up and event disable */
# define PICOUART_CFG_SOURCE_WESB (1 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on start bit detection */
# define PICOUART_CFG_SOURCE_WEFF (2 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on full frame reception */
# define PICOUART_CFG_SOURCE_WECH (3 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on character recognition */
#define PICOUART_CFG_ACTION (1 << 0) /* Bit 0: Action to perform */
#define PICOUART_CFG_MATCH_SHIFT (8) /* Bit 8-15: Data Match */

12
arch/arm/src/sam34/hardware/sam_afec.h
View File

@ -209,12 +209,12 @@
# define AFEC_EMR_CMPFILTER(n) ((uint32_t)(n) << AFEC_EMR_CMPFILTER_SHIFT)
#define AFEC_EMR_RES_SHIFT (16) /* Bits 16-18: Resolution */
#define AFEC_EMR_RES_MASK (7 << AFEC_EMR_RES_SHIFT)
# define AFEC_EMR_RES_NOAVG (0 << AFEC_EMR_RES_SHIFT) /* 12-bit resolution, AFEC sample rate is maximum (no averaging) */
# define AFEC_EMR_RES_LOWRES (1 << AFEC_EMR_RES_SHIFT) /* 10-bit resolution, AFEC sample rate is maximum (no averaging) */
# define AFEC_EMR_RES_OSR4 (2 << AFEC_EMR_RES_SHIFT) /* 13-bit resolution, AFEC sample rate divided by 4 (averaging) */
# define AFEC_EMR_RES_OSR16 (3 << AFEC_EMR_RES_SHIFT) /* 14-bit resolution, AFEC sample rate divided by 16 (averaging) */
# define AFEC_EMR_RES_OSR64 (4 << AFEC_EMR_RES_SHIFT) /* 15-bit resolution, AFEC sample rate divided by 64 (averaging) */
# define AFEC_EMR_RES_OSR256 (5 << AFEC_EMR_RES_SHIFT) /* 16-bit resolution, AFEC sample rate divided by 256 (averaging) */
# define AFEC_EMR_RES_NOAVG (0 << AFEC_EMR_RES_SHIFT) /* 12-bit resolution, AFEC sample rate is maximum (no averaging) */
# define AFEC_EMR_RES_LOWRES (1 << AFEC_EMR_RES_SHIFT) /* 10-bit resolution, AFEC sample rate is maximum (no averaging) */
# define AFEC_EMR_RES_OSR4 (2 << AFEC_EMR_RES_SHIFT) /* 13-bit resolution, AFEC sample rate divided by 4 (averaging) */
# define AFEC_EMR_RES_OSR16 (3 << AFEC_EMR_RES_SHIFT) /* 14-bit resolution, AFEC sample rate divided by 16 (averaging) */
# define AFEC_EMR_RES_OSR64 (4 << AFEC_EMR_RES_SHIFT) /* 15-bit resolution, AFEC sample rate divided by 64 (averaging) */
# define AFEC_EMR_RES_OSR256 (5 << AFEC_EMR_RES_SHIFT) /* 16-bit resolution, AFEC sample rate divided by 256 (averaging) */
#define AFEC_EMR_TAG (1 << 24) /* Bit 24: TAG of the AFEC_LDCR register */
#define AFEC_EMR_STM (1 << 25) /* Bit 25: Single Trigger Mode */

2
arch/arm/src/sam34/sam4s_nand.h
View File

@ -47,7 +47,7 @@
/* Only NCS0 can support NAND. The rest is a fantasy */
#if defined(CONFIG_SAM34_EXTNAND)
# define CONFIG_SAM34_NCS0_NAND 1
# define CONFIG_SAM34_NCS0_NAND 1
#else
# undef CONFIG_SAM34_NCS0_NAND
#endif

4
arch/arm/src/sam34/sam_emac.c
View File

@ -329,8 +329,8 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t addr);
static void sam_putreg(struct sam_emac_s *priv,
uintptr_t addr, uint32_t val);
#else
# define sam_getreg(priv,addr) getreg32(addr)
# define sam_putreg(priv,addr,val) putreg32(val,addr)
# define sam_getreg(priv,addr) getreg32(addr)
# define sam_putreg(priv,addr,val) putreg32(val,addr)
#endif
/* Buffer management */

12
arch/arm/src/sam34/sam_rtc.c
View File

@ -52,12 +52,12 @@
/* Configuration ************************************************************/
#ifdef CONFIG_RTC_HIRES
# if !defined(CONFIG_SAM34_RTT)
# error RTT is required to emulate high resolution RTC
# endif
# if (CONFIG_RTC_FREQUENCY > 32768) || ((32768 % CONFIG_RTC_FREQUENCY) != 0)
# error CONFIG_RTC_FREQUENCY must be an integer division of 32768
# endif
# if !defined(CONFIG_SAM34_RTT)
# error RTT is required to emulate high resolution RTC
# endif
# if (CONFIG_RTC_FREQUENCY > 32768) || ((32768 % CONFIG_RTC_FREQUENCY) != 0)
# error CONFIG_RTC_FREQUENCY must be an integer division of 32768
# endif
#endif
#if defined(CONFIG_RTC_ALARM) && !defined(CONFIG_SCHED_WORKQUEUE)

4
arch/arm/src/sam34/sam_rtt.c
View File

@ -99,8 +99,8 @@ struct sam34_lowerhalf_s
static uint32_t sam34_getreg(uint32_t addr);
static void sam34_putreg(uint32_t val, uint32_t addr);
#else
# define sam34_getreg(addr) getreg32(addr)
# define sam34_putreg(val,addr) putreg32(val,addr)
# define sam34_getreg(addr) getreg32(addr)
# define sam34_putreg(val,addr) putreg32(val,addr)
#endif
/* Interrupt handling *******************************************************/

4
arch/arm/src/sam34/sam_spi.c
View File

@ -214,7 +214,7 @@ struct sam_spidev_s
static bool spi_checkreg(struct sam_spidev_s *spi, bool wr,
uint32_t value, uint32_t address);
#else
# define spi_checkreg(spi,wr,value,address) (false)
# define spi_checkreg(spi,wr,value,address) (false)
#endif
static inline uint32_t spi_getreg(struct sam_spidev_s *spi,
@ -226,7 +226,7 @@ static inline struct sam_spidev_s *spi_device(struct sam_spics_s *spics);
#ifdef CONFIG_DEBUG_SPI_INFO
static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg);
#else
# define spi_dumpregs(spi,msg)
# define spi_dumpregs(spi,msg)
#endif
static inline void spi_flush(struct sam_spidev_s *spi);

4
arch/arm/src/sam34/sam_tc.c
View File

@ -97,8 +97,8 @@ struct sam34_lowerhalf_s
static uint32_t sam34_getreg(uint32_t addr);
static void sam34_putreg(uint32_t val, uint32_t addr);
#else
# define sam34_getreg(addr) getreg32(addr)
# define sam34_putreg(val,addr) putreg32(val,addr)
# define sam34_getreg(addr) getreg32(addr)
# define sam34_putreg(val,addr) putreg32(val,addr)
#endif
/* Interrupt handling *******************************************************/

6
arch/arm/src/sam34/sam_twi.c
View File

@ -148,9 +148,9 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address);
static void twi_putabs(struct twi_dev_s *priv, uintptr_t address,
uint32_t value);
#else
# define twi_checkreg(priv,wr,value,address) (false)
# define twi_putabs(p,a,v) putreg32(v,a)
# define twi_getabs(p,a) getreg32(a)
# define twi_checkreg(priv,wr,value,address) (false)
# define twi_putabs(p,a,v) putreg32(v,a)
# define twi_getabs(p,a) getreg32(a)
#endif
static inline uint32_t twi_getrel(struct twi_dev_s *priv,

2
arch/arm/src/sam34/sam_udp.c
View File

@ -329,7 +329,7 @@ static void sam_dumpep(struct sam_usbdev_s *priv, uint8_t epno);
#else
static inline uint32_t sam_getreg(uintptr_t regaddr);
static inline void sam_putreg(uint32_t regval, uintptr_t regaddr);
# define sam_dumpep(priv,epno)
# define sam_dumpep(priv,epno)
#endif
static void sam_csr_setbits(uint8_t epno, uint32_t setbits);

4
arch/arm/src/sam34/sam_wdt.c
View File

@ -103,8 +103,8 @@ struct sam34_lowerhalf_s
static uint32_t sam34_getreg(uint32_t addr);
static void sam34_putreg(uint32_t val, uint32_t addr);
#else
# define sam34_getreg(addr) getreg32(addr)
# define sam34_putreg(val,addr) putreg32(val,addr)
# define sam34_getreg(addr) getreg32(addr)
# define sam34_putreg(val,addr) putreg32(val,addr)
#endif
/* Interrupt handling *******************************************************/

Some files were not shown because too many files have changed in this diff Show More