diff --git a/arch/arm/src/arm/arm_initialstate.c b/arch/arm/src/arm/arm_initialstate.c index ca52cba491..e6ea138130 100644 --- a/arch/arm/src/arm/arm_initialstate.c +++ b/arch/arm/src/arm/arm_initialstate.c @@ -141,9 +141,9 @@ void up_initial_state(struct tcb_s *tcb) /* Enable or disable interrupts, based on user configuration */ -# ifdef CONFIG_SUPPRESS_INTERRUPTS +#ifdef CONFIG_SUPPRESS_INTERRUPTS cpsr |= PSR_I_BIT; -# endif +#endif #ifdef CONFIG_ARM_THUMB cpsr |= PSR_T_BIT; diff --git a/arch/arm/src/armv6-m/arm_hardfault.c b/arch/arm/src/armv6-m/arm_hardfault.c index 4dea1b87b1..6b02754e06 100644 --- a/arch/arm/src/armv6-m/arm_hardfault.c +++ b/arch/arm/src/armv6-m/arm_hardfault.c @@ -39,15 +39,15 @@ ****************************************************************************/ #ifdef CONFIG_DEBUG_HARDFAULT_ALERT -# define hfalert(format, ...) _alert(format, ##__VA_ARGS__) +# define hfalert(format, ...) _alert(format, ##__VA_ARGS__) #else -# define hfalert(x...) +# define hfalert(x...) #endif #ifdef CONFIG_DEBUG_HARDFAULT_INFO -# define hfinfo(format, ...) _info(format, ##__VA_ARGS__) +# define hfinfo(format, ...) _info(format, ##__VA_ARGS__) #else -# define hfinfo(x...) +# define hfinfo(x...) #endif #define INSN_SVC0 0xdf00 /* insn: svc 0 */ diff --git a/arch/arm/src/armv6-m/arm_svcall.c b/arch/arm/src/armv6-m/arm_svcall.c index a11ff403ad..02a609fc55 100644 --- a/arch/arm/src/armv6-m/arm_svcall.c +++ b/arch/arm/src/armv6-m/arm_svcall.c @@ -127,9 +127,9 @@ int arm_svcall(int irq, void *context, void *arg) */ #ifdef CONFIG_DEBUG_SYSCALL_INFO -# ifndef CONFIG_DEBUG_SVCALL +# ifndef CONFIG_DEBUG_SVCALL if (cmd > SYS_switch_context) -# endif +# endif { svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd); svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", @@ -138,13 +138,13 @@ int arm_svcall(int irq, void *context, void *arg) svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); -# ifdef CONFIG_BUILD_PROTECTED +# ifdef CONFIG_BUILD_PROTECTED svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n", regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]); -# else +# else svcinfo(" PSR: %08x PRIMASK: %08x\n", regs[REG_XPSR], regs[REG_PRIMASK]); -# endif +# endif } #endif @@ -429,11 +429,11 @@ int arm_svcall(int irq, void *context, void *arg) */ #ifdef CONFIG_DEBUG_SYSCALL_INFO -# ifndef CONFIG_DEBUG_SVCALL +# ifndef CONFIG_DEBUG_SVCALL if (cmd > SYS_switch_context) -# else +# else if (regs != CURRENT_REGS) -# endif +# endif { svcinfo("SVCall Return:\n"); svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", @@ -446,21 +446,21 @@ int arm_svcall(int irq, void *context, void *arg) CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11], CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13], CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]); -#ifdef CONFIG_BUILD_PROTECTED +# ifdef CONFIG_BUILD_PROTECTED svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n", CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK], CURRENT_REGS[REG_EXC_RETURN]); -#else +# else svcinfo(" PSR: %08x PRIMASK: %08x\n", CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]); -#endif +# endif } -# ifdef CONFIG_DEBUG_SVCALL +# ifdef CONFIG_DEBUG_SVCALL else { svcinfo("SVCall Return: %d\n", regs[REG_R0]); } -# endif +# endif #endif return OK; diff --git a/arch/arm/src/armv7-m/arm_busfault.c b/arch/arm/src/armv7-m/arm_busfault.c index 9fa43c4ea1..3e12ec8efc 100644 --- a/arch/arm/src/armv7-m/arm_busfault.c +++ b/arch/arm/src/armv7-m/arm_busfault.c @@ -39,9 +39,9 @@ ****************************************************************************/ #ifdef CONFIG_DEBUG_BUSFAULT -# define bfalert(format, ...) _alert(format, ##__VA_ARGS__) +# define bfalert(format, ...) _alert(format, ##__VA_ARGS__) #else -# define bfalert(x...) +# define bfalert(x...) #endif /**************************************************************************** diff --git a/arch/arm/src/armv7-m/arm_hardfault.c b/arch/arm/src/armv7-m/arm_hardfault.c index d1c440370c..d45c979662 100644 --- a/arch/arm/src/armv7-m/arm_hardfault.c +++ b/arch/arm/src/armv7-m/arm_hardfault.c @@ -45,15 +45,15 @@ */ #ifdef CONFIG_DEBUG_HARDFAULT_ALERT -# define hfalert(format, ...) _alert(format, ##__VA_ARGS__) +# define hfalert(format, ...) _alert(format, ##__VA_ARGS__) #else -# define hfalert(x...) +# define hfalert(x...) #endif #ifdef CONFIG_DEBUG_HARDFAULT_INFO -# define hfinfo(format, ...) _info(format, ##__VA_ARGS__) +# define hfinfo(format, ...) _info(format, ##__VA_ARGS__) #else -# define hfinfo(x...) +# define hfinfo(x...) #endif #define INSN_SVC0 0xdf00 /* insn: svc 0 */ diff --git a/arch/arm/src/armv7-m/arm_memfault.c b/arch/arm/src/armv7-m/arm_memfault.c index 8fdecd7f3e..afde6fad92 100644 --- a/arch/arm/src/armv7-m/arm_memfault.c +++ b/arch/arm/src/armv7-m/arm_memfault.c @@ -38,9 +38,9 @@ ****************************************************************************/ #ifdef CONFIG_DEBUG_MEMFAULT -# define mfalert(format, ...) _alert(format, ##__VA_ARGS__) +# define mfalert(format, ...) _alert(format, ##__VA_ARGS__) #else -# define mfalert(x...) +# define mfalert(x...) #endif /**************************************************************************** diff --git a/arch/arm/src/armv7-m/arm_svcall.c b/arch/arm/src/armv7-m/arm_svcall.c index 97a882e8dc..d9f5c0aa00 100644 --- a/arch/arm/src/armv7-m/arm_svcall.c +++ b/arch/arm/src/armv7-m/arm_svcall.c @@ -135,9 +135,9 @@ int arm_svcall(int irq, void *context, void *arg) */ #ifdef CONFIG_DEBUG_SYSCALL_INFO -# ifndef CONFIG_DEBUG_SVCALL +# ifndef CONFIG_DEBUG_SVCALL if (cmd > SYS_switch_context) -# endif +# endif { svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd); svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", @@ -146,12 +146,12 @@ int arm_svcall(int irq, void *context, void *arg) svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); -# ifdef REG_EXC_RETURN +# ifdef REG_EXC_RETURN svcinfo(" PSR: %08x EXC_RETURN: %08x\n", regs[REG_XPSR], regs[REG_EXC_RETURN]); -# else +# else svcinfo(" PSR: %08x\n", regs[REG_XPSR]); -# endif +# endif } #endif @@ -437,11 +437,11 @@ int arm_svcall(int irq, void *context, void *arg) */ #ifdef CONFIG_DEBUG_SYSCALL_INFO -# ifndef CONFIG_DEBUG_SVCALL +# ifndef CONFIG_DEBUG_SVCALL if (cmd > SYS_switch_context) -# else +# else if (regs != CURRENT_REGS) -# endif +# endif { svcinfo("SVCall Return:\n"); svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", @@ -454,19 +454,19 @@ int arm_svcall(int irq, void *context, void *arg) CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11], CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13], CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]); -# ifdef REG_EXC_RETURN +# ifdef REG_EXC_RETURN svcinfo(" PSR: %08x EXC_RETURN: %08x\n", CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]); -# else +# else svcinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]); -# endif +# endif } -# ifdef CONFIG_DEBUG_SVCALL +# ifdef CONFIG_DEBUG_SVCALL else { svcinfo("SVCall Return: %d\n", regs[REG_R0]); } -# endif +# endif #endif return OK; diff --git a/arch/arm/src/armv7-m/arm_usagefault.c b/arch/arm/src/armv7-m/arm_usagefault.c index ddb3998ec4..39cc46b114 100644 --- a/arch/arm/src/armv7-m/arm_usagefault.c +++ b/arch/arm/src/armv7-m/arm_usagefault.c @@ -39,9 +39,9 @@ ****************************************************************************/ #ifdef CONFIG_DEBUG_USAGEFAULT -# define ufalert(format, ...) _alert(format, ##__VA_ARGS__) +# define ufalert(format, ...) _alert(format, ##__VA_ARGS__) #else -# define ufalert(x...) +# define ufalert(x...) #endif /**************************************************************************** diff --git a/arch/arm/src/armv8-m/arm_busfault.c b/arch/arm/src/armv8-m/arm_busfault.c index 559cba5fb4..2060cae591 100644 --- a/arch/arm/src/armv8-m/arm_busfault.c +++ b/arch/arm/src/armv8-m/arm_busfault.c @@ -39,9 +39,9 @@ ****************************************************************************/ #ifdef CONFIG_DEBUG_BUSFAULT -# define bfalert(format, ...) _alert(format, ##__VA_ARGS__) +# define bfalert(format, ...) _alert(format, ##__VA_ARGS__) #else -# define bfalert(x...) +# define bfalert(x...) #endif /**************************************************************************** diff --git a/arch/arm/src/armv8-m/arm_hardfault.c b/arch/arm/src/armv8-m/arm_hardfault.c index 44ac314f7b..5a9542dca7 100644 --- a/arch/arm/src/armv8-m/arm_hardfault.c +++ b/arch/arm/src/armv8-m/arm_hardfault.c @@ -45,15 +45,15 @@ */ #ifdef CONFIG_DEBUG_HARDFAULT_ALERT -# define hfalert(format, ...) _alert(format, ##__VA_ARGS__) +# define hfalert(format, ...) _alert(format, ##__VA_ARGS__) #else -# define hfalert(x...) +# define hfalert(x...) #endif #ifdef CONFIG_DEBUG_HARDFAULT_INFO -# define hfinfo(format, ...) _info(format, ##__VA_ARGS__) +# define hfinfo(format, ...) _info(format, ##__VA_ARGS__) #else -# define hfinfo(x...) +# define hfinfo(x...) #endif #define INSN_SVC0 0xdf00 /* insn: svc 0 */ diff --git a/arch/arm/src/armv8-m/arm_memfault.c b/arch/arm/src/armv8-m/arm_memfault.c index 506e70ed29..e9bdbc580e 100644 --- a/arch/arm/src/armv8-m/arm_memfault.c +++ b/arch/arm/src/armv8-m/arm_memfault.c @@ -38,9 +38,9 @@ ****************************************************************************/ #ifdef CONFIG_DEBUG_MEMFAULT -# define mfalert(format, ...) _alert(format, ##__VA_ARGS__) +# define mfalert(format, ...) _alert(format, ##__VA_ARGS__) #else -# define mfalert(x...) +# define mfalert(x...) #endif /**************************************************************************** diff --git a/arch/arm/src/armv8-m/arm_svcall.c b/arch/arm/src/armv8-m/arm_svcall.c index c98a831e88..70fc9643bd 100644 --- a/arch/arm/src/armv8-m/arm_svcall.c +++ b/arch/arm/src/armv8-m/arm_svcall.c @@ -134,9 +134,9 @@ int arm_svcall(int irq, void *context, void *arg) */ #ifdef CONFIG_DEBUG_SYSCALL_INFO -# ifndef CONFIG_DEBUG_SVCALL +# ifndef CONFIG_DEBUG_SVCALL if (cmd > SYS_switch_context) -# endif +# endif { svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd); svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", @@ -145,12 +145,12 @@ int arm_svcall(int irq, void *context, void *arg) svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n", regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11], regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]); -# ifdef REG_EXC_RETURN +# ifdef REG_EXC_RETURN svcinfo(" PSR: %08x EXC_RETURN: %08x\n", regs[REG_XPSR], regs[REG_EXC_RETURN]); -# else +# else svcinfo(" PSR: %08x\n", regs[REG_XPSR]); -# endif +# endif } #endif @@ -437,11 +437,11 @@ int arm_svcall(int irq, void *context, void *arg) */ #ifdef CONFIG_DEBUG_SYSCALL_INFO -# ifndef CONFIG_DEBUG_SVCALL +# ifndef CONFIG_DEBUG_SVCALL if (cmd > SYS_switch_context) -# else +# else if (regs != CURRENT_REGS) -# endif +# endif { svcinfo("SVCall Return:\n"); svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n", @@ -454,19 +454,19 @@ int arm_svcall(int irq, void *context, void *arg) CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11], CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13], CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]); -# ifdef REG_EXC_RETURN +# ifdef REG_EXC_RETURN svcinfo(" PSR: %08x EXC_RETURN: %08x\n", CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]); -# else +# else svcinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]); -# endif +# endif } -# ifdef CONFIG_DEBUG_SVCALL +# ifdef CONFIG_DEBUG_SVCALL else { svcinfo("SVCall Return: %d\n", regs[REG_R0]); } -# endif +# endif #endif return OK; diff --git a/arch/arm/src/armv8-m/arm_usagefault.c b/arch/arm/src/armv8-m/arm_usagefault.c index 41b6808e33..edbe6353cb 100644 --- a/arch/arm/src/armv8-m/arm_usagefault.c +++ b/arch/arm/src/armv8-m/arm_usagefault.c @@ -39,9 +39,9 @@ ****************************************************************************/ #ifdef CONFIG_DEBUG_USAGEFAULT -# define ufalert(format, ...) _alert(format, ##__VA_ARGS__) +# define ufalert(format, ...) _alert(format, ##__VA_ARGS__) #else -# define ufalert(x...) +# define ufalert(x...) #endif /**************************************************************************** diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c index f052cb3e49..fa00b31d98 100644 --- a/arch/arm/src/c5471/c5471_ethernet.c +++ b/arch/arm/src/c5471/c5471_ethernet.c @@ -80,7 +80,7 @@ */ #ifndef CONFIG_C5471_NET_NINTERFACES -# define CONFIG_C5471_NET_NINTERFACES 1 +# define CONFIG_C5471_NET_NINTERFACES 1 #endif /* CONFIG_C5471_NET_STATS will enabled collection of driver statistics. @@ -99,7 +99,7 @@ # undef CONFIG_C5471_AUTONEGOTIATION # undef CONFIG_C5471_BASET100 #else -# define CONFIG_C5471_AUTONEGOTIATION 1 +# define CONFIG_C5471_AUTONEGOTIATION 1 # undef CONFIG_C5471_BASET100 # undef CONFIG_C5471_BASET10 #endif @@ -435,7 +435,7 @@ static inline void c5471_dumpbuffer(const char *msg, const uint8_t *buffer, ninfodumpbuffer(msg, buffer, nbytes); } #else -# define c5471_dumpbuffer(msg, buffer,nbytes) +# define c5471_dumpbuffer(msg, buffer,nbytes) #endif /**************************************************************************** diff --git a/arch/arm/src/c5471/c5471_serial.c b/arch/arm/src/c5471/c5471_serial.c index 394b5bea0e..7d1888be1d 100644 --- a/arch/arm/src/c5471/c5471_serial.c +++ b/arch/arm/src/c5471/c5471_serial.c @@ -48,7 +48,7 @@ #define BASE_BAUD 115200 #if defined(CONFIG_UART_IRDA_HWFLOWCONTROL) || defined(CONFIG_UART_MODEM_HWFLOWCONTROL) -# define CONFIG_UART_HWFLOWCONTROL +# define CONFIG_UART_HWFLOWCONTROL #endif /**************************************************************************** @@ -203,13 +203,13 @@ static uart_dev_t g_modemport = /* Now, which one with be tty0/console and which tty1? */ #ifdef CONFIG_SERIAL_IRDA_CONSOLE -# define CONSOLE_DEV g_irdaport -# define TTYS0_DEV g_irdaport -# define TTYS1_DEV g_modemport +# define CONSOLE_DEV g_irdaport +# define TTYS0_DEV g_irdaport +# define TTYS1_DEV g_modemport #else -# define CONSOLE_DEV g_modemport -# define TTYS0_DEV g_modemport -# define TTYS1_DEV g_irdaport +# define CONSOLE_DEV g_modemport +# define TTYS0_DEV g_modemport +# define TTYS1_DEV g_irdaport #endif /**************************************************************************** diff --git a/arch/arm/src/common/arm_internal.h b/arch/arm/src/common/arm_internal.h index a1dbcfb904..3f68b49536 100644 --- a/arch/arm/src/common/arm_internal.h +++ b/arch/arm/src/common/arm_internal.h @@ -356,7 +356,7 @@ uint32_t *arm_doirq(int irq, uint32_t *regs); void arm_pginitialize(void); uint32_t *arm_va2pte(uintptr_t vaddr); #else /* CONFIG_PAGING */ -# define arm_pginitialize() +# define arm_pginitialize() #endif /* CONFIG_PAGING */ /* Exception Handlers */ @@ -382,7 +382,7 @@ void arm_pginitialize(void); uint32_t *arm_va2pte(uintptr_t vaddr); void arm_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr); #else /* CONFIG_PAGING */ -# define arm_pginitialize() +# define arm_pginitialize() void arm_dataabort(uint32_t *regs); #endif /* CONFIG_PAGING */ @@ -442,7 +442,7 @@ void arm_l2ccinitialize(void); #if CONFIG_MM_REGIONS > 1 void arm_addregion(void); #else -# define arm_addregion() +# define arm_addregion() #endif /* Networking ***************************************************************/ @@ -461,7 +461,7 @@ void arm_addregion(void); #if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void); #else -# define arm_netinitialize() +# define arm_netinitialize() #endif /* USB **********************************************************************/ @@ -470,8 +470,8 @@ void arm_netinitialize(void); void arm_usbinitialize(void); void arm_usbuninitialize(void); #else -# define arm_usbinitialize() -# define arm_usbuninitialize() +# define arm_usbinitialize() +# define arm_usbuninitialize() #endif /* Debug ********************************************************************/ diff --git a/arch/arm/src/dm320/dm320_serial.c b/arch/arm/src/dm320/dm320_serial.c index 01d70362a6..40da3df612 100644 --- a/arch/arm/src/dm320/dm320_serial.c +++ b/arch/arm/src/dm320/dm320_serial.c @@ -171,13 +171,13 @@ static uart_dev_t g_uart1port = /* Now, which one with be tty0/console and which tty1? */ #ifdef CONFIG_SERIAL_IRDA_CONSOLE -# define CONSOLE_DEV g_uart1port -# define TTYS0_DEV g_uart1port -# define TTYS1_DEV g_uart0port +# define CONSOLE_DEV g_uart1port +# define TTYS0_DEV g_uart1port +# define TTYS1_DEV g_uart0port #else -# define CONSOLE_DEV g_uart0port -# define TTYS0_DEV g_uart0port -# define TTYS1_DEV g_uart1port +# define CONSOLE_DEV g_uart0port +# define TTYS0_DEV g_uart0port +# define TTYS1_DEV g_uart1port #endif /**************************************************************************** diff --git a/arch/arm/src/dm320/dm320_timer.h b/arch/arm/src/dm320/dm320_timer.h index f773a0384c..5e16388f4d 100644 --- a/arch/arm/src/dm320/dm320_timer.h +++ b/arch/arm/src/dm320/dm320_timer.h @@ -60,9 +60,9 @@ #define DM320_TMR_MODE_TEST_MASK 0x00fc /* Bits 7:2=Test */ #define DM320_TMR_MODE_MODE_MASK 0x0003 /* Bits 1:0=timer mode */ -# define DM320_TMR_MODE_STOP 0x0000 /* Stop Timer */ -# define DM320_TMR_MODE_ONESHOT 0x0001 /* Start one-shot timer */ -# define DM320_TMR_MODE_FREERUN 0x0002 /* Start free-running timer */ +# define DM320_TMR_MODE_STOP 0x0000 /* Stop Timer */ +# define DM320_TMR_MODE_ONESHOT 0x0001 /* Start one-shot timer */ +# define DM320_TMR_MODE_FREERUN 0x0002 /* Start free-running timer */ /* Timer 0,1,2,3 Clock Select Register Bits: */ @@ -76,7 +76,7 @@ #define DM320_TMR_TMTRG_MASK 0x0001 /* Bit 0=One short trigger */ -# define DM320_TMR_TMTRG_START 0x0001 /* 1 starts one shot timer */ +# define DM320_TMR_TMTRG_START 0x0001 /* 1 starts one shot timer */ /* Timer 0,1,2,3 Timer Counter Register Bits: */ diff --git a/arch/arm/src/dm320/dm320_usbdev.c b/arch/arm/src/dm320/dm320_usbdev.c index 4dd5682629..d7dfe8b69b 100644 --- a/arch/arm/src/dm320/dm320_usbdev.c +++ b/arch/arm/src/dm320/dm320_usbdev.c @@ -261,12 +261,12 @@ static void dm320_putreg8(uint8_t val, uint32_t addr); static void dm320_putreg16(uint16_t val, uint32_t addr); static void dm320_putreg32(uint32_t val, uint32_t addr); #else -# define dm320_getreg8(addr) getreg8(addr) -# define dm320_getreg16(addr) getreg16(addr) -# define dm320_getreg32(addr) getreg32(addr) -# define dm320_putreg8(val,addr) putreg8(val,addr) -# define dm320_putreg16(val,addr) putreg16(val,addr) -# define dm320_putreg32(val,addr) putreg32(val,addr) +# define dm320_getreg8(addr) getreg8(addr) +# define dm320_getreg16(addr) getreg16(addr) +# define dm320_getreg32(addr) getreg32(addr) +# define dm320_putreg8(val,addr) putreg8(val,addr) +# define dm320_putreg16(val,addr) putreg16(val,addr) +# define dm320_putreg32(val,addr) putreg32(val,addr) #endif /* Request queue operations *************************************************/ diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c index ff54616dc9..4f7bb31894 100644 --- a/arch/arm/src/efm32/efm32_usbdev.c +++ b/arch/arm/src/efm32/efm32_usbdev.c @@ -465,8 +465,8 @@ struct efm32_usbdev_s static uint32_t efm32_getreg(uint32_t addr); static void efm32_putreg(uint32_t val, uint32_t addr); #else -# define efm32_getreg(addr) getreg32(addr) -# define efm32_putreg(val,addr) putreg32(val,addr) +# define efm32_getreg(addr) getreg32(addr) +# define efm32_putreg(val,addr) putreg32(val,addr) #endif /* Request queue operations *************************************************/ diff --git a/arch/arm/src/efm32/efm32_usbhost.c b/arch/arm/src/efm32/efm32_usbhost.c index 8120cfd9ce..a15e8dc6a4 100644 --- a/arch/arm/src/efm32/efm32_usbhost.c +++ b/arch/arm/src/efm32/efm32_usbhost.c @@ -284,8 +284,8 @@ static void efm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t efm32_getreg(uint32_t addr); static void efm32_putreg(uint32_t addr, uint32_t value); #else -# define efm32_getreg(addr) getreg32(addr) -# define efm32_putreg(addr,val) putreg32(val,addr) +# define efm32_getreg(addr) getreg32(addr) +# define efm32_putreg(addr,val) putreg32(val,addr) #endif static inline void efm32_modifyreg(uint32_t addr, uint32_t clrbits, diff --git a/arch/arm/src/efm32/hardware/efm32gg_memorymap.h b/arch/arm/src/efm32/hardware/efm32gg_memorymap.h index 8c60f6b24f..33931c6101 100644 --- a/arch/arm/src/efm32/hardware/efm32gg_memorymap.h +++ b/arch/arm/src/efm32/hardware/efm32gg_memorymap.h @@ -68,7 +68,7 @@ #define EFM32_FLASH_MEM_BASE 0x00000000 /* FLASH base address */ # define EFM32_FLASH_MEM_BITS 0x00000028 /* FLASH used bits */ #define EFM32_RAM_CODE_MEM_BASE 0x10000000 /* RAM_CODE base address */ -# define EFM32_RAM_CODE_MEM_BITS 0x00000014 /* RAM_CODE used bits */ +# define EFM32_RAM_CODE_MEM_BITS 0x00000014 /* RAM_CODE used bits */ #define EFM32_RAM_MEM_BASE 0x20000000 /* RAM base address */ # define EFM32_RAM_MEM_BITS 0x00000018 /* RAM used bits */ #define EFM32_PER_MEM_BASE 0x40000000 /* PER base address */ diff --git a/arch/arm/src/gd32f4/gd32f4xx_enet.c b/arch/arm/src/gd32f4/gd32f4xx_enet.c index 8d6b189347..58dd72e4c1 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_enet.c +++ b/arch/arm/src/gd32f4/gd32f4xx_enet.c @@ -3295,7 +3295,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv) * CK_PLLP clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_GD32F4_MII_CKOUT0) +# if defined(CONFIG_GD32F4_MII_CKOUT0) /* Configure CKOUT0 to drive the PHY. Board logic must provide * CKOUT0 clocking info. */ @@ -3303,14 +3303,14 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv) gd32_gpio_config(GPIO_CKOUT0); gd32_rcu_ckout0_config(BOARD_CFG_CKOUT0_SOURCE, BOARD_CFG_CKOUT0_DIVIDER); -# elif defined(CONFIG_GD32F4_MII_CKOUT1) +# elif defined(CONFIG_GD32F4_MII_CKOUT1) /* Configure CKOUT1 to drive the PHY. Board logic must provide * CKOUT1 clocking info. */ gd32_gpio_config(GPIO_CKOUT1); gd32_rcu_ckout1_config(BOARD_CFG_CKOUT1_SOURCE, BOARD_CFG_CKOUT1_DIVIDER); -# endif +# endif /* MII interface pins (17): * @@ -3351,7 +3351,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv) * CK_PLLP clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_GD32F4_RMII_CKOUT0) +# if defined(CONFIG_GD32F4_RMII_CKOUT0) /* Configure CKOUT0 to drive the PHY. Board logic must provide * CKOUT0 clocking info. */ @@ -3359,7 +3359,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv) gd32_gpio_config(GPIO_CKOUT0); gd32_rcu_ckout0_config(BOARD_CFG_CKOUT0_SOURCE, BOARD_CFG_CKOUT0_DIV); -# elif defined(CONFIG_GD32F4_RMII_CKOUT1) +# elif defined(CONFIG_GD32F4_RMII_CKOUT1) /* Configure CKOUT1 to drive the PHY. Board logic must provide * CKOUT1 clocking info. */ @@ -3367,7 +3367,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv) gd32_gpio_config(GPIO_CKOUT1); gd32_rcu_ckout1_config(BOARD_CFG_CKOUT1_SOURCE, BOARD_CFG_CKOUT1_DIVIDER); -# endif +# endif /* RMII interface pins (7): * @@ -3383,7 +3383,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv) gd32_gpio_config(GPIO_ENET_RMII_TXD0); gd32_gpio_config(GPIO_ENET_RMII_TXD1); -#endif +# endif #endif #ifdef CONFIG_GD32F4_ENET_PTP diff --git a/arch/arm/src/gd32f4/gd32f4xx_i2c.c b/arch/arm/src/gd32f4/gd32f4xx_i2c.c index 4fb004dd86..fbe8709fb7 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_i2c.c +++ b/arch/arm/src/gd32f4/gd32f4xx_i2c.c @@ -130,14 +130,14 @@ # error "Now I2C DMA has not ready" -# if defined(CONFIG_I2C_DMAPRIO) -# if (CONFIG_I2C_DMAPRIO & ~DMA_CHXCTL_PRIO_MASK) != 0 -# error "Illegal value for CONFIG_I2C_DMAPRIO" -# endif -# define I2C_DMA_PRIO CONFIG_I2C_DMAPRIO -# else -# define I2C_DMA_PRIO DMA_PRIO_HIGH_SELECT -# endif +# if defined(CONFIG_I2C_DMAPRIO) +# if (CONFIG_I2C_DMAPRIO & ~DMA_CHXCTL_PRIO_MASK) != 0 +# error "Illegal value for CONFIG_I2C_DMAPRIO" +# endif +# define I2C_DMA_PRIO CONFIG_I2C_DMAPRIO +# else +# define I2C_DMA_PRIO DMA_PRIO_HIGH_SELECT +# endif #endif /* Debug ********************************************************************/ diff --git a/arch/arm/src/gd32f4/gd32f4xx_serial.c b/arch/arm/src/gd32f4/gd32f4xx_serial.c index 753cc0717e..4e3c301090 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_serial.c +++ b/arch/arm/src/gd32f4/gd32f4xx_serial.c @@ -356,65 +356,65 @@ static const struct uart_ops_s g_uart_ops_no_dma = #ifdef CONFIG_GD32F4_USART0_SERIALDRIVER static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE]; static char g_usart0txbuffer[CONFIG_USART0_TXBUFSIZE]; -# ifdef CONFIG_GD32F4_USART0_RXDMA +# ifdef CONFIG_GD32F4_USART0_RXDMA static char g_usart0rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_GD32F4_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; -# ifdef CONFIG_GD32F4_USART1_RXDMA +# ifdef CONFIG_GD32F4_USART1_RXDMA static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_GD32F4_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; -# ifdef CONFIG_GD32F4_USART2_RXDMA +# ifdef CONFIG_GD32F4_USART2_RXDMA static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_GD32F4_UART3_SERIALDRIVER static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE]; static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE]; -# ifdef CONFIG_GD32F4_UART3_RXDMA +# ifdef CONFIG_GD32F4_UART3_RXDMA static char g_uart3rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_GD32F4_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; -# ifdef CONFIG_GD32F4_UART4_RXDMA +# ifdef CONFIG_GD32F4_UART4_RXDMA static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_GD32F4_USART5_SERIALDRIVER static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE]; static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE]; -# ifdef CONFIG_GD32F4_USART5_RXDMA +# ifdef CONFIG_GD32F4_USART5_RXDMA static char g_usart5rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_GD32F4_UART6_SERIALDRIVER static char g_uart6rxbuffer[CONFIG_UART6_RXBUFSIZE]; static char g_uart6txbuffer[CONFIG_UART6_TXBUFSIZE]; -# ifdef CONFIG_GD32F4_UART6_RXDMA +# ifdef CONFIG_GD32F4_UART6_RXDMA static char g_uart6rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_GD32F4_UART7_SERIALDRIVER static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; static char g_uart7txbuffer[CONFIG_UART7_TXBUFSIZE]; -# ifdef CONFIG_GD32F4_UART7_RXDMA +# ifdef CONFIG_GD32F4_UART7_RXDMA static char g_uart7rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif /* This describes the state of the GD32 USART0 ports. */ diff --git a/arch/arm/src/gd32f4/hardware/gd32f4xx_rcu.h b/arch/arm/src/gd32f4/hardware/gd32f4xx_rcu.h index 12db01f252..1851c69da2 100644 --- a/arch/arm/src/gd32f4/hardware/gd32f4xx_rcu.h +++ b/arch/arm/src/gd32f4/hardware/gd32f4xx_rcu.h @@ -236,7 +236,7 @@ #define RCU_CFG0_CKOUT0DIV_SHIFT (24) /* Bits 24-26: The CK_OUT0 divider */ #define RCU_CFG0_CKOUT0DIV_MASK (7 << RCU_CFG0_CKOUT0DIV_SHIFT) -# define RCU_CFG0_CKOUT0DIV(n) ((n) << RCU_CFG0_CKOUT0DIV_SHIFT) +# define RCU_CFG0_CKOUT0DIV(n) ((n) << RCU_CFG0_CKOUT0DIV_SHIFT) # define RCU_CFG0_CKOUT0_DIV1 RCU_CFG0_CKOUT0DIV(0) /* CK_OUT0 is divided by 1, n=0..3 */ # define RCU_CFG0_CKOUT0_DIV2 RCU_CFG0_CKOUT0DIV(4) /* CK_OUT0 is divided by 2 */ # define RCU_CFG0_CKOUT0_DIV3 RCU_CFG0_CKOUT0DIV(5) /* CK_OUT0 is divided by 3 */ @@ -245,7 +245,7 @@ #define RCU_CFG0_CKOUT1DIV_SHIFT (27) /* Bits 27-29: The CK_OUT1 divider */ #define RCU_CFG0_CKOUT1DIV_MASK (7 << RCU_CFG0_CKOUT1DIV_SHIFT) -# define RCU_CFG0_CKOUT1DIV(n) ((n) << RCU_CFG0_CKOUT1DIV_SHIFT) +# define RCU_CFG0_CKOUT1DIV(n) ((n) << RCU_CFG0_CKOUT1DIV_SHIFT) # define RCU_CFG0_CKOUT1_DIV1 RCU_CFG0_CKOUT1DIV(0) /* CK_OUT1 is divided by 1, n=0..3 */ # define RCU_CFG0_CKOUT1_DIV2 RCU_CFG0_CKOUT1DIV(4) /* CK_OUT1 is divided by 2 */ # define RCU_CFG0_CKOUT1_DIV3 RCU_CFG0_CKOUT1DIV(5) /* CK_OUT1 is divided by 3 */ diff --git a/arch/arm/src/imx1/imx_serial.c b/arch/arm/src/imx1/imx_serial.c index ea8d1fff0e..69ed4e3fc5 100644 --- a/arch/arm/src/imx1/imx_serial.c +++ b/arch/arm/src/imx1/imx_serial.c @@ -251,107 +251,107 @@ static struct uart_dev_s g_uart3port = /* Now, which one with be tty0/console and which tty1 and tty2? */ #if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART1) -# define CONSOLE_DEV g_uart1port /* UART1 is /dev/console */ -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# define TTYS0_DEV g_uart1port /* UART1 is /dev/ttyS0 */ -# if defined(CONFIG_IMX1_UART2) -# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */ -# if defined(CONFIG_IMX1_UART3) -# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */ -# else -# undef TTYS2_DEV /* No /dev/ttyS2 */ -# endif -# elif defined(CONFIG_IMX1_UART3) -# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */ -# undef TTYS2_DEV /* No /dev/ttyS2 */ -# else -# undef TTYS1_DEV /* No /dev/ttyS1 */ -# undef TTYS2_DEV /* No /dev/ttyS2 */ -# endif - -#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART2) -# define CONSOLE_DEV g_uart2port /* UART2 is /dev/console */ -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE -# define TTYS0_DEV g_uart2port /* UART2 is /dev/ttyS0 */ -# if defined(CONFIG_IMX1_UART1) -# define TTYS1_DEV g_uart1port /* UART1 is /dev/ttyS1 */ -# if defined(CONFIG_IMX1_UART3) -# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */ -# else -# undef TTYS2_DEV /* No /dev/ttyS2 */ -# endif -# elif defined(CONFIG_IMX1_UART3) -# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */ -# else -# undef TTYS1_DEV /* No /dev/ttyS1 */ -# undef TTYS2_DEV /* No /dev/ttyS2 */ -# endif - -#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART3) -# define CONSOLE_DEV g_uart3port /* UART3 is /dev/console */ -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# define TTYS0_DEV g_uart3port /* UART3 is /dev/ttyS0 */ -# if defined(CONFIG_IMX1_UART1) -# define TTYS1_DEV g_uart1port /* UART1 is /dev/ttyS1 */ -# if defined(CONFIG_IMX1_UART2) -# define TTYS2_DEV g_uart2port /* UART2 is /dev/ttyS2 */ -# else -# undef TTYS2_DEV /* No /dev/ttyS2 */ -# endif -# elif defined(CONFIG_IMX1_UART2) -# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */ -# undef TTYS2_DEV /* No /dev/ttyS2 */ -# else -# undef TTYS1_DEV /* No /dev/ttyS1 */ -# undef TTYS2_DEV /* No /dev/ttyS2 */ -# endif - -#else -# undef CONSOLE_DEV g_uart1port /* No /dev/console */ -# undef CONFIG_UART1_SERIAL_CONSOLE -# undef CONFIG_UART2_SERIAL_CONSOLE -# undef CONFIG_UART3_SERIAL_CONSOLE - -# if defined(CONFIG_IMX1_UART1) -# define TTYS0_DEV g_uart1port /* UART1 is /dev/ttyS0 */ +# define CONSOLE_DEV g_uart1port /* UART1 is /dev/console */ +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# define TTYS0_DEV g_uart1port /* UART1 is /dev/ttyS0 */ # if defined(CONFIG_IMX1_UART2) -# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */ +# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */ # if defined(CONFIG_IMX1_UART3) -# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */ +# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */ # else -# undef TTYS2_DEV /* No /dev/ttyS2 */ +# undef TTYS2_DEV /* No /dev/ttyS2 */ # endif # elif defined(CONFIG_IMX1_UART3) -# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */ -# undef TTYS2_DEV /* No /dev/ttyS2 */ +# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */ +# undef TTYS2_DEV /* No /dev/ttyS2 */ # else -# undef TTYS1_DEV /* No /dev/ttyS1 */ -# undef TTYS2_DEV /* No /dev/ttyS2 */ +# undef TTYS1_DEV /* No /dev/ttyS1 */ +# undef TTYS2_DEV /* No /dev/ttyS2 */ # endif -# elif defined(CONFIG_IMX1_UART2) -# define TTYS0_DEV g_uart2port /* UART2 is /dev/ttyS0 */ -# undef TTYS2_DEV /* No /dev/ttyS2 */ -# if defined(CONFIG_IMX1_UART3) -# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */ +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART2) +# define CONSOLE_DEV g_uart2port /* UART2 is /dev/console */ +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# define TTYS0_DEV g_uart2port /* UART2 is /dev/ttyS0 */ +# if defined(CONFIG_IMX1_UART1) +# define TTYS1_DEV g_uart1port /* UART1 is /dev/ttyS1 */ +# if defined(CONFIG_IMX1_UART3) +# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */ +# else +# undef TTYS2_DEV /* No /dev/ttyS2 */ +# endif +# elif defined(CONFIG_IMX1_UART3) +# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */ # else -# undef TTYS1_DEV /* No /dev/ttyS1 */ +# undef TTYS1_DEV /* No /dev/ttyS1 */ +# undef TTYS2_DEV /* No /dev/ttyS2 */ # endif -# elif defined(CONFIG_IMX1_UART3) -# define TTYS0_DEV g_uart3port /* UART3 is /dev/ttyS0 */ -# undef TTYS1_DEV /* No /dev/ttyS1 */ -# undef TTYS2_DEV /* No /dev/ttyS2 */ +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_IMX1_UART3) +# define CONSOLE_DEV g_uart3port /* UART3 is /dev/console */ +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# define TTYS0_DEV g_uart3port /* UART3 is /dev/ttyS0 */ +# if defined(CONFIG_IMX1_UART1) +# define TTYS1_DEV g_uart1port /* UART1 is /dev/ttyS1 */ +# if defined(CONFIG_IMX1_UART2) +# define TTYS2_DEV g_uart2port /* UART2 is /dev/ttyS2 */ +# else +# undef TTYS2_DEV /* No /dev/ttyS2 */ +# endif +# elif defined(CONFIG_IMX1_UART2) +# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */ +# undef TTYS2_DEV /* No /dev/ttyS2 */ +# else +# undef TTYS1_DEV /* No /dev/ttyS1 */ +# undef TTYS2_DEV /* No /dev/ttyS2 */ +# endif -# else -# error "No UARTs enabled" -# undef TTYS0_DEV /* No /dev/ttyS0 */ -# undef TTYS1_DEV /* No /dev/ttyS1 */ -# undef TTYS2_DEV /* No /dev/ttyS2 */ -# endif +#else +# undef CONSOLE_DEV g_uart1port /* No /dev/console */ +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE + +# if defined(CONFIG_IMX1_UART1) +# define TTYS0_DEV g_uart1port /* UART1 is /dev/ttyS0 */ +# if defined(CONFIG_IMX1_UART2) +# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */ +# if defined(CONFIG_IMX1_UART3) +# define TTYS2_DEV g_uart3port /* UART3 is /dev/ttyS2 */ +# else +# undef TTYS2_DEV /* No /dev/ttyS2 */ +# endif +# elif defined(CONFIG_IMX1_UART3) +# define TTYS1_DEV g_uart3port /* UART3 is /dev/ttyS1 */ +# undef TTYS2_DEV /* No /dev/ttyS2 */ +# else +# undef TTYS1_DEV /* No /dev/ttyS1 */ +# undef TTYS2_DEV /* No /dev/ttyS2 */ +# endif + +# elif defined(CONFIG_IMX1_UART2) +# define TTYS0_DEV g_uart2port /* UART2 is /dev/ttyS0 */ +# undef TTYS2_DEV /* No /dev/ttyS2 */ +# if defined(CONFIG_IMX1_UART3) +# define TTYS1_DEV g_uart2port /* UART2 is /dev/ttyS1 */ +# else +# undef TTYS1_DEV /* No /dev/ttyS1 */ +# endif + +# elif defined(CONFIG_IMX1_UART3) +# define TTYS0_DEV g_uart3port /* UART3 is /dev/ttyS0 */ +# undef TTYS1_DEV /* No /dev/ttyS1 */ +# undef TTYS2_DEV /* No /dev/ttyS2 */ + +# else +# error "No UARTs enabled" +# undef TTYS0_DEV /* No /dev/ttyS0 */ +# undef TTYS1_DEV /* No /dev/ttyS1 */ +# undef TTYS2_DEV /* No /dev/ttyS2 */ +# endif #endif /**************************************************************************** @@ -1140,12 +1140,12 @@ void arm_serialinit(void) #ifdef TTYS0_DEV uart_register("/dev/ttyS0", &TTYS0_DEV); -# ifdef TTYS1_DEV +# ifdef TTYS1_DEV uart_register("/dev/ttyS1", &TTYS1_DEV); -# ifdef TTYS2_DEV +# ifdef TTYS2_DEV uart_register("/dev/ttyS2", &TTYS2_DEV); +# endif # endif -# endif #endif } diff --git a/arch/arm/src/imx6/hardware/imx_enet.h b/arch/arm/src/imx6/hardware/imx_enet.h index 1f38f1a666..23fc0aa771 100644 --- a/arch/arm/src/imx6/hardware/imx_enet.h +++ b/arch/arm/src/imx6/hardware/imx_enet.h @@ -515,13 +515,13 @@ */ #ifdef IMX_ENET_HAS_DBSWAP -# ifndef CONFIG_ENDIAN_BIG -# define IMX_USE_DBSWAP -# endif +# ifndef CONFIG_ENDIAN_BIG +# define IMX_USE_DBSWAP +# endif #else -# ifndef CONFIG_ENDIAN_BIG -# define IMX_BUFFERS_SWAP -# endif +# ifndef CONFIG_ENDIAN_BIG +# define IMX_BUFFERS_SWAP +# endif #endif #ifndef IMX_BUFFERS_SWAP diff --git a/arch/arm/src/imx6/imx_serial.c b/arch/arm/src/imx6/imx_serial.c index 5ddfce8c52..6b7a3ec809 100644 --- a/arch/arm/src/imx6/imx_serial.c +++ b/arch/arm/src/imx6/imx_serial.c @@ -1090,18 +1090,18 @@ void arm_serialinit(void) #ifdef TTYS0_DEV uart_register("/dev/ttyS0", &TTYS0_DEV); -# ifdef TTYS1_DEV +# ifdef TTYS1_DEV uart_register("/dev/ttyS1", &TTYS1_DEV); -# ifdef TTYS2_DEV +# ifdef TTYS2_DEV uart_register("/dev/ttyS2", &TTYS2_DEV); -# ifdef TTYS3_DEV +# ifdef TTYS3_DEV uart_register("/dev/ttyS3", &TTYS2_DEV); -# ifdef TTYS4_DEV +# ifdef TTYS4_DEV uart_register("/dev/ttyS4", &TTYS2_DEV); +# endif # endif # endif # endif -# endif #endif } diff --git a/arch/arm/src/imxrt/hardware/imxrt_enet.h b/arch/arm/src/imxrt/hardware/imxrt_enet.h index ca423ae1b6..486a30f144 100644 --- a/arch/arm/src/imxrt/hardware/imxrt_enet.h +++ b/arch/arm/src/imxrt/hardware/imxrt_enet.h @@ -509,13 +509,13 @@ */ #ifdef IMXRT_ENET_HAS_DBSWAP -# ifndef CONFIG_ENDIAN_BIG -# define IMXRT_USE_DBSWAP -# endif +# ifndef CONFIG_ENDIAN_BIG +# define IMXRT_USE_DBSWAP +# endif #else -# ifndef CONFIG_ENDIAN_BIG -# define IMXRT_BUFFERS_SWAP -# endif +# ifndef CONFIG_ENDIAN_BIG +# define IMXRT_BUFFERS_SWAP +# endif #endif #ifndef IMXRT_BUFFERS_SWAP diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h index 4eed2f4e0f..b2630e0236 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_ccm.h @@ -200,7 +200,7 @@ /* Bits 13-15: Reserved */ #define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */ #define CCM_CBCDR_SEMC_PODF_MASK (0x7 << CCM_CBCDR_SEMC_PODF_SHIFT) -# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT) +# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT) /* Bits 19-24: Reserved */ #define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */ #define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) diff --git a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h index 094f9513dc..08e1565707 100644 --- a/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h +++ b/arch/arm/src/imxrt/hardware/rt102x/imxrt102x_iomuxc.h @@ -1012,7 +1012,7 @@ #define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP (1 << 14) #define GPR_GPR2_MQS_CLK_DIV_SHIFT (16) #define GPR_GPR2_MQS_CLK_DIV_MASK (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT) -# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT) +# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT) #define GPR_GPR2_MQS_SW_RST_EN (1 << 24) #define GPR_GPR2_MQS_EN (1 << 25) #define GPR_GPR2_MQS_OVERSAMPLE32 (0 << 26) diff --git a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h index 94ec88384b..183a761678 100644 --- a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h +++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_ccm.h @@ -209,7 +209,7 @@ /* Bits 13-15: Reserved */ #define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */ #define CCM_CBCDR_SEMC_PODF_MASK (0x3 << CCM_CBCDR_SEMC_PODF_SHIFT) -# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT) +# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT) /* Bits 19-24: Reserved */ #define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */ #define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) @@ -262,7 +262,7 @@ /* Bits 20-22: Reserved */ #define CCM_CBCMR_LCDIF_PODF_SHIFT (23) /* Bits 23-25: Post-divider for LCDIF clock */ #define CCM_CBCMR_LCDIF_PODF_MASK (0x7 << CCM_CBCMR_LCDIF_PODF_SHIFT) -# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT) +# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT) #define CCM_CBCMR_LPSPI_PODF_SHIFT (26) /* Bits 26-28: Divider for LPSPI */ #define CCM_CBCMR_LPSPI_PODF_MASK (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT) # define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT) diff --git a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h index 0c32cd4093..46a31b670c 100644 --- a/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h +++ b/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_iomuxc.h @@ -1288,7 +1288,7 @@ #define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP (1 << 14) #define GPR_GPR2_MQS_CLK_DIV_SHIFT (16) #define GPR_GPR2_MQS_CLK_DIV_MASK (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT) -# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT) +# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT) #define GPR_GPR2_MQS_SW_RST_EN (1 << 24) #define GPR_GPR2_MQS_EN (1 << 25) #define GPR_GPR2_MQS_OVERSAMPLE32 (0 << 26) diff --git a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h index bd3fe42ce6..402ccd62c0 100644 --- a/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h +++ b/arch/arm/src/imxrt/hardware/rt106x/imxrt106x_ccm.h @@ -205,7 +205,7 @@ /* Bits 13-15: Reserved */ #define CCM_CBCDR_SEMC_PODF_SHIFT (16) /* Bits 16-18: Post divider for SEMC clock */ #define CCM_CBCDR_SEMC_PODF_MASK (0x3 << CCM_CBCDR_SEMC_PODF_SHIFT) -# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT) +# define CCM_CBCDR_SEMC_PODF(n) ((uint32_t)(n) << CCM_CBCDR_SEMC_PODF_SHIFT) /* Bits 19-24: Reserved */ #define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25) /* Bit 25: Selector for peripheral main clock */ #define CCM_CBCDR_PERIPH_CLK_SEL_MASK (1 << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT) @@ -268,7 +268,7 @@ /* Bits 20-22: Reserved */ #define CCM_CBCMR_LCDIF_PODF_SHIFT (23) /* Bits 23-25: Post-divider for LCDIF clock */ #define CCM_CBCMR_LCDIF_PODF_MASK (0x7 << CCM_CBCMR_LCDIF_PODF_SHIFT) -# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT) +# define CCM_CBCMR_LCDIF_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LCDIF_PODF_SHIFT) #define CCM_CBCMR_LPSPI_PODF_SHIFT (26) /* Bits 26-28: Divider for LPSPI */ #define CCM_CBCMR_LPSPI_PODF_MASK (0x7 << CCM_CBCMR_LPSPI_PODF_SHIFT) # define CCM_CBCMR_LPSPI_PODF(n) ((uint32_t)(n) << CCM_CBCMR_LPSPI_PODF_SHIFT) diff --git a/arch/arm/src/imxrt/imxrt_allocateheap.c b/arch/arm/src/imxrt/imxrt_allocateheap.c index 333804c863..414fc487bc 100644 --- a/arch/arm/src/imxrt/imxrt_allocateheap.c +++ b/arch/arm/src/imxrt/imxrt_allocateheap.c @@ -121,9 +121,9 @@ */ #if defined(IMXRT_OCRAM2_BASE) -# define _IMXRT_OCRAM_BASE IMXRT_OCRAM2_BASE +# define _IMXRT_OCRAM_BASE IMXRT_OCRAM2_BASE #else -# define _IMXRT_OCRAM_BASE IMXRT_OCRAM_BASE +# define _IMXRT_OCRAM_BASE IMXRT_OCRAM_BASE #endif #define CONFIG_ITCM_USED 0 diff --git a/arch/arm/src/imxrt/imxrt_enc.c b/arch/arm/src/imxrt/imxrt_enc.c index 5640efaa49..4bca7619ba 100644 --- a/arch/arm/src/imxrt/imxrt_enc.c +++ b/arch/arm/src/imxrt/imxrt_enc.c @@ -77,7 +77,7 @@ #endif #ifndef CONFIG_ENC1_HNE -# define CONFIG_ENC1_HNE 0 +# define CONFIG_ENC1_HNE 0 #endif #ifndef CONFIG_ENC1_XIE @@ -89,7 +89,7 @@ #endif #ifndef CONFIG_ENC1_XNE -# define CONFIG_ENC1_XNE 0 +# define CONFIG_ENC1_XNE 0 #endif #ifndef CONFIG_ENC1_MOD @@ -97,7 +97,7 @@ #endif #ifndef CONFIG_ENC1_MODULUS -# define CONFIG_ENC1_MODULUS 0 +# define CONFIG_ENC1_MODULUS 0 #endif #if defined(CONFIG_DEBUG_SENSORS) @@ -122,7 +122,7 @@ #endif #ifndef CONFIG_ENC2_HNE -# define CONFIG_ENC2_HNE 0 +# define CONFIG_ENC2_HNE 0 #endif #ifndef CONFIG_ENC2_XIE @@ -134,7 +134,7 @@ #endif #ifndef CONFIG_ENC2_XNE -# define CONFIG_ENC2_XNE 0 +# define CONFIG_ENC2_XNE 0 #endif #ifndef CONFIG_ENC2_MOD @@ -142,7 +142,7 @@ #endif #ifndef CONFIG_ENC2_MODULUS -# define CONFIG_ENC2_MODULUS 0 +# define CONFIG_ENC2_MODULUS 0 #endif #if defined(CONFIG_DEBUG_SENSORS) @@ -167,7 +167,7 @@ #endif #ifndef CONFIG_ENC3_HNE -# define CONFIG_ENC3_HNE 0 +# define CONFIG_ENC3_HNE 0 #endif #ifndef CONFIG_ENC3_XIE @@ -179,7 +179,7 @@ #endif #ifndef CONFIG_ENC3_XNE -# define CONFIG_ENC3_XNE 0 +# define CONFIG_ENC3_XNE 0 #endif #ifndef CONFIG_ENC3_MOD @@ -187,7 +187,7 @@ #endif #ifndef CONFIG_ENC3_MODULUS -# define CONFIG_ENC3_MODULUS 0 +# define CONFIG_ENC3_MODULUS 0 #endif #if defined(CONFIG_DEBUG_SENSORS) @@ -212,7 +212,7 @@ #endif #ifndef CONFIG_ENC4_HNE -# define CONFIG_ENC4_HNE 0 +# define CONFIG_ENC4_HNE 0 #endif #ifndef CONFIG_ENC4_XIE @@ -224,7 +224,7 @@ #endif #ifndef CONFIG_ENC4_XNE -# define CONFIG_ENC4_XNE 0 +# define CONFIG_ENC4_XNE 0 #endif #ifndef CONFIG_ENC4_MOD @@ -232,7 +232,7 @@ #endif #ifndef CONFIG_ENC4_MODULUS -# define CONFIG_ENC4_MODULUS 0 +# define CONFIG_ENC4_MODULUS 0 #endif #if defined(CONFIG_DEBUG_SENSORS) diff --git a/arch/arm/src/imxrt/imxrt_flexcan.c b/arch/arm/src/imxrt/imxrt_flexcan.c index 8221647c8b..af035867ce 100644 --- a/arch/arm/src/imxrt/imxrt_flexcan.c +++ b/arch/arm/src/imxrt/imxrt_flexcan.c @@ -821,10 +821,10 @@ static void imxrt_receive(struct imxrt_driver_s *priv, uint32_t mbi; uint32_t mbj; struct mb_s *rf; -# ifdef CONFIG_NET_CAN_CANFD +#ifdef CONFIG_NET_CAN_CANFD uint32_t *frame_data_word; uint32_t i; -# endif +#endif uint32_t f; while ((f = flags) != 0) diff --git a/arch/arm/src/imxrt/imxrt_flexpwm.c b/arch/arm/src/imxrt/imxrt_flexpwm.c index ec841d4cfb..23e635f503 100644 --- a/arch/arm/src/imxrt/imxrt_flexpwm.c +++ b/arch/arm/src/imxrt/imxrt_flexpwm.c @@ -52,9 +52,9 @@ #ifdef CONFIG_IMXRT_FLEXPWM #ifdef CONFIG_PWM_NCHANNELS -# define PWM_NCHANNELS CONFIG_PWM_NCHANNELS +# define PWM_NCHANNELS CONFIG_PWM_NCHANNELS #else -# define PWM_NCHANNELS 1 +# define PWM_NCHANNELS 1 #endif #define MODULE_OFFSET 0x60 diff --git a/arch/arm/src/imxrt/imxrt_serial.c b/arch/arm/src/imxrt/imxrt_serial.c index fcf14e51df..805f33e874 100644 --- a/arch/arm/src/imxrt/imxrt_serial.c +++ b/arch/arm/src/imxrt/imxrt_serial.c @@ -804,15 +804,15 @@ static struct imxrt_uart_s g_lpuart1priv = .size = CONFIG_LPUART1_TXBUFSIZE, .buffer = g_lpuart1txbuffer, }, - #if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) +# if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA) +# elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) +# elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart1priv, }, @@ -822,38 +822,38 @@ static struct imxrt_uart_s g_lpuart1priv = .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) .oflow = 1, .cts_gpio = GPIO_LPUART1_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) \ || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL))) .rts_gpio = GPIO_LPUART1_RTS, -#endif -#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE .tx_gpio = GPIO_LPUART1_TX, -#endif +# endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ +# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ && defined(CONFIG_LPUART1_INVERTIFLOWCONTROL)) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART1_TXDMA +# ifdef CONFIG_LPUART1_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART1_TX, .txdmasem = SEM_INITIALIZER(1), -#endif -#ifdef CONFIG_LPUART1_RXDMA +# endif +# ifdef CONFIG_LPUART1_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART1_RX, .rxfifo = g_lpuart1rxfifo, -#endif +# endif }; #endif @@ -892,37 +892,37 @@ static struct imxrt_uart_s g_lpuart2priv = .parity = CONFIG_LPUART2_PARITY, .bits = CONFIG_LPUART2_BITS, .stopbits2 = CONFIG_LPUART2_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL) .oflow = 1, .cts_gpio = GPIO_LPUART2_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) \ || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL))) .rts_gpio = GPIO_LPUART2_RTS, -#endif -#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE .tx_gpio = GPIO_LPUART2_TX, -#endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ +# endif +# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ && defined(CONFIG_LPUART2_INVERTIFLOWCONTROL)) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART2_TXDMA +# ifdef CONFIG_LPUART2_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART2_TX, .txdmasem = SEM_INITIALIZER(1), -#endif -#ifdef CONFIG_LPUART2_RXDMA +# endif +# ifdef CONFIG_LPUART2_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART2_RX, .rxfifo = g_lpuart2rxfifo, -#endif +# endif }; #endif @@ -941,15 +941,15 @@ static struct imxrt_uart_s g_lpuart3priv = .size = CONFIG_LPUART3_TXBUFSIZE, .buffer = g_lpuart3txbuffer, }, - #if defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA) +# if defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART3_RXDMA) && !defined(CONFIG_LPUART3_TXDMA) +# elif defined(CONFIG_LPUART3_RXDMA) && !defined(CONFIG_LPUART3_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA) +# elif !defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart3priv, }, @@ -959,37 +959,37 @@ static struct imxrt_uart_s g_lpuart3priv = .parity = CONFIG_LPUART3_PARITY, .bits = CONFIG_LPUART3_BITS, .stopbits2 = CONFIG_LPUART3_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART3_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART3_OFLOWCONTROL) .oflow = 1, .cts_gpio = GPIO_LPUART3_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) \ || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL))) .rts_gpio = GPIO_LPUART3_RTS, -#endif -#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE .tx_gpio = GPIO_LPUART3_TX, -#endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ +# endif +# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ && defined(CONFIG_LPUART3_INVERTIFLOWCONTROL)) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART3_TXDMA +# ifdef CONFIG_LPUART3_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART3_TX, .txdmasem = SEM_INITIALIZER(1), -#endif -#ifdef CONFIG_LPUART3_RXDMA +# endif +# ifdef CONFIG_LPUART3_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART3_RX, .rxfifo = g_lpuart3rxfifo, -#endif +# endif }; #endif @@ -1026,37 +1026,37 @@ static struct imxrt_uart_s g_lpuart4priv = .parity = CONFIG_LPUART4_PARITY, .bits = CONFIG_LPUART4_BITS, .stopbits2 = CONFIG_LPUART4_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART4_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART4_OFLOWCONTROL) .oflow = 1, .cts_gpio = GPIO_LPUART4_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) \ || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL))) .rts_gpio = GPIO_LPUART4_RTS, -#endif -#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE .tx_gpio = GPIO_LPUART4_TX, -#endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ +# endif +# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ && defined(CONFIG_LPUART4_INVERTIFLOWCONTROL)) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART4_TXDMA +# ifdef CONFIG_LPUART4_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART4_TX, .txdmasem = SEM_INITIALIZER(1), -#endif -#ifdef CONFIG_LPUART4_RXDMA +# endif +# ifdef CONFIG_LPUART4_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART4_RX, .rxfifo = g_lpuart4rxfifo, -#endif +# endif }; #endif @@ -1075,15 +1075,15 @@ static struct imxrt_uart_s g_lpuart5priv = .size = CONFIG_LPUART5_TXBUFSIZE, .buffer = g_lpuart5txbuffer, }, - #if defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA) +# if defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART5_RXDMA) && !defined(CONFIG_LPUART5_TXDMA) +# elif defined(CONFIG_LPUART5_RXDMA) && !defined(CONFIG_LPUART5_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA) +# elif !defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart5priv, }, @@ -1093,37 +1093,37 @@ static struct imxrt_uart_s g_lpuart5priv = .parity = CONFIG_LPUART5_PARITY, .bits = CONFIG_LPUART5_BITS, .stopbits2 = CONFIG_LPUART5_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART5_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART5_OFLOWCONTROL) .oflow = 1, .cts_gpio = GPIO_LPUART5_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) \ || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL))) .rts_gpio = GPIO_LPUART5_RTS, -#endif -#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE .tx_gpio = GPIO_LPUART5_TX, -#endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ +# endif +# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ && defined(CONFIG_LPUART5_INVERTIFLOWCONTROL)) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART5_TXDMA +# ifdef CONFIG_LPUART5_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART5_TX, .txdmasem = SEM_INITIALIZER(1), -#endif -#ifdef CONFIG_LPUART5_RXDMA +# endif +# ifdef CONFIG_LPUART5_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART5_RX, .rxfifo = g_lpuart5rxfifo, -#endif +# endif }; #endif @@ -1142,15 +1142,15 @@ static struct imxrt_uart_s g_lpuart6priv = .size = CONFIG_LPUART6_TXBUFSIZE, .buffer = g_lpuart6txbuffer, }, - #if defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA) +# if defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART6_RXDMA) && !defined(CONFIG_LPUART6_TXDMA) +# elif defined(CONFIG_LPUART6_RXDMA) && !defined(CONFIG_LPUART6_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA) +# elif !defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart6priv, }, @@ -1160,37 +1160,37 @@ static struct imxrt_uart_s g_lpuart6priv = .parity = CONFIG_LPUART6_PARITY, .bits = CONFIG_LPUART6_BITS, .stopbits2 = CONFIG_LPUART6_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART6_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART6_OFLOWCONTROL) .oflow = 1, .cts_gpio = GPIO_LPUART6_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) \ || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL))) .rts_gpio = GPIO_LPUART6_RTS, -#endif -#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE .tx_gpio = GPIO_LPUART6_TX, -#endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ +# endif +# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ && defined(CONFIG_LPUART6_INVERTIFLOWCONTROL)) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART6_TXDMA +# ifdef CONFIG_LPUART6_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART6_TX, .txdmasem = SEM_INITIALIZER(1), -#endif -#ifdef CONFIG_LPUART6_RXDMA +# endif +# ifdef CONFIG_LPUART6_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART6_RX, .rxfifo = g_lpuart6rxfifo, -#endif +# endif }; #endif @@ -1209,15 +1209,15 @@ static struct imxrt_uart_s g_lpuart7priv = .size = CONFIG_LPUART7_TXBUFSIZE, .buffer = g_lpuart7txbuffer, }, - #if defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA) +# if defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART7_RXDMA) && !defined(CONFIG_LPUART7_TXDMA) +# elif defined(CONFIG_LPUART7_RXDMA) && !defined(CONFIG_LPUART7_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA) +# elif !defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart7priv, }, @@ -1227,37 +1227,37 @@ static struct imxrt_uart_s g_lpuart7priv = .parity = CONFIG_LPUART7_PARITY, .bits = CONFIG_LPUART7_BITS, .stopbits2 = CONFIG_LPUART7_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART7_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART7_OFLOWCONTROL) .oflow = 1, .cts_gpio = GPIO_LPUART7_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) \ || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL))) .rts_gpio = GPIO_LPUART7_RTS, -#endif -#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE .tx_gpio = GPIO_LPUART7_TX, -#endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ +# endif +# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ && defined(CONFIG_LPUART7_INVERTIFLOWCONTROL)) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART7_TXDMA +# ifdef CONFIG_LPUART7_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART7_TX, .txdmasem = SEM_INITIALIZER(1), -#endif -#ifdef CONFIG_LPUART7_RXDMA +# endif +# ifdef CONFIG_LPUART7_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART7_RX, .rxfifo = g_lpuart7rxfifo, -#endif +# endif }; #endif @@ -1276,15 +1276,15 @@ static struct imxrt_uart_s g_lpuart8priv = .size = CONFIG_LPUART8_TXBUFSIZE, .buffer = g_lpuart8txbuffer, }, - #if defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA) +# if defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART8_RXDMA) && !defined(CONFIG_LPUART8_TXDMA) +# elif defined(CONFIG_LPUART8_RXDMA) && !defined(CONFIG_LPUART8_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA) +# elif !defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart8priv, }, @@ -1294,37 +1294,37 @@ static struct imxrt_uart_s g_lpuart8priv = .parity = CONFIG_LPUART8_PARITY, .bits = CONFIG_LPUART8_BITS, .stopbits2 = CONFIG_LPUART8_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART8_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART8_OFLOWCONTROL) .oflow = 1, .cts_gpio = GPIO_LPUART8_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) \ || (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL))) .rts_gpio = GPIO_LPUART8_RTS, -#endif -#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE .tx_gpio = GPIO_LPUART8_TX, -#endif -#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ +# endif +# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \ && defined(CONFIG_LPUART8_INVERTIFLOWCONTROL)) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART8_TXDMA +# ifdef CONFIG_LPUART8_TXDMA .dma_txreqsrc = IMXRT_DMACHAN_LPUART8_TX, .txdmasem = SEM_INITIALIZER(1), -#endif -#ifdef CONFIG_LPUART8_RXDMA +# endif +# ifdef CONFIG_LPUART8_RXDMA .dma_rxreqsrc = IMXRT_DMACHAN_LPUART8_RX, .rxfifo = g_lpuart8rxfifo, -#endif +# endif }; #endif diff --git a/arch/arm/src/imxrt/imxrt_usbdev.c b/arch/arm/src/imxrt/imxrt_usbdev.c index f59bce2d77..fb4ad971f4 100644 --- a/arch/arm/src/imxrt/imxrt_usbdev.c +++ b/arch/arm/src/imxrt/imxrt_usbdev.c @@ -408,8 +408,8 @@ struct imxrt_usbdev_s static uint32_t imxrt_getreg(uint32_t addr); static void imxrt_putreg(uint32_t val, uint32_t addr); #else -# define imxrt_getreg(addr) getreg32(addr) -# define imxrt_putreg(val,addr) putreg32(val,addr) +# define imxrt_getreg(addr) getreg32(addr) +# define imxrt_putreg(val,addr) putreg32(val,addr) #endif static inline void imxrt_clrbits(uint32_t mask, uint32_t addr); diff --git a/arch/arm/src/kinetis/hardware/kinetis_adc.h b/arch/arm/src/kinetis/hardware/kinetis_adc.h index 484a9c38a6..31940f8bbc 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_adc.h +++ b/arch/arm/src/kinetis/hardware/kinetis_adc.h @@ -183,10 +183,10 @@ #define ADC_CFG1_MODE_SHIFT (2) /* Bits 2-3: Conversion mode selection */ #define ADC_CFG1_MODE_MASK (3 << ADC_CFG1_MODE_SHIFT) -# define ADC_CFG1_MODE_89BIT (0 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 8-bit; DIFF=1 9-bit */ -# define ADC_CFG1_MODE_1213BIT (1 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 12-bit; DIFF=1 13-bit */ -# define ADC_CFG1_MODE_1011BIT (2 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 10-bit; DIFF=1 11-bit */ -# define ADC_CFG1_MODE_1616BIT (3 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 16-bit; DIFF=1 16-bit */ +# define ADC_CFG1_MODE_89BIT (0 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 8-bit; DIFF=1 9-bit */ +# define ADC_CFG1_MODE_1213BIT (1 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 12-bit; DIFF=1 13-bit */ +# define ADC_CFG1_MODE_1011BIT (2 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 10-bit; DIFF=1 11-bit */ +# define ADC_CFG1_MODE_1616BIT (3 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 16-bit; DIFF=1 16-bit */ #define ADC_CFG1_ADLSMP (1 << 4) /* Bit 4: Sample time configuration */ #define ADC_CFG1_ADIV_SHIFT (5) /* Bits 5-6: Clock divide select */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_enet.h b/arch/arm/src/kinetis/hardware/kinetis_enet.h index fdff9fa392..627dcc53a0 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_enet.h +++ b/arch/arm/src/kinetis/hardware/kinetis_enet.h @@ -489,13 +489,13 @@ */ #ifdef KINETIS_ENET_HAS_DBSWAP -# ifndef CONFIG_ENDIAN_BIG -# define KINETIS_USE_DBSWAP -# endif +# ifndef CONFIG_ENDIAN_BIG +# define KINETIS_USE_DBSWAP +# endif #else -# ifndef CONFIG_ENDIAN_BIG -# define KINETIS_BUFFERS_SWAP -# endif +# ifndef CONFIG_ENDIAN_BIG +# define KINETIS_BUFFERS_SWAP +# endif #endif #ifndef KINETIS_BUFFERS_SWAP diff --git a/arch/arm/src/kinetis/hardware/kinetis_flexbus.h b/arch/arm/src/kinetis/hardware/kinetis_flexbus.h index f926f2995d..6720b02e84 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_flexbus.h +++ b/arch/arm/src/kinetis/hardware/kinetis_flexbus.h @@ -68,8 +68,6 @@ /* Register Addresses *******************************************************/ -# define 0x4000c000 /* FlexBus */ - #define KINETIS_FB_CS_BASE(n) (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CS_OFFSET(n)) #define KINETIS_FB_CSAR(n) (KINETIS_FB_CS_BASE(n)+KINETIS_FB_CSAR_OFFSET) #define KINETIS_FB_CSMR(n) (KINETIS_FB_CS_BASE(n)+KINETIS_FB_CSMR_OFFSET) diff --git a/arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h index ea1181bf43..7e3f3282b6 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h +++ b/arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h @@ -46,10 +46,10 @@ #define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read- * only data (Includes exception * vectors in first 1024 bytes) */ -# if !defined(KINETIS_FLEXMEM_SIZE) +#if !defined(KINETIS_FLEXMEM_SIZE) # define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */ # define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */ -# endif +#endif #define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM * (ICODE/DCODE) */ #define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband diff --git a/arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h index b6d6ff3a91..78fae57db9 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h +++ b/arch/arm/src/kinetis/hardware/kinetis_k64memorymap.h @@ -48,135 +48,135 @@ defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || \ defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12) -# define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read- +# define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read- * only data (Includes exception * vectors in first 1024 bytes) */ -# if !defined(KINETIS_FLEXMEM_SIZE) -# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */ -# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */ -# endif -# define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM +# if !defined(KINETIS_FLEXMEM_SIZE) +# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */ +# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */ +# endif +# define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM * (ICODE/DCODE) */ -# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband +# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband * region */ /* 0x20100000 * -0x21ffffff Reserved */ -# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */ +# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */ /* 0x24000000 * -0x3fffffff Reserved */ -# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral +# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral * bridge 0 (AIPS-Lite0) */ -# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral +# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral * bridge 1 (AIPS-Lite1) */ -# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general +# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general * purpose input/output (GPIO) */ /* 0x40100000 * -0x41ffffff Reserved */ -# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge +# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge * (AIPS-Lite) and general purpose * input/output (GPIO) bitband */ /* 0x44000000 * -0x5fffffff Reserved */ -# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */ -# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */ +# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */ +# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */ /* 0xe0100000 * -0xffffffff Reserved */ /* Peripheral Bridge 0 Memory Map *******************************************/ -# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ -# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ -# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ -# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ -# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */ -# define KINETIS_MPU_BASE 0x4000d000 /* MPU */ -# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ -# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */ -# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */ -# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */ -# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */ -# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */ -# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */ -# define KINETIS_CRC_BASE 0x40032000 /* CRC */ -# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */ -# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */ -# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ -# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */ -# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */ -# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ -# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */ -# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */ -# define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */ -# define KINETIS_SYSR_BASE 0x40041000 /* System register file */ -# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */ -# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */ -# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */ -# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */ -# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */ -# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12)) -# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */ -# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ -# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ -# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ -# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ -# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */ -# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */ -# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */ -# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ -# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */ -# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */ -# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ -# define KINETIS_I2C2_BASE 0x400E6000 /* I2C 2 */ -# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */ -# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ -# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ -# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */ -# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ -# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ -# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ -# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ -# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ -# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ +# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ +# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ +# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ +# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ +# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */ +# define KINETIS_MPU_BASE 0x4000d000 /* MPU */ +# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ +# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */ +# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */ +# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */ +# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */ +# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */ +# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */ +# define KINETIS_CRC_BASE 0x40032000 /* CRC */ +# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */ +# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */ +# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ +# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */ +# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */ +# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ +# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */ +# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */ +# define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */ +# define KINETIS_SYSR_BASE 0x40041000 /* System register file */ +# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */ +# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */ +# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */ +# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */ +# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */ +# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12)) +# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */ +# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ +# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ +# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ +# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ +# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */ +# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */ +# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */ +# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ +# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */ +# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */ +# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ +# define KINETIS_I2C2_BASE 0x400E6000 /* I2C 2 */ +# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */ +# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ +# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ +# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */ +# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ +# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ +# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ +# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ +# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ +# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ /* Peripheral Bridge 1 Memory Map *******************************************/ -# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ -# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */ -# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */ -# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */ -# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */ -# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer 2 */ -# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */ -# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ -# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */ -# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */ -# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */ -# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */ -# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */ -# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general +# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ +# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */ +# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */ +# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */ +# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */ +# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer 2 */ +# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */ +# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ +# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */ +# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */ +# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */ +# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */ +# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */ +# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general * purpose input/output module that shares the * crossbar switch slave port with the AIPS-Lite * is accessed at this address. */ -# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) -# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ -# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ -# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ -# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ -# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ +# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) +# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ +# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ +# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ +# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ +# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ /* Private Peripheral Bus (PPB) Memory Map **********************************/ -# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ -# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ -# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */ -# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ -# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */ -# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */ -# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */ -# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */ -# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ -# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */ -# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ +# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ +# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ +# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */ +# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ +# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */ +# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */ +# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */ +# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */ +# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ +# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */ +# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ #else /* The memory map for other parts is defined in other documents and may or diff --git a/arch/arm/src/kinetis/hardware/kinetis_k66memorymap.h b/arch/arm/src/kinetis/hardware/kinetis_k66memorymap.h index a67d6b0aaa..24d064cc7b 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_k66memorymap.h +++ b/arch/arm/src/kinetis/hardware/kinetis_k66memorymap.h @@ -46,164 +46,164 @@ #if defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \ defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18) -# define KINETIS_FLASH_BASE 0x00000000 /* -0x07ffffff Program flash and read- +# define KINETIS_FLASH_BASE 0x00000000 /* -0x07ffffff Program flash and read- * only data (Includes exception * vectors in first 1024 bytes) */ -# define KINETIS_SDRAMALIAS_BASE 0x08000000 /* -0x0fffffff SDRAM (Aliased area). mapped +# define KINETIS_SDRAMALIAS_BASE 0x08000000 /* -0x0fffffff SDRAM (Aliased area). mapped * to same space of 0x88000000 - * 0x8FFF_FFFF. See bit31 of * SDRAMC */ -# if defined(KINETIS_FLEXMEM_SIZE) -# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */ -# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */ -# else -# define KINETIS_PRGACCLRAM_BASE 0x14000000 /* -0x17ffffff For devices with program flash +# if defined(KINETIS_FLEXMEM_SIZE) +# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */ +# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */ +# else +# define KINETIS_PRGACCLRAM_BASE 0x14000000 /* -0x17ffffff For devices with program flash * only: Programming acceleration * RAM */ -# endif -# define KINETIS_FBALIAS_BASE 0x18000000 /* -0x1bffffff FlexBus (Aliased Area). mapped +# endif +# define KINETIS_FBALIAS_BASE 0x18000000 /* -0x1bffffff FlexBus (Aliased Area). mapped * to same space of 0x9800_0000 - * 0x9BFF_FFFF. See bit31 of * FlexBus chip select */ -# define KINETIS_SRAML_BASE 0x1c000000 /* -0x1fffffff SRAM_L: Lower SRAM +# define KINETIS_SRAML_BASE 0x1c000000 /* -0x1fffffff SRAM_L: Lower SRAM * (ICODE/DCODE) */ -# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband +# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband * region */ /* 0x20100000 * -0x21ffffff Reserved */ -# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */ +# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */ /* 0x24000000 * -0x2fffffff Reserved */ -# define KINETIS_FDATALIAS_BASE 0x30000000 /* -0x33ffffff Flash Data Alias */ -# define KINETIS_FLEXNVMCO_BASE 0x34000000 /* -0x3fffffff FlexNVM Cortex-M4 core only */ -# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral +# define KINETIS_FDATALIAS_BASE 0x30000000 /* -0x33ffffff Flash Data Alias */ +# define KINETIS_FLEXNVMCO_BASE 0x34000000 /* -0x3fffffff FlexNVM Cortex-M4 core only */ +# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral * bridge 0 (AIPS-Lite0) */ -# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral +# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral * bridge 1 (AIPS-Lite1) */ -# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general +# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general * purpose input/output (GPIO) */ /* 0x40100000 * -0x41ffffff Reserved */ -# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge +# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge * (AIPS-Lite) and general purpose * input/output (GPIO) bitband */ /* 0x44000000 * -0x5fffffff Reserved */ -# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus (External Memory - Write-back) */ -# define KINETIS_SDRAMWB_BASE 0x70000000 /* -0x7fffffff SDRAM (External RAM - Write-back) */ -# define KINETIS_SDRAMWT_BASE 0x80000000 /* -0x8fffffff SDRAM (External RAM - Write-through) */ -# define KINETIS_FLEXBUSWT_BASE 0x90000000 /* -0x9fffffff FlexBus (External RAM - Write-through) */ -# define KINETIS_FLEXBUSEP_BASE 0xa0000000 /* -0xdfffffff FlexBus External Peripheral - Not executable)*/ -# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */ +# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus (External Memory - Write-back) */ +# define KINETIS_SDRAMWB_BASE 0x70000000 /* -0x7fffffff SDRAM (External RAM - Write-back) */ +# define KINETIS_SDRAMWT_BASE 0x80000000 /* -0x8fffffff SDRAM (External RAM - Write-through) */ +# define KINETIS_FLEXBUSWT_BASE 0x90000000 /* -0x9fffffff FlexBus (External RAM - Write-through) */ +# define KINETIS_FLEXBUSEP_BASE 0xa0000000 /* -0xdfffffff FlexBus External Peripheral - Not executable)*/ +# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */ /* 0xe0100000 * -0xffffffff Reserved */ /* Peripheral Bridge 0 Memory Map *******************************************/ -# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ -# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ -# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ -# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ -# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */ -# define KINETIS_MPU_BASE 0x4000d000 /* MPU */ -# define KINETIS_SDRAMC_BASE 0x4000f000 /* SDRAMC */ -# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ -# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */ -# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */ -# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */ -# define KINETIS_RNGA_BASE 0x40029000 /* Random Number Generator (RNGA) */ -# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */ -# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */ -# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */ -# define KINETIS_CRC_BASE 0x40032000 /* CRC */ -# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */ -# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */ -# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ -# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */ -# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */ -# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer (FTM) 2 */ -# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ -# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */ -# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */ -# define KINETIS_DAC0_BASE 0x4003f000 /* DAC0 */ -# define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */ -# define KINETIS_SYSR_BASE 0x40041000 /* System register file */ -# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */ -# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */ -# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */ -# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12)) -# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */ -# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ -# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ -# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ -# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ -# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */ -# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */ -# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */ -# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ -# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */ -# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */ -# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ -# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */ -# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ -# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ -# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */ -# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ -# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ -# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ -# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ -# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ -# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ -# define KINETIS_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */ +# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ +# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ +# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ +# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ +# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */ +# define KINETIS_MPU_BASE 0x4000d000 /* MPU */ +# define KINETIS_SDRAMC_BASE 0x4000f000 /* SDRAMC */ +# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ +# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */ +# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */ +# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */ +# define KINETIS_RNGA_BASE 0x40029000 /* Random Number Generator (RNGA) */ +# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */ +# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */ +# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */ +# define KINETIS_CRC_BASE 0x40032000 /* CRC */ +# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */ +# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */ +# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ +# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */ +# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */ +# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer (FTM) 2 */ +# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ +# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */ +# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */ +# define KINETIS_DAC0_BASE 0x4003f000 /* DAC0 */ +# define KINETIS_LPTMR0_BASE 0x40040000 /* Low power timer 0 */ +# define KINETIS_SYSR_BASE 0x40041000 /* System register file */ +# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */ +# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */ +# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */ +# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12)) +# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */ +# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ +# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ +# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ +# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ +# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */ +# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */ +# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */ +# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ +# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */ +# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */ +# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ +# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */ +# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ +# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ +# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */ +# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ +# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ +# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ +# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ +# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ +# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ +# define KINETIS_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */ /* Peripheral Bridge 1 Memory Map *******************************************/ -# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ -# define KINETIS_RNGA_ALT_BASE 0x400a0000 /* Alternate address Random number generator (RNGA) */ -# define KINETIS_USBHS_BASE 0x400a1000 /* USB OTG HS/FS/LS */ -# define KINETIS_USBHSPHY_BASE 0x400a2000 /* USBHS PHY */ -# define KINETIS_USBHSDCD_BASE 0x400a3000 /* USBHS DCD */ -# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */ -# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */ -# define KINETIS_SDHC_BASE 0x400b1000 /* eSDHC */ -# define KINETIS_FTM2_ALT_BASE 0x400b8000 /* Alternate address FlexTimer 2 */ -# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */ -# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ -# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */ -# define KINETIS_LPUART0_BASE 0x400c4000 /* LPUART0 */ -# define KINETIS_TPM1_BASE 0x400c9000 /* TPM1 */ -# define KINETIS_TPM2_BASE 0x400ca000 /* TPM2 */ -# define KINETIS_DAC0_ALT_BASE 0x400cc000 /* Alternate address 12-bit digital-to-analog converter (DAC) 0 */ -# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */ -# define KINETIS_I2C2_BASE 0x400e6000 /* I2C 2 */ -# define KINETIS_I2C3_BASE 0x400e7000 /* I2C 3 */ -# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */ -# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general +# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ +# define KINETIS_RNGA_ALT_BASE 0x400a0000 /* Alternate address Random number generator (RNGA) */ +# define KINETIS_USBHS_BASE 0x400a1000 /* USB OTG HS/FS/LS */ +# define KINETIS_USBHSPHY_BASE 0x400a2000 /* USBHS PHY */ +# define KINETIS_USBHSDCD_BASE 0x400a3000 /* USBHS DCD */ +# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */ +# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */ +# define KINETIS_SDHC_BASE 0x400b1000 /* eSDHC */ +# define KINETIS_FTM2_ALT_BASE 0x400b8000 /* Alternate address FlexTimer 2 */ +# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */ +# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ +# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */ +# define KINETIS_LPUART0_BASE 0x400c4000 /* LPUART0 */ +# define KINETIS_TPM1_BASE 0x400c9000 /* TPM1 */ +# define KINETIS_TPM2_BASE 0x400ca000 /* TPM2 */ +# define KINETIS_DAC0_ALT_BASE 0x400cc000 /* Alternate address 12-bit digital-to-analog converter (DAC) 0 */ +# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */ +# define KINETIS_I2C2_BASE 0x400e6000 /* I2C 2 */ +# define KINETIS_I2C3_BASE 0x400e7000 /* I2C 3 */ +# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */ +# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general * purpose input/output module that shares the * crossbar switch slave port with the AIPS-Lite * is accessed at this address. */ -# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) -# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ -# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ -# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ -# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ -# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ +# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) +# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ +# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ +# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ +# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ +# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ /* Private Peripheral Bus (PPB) Memory Map **********************************/ -# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ -# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ -# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */ -# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ -# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */ -# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */ -# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */ -# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */ -# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ -# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */ -# define KINETIS_CACHECTL_BASE 0xe0082000 /* Cache Controller */ -# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ +# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ +# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ +# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */ +# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ +# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */ +# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */ +# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */ +# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */ +# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ +# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */ +# define KINETIS_CACHECTL_BASE 0xe0082000 /* Cache Controller */ +# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ #else /* The memory map for other parts is defined in other documents and may or diff --git a/arch/arm/src/kinetis/hardware/kinetis_kx6tpm.h b/arch/arm/src/kinetis/hardware/kinetis_kx6tpm.h index 6c28fd9237..881a70ea94 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_kx6tpm.h +++ b/arch/arm/src/kinetis/hardware/kinetis_kx6tpm.h @@ -81,20 +81,20 @@ #define TPM_SC_PS_SHIFT 0 /* Bits 0-2: Prescale Factor Selection */ #define TPM_SC_PS_MASK (7 << TPM_SC_PS_SHIFT) -# define TPM_SC_PS_DIV1 (0 << TPM_SC_PS_SHIFT) /* Divide Clock by 1 */ -# define TPM_SC_PS_DIV2 (1 << TPM_SC_PS_SHIFT) /* Divide Clock by 2 */ -# define TPM_SC_PS_DIV4 (2 << TPM_SC_PS_SHIFT) /* Divide Clock by 4 */ -# define TPM_SC_PS_DIV8 (3 << TPM_SC_PS_SHIFT) /* Divide Clock by 8 */ -# define TPM_SC_PS_DIV16 (4 << TPM_SC_PS_SHIFT) /* Divide Clock by 16 */ -# define TPM_SC_PS_DIV32 (5 << TPM_SC_PS_SHIFT) /* Divide Clock by 32 */ -# define TPM_SC_PS_DIV64 (6 << TPM_SC_PS_SHIFT) /* Divide Clock by 64 */ -# define TPM_SC_PS_DIV128 (7 << TPM_SC_PS_SHIFT) /* Divide Clock by 128 */ +# define TPM_SC_PS_DIV1 (0 << TPM_SC_PS_SHIFT) /* Divide Clock by 1 */ +# define TPM_SC_PS_DIV2 (1 << TPM_SC_PS_SHIFT) /* Divide Clock by 2 */ +# define TPM_SC_PS_DIV4 (2 << TPM_SC_PS_SHIFT) /* Divide Clock by 4 */ +# define TPM_SC_PS_DIV8 (3 << TPM_SC_PS_SHIFT) /* Divide Clock by 8 */ +# define TPM_SC_PS_DIV16 (4 << TPM_SC_PS_SHIFT) /* Divide Clock by 16 */ +# define TPM_SC_PS_DIV32 (5 << TPM_SC_PS_SHIFT) /* Divide Clock by 32 */ +# define TPM_SC_PS_DIV64 (6 << TPM_SC_PS_SHIFT) /* Divide Clock by 64 */ +# define TPM_SC_PS_DIV128 (7 << TPM_SC_PS_SHIFT) /* Divide Clock by 128 */ #define TPM_SC_CMOD_SHIFT 3 /* Bits 3-4: Clock Mode Selection */ #define TPM_SC_CMOD_MASK (3 << TPM_SC_CMOD_SHIFT) -# define TPM_SC_CMOD_DIS (0 << TPM_SC_CMOD_SHIFT) /* TPM counter is disabled */ -# define TPM_SC_CMOD_LPTPM_CLK (1 << TPM_SC_CMOD_SHIFT) /* TPM increments on every counter clock */ -# define TPM_SC_CMOD_LPTPM_EXTCLK (2 << TPM_SC_CMOD_SHIFT) /* TPM increments on rising edge of EXTCLK */ +# define TPM_SC_CMOD_DIS (0 << TPM_SC_CMOD_SHIFT) /* TPM counter is disabled */ +# define TPM_SC_CMOD_LPTPM_CLK (1 << TPM_SC_CMOD_SHIFT) /* TPM increments on every counter clock */ +# define TPM_SC_CMOD_LPTPM_EXTCLK (2 << TPM_SC_CMOD_SHIFT) /* TPM increments on rising edge of EXTCLK */ #define TPM_SC_CPWMS (1 << 5) /* Bit 5: Center-aligned PWM Select */ #define TPM_SC_TOIE (1 << 6) /* Bit 6: Timer Overflow Interrupt Enable */ @@ -162,8 +162,8 @@ #define TPM_CONF_DBGMODE_SHIFT 6 /* Bits 6-7: Debug Mode */ #define TPM_CONF_DBGMODE_MASK (3 << TPM_CONF_DBGMODE_SHIFT) -# define TPM_CONF_DBGMODE_PAUSE (0 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter will pause during DEBUG mode */ -# define TPM_CONF_DBGMODE_CONT (3 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter continue working in DEBUG mode */ +# define TPM_CONF_DBGMODE_PAUSE (0 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter will pause during DEBUG mode */ +# define TPM_CONF_DBGMODE_CONT (3 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter continue working in DEBUG mode */ #define TPM_CONF_GTBSYNC (1 << 8) /* Bit 8: Global Time Base Synchronization */ #define TPM_CONF_GTBEEN (1 << 9) /* Bit 9: Global Time Base Enable */ @@ -179,25 +179,25 @@ #define TPM_CONF_TRGSEL_SHIFT 24 /* Bits 24-27: Trigger Select */ #define TPM_CONF_TRGSEL_MASK (0xf << TPM_CONF_TRGSEL_SHIFT) /* Internal TPM_CONF_TRGSRC set */ -# define TPM_CONF_TRGSEL_INTC0 (0 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 0 pin input capture */ -# define TPM_CONF_TRGSEL_INTC1 (2 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 1 pin input capture */ -# define TPM_CONF_TRGSEL_INTC01 (3 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 0 or 1 pin input capture */ +# define TPM_CONF_TRGSEL_INTC0 (0 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 0 pin input capture */ +# define TPM_CONF_TRGSEL_INTC1 (2 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 1 pin input capture */ +# define TPM_CONF_TRGSEL_INTC01 (3 << TPM_CONF_TRGSEL_SHIFT) /* Internal Channel 0 or 1 pin input capture */ -# define TPM_CONF_TRGSEL_EXTRG_IN (0 << TPM_CONF_TRGSEL_SHIFT) /* External trigger pin input */ -# define TPM_CONF_TRGSEL_CMP0 (1 << TPM_CONF_TRGSEL_SHIFT) /* CPM0 output */ -# define TPM_CONF_TRGSEL_CMP1 (2 << TPM_CONF_TRGSEL_SHIFT) /* CPM1 output */ -# define TPM_CONF_TRGSEL_CMP2 (3 << TPM_CONF_TRGSEL_SHIFT) /* CPM2 output */ -# define TPM_CONF_TRGSEL_PIT0 (4 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 0 */ -# define TPM_CONF_TRGSEL_PIT1 (5 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 1 */ -# define TPM_CONF_TRGSEL_PIT2 (6 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 2 */ -# define TPM_CONF_TRGSEL_PIT3 (7 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 3 */ -# define TPM_CONF_TRGSEL_FTM0 (8 << TPM_CONF_TRGSEL_SHIFT) /* FTM0 initialization trigger and channel triggers */ -# define TPM_CONF_TRGSEL_FTM1 (9 << TPM_CONF_TRGSEL_SHIFT) /* FTM1 initialization trigger and channel triggers */ -# define TPM_CONF_TRGSEL_FTM2 (10 << TPM_CONF_TRGSEL_SHIFT) /* FTM2 initialization trigger and channel triggers */ -# define TPM_CONF_TRGSEL_FTM3 (11 << TPM_CONF_TRGSEL_SHIFT) /* FTM3 initialization trigger and channel triggers */ -# define TPM_CONF_TRGSEL_RTC_ALRM (12 << TPM_CONF_TRGSEL_SHIFT) /* RTC Alarm */ -# define TPM_CONF_TRGSEL_RTC_SECS (13 << TPM_CONF_TRGSEL_SHIFT) /* RTC Seconds */ -# define TPM_CONF_TRGSEL_LPTMR (14 << TPM_CONF_TRGSEL_SHIFT) /* LPTMR trigger */ -# define TPM_CONF_TRGSEL_SW (15 << TPM_CONF_TRGSEL_SHIFT) /* Software Trigger */ +# define TPM_CONF_TRGSEL_EXTRG_IN (0 << TPM_CONF_TRGSEL_SHIFT) /* External trigger pin input */ +# define TPM_CONF_TRGSEL_CMP0 (1 << TPM_CONF_TRGSEL_SHIFT) /* CPM0 output */ +# define TPM_CONF_TRGSEL_CMP1 (2 << TPM_CONF_TRGSEL_SHIFT) /* CPM1 output */ +# define TPM_CONF_TRGSEL_CMP2 (3 << TPM_CONF_TRGSEL_SHIFT) /* CPM2 output */ +# define TPM_CONF_TRGSEL_PIT0 (4 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 0 */ +# define TPM_CONF_TRGSEL_PIT1 (5 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 1 */ +# define TPM_CONF_TRGSEL_PIT2 (6 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 2 */ +# define TPM_CONF_TRGSEL_PIT3 (7 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 3 */ +# define TPM_CONF_TRGSEL_FTM0 (8 << TPM_CONF_TRGSEL_SHIFT) /* FTM0 initialization trigger and channel triggers */ +# define TPM_CONF_TRGSEL_FTM1 (9 << TPM_CONF_TRGSEL_SHIFT) /* FTM1 initialization trigger and channel triggers */ +# define TPM_CONF_TRGSEL_FTM2 (10 << TPM_CONF_TRGSEL_SHIFT) /* FTM2 initialization trigger and channel triggers */ +# define TPM_CONF_TRGSEL_FTM3 (11 << TPM_CONF_TRGSEL_SHIFT) /* FTM3 initialization trigger and channel triggers */ +# define TPM_CONF_TRGSEL_RTC_ALRM (12 << TPM_CONF_TRGSEL_SHIFT) /* RTC Alarm */ +# define TPM_CONF_TRGSEL_RTC_SECS (13 << TPM_CONF_TRGSEL_SHIFT) /* RTC Seconds */ +# define TPM_CONF_TRGSEL_LPTMR (14 << TPM_CONF_TRGSEL_SHIFT) /* LPTMR trigger */ +# define TPM_CONF_TRGSEL_SW (15 << TPM_CONF_TRGSEL_SHIFT) /* Software Trigger */ #endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_KX6TPM_H */ diff --git a/arch/arm/src/kinetis/hardware/kinetis_sim.h b/arch/arm/src/kinetis/hardware/kinetis_sim.h index eb8399d4b6..21367a376e 100644 --- a/arch/arm/src/kinetis/hardware/kinetis_sim.h +++ b/arch/arm/src/kinetis/hardware/kinetis_sim.h @@ -639,7 +639,7 @@ #endif /* Bits 13-14: Reserved */ #if defined(KINETIS_SIM_SOPT7_ADC1ALTTRGEN) -# define SIM_SOPT7_ADC1ALTTRGEN (1 << 15) /* Bit 15: ADC1 alternate trigger enable */ +# define SIM_SOPT7_ADC1ALTTRGEN (1 << 15) /* Bit 15: ADC1 alternate trigger enable */ #endif /* Bits 16-31: Reserved */ #if defined(KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL) diff --git a/arch/arm/src/kinetis/kinetis_clockconfig.c b/arch/arm/src/kinetis/kinetis_clockconfig.c index 036023373f..e47d6ad4bb 100644 --- a/arch/arm/src/kinetis/kinetis_clockconfig.c +++ b/arch/arm/src/kinetis/kinetis_clockconfig.c @@ -68,15 +68,15 @@ /* A board may provide BOARD_EXTAL_LP to not choose MCG_C2_HGO */ -# if defined(BOARD_EXTAL_LP) -# define BOARD_MGC_C2_HGO 0 /* Do not use MCG_C2_HGO */ -# else -# if !defined(KINETIS_MCG_HAS_C2_HGO) -# error BOARD_EXTAL_LP is not defined and MCG_C2_HGO is not supported on this SoC! -# else -# define BOARD_MGC_C2_HGO MCG_C2_HGO -# endif -# endif +# if defined(BOARD_EXTAL_LP) +# define BOARD_MGC_C2_HGO 0 /* Do not use MCG_C2_HGO */ +# else +# if !defined(KINETIS_MCG_HAS_C2_HGO) +# error BOARD_EXTAL_LP is not defined and MCG_C2_HGO is not supported on this SoC! +# else +# define BOARD_MGC_C2_HGO MCG_C2_HGO +# endif +# endif /* A board must provide BOARD_MCG_C2_FCFTRIM when SoC has the setting */ @@ -97,11 +97,11 @@ /* A board must provide BOARD_MCG_C2_LOCRE0 when SoC has the setting */ # if defined(KINETIS_MCG_HAS_C2_LOCRE0) && !defined(BOARD_MCG_C2_LOCRE0) -# error MCG_C2_LOCRE0 is supported on this SoC and BOARD_MCG_C2_LOCRE0 is not defined! +# error MCG_C2_LOCRE0 is supported on this SoC and BOARD_MCG_C2_LOCRE0 is not defined! # endif # if !defined(KINETIS_MCG_HAS_C2_LOCRE0) && defined(BOARD_MCG_C2_LOCRE0) -# error BOARD_MCG_C2_LOCRE0 is defined but MCG_C2_LOCRE0 is not supported on this SoC! +# error BOARD_MCG_C2_LOCRE0 is defined but MCG_C2_LOCRE0 is not supported on this SoC! # endif /* Provide the 0 default */ diff --git a/arch/arm/src/kinetis/kinetis_config.h b/arch/arm/src/kinetis/kinetis_config.h index 239e579e3d..3a40e011ee 100644 --- a/arch/arm/src/kinetis/kinetis_config.h +++ b/arch/arm/src/kinetis/kinetis_config.h @@ -334,7 +334,7 @@ #endif #ifndef CONFIG_ENETNETHIFS -# define CONFIG_ENETNETHIFS 1 +# define CONFIG_ENETNETHIFS 1 #endif /**************************************************************************** diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c index 78bcd357a3..8ae96a6f8b 100644 --- a/arch/arm/src/kinetis/kinetis_serial.c +++ b/arch/arm/src/kinetis/kinetis_serial.c @@ -405,55 +405,55 @@ static const struct uart_ops_s g_uart_dma_ops = #ifdef CONFIG_KINETIS_UART0 static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; -# ifdef CONFIG_KINETIS_UART0_RXDMA +# ifdef CONFIG_KINETIS_UART0_RXDMA static char g_uart0rxfifo[RXDMA_BUFFER_SIZE] aligned_data(ARMV7M_DCACHE_LINESIZE); -# endif +# endif #endif #ifdef CONFIG_KINETIS_UART1 static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; -# ifdef CONFIG_KINETIS_UART1_RXDMA +# ifdef CONFIG_KINETIS_UART1_RXDMA static char g_uart1rxfifo[RXDMA_BUFFER_SIZE] aligned_data(ARMV7M_DCACHE_LINESIZE); -# endif +# endif #endif #ifdef CONFIG_KINETIS_UART2 static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; -# ifdef CONFIG_KINETIS_UART2_RXDMA +# ifdef CONFIG_KINETIS_UART2_RXDMA static char g_uart2rxfifo[RXDMA_BUFFER_SIZE] aligned_data(ARMV7M_DCACHE_LINESIZE); -# endif +# endif #endif #ifdef CONFIG_KINETIS_UART3 static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE]; static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE]; -# ifdef CONFIG_KINETIS_UART3_RXDMA +# ifdef CONFIG_KINETIS_UART3_RXDMA static char g_uart3rxfifo[RXDMA_BUFFER_SIZE] aligned_data(ARMV7M_DCACHE_LINESIZE); -# endif +# endif #endif #ifdef CONFIG_KINETIS_UART4 static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; -# ifdef CONFIG_KINETIS_UART4_RXDMA +# ifdef CONFIG_KINETIS_UART4_RXDMA static char g_uart4rxfifo[RXDMA_BUFFER_SIZE] aligned_data(ARMV7M_DCACHE_LINESIZE); -# endif +# endif #endif #ifdef CONFIG_KINETIS_UART5 static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; -# ifdef CONFIG_KINETIS_UART5_RXDMA +# ifdef CONFIG_KINETIS_UART5_RXDMA static char g_uart5rxfifo[RXDMA_BUFFER_SIZE] aligned_data(ARMV7M_DCACHE_LINESIZE); -# endif +# endif #endif /* This describes the state of the Kinetis UART0 port. */ @@ -464,25 +464,25 @@ static struct up_dev_s g_uart0priv = .uartbase = KINETIS_UART0_BASE, .clock = BOARD_CORECLK_FREQ, .baud = CONFIG_UART0_BAUD, -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES .irqe = KINETIS_IRQ_UART0E, -#endif +# endif .irqs = KINETIS_IRQ_UART0S, .parity = CONFIG_UART0_PARITY, .bits = CONFIG_UART0_BITS, .stop2 = CONFIG_UART0_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART0_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART0_OFLOWCONTROL) .oflow = true, .cts_gpio = PIN_UART0_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART0_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART0_IFLOWCONTROL) .iflow = true, .rts_gpio = PIN_UART0_RTS, -#endif -#ifdef CONFIG_KINETIS_UART0_RXDMA +# endif +# ifdef CONFIG_KINETIS_UART0_RXDMA .rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART0_RX, .rxfifo = g_uart0rxfifo, -#endif +# endif }; static uart_dev_t g_uart0port = @@ -497,11 +497,11 @@ static uart_dev_t g_uart0port = .size = CONFIG_UART0_TXBUFSIZE, .buffer = g_uart0txbuffer, }, -#ifdef CONFIG_KINETIS_UART0_RXDMA +# ifdef CONFIG_KINETIS_UART0_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart0priv, }; #endif @@ -514,25 +514,25 @@ static struct up_dev_s g_uart1priv = .uartbase = KINETIS_UART1_BASE, .clock = BOARD_CORECLK_FREQ, .baud = CONFIG_UART1_BAUD, -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES .irqe = KINETIS_IRQ_UART1E, -#endif +# endif .irqs = KINETIS_IRQ_UART1S, .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, .stop2 = CONFIG_UART1_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART1_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART1_OFLOWCONTROL) .oflow = true, .cts_gpio = PIN_UART1_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART1_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART1_IFLOWCONTROL) .iflow = true, .rts_gpio = PIN_UART1_RTS, -#endif -#ifdef CONFIG_KINETIS_UART1_RXDMA +# endif +# ifdef CONFIG_KINETIS_UART1_RXDMA .rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART1_RX, .rxfifo = g_uart1rxfifo, -#endif +# endif }; static uart_dev_t g_uart1port = @@ -547,11 +547,11 @@ static uart_dev_t g_uart1port = .size = CONFIG_UART1_TXBUFSIZE, .buffer = g_uart1txbuffer, }, -#ifdef CONFIG_KINETIS_UART1_RXDMA +# ifdef CONFIG_KINETIS_UART1_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart1priv, }; #endif @@ -564,25 +564,25 @@ static struct up_dev_s g_uart2priv = .uartbase = KINETIS_UART2_BASE, .clock = BOARD_BUS_FREQ, .baud = CONFIG_UART2_BAUD, -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES .irqe = KINETIS_IRQ_UART2E, -#endif +# endif .irqs = KINETIS_IRQ_UART2S, .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, .stop2 = CONFIG_UART2_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART2_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART2_OFLOWCONTROL) .oflow = true, .cts_gpio = PIN_UART2_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART2_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART2_IFLOWCONTROL) .iflow = true, .rts_gpio = PIN_UART2_RTS, -#endif -#ifdef CONFIG_KINETIS_UART2_RXDMA +# endif +# ifdef CONFIG_KINETIS_UART2_RXDMA .rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART2_RX, .rxfifo = g_uart2rxfifo, -#endif +# endif }; static uart_dev_t g_uart2port = @@ -597,11 +597,11 @@ static uart_dev_t g_uart2port = .size = CONFIG_UART2_TXBUFSIZE, .buffer = g_uart2txbuffer, }, -#ifdef CONFIG_KINETIS_UART2_RXDMA +# ifdef CONFIG_KINETIS_UART2_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart2priv, }; #endif @@ -614,25 +614,25 @@ static struct up_dev_s g_uart3priv = .uartbase = KINETIS_UART3_BASE, .clock = BOARD_BUS_FREQ, .baud = CONFIG_UART3_BAUD, -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES .irqe = KINETIS_IRQ_UART3E, -#endif +# endif .irqs = KINETIS_IRQ_UART3S, .parity = CONFIG_UART3_PARITY, .bits = CONFIG_UART3_BITS, .stop2 = CONFIG_UART3_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART3_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART3_OFLOWCONTROL) .oflow = true, .cts_gpio = PIN_UART3_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART3_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART3_IFLOWCONTROL) .iflow = true, .rts_gpio = PIN_UART3_RTS, -#endif -#ifdef CONFIG_KINETIS_UART3_RXDMA +# endif +# ifdef CONFIG_KINETIS_UART3_RXDMA .rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART3_RX, .rxfifo = g_uart3rxfifo, -#endif +# endif }; static uart_dev_t g_uart3port = @@ -647,11 +647,11 @@ static uart_dev_t g_uart3port = .size = CONFIG_UART3_TXBUFSIZE, .buffer = g_uart3txbuffer, }, -#ifdef CONFIG_KINETIS_UART3_RXDMA +# ifdef CONFIG_KINETIS_UART3_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart3priv, }; #endif @@ -664,25 +664,25 @@ static struct up_dev_s g_uart4priv = .uartbase = KINETIS_UART4_BASE, .clock = BOARD_BUS_FREQ, .baud = CONFIG_UART4_BAUD, -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES .irqe = KINETIS_IRQ_UART4E, -#endif +# endif .irqs = KINETIS_IRQ_UART4S, .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stop2 = CONFIG_UART4_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL) .oflow = true, .cts_gpio = PIN_UART4_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL) .iflow = true, .rts_gpio = PIN_UART4_RTS, -#endif -#ifdef CONFIG_KINETIS_UART4_RXDMA +# endif +# ifdef CONFIG_KINETIS_UART4_RXDMA .rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART4_RXTX, .rxfifo = g_uart4rxfifo, -#endif +# endif }; static uart_dev_t g_uart4port = @@ -697,11 +697,11 @@ static uart_dev_t g_uart4port = .size = CONFIG_UART4_TXBUFSIZE, .buffer = g_uart4txbuffer, }, -#ifdef CONFIG_KINETIS_UART4_RXDMA +# ifdef CONFIG_KINETIS_UART4_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart4priv, }; #endif @@ -714,25 +714,25 @@ static struct up_dev_s g_uart5priv = .uartbase = KINETIS_UART5_BASE, .clock = BOARD_BUS_FREQ, .baud = CONFIG_UART5_BAUD, -#ifdef CONFIG_DEBUG_FEATURES +# ifdef CONFIG_DEBUG_FEATURES .irqe = KINETIS_IRQ_UART5E, -#endif +# endif .irqs = KINETIS_IRQ_UART5S, .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stop2 = CONFIG_UART5_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL) .oflow = true, .cts_gpio = PIN_UART5_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL) .iflow = true, .rts_gpio = PIN_UART5_RTS, -#endif -#ifdef CONFIG_KINETIS_UART5_RXDMA +# endif +# ifdef CONFIG_KINETIS_UART5_RXDMA .rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART5_RX, .rxfifo = g_uart5rxfifo, -#endif +# endif }; static uart_dev_t g_uart5port = @@ -747,11 +747,11 @@ static uart_dev_t g_uart5port = .size = CONFIG_UART5_TXBUFSIZE, .buffer = g_uart5txbuffer, }, -#ifdef CONFIG_KINETIS_UART5_RXDMA +# ifdef CONFIG_KINETIS_UART5_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart5priv, }; #endif diff --git a/arch/arm/src/kl/hardware/kl_memorymap.h b/arch/arm/src/kl/hardware/kl_memorymap.h index e5cbf5985c..afb5ba5aab 100644 --- a/arch/arm/src/kl/hardware/kl_memorymap.h +++ b/arch/arm/src/kl/hardware/kl_memorymap.h @@ -41,81 +41,81 @@ * K40P144M100SF2RM */ -# define KL_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read- +# define KL_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read- * only data (Includes exception * vectors in first 1024 bytes) */ -# define KL_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM +# define KL_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM * (ICODE/DCODE) */ -# define KL_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband +# define KL_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband * region */ /* 0x20100000 * -0x3fffffff Reserved */ -# define KIP_AIPS_BASE 0x40000000 /* -0x4007ffff AIPS Peripherals */ +# define KIP_AIPS_BASE 0x40000000 /* -0x4007ffff AIPS Peripherals */ /* 0x40080000 * -0x400fffff Reserved */ -# define KL_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) +# define KL_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) /* 0x40100000 * -0x43ffffff Reserved */ -# define KL_BME_BASE 0x44000000 /* -0x5fffffff Bit Manipulation Engine (BME) access +# define KL_BME_BASE 0x44000000 /* -0x5fffffff Bit Manipulation Engine (BME) access * to AIPS Peripherals for slots 0-127 */ /* 0x60000000 * -0xdfffffff Reserved */ -# define KL_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */ +# define KL_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */ /* 0xe0100000 * -0xefffffff Reserved */ -# define KL_MTB_BASE 0xf0000000 /* -0xffffffff Micro Trace Buffer (MTB) registers */ +# define KL_MTB_BASE 0xf0000000 /* -0xffffffff Micro Trace Buffer (MTB) registers */ /* AIPS Memory Map **********************************************************/ -# define KL_DMAC_BASE 0x40008000 /* DMA controller */ -# define KL_AIPSGPIO_BASE 0x4000f000 /* GPIO controller (aliased to 0x400ff000) */ -# define KL_FTFL_BASE 0x40020000 /* Flash memory */ -# define KL_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */ -# define KL_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ -# define KL_TPM0_BASE 0x40038000 /* Timer/PWM (TPM) 0 */ -# define KL_TPM1_BASE 0x40039000 /* Timer/PWM (TPM) 1 */ -# define KL_TPM2_BASE 0x4003a000 /* Timer/PWM (TPM) 2 */ -# define KL_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ -# define KL_RTC_BASE 0x4003d000 /* Real time clock */ -# define KL_DAC0_BASE 0x4003f000 /* Digital-to-analog convert (DAC) 0 */ -# define KL_LPTMR_BASE 0x40040000 /* Low power timer */ -# define KL_TSI_BASE 0x40045000 /* Touch sense interface */ -# define KL_SIMLP_BASE 0x40047000 /* SIM low-power logic */ -# define KL_SIM_BASE 0x40048000 /* System integration module (SIM) */ -# define KL_PORT_BASE(n) (0x40049000 + ((n) << 12)) -# define KL_PORTA_BASE 0x40049000 /* Port A multiplexing control */ -# define KL_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ -# define KL_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ -# define KL_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ -# define KL_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ -# define KL_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ -# define KL_OSC_BASE 0x40065000 /* System oscillator (OSC) */ -# define KL_I2C0_BASE 0x40066000 /* I2C 0 */ -# define KL_I2C1_BASE 0x40067000 /* I2C 1 */ -# define KL_UART0_BASE 0x4006a000 /* UART0 */ -# define KL_UART1_BASE 0x4006b000 /* UART1 */ -# define KL_UART2_BASE 0x4006c000 /* UART2 */ -# define KL_USB0_BASE 0x40072000 /* USB OTG FS/LS */ -# define KL_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ -# define KL_SPI0_BASE 0x40076000 /* SPI 0 */ -# define KL_SPI1_BASE 0x40077000 /* SPI 1 */ -# define KL_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ -# define KL_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ -# define KL_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ -# define KL_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */ +# define KL_DMAC_BASE 0x40008000 /* DMA controller */ +# define KL_AIPSGPIO_BASE 0x4000f000 /* GPIO controller (aliased to 0x400ff000) */ +# define KL_FTFL_BASE 0x40020000 /* Flash memory */ +# define KL_DMAMUX0_BASE 0x40021000 /* DMA channel multiplexer 0 */ +# define KL_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ +# define KL_TPM0_BASE 0x40038000 /* Timer/PWM (TPM) 0 */ +# define KL_TPM1_BASE 0x40039000 /* Timer/PWM (TPM) 1 */ +# define KL_TPM2_BASE 0x4003a000 /* Timer/PWM (TPM) 2 */ +# define KL_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ +# define KL_RTC_BASE 0x4003d000 /* Real time clock */ +# define KL_DAC0_BASE 0x4003f000 /* Digital-to-analog convert (DAC) 0 */ +# define KL_LPTMR_BASE 0x40040000 /* Low power timer */ +# define KL_TSI_BASE 0x40045000 /* Touch sense interface */ +# define KL_SIMLP_BASE 0x40047000 /* SIM low-power logic */ +# define KL_SIM_BASE 0x40048000 /* System integration module (SIM) */ +# define KL_PORT_BASE(n) (0x40049000 + ((n) << 12)) +# define KL_PORTA_BASE 0x40049000 /* Port A multiplexing control */ +# define KL_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ +# define KL_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ +# define KL_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ +# define KL_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ +# define KL_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ +# define KL_OSC_BASE 0x40065000 /* System oscillator (OSC) */ +# define KL_I2C0_BASE 0x40066000 /* I2C 0 */ +# define KL_I2C1_BASE 0x40067000 /* I2C 1 */ +# define KL_UART0_BASE 0x4006a000 /* UART0 */ +# define KL_UART1_BASE 0x4006b000 /* UART1 */ +# define KL_UART2_BASE 0x4006c000 /* UART2 */ +# define KL_USB0_BASE 0x40072000 /* USB OTG FS/LS */ +# define KL_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ +# define KL_SPI0_BASE 0x40076000 /* SPI 0 */ +# define KL_SPI1_BASE 0x40077000 /* SPI 1 */ +# define KL_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ +# define KL_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ +# define KL_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ +# define KL_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */ /* 0x400ff000 * GPIO Controller */ -# define KL_GPIOn_BASE(n) (0x400ff000 + ((n) << 6)) -# define KL_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ -# define KL_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ -# define KL_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ -# define KL_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ -# define KL_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ +# define KL_GPIOn_BASE(n) (0x400ff000 + ((n) << 6)) +# define KL_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ +# define KL_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ +# define KL_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ +# define KL_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ +# define KL_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ /* Private Peripheral Bus (PPB) Memory Map **********************************/ -# define KL_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ -# define KL_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ +# define KL_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ +# define KL_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ /**************************************************************************** * Public Types diff --git a/arch/arm/src/kl/hardware/kl_tpm.h b/arch/arm/src/kl/hardware/kl_tpm.h index 545875e59f..aeedcf2b32 100644 --- a/arch/arm/src/kl/hardware/kl_tpm.h +++ b/arch/arm/src/kl/hardware/kl_tpm.h @@ -114,22 +114,22 @@ #define TPM_SC_PS_SHIFT 0 /* Bits 0-2: Prescale Factor Selection */ #define TPM_SC_PS_MASK (7 << TPM_SC_PS_SHIFT) -# define TPM_SC_PS_DIV1 (0 << TPM_SC_PS_SHIFT) /* Divide Clock by 1 */ -# define TPM_SC_PS_DIV2 (1 << TPM_SC_PS_SHIFT) /* Divide Clock by 2 */ -# define TPM_SC_PS_DIV4 (2 << TPM_SC_PS_SHIFT) /* Divide Clock by 4 */ -# define TPM_SC_PS_DIV8 (3 << TPM_SC_PS_SHIFT) /* Divide Clock by 8 */ -# define TPM_SC_PS_DIV16 (4 << TPM_SC_PS_SHIFT) /* Divide Clock by 16 */ -# define TPM_SC_PS_DIV32 (5 << TPM_SC_PS_SHIFT) /* Divide Clock by 32 */ -# define TPM_SC_PS_DIV64 (6 << TPM_SC_PS_SHIFT) /* Divide Clock by 64 */ -# define TPM_SC_PS_DIV128 (7 << TPM_SC_PS_SHIFT) /* Divide Clock by 128 */ +# define TPM_SC_PS_DIV1 (0 << TPM_SC_PS_SHIFT) /* Divide Clock by 1 */ +# define TPM_SC_PS_DIV2 (1 << TPM_SC_PS_SHIFT) /* Divide Clock by 2 */ +# define TPM_SC_PS_DIV4 (2 << TPM_SC_PS_SHIFT) /* Divide Clock by 4 */ +# define TPM_SC_PS_DIV8 (3 << TPM_SC_PS_SHIFT) /* Divide Clock by 8 */ +# define TPM_SC_PS_DIV16 (4 << TPM_SC_PS_SHIFT) /* Divide Clock by 16 */ +# define TPM_SC_PS_DIV32 (5 << TPM_SC_PS_SHIFT) /* Divide Clock by 32 */ +# define TPM_SC_PS_DIV64 (6 << TPM_SC_PS_SHIFT) /* Divide Clock by 64 */ +# define TPM_SC_PS_DIV128 (7 << TPM_SC_PS_SHIFT) /* Divide Clock by 128 */ #define TPM_SC_CMOD_SHIFT 3 /* Bits 3-4: Clock Mode Selection */ -#define TPM_SC_CMOD_MASK (3 << TPM_SC_CMOD_SHIFT) -# define TPM_SC_CMOD_DIS (0 << TPM_SC_CMOD_SHIFT) /* TPM counter is disabled */ -# define TPM_SC_CMOD_LPTPM_CLK (1 << TPM_SC_CMOD_SHIFT) /* TPM increments on every counter clock */ -# define TPM_SC_CMOD_LPTPM_EXTCLK (2 << TPM_SC_CMOD_SHIFT) /* TPM increments on rising edge of EXTCLK */ -# define TPM_SC_CMOD_RESERV (3 << TPM_SC_CMOD_SHIFT) /* Reserved */ +#define TPM_SC_CMOD_MASK (3 << TPM_SC_CMOD_SHIFT) +# define TPM_SC_CMOD_DIS (0 << TPM_SC_CMOD_SHIFT) /* TPM counter is disabled */ +# define TPM_SC_CMOD_LPTPM_CLK (1 << TPM_SC_CMOD_SHIFT) /* TPM increments on every counter clock */ +# define TPM_SC_CMOD_LPTPM_EXTCLK (2 << TPM_SC_CMOD_SHIFT) /* TPM increments on rising edge of EXTCLK */ +# define TPM_SC_CMOD_RESERV (3 << TPM_SC_CMOD_SHIFT) /* Reserved */ #define TPM_SC_CPWMS (1 << 5) /* Bit 5: Center-aligned PWM Select */ #define TPM_SC_TOIE (1 << 6) /* Bit 6: Timer Overflow Interrupt Enable */ @@ -158,8 +158,8 @@ #define TPM_CONF_DOZEEN 5 /* Bit 5: Doze Enable */ #define TPM_CONF_DBGMODE_SHIFT 6 /* Bits 6-7: Debug Mode */ #define TPM_CONF_DBGMODE_MASK (3 << TPM_DBGMODE_SHIFT) -# define TPM_CONF_DBGMODE_PAUSE (0 << TPM_DBGMODE_SHIFT) /* TPM counter will pause during DEBUG mode */ -# define TPM_CONF_DBGMODE_CONT (3 << TPM_DBGMODE_SHIFT) /* TPM counter continue working in DEBUG mode */ +# define TPM_CONF_DBGMODE_PAUSE (0 << TPM_DBGMODE_SHIFT) /* TPM counter will pause during DEBUG mode */ +# define TPM_CONF_DBGMODE_CONT (3 << TPM_DBGMODE_SHIFT) /* TPM counter continue working in DEBUG mode */ /* Bit 8: Reserved */ #define TPM_CONF_GTBEEN (1 << 9) /* Bit 9: Global Time Base Enable */ @@ -168,31 +168,31 @@ #define TPM_CONF_CSOO (1 << 17) /* Bit 17: Counter Stop On Overflow */ #define TPM_CONF_CROT (1 << 18) /* Bit 18: Counter Reload On Trigger */ /* Bits 19-23: Reserved */ -#define TPM_CONF_TRGSEL_SHIFT 24 -#define TPM_CONF_TRGSEL_MASK (15 << TPM_CONF_TRGSEL_SHIFT) -# define TPM_CONF_TRGSEL_EXTRG_IN (0 << TPM_CONF_TRGSEL_SHIFT) /* External trigger pin input */ -# define TPM_CONF_TRGSEL_CMP0 (1 << TPM_CONF_TRGSEL_SHIFT) /* CPM0 output */ +#define TPM_CONF_TRGSEL_SHIFT 24 +#define TPM_CONF_TRGSEL_MASK (15 << TPM_CONF_TRGSEL_SHIFT) +# define TPM_CONF_TRGSEL_EXTRG_IN (0 << TPM_CONF_TRGSEL_SHIFT) /* External trigger pin input */ +# define TPM_CONF_TRGSEL_CMP0 (1 << TPM_CONF_TRGSEL_SHIFT) /* CPM0 output */ /* (2 << TPM_CONF_TRGSEL_SHIFT) Reserved */ /* (3 << TPM_CONF_TRGSEL_SHIFT) Reserved */ -# define TPM_CONF_TRGSEL_PIT0 (4 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 0 */ -# define TPM_CONF_TRGSEL_PIT1 (5 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 1 */ +# define TPM_CONF_TRGSEL_PIT0 (4 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 0 */ +# define TPM_CONF_TRGSEL_PIT1 (5 << TPM_CONF_TRGSEL_SHIFT) /* PIT trigger 1 */ /* (6 << TPM_CONF_TRGSEL_SHIFT) Reserved */ /* (7 << TPM_CONF_TRGSEL_SHIFT) Reserved */ -# define TPM_CONF_TRGSEL_TPM0 (8 << TPM_CONF_TRGSEL_SHIFT) /* TPM0 Overflow */ -# define TPM_CONF_TRGSEL_TPM1 (9 << TPM_CONF_TRGSEL_SHIFT) /* TPM1 Overflow */ -# define TPM_CONF_TRGSEL_TPM2 (10 << TPM_CONF_TRGSEL_SHIFT) /* TPM1 Overflow */ +# define TPM_CONF_TRGSEL_TPM0 (8 << TPM_CONF_TRGSEL_SHIFT) /* TPM0 Overflow */ +# define TPM_CONF_TRGSEL_TPM1 (9 << TPM_CONF_TRGSEL_SHIFT) /* TPM1 Overflow */ +# define TPM_CONF_TRGSEL_TPM2 (10 << TPM_CONF_TRGSEL_SHIFT) /* TPM1 Overflow */ /* (11 << TPM_CONF_TRGSEL_SHIFT) Reserved */ -# define TPM_CONF_TRGSEL_RTC_ALRM (12 << TPM_CONF_TRGSEL_SHIFT) /* RTC Alarm */ -# define TPM_CONF_TRGSEL_RTC_SECS (13 << TPM_CONF_TRGSEL_SHIFT) /* RTC Seconds */ -# define TPM_CONF_TRGSEL_LPTMR (14 << TPM_CONF_TRGSEL_SHIFT) /* LPTMR trigger */ +# define TPM_CONF_TRGSEL_RTC_ALRM (12 << TPM_CONF_TRGSEL_SHIFT) /* RTC Alarm */ +# define TPM_CONF_TRGSEL_RTC_SECS (13 << TPM_CONF_TRGSEL_SHIFT) /* RTC Seconds */ +# define TPM_CONF_TRGSEL_LPTMR (14 << TPM_CONF_TRGSEL_SHIFT) /* LPTMR trigger */ /* (15 << TPM_CONF_TRGSEL_SHIFT) Reserved */ diff --git a/arch/arm/src/lc823450/lc823450_syscontrol.h b/arch/arm/src/lc823450/lc823450_syscontrol.h index 0924e4c59c..30cc8cf6ef 100644 --- a/arch/arm/src/lc823450/lc823450_syscontrol.h +++ b/arch/arm/src/lc823450/lc823450_syscontrol.h @@ -277,8 +277,8 @@ void lc823450_clock_dump(void); void mod_stby_regs(uint32_t clearbits, uint32_t setbits); void lc823450_mod_stby_regs(uint32_t clearbits, uint32_t setbits); #else -# define mod_stby_regs(...) -# define lc823450_mod_stby_regs(...) +# define mod_stby_regs(...) +# define lc823450_mod_stby_regs(...) #endif #if defined(__cplusplus) diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_memorymap.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_memorymap.h index d71cd46a2a..024c6b7c88 100644 --- a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_memorymap.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_memorymap.h @@ -50,15 +50,15 @@ /* Off chip Memory via External Memory Interface */ #define LPC17_40_EXTRAM_BASE 0x80000000 /* */ -# define LPC17_40_EXTSRAM_CS0 0x80000000 /* Chip select 0 /up to 64MB/ */ -# define LPC17_40_EXTSRAM_CS1 0x90000000 /* Chip select 1 /up to 64MB/ */ -# define LPC17_40_EXTSRAM_CS2 0x98000000 /* Chip select 2 /up to 64MB/ */ -# define LPC17_40_EXTSRAM_CS3 0x9c000000 /* Chip select 3 /up to 64MB/ */ +# define LPC17_40_EXTSRAM_CS0 0x80000000 /* Chip select 0 /up to 64MB/ */ +# define LPC17_40_EXTSRAM_CS1 0x90000000 /* Chip select 1 /up to 64MB/ */ +# define LPC17_40_EXTSRAM_CS2 0x98000000 /* Chip select 2 /up to 64MB/ */ +# define LPC17_40_EXTSRAM_CS3 0x9c000000 /* Chip select 3 /up to 64MB/ */ -# define LPC17_40_EXTDRAM_CS0 0xa0000000 /* Chip select 0 /up to 256MB/ */ -# define LPC17_40_EXTDRAM_CS1 0xb0000000 /* Chip select 1 /up to 256MB/ */ -# define LPC17_40_EXTDRAM_CS2 0xc0000000 /* Chip select 2 /up to 256MB/ */ -# define LPC17_40_EXTDRAM_CS3 0xd0000000 /* Chip select 3 /up to 256MB/ */ +# define LPC17_40_EXTDRAM_CS0 0xa0000000 /* Chip select 0 /up to 256MB/ */ +# define LPC17_40_EXTDRAM_CS1 0xb0000000 /* Chip select 1 /up to 256MB/ */ +# define LPC17_40_EXTDRAM_CS2 0xc0000000 /* Chip select 2 /up to 256MB/ */ +# define LPC17_40_EXTDRAM_CS3 0xd0000000 /* Chip select 3 /up to 256MB/ */ #define LPC17_40_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */ #define LPC17_40_SCS_BASE 0xe000e000 diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h index d47497636a..55f846db87 100644 --- a/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc178x_40xx_syscon.h @@ -373,7 +373,7 @@ #define SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT (0) /* Bits 0-4: divide value for SPIFI clock */ #define SYSCON_SPIFICLKSEL_SPIFIDIV_MASK (0x1f << SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT) -# define SYSCON_SPIFICLKSEL_SPIFIDIV(n) ((n-1) << SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT) /* n = 2 - 31 */ +# define SYSCON_SPIFICLKSEL_SPIFIDIV(n) ((n-1) << SYSCON_SPIFICLKSEL_SPIFIDIV_SHIFT) /* n = 2 - 31 */ /* Bits 5-7: Reserved */ #define SYSCON_SPIFICLKSEL_SPIFISEL_SHIFT (8) /* Bits 8-9: Selects input clock for SPIFI clock divider */ @@ -509,10 +509,10 @@ /* System control registers -- Matrix Arbitration Priorities */ -# define SYSCON_MATRIXARB_PRI_LOWEST (0) -# define SYSCON_MATRIXARB_PRI_LOW (1) -# define SYSCON_MATRIXARB_PRI_HIGH (2) -# define SYSCON_MATRIXARB_PRI_HIGHEST (3) +# define SYSCON_MATRIXARB_PRI_LOWEST (0) +# define SYSCON_MATRIXARB_PRI_LOW (1) +# define SYSCON_MATRIXARB_PRI_HIGH (2) +# define SYSCON_MATRIXARB_PRI_HIGHEST (3) #define SYSCON_MATRIXARB_PRI_ICODE_SHIFT (0) /* Bits 0-1: I-Code bus priority (should be lower than D-Code) */ #define SYSCON_MATRIXARB_PRI_ICODE_MASK (3 << SYSCON_MATRIXARB_PRI_ICODE_SHIFT) @@ -642,7 +642,7 @@ /* Delay values multiplied by 250 picoseconds */ #define SYSCON_EMCDLYCTL_CMDDLY_SHIFT (0) /* Bits 0-4: Delay value for EMC outputs in command delayed mode */ #define SYSCON_EMCDLYCTL_CMDDLY_MASK (0x1f << SYSCON_EMCDLYCTL_CMDDLY_SHIFT) -# define SYSCON_EMCDLYCTL_CMDDLY(n) ((n-1) << SYSCON_EMCDLYCTL_CMDDLY_SHIFT) /* n = 3 - 32 */ +# define SYSCON_EMCDLYCTL_CMDDLY(n) ((n-1) << SYSCON_EMCDLYCTL_CMDDLY_SHIFT) /* n = 3 - 32 */ /* Bits 5-7: Reserved */ #define SYSCON_EMCDLYCTL_FBCLKDLY_SHIFT (8) /* Bits 8-12: Delay value for the feedback clock that controls input data sampling */ @@ -652,12 +652,12 @@ /* Bits 13-15: Reserved */ #define SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT (16) /* Bits 16-20: Delay value for the CLKOUT0 output */ #define SYSCON_EMCDLYCTL_CLKOUT0DLY_MASK (0x1f << SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT) -# define SYSCON_EMCDLYCTL_CLKOUT0DLY(n) ((n-1) << SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT) /* n = 3 - 32 */ +# define SYSCON_EMCDLYCTL_CLKOUT0DLY(n) ((n-1) << SYSCON_EMCDLYCTL_CLKOUT0DLY_SHIFT) /* n = 3 - 32 */ /* Bits 21-23: Reserved */ #define SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT (24) /* Bits 24-28: Delay value for the CLKOUT1 output */ #define SYSCON_EMCDLYCTL_CLKOUT1DLY_MASK (0x1f << SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT) -# define SYSCON_EMCDLYCTL_CLKOUT1DLY(n) ((n-1) << SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT) /* n = 3 - 32 */ +# define SYSCON_EMCDLYCTL_CLKOUT1DLY(n) ((n-1) << SYSCON_EMCDLYCTL_CLKOUT1DLY_SHIFT) /* n = 3 - 32 */ /* Bits 29-31: Reserved */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_can.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_can.h index 2971bb2b0c..4ec2bcc3b1 100644 --- a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_can.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_can.h @@ -321,28 +321,28 @@ /* Bits 11-15: Reserved */ #define CAN_ICR_ERRBIT_SHIFT (16) /* Bits 16-20: Error Code Capture */ #define CAN_ICR_ERRBIT_MASK (0x1f << CAN_ICR_ERRBIT_SHIFT) -# define CAN_ICR_ERRBIT_SOF (3 << CAN_ICR_ERRBIT_SHIFT) /* Start of Frame */ -# define CAN_ICR_ERRBIT_ID28 (2 << CAN_ICR_ERRBIT_SHIFT) /* ID28 ... ID21 */ -# define CAN_ICR_ERRBIT_SRTR (4 << CAN_ICR_ERRBIT_SHIFT) /* SRTR Bit */ -# define CAN_ICR_ERRBIT_IDE (5 << CAN_ICR_ERRBIT_SHIFT) /* DE bit */ -# define CAN_ICR_ERRBIT_ID20 (6 << CAN_ICR_ERRBIT_SHIFT) /* ID20 ... ID18 */ -# define CAN_ICR_ERRBIT_ID17 (7 << CAN_ICR_ERRBIT_SHIFT) /* ID17 ... 13 */ -# define CAN_ICR_ERRBIT_CRC (8 << CAN_ICR_ERRBIT_SHIFT) /* CRC Sequence */ -# define CAN_ICR_ERRBIT_DATA (10 << CAN_ICR_ERRBIT_SHIFT) /* Data Field */ -# define CAN_ICR_ERRBIT_LEN (11 << CAN_ICR_ERRBIT_SHIFT) /* Data Length Code */ -# define CAN_ICR_ERRBIT_ RTR (12 << CAN_ICR_ERRBIT_SHIFT) /* RTR Bit */ -# define CAN_ICR_ERRBIT_ID4 (14 << CAN_ICR_ERRBIT_SHIFT) /* ID4 ... ID0 */ -# define CAN_ICR_ERRBIT_ID12 (15 << CAN_ICR_ERRBIT_SHIFT) /* ID12 ... ID5 */ -# define CAN_ICR_ERRBIT_AERR (17 << CAN_ICR_ERRBIT_SHIFT) /* Active Error Flag */ -# define CAN_ICR_ERRBIT_INTERMSN (18 << CAN_ICR_ERRBIT_SHIFT) /* Intermission */ -# define CAN_ICR_ERRBIT_DOM (19 << CAN_ICR_ERRBIT_SHIFT) /* Tolerate Dominant Bits */ -# define CAN_ICR_ERRBIT_PERR (22 << CAN_ICR_ERRBIT_SHIFT) /* Passive Error Flag */ -# define CAN_ICR_ERRBIT_ERRDLM (23 << CAN_ICR_ERRBIT_SHIFT) /* Error Delimiter */ -# define CAN_ICR_ERRBIT_CRCDLM (24 << CAN_ICR_ERRBIT_SHIFT) /* CRC Delimiter */ -# define CAN_ICR_ERRBIT_ACKSLT (25 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Slot */ -# define CAN_ICR_ERRBIT_EOF (26 << CAN_ICR_ERRBIT_SHIFT) /* End of Frame */ -# define CAN_ICR_ERRBIT_ACKDLM (27 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Delimiter */ -# define CAN_ICR_ERRBIT_OVLD (28 << CAN_ICR_ERRBIT_SHIFT) /* Overload flag */ +# define CAN_ICR_ERRBIT_SOF (3 << CAN_ICR_ERRBIT_SHIFT) /* Start of Frame */ +# define CAN_ICR_ERRBIT_ID28 (2 << CAN_ICR_ERRBIT_SHIFT) /* ID28 ... ID21 */ +# define CAN_ICR_ERRBIT_SRTR (4 << CAN_ICR_ERRBIT_SHIFT) /* SRTR Bit */ +# define CAN_ICR_ERRBIT_IDE (5 << CAN_ICR_ERRBIT_SHIFT) /* DE bit */ +# define CAN_ICR_ERRBIT_ID20 (6 << CAN_ICR_ERRBIT_SHIFT) /* ID20 ... ID18 */ +# define CAN_ICR_ERRBIT_ID17 (7 << CAN_ICR_ERRBIT_SHIFT) /* ID17 ... 13 */ +# define CAN_ICR_ERRBIT_CRC (8 << CAN_ICR_ERRBIT_SHIFT) /* CRC Sequence */ +# define CAN_ICR_ERRBIT_DATA (10 << CAN_ICR_ERRBIT_SHIFT) /* Data Field */ +# define CAN_ICR_ERRBIT_LEN (11 << CAN_ICR_ERRBIT_SHIFT) /* Data Length Code */ +# define CAN_ICR_ERRBIT_ RTR (12 << CAN_ICR_ERRBIT_SHIFT) /* RTR Bit */ +# define CAN_ICR_ERRBIT_ID4 (14 << CAN_ICR_ERRBIT_SHIFT) /* ID4 ... ID0 */ +# define CAN_ICR_ERRBIT_ID12 (15 << CAN_ICR_ERRBIT_SHIFT) /* ID12 ... ID5 */ +# define CAN_ICR_ERRBIT_AERR (17 << CAN_ICR_ERRBIT_SHIFT) /* Active Error Flag */ +# define CAN_ICR_ERRBIT_INTERMSN (18 << CAN_ICR_ERRBIT_SHIFT) /* Intermission */ +# define CAN_ICR_ERRBIT_DOM (19 << CAN_ICR_ERRBIT_SHIFT) /* Tolerate Dominant Bits */ +# define CAN_ICR_ERRBIT_PERR (22 << CAN_ICR_ERRBIT_SHIFT) /* Passive Error Flag */ +# define CAN_ICR_ERRBIT_ERRDLM (23 << CAN_ICR_ERRBIT_SHIFT) /* Error Delimiter */ +# define CAN_ICR_ERRBIT_CRCDLM (24 << CAN_ICR_ERRBIT_SHIFT) /* CRC Delimiter */ +# define CAN_ICR_ERRBIT_ACKSLT (25 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Slot */ +# define CAN_ICR_ERRBIT_EOF (26 << CAN_ICR_ERRBIT_SHIFT) /* End of Frame */ +# define CAN_ICR_ERRBIT_ACKDLM (27 << CAN_ICR_ERRBIT_SHIFT) /* Acknowledge Delimiter */ +# define CAN_ICR_ERRBIT_OVLD (28 << CAN_ICR_ERRBIT_SHIFT) /* Overload flag */ #define CAN_ICR_ERRDIR (1 << 21) /* Bit 21: Direction bit at time of error */ #define CAN_ICR_ERRC_SHIFT (22) /* Bits 22-23: Type of error */ diff --git a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_wdt.h b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_wdt.h index 1e2d2eda58..6e4880f61d 100644 --- a/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_wdt.h +++ b/arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_wdt.h @@ -121,14 +121,14 @@ /* Watchdog timer warning interrupt register */ #ifdef LPC178x_40xx -# define WDT_WARNINT (0x3ff) /* Bits 0-9: Warning Interrupt compare value */ +# define WDT_WARNINT (0x3ff) /* Bits 0-9: Warning Interrupt compare value */ /* Bits 10-31: Reserved */ #endif /* Watchdog timer value register */ #ifdef LPC178x_40xx -# define WDT_WINDOW (0xffffff) /* Bits 0-23: Watchdog window value */ +# define WDT_WINDOW (0xffffff) /* Bits 0-23: Watchdog window value */ /* Bits 24-31: Reserved */ #endif diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_can.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_can.c index 2560446b3c..f10380548c 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_can.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_can.c @@ -51,11 +51,11 @@ #include #if defined(CONFIG_CAN) -# define CHRDEV_CAN +# define CHRDEV_CAN #endif #if defined(CONFIG_NET_CAN) -# define SOCKET_CAN +# define SOCKET_CAN #endif #include @@ -343,13 +343,13 @@ static struct up_dev_s g_can1priv = .baud = CONFIG_LPC17_40_CAN1_BAUD, .base = LPC17_40_CAN1_BASE, }; -# if defined(CHRDEV_CAN) +# if defined(CHRDEV_CAN) static struct lpc17_40_can_s g_can1dev = { .cd_ops = &g_canops, .cd_priv = &g_can1priv, }; -# endif +# endif #endif #ifdef CONFIG_LPC17_40_CAN2 @@ -360,13 +360,13 @@ static struct up_dev_s g_can2priv = .baud = CONFIG_LPC17_40_CAN2_BAUD, .base = LPC17_40_CAN2_BASE, }; -# if defined(CHRDEV_CAN) +# if defined(CHRDEV_CAN) static struct lpc17_40_can_s g_can2dev = { .cd_ops = &g_canops, .cd_priv = &g_can2priv, }; -# endif +# endif #endif #if defined(SOCKET_CAN) diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c index c8b02b70e2..4a8a1e7fa8 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_ethernet.c @@ -340,8 +340,8 @@ static void lpc17_40_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t lpc17_40_getreg(uint32_t addr); static void lpc17_40_putreg(uint32_t val, uint32_t addr); #else -# define lpc17_40_getreg(addr) getreg32(addr) -# define lpc17_40_putreg(val,addr) putreg32(val,addr) +# define lpc17_40_getreg(addr) getreg32(addr) +# define lpc17_40_putreg(val,addr) putreg32(val,addr) #endif /* Common TX logic */ @@ -1264,11 +1264,11 @@ static int lpc17_40_interrupt(int irq, void *context, void *arg) /* Clear the pending interrupt */ #if 0 /* Apparently not necessary */ -# if CONFIG_LPC17_40_NINTERFACES > 1 +# if CONFIG_LPC17_40_NINTERFACES > 1 lpc17_40_clrpend(priv->irq); -# else +# else lpc17_40_clrpend(LPC17_40_IRQ_ETH); -# endif +# endif #endif return OK; diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c index 0845109bb7..a706c7315e 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_lowputc.c @@ -142,7 +142,7 @@ #ifdef LPC178x_40xx /* Use the global PCLK frequency */ -# define CONSOLE_NUMERATOR BOARD_PCLK_FREQUENCY +# define CONSOLE_NUMERATOR BOARD_PCLK_FREQUENCY #else # ifdef CONFIG_LPC17_40_UART_USE_FRACTIONAL_DIVIDER diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c index ba5c05b103..a6ef0f546d 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c @@ -365,8 +365,8 @@ static void lpc17_40_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t lpc17_40_getreg(uint32_t addr); static void lpc17_40_putreg(uint32_t val, uint32_t addr); #else -# define lpc17_40_getreg(addr) getreg32(addr) -# define lpc17_40_putreg(val,addr) putreg32(val,addr) +# define lpc17_40_getreg(addr) getreg32(addr) +# define lpc17_40_putreg(val,addr) putreg32(val,addr) #endif /* Command operations *******************************************************/ diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c index 26cfc4555d..c8e1b17dbb 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c @@ -269,8 +269,8 @@ static void lpc17_40_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t lpc17_40_getreg(uint32_t addr); static void lpc17_40_putreg(uint32_t val, uint32_t addr); #else -# define lpc17_40_getreg(addr) getreg32(addr) -# define lpc17_40_putreg(val,addr) putreg32(val,addr) +# define lpc17_40_getreg(addr) getreg32(addr) +# define lpc17_40_putreg(val,addr) putreg32(val,addr) #endif /* Semaphores ***************************************************************/ diff --git a/arch/arm/src/lpc214x/lpc214x_usbdev.c b/arch/arm/src/lpc214x/lpc214x_usbdev.c index 0a2ba73c86..0a8ce69a92 100644 --- a/arch/arm/src/lpc214x/lpc214x_usbdev.c +++ b/arch/arm/src/lpc214x/lpc214x_usbdev.c @@ -371,8 +371,8 @@ struct lpc214x_usbdev_s static uint32_t lpc214x_getreg(uint32_t addr); static void lpc214x_putreg(uint32_t val, uint32_t addr); #else -# define lpc214x_getreg(addr) getreg32(addr) -# define lpc214x_putreg(val,addr) putreg32(val,addr) +# define lpc214x_getreg(addr) getreg32(addr) +# define lpc214x_putreg(val,addr) putreg32(val,addr) #endif /* Command operations *******************************************************/ diff --git a/arch/arm/src/lpc2378/lpc23xx_uart.h b/arch/arm/src/lpc2378/lpc23xx_uart.h index 976317a0a2..d11fae561e 100644 --- a/arch/arm/src/lpc2378/lpc23xx_uart.h +++ b/arch/arm/src/lpc2378/lpc23xx_uart.h @@ -91,26 +91,26 @@ /* PCKLSEL0 bits 7:6, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */ #ifdef U0_PCLKDIV -# if U0_PCLKDIV == 1 -# define U0_PCLKSEL (0x00000040) -# elif U0_PCLKDIV == 2 -# define U0_PCLKSEL (0x00000080) -# elif U0_PCLKDIV == 4 -# define U0_PCLKSEL (0x00000000) -# endif +# if U0_PCLKDIV == 1 +# define U0_PCLKSEL (0x00000040) +# elif U0_PCLKDIV == 2 +# define U0_PCLKSEL (0x00000080) +# elif U0_PCLKDIV == 4 +# define U0_PCLKSEL (0x00000000) +# endif #else # error "UART0 PCLK divider not set" #endif /* PCKLSEL1 bits 17:16, 00=CCLK/4, 01=CCLK/1 , 10=CCLK/2 */ #ifdef U2_PCLKDIV -# if U2_PCLKDIV == 1 -# define U2_PCLKSEL (0x00010000) -# elif U2_PCLKDIV == 2 -# define U2_PCLKSEL (0x00020000) -# elif U2_PCLKDIV == 4 -# define U2_PCLKSEL (0x00000000) -# endif +# if U2_PCLKDIV == 1 +# define U2_PCLKSEL (0x00010000) +# elif U2_PCLKDIV == 2 +# define U2_PCLKSEL (0x00020000) +# elif U2_PCLKDIV == 4 +# define U2_PCLKSEL (0x00000000) +# endif #else # error "UART2 PCLK divider not set" #endif diff --git a/arch/arm/src/lpc31xx/lpc31_memorymap.h b/arch/arm/src/lpc31xx/lpc31_memorymap.h index 3fe86c3293..53c95c5f02 100644 --- a/arch/arm/src/lpc31xx/lpc31_memorymap.h +++ b/arch/arm/src/lpc31xx/lpc31_memorymap.h @@ -199,7 +199,7 @@ */ #ifndef CONFIG_ARCH_ROMPGTABLE -# define LPC31_FIRST_VSECTION 0x00000000 /* Beginning of the virtual address space */ +# define LPC31_FIRST_VSECTION 0x00000000 /* Beginning of the virtual address space */ # define LPC31_SHADOWSPACE_VSECTION 0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */ # define LPC31_INTSRAM_VSECTION 0x11028000 /* Internal SRAM 96Kb-192Kb */ # define LPC31_INTSRAM0_VADDR 0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */ diff --git a/arch/arm/src/lpc31xx/lpc31_usbdev.c b/arch/arm/src/lpc31xx/lpc31_usbdev.c index 7667339166..08c39a3c96 100644 --- a/arch/arm/src/lpc31xx/lpc31_usbdev.c +++ b/arch/arm/src/lpc31xx/lpc31_usbdev.c @@ -340,8 +340,8 @@ struct lpc31_usbdev_s static uint32_t lpc31_getreg(uint32_t addr); static void lpc31_putreg(uint32_t val, uint32_t addr); #else -# define lpc31_getreg(addr) getreg32(addr) -# define lpc31_putreg(val,addr) putreg32(val,addr) +# define lpc31_getreg(addr) getreg32(addr) +# define lpc31_putreg(val,addr) putreg32(val,addr) #endif static inline void lpc31_clrbits(uint32_t mask, uint32_t addr); diff --git a/arch/arm/src/lpc43xx/hardware/lpc43_gpdma.h b/arch/arm/src/lpc43xx/hardware/lpc43_gpdma.h index 622d9e83bf..bba75f9eaa 100644 --- a/arch/arm/src/lpc43xx/hardware/lpc43_gpdma.h +++ b/arch/arm/src/lpc43xx/hardware/lpc43_gpdma.h @@ -318,13 +318,13 @@ #define GPDMA_CONTROL_S_SHIFT (24) /* Bit 24: Source AHB master select */ -# define GPDMA_CONTROL_S0 (0 << GPDMA_CONTROL_S_SHIFT) /* AHB Master 0 selected for source transfer. */ -# define GPDMA_CONTROL_S1 (1 << GPDMA_CONTROL_S_SHIFT) /* AHB Master 1 selected for source transfer. */ +# define GPDMA_CONTROL_S0 (0 << GPDMA_CONTROL_S_SHIFT) /* AHB Master 0 selected for source transfer. */ +# define GPDMA_CONTROL_S1 (1 << GPDMA_CONTROL_S_SHIFT) /* AHB Master 1 selected for source transfer. */ #define GPDMA_CONTROL_D_SHIFT (25) /* Bit 25: Destination AHB master select */ -# define GPDMA_CONTROL_D0 (0 << GPDMA_CONTROL_D_SHIFT) /* AHB Master 0 selected for destination transfer. */ -# define GPDMA_CONTROL_D1 (1 << GPDMA_CONTROL_D_SHIFT) /* AHB Master 1 selected for destination transfer. */ +# define GPDMA_CONTROL_D0 (0 << GPDMA_CONTROL_D_SHIFT) /* AHB Master 0 selected for destination transfer. */ +# define GPDMA_CONTROL_D1 (1 << GPDMA_CONTROL_D_SHIFT) /* AHB Master 1 selected for destination transfer. */ #define GPDMA_CONTROL_SI (1 << 26) /* Bit 26: Source increment */ #define GPDMA_CONTROL_DI (1 << 27) /* Bit 27: Destination increment */ diff --git a/arch/arm/src/lpc43xx/hardware/lpc43_sct.h b/arch/arm/src/lpc43xx/hardware/lpc43_sct.h index d8ed2abc6d..63319b6138 100644 --- a/arch/arm/src/lpc43xx/hardware/lpc43_sct.h +++ b/arch/arm/src/lpc43xx/hardware/lpc43_sct.h @@ -1081,22 +1081,22 @@ #define SCT_CONFIG_CLKSEL_SHIFT (3) /* Bits 3-6: SCT clock select */ #define SCT_CONFIG_CLKSEL_MASK (15 << SCT_CONFIG_CLKSEL_SHIFT) -# define SCT_CONFIG_CLKSEL_REDGE0 (0 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 0 */ -# define SCT_CONFIG_CLKSEL_FEDGE0 (1 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 0 */ -# define SCT_CONFIG_CLKSEL_REDGE1 (2 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 1 */ -# define SCT_CONFIG_CLKSEL_FEDGE1 (3 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 1 */ -# define SCT_CONFIG_CLKSEL_REDGE2 (4 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 2 */ -# define SCT_CONFIG_CLKSEL_FEDGE2 (5 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 2 */ -# define SCT_CONFIG_CLKSEL_REDGE3 (6 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 3 */ -# define SCT_CONFIG_CLKSEL_FEDGE3 (7 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 3 */ -# define SCT_CONFIG_CLKSEL_REDGE4 (8 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 4 */ -# define SCT_CONFIG_CLKSEL_FEDGE4 (9 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 4 */ -# define SCT_CONFIG_CLKSEL_REDGE5 (10 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 5 */ -# define SCT_CONFIG_CLKSEL_FEDGE5 (11 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 5 */ -# define SCT_CONFIG_CLKSEL_REDGE6 (12 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 6 */ -# define SCT_CONFIG_CLKSEL_FEDGE6 (13 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 6 */ -# define SCT_CONFIG_CLKSEL_REDGE7 (14 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 7 */ -# define SCT_CONFIG_CLKSEL_FEDGE7 (15 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 7 */ +# define SCT_CONFIG_CLKSEL_REDGE0 (0 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 0 */ +# define SCT_CONFIG_CLKSEL_FEDGE0 (1 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 0 */ +# define SCT_CONFIG_CLKSEL_REDGE1 (2 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 1 */ +# define SCT_CONFIG_CLKSEL_FEDGE1 (3 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 1 */ +# define SCT_CONFIG_CLKSEL_REDGE2 (4 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 2 */ +# define SCT_CONFIG_CLKSEL_FEDGE2 (5 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 2 */ +# define SCT_CONFIG_CLKSEL_REDGE3 (6 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 3 */ +# define SCT_CONFIG_CLKSEL_FEDGE3 (7 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 3 */ +# define SCT_CONFIG_CLKSEL_REDGE4 (8 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 4 */ +# define SCT_CONFIG_CLKSEL_FEDGE4 (9 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 4 */ +# define SCT_CONFIG_CLKSEL_REDGE5 (10 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 5 */ +# define SCT_CONFIG_CLKSEL_FEDGE5 (11 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 5 */ +# define SCT_CONFIG_CLKSEL_REDGE6 (12 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 6 */ +# define SCT_CONFIG_CLKSEL_FEDGE6 (13 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 6 */ +# define SCT_CONFIG_CLKSEL_REDGE7 (14 << SCT_CONFIG_CLKSEL_SHIFT) /* Rising edges on input 7 */ +# define SCT_CONFIG_CLKSEL_FEDGE7 (15 << SCT_CONFIG_CLKSEL_SHIFT) /* Falling edges on input 7 */ #define SCT_CONFIG_NORELOADU (1 << 7) /* Bit 7: Disable unified match register reload */ #define SCT_CONFIG_NORELOADL (1 << 7) /* Bit 7: Disable lower match registers reload */ diff --git a/arch/arm/src/lpc43xx/lpc43_ethernet.c b/arch/arm/src/lpc43xx/lpc43_ethernet.c index f57cd6f57c..053e9ccfcc 100644 --- a/arch/arm/src/lpc43xx/lpc43_ethernet.c +++ b/arch/arm/src/lpc43xx/lpc43_ethernet.c @@ -552,9 +552,9 @@ static uint32_t lpc43_getreg(uint32_t addr); static void lpc43_putreg(uint32_t val, uint32_t addr); static void lpc43_checksetup(void); #else -# define lpc43_getreg(addr) getreg32(addr) -# define lpc43_putreg(val,addr) putreg32(val,addr) -# define lpc43_checksetup() +# define lpc43_getreg(addr) getreg32(addr) +# define lpc43_putreg(val,addr) putreg32(val,addr) +# define lpc43_checksetup() #endif /* Free buffer management */ diff --git a/arch/arm/src/lpc43xx/lpc43_sdmmc.c b/arch/arm/src/lpc43xx/lpc43_sdmmc.c index 553db45076..7498d7fe7c 100644 --- a/arch/arm/src/lpc43xx/lpc43_sdmmc.c +++ b/arch/arm/src/lpc43xx/lpc43_sdmmc.c @@ -245,8 +245,8 @@ struct lpc43_dev_s static uint32_t lpc43_getreg(uint32_t addr); static void lpc43_putreg(uint32_t val, uint32_t addr); #else -# define lpc43_getreg(addr) getreg32(addr) -# define lpc43_putreg(val,addr) putreg32(val,addr) +# define lpc43_getreg(addr) getreg32(addr) +# define lpc43_putreg(val,addr) putreg32(val,addr) #endif /* Low-level helpers ********************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_serial.c b/arch/arm/src/lpc43xx/lpc43_serial.c index ad0381acf9..f142ccee66 100644 --- a/arch/arm/src/lpc43xx/lpc43_serial.c +++ b/arch/arm/src/lpc43xx/lpc43_serial.c @@ -341,7 +341,7 @@ static uart_dev_t g_usart3port = # define CONSOLE_DEV g_usart3port /* USART3=console */ # define TTYS0_DEV g_usart3port /* USART3=ttyS0 */ # define USART3_ASSIGNED 1 -# endif +# endif #else /* No console, assign only ttyS0 */ @@ -357,7 +357,7 @@ static uart_dev_t g_usart3port = # else /* elif defined(CONFIG_LPC43_USART3) */ # define TTYS0_DEV g_usart3port /* USART3=ttyS0 */ # define USART3_ASSIGNED 1 -# endif +# endif #endif /* Assign ttyS1 */ diff --git a/arch/arm/src/lpc43xx/lpc43_timer.c b/arch/arm/src/lpc43xx/lpc43_timer.c index f690b8c610..59569ec368 100644 --- a/arch/arm/src/lpc43xx/lpc43_timer.c +++ b/arch/arm/src/lpc43xx/lpc43_timer.c @@ -96,8 +96,8 @@ struct lpc43_lowerhalf_s static uint32_t lpc43_getreg(uint32_t addr); static void lpc43_putreg(uint32_t val, uint32_t addr); #else -# define lpc43_getreg(addr) getreg32(addr) -# define lpc43_putreg(val,addr) putreg32(val,addr) +# define lpc43_getreg(addr) getreg32(addr) +# define lpc43_putreg(val,addr) putreg32(val,addr) #endif /* Interrupt handling *******************************************************/ diff --git a/arch/arm/src/lpc43xx/lpc43_usb0dev.c b/arch/arm/src/lpc43xx/lpc43_usb0dev.c index 71f3f90c11..eeefdfc9dc 100644 --- a/arch/arm/src/lpc43xx/lpc43_usb0dev.c +++ b/arch/arm/src/lpc43xx/lpc43_usb0dev.c @@ -344,8 +344,8 @@ struct lpc43_usbdev_s static uint32_t lpc43_getreg(uint32_t addr); static void lpc43_putreg(uint32_t val, uint32_t addr); #else -# define lpc43_getreg(addr) getreg32(addr) -# define lpc43_putreg(val,addr) putreg32(val,addr) +# define lpc43_getreg(addr) getreg32(addr) +# define lpc43_putreg(val,addr) putreg32(val,addr) #endif static inline void lpc43_clrbits(uint32_t mask, uint32_t addr); diff --git a/arch/arm/src/lpc54xx/hardware/lpc54_dma.h b/arch/arm/src/lpc54xx/hardware/lpc54_dma.h index 23e64a0bc1..6fc95d7778 100644 --- a/arch/arm/src/lpc54xx/hardware/lpc54_dma.h +++ b/arch/arm/src/lpc54xx/hardware/lpc54_dma.h @@ -134,17 +134,17 @@ #define DMA_CFG_TRIGBURST (1 << 6) /* Bit 6: Trigger Burst */ #define DMA_CFG_BURSTPOWER_SHIFT (8) /* Bits 8-11: Burst Power */ #define DMA_CFG_BURSTPOWER_MASK (15 << DMA_CFG_BURSTPOWER_SHIFT) -# define DMA_CFG_BURSTPOWER_1 (0 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 1 (2^0) */ -# define DMA_CFG_BURSTPOWER_2 (1 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 2 (2^1) */ -# define DMA_CFG_BURSTPOWER_3 (2 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 4 (2^2) */ -# define DMA_CFG_BURSTPOWER_8 (3 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 8 (2^2) */ -# define DMA_CFG_BURSTPOWER_16 (4 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 16 (2^2) */ -# define DMA_CFG_BURSTPOWER_32 (5 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 32 (2^2) */ -# define DMA_CFG_BURSTPOWER_64 (6 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 64 (2^2) */ -# define DMA_CFG_BURSTPOWER_128 (7 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 128 (2^2) */ -# define DMA_CFG_BURSTPOWER_256 (8 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 256 (2^2) */ -# define DMA_CFG_BURSTPOWER_512 (9 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 256 (2^2) */ -# define DMA_CFG_BURSTPOWER_1024 (10 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 1024 (2^10) */ +# define DMA_CFG_BURSTPOWER_1 (0 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 1 (2^0) */ +# define DMA_CFG_BURSTPOWER_2 (1 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 2 (2^1) */ +# define DMA_CFG_BURSTPOWER_3 (2 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 4 (2^2) */ +# define DMA_CFG_BURSTPOWER_8 (3 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 8 (2^2) */ +# define DMA_CFG_BURSTPOWER_16 (4 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 16 (2^2) */ +# define DMA_CFG_BURSTPOWER_32 (5 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 32 (2^2) */ +# define DMA_CFG_BURSTPOWER_64 (6 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 64 (2^2) */ +# define DMA_CFG_BURSTPOWER_128 (7 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 128 (2^2) */ +# define DMA_CFG_BURSTPOWER_256 (8 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 256 (2^2) */ +# define DMA_CFG_BURSTPOWER_512 (9 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 256 (2^2) */ +# define DMA_CFG_BURSTPOWER_1024 (10 << DMA_CFG_BURSTPOWER_SHIFT) /* Burst size = 1024 (2^10) */ #define DMA_CFG_SRCBURSTWRAP (1 << 14) /* Bit 14: Source Burst Wrap */ #define DMA_CFG_DSTBURSTWRAP (1 << 15) /* Bit 15: Destination Burst Wrap */ diff --git a/arch/arm/src/lpc54xx/hardware/lpc54_ethernet.h b/arch/arm/src/lpc54xx/hardware/lpc54_ethernet.h index 93a42af265..2f06d7a188 100644 --- a/arch/arm/src/lpc54xx/hardware/lpc54_ethernet.h +++ b/arch/arm/src/lpc54xx/hardware/lpc54_ethernet.h @@ -571,13 +571,13 @@ #define ETH_DMA_MODE_TXPR (1 << 11) /* Bit 11: Transmit priority */ #define ETH_DMA_MODE_PR_SHIFT (12) /* Bits 12-14: Priority ratio */ #define ETH_DMA_MODE_PR_MASK (7 << ETH_DMA_MODE_PR_SHIFT) -# define ETH_DMA_MODE_PR_1TO1 (0 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 1:1 */ -# define ETH_DMA_MODE_PR_3TO1 (2 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 3:1 */ -# define ETH_DMA_MODE_PR_4TO1 (3 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 4:1 */ -# define ETH_DMA_MODE_PR_5TO1 (4 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 5:1 */ -# define ETH_DMA_MODE_PR_6TO1 (5 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 6:1 */ -# define ETH_DMA_MODE_PR_7TO1 (6 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 7:1 */ -# define ETH_DMA_MODE_PR_8TO1 (7 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 8:1 */ +# define ETH_DMA_MODE_PR_1TO1 (0 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 1:1 */ +# define ETH_DMA_MODE_PR_3TO1 (2 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 3:1 */ +# define ETH_DMA_MODE_PR_4TO1 (3 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 4:1 */ +# define ETH_DMA_MODE_PR_5TO1 (4 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 5:1 */ +# define ETH_DMA_MODE_PR_6TO1 (5 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 6:1 */ +# define ETH_DMA_MODE_PR_7TO1 (6 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 7:1 */ +# define ETH_DMA_MODE_PR_8TO1 (7 << ETH_DMA_MODE_PR_SHIFT) /* Priority ratio is 8:1 */ /* DMA system bus mode */ diff --git a/arch/arm/src/lpc54xx/lpc54_ethernet.c b/arch/arm/src/lpc54xx/lpc54_ethernet.c index dd90770137..d4ec7ba5a6 100644 --- a/arch/arm/src/lpc54xx/lpc54_ethernet.c +++ b/arch/arm/src/lpc54xx/lpc54_ethernet.c @@ -370,8 +370,8 @@ static uint32_t *g_txbuffers1[CONFIG_LPC54_ETH_NTXDESC1]; static uint32_t lpc54_getreg(uintptr_t addr); static void lpc54_putreg(uint32_t val, uintptr_t addr); #else -# define lpc54_getreg(addr) getreg32(addr) -# define lpc54_putreg(val,addr) putreg32(val,addr) +# define lpc54_getreg(addr) getreg32(addr) +# define lpc54_putreg(val,addr) putreg32(val,addr) #endif /* Common TX logic */ diff --git a/arch/arm/src/lpc54xx/lpc54_sdmmc.c b/arch/arm/src/lpc54xx/lpc54_sdmmc.c index b8d28f5839..398131567b 100644 --- a/arch/arm/src/lpc54xx/lpc54_sdmmc.c +++ b/arch/arm/src/lpc54xx/lpc54_sdmmc.c @@ -245,8 +245,8 @@ struct lpc54_dev_s static uint32_t lpc54_getreg(uint32_t addr); static void lpc54_putreg(uint32_t val, uint32_t addr); #else -# define lpc54_getreg(addr) getreg32(addr) -# define lpc54_putreg(val,addr) putreg32(val,addr) +# define lpc54_getreg(addr) getreg32(addr) +# define lpc54_putreg(val,addr) putreg32(val,addr) #endif /* Low-level helpers ********************************************************/ diff --git a/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c b/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c index 0cf834ffba..6deba1bcde 100644 --- a/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c +++ b/arch/arm/src/lpc54xx/lpc54_usb0_ohci.c @@ -364,8 +364,8 @@ static void lpc54_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t lpc54_getreg(uint32_t addr); static void lpc54_putreg(uint32_t val, uint32_t addr); #else -# define lpc54_getreg(addr) getreg32(addr) -# define lpc54_putreg(val,addr) putreg32(val,addr) +# define lpc54_getreg(addr) getreg32(addr) +# define lpc54_putreg(val,addr) putreg32(val,addr) #endif /* Byte stream access helper functions **************************************/ diff --git a/arch/arm/src/phy62xx/phy62xx_hardfault.c b/arch/arm/src/phy62xx/phy62xx_hardfault.c index 7189fe8b36..3213aa8848 100644 --- a/arch/arm/src/phy62xx/phy62xx_hardfault.c +++ b/arch/arm/src/phy62xx/phy62xx_hardfault.c @@ -42,15 +42,15 @@ extern uint8_t _stextram[]; extern uint8_t _etextram[]; #ifdef CONFIG_DEBUG_HARDFAULT_ALERT -# define hfalert(format, ...) _alert(format, ##__VA_ARGS__) +# define hfalert(format, ...) _alert(format, ##__VA_ARGS__) #else -# define hfalert(x...) +# define hfalert(x...) #endif #ifdef CONFIG_DEBUG_HARDFAULT_INFO -# define hfinfo(format, ...) _info(format, ##__VA_ARGS__) +# define hfinfo(format, ...) _info(format, ##__VA_ARGS__) #else -# define hfinfo(x...) +# define hfinfo(x...) #endif #define INSN_SVC0 0xdf00 /* insn: svc 0 */ diff --git a/arch/arm/src/rp2040/hardware/rp2040_memorymap.h b/arch/arm/src/rp2040/hardware/rp2040_memorymap.h index 0f4d90817f..b905159c2c 100644 --- a/arch/arm/src/rp2040/hardware/rp2040_memorymap.h +++ b/arch/arm/src/rp2040/hardware/rp2040_memorymap.h @@ -113,10 +113,10 @@ #ifndef __ASSEMBLY__ -# define xorbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_XOR_REG_OFFSET) -# define setbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_SET_REG_OFFSET) -# define clrbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_CLR_REG_OFFSET) -# define modbits_reg32(v,m,a) xorbits_reg32((getreg32(a) ^ (v)) & (m), a) +# define xorbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_XOR_REG_OFFSET) +# define setbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_SET_REG_OFFSET) +# define clrbits_reg32(v,a) putreg32(v, (a) | RP2040_ATOMIC_CLR_REG_OFFSET) +# define modbits_reg32(v,m,a) xorbits_reg32((getreg32(a) ^ (v)) & (m), a) /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h index 8192f2478e..f7304ed30d 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_enet.h @@ -514,13 +514,13 @@ */ #ifdef S32K1XX_ENET_HAS_DBSWAP -# ifndef CONFIG_ENDIAN_BIG -# define S32K1XX_USE_DBSWAP -# endif +# ifndef CONFIG_ENDIAN_BIG +# define S32K1XX_USE_DBSWAP +# endif #else -# ifndef CONFIG_ENDIAN_BIG -# define S32K1XX_BUFFERS_SWAP -# endif +# ifndef CONFIG_ENDIAN_BIG +# define S32K1XX_BUFFERS_SWAP +# endif #endif #ifndef S32K1XX_BUFFERS_SWAP diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_sim.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_sim.h index ff4e67b5a2..283d1907ff 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_sim.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_sim.h @@ -190,8 +190,8 @@ /* ADC Options Register */ #define SIM_ADCOPT_ADC0TRGSEL (1 << 0) /* Bit 0: ADC0 trigger source select */ -# define SIM_ADCOPT_ADC0TRGSEL_PDB (0) /* PDB output */ -# define SIM_ADCOPT_ADC0TRGSEL_TRGMUX (1 << 0) /* TRGMUX output */ +# define SIM_ADCOPT_ADC0TRGSEL_PDB (0) /* PDB output */ +# define SIM_ADCOPT_ADC0TRGSEL_TRGMUX (1 << 0) /* TRGMUX output */ #define SIM_ADCOPT_ADC0SWPRETRG_SHIFT (1) /* Bits 1-3: ADC0 software pretrigger sources */ #define SIM_ADCOPT_ADC0SWPRETRG_MASK (7 << SIM_ADCOPT_ADC0SWPRETRG_SHIFT) # define SIM_ADCOPT_ADC0SWPRETRG_DISABLED (0 << SIM_ADCOPT_ADC0SWPRETRG_SHIFT) /* Software pretrigger disabled */ @@ -207,8 +207,8 @@ # define SIM_ADCOPT_ADC0PRETRGSEL_SW (2 << SIM_ADCOPT_ADC0PRETRGSEL_SHIFT) /* Software pretrigger */ #define SIM_ADCOPT_ADC1TRGSEL (1 << 8) /* Bit 8: ADC1 trigger source select */ -# define SIM_ADCOPT_ADC1TRGSEL_PDB (0) /* PDB output */ -# define SIM_ADCOPT_ADC1TRGSEL_TRGMUX (1 << 8) /* TRGMUX output */ +# define SIM_ADCOPT_ADC1TRGSEL_PDB (0) /* PDB output */ +# define SIM_ADCOPT_ADC1TRGSEL_TRGMUX (1 << 8) /* TRGMUX output */ #define SIM_ADCOPT_ADC1SWPRETRG_SHIFT (9) /* Bits 9-11: ADC1 software pretrigger sources */ #define SIM_ADCOPT_ADC1SWPRETRG_MASK (7 << SIM_ADCOPT_ADC1SWPRETRG_SHIFT) # define SIM_ADCOPT_ADC1SWPRETRG_DISABLED (0 << SIM_ADCOPT_ADC1SWPRETRG_SHIFT) /* Software pretrigger disabled */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_lpspi.c b/arch/arm/src/s32k1xx/s32k1xx_lpspi.c index 82ca35f178..a17dc91164 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_lpspi.c +++ b/arch/arm/src/s32k1xx/s32k1xx_lpspi.c @@ -1917,7 +1917,7 @@ static void s32k1xx_lpspi_bus_initialize(struct s32k1xx_lpspidev_s *priv) static void up_pm_notify(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { -# ifdef CONFIG_PM_SPI0 +# ifdef CONFIG_PM_SPI0 struct s32k1xx_lpspidev_s *priv0 = NULL; @@ -1925,8 +1925,8 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain, priv0 = &g_lpspi0dev; -# endif -# ifdef CONFIG_PM_SPI1 +# endif +# ifdef CONFIG_PM_SPI1 struct s32k1xx_lpspidev_s *priv1 = NULL; @@ -1934,7 +1934,7 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain, priv1 = &g_lpspi1dev; -# endif +# endif unsigned int count = 0; /* the amount of peripheral clocks to change */ @@ -1967,19 +1967,19 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain, clock_source = CLK_SRC_SPLL_DIV2; -# ifdef CONFIG_PM_SPI0 +# ifdef CONFIG_PM_SPI0 /* add 1 to count to do it for SPI0 */ count++; -# endif +# endif -# ifdef CONFIG_PM_SPI1 +# ifdef CONFIG_PM_SPI1 /* add 1 to count to do it for SPI1 */ count++; -# endif +# endif } break; @@ -1998,7 +1998,7 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain, const struct peripheral_clock_config_s clock_config[] = { -# ifdef CONFIG_PM_SPI0 +# ifdef CONFIG_PM_SPI0 { .clkname = LPSPI0_CLK, @@ -2007,8 +2007,8 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain, .frac = MULTIPLY_BY_ONE, .divider = 1, }, -# endif -# ifdef CONFIG_PM_SPI1 +# endif +# ifdef CONFIG_PM_SPI1 { .clkname = LPSPI1_CLK, @@ -2017,45 +2017,45 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain, .frac = MULTIPLY_BY_ONE, .divider = 1, } -# endif +# endif }; -# ifdef CONFIG_PM_SPI0 +# ifdef CONFIG_PM_SPI0 /* disable LPSP0 */ s32k1xx_lpspi_modifyreg32(priv0, S32K1XX_LPSPI_CR_OFFSET, 0, !LPSPI_CR_MEN); -# endif -# ifdef CONFIG_PM_SPI1 +# endif +# ifdef CONFIG_PM_SPI1 /* disable LPSPI */ s32k1xx_lpspi_modifyreg32(priv1, S32K1XX_LPSPI_CR_OFFSET, 0, !LPSPI_CR_MEN); -# endif +# endif /* change the clock config for the new mode */ s32k1xx_periphclocks(count, clock_config); -# ifdef CONFIG_PM_SPI0 +# ifdef CONFIG_PM_SPI0 /* Enable LPSP0 */ s32k1xx_lpspi_modifyreg32(priv0, S32K1XX_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); -# endif -# ifdef CONFIG_PM_SPI1 +# endif +# ifdef CONFIG_PM_SPI1 /* Enable LPSPI */ s32k1xx_lpspi_modifyreg32(priv1, S32K1XX_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); -# endif +# endif /* get the clock freq */ } @@ -2276,14 +2276,14 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, /* make the private struct for lpspi bus 0 */ priv0 = &g_lpspi0dev; -# endif -# ifdef CONFIG_PM_SPI1 +# endif +# ifdef CONFIG_PM_SPI1 struct s32k1xx_lpspidev_s *priv1 = NULL; /* make the private struct for lpspi bus 1 */ priv1 = &g_lpspi1dev; -# endif +# endif unsigned int count = 0; /* the amount of peripheral clocks to change */ @@ -2312,20 +2312,20 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, clock_source = CLK_SRC_SIRC_DIV2; -# ifdef CONFIG_PM_SPI0_STANDBY +# ifdef CONFIG_PM_SPI0_STANDBY /* increase count to change the SPI0 */ count++; -# endif -# ifdef CONFIG_PM_SPI1_STANDBY +# endif +# ifdef CONFIG_PM_SPI1_STANDBY /* increase count to change the SPI1 */ count++; -# endif +# endif } break; @@ -2339,20 +2339,20 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, clock_source = CLK_SRC_SIRC_DIV2; -# ifdef CONFIG_PM_SPI0_SLEEP +# ifdef CONFIG_PM_SPI0_SLEEP /* increase count to change the SPI0 */ count++; -# endif -# ifdef CONFIG_PM_SPI1_SLEEP +# endif +# ifdef CONFIG_PM_SPI1_SLEEP /* increase count to change the SPI1 */ count++; -# endif +# endif } break; @@ -2371,7 +2371,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, const struct peripheral_clock_config_s clock_config[] = { -# ifdef CONFIG_PM_SPI0 +# ifdef CONFIG_PM_SPI0 { .clkname = LPSPI0_CLK, .clkgate = true, @@ -2379,8 +2379,8 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, .frac = MULTIPLY_BY_ONE, .divider = 1, }, -# endif -# ifdef CONFIG_PM_SPI1 +# endif +# ifdef CONFIG_PM_SPI1 { .clkname = LPSPI1_CLK, .clkgate = true, @@ -2388,46 +2388,46 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, .frac = MULTIPLY_BY_ONE, .divider = 1, } -# endif +# endif }; -# ifdef CONFIG_PM_SPI0 +# ifdef CONFIG_PM_SPI0 /* disable LPSPI0 */ s32k1xx_lpspi_modifyreg32(priv0, S32K1XX_LPSPI_CR_OFFSET, 0, !LPSPI_CR_MEN); -# endif -# ifdef CONFIG_PM_SPI1 +# endif +# ifdef CONFIG_PM_SPI1 /* disable LPSPI1 */ s32k1xx_lpspi_modifyreg32(priv1, S32K1XX_LPSPI_CR_OFFSET, 0, !LPSPI_CR_MEN); -# endif +# endif /* change the clock config for the new mode */ s32k1xx_periphclocks(count, clock_config); -# ifdef CONFIG_PM_SPI0 +# ifdef CONFIG_PM_SPI0 /* Enable LPSPI */ s32k1xx_lpspi_modifyreg32(priv0, S32K1XX_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); -# endif -# ifdef CONFIG_PM_SPI1 +# endif +# ifdef CONFIG_PM_SPI1 /* Enable LPSPI */ s32k1xx_lpspi_modifyreg32(priv1, S32K1XX_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); -# endif +# endif } /* get the clock freq */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_serial.c b/arch/arm/src/s32k1xx/s32k1xx_serial.c index 738d4d93a2..df2b2ed83f 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_serial.c +++ b/arch/arm/src/s32k1xx/s32k1xx_serial.c @@ -608,7 +608,7 @@ static struct s32k1xx_uart_s g_lpuart2priv = # ifdef CONFIG_LPUART2_RXDMA .dma_rxreqsrc = S32K1XX_DMACHAN_LPUART2_RX, .rxfifo = g_lpuart2rxfifo, -# endif +# endif }; #endif diff --git a/arch/arm/src/s32k3xx/s32k3xx_qspi.c b/arch/arm/src/s32k3xx/s32k3xx_qspi.c index 4fde2bdb66..5a6ebcb9b7 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_qspi.c +++ b/arch/arm/src/s32k3xx/s32k3xx_qspi.c @@ -151,7 +151,7 @@ static void qspi_resetregisters(void); #if defined(CONFIG_DEBUG_SPI_INFO) && defined(CONFIG_DEBUG_GPIO) static void qspi_dumpgpioconfig(const char *msg); #else -# define qspi_dumpgpioconfig(msg) +# define qspi_dumpgpioconfig(msg) #endif static inline uint32_t qspi_isbusy(void); diff --git a/arch/arm/src/s32k3xx/s32k3xx_serial.c b/arch/arm/src/s32k3xx/s32k3xx_serial.c index 3768307870..ca30e7fa50 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_serial.c +++ b/arch/arm/src/s32k3xx/s32k3xx_serial.c @@ -1730,37 +1730,37 @@ static struct s32k3xx_uart_s g_lpuart0priv = .parity = CONFIG_LPUART0_PARITY, .bits = CONFIG_LPUART0_BITS, .stopbits2 = CONFIG_LPUART0_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART0_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART0_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART0_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART0_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART0_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART0_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART0_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART0_IFLOWCONTROL))) .rts_gpio = PIN_LPUART0_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART0_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART0_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART0_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART0_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART0_TXDMA +# ifdef CONFIG_LPUART0_TXDMA .dma_txreqsrc = DMA_REQ_LPUART08_TX, -#endif -#ifdef CONFIG_LPUART0_RXDMA +# endif +# ifdef CONFIG_LPUART0_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART08_RX, .rxfifo = g_lpuart0rxfifo, -#endif +# endif }; #endif @@ -1779,15 +1779,15 @@ static struct s32k3xx_uart_s g_lpuart1priv = .size = CONFIG_LPUART1_TXBUFSIZE, .buffer = g_lpuart1txbuffer, }, - #if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) +# if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA) +# elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) +# elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart1priv, }, @@ -1797,37 +1797,37 @@ static struct s32k3xx_uart_s g_lpuart1priv = .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART1_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL))) .rts_gpio = PIN_LPUART1_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART1_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART1_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART1_TXDMA +# ifdef CONFIG_LPUART1_TXDMA .dma_txreqsrc = DMA_REQ_LPUART19_TX, -#endif -#ifdef CONFIG_LPUART1_RXDMA +# endif +# ifdef CONFIG_LPUART1_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART19_RX, .rxfifo = g_lpuart1rxfifo, -#endif +# endif }; #endif @@ -1846,15 +1846,15 @@ static struct s32k3xx_uart_s g_lpuart2priv = .size = CONFIG_LPUART2_TXBUFSIZE, .buffer = g_lpuart2txbuffer, }, - #if defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_TXDMA) +# if defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART2_RXDMA) && !defined(CONFIG_LPUART2_TXDMA) +# elif defined(CONFIG_LPUART2_RXDMA) && !defined(CONFIG_LPUART2_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_TXDMA) +# elif !defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart2priv, }, @@ -1864,37 +1864,37 @@ static struct s32k3xx_uart_s g_lpuart2priv = .parity = CONFIG_LPUART2_PARITY, .bits = CONFIG_LPUART2_BITS, .stopbits2 = CONFIG_LPUART2_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART2_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL))) .rts_gpio = PIN_LPUART2_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART2_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART2_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART2_TXDMA +# ifdef CONFIG_LPUART2_TXDMA .dma_txreqsrc = DMA_REQ_LPUART210_TX, -#endif -#ifdef CONFIG_LPUART2_RXDMA +# endif +# ifdef CONFIG_LPUART2_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART210_RX, .rxfifo = g_lpuart2rxfifo, -#endif +# endif }; #endif @@ -1913,15 +1913,15 @@ static struct s32k3xx_uart_s g_lpuart3priv = .size = CONFIG_LPUART3_TXBUFSIZE, .buffer = g_lpuart3txbuffer, }, - #if defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA) +# if defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART3_RXDMA) && !defined(CONFIG_LPUART3_TXDMA) +# elif defined(CONFIG_LPUART3_RXDMA) && !defined(CONFIG_LPUART3_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA) +# elif !defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart3priv, }, @@ -1931,37 +1931,37 @@ static struct s32k3xx_uart_s g_lpuart3priv = .parity = CONFIG_LPUART3_PARITY, .bits = CONFIG_LPUART3_BITS, .stopbits2 = CONFIG_LPUART3_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART3_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART3_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART3_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL))) .rts_gpio = PIN_LPUART3_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART3_TX, -#endif + #endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART3_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART3_TXDMA +# ifdef CONFIG_LPUART3_TXDMA .dma_txreqsrc = DMA_REQ_LPUART311_TX, -#endif -#ifdef CONFIG_LPUART3_RXDMA +# endif +# ifdef CONFIG_LPUART3_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART311_RX, .rxfifo = g_lpuart3rxfifo, -#endif +# endif }; #endif @@ -1980,15 +1980,15 @@ static struct s32k3xx_uart_s g_lpuart4priv = .size = CONFIG_LPUART4_TXBUFSIZE, .buffer = g_lpuart4txbuffer, }, - #if defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_TXDMA) +# if defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART4_RXDMA) && !defined(CONFIG_LPUART4_TXDMA) +# elif defined(CONFIG_LPUART4_RXDMA) && !defined(CONFIG_LPUART4_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_TXDMA) +# elif !defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart4priv, }, @@ -1998,37 +1998,37 @@ static struct s32k3xx_uart_s g_lpuart4priv = .parity = CONFIG_LPUART4_PARITY, .bits = CONFIG_LPUART4_BITS, .stopbits2 = CONFIG_LPUART4_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART4_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART4_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART4_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL))) .rts_gpio = PIN_LPUART4_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART4_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART4_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART4_TXDMA +# ifdef CONFIG_LPUART4_TXDMA .dma_txreqsrc = DMA_REQ_LPUART412_TX, -#endif -#ifdef CONFIG_LPUART4_RXDMA +# endif +# ifdef CONFIG_LPUART4_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART412_RX, .rxfifo = g_lpuart4rxfifo, -#endif +# endif }; #endif @@ -2047,15 +2047,15 @@ static struct s32k3xx_uart_s g_lpuart5priv = .size = CONFIG_LPUART5_TXBUFSIZE, .buffer = g_lpuart5txbuffer, }, - #if defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA) +# if defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART5_RXDMA) && !defined(CONFIG_LPUART5_TXDMA) +# elif defined(CONFIG_LPUART5_RXDMA) && !defined(CONFIG_LPUART5_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA) +# elif !defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart5priv, }, @@ -2065,37 +2065,37 @@ static struct s32k3xx_uart_s g_lpuart5priv = .parity = CONFIG_LPUART5_PARITY, .bits = CONFIG_LPUART5_BITS, .stopbits2 = CONFIG_LPUART5_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART5_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART5_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART5_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL))) .rts_gpio = PIN_LPUART5_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART5_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART5_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART5_TXDMA +# ifdef CONFIG_LPUART5_TXDMA .dma_txreqsrc = DMA_REQ_LPUART513_TX, -#endif -#ifdef CONFIG_LPUART5_RXDMA +# endif +# ifdef CONFIG_LPUART5_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART513_RX, .rxfifo = g_lpuart5rxfifo, -#endif +# endif }; #endif @@ -2114,15 +2114,15 @@ static struct s32k3xx_uart_s g_lpuart6priv = .size = CONFIG_LPUART6_TXBUFSIZE, .buffer = g_lpuart6txbuffer, }, - #if defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA) +# if defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART6_RXDMA) && !defined(CONFIG_LPUART6_TXDMA) +# elif defined(CONFIG_LPUART6_RXDMA) && !defined(CONFIG_LPUART6_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA) +# elif !defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart6priv, }, @@ -2132,37 +2132,37 @@ static struct s32k3xx_uart_s g_lpuart6priv = .parity = CONFIG_LPUART6_PARITY, .bits = CONFIG_LPUART6_BITS, .stopbits2 = CONFIG_LPUART6_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART6_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART6_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART6_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL))) .rts_gpio = PIN_LPUART6_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART6_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART6_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART6_TXDMA +# ifdef CONFIG_LPUART6_TXDMA .dma_txreqsrc = DMA_REQ_LPUART614_TX, -#endif -#ifdef CONFIG_LPUART6_RXDMA +# endif +# ifdef CONFIG_LPUART6_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART614_RX, .rxfifo = g_lpuart6rxfifo, -#endif +# endif }; #endif @@ -2181,15 +2181,15 @@ static struct s32k3xx_uart_s g_lpuart7priv = .size = CONFIG_LPUART7_TXBUFSIZE, .buffer = g_lpuart7txbuffer, }, - #if defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA) +# if defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART7_RXDMA) && !defined(CONFIG_LPUART7_TXDMA) +# elif defined(CONFIG_LPUART7_RXDMA) && !defined(CONFIG_LPUART7_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA) +# elif !defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart7priv, }, @@ -2199,37 +2199,37 @@ static struct s32k3xx_uart_s g_lpuart7priv = .parity = CONFIG_LPUART7_PARITY, .bits = CONFIG_LPUART7_BITS, .stopbits2 = CONFIG_LPUART7_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART7_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART7_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART7_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL))) .rts_gpio = PIN_LPUART7_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART7_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART7_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART7_TXDMA +# ifdef CONFIG_LPUART7_TXDMA .dma_txreqsrc = DMA_REQ_LPUART715_TX, -#endif -#ifdef CONFIG_LPUART7_RXDMA +# endif +# ifdef CONFIG_LPUART7_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART715_RX, .rxfifo = g_lpuart7rxfifo, -#endif +# endif }; #endif @@ -2248,15 +2248,15 @@ static struct s32k3xx_uart_s g_lpuart8priv = .size = CONFIG_LPUART8_TXBUFSIZE, .buffer = g_lpuart8txbuffer, }, - #if defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA) +# if defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART8_RXDMA) && !defined(CONFIG_LPUART8_TXDMA) +# elif defined(CONFIG_LPUART8_RXDMA) && !defined(CONFIG_LPUART8_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA) +# elif !defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart8priv, }, @@ -2266,37 +2266,37 @@ static struct s32k3xx_uart_s g_lpuart8priv = .parity = CONFIG_LPUART8_PARITY, .bits = CONFIG_LPUART8_BITS, .stopbits2 = CONFIG_LPUART8_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART8_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART8_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART8_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL))) .rts_gpio = PIN_LPUART8_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART8_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART8_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART8_TXDMA +# ifdef CONFIG_LPUART8_TXDMA .dma_txreqsrc = DMA_REQ_LPUART08_TX, -#endif -#ifdef CONFIG_LPUART8_RXDMA +# endif +# ifdef CONFIG_LPUART8_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART08_RX, .rxfifo = g_lpuart8rxfifo, -#endif +# endif }; #endif @@ -2315,15 +2315,15 @@ static struct s32k3xx_uart_s g_lpuart9priv = .size = CONFIG_LPUART9_TXBUFSIZE, .buffer = g_lpuart9txbuffer, }, - #if defined(CONFIG_LPUART9_RXDMA) && defined(CONFIG_LPUART9_TXDMA) +# if defined(CONFIG_LPUART9_RXDMA) && defined(CONFIG_LPUART9_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART9_RXDMA) && !defined(CONFIG_LPUART9_TXDMA) +# elif defined(CONFIG_LPUART9_RXDMA) && !defined(CONFIG_LPUART9_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART9_RXDMA) && defined(CONFIG_LPUART9_TXDMA) +# elif !defined(CONFIG_LPUART9_RXDMA) && defined(CONFIG_LPUART9_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart9priv, }, @@ -2333,37 +2333,37 @@ static struct s32k3xx_uart_s g_lpuart9priv = .parity = CONFIG_LPUART9_PARITY, .bits = CONFIG_LPUART9_BITS, .stopbits2 = CONFIG_LPUART9_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART9_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART9_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART9_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART9_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART9_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART9_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART9_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART9_IFLOWCONTROL))) .rts_gpio = PIN_LPUART9_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART9_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART9_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART9_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART9_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART9_TXDMA +# ifdef CONFIG_LPUART9_TXDMA .dma_txreqsrc = DMA_REQ_LPUART19_TX, -#endif -#ifdef CONFIG_LPUART9_RXDMA +# endif +# ifdef CONFIG_LPUART9_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART19_RX, .rxfifo = g_lpuart9rxfifo, -#endif +# endif }; #endif @@ -2382,15 +2382,15 @@ static struct s32k3xx_uart_s g_lpuart10priv = .size = CONFIG_LPUART10_TXBUFSIZE, .buffer = g_lpuart10txbuffer, }, - #if defined(CONFIG_LPUART10_RXDMA) && defined(CONFIG_LPUART10_TXDMA) +# if defined(CONFIG_LPUART10_RXDMA) && defined(CONFIG_LPUART10_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART10_RXDMA) && !defined(CONFIG_LPUART10_TXDMA) +# elif defined(CONFIG_LPUART10_RXDMA) && !defined(CONFIG_LPUART10_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART10_RXDMA) && defined(CONFIG_LPUART10_TXDMA) +# elif !defined(CONFIG_LPUART10_RXDMA) && defined(CONFIG_LPUART10_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart10priv, }, @@ -2400,37 +2400,37 @@ static struct s32k3xx_uart_s g_lpuart10priv = .parity = CONFIG_LPUART10_PARITY, .bits = CONFIG_LPUART10_BITS, .stopbits2 = CONFIG_LPUART10_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART10_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART10_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART10_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART10_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART10_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART10_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART10_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART10_IFLOWCONTROL))) .rts_gpio = PIN_LPUART10_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART10_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART10_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART10_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART10_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART10_TXDMA +# ifdef CONFIG_LPUART10_TXDMA .dma_txreqsrc = DMA_REQ_LPUART210_TX, -#endif -#ifdef CONFIG_LPUART10_RXDMA +# endif +# ifdef CONFIG_LPUART10_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART210_RX, .rxfifo = g_lpuart10rxfifo, -#endif +# endif }; #endif @@ -2449,15 +2449,15 @@ static struct s32k3xx_uart_s g_lpuart11priv = .size = CONFIG_LPUART11_TXBUFSIZE, .buffer = g_lpuart11txbuffer, }, - #if defined(CONFIG_LPUART11_RXDMA) && defined(CONFIG_LPUART11_TXDMA) +# if defined(CONFIG_LPUART11_RXDMA) && defined(CONFIG_LPUART11_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART11_RXDMA) && !defined(CONFIG_LPUART11_TXDMA) +# elif defined(CONFIG_LPUART11_RXDMA) && !defined(CONFIG_LPUART11_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART11_RXDMA) && defined(CONFIG_LPUART11_TXDMA) +# elif !defined(CONFIG_LPUART11_RXDMA) && defined(CONFIG_LPUART11_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart11priv, }, @@ -2467,37 +2467,37 @@ static struct s32k3xx_uart_s g_lpuart11priv = .parity = CONFIG_LPUART11_PARITY, .bits = CONFIG_LPUART11_BITS, .stopbits2 = CONFIG_LPUART11_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART11_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART11_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART11_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART11_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART11_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART11_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART11_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART11_IFLOWCONTROL))) .rts_gpio = PIN_LPUART11_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART11_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART11_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART11_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART11_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART11_TXDMA +# ifdef CONFIG_LPUART11_TXDMA .dma_txreqsrc = DMA_REQ_LPUART311_TX, -#endif -#ifdef CONFIG_LPUART11_RXDMA +# endif +# ifdef CONFIG_LPUART11_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART311_RX, .rxfifo = g_lpuart11rxfifo, -#endif +# endif }; #endif @@ -2516,15 +2516,15 @@ static struct s32k3xx_uart_s g_lpuart12priv = .size = CONFIG_LPUART12_TXBUFSIZE, .buffer = g_lpuart12txbuffer, }, - #if defined(CONFIG_LPUART12_RXDMA) && defined(CONFIG_LPUART12_TXDMA) +# if defined(CONFIG_LPUART12_RXDMA) && defined(CONFIG_LPUART12_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART12_RXDMA) && !defined(CONFIG_LPUART12_TXDMA) +# elif defined(CONFIG_LPUART12_RXDMA) && !defined(CONFIG_LPUART12_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART12_RXDMA) && defined(CONFIG_LPUART12_TXDMA) +# elif !defined(CONFIG_LPUART12_RXDMA) && defined(CONFIG_LPUART12_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart12priv, }, @@ -2534,37 +2534,37 @@ static struct s32k3xx_uart_s g_lpuart12priv = .parity = CONFIG_LPUART12_PARITY, .bits = CONFIG_LPUART12_BITS, .stopbits2 = CONFIG_LPUART12_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART12_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART12_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART12_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART12_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART12_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART12_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART12_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART12_IFLOWCONTROL))) .rts_gpio = PIN_LPUART12_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART12_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART12_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART12_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART12_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART12_TXDMA +# ifdef CONFIG_LPUART12_TXDMA .dma_txreqsrc = DMA_REQ_LPUART412_TX, -#endif -#ifdef CONFIG_LPUART12_RXDMA +# endif +# ifdef CONFIG_LPUART12_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART412_RX, .rxfifo = g_lpuart12rxfifo, -#endif +# endif }; #endif @@ -2583,15 +2583,15 @@ static struct s32k3xx_uart_s g_lpuart13priv = .size = CONFIG_LPUART13_TXBUFSIZE, .buffer = g_lpuart13txbuffer, }, - #if defined(CONFIG_LPUART13_RXDMA) && defined(CONFIG_LPUART13_TXDMA) +# if defined(CONFIG_LPUART13_RXDMA) && defined(CONFIG_LPUART13_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART13_RXDMA) && !defined(CONFIG_LPUART13_TXDMA) +# elif defined(CONFIG_LPUART13_RXDMA) && !defined(CONFIG_LPUART13_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART13_RXDMA) && defined(CONFIG_LPUART13_TXDMA) +# elif !defined(CONFIG_LPUART13_RXDMA) && defined(CONFIG_LPUART13_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart13priv, }, @@ -2601,37 +2601,37 @@ static struct s32k3xx_uart_s g_lpuart13priv = .parity = CONFIG_LPUART13_PARITY, .bits = CONFIG_LPUART13_BITS, .stopbits2 = CONFIG_LPUART13_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART13_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART13_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART13_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART13_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART13_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART13_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART13_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART13_IFLOWCONTROL))) .rts_gpio = PIN_LPUART13_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART13_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART13_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART13_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART13_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART13_TXDMA +# ifdef CONFIG_LPUART13_TXDMA .dma_txreqsrc = DMA_REQ_LPUART513_TX, -#endif -#ifdef CONFIG_LPUART13_RXDMA +# endif +# ifdef CONFIG_LPUART13_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART513_RX, .rxfifo = g_lpuart13rxfifo, -#endif +# endif }; #endif @@ -2650,15 +2650,15 @@ static struct s32k3xx_uart_s g_lpuart14priv = .size = CONFIG_LPUART14_TXBUFSIZE, .buffer = g_lpuart14txbuffer, }, - #if defined(CONFIG_LPUART14_RXDMA) && defined(CONFIG_LPUART14_TXDMA) +# if defined(CONFIG_LPUART14_RXDMA) && defined(CONFIG_LPUART14_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART14_RXDMA) && !defined(CONFIG_LPUART14_TXDMA) +# elif defined(CONFIG_LPUART14_RXDMA) && !defined(CONFIG_LPUART14_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART14_RXDMA) && defined(CONFIG_LPUART14_TXDMA) +# elif !defined(CONFIG_LPUART14_RXDMA) && defined(CONFIG_LPUART14_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart14priv, }, @@ -2668,37 +2668,37 @@ static struct s32k3xx_uart_s g_lpuart14priv = .parity = CONFIG_LPUART14_PARITY, .bits = CONFIG_LPUART14_BITS, .stopbits2 = CONFIG_LPUART14_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART14_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART14_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART14_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART14_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART14_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART14_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART14_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART14_IFLOWCONTROL))) .rts_gpio = PIN_LPUART14_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART14_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART14_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART14_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART14_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART14_TXDMA +# ifdef CONFIG_LPUART14_TXDMA .dma_txreqsrc = DMA_REQ_LPUART614_TX, -#endif -#ifdef CONFIG_LPUART14_RXDMA +# endif +# ifdef CONFIG_LPUART14_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART614_RX, .rxfifo = g_lpuart14rxfifo, -#endif +# endif }; #endif @@ -2717,15 +2717,15 @@ static struct s32k3xx_uart_s g_lpuart15priv = .size = CONFIG_LPUART15_TXBUFSIZE, .buffer = g_lpuart15txbuffer, }, - #if defined(CONFIG_LPUART15_RXDMA) && defined(CONFIG_LPUART15_TXDMA) +# if defined(CONFIG_LPUART15_RXDMA) && defined(CONFIG_LPUART15_TXDMA) .ops = &g_lpuart_rxtxdma_ops, - #elif defined(CONFIG_LPUART15_RXDMA) && !defined(CONFIG_LPUART15_TXDMA) +# elif defined(CONFIG_LPUART15_RXDMA) && !defined(CONFIG_LPUART15_TXDMA) .ops = &g_lpuart_rxdma_ops, - #elif !defined(CONFIG_LPUART15_RXDMA) && defined(CONFIG_LPUART15_TXDMA) +# elif !defined(CONFIG_LPUART15_RXDMA) && defined(CONFIG_LPUART15_TXDMA) .ops = &g_lpuart_txdma_ops, - #else +# else .ops = &g_lpuart_ops, - #endif +# endif .priv = &g_lpuart15priv, }, @@ -2735,37 +2735,37 @@ static struct s32k3xx_uart_s g_lpuart15priv = .parity = CONFIG_LPUART15_PARITY, .bits = CONFIG_LPUART15_BITS, .stopbits2 = CONFIG_LPUART15_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART15_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART15_OFLOWCONTROL) .oflow = 1, .cts_gpio = PIN_LPUART15_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART15_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART15_IFLOWCONTROL) .iflow = 1, -#endif -# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART15_RS485RTSCONTROL)) || \ +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART15_RS485RTSCONTROL)) || \ (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART15_IFLOWCONTROL))) .rts_gpio = PIN_LPUART15_RTS, -#endif -#ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE +# endif +# ifdef CONFIG_S32K3XX_LPUART_SINGLEWIRE .tx_gpio = PIN_LPUART15_TX, -#endif +# endif -#if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ defined(CONFIG_LPUART15_INVERTIFLOWCONTROL) .inviflow = 1, -#endif +# endif -#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART15_RS485RTSCONTROL) +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART15_RS485RTSCONTROL) .rs485mode = 1, -#endif +# endif -#ifdef CONFIG_LPUART15_TXDMA +# ifdef CONFIG_LPUART15_TXDMA .dma_txreqsrc = DMA_REQ_LPUART715_TX, -#endif -#ifdef CONFIG_LPUART15_RXDMA +# endif +# ifdef CONFIG_LPUART15_RXDMA .dma_rxreqsrc = DMA_REQ_LPUART715_RX, .rxfifo = g_lpuart15rxfifo, -#endif +# endif }; #endif diff --git a/arch/arm/src/sam34/hardware/sam4l_bpm.h b/arch/arm/src/sam34/hardware/sam4l_bpm.h index 03809efe65..5b4c1eb404 100644 --- a/arch/arm/src/sam34/hardware/sam4l_bpm.h +++ b/arch/arm/src/sam34/hardware/sam4l_bpm.h @@ -105,10 +105,10 @@ #define BPM_PMCON_RET (1 << 9) /* Bit 9: RETENTION Mode */ #define BPM_PMCON_SLEEP_SHIFT (12) /* Bits 12-13: SLEEP mode Configuration */ #define BPM_PMCON_SLEEP_MASK (3 << BPM_PMCON_SLEEP_SHIFT) -# define BPM_PMCON_SLEEP_SLEEP0 (0 << BPM_PMCON_SLEEP_SHIFT) /* CPU clock stopped */ -# define BPM_PMCON_SLEEP_SLEEP1 (1 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB clocks stopped */ -# define BPM_PMCON_SLEEP_SLEEP2 (2 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK clocks stopped */ -# define BPM_PMCON_SLEEP_SLEEP3 (3 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK+sources stopped */ +# define BPM_PMCON_SLEEP_SLEEP0 (0 << BPM_PMCON_SLEEP_SHIFT) /* CPU clock stopped */ +# define BPM_PMCON_SLEEP_SLEEP1 (1 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB clocks stopped */ +# define BPM_PMCON_SLEEP_SLEEP2 (2 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK clocks stopped */ +# define BPM_PMCON_SLEEP_SLEEP3 (3 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK+sources stopped */ #define BPM_PMCON_CK32S (1 << 16) /* Bit 16: 32kHz-1kHz Clock Source Selection */ #define BPM_PMCON_FASTWKUP (1 << 24) /* Bit 24: Fast Wakeup */ diff --git a/arch/arm/src/sam34/hardware/sam4l_picouart.h b/arch/arm/src/sam34/hardware/sam4l_picouart.h index 4a6821a44f..674c85dc26 100644 --- a/arch/arm/src/sam34/hardware/sam4l_picouart.h +++ b/arch/arm/src/sam34/hardware/sam4l_picouart.h @@ -66,10 +66,10 @@ #define PICOUART_CFG_SOURCE_SHIFT (0) /* Bit 0-1: Source Enable Mode */ #define PICOUART_CFG_SOURCE_MASK (3 << PICOUART_CFG_SOURCE_SHIFT) -# define PICOUART_CFG_SOURCE_WE (0 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up and event disable */ -# define PICOUART_CFG_SOURCE_WESB (1 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on start bit detection */ -# define PICOUART_CFG_SOURCE_WEFF (2 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on full frame reception */ -# define PICOUART_CFG_SOURCE_WECH (3 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on character recognition */ +# define PICOUART_CFG_SOURCE_WE (0 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up and event disable */ +# define PICOUART_CFG_SOURCE_WESB (1 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on start bit detection */ +# define PICOUART_CFG_SOURCE_WEFF (2 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on full frame reception */ +# define PICOUART_CFG_SOURCE_WECH (3 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on character recognition */ #define PICOUART_CFG_ACTION (1 << 0) /* Bit 0: Action to perform */ #define PICOUART_CFG_MATCH_SHIFT (8) /* Bit 8-15: Data Match */ diff --git a/arch/arm/src/sam34/hardware/sam_afec.h b/arch/arm/src/sam34/hardware/sam_afec.h index cafb4e638e..dd616ab8e8 100644 --- a/arch/arm/src/sam34/hardware/sam_afec.h +++ b/arch/arm/src/sam34/hardware/sam_afec.h @@ -209,12 +209,12 @@ # define AFEC_EMR_CMPFILTER(n) ((uint32_t)(n) << AFEC_EMR_CMPFILTER_SHIFT) #define AFEC_EMR_RES_SHIFT (16) /* Bits 16-18: Resolution */ #define AFEC_EMR_RES_MASK (7 << AFEC_EMR_RES_SHIFT) -# define AFEC_EMR_RES_NOAVG (0 << AFEC_EMR_RES_SHIFT) /* 12-bit resolution, AFEC sample rate is maximum (no averaging) */ -# define AFEC_EMR_RES_LOWRES (1 << AFEC_EMR_RES_SHIFT) /* 10-bit resolution, AFEC sample rate is maximum (no averaging) */ -# define AFEC_EMR_RES_OSR4 (2 << AFEC_EMR_RES_SHIFT) /* 13-bit resolution, AFEC sample rate divided by 4 (averaging) */ -# define AFEC_EMR_RES_OSR16 (3 << AFEC_EMR_RES_SHIFT) /* 14-bit resolution, AFEC sample rate divided by 16 (averaging) */ -# define AFEC_EMR_RES_OSR64 (4 << AFEC_EMR_RES_SHIFT) /* 15-bit resolution, AFEC sample rate divided by 64 (averaging) */ -# define AFEC_EMR_RES_OSR256 (5 << AFEC_EMR_RES_SHIFT) /* 16-bit resolution, AFEC sample rate divided by 256 (averaging) */ +# define AFEC_EMR_RES_NOAVG (0 << AFEC_EMR_RES_SHIFT) /* 12-bit resolution, AFEC sample rate is maximum (no averaging) */ +# define AFEC_EMR_RES_LOWRES (1 << AFEC_EMR_RES_SHIFT) /* 10-bit resolution, AFEC sample rate is maximum (no averaging) */ +# define AFEC_EMR_RES_OSR4 (2 << AFEC_EMR_RES_SHIFT) /* 13-bit resolution, AFEC sample rate divided by 4 (averaging) */ +# define AFEC_EMR_RES_OSR16 (3 << AFEC_EMR_RES_SHIFT) /* 14-bit resolution, AFEC sample rate divided by 16 (averaging) */ +# define AFEC_EMR_RES_OSR64 (4 << AFEC_EMR_RES_SHIFT) /* 15-bit resolution, AFEC sample rate divided by 64 (averaging) */ +# define AFEC_EMR_RES_OSR256 (5 << AFEC_EMR_RES_SHIFT) /* 16-bit resolution, AFEC sample rate divided by 256 (averaging) */ #define AFEC_EMR_TAG (1 << 24) /* Bit 24: TAG of the AFEC_LDCR register */ #define AFEC_EMR_STM (1 << 25) /* Bit 25: Single Trigger Mode */ diff --git a/arch/arm/src/sam34/sam4s_nand.h b/arch/arm/src/sam34/sam4s_nand.h index e1fbe485af..23dbb10353 100644 --- a/arch/arm/src/sam34/sam4s_nand.h +++ b/arch/arm/src/sam34/sam4s_nand.h @@ -47,7 +47,7 @@ /* Only NCS0 can support NAND. The rest is a fantasy */ #if defined(CONFIG_SAM34_EXTNAND) - # define CONFIG_SAM34_NCS0_NAND 1 + # define CONFIG_SAM34_NCS0_NAND 1 #else # undef CONFIG_SAM34_NCS0_NAND #endif diff --git a/arch/arm/src/sam34/sam_emac.c b/arch/arm/src/sam34/sam_emac.c index 490f4dc7bb..e215297a34 100644 --- a/arch/arm/src/sam34/sam_emac.c +++ b/arch/arm/src/sam34/sam_emac.c @@ -329,8 +329,8 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t addr); static void sam_putreg(struct sam_emac_s *priv, uintptr_t addr, uint32_t val); #else -# define sam_getreg(priv,addr) getreg32(addr) -# define sam_putreg(priv,addr,val) putreg32(val,addr) +# define sam_getreg(priv,addr) getreg32(addr) +# define sam_putreg(priv,addr,val) putreg32(val,addr) #endif /* Buffer management */ diff --git a/arch/arm/src/sam34/sam_rtc.c b/arch/arm/src/sam34/sam_rtc.c index 17e60ea5b3..f0661dfa51 100644 --- a/arch/arm/src/sam34/sam_rtc.c +++ b/arch/arm/src/sam34/sam_rtc.c @@ -52,12 +52,12 @@ /* Configuration ************************************************************/ #ifdef CONFIG_RTC_HIRES -# if !defined(CONFIG_SAM34_RTT) -# error RTT is required to emulate high resolution RTC -# endif -# if (CONFIG_RTC_FREQUENCY > 32768) || ((32768 % CONFIG_RTC_FREQUENCY) != 0) -# error CONFIG_RTC_FREQUENCY must be an integer division of 32768 -# endif +# if !defined(CONFIG_SAM34_RTT) +# error RTT is required to emulate high resolution RTC +# endif +# if (CONFIG_RTC_FREQUENCY > 32768) || ((32768 % CONFIG_RTC_FREQUENCY) != 0) +# error CONFIG_RTC_FREQUENCY must be an integer division of 32768 +# endif #endif #if defined(CONFIG_RTC_ALARM) && !defined(CONFIG_SCHED_WORKQUEUE) diff --git a/arch/arm/src/sam34/sam_rtt.c b/arch/arm/src/sam34/sam_rtt.c index 80d6eeefdf..7ae534564a 100644 --- a/arch/arm/src/sam34/sam_rtt.c +++ b/arch/arm/src/sam34/sam_rtt.c @@ -99,8 +99,8 @@ struct sam34_lowerhalf_s static uint32_t sam34_getreg(uint32_t addr); static void sam34_putreg(uint32_t val, uint32_t addr); #else -# define sam34_getreg(addr) getreg32(addr) -# define sam34_putreg(val,addr) putreg32(val,addr) +# define sam34_getreg(addr) getreg32(addr) +# define sam34_putreg(val,addr) putreg32(val,addr) #endif /* Interrupt handling *******************************************************/ diff --git a/arch/arm/src/sam34/sam_spi.c b/arch/arm/src/sam34/sam_spi.c index 5e35a71d0c..4ecfea4128 100644 --- a/arch/arm/src/sam34/sam_spi.c +++ b/arch/arm/src/sam34/sam_spi.c @@ -214,7 +214,7 @@ struct sam_spidev_s static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value, uint32_t address); #else -# define spi_checkreg(spi,wr,value,address) (false) +# define spi_checkreg(spi,wr,value,address) (false) #endif static inline uint32_t spi_getreg(struct sam_spidev_s *spi, @@ -226,7 +226,7 @@ static inline struct sam_spidev_s *spi_device(struct sam_spics_s *spics); #ifdef CONFIG_DEBUG_SPI_INFO static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg); #else -# define spi_dumpregs(spi,msg) +# define spi_dumpregs(spi,msg) #endif static inline void spi_flush(struct sam_spidev_s *spi); diff --git a/arch/arm/src/sam34/sam_tc.c b/arch/arm/src/sam34/sam_tc.c index 45d50e4af8..5bfb0d11f2 100644 --- a/arch/arm/src/sam34/sam_tc.c +++ b/arch/arm/src/sam34/sam_tc.c @@ -97,8 +97,8 @@ struct sam34_lowerhalf_s static uint32_t sam34_getreg(uint32_t addr); static void sam34_putreg(uint32_t val, uint32_t addr); #else -# define sam34_getreg(addr) getreg32(addr) -# define sam34_putreg(val,addr) putreg32(val,addr) +# define sam34_getreg(addr) getreg32(addr) +# define sam34_putreg(val,addr) putreg32(val,addr) #endif /* Interrupt handling *******************************************************/ diff --git a/arch/arm/src/sam34/sam_twi.c b/arch/arm/src/sam34/sam_twi.c index 3cd93c2f41..eae14a5643 100644 --- a/arch/arm/src/sam34/sam_twi.c +++ b/arch/arm/src/sam34/sam_twi.c @@ -148,9 +148,9 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address); static void twi_putabs(struct twi_dev_s *priv, uintptr_t address, uint32_t value); #else -# define twi_checkreg(priv,wr,value,address) (false) -# define twi_putabs(p,a,v) putreg32(v,a) -# define twi_getabs(p,a) getreg32(a) +# define twi_checkreg(priv,wr,value,address) (false) +# define twi_putabs(p,a,v) putreg32(v,a) +# define twi_getabs(p,a) getreg32(a) #endif static inline uint32_t twi_getrel(struct twi_dev_s *priv, diff --git a/arch/arm/src/sam34/sam_udp.c b/arch/arm/src/sam34/sam_udp.c index d9fdca2e5b..cab91708c4 100644 --- a/arch/arm/src/sam34/sam_udp.c +++ b/arch/arm/src/sam34/sam_udp.c @@ -329,7 +329,7 @@ static void sam_dumpep(struct sam_usbdev_s *priv, uint8_t epno); #else static inline uint32_t sam_getreg(uintptr_t regaddr); static inline void sam_putreg(uint32_t regval, uintptr_t regaddr); -# define sam_dumpep(priv,epno) +# define sam_dumpep(priv,epno) #endif static void sam_csr_setbits(uint8_t epno, uint32_t setbits); diff --git a/arch/arm/src/sam34/sam_wdt.c b/arch/arm/src/sam34/sam_wdt.c index aa3f8cec82..4e5af9e140 100644 --- a/arch/arm/src/sam34/sam_wdt.c +++ b/arch/arm/src/sam34/sam_wdt.c @@ -103,8 +103,8 @@ struct sam34_lowerhalf_s static uint32_t sam34_getreg(uint32_t addr); static void sam34_putreg(uint32_t val, uint32_t addr); #else -# define sam34_getreg(addr) getreg32(addr) -# define sam34_putreg(val,addr) putreg32(val,addr) +# define sam34_getreg(addr) getreg32(addr) +# define sam34_putreg(val,addr) putreg32(val,addr) #endif /* Interrupt handling *******************************************************/ diff --git a/arch/arm/src/sama5/hardware/sam_gmac.h b/arch/arm/src/sama5/hardware/sam_gmac.h index 42180aff1b..ef72e2aea7 100644 --- a/arch/arm/src/sama5/hardware/sam_gmac.h +++ b/arch/arm/src/sama5/hardware/sam_gmac.h @@ -1002,10 +1002,10 @@ #define GMACRXD_STA_SNAP (1 << 24) /* Bit 24: Frame was SNAP encoded */ #define GMACRXD_STA_ADDR_SHIFT (25) /* Bits 25-26: Specific Address Register match */ #define GMACRXD_STA_ADDR_MASK (3 << GMACRXD_STA_ADDR_SHIFT) -# define GMACRXD_STA_ADDR1_MATCH (0 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 1 match */ -# define GMACRXD_STA_ADDR2_MATCH (1 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 2 match */ -# define GMACRXD_STA_ADDR3_MATCH (2 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 3 match */ -# define GMACRXD_STA_ADDR4_MATCH (3 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 4 match */ +# define GMACRXD_STA_ADDR1_MATCH (0 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 1 match */ +# define GMACRXD_STA_ADDR2_MATCH (1 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 2 match */ +# define GMACRXD_STA_ADDR3_MATCH (2 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 3 match */ +# define GMACRXD_STA_ADDR4_MATCH (3 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 4 match */ #define GMACRXD_STA_ADDRMATCH (1 << 27) /* Bit 27: Specific Address Register match found */ /* Bit 28: Reserved */ diff --git a/arch/arm/src/sama5/hardware/sam_sdmmc.h b/arch/arm/src/sama5/hardware/sam_sdmmc.h index 0439f13ca6..9fe4f12d2c 100644 --- a/arch/arm/src/sama5/hardware/sam_sdmmc.h +++ b/arch/arm/src/sama5/hardware/sam_sdmmc.h @@ -591,9 +591,9 @@ enum bus_mode */ #ifdef CONFIG_SAMA5_SDMMC_50MHZ -# define SAMA5_SDMMC_BUS_SPEED 50000000 +# define SAMA5_SDMMC_BUS_SPEED 50000000 #else -# define SAMA5_SDMMC_BUS_SPEED 25000000 +# define SAMA5_SDMMC_BUS_SPEED 25000000 #endif /* SDMA default buffer size - needed to reset the start address after an SDMA diff --git a/arch/arm/src/sama5/hardware/sam_trng.h b/arch/arm/src/sama5/hardware/sam_trng.h index 8806bcf120..5975544638 100644 --- a/arch/arm/src/sama5/hardware/sam_trng.h +++ b/arch/arm/src/sama5/hardware/sam_trng.h @@ -58,7 +58,7 @@ # define TRNG_CR_DISABLE (0) /* Bit 0: 0=Disables the TRNG */ #define TRNG_CR_KEY_SHIFT (8) /* Bits 8-31: Security key */ #define TRNG_CR_KEY_MASK (0xffffff << TRNG_CR_KEY_SHIFT) -# define TRNG_CR_KEY (0x524e47 << TRNG_CR_KEY_SHIFT) /* RNG in ASCII */ +# define TRNG_CR_KEY (0x524e47 << TRNG_CR_KEY_SHIFT) /* RNG in ASCII */ /* Interrupt Enable Register, * Interrupt Disable Register, Interrupt Mask Register, diff --git a/arch/arm/src/sama5/sam_allocateheap.c b/arch/arm/src/sama5/sam_allocateheap.c index b2293be8f9..90bd2cdcbd 100644 --- a/arch/arm/src/sama5/sam_allocateheap.c +++ b/arch/arm/src/sama5/sam_allocateheap.c @@ -131,7 +131,7 @@ # error CONFIG_SAMA5_DDRCS_HEAP_END is beyond CONFIG_RAM_VEND # elif CONFIG_SAMA5_DDRCS_HEAP_END < CONFIG_RAM_VSTART # error CONFIG_SAMA5_DDRCS_HEAP_END is before CONFIG_RAM_VSTART -# endif +# endif # define SAMA5_PRIMARY_HEAP_END CONFIG_SAMA5_DDRCS_HEAP_END #else diff --git a/arch/arm/src/sama5/sam_emaca.c b/arch/arm/src/sama5/sam_emaca.c index 6af9c6d347..9e19eaf478 100644 --- a/arch/arm/src/sama5/sam_emaca.c +++ b/arch/arm/src/sama5/sam_emaca.c @@ -360,8 +360,8 @@ static uint32_t sam_getreg(struct sam_emac_s *priv, uintptr_t addr); static void sam_putreg(struct sam_emac_s *priv, uintptr_t addr, uint32_t val); #else -# define sam_getreg(priv,addr) getreg32(addr) -# define sam_putreg(priv,addr,val) putreg32(val,addr) +# define sam_getreg(priv,addr) getreg32(addr) +# define sam_putreg(priv,addr,val) putreg32(val,addr) #endif /* Buffer management */ diff --git a/arch/arm/src/sama5/sam_flexcom_spi.c b/arch/arm/src/sama5/sam_flexcom_spi.c index 2c3a2db464..29c85cd208 100644 --- a/arch/arm/src/sama5/sam_flexcom_spi.c +++ b/arch/arm/src/sama5/sam_flexcom_spi.c @@ -235,7 +235,7 @@ static inline struct sam_flex_spidev_s static void flex_spi_dumpregs(struct sam_flex_spidev_s *flex_spi, const char *msg); #else -# define flex_spi_dumpregs(flex_spi,msg) +# define flex_spi_dumpregs(flex_spi,msg) #endif static inline void flex_spi_flush(struct sam_flex_spidev_s *flex_spi); diff --git a/arch/arm/src/sama5/sam_gmac.c b/arch/arm/src/sama5/sam_gmac.c index fc54473a7c..07cce97b9e 100644 --- a/arch/arm/src/sama5/sam_gmac.c +++ b/arch/arm/src/sama5/sam_gmac.c @@ -285,8 +285,8 @@ static uint32_t sam_getreg(struct sam_gmac_s *priv, uintptr_t addr); static void sam_putreg(struct sam_gmac_s *priv, uintptr_t addr, uint32_t val); #else -# define sam_getreg(priv,addr) getreg32(addr) -# define sam_putreg(priv,addr,val) putreg32(val,addr) +# define sam_getreg(priv,addr) getreg32(addr) +# define sam_putreg(priv,addr,val) putreg32(val,addr) #endif /* Buffer management */ diff --git a/arch/arm/src/sama5/sam_hsmci.c b/arch/arm/src/sama5/sam_hsmci.c index 749f3143e0..1c4475ec41 100644 --- a/arch/arm/src/sama5/sam_hsmci.c +++ b/arch/arm/src/sama5/sam_hsmci.c @@ -458,7 +458,7 @@ struct sam_dev_s static bool sam_checkreg(struct sam_dev_s *priv, bool wr, uint32_t value, uint32_t address); #else -# define sam_checkreg(priv,wr,value,address) (false) +# define sam_checkreg(priv,wr,value,address) (false) #endif static inline uint32_t sam_getreg(struct sam_dev_s *priv, diff --git a/arch/arm/src/sama5/sam_ohci.c b/arch/arm/src/sama5/sam_ohci.c index 72711ed096..c3db4d59fd 100644 --- a/arch/arm/src/sama5/sam_ohci.c +++ b/arch/arm/src/sama5/sam_ohci.c @@ -338,8 +338,8 @@ static void sam_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t sam_getreg(uint32_t addr); static void sam_putreg(uint32_t val, uint32_t addr); #else -# define sam_getreg(addr) getreg32(addr) -# define sam_putreg(val,addr) putreg32(val,addr) +# define sam_getreg(addr) getreg32(addr) +# define sam_putreg(val,addr) putreg32(val,addr) #endif /* Byte stream access helper functions **************************************/ diff --git a/arch/arm/src/sama5/sam_pwm.c b/arch/arm/src/sama5/sam_pwm.c index 3c2144694c..fb76d80320 100644 --- a/arch/arm/src/sama5/sam_pwm.c +++ b/arch/arm/src/sama5/sam_pwm.c @@ -302,7 +302,7 @@ static bool pwm_checkreg(struct sam_pwm_s *chan, bool wr, uint32_t regval, uintptr_t regaddr); #else -# define pwm_checkreg(chan,wr,regval,regaddr) (false) +# define pwm_checkreg(chan,wr,regval,regaddr) (false) #endif static uint32_t pwm_getreg(struct sam_pwm_chan_s *chan, int offset); diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c index e7b7746415..6d9037e1c0 100644 --- a/arch/arm/src/sama5/sam_spi.c +++ b/arch/arm/src/sama5/sam_spi.c @@ -201,7 +201,7 @@ struct sam_spidev_s static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value, uint32_t address); #else -# define spi_checkreg(spi,wr,value,address) (false) +# define spi_checkreg(spi,wr,value,address) (false) #endif static inline uint32_t spi_getreg(struct sam_spidev_s *spi, @@ -213,7 +213,7 @@ static inline struct sam_spidev_s *spi_device(struct sam_spics_s *spics); #ifdef CONFIG_DEBUG_SPI_INFO static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg); #else -# define spi_dumpregs(spi,msg) +# define spi_dumpregs(spi,msg) #endif static inline void spi_flush(struct sam_spidev_s *spi); diff --git a/arch/arm/src/sama5/sam_ssc.c b/arch/arm/src/sama5/sam_ssc.c index 5277a11619..20d33e769a 100644 --- a/arch/arm/src/sama5/sam_ssc.c +++ b/arch/arm/src/sama5/sam_ssc.c @@ -496,7 +496,7 @@ struct sam_ssc_s static bool ssc_checkreg(struct sam_ssc_s *priv, bool wr, uint32_t regval, uint32_t regaddr); #else -# define ssc_checkreg(priv,wr,regval,regaddr) (false) +# define ssc_checkreg(priv,wr,regval,regaddr) (false) #endif static inline uint32_t ssc_getreg(struct sam_ssc_s *priv, diff --git a/arch/arm/src/sama5/sam_twi.c b/arch/arm/src/sama5/sam_twi.c index aa83c8c836..43c4c16fd6 100644 --- a/arch/arm/src/sama5/sam_twi.c +++ b/arch/arm/src/sama5/sam_twi.c @@ -197,9 +197,9 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address); static void twi_putabs(struct twi_dev_s *priv, uintptr_t address, uint32_t value); #else -# define twi_checkreg(priv,wr,value,address) (false) -# define twi_putabs(p,a,v) putreg32(v,a) -# define twi_getabs(p,a) getreg32(a) +# define twi_checkreg(priv,wr,value,address) (false) +# define twi_putabs(p,a,v) putreg32(v,a) +# define twi_getabs(p,a) getreg32(a) #endif static inline uint32_t twi_getrel(struct twi_dev_s *priv, diff --git a/arch/arm/src/sama5/sam_udphs.c b/arch/arm/src/sama5/sam_udphs.c index c1f9e0e4c8..a834077e5f 100644 --- a/arch/arm/src/sama5/sam_udphs.c +++ b/arch/arm/src/sama5/sam_udphs.c @@ -395,7 +395,7 @@ static void sam_dumpep(struct sam_usbdev_s *priv, int epno); #else static inline uint32_t sam_getreg(uintptr_t regaddr); static inline void sam_putreg(uint32_t regval, uintptr_t regaddr); -# define sam_dumpep(priv,epno) +# define sam_dumpep(priv,epno) #endif /* Suspend/Resume Helpers ***************************************************/ diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c index 1069e5cfc9..abb44dd103 100644 --- a/arch/arm/src/sama5/sam_wdt.c +++ b/arch/arm/src/sama5/sam_wdt.c @@ -102,8 +102,8 @@ struct sam_lowerhalf_s static uint32_t sam_getreg(uintptr_t regaddr); static void sam_putreg(uint32_t regval, uintptr_t regaddr); #else -# define sam_getreg(regaddr) getreg32(regaddr) -# define sam_putreg(regval,regaddr) putreg32(regval,regaddr) +# define sam_getreg(regaddr) getreg32(regaddr) +# define sam_putreg(regval,regaddr) putreg32(regval,regaddr) #endif /* Interrupt handling *******************************************************/ diff --git a/arch/arm/src/samd2l2/sam_spi.c b/arch/arm/src/samd2l2/sam_spi.c index 23fda9dba2..ea9cc1941c 100644 --- a/arch/arm/src/samd2l2/sam_spi.c +++ b/arch/arm/src/samd2l2/sam_spi.c @@ -136,7 +136,7 @@ struct sam_spidev_s static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, uint32_t regval, uint32_t regaddr); #else -# define spi_checkreg(priv,wr,regval,regaddr) (false) +# define spi_checkreg(priv,wr,regval,regaddr) (false) #endif static uint8_t spi_getreg8(struct sam_spidev_s *priv, @@ -159,7 +159,7 @@ static void spi_dma_setup(struct sam_spidev_s *priv); #ifdef CONFIG_DEBUG_SPI_INFO static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg); #else -# define spi_dumpregs(priv,msg) +# define spi_dumpregs(priv,msg) #endif /* Interrupt handling */ diff --git a/arch/arm/src/samd2l2/sam_usb.c b/arch/arm/src/samd2l2/sam_usb.c index 2ce1aaa419..e2da9f3c28 100644 --- a/arch/arm/src/samd2l2/sam_usb.c +++ b/arch/arm/src/samd2l2/sam_usb.c @@ -383,7 +383,7 @@ static inline uint32_t sam_getreg16(uintptr_t regaddr); static inline void sam_putreg16(uint16_t regval, uintptr_t regaddr); static inline uint32_t sam_getreg8(uintptr_t regaddr); static inline void sam_putreg8(uint8_t regval, uintptr_t regaddr); -# define sam_dumpep(priv,epno) +# define sam_dumpep(priv,epno) #endif /* Suspend/Resume Helpers ***************************************************/ diff --git a/arch/arm/src/samd5e5/hardware/sam_gmac.h b/arch/arm/src/samd5e5/hardware/sam_gmac.h index 4f0da6508c..9f39174ba4 100644 --- a/arch/arm/src/samd5e5/hardware/sam_gmac.h +++ b/arch/arm/src/samd5e5/hardware/sam_gmac.h @@ -1003,10 +1003,10 @@ #define GMACRXD_STA_SNAP (1 << 24) /* Bit 24: Frame was SNAP encoded */ #define GMACRXD_STA_ADDR_SHIFT (25) /* Bits 25-26: Specific Address Register match */ #define GMACRXD_STA_ADDR_MASK (3 << GMACRXD_STA_ADDR_SHIFT) -# define GMACRXD_STA_ADDR1_MATCH (0 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 1 match */ -# define GMACRXD_STA_ADDR2_MATCH (1 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 2 match */ -# define GMACRXD_STA_ADDR3_MATCH (2 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 3 match */ -# define GMACRXD_STA_ADDR4_MATCH (3 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 4 match */ +# define GMACRXD_STA_ADDR1_MATCH (0 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 1 match */ +# define GMACRXD_STA_ADDR2_MATCH (1 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 2 match */ +# define GMACRXD_STA_ADDR3_MATCH (2 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 3 match */ +# define GMACRXD_STA_ADDR4_MATCH (3 << GMACRXD_STA_ADDR_SHIFT) /* Specific address register 4 match */ #define GMACRXD_STA_ADDRMATCH (1 << 27) /* Bit 27: Specific Address Register match found */ /* Bit 28: Reserved */ diff --git a/arch/arm/src/samd5e5/sam_gmac.c b/arch/arm/src/samd5e5/sam_gmac.c index c0fed3675c..52e28a26c0 100644 --- a/arch/arm/src/samd5e5/sam_gmac.c +++ b/arch/arm/src/samd5e5/sam_gmac.c @@ -282,8 +282,8 @@ static uint32_t sam_getreg(struct sam_gmac_s *priv, uintptr_t addr); static void sam_putreg(struct sam_gmac_s *priv, uintptr_t addr, uint32_t val); #else -# define sam_getreg(priv,addr) getreg32(addr) -# define sam_putreg(priv,addr,val) putreg32(val,addr) +# define sam_getreg(priv,addr) getreg32(addr) +# define sam_putreg(priv,addr,val) putreg32(val,addr) #endif /* Buffer management */ diff --git a/arch/arm/src/samd5e5/sam_spi.c b/arch/arm/src/samd5e5/sam_spi.c index 0bf2c43e4c..f90bef8d2c 100644 --- a/arch/arm/src/samd5e5/sam_spi.c +++ b/arch/arm/src/samd5e5/sam_spi.c @@ -130,7 +130,7 @@ struct sam_spidev_s static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, uint32_t regval, uint32_t regaddr); #else -# define spi_checkreg(priv,wr,regval,regaddr) (false) +# define spi_checkreg(priv,wr,regval,regaddr) (false) #endif static uint8_t spi_getreg8(struct sam_spidev_s *priv, @@ -153,7 +153,7 @@ static void spi_dma_setup(struct sam_spidev_s *priv); #ifdef CONFIG_DEBUG_SPI_INFO static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg); #else -# define spi_dumpregs(priv,msg) +# define spi_dumpregs(priv,msg) #endif /* Interrupt handling */ diff --git a/arch/arm/src/samd5e5/sam_usb.c b/arch/arm/src/samd5e5/sam_usb.c index 56048971b2..d49c974826 100644 --- a/arch/arm/src/samd5e5/sam_usb.c +++ b/arch/arm/src/samd5e5/sam_usb.c @@ -711,9 +711,9 @@ static inline uint32_t sam_getreg16(uintptr_t regaddr); static inline void sam_putreg16(uint16_t regval, uintptr_t regaddr); static inline uint32_t sam_getreg8(uintptr_t regaddr); static inline void sam_putreg8(uint8_t regval, uintptr_t regaddr); -# define sam_dumpep(priv, epno) +# define sam_dumpep(priv, epno) #ifdef CONFIG_USBHOST -# define sam_dumppipe(priv, epno) +# define sam_dumppipe(priv, epno) #endif #endif static inline void sam_modifyreg8(uint32_t clrbits, diff --git a/arch/arm/src/samv7/hardware/sam_matrix.h b/arch/arm/src/samv7/hardware/sam_matrix.h index 65e5016c64..e7f81fcb8b 100644 --- a/arch/arm/src/samv7/hardware/sam_matrix.h +++ b/arch/arm/src/samv7/hardware/sam_matrix.h @@ -51,7 +51,7 @@ # define SAM_MATRIX_MCFG11_OFFSET 0x002c /* Master Configuration Register 11 */ /* 0x0030-0x003c: Reserved */ #define SAM_MATRIX_SCFG_OFFSET(n) (0x0040+((n)<<2)) -# define SAM_MATRIX_SCFG0_OFFSET 0x0040 /* Slave Configuration Register 0 */ +# define SAM_MATRIX_SCFG0_OFFSET 0x0040 /* Slave Configuration Register 0 */ # define SAM_MATRIX_SCFG1_OFFSET 0x0044 /* Slave Configuration Register 1 */ # define SAM_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */ # define SAM_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */ diff --git a/arch/arm/src/samv7/hardware/sam_trng.h b/arch/arm/src/samv7/hardware/sam_trng.h index c80f4fec3e..f797a7e550 100644 --- a/arch/arm/src/samv7/hardware/sam_trng.h +++ b/arch/arm/src/samv7/hardware/sam_trng.h @@ -58,7 +58,7 @@ # define TRNG_CR_DISABLE (0) /* Bit 0: 0=Disables the TRNG */ #define TRNG_CR_KEY_SHIFT (8) /* Bits 8-31: Security key */ #define TRNG_CR_KEY_MASK (0xffffff << TRNG_CR_KEY_SHIFT) -# define TRNG_CR_KEY (0x524e47 << TRNG_CR_KEY_SHIFT) /* RNG in ASCII */ +# define TRNG_CR_KEY (0x524e47 << TRNG_CR_KEY_SHIFT) /* RNG in ASCII */ /* Interrupt Enable Register, Interrupt Disable Register, * Interrupt Mask Register, and Interrupt Status Register diff --git a/arch/arm/src/samv7/hardware/sam_usbhs.h b/arch/arm/src/samv7/hardware/sam_usbhs.h index c017e82fde..ebac071802 100644 --- a/arch/arm/src/samv7/hardware/sam_usbhs.h +++ b/arch/arm/src/samv7/hardware/sam_usbhs.h @@ -692,9 +692,9 @@ #define USBHS_HSTPIPISR_CURRBK_SHIFT (14) /* Bits 14-15: Current Bank */ #define USBHS_HSTPIPISR_CURRBK_MASK (3 << USBHS_HSTPIPISR_CURRBK_SHIFT) -# define USBHS_HSTPIPISR_CURRBK_BANK0 (0 << USBHS_HSTPIPISR_CURRBK_SHIFT) /* Current bank is bank0 */ -# define USBHS_HSTPIPISR_CURRBK_BANK1 (1 << USBHS_HSTPIPISR_CURRBK_SHIFT) /* Current bank is bank1 */ -# define USBHS_HSTPIPISR_CURRBK_BANK2 (2 << USBHS_HSTPIPISR_CURRBK_SHIFT) /* Current bank is bank2 */ +# define USBHS_HSTPIPISR_CURRBK_BANK0 (0 << USBHS_HSTPIPISR_CURRBK_SHIFT) /* Current bank is bank0 */ +# define USBHS_HSTPIPISR_CURRBK_BANK1 (1 << USBHS_HSTPIPISR_CURRBK_SHIFT) /* Current bank is bank1 */ +# define USBHS_HSTPIPISR_CURRBK_BANK2 (2 << USBHS_HSTPIPISR_CURRBK_SHIFT) /* Current bank is bank2 */ #define USBHS_HSTPIPISR_RWALL (1 << 16) /* Bit 16: Read/Write Allowed */ #define USBHS_HSTPIPISR_CFGOK (1 << 18) /* Bit 18: Configuration OK Status */ diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c index ea5333187d..e11d75c992 100644 --- a/arch/arm/src/samv7/sam_hsmci.c +++ b/arch/arm/src/samv7/sam_hsmci.c @@ -393,7 +393,7 @@ struct sam_dev_s static bool sam_checkreg(struct sam_dev_s *priv, bool wr, uint32_t value, uint32_t address); #else -# define sam_checkreg(priv,wr,value,address) (false) +# define sam_checkreg(priv,wr,value,address) (false) #endif static inline uint32_t sam_getreg(struct sam_dev_s *priv, diff --git a/arch/arm/src/samv7/sam_qspi.c b/arch/arm/src/samv7/sam_qspi.c index ec673b45ae..0c196842f4 100644 --- a/arch/arm/src/samv7/sam_qspi.c +++ b/arch/arm/src/samv7/sam_qspi.c @@ -89,7 +89,7 @@ #endif #ifdef CONFIG_SAMV7_QSPI_DMA -# define SAMV7_QSPI0_DMA true +# define SAMV7_QSPI0_DMA true #endif #ifndef CONFIG_SAMV7_QSPI_DMA @@ -206,7 +206,7 @@ struct sam_qspidev_s static bool qspi_checkreg(struct sam_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else -# define qspi_checkreg(priv,wr,value,address) (false) +# define qspi_checkreg(priv,wr,value,address) (false) #endif static inline uint32_t qspi_getreg(struct sam_qspidev_s *priv, @@ -217,7 +217,7 @@ static inline void qspi_putreg(struct sam_qspidev_s *priv, uint32_t value, #ifdef CONFIG_DEBUG_SPI_INFO static void qspi_dumpregs(struct sam_qspidev_s *priv, const char *msg); #else -# define qspi_dumpregs(priv,msg) +# define qspi_dumpregs(priv,msg) #endif /* DMA support */ diff --git a/arch/arm/src/samv7/sam_rswdt.c b/arch/arm/src/samv7/sam_rswdt.c index eeb77cdc5b..fdc3d78ad8 100644 --- a/arch/arm/src/samv7/sam_rswdt.c +++ b/arch/arm/src/samv7/sam_rswdt.c @@ -102,8 +102,8 @@ struct sam_lowerhalf_s static uint32_t sam_getreg(uintptr_t regaddr); static void sam_putreg(uint32_t regval, uintptr_t regaddr); #else -# define sam_getreg(regaddr) getreg32(regaddr) -# define sam_putreg(regval,regaddr) putreg32(regval,regaddr) +# define sam_getreg(regaddr) getreg32(regaddr) +# define sam_putreg(regval,regaddr) putreg32(regval,regaddr) #endif /* Interrupt handling *******************************************************/ diff --git a/arch/arm/src/samv7/sam_serial.c b/arch/arm/src/samv7/sam_serial.c index 2f2327fdc7..6a4318aaca 100644 --- a/arch/arm/src/samv7/sam_serial.c +++ b/arch/arm/src/samv7/sam_serial.c @@ -64,7 +64,7 @@ #if defined(CONFIG_USART0_RXDMA) || defined(CONFIG_USART1_RXDMA) || \ defined(CONFIG_USART2_RXDMA) -# define SERIAL_HAVE_RXDMA +# define SERIAL_HAVE_RXDMA #else # undef SERIAL_HAVE_RXDMA #endif @@ -91,12 +91,12 @@ #endif #ifndef CONFIG_SAMV7_SERIAL_DMA_TIMEOUT -# define CONFIG_SAMV7_SERIAL_DMA_TIMEOUT 0 +# define CONFIG_SAMV7_SERIAL_DMA_TIMEOUT 0 #endif #ifdef SERIAL_HAVE_RXDMA -# define DMA_RXFLAGS (DMACH_FLAG_FIFOCFG_LARGEST | \ +# define DMA_RXFLAGS (DMACH_FLAG_FIFOCFG_LARGEST | \ DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | \ DMACH_FLAG_PERIPHWIDTH_32BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 | \ DMACH_FLAG_MEMPID_MAX | DMACH_FLAG_MEMAHB_AHB_IF0 | \ @@ -525,29 +525,29 @@ static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; #if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_SERIALDRIVER) static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE]; static char g_usart0txbuffer[CONFIG_USART0_TXBUFSIZE]; -# ifdef CONFIG_USART0_RXDMA +# ifdef CONFIG_USART0_RXDMA static uint32_t g_usart0rxbuf[2][RXDMA_BUFFER_SIZE] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct chnext_view1_s g_usart0rxdesc[2]; -# endif +# endif #endif #if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_SERIALDRIVER) static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; -# ifdef CONFIG_USART1_RXDMA +# ifdef CONFIG_USART1_RXDMA static uint32_t g_usart1rxbuf[2][RXDMA_BUFFER_SIZE] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct chnext_view1_s g_usart1rxdesc[2]; -# endif +# endif #endif #if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_SERIALDRIVER) static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; -# ifdef CONFIG_USART2_RXDMA +# ifdef CONFIG_USART2_RXDMA static uint32_t g_usart2rxbuf[2][RXDMA_BUFFER_SIZE] aligned_data(ARMV7M_DCACHE_LINESIZE); static struct chnext_view1_s g_usart2rxdesc[2]; -# endif +# endif #endif /* This describes the state of the UART0 port. */ @@ -717,10 +717,10 @@ static struct sam_dev_s g_usart0priv = .parity = CONFIG_USART0_PARITY, .bits = CONFIG_USART0_BITS, .stopbits2 = CONFIG_USART0_2STOP, -#if defined(CONFIG_USART0_OFLOWCONTROL) || defined(CONFIG_USART0_IFLOWCONTROL) +# if defined(CONFIG_USART0_OFLOWCONTROL) || defined(CONFIG_USART0_IFLOWCONTROL) .flowc = true, -#endif -#ifdef CONFIG_USART0_RXDMA +# endif +# ifdef CONFIG_USART0_RXDMA .buf_idx = 0, .nextcache = 0, .rxbuf = @@ -732,11 +732,11 @@ static struct sam_dev_s g_usart0priv = &g_usart0rxdesc[0], &g_usart0rxdesc[1] }, .has_rxdma = true, -#endif -#ifdef CONFIG_SAMV7_USART0_RS485MODE +# endif +# ifdef CONFIG_SAMV7_USART0_RS485MODE .has_rs485 = true, .rs485_dir_gpio = GPIO_USART0_RTS, -#endif +# endif }; static uart_dev_t g_usart0port = @@ -751,11 +751,11 @@ static uart_dev_t g_usart0port = .size = CONFIG_USART0_TXBUFSIZE, .buffer = g_usart0txbuffer, }, -#ifdef CONFIG_USART0_RXDMA +# ifdef CONFIG_USART0_RXDMA .ops = &g_uart_rxdma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart0priv, }; #endif @@ -772,10 +772,10 @@ static struct sam_dev_s g_usart1priv = .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, -#if defined(CONFIG_USART1_OFLOWCONTROL) || defined(CONFIG_USART1_IFLOWCONTROL) +# if defined(CONFIG_USART1_OFLOWCONTROL) || defined(CONFIG_USART1_IFLOWCONTROL) .flowc = true, -#endif -#ifdef CONFIG_USART1_RXDMA +# endif +# ifdef CONFIG_USART1_RXDMA .buf_idx = 0, .nextcache = 0, .rxbuf = @@ -787,11 +787,11 @@ static struct sam_dev_s g_usart1priv = &g_usart1rxdesc[0], &g_usart1rxdesc[1] }, .has_rxdma = true, -#endif -#ifdef CONFIG_SAMV7_USART1_RS485MODE +# endif +# ifdef CONFIG_SAMV7_USART1_RS485MODE .has_rs485 = true, .rs485_dir_gpio = GPIO_USART1_RTS, -#endif +# endif }; static uart_dev_t g_usart1port = @@ -806,11 +806,11 @@ static uart_dev_t g_usart1port = .size = CONFIG_USART1_TXBUFSIZE, .buffer = g_usart1txbuffer, }, -#ifdef CONFIG_USART1_RXDMA +# ifdef CONFIG_USART1_RXDMA .ops = &g_uart_rxdma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart1priv, }; #endif @@ -827,10 +827,10 @@ static struct sam_dev_s g_usart2priv = .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, -#if defined(CONFIG_USART2_OFLOWCONTROL) || defined(CONFIG_USART2_IFLOWCONTROL) +# if defined(CONFIG_USART2_OFLOWCONTROL) || defined(CONFIG_USART2_IFLOWCONTROL) .flowc = true, -#endif -#ifdef CONFIG_USART2_RXDMA +# endif +# ifdef CONFIG_USART2_RXDMA .buf_idx = 0, .nextcache = 0, .rxbuf = @@ -842,11 +842,11 @@ static struct sam_dev_s g_usart2priv = &g_usart2rxdesc[0], &g_usart2rxdesc[1] }, .has_rxdma = true, -#endif -#ifdef CONFIG_SAMV7_USART2_RS485MODE +# endif +# ifdef CONFIG_SAMV7_USART2_RS485MODE .has_rs485 = true, .rs485_dir_gpio = GPIO_USART2_RTS, -#endif +# endif }; static uart_dev_t g_usart2port = @@ -861,11 +861,11 @@ static uart_dev_t g_usart2port = .size = CONFIG_USART2_TXBUFSIZE, .buffer = g_usart2txbuffer, }, -#ifdef CONFIG_USART2_RXDMA +# ifdef CONFIG_USART2_RXDMA .ops = &g_uart_rxdma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart2priv, }; #endif diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c index f70dff06fa..fce42793d0 100644 --- a/arch/arm/src/samv7/sam_spi.c +++ b/arch/arm/src/samv7/sam_spi.c @@ -204,7 +204,7 @@ struct sam_spidev_s static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value, uint32_t address); #else -# define spi_checkreg(spi,wr,value,address) (false) +# define spi_checkreg(spi,wr,value,address) (false) #endif static inline uint32_t spi_getreg(struct sam_spidev_s *spi, @@ -216,7 +216,7 @@ static inline struct sam_spidev_s *spi_device(struct sam_spics_s *spics); #ifdef CONFIG_DEBUG_SPI_INFO static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg); #else -# define spi_dumpregs(spi,msg) +# define spi_dumpregs(spi,msg) #endif static inline void spi_flush(struct sam_spidev_s *spi); diff --git a/arch/arm/src/samv7/sam_spi_slave.c b/arch/arm/src/samv7/sam_spi_slave.c index 4cab3a5bbc..2b8a2a560b 100644 --- a/arch/arm/src/samv7/sam_spi_slave.c +++ b/arch/arm/src/samv7/sam_spi_slave.c @@ -116,7 +116,7 @@ struct sam_spidev_s static bool spi_checkreg(struct sam_spidev_s *priv, bool wr, uint32_t value, uint32_t address); #else -# define spi_checkreg(priv,wr,value,address) (false) +# define spi_checkreg(priv,wr,value,address) (false) #endif static uint32_t spi_getreg(struct sam_spidev_s *priv, @@ -127,7 +127,7 @@ static void spi_putreg(struct sam_spidev_s *priv, uint32_t value, #ifdef CONFIG_DEBUG_SPI_INFO static void spi_dumpregs(struct sam_spidev_s *priv, const char *msg); #else -# define spi_dumpregs(priv,msg) +# define spi_dumpregs(priv,msg) #endif /* Interrupt Handling */ diff --git a/arch/arm/src/samv7/sam_ssc.c b/arch/arm/src/samv7/sam_ssc.c index 071be7bc33..21a95dd381 100644 --- a/arch/arm/src/samv7/sam_ssc.c +++ b/arch/arm/src/samv7/sam_ssc.c @@ -470,7 +470,7 @@ struct sam_ssc_s static bool ssc_checkreg(struct sam_ssc_s *priv, bool wr, uint32_t regval, uint32_t regaddr); #else -# define ssc_checkreg(priv,wr,regval,regaddr) (false) +# define ssc_checkreg(priv,wr,regval,regaddr) (false) #endif static inline uint32_t ssc_getreg(struct sam_ssc_s *priv, diff --git a/arch/arm/src/samv7/sam_twihs.c b/arch/arm/src/samv7/sam_twihs.c index 133ba88313..1be6385ab8 100644 --- a/arch/arm/src/samv7/sam_twihs.c +++ b/arch/arm/src/samv7/sam_twihs.c @@ -190,9 +190,9 @@ static uint32_t twi_getabs(struct twi_dev_s *priv, uintptr_t address); static void twi_putabs(struct twi_dev_s *priv, uintptr_t address, uint32_t value); #else -# define twi_checkreg(priv,wr,value,address) (false) -# define twi_putabs(p,a,v) putreg32(v,a) -# define twi_getabs(p,a) getreg32(a) +# define twi_checkreg(priv,wr,value,address) (false) +# define twi_putabs(p,a,v) putreg32(v,a) +# define twi_getabs(p,a) getreg32(a) #endif static inline uint32_t twi_getrel(struct twi_dev_s *priv, diff --git a/arch/arm/src/samv7/sam_usbdevhs.c b/arch/arm/src/samv7/sam_usbdevhs.c index eb3036d3c2..53ff40e01a 100644 --- a/arch/arm/src/samv7/sam_usbdevhs.c +++ b/arch/arm/src/samv7/sam_usbdevhs.c @@ -455,7 +455,7 @@ static void sam_dumpep(struct sam_usbdev_s *priv, int epno); #else static inline uint32_t sam_getreg(uintptr_t regaddr); static inline void sam_putreg(uint32_t regval, uintptr_t regaddr); -# define sam_dumpep(priv,epno) +# define sam_dumpep(priv,epno) #endif /* Suspend/Resume Helpers ***************************************************/ diff --git a/arch/arm/src/samv7/sam_wdt.c b/arch/arm/src/samv7/sam_wdt.c index 52bf87bc15..26df5d5282 100644 --- a/arch/arm/src/samv7/sam_wdt.c +++ b/arch/arm/src/samv7/sam_wdt.c @@ -102,8 +102,8 @@ struct sam_lowerhalf_s static uint32_t sam_getreg(uintptr_t regaddr); static void sam_putreg(uint32_t regval, uintptr_t regaddr); #else -# define sam_getreg(regaddr) getreg32(regaddr) -# define sam_putreg(regval,regaddr) putreg32(regval,regaddr) +# define sam_getreg(regaddr) getreg32(regaddr) +# define sam_putreg(regval,regaddr) putreg32(regval,regaddr) #endif /* Interrupt handling *******************************************************/ diff --git a/arch/arm/src/stm32/hardware/stm32_eth.h b/arch/arm/src/stm32/hardware/stm32_eth.h index 438b2a04bc..402a728e96 100644 --- a/arch/arm/src/stm32/hardware/stm32_eth.h +++ b/arch/arm/src/stm32/hardware/stm32_eth.h @@ -784,9 +784,9 @@ #define ETH_RDES4_IPPT_SHIFT (0) /* Bits 0-2: IP payload type */ #define ETH_RDES4_IPPT_MASK (7 << ETH_RDES4_IPPT_SHIFT) -# define ETH_RDES4_IPPT_UDP (1 << ETH_RDES4_IPPT_SHIFT) /* UDP payload in IP datagram */ -# define ETH_RDES4_IPPT_TCP (2 << ETH_RDES4_IPPT_SHIFT) /* TCP payload in IP datagram */ -# define ETH_RDES4_IPPT_ICMP (3 << ETH_RDES4_IPPT_SHIFT) /* ICMP payload in IP datagram */ +# define ETH_RDES4_IPPT_UDP (1 << ETH_RDES4_IPPT_SHIFT) /* UDP payload in IP datagram */ +# define ETH_RDES4_IPPT_TCP (2 << ETH_RDES4_IPPT_SHIFT) /* TCP payload in IP datagram */ +# define ETH_RDES4_IPPT_ICMP (3 << ETH_RDES4_IPPT_SHIFT) /* ICMP payload in IP datagram */ #define ETH_RDES4_IPHE (1 << 3) /* Bit 3: IP header error */ #define ETH_RDES4_IPPE (1 << 4) /* Bit 4: IP payload error */ diff --git a/arch/arm/src/stm32/hardware/stm32_lcd.h b/arch/arm/src/stm32/hardware/stm32_lcd.h index 840da1de7a..4f12393e64 100644 --- a/arch/arm/src/stm32/hardware/stm32_lcd.h +++ b/arch/arm/src/stm32/hardware/stm32_lcd.h @@ -100,11 +100,11 @@ #define LCD_CR_VSEL (1 << 1) /* Bit 1: Voltage source selection */ #define LCD_CR_DUTY_SHIFT (2) /* Bits 2-4: Duty selection */ #define LCD_CR_DUTY_MASK (7 << LCD_CR_DUTY_SHIFT) -# define LCD_CR_DUTY_STATIC (0 << LCD_CR_DUTY_SHIFT) /* 000: Static duty */ -# define LCD_CR_DUTY_1TO2 (1 << LCD_CR_DUTY_SHIFT) /* 001: 1/2 duty */ -# define LCD_CR_DUTY_1TO3 (2 << LCD_CR_DUTY_SHIFT) /* 010: 1/3 duty */ -# define LCD_CR_DUTY_1TO4 (3 << LCD_CR_DUTY_SHIFT) /* 011: 1/4 duty */ -# define LCD_CR_DUTY_1TO8 (4 << LCD_CR_DUTY_SHIFT) /* 100: 1/8 duty */ +# define LCD_CR_DUTY_STATIC (0 << LCD_CR_DUTY_SHIFT) /* 000: Static duty */ +# define LCD_CR_DUTY_1TO2 (1 << LCD_CR_DUTY_SHIFT) /* 001: 1/2 duty */ +# define LCD_CR_DUTY_1TO3 (2 << LCD_CR_DUTY_SHIFT) /* 010: 1/3 duty */ +# define LCD_CR_DUTY_1TO4 (3 << LCD_CR_DUTY_SHIFT) /* 011: 1/4 duty */ +# define LCD_CR_DUTY_1TO8 (4 << LCD_CR_DUTY_SHIFT) /* 100: 1/8 duty */ #define LCD_CR_BIAS_SHIFT (5) /* Bits 5-6: Bias selector */ #define LCD_CR_BIAS_MASK (3 << LCD_CR_BIAS_SHIFT) diff --git a/arch/arm/src/stm32/hardware/stm32_pwr.h b/arch/arm/src/stm32/hardware/stm32_pwr.h index 9e59160367..7a4777256e 100644 --- a/arch/arm/src/stm32/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32/hardware/stm32_pwr.h @@ -72,7 +72,7 @@ # define PWR_CR_2p7V (5 << PWR_CR_PLS_SHIFT) /* 101: 2.7V */ # define PWR_CR_2p8V (6 << PWR_CR_PLS_SHIFT) /* 110: 2.8V */ # define PWR_CR_2p9V (7 << PWR_CR_PLS_SHIFT) /* 111: 2.9V */ -# endif +# endif #define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/stm32/stm32_dac.c index 2220a8d3a5..782b24e95e 100644 --- a/arch/arm/src/stm32/stm32_dac.c +++ b/arch/arm/src/stm32/stm32_dac.c @@ -129,33 +129,33 @@ #if defined(CONFIG_STM32_DAC1CH1_DMA) || defined(CONFIG_STM32_DAC1CH2_DMA) || \ defined(CONFIG_STM32_DAC2CH1_DMA) -# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) -# ifndef CONFIG_STM32_DMA2 -# warning "STM32 F1/F3 DAC DMA support requires CONFIG_STM32_DMA2" -# undef CONFIG_STM32_DAC1CH1_DMA -# undef CONFIG_STM32_DAC1CH2_DMA -# undef CONFIG_STM32_DAC2CH1_DMA -# endif -# elif defined(CONFIG_STM32_STM32F33XX) -# ifndef CONFIG_STM32_DMA1 -# warning "STM32 F334 DAC DMA support requires CONFIG_STM32_DMA1" -# undef CONFIG_STM32_DAC1CH1_DMA -# undef CONFIG_STM32_DAC1CH2_DMA -# undef CONFIG_STM32_DAC2CH1_DMA -# endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# ifndef CONFIG_STM32_DMA1 -# warning "STM32 F4 DAC DMA support requires CONFIG_STM32_DMA1" -# undef CONFIG_STM32_DAC1CH1_DMA -# undef CONFIG_STM32_DAC1CH2_DMA -# undef CONFIG_STM32_DAC2CH1_DMA -# endif -# else -# warning "No DAC DMA information for this STM32 family" -# undef CONFIG_STM32_DAC1CH1_DMA -# undef CONFIG_STM32_DAC1CH2_DMA -# undef CONFIG_STM32_DAC2CH1_DMA -# endif +# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) +# ifndef CONFIG_STM32_DMA2 +# warning "STM32 F1/F3 DAC DMA support requires CONFIG_STM32_DMA2" +# undef CONFIG_STM32_DAC1CH1_DMA +# undef CONFIG_STM32_DAC1CH2_DMA +# undef CONFIG_STM32_DAC2CH1_DMA +# endif +# elif defined(CONFIG_STM32_STM32F33XX) +# ifndef CONFIG_STM32_DMA1 +# warning "STM32 F334 DAC DMA support requires CONFIG_STM32_DMA1" +# undef CONFIG_STM32_DAC1CH1_DMA +# undef CONFIG_STM32_DAC1CH2_DMA +# undef CONFIG_STM32_DAC2CH1_DMA +# endif +# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# ifndef CONFIG_STM32_DMA1 +# warning "STM32 F4 DAC DMA support requires CONFIG_STM32_DMA1" +# undef CONFIG_STM32_DAC1CH1_DMA +# undef CONFIG_STM32_DAC1CH2_DMA +# undef CONFIG_STM32_DAC2CH1_DMA +# endif +# else +# warning "No DAC DMA information for this STM32 family" +# undef CONFIG_STM32_DAC1CH1_DMA +# undef CONFIG_STM32_DAC1CH2_DMA +# undef CONFIG_STM32_DAC2CH1_DMA +# endif #endif #if defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG1) || defined(CONFIG_STM32_DAC1CH1_HRTIM_TRG2) @@ -220,10 +220,10 @@ #undef HAVE_DMA #if defined(CONFIG_STM32_DAC1CH1_DMA) || defined(CONFIG_STM32_DAC1CH2_DMA) || \ defined(CONFIG_STM32_DAC2CH1_DMA) -# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ - defined(CONFIG_STM32_STM32F33XX) -# define HAVE_DMA 1 -# define DAC_DMA 2 +# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F33XX) +# define HAVE_DMA 1 +# define DAC_DMA 2 # if defined(CONFIG_STM32_DAC1CH1) && !defined(CONFIG_STM32_DAC1CH1_DMA_EXTERNAL) # define DAC1CH1_DMA_CHAN DMACHAN_DAC1_CH1 # endif @@ -233,19 +233,19 @@ # if defined(CONFIG_STM32_DAC2CH1) && !defined(CONFIG_STM32_DAC2CH1_DMA_EXTERNAL) # define DAC2CH1_DMA_CHAN DMACHAN_DAC2_CH1 # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -# define HAVE_DMA 1 -# define DAC_DMA 1 -# if defined(CONFIG_STM32_DAC1CH1) && !defined(CONFIG_STM32_DAC1CH1_DMA_EXTERNAL) -# define DAC1CH1_DMA_CHAN DMAMAP_DAC1 +# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# define HAVE_DMA 1 +# define DAC_DMA 1 +# if defined(CONFIG_STM32_DAC1CH1) && !defined(CONFIG_STM32_DAC1CH1_DMA_EXTERNAL) +# define DAC1CH1_DMA_CHAN DMAMAP_DAC1 +# endif +# if defined(CONFIG_STM32_DAC1CH2) && !defined(CONFIG_STM32_DAC1CH2_DMA_EXTERNAL) +# define DAC1CH2_DMA_CHAN DMAMAP_DAC1 +# endif +# if defined(CONFIG_STM32_DAC2CH1) && !defined(CONFIG_STM32_DAC2CH1_DMA_EXTERNAL) +# define DAC2CH1_DMA_CHAN DMAMAP_DAC2 +# endif # endif -# if defined(CONFIG_STM32_DAC1CH2) && !defined(CONFIG_STM32_DAC1CH2_DMA_EXTERNAL) -# define DAC1CH2_DMA_CHAN DMAMAP_DAC1 -# endif -# if defined(CONFIG_STM32_DAC2CH1) && !defined(CONFIG_STM32_DAC2CH1_DMA_EXTERNAL) -# define DAC2CH1_DMA_CHAN DMAMAP_DAC2 -# endif -# endif #endif /* Timer configuration. The STM32 supports 8 different trigger for DAC diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/stm32/stm32_eth.c index 1b7b93b109..149dcaf0a6 100644 --- a/arch/arm/src/stm32/stm32_eth.c +++ b/arch/arm/src/stm32/stm32_eth.c @@ -665,9 +665,9 @@ static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); #else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(val,addr) putreg32(val,addr) -# define stm32_checksetup() +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) +# define stm32_checksetup() #endif /* Free buffer management */ @@ -3365,7 +3365,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the MII interface */ -#if defined(CONFIG_STM32_MII) +# if defined(CONFIG_STM32_MII) /* Select the MII interface */ @@ -3380,7 +3380,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32_MII_MCO1) +# if defined(CONFIG_STM32_MII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3388,7 +3388,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32_MII_MCO2) +# elif defined(CONFIG_STM32_MII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3396,12 +3396,12 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32_MII_MCO) +# elif defined(CONFIG_STM32_MII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); stm32_mcoconfig(BOARD_CFGR_MCO_SOURCE); -# endif +# endif /* MII interface pins (17): * @@ -3427,7 +3427,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the RMII interface. */ -#elif defined(CONFIG_STM32_RMII) +# elif defined(CONFIG_STM32_RMII) /* Select the RMII interface */ @@ -3442,7 +3442,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32_RMII_MCO1) +# if defined(CONFIG_STM32_RMII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3450,7 +3450,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32_RMII_MCO2) +# elif defined(CONFIG_STM32_RMII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3458,12 +3458,12 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32_RMII_MCO) +# elif defined(CONFIG_STM32_RMII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); stm32_mcoconfig(BOARD_CFGR_MCO_SOURCE); -# endif +# endif /* RMII interface pins (7): * @@ -3479,7 +3479,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_ETH_RMII_TXD1); stm32_configgpio(GPIO_ETH_RMII_TX_EN); -#endif +# endif #endif #ifdef CONFIG_STM32_ETH_PTP diff --git a/arch/arm/src/stm32/stm32_hciuart.c b/arch/arm/src/stm32/stm32_hciuart.c index 788a1733b7..d9d34906f4 100644 --- a/arch/arm/src/stm32/stm32_hciuart.c +++ b/arch/arm/src/stm32/stm32_hciuart.c @@ -189,7 +189,7 @@ DMA_CCR_PSIZE_8BITS | \ DMA_CCR_MSIZE_8BITS | \ CONFIG_STM32_HCIUART_RXDMAPRIO) -# endif +# endif #endif /* All interrupts */ @@ -352,9 +352,9 @@ static int hciuart_pm_prepare(struct pm_callback_s *cb, int domain, static uint8_t g_usart1_rxbuffer[CONFIG_STM32_HCIUART1_RXBUFSIZE]; static uint8_t g_usart1_txbuffer[CONFIG_STM32_HCIUART1_TXBUFSIZE]; -# ifdef CONFIG_STM32_HCIUART1_RXDMA +# ifdef CONFIG_STM32_HCIUART1_RXDMA static uint8_t g_usart1_rxdmabuffer[RXDMA_BUFFER_SIZE]; -# endif +# endif /* HCI USART1 variable state information */ @@ -381,26 +381,26 @@ static const struct hciuart_config_s g_hciusart1_config = .rxbuffer = g_usart1_rxbuffer, .txbuffer = g_usart1_txbuffer, -#ifdef CONFIG_STM32_HCIUART1_RXDMA +# ifdef CONFIG_STM32_HCIUART1_RXDMA .rxdmabuffer = g_usart1_rxdmabuffer, -#endif +# endif .rxbufsize = CONFIG_STM32_HCIUART1_RXBUFSIZE, .txbufsize = CONFIG_STM32_HCIUART1_TXBUFSIZE, -#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW +# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART1_RXBUFSIZE), .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART1_RXBUFSIZE), -#endif -#ifdef CONFIG_STM32_HCIUART_RXDMA +# endif +# ifdef CONFIG_STM32_HCIUART_RXDMA .rxdmachan = DMAMAP_USART1_RX, -#endif +# endif .irq = STM32_IRQ_USART1, .baud = CONFIG_STM32_HCIUART1_BAUD, -#if defined(CONFIG_STM32_STM32F33XX) +# if defined(CONFIG_STM32_STM32F33XX) .apbclock = STM32_PCLK1_FREQUENCY, /* Errata 2.5.1 */ -#else +# else .apbclock = STM32_PCLK2_FREQUENCY, -#endif +# endif .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, @@ -416,9 +416,9 @@ static const struct hciuart_config_s g_hciusart1_config = static uint8_t g_usart2_rxbuffer[CONFIG_STM32_HCIUART2_RXBUFSIZE]; static uint8_t g_usart2_txbuffer[CONFIG_STM32_HCIUART2_TXBUFSIZE]; -# ifdef CONFIG_STM32_HCIUART2_RXDMA +# ifdef CONFIG_STM32_HCIUART2_RXDMA static uint8_t g_usart2_rxdmabuffer[RXDMA_BUFFER_SIZE]; -# endif +# endif /* HCI USART2 variable state information */ @@ -445,18 +445,18 @@ static const struct hciuart_config_s g_hciusart2_config = .rxbuffer = g_usart2_rxbuffer, .txbuffer = g_usart2_txbuffer, -#ifdef CONFIG_STM32_HCIUART2_RXDMA +# ifdef CONFIG_STM32_HCIUART2_RXDMA .rxdmabuffer = g_usart2_rxdmabuffer, -#endif +# endif .rxbufsize = CONFIG_STM32_HCIUART2_RXBUFSIZE, .txbufsize = CONFIG_STM32_HCIUART2_TXBUFSIZE, -#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW +# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART2_RXBUFSIZE), .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART2_RXBUFSIZE), -#endif -#ifdef CONFIG_STM32_HCIUART_RXDMA +# endif +# ifdef CONFIG_STM32_HCIUART_RXDMA .rxdmachan = DMAMAP_USART2_RX, -#endif +# endif .irq = STM32_IRQ_USART2, .baud = CONFIG_STM32_HCIUART2_BAUD, @@ -476,9 +476,9 @@ static const struct hciuart_config_s g_hciusart2_config = static uint8_t g_usart3_rxbuffer[CONFIG_STM32_HCIUART3_RXBUFSIZE]; static uint8_t g_usart3_txbuffer[CONFIG_STM32_HCIUART3_TXBUFSIZE]; -#ifdef CONFIG_STM32_HCIUART3_RXDMA +# ifdef CONFIG_STM32_HCIUART3_RXDMA static uint8_t g_usart3_rxdmabuffer[RXDMA_BUFFER_SIZE]; -#endif +# endif /* HCI USART3 variable state information */ @@ -505,18 +505,18 @@ static const struct hciuart_config_s g_hciusart3_config = .rxbuffer = g_usart3_rxbuffer, .txbuffer = g_usart3_txbuffer, -#ifdef CONFIG_STM32_HCIUART3_RXDMA +# ifdef CONFIG_STM32_HCIUART3_RXDMA .rxdmabuffer = g_usart3_rxdmabuffer, -#endif +# endif .rxbufsize = CONFIG_STM32_HCIUART3_RXBUFSIZE, .txbufsize = CONFIG_STM32_HCIUART3_TXBUFSIZE, -#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW +# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART3_RXBUFSIZE), .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART3_RXBUFSIZE), -#endif -#ifdef CONFIG_STM32_HCIUART_RXDMA +# endif +# ifdef CONFIG_STM32_HCIUART_RXDMA .rxdmachan = DMAMAP_USART3_RX, -#endif +# endif .irq = STM32_IRQ_USART3, .baud = CONFIG_STM32_HCIUART3_BAUD, @@ -534,13 +534,11 @@ static const struct hciuart_config_s g_hciusart3_config = #ifdef CONFIG_STM32_USART6_HCIUART /* I/O buffers */ -#ifdef CONFIG_STM32_USART6_HCIUART static uint8_t g_usart6_rxbuffer[CONFIG_STM32_HCIUART6_RXBUFSIZE]; static uint8_t g_usart6_txbuffer[CONFIG_STM32_HCIUART6_TXBUFSIZE]; -# ifdef CONFIG_STM32_HCIUART6_RXDMA +# ifdef CONFIG_STM32_HCIUART6_RXDMA static uint8_t g_usart6_rxdmabuffer[RXDMA_BUFFER_SIZE]; -# endif -#endif +# endif /* HCI USART6 variable state information */ @@ -567,18 +565,18 @@ static const struct hciuart_config_s g_hciusart6_config = .rxbuffer = g_usart6_rxbuffer, .txbuffer = g_usart6_txbuffer, -#ifdef CONFIG_STM32_HCIUART6_RXDMA +# ifdef CONFIG_STM32_HCIUART6_RXDMA .rxdmabuffer = g_usart6_rxdmabuffer, -#endif +# endif .rxbufsize = CONFIG_STM32_HCIUART6_RXBUFSIZE, .txbufsize = CONFIG_STM32_HCIUART6_TXBUFSIZE, -#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW +# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART6_RXBUFSIZE), .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART6_RXBUFSIZE), -#endif -#ifdef CONFIG_STM32_HCIUART_RXDMA +# endif +# ifdef CONFIG_STM32_HCIUART_RXDMA .rxdmachan = DMAMAP_USART6_RX, -#endif +# endif .irq = STM32_IRQ_USART6, .baud = CONFIG_STM32_HCIUART6_BAUD, @@ -598,9 +596,9 @@ static const struct hciuart_config_s g_hciusart6_config = static uint8_t g_uart7_rxbuffer[CONFIG_STM32_HCIUART7_RXBUFSIZE]; static uint8_t g_uart7_txbuffer[CONFIG_STM32_HCIUART7_TXBUFSIZE]; -#ifdef CONFIG_STM32_HCIUART7_RXDMA +# ifdef CONFIG_STM32_HCIUART7_RXDMA static uint8_t g_uart7_rxdmabuffer[RXDMA_BUFFER_SIZE]; -#endif +# endif /* HCI UART7 variable state information */ @@ -627,18 +625,18 @@ static const struct hciuart_config_s g_hciuart7_config = .rxbuffer = g_uart7_rxbuffer, .txbuffer = g_uart7_txbuffer, -#ifdef CONFIG_STM32_HCIUART7_RXDMA +# ifdef CONFIG_STM32_HCIUART7_RXDMA .rxdmabuffer = g_uart7_rxdmabuffer, -#endif +# endif .rxbufsize = CONFIG_STM32_HCIUART7_RXBUFSIZE, .txbufsize = CONFIG_STM32_HCIUART7_TXBUFSIZE, -#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW +# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART7_RXBUFSIZE), .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART7_RXBUFSIZE), -#endif -#ifdef CONFIG_STM32_HCIUART_RXDMA +# endif +# ifdef CONFIG_STM32_HCIUART_RXDMA .rxdmachan = DMAMAP_UART7_RX, -#endif +# endif .irq = STM32_IRQ_UART7, .baud = CONFIG_STM32_HCIUART7_BAUD, @@ -658,9 +656,9 @@ static const struct hciuart_config_s g_hciuart7_config = static uint8_t g_uart8_rxbuffer[CONFIG_STM32_HCIUART8_RXBUFSIZE]; static uint8_t g_uart8_txbuffer[CONFIG_STM32_HCIUART8_TXBUFSIZE]; -#ifdef CONFIG_STM32_HCIUART8_RXDMA +# ifdef CONFIG_STM32_HCIUART8_RXDMA static uint8_t g_uart8_rxdmabuffer[RXDMA_BUFFER_SIZE]; -#endif +# endif /* HCI UART8 variable state information */ @@ -687,18 +685,18 @@ static const struct hciuart_config_s g_hciuart8_config = .rxbuffer = g_uart8_rxbuffer, .txbuffer = g_uart8_txbuffer, -#ifdef CONFIG_STM32_HCIUART8_RXDMA +# ifdef CONFIG_STM32_HCIUART8_RXDMA .rxdmabuffer = g_uart8_rxdmabuffer, -#endif +# endif .rxbufsize = CONFIG_STM32_HCIUART8_RXBUFSIZE, .txbufsize = CONFIG_STM32_HCIUART8_TXBUFSIZE, -#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW +# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW .rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART8_RXBUFSIZE), .rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART8_RXBUFSIZE), -#endif -#ifdef CONFIG_STM32_HCIUART_RXDMA +# endif +# ifdef CONFIG_STM32_HCIUART_RXDMA .rxdmachan = DMAMAP_UART8_RX, -#endif +# endif .irq = STM32_IRQ_UART8, .baud = CONFIG_STM32_HCIUART8_BAUD, diff --git a/arch/arm/src/stm32/stm32_i2s.c b/arch/arm/src/stm32/stm32_i2s.c index c9dadf6bc2..d2e09b71b8 100644 --- a/arch/arm/src/stm32/stm32_i2s.c +++ b/arch/arm/src/stm32/stm32_i2s.c @@ -323,7 +323,7 @@ struct stm32_i2s_s static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, uint16_t regval, uint32_t regaddr); #else -# define i2s_checkreg(priv,wr,regval,regaddr) (false) +# define i2s_checkreg(priv,wr,regval,regaddr) (false) #endif static inline uint16_t i2s_getreg(struct stm32_i2s_s *priv, uint8_t offset); diff --git a/arch/arm/src/stm32/stm32_iwdg.c b/arch/arm/src/stm32/stm32_iwdg.c index 425aa343e8..77fa9f1101 100644 --- a/arch/arm/src/stm32/stm32_iwdg.c +++ b/arch/arm/src/stm32/stm32_iwdg.c @@ -128,8 +128,8 @@ struct stm32_lowerhalf_s static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); #else -# define stm32_getreg(addr) getreg16(addr) -# define stm32_putreg(val,addr) putreg16(val,addr) +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) #endif static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv); diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c index 4969707df9..1af7cb48a1 100644 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/arch/arm/src/stm32/stm32_otgfsdev.c @@ -505,8 +505,8 @@ struct stm32_usbdev_s static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); #else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(val,addr) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) #endif /* Request queue operations *************************************************/ @@ -5366,9 +5366,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = OTGFS_GCCFG_PWRDWN; -# ifdef CONFIG_USBDEV_VBUSSENSING +# ifdef CONFIG_USBDEV_VBUSSENSING regval |= OTGFS_GCCFG_VBDEN; -# endif +# endif #else /* In the case of the all others the meaning of the bit is No VBUS @@ -5377,12 +5377,12 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = (OTGFS_GCCFG_PWRDWN | OTGFS_GCCFG_VBUSASEN | OTGFS_GCCFG_VBUSBSEN); -# ifndef CONFIG_USBDEV_VBUSSENSING +# ifndef CONFIG_USBDEV_VBUSSENSING regval |= OTGFS_GCCFG_NOVBUSSENS; -# endif -# ifdef CONFIG_STM32_OTGFS_SOFOUTPUT +# endif +# ifdef CONFIG_STM32_OTGFS_SOFOUTPUT regval |= OTGFS_GCCFG_SOFOUTEN; -# endif +# endif #endif stm32_putreg(regval, STM32_OTGFS_GCCFG); up_mdelay(20); @@ -5392,11 +5392,11 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) */ #if defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) -# ifndef CONFIG_USBDEV_VBUSSENSING +# ifndef CONFIG_USBDEV_VBUSSENSING regval = stm32_getreg(STM32_OTGFS_GOTGCTL); regval |= (OTGFS_GOTGCTL_BVALOEN | OTGFS_GOTGCTL_BVALOVAL); stm32_putreg(regval, STM32_OTGFS_GOTGCTL); -# endif +# endif #endif /* Force Device Mode */ diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/stm32/stm32_otgfshost.c index f7513c3906..f328b28b6e 100644 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ b/arch/arm/src/stm32/stm32_otgfshost.c @@ -275,8 +275,8 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t addr, uint32_t value); #else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(addr,val) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(addr,val) putreg32(val,addr) #endif static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/stm32/stm32_otghsdev.c index 1b166047bd..cbbb251c88 100644 --- a/arch/arm/src/stm32/stm32_otghsdev.c +++ b/arch/arm/src/stm32/stm32_otghsdev.c @@ -455,8 +455,8 @@ struct stm32_usbdev_s static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); #else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(val,addr) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) #endif /* Request queue operations *************************************************/ diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/stm32/stm32_otghshost.c index be55ad985a..ca6f045904 100644 --- a/arch/arm/src/stm32/stm32_otghshost.c +++ b/arch/arm/src/stm32/stm32_otghshost.c @@ -280,8 +280,8 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t addr, uint32_t value); #else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(addr,val) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(addr,val) putreg32(val,addr) #endif static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32/stm32_rcc.c index 850ac21ed5..dcebf6e36d 100644 --- a/arch/arm/src/stm32/stm32_rcc.c +++ b/arch/arm/src/stm32/stm32_rcc.c @@ -82,11 +82,11 @@ ****************************************************************************/ #if defined(CONFIG_STM32_STM32L15XX) -# define STM32_RCC_XXX STM32_RCC_CSR -# define RCC_XXX_YYYRST RCC_CSR_RTCRST +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST #else -# define STM32_RCC_XXX STM32_RCC_BDCR -# define RCC_XXX_YYYRST RCC_BDCR_BDRST +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST #endif /**************************************************************************** diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index 0b5552f331..ccc53df7b8 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -216,7 +216,7 @@ DMA_CCR_PSIZE_8BITS | \ DMA_CCR_MSIZE_8BITS | \ CONFIG_USART_RXDMAPRIO) -# endif +# endif #endif /* SERIAL_HAVE_RXDMA */ @@ -634,65 +634,65 @@ static const struct uart_ops_s g_uart_txdma_ops = #ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; -# ifdef CONFIG_USART1_RXDMA +# ifdef CONFIG_USART1_RXDMA static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; -# ifdef CONFIG_USART2_RXDMA +# ifdef CONFIG_USART2_RXDMA static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; -# ifdef CONFIG_USART3_RXDMA +# ifdef CONFIG_USART3_RXDMA static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; -# ifdef CONFIG_UART4_RXDMA +# ifdef CONFIG_UART4_RXDMA static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; -# ifdef CONFIG_UART5_RXDMA +# ifdef CONFIG_UART5_RXDMA static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32_USART6_SERIALDRIVER static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; static char g_usart6txbuffer[CONFIG_USART6_TXBUFSIZE]; -# ifdef CONFIG_USART6_RXDMA +# ifdef CONFIG_USART6_RXDMA static char g_usart6rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32_UART7_SERIALDRIVER static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; static char g_uart7txbuffer[CONFIG_UART7_TXBUFSIZE]; -# ifdef CONFIG_UART7_RXDMA +# ifdef CONFIG_UART7_RXDMA static char g_uart7rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32_UART8_SERIALDRIVER static char g_uart8rxbuffer[CONFIG_UART8_RXBUFSIZE]; static char g_uart8txbuffer[CONFIG_UART8_TXBUFSIZE]; -# ifdef CONFIG_UART8_RXDMA +# ifdef CONFIG_UART8_RXDMA static char g_uart8rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif /* This describes the state of the STM32 USART1 ports. */ @@ -702,9 +702,9 @@ static struct up_dev_s g_usart1priv = { .dev = { -#if CONSOLE_UART == 1 +# if CONSOLE_UART == 1 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART1_RXBUFSIZE, @@ -715,15 +715,15 @@ static struct up_dev_s g_usart1priv = .size = CONFIG_USART1_TXBUFSIZE, .buffer = g_usart1txbuffer, }, -#if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA) +# if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA) .ops = &g_uart_rxtxdma_ops, -#elif defined(CONFIG_USART1_RXDMA) && !defined(CONFIG_USART1_TXDMA) +# elif defined(CONFIG_USART1_RXDMA) && !defined(CONFIG_USART1_TXDMA) .ops = &g_uart_rxdma_ops, -#elif !defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA) +# elif !defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA) .ops = &g_uart_txdma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart1priv, }, @@ -732,38 +732,38 @@ static struct up_dev_s g_usart1priv = .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, -#if defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F302) +# if defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F302) .apbclock = STM32_PCLK1_FREQUENCY, /* Errata 2.5.1 */ -#else +# else .apbclock = STM32_PCLK2_FREQUENCY, -#endif +# endif .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART1_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART1_RTS, -#endif -#ifdef CONFIG_USART1_TXDMA +# endif +# ifdef CONFIG_USART1_TXDMA .txdma_channel = DMAMAP_USART1_TX, -#endif -#ifdef CONFIG_USART1_RXDMA +# endif +# ifdef CONFIG_USART1_RXDMA .rxdma_channel = DMAMAP_USART1_RX, .rxfifo = g_usart1rxfifo, -#endif - -#ifdef CONFIG_USART1_RS485 - .rs485_dir_gpio = GPIO_USART1_RS485_DIR, -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART1_RS485 + .rs485_dir_gpio = GPIO_USART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -774,9 +774,9 @@ static struct up_dev_s g_usart2priv = { .dev = { -#if CONSOLE_UART == 2 +# if CONSOLE_UART == 2 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART2_RXBUFSIZE, @@ -787,15 +787,15 @@ static struct up_dev_s g_usart2priv = .size = CONFIG_USART2_TXBUFSIZE, .buffer = g_usart2txbuffer, }, -#if defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA) +# if defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA) .ops = &g_uart_rxtxdma_ops, -#elif defined(CONFIG_USART2_RXDMA) && !defined(CONFIG_USART2_TXDMA) +# elif defined(CONFIG_USART2_RXDMA) && !defined(CONFIG_USART2_TXDMA) .ops = &g_uart_rxdma_ops, -#elif !defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA) +# elif !defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA) .ops = &g_uart_txdma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart2priv, }, @@ -808,30 +808,30 @@ static struct up_dev_s g_usart2priv = .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART2_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART2_RTS, -#endif -#ifdef CONFIG_USART2_TXDMA +# endif +# ifdef CONFIG_USART2_TXDMA .txdma_channel = DMAMAP_USART2_TX, -#endif -#ifdef CONFIG_USART2_RXDMA +# endif +# ifdef CONFIG_USART2_RXDMA .rxdma_channel = DMAMAP_USART2_RX, .rxfifo = g_usart2rxfifo, -#endif - -#ifdef CONFIG_USART2_RS485 - .rs485_dir_gpio = GPIO_USART2_RS485_DIR, -# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART2_RS485 + .rs485_dir_gpio = GPIO_USART2_RS485_DIR, +# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -842,9 +842,9 @@ static struct up_dev_s g_usart3priv = { .dev = { -#if CONSOLE_UART == 3 +# if CONSOLE_UART == 3 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART3_RXBUFSIZE, @@ -855,15 +855,15 @@ static struct up_dev_s g_usart3priv = .size = CONFIG_USART3_TXBUFSIZE, .buffer = g_usart3txbuffer, }, -#if defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA) +# if defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA) .ops = &g_uart_rxtxdma_ops, -#elif defined(CONFIG_USART3_RXDMA) && !defined(CONFIG_USART3_TXDMA) +# elif defined(CONFIG_USART3_RXDMA) && !defined(CONFIG_USART3_TXDMA) .ops = &g_uart_rxdma_ops, -#elif !defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA) +# elif !defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA) .ops = &g_uart_txdma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart3priv, }, @@ -876,30 +876,30 @@ static struct up_dev_s g_usart3priv = .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART3_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART3_RTS, -#endif -#ifdef CONFIG_USART3_TXDMA +# endif +# ifdef CONFIG_USART3_TXDMA .txdma_channel = DMAMAP_USART3_TX, -#endif -#ifdef CONFIG_USART3_RXDMA +# endif +# ifdef CONFIG_USART3_RXDMA .rxdma_channel = DMAMAP_USART3_RX, .rxfifo = g_usart3rxfifo, -#endif - -#ifdef CONFIG_USART3_RS485 - .rs485_dir_gpio = GPIO_USART3_RS485_DIR, -# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART3_RS485 + .rs485_dir_gpio = GPIO_USART3_RS485_DIR, +# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -910,9 +910,9 @@ static struct up_dev_s g_uart4priv = { .dev = { -#if CONSOLE_UART == 4 +# if CONSOLE_UART == 4 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_UART4_RXBUFSIZE, @@ -923,15 +923,15 @@ static struct up_dev_s g_uart4priv = .size = CONFIG_UART4_TXBUFSIZE, .buffer = g_uart4txbuffer, }, -#if defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA) +# if defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA) .ops = &g_uart_rxtxdma_ops, -#elif defined(CONFIG_UART4_RXDMA) && !defined(CONFIG_UART4_TXDMA) +# elif defined(CONFIG_UART4_RXDMA) && !defined(CONFIG_UART4_TXDMA) .ops = &g_uart_rxdma_ops, -#elif !defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA) +# elif !defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA) .ops = &g_uart_txdma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart4priv, }, @@ -939,35 +939,35 @@ static struct up_dev_s g_uart4priv = .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_UART4_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART4_RTS, -#endif +# endif .baud = CONFIG_UART4_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, -#ifdef CONFIG_UART4_TXDMA +# ifdef CONFIG_UART4_TXDMA .txdma_channel = DMAMAP_UART4_TX, -#endif -#ifdef CONFIG_UART4_RXDMA +# endif +# ifdef CONFIG_UART4_RXDMA .rxdma_channel = DMAMAP_UART4_RX, .rxfifo = g_uart4rxfifo, -#endif - -#ifdef CONFIG_UART4_RS485 - .rs485_dir_gpio = GPIO_UART4_RS485_DIR, -# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_UART4_RS485 + .rs485_dir_gpio = GPIO_UART4_RS485_DIR, +# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -978,9 +978,9 @@ static struct up_dev_s g_uart5priv = { .dev = { -#if CONSOLE_UART == 5 +# if CONSOLE_UART == 5 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_UART5_RXBUFSIZE, @@ -991,15 +991,15 @@ static struct up_dev_s g_uart5priv = .size = CONFIG_UART5_TXBUFSIZE, .buffer = g_uart5txbuffer, }, -#if defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA) +# if defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA) .ops = &g_uart_rxtxdma_ops, -#elif defined(CONFIG_UART5_RXDMA) && !defined(CONFIG_UART5_TXDMA) +# elif defined(CONFIG_UART5_RXDMA) && !defined(CONFIG_UART5_TXDMA) .ops = &g_uart_rxdma_ops, -#elif !defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA) +# elif !defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA) .ops = &g_uart_txdma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart5priv, }, @@ -1007,35 +1007,35 @@ static struct up_dev_s g_uart5priv = .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_UART5_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART5_RTS, -#endif +# endif .baud = CONFIG_UART5_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, -#ifdef CONFIG_UART5_TXDMA +# ifdef CONFIG_UART5_TXDMA .txdma_channel = DMAMAP_UART5_TX, -#endif -#ifdef CONFIG_UART5_RXDMA +# endif +# ifdef CONFIG_UART5_RXDMA .rxdma_channel = DMAMAP_UART5_RX, .rxfifo = g_uart5rxfifo, -#endif - -#ifdef CONFIG_UART5_RS485 - .rs485_dir_gpio = GPIO_UART5_RS485_DIR, -# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_UART5_RS485 + .rs485_dir_gpio = GPIO_UART5_RS485_DIR, +# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -1046,9 +1046,9 @@ static struct up_dev_s g_usart6priv = { .dev = { -#if CONSOLE_UART == 6 +# if CONSOLE_UART == 6 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART6_RXBUFSIZE, @@ -1059,15 +1059,15 @@ static struct up_dev_s g_usart6priv = .size = CONFIG_USART6_TXBUFSIZE, .buffer = g_usart6txbuffer, }, -#if defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA) +# if defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA) .ops = &g_uart_rxtxdma_ops, -#elif defined(CONFIG_USART6_RXDMA) && !defined(CONFIG_USART6_TXDMA) +# elif defined(CONFIG_USART6_RXDMA) && !defined(CONFIG_USART6_TXDMA) .ops = &g_uart_rxdma_ops, -#elif !defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA) +# elif !defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA) .ops = &g_uart_txdma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart6priv, }, @@ -1080,30 +1080,30 @@ static struct up_dev_s g_usart6priv = .usartbase = STM32_USART6_BASE, .tx_gpio = GPIO_USART6_TX, .rx_gpio = GPIO_USART6_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART6_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART6_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART6_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART6_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART6_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART6_RTS, -#endif -#ifdef CONFIG_USART6_TXDMA +# endif +# ifdef CONFIG_USART6_TXDMA .txdma_channel = DMAMAP_USART6_TX, -#endif -#ifdef CONFIG_USART6_RXDMA +# endif +# ifdef CONFIG_USART6_RXDMA .rxdma_channel = DMAMAP_USART6_RX, .rxfifo = g_usart6rxfifo, -#endif - -#ifdef CONFIG_USART6_RS485 - .rs485_dir_gpio = GPIO_USART6_RS485_DIR, -# if (CONFIG_USART6_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART6_RS485 + .rs485_dir_gpio = GPIO_USART6_RS485_DIR, +# if (CONFIG_USART6_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -1114,9 +1114,9 @@ static struct up_dev_s g_uart7priv = { .dev = { -#if CONSOLE_UART == 7 +# if CONSOLE_UART == 7 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_UART7_RXBUFSIZE, @@ -1127,15 +1127,15 @@ static struct up_dev_s g_uart7priv = .size = CONFIG_UART7_TXBUFSIZE, .buffer = g_uart7txbuffer, }, -#if defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA) +# if defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA) .ops = &g_uart_rxtxdma_ops, -#elif defined(CONFIG_UART7_RXDMA) && !defined(CONFIG_UART7_TXDMA) +# elif defined(CONFIG_UART7_RXDMA) && !defined(CONFIG_UART7_TXDMA) .ops = &g_uart_rxdma_ops, -#elif !defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA) +# elif !defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA) .ops = &g_uart_txdma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart7priv, }, @@ -1148,30 +1148,30 @@ static struct up_dev_s g_uart7priv = .usartbase = STM32_UART7_BASE, .tx_gpio = GPIO_UART7_TX, .rx_gpio = GPIO_UART7_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART7_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART7_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_UART7_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART7_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART7_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART7_RTS, -#endif -#ifdef CONFIG_UART7_TXDMA +# endif +# ifdef CONFIG_UART7_TXDMA .txdma_channel = DMAMAP_UART7_TX, -#endif -#ifdef CONFIG_UART7_RXDMA +# endif +# ifdef CONFIG_UART7_RXDMA .rxdma_channel = DMAMAP_UART7_RX, .rxfifo = g_uart7rxfifo, -#endif - -#ifdef CONFIG_UART7_RS485 - .rs485_dir_gpio = GPIO_UART7_RS485_DIR, -# if (CONFIG_UART7_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_UART7_RS485 + .rs485_dir_gpio = GPIO_UART7_RS485_DIR, +# if (CONFIG_UART7_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -1182,9 +1182,9 @@ static struct up_dev_s g_uart8priv = { .dev = { -#if CONSOLE_UART == 8 +# if CONSOLE_UART == 8 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_UART8_RXBUFSIZE, @@ -1195,15 +1195,15 @@ static struct up_dev_s g_uart8priv = .size = CONFIG_UART8_TXBUFSIZE, .buffer = g_uart8txbuffer, }, -#if defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA) +# if defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA) .ops = &g_uart_rxtxdma_ops, -#elif defined(CONFIG_UART8_RXDMA) && !defined(CONFIG_UART8_TXDMA) +# elif defined(CONFIG_UART8_RXDMA) && !defined(CONFIG_UART8_TXDMA) .ops = &g_uart_rxdma_ops, -#elif !defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA) +# elif !defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA) .ops = &g_uart_txdma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart8priv, }, @@ -1216,30 +1216,30 @@ static struct up_dev_s g_uart8priv = .usartbase = STM32_UART8_BASE, .tx_gpio = GPIO_UART8_TX, .rx_gpio = GPIO_UART8_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART8_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART8_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_UART8_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART8_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART8_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART8_RTS, -#endif -#ifdef CONFIG_UART8_TXDMA +# endif +# ifdef CONFIG_UART8_TXDMA .txdma_channel = DMAMAP_UART8_TX, -#endif -#ifdef CONFIG_UART8_RXDMA +# endif +# ifdef CONFIG_UART8_RXDMA .rxdma_channel = DMAMAP_UART8_RX, .rxfifo = g_uart8rxfifo, -#endif - -#ifdef CONFIG_UART8_RS485 - .rs485_dir_gpio = GPIO_UART8_RS485_DIR, -# if (CONFIG_UART8_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_UART8_RS485 + .rs485_dir_gpio = GPIO_UART8_RS485_DIR, +# if (CONFIG_UART8_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif diff --git a/arch/arm/src/stm32/stm32_usbdev.c b/arch/arm/src/stm32/stm32_usbdev.c index 9a56acea35..1983684789 100644 --- a/arch/arm/src/stm32/stm32_usbdev.c +++ b/arch/arm/src/stm32/stm32_usbdev.c @@ -369,10 +369,10 @@ static void stm32_putreg(uint16_t val, uint32_t addr); static void stm32_checksetup(void); static void stm32_dumpep(int epno); #else -# define stm32_getreg(addr) getreg16(addr) -# define stm32_putreg(val,addr) putreg16(val,addr) -# define stm32_checksetup() -# define stm32_dumpep(epno) +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +# define stm32_checksetup() +# define stm32_dumpep(epno) #endif /* Low-Level Helpers ********************************************************/ diff --git a/arch/arm/src/stm32/stm32_usbfs.c b/arch/arm/src/stm32/stm32_usbfs.c index 3d5b717e8f..220b86b066 100644 --- a/arch/arm/src/stm32/stm32_usbfs.c +++ b/arch/arm/src/stm32/stm32_usbfs.c @@ -350,10 +350,10 @@ static void stm32_putreg(uint16_t val, uint32_t addr); static void stm32_checksetup(void); static void stm32_dumpep(int epno); #else -# define stm32_getreg(addr) getreg16(addr) -# define stm32_putreg(val,addr) putreg16(val,addr) -# define stm32_checksetup() -# define stm32_dumpep(epno) +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +# define stm32_checksetup() +# define stm32_dumpep(epno) #endif /* Low-Level Helpers ********************************************************/ diff --git a/arch/arm/src/stm32/stm32_wwdg.c b/arch/arm/src/stm32/stm32_wwdg.c index f99133bea4..aac9a289db 100644 --- a/arch/arm/src/stm32/stm32_wwdg.c +++ b/arch/arm/src/stm32/stm32_wwdg.c @@ -103,8 +103,8 @@ struct stm32_lowerhalf_s static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); #else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(val,addr) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) #endif static void stm32_setwindow(struct stm32_lowerhalf_s *priv, uint8_t window); diff --git a/arch/arm/src/stm32/stm32f10xxx_rcc.c b/arch/arm/src/stm32/stm32f10xxx_rcc.c index bd89aa0e57..cd3e346661 100644 --- a/arch/arm/src/stm32/stm32f10xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f10xxx_rcc.c @@ -671,18 +671,18 @@ static void stm32_stdclockconfig(void) /* If this is a value-line part and we are using the HSE as the PLL */ -# if defined(CONFIG_STM32_VALUELINE) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) +# if defined(CONFIG_STM32_VALUELINE) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) -# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1) -# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1 -# endif +# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1) +# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1 +# endif /* Set the HSE prescaler */ regval = STM32_CFGR2_PREDIV1; putreg32(regval, STM32_RCC_CFGR2); -# endif +# endif #endif /* Value-line devices don't implement flash prefetch/waitstates */ diff --git a/arch/arm/src/stm32/stm32f37xxx_rcc.c b/arch/arm/src/stm32/stm32f37xxx_rcc.c index c3d2ded4f6..08f797d087 100644 --- a/arch/arm/src/stm32/stm32f37xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f37xxx_rcc.c @@ -519,16 +519,16 @@ static void stm32_stdclockconfig(void) /* If this is a value-line part and we are using the HSE as the PLL */ -# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV & 1) -# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV -# endif +# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV & 1) +# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV +# endif /* Set the HSE prescaler */ regval = STM32_CFGR2_PREDIV; putreg32(regval, STM32_RCC_CFGR2); -# endif +#endif /* Enable FLASH prefetch buffer and set FLASH wait states */ diff --git a/arch/arm/src/stm32/stm32f40xxx_i2c.c b/arch/arm/src/stm32/stm32f40xxx_i2c.c index a8aa2dc770..ced6566a35 100644 --- a/arch/arm/src/stm32/stm32f40xxx_i2c.c +++ b/arch/arm/src/stm32/stm32f40xxx_i2c.c @@ -150,14 +150,14 @@ #ifdef CONFIG_STM32_I2C_DMA -# if defined(CONFIG_I2C_DMAPRIO) -# if (CONFIG_I2C_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_I2C_DMAPRIO" -# endif -# define I2C_DMA_PRIO CONFIG_I2C_DMAPRIO -# else -# define I2C_DMA_PRIO DMA_SCR_PRIMED -# endif +# if defined(CONFIG_I2C_DMAPRIO) +# if (CONFIG_I2C_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_I2C_DMAPRIO" +# endif +# define I2C_DMA_PRIO CONFIG_I2C_DMAPRIO +# else +# define I2C_DMA_PRIO DMA_SCR_PRIMED +# endif #endif @@ -431,10 +431,10 @@ static const struct stm32_i2c_config_s stm32_i2c2_config = .reset_bit = RCC_APB1RSTR_I2C2RST, .scl_pin = GPIO_I2C2_SCL, .sda_pin = GPIO_I2C2_SDA, -#ifndef CONFIG_I2C_POLLED +# ifndef CONFIG_I2C_POLLED .ev_irq = STM32_IRQ_I2C2EV, .er_irq = STM32_IRQ_I2C2ER -#endif +# endif }; static struct stm32_i2c_priv_s stm32_i2c2_priv = @@ -443,9 +443,9 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = .config = &stm32_i2c2_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED +# ifndef CONFIG_I2C_POLLED .sem_isr = SEM_INITIALIZER(0), -#endif +# endif .intstate = INTSTATE_IDLE, .msgc = 0, .msgv = NULL, @@ -453,13 +453,13 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = .dcnt = 0, .flags = 0, .status = 0, -#ifdef CONFIG_STM32_I2C_DMA -# ifndef CONFIG_STM32_DMA1 -# error "I2C2 enabled with DMA but corresponding DMA controller 1 is not enabled!" -# endif +# ifdef CONFIG_STM32_I2C_DMA +# ifndef CONFIG_STM32_DMA1 +# error "I2C2 enabled with DMA but corresponding DMA controller 1 is not enabled!" +# endif .rxch = DMAMAP_I2C2_RX, .txch = DMAMAP_I2C2_TX, -#endif +# endif }; #endif @@ -471,10 +471,10 @@ static const struct stm32_i2c_config_s stm32_i2c3_config = .reset_bit = RCC_APB1RSTR_I2C3RST, .scl_pin = GPIO_I2C3_SCL, .sda_pin = GPIO_I2C3_SDA, -#ifndef CONFIG_I2C_POLLED +# ifndef CONFIG_I2C_POLLED .ev_irq = STM32_IRQ_I2C3EV, .er_irq = STM32_IRQ_I2C3ER -#endif +# endif }; static struct stm32_i2c_priv_s stm32_i2c3_priv = @@ -483,9 +483,9 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = .config = &stm32_i2c3_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, -#ifndef CONFIG_I2C_POLLED +# ifndef CONFIG_I2C_POLLED .sem_isr = SEM_INITIALIZER(0), -#endif +# endif .intstate = INTSTATE_IDLE, .msgc = 0, .msgv = NULL, @@ -493,13 +493,13 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = .dcnt = 0, .flags = 0, .status = 0, -#ifdef CONFIG_STM32_I2C_DMA -# ifndef CONFIG_STM32_DMA1 -# error "I2C3 enabled with DMA but corresponding DMA controller 1 is not enabled!" -# endif +# ifdef CONFIG_STM32_I2C_DMA +# ifndef CONFIG_STM32_DMA1 +# error "I2C3 enabled with DMA but corresponding DMA controller 1 is not enabled!" +# endif .rxch = DMAMAP_I2C3_RX, .txch = DMAMAP_I2C3_TX, -#endif +# endif }; #endif diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c index aacc475b71..c53f1f5a91 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c @@ -76,13 +76,13 @@ /* Proxy definitions to make the same code work for all the STM32 series ****/ -# define STM32_RCC_XXX STM32_RCC_BDCR -# define RCC_XXX_YYYRST RCC_BDCR_BDRST -# define RCC_XXX_RTCEN RCC_BDCR_RTCEN -# define RCC_XXX_RTCSEL_MASK RCC_BDCR_RTCSEL_MASK -# define RCC_XXX_RTCSEL_LSE RCC_BDCR_RTCSEL_LSE -# define RCC_XXX_RTCSEL_LSI RCC_BDCR_RTCSEL_LSI -# define RCC_XXX_RTCSEL_HSE RCC_BDCR_RTCSEL_HSE +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +# define RCC_XXX_RTCEN RCC_BDCR_RTCEN +# define RCC_XXX_RTCSEL_MASK RCC_BDCR_RTCSEL_MASK +# define RCC_XXX_RTCSEL_LSE RCC_BDCR_RTCSEL_LSE +# define RCC_XXX_RTCSEL_LSI RCC_BDCR_RTCSEL_LSI +# define RCC_XXX_RTCSEL_HSE RCC_BDCR_RTCSEL_HSE /* Time conversions */ diff --git a/arch/arm/src/stm32/stm32l15xxx_rtcc.c b/arch/arm/src/stm32/stm32l15xxx_rtcc.c index 894df0b029..7cec587c5b 100644 --- a/arch/arm/src/stm32/stm32l15xxx_rtcc.c +++ b/arch/arm/src/stm32/stm32l15xxx_rtcc.c @@ -75,7 +75,7 @@ #endif #if !defined(CONFIG_STM32_RTC_MAGIC) -# define CONFIG_STM32_RTC_MAGIC (0xfacefeed) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeed) #endif #if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) @@ -83,7 +83,7 @@ #endif #if !defined(CONFIG_STM32_RTC_MAGIC_REG) -# define CONFIG_STM32_RTC_MAGIC_REG (0) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif #define RTC_MAGIC CONFIG_STM32_RTC_MAGIC diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h index 9d198302dd..60766a7d7d 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h @@ -334,17 +334,17 @@ #define USART_PRESC_SHIFT (0) /* Bits 0-3: Clock prescaler */ #define USART_PRESC_MASK (15 << USART_PRESC_SHIFT) -# define USART_PRESC_NODIV (0 << USART_PRESC_SHIFT) /* Input clock not divided */ -# define USART_PRESC_DIV1 (1 << USART_PRESC_SHIFT) /* Input clock divided by 2 */ -# define USART_PRESC_DIV4 (2 << USART_PRESC_SHIFT) /* Input clock divided by 4 */ -# define USART_PRESC_DIV6 (3 << USART_PRESC_SHIFT) /* Input clock divided by 6 */ -# define USART_PRESC_DIV8 (4 << USART_PRESC_SHIFT) /* Input clock divided by 8 */ -# define USART_PRESC_DIV10 (5 << USART_PRESC_SHIFT) /* Input clock divided by 10 */ -# define USART_PRESC_DIV12 (6 << USART_PRESC_SHIFT) /* Input clock divided by 12 */ -# define USART_PRESC_DIV16 (7 << USART_PRESC_SHIFT) /* Input clock divided by 16 */ -# define USART_PRESC_DIV32 (8 << USART_PRESC_SHIFT) /* Input clock divided by 32 */ -# define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */ -# define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ -# define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ +# define USART_PRESC_NODIV (0 << USART_PRESC_SHIFT) /* Input clock not divided */ +# define USART_PRESC_DIV1 (1 << USART_PRESC_SHIFT) /* Input clock divided by 2 */ +# define USART_PRESC_DIV4 (2 << USART_PRESC_SHIFT) /* Input clock divided by 4 */ +# define USART_PRESC_DIV6 (3 << USART_PRESC_SHIFT) /* Input clock divided by 6 */ +# define USART_PRESC_DIV8 (4 << USART_PRESC_SHIFT) /* Input clock divided by 8 */ +# define USART_PRESC_DIV10 (5 << USART_PRESC_SHIFT) /* Input clock divided by 10 */ +# define USART_PRESC_DIV12 (6 << USART_PRESC_SHIFT) /* Input clock divided by 12 */ +# define USART_PRESC_DIV16 (7 << USART_PRESC_SHIFT) /* Input clock divided by 16 */ +# define USART_PRESC_DIV32 (8 << USART_PRESC_SHIFT) /* Input clock divided by 32 */ +# define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */ +# define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ +# define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ #endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c index b37b94fbe2..4b572fffea 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c @@ -311,9 +311,9 @@ static const struct uart_ops_s g_uart_ops = .receive = stm32serial_receive, .rxint = stm32serial_rxint, .rxavailable = stm32serial_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL +# ifdef CONFIG_SERIAL_IFLOWCONTROL .rxflowcontrol = stm32serial_rxflowcontrol, -#endif +# endif .send = stm32serial_send, .txint = stm32serial_txint, .txready = stm32serial_txready, @@ -332,9 +332,9 @@ static const struct uart_ops_s g_uart_dma_ops = .receive = stm32serial_dmareceive, .rxint = stm32serial_dmarxint, .rxavailable = stm32serial_dmarxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL +# ifdef CONFIG_SERIAL_IFLOWCONTROL .rxflowcontrol = stm32serial_rxflowcontrol, -#endif +# endif .send = stm32serial_send, .txint = stm32serial_txint, .txready = stm32serial_txready, @@ -347,41 +347,41 @@ static const struct uart_ops_s g_uart_dma_ops = #ifdef CONFIG_STM32F0L0G0_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; -# ifdef CONFIG_USART1_RXDMA +# ifdef CONFIG_USART1_RXDMA static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32F0L0G0_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; -# ifdef CONFIG_USART2_RXDMA +# ifdef CONFIG_USART2_RXDMA static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32F0L0G0_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; -# ifdef CONFIG_USART3_RXDMA +# ifdef CONFIG_USART3_RXDMA static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32F0L0G0_USART4 static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; -# ifdef CONFIG_USART4_RXDMA +# ifdef CONFIG_USART4_RXDMA static char g_usart4rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32F0L0G0_USART5 static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE]; static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE]; -# ifdef CONFIG_USART5_RXDMA +# ifdef CONFIG_USART5_RXDMA static char g_usart5rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif /* This describes the state of the STM32 USART1 ports. */ @@ -391,9 +391,9 @@ static struct stm32_serial_s g_usart1priv = { .dev = { -#if CONSOLE_USART == 1 +# if CONSOLE_USART == 1 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART1_RXBUFSIZE, @@ -404,11 +404,11 @@ static struct stm32_serial_s g_usart1priv = .size = CONFIG_USART1_TXBUFSIZE, .buffer = g_usart1txbuffer, }, -#ifdef CONFIG_USART1_RXDMA +# ifdef CONFIG_USART1_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart1priv, }, @@ -421,27 +421,27 @@ static struct stm32_serial_s g_usart1priv = .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART1_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART1_RTS, -#endif -#ifdef CONFIG_USART1_RXDMA +# endif +# ifdef CONFIG_USART1_RXDMA .rxdma_channel = DMAMAP_USART1_RX, .rxfifo = g_usart1rxfifo, -#endif - -#ifdef CONFIG_USART1_RS485 - .rs485_dir_gpio = GPIO_USART1_RS485_DIR, -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART1_RS485 + .rs485_dir_gpio = GPIO_USART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -452,9 +452,9 @@ static struct stm32_serial_s g_usart2priv = { .dev = { -#if CONSOLE_USART == 2 +# if CONSOLE_USART == 2 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART2_RXBUFSIZE, @@ -465,11 +465,11 @@ static struct stm32_serial_s g_usart2priv = .size = CONFIG_USART2_TXBUFSIZE, .buffer = g_usart2txbuffer, }, -#ifdef CONFIG_USART2_RXDMA +# ifdef CONFIG_USART2_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart2priv, }, @@ -482,27 +482,27 @@ static struct stm32_serial_s g_usart2priv = .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART2_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART2_RTS, -#endif -#ifdef CONFIG_USART2_RXDMA +# endif +# ifdef CONFIG_USART2_RXDMA .rxdma_channel = DMAMAP_USART2_RX, .rxfifo = g_usart2rxfifo, -#endif - -#ifdef CONFIG_USART2_RS485 - .rs485_dir_gpio = GPIO_USART2_RS485_DIR, -# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART2_RS485 + .rs485_dir_gpio = GPIO_USART2_RS485_DIR, +# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -513,9 +513,9 @@ static struct stm32_serial_s g_usart3priv = { .dev = { -#if CONSOLE_USART == 3 +# if CONSOLE_USART == 3 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART3_RXBUFSIZE, @@ -526,11 +526,11 @@ static struct stm32_serial_s g_usart3priv = .size = CONFIG_USART3_TXBUFSIZE, .buffer = g_usart3txbuffer, }, -#ifdef CONFIG_USART3_RXDMA +# ifdef CONFIG_USART3_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart3priv, }, @@ -543,27 +543,27 @@ static struct stm32_serial_s g_usart3priv = .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART3_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART3_RTS, -#endif -#ifdef CONFIG_USART3_RXDMA +# endif +# ifdef CONFIG_USART3_RXDMA .rxdma_channel = DMAMAP_USART3_RX, .rxfifo = g_usart3rxfifo, -#endif - -#ifdef CONFIG_USART3_RS485 - .rs485_dir_gpio = GPIO_USART3_RS485_DIR, -# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART3_RS485 + .rs485_dir_gpio = GPIO_USART3_RS485_DIR, +# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -574,9 +574,9 @@ static struct stm32_serial_s g_usart4priv = { .dev = { -#if CONSOLE_USART == 4 +# if CONSOLE_USART == 4 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART4_RXBUFSIZE, @@ -587,11 +587,11 @@ static struct stm32_serial_s g_usart4priv = .size = CONFIG_USART4_TXBUFSIZE, .buffer = g_usart4txbuffer, }, -#ifdef CONFIG_USART4_RXDMA +# ifdef CONFIG_USART4_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart4priv, }, @@ -599,36 +599,36 @@ static struct stm32_serial_s g_usart4priv = .parity = CONFIG_USART4_PARITY, .bits = CONFIG_USART4_BITS, .stopbits2 = CONFIG_USART4_2STOP, -#ifdef CONFIG_SERIAL_IFLOWCONTROL +# ifdef CONFIG_SERIAL_IFLOWCONTROL .iflow = false, -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL +# endif +# ifdef CONFIG_SERIAL_OFLOWCONTROL .oflow = false, -#endif +# endif .baud = CONFIG_USART4_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_USART4_BASE, .tx_gpio = GPIO_USART4_TX, .rx_gpio = GPIO_USART4_RX, -#ifdef CONFIG_SERIAL_OFLOWCONTROL +# ifdef CONFIG_SERIAL_OFLOWCONTROL .cts_gpio = 0, -#endif -#ifdef CONFIG_SERIAL_IFLOWCONTROL +# endif +# ifdef CONFIG_SERIAL_IFLOWCONTROL .rts_gpio = 0, -#endif -#ifdef CONFIG_USART4_RXDMA +# endif +# ifdef CONFIG_USART4_RXDMA .rxdma_channel = DMAMAP_USART4_RX, .rxfifo = g_usart4rxfifo, -#endif - -#ifdef CONFIG_USART4_RS485 - .rs485_dir_gpio = GPIO_USART4_RS485_DIR, -# if (CONFIG_USART4_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART4_RS485 + .rs485_dir_gpio = GPIO_USART4_RS485_DIR, +# if (CONFIG_USART4_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -639,9 +639,9 @@ static struct stm32_serial_s g_usart5priv = { .dev = { -#if CONSOLE_USART == 5 +# if CONSOLE_USART == 5 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART5_RXBUFSIZE, @@ -652,11 +652,11 @@ static struct stm32_serial_s g_usart5priv = .size = CONFIG_USART5_TXBUFSIZE, .buffer = g_usart5txbuffer, }, -#ifdef CONFIG_USART5_RXDMA +# ifdef CONFIG_USART5_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart5priv, }, @@ -664,36 +664,36 @@ static struct stm32_serial_s g_usart5priv = .parity = CONFIG_USART5_PARITY, .bits = CONFIG_USART5_BITS, .stopbits2 = CONFIG_USART5_2STOP, -#ifdef CONFIG_SERIAL_IFLOWCONTROL +# ifdef CONFIG_SERIAL_IFLOWCONTROL .iflow = false, -#endif -#ifdef CONFIG_SERIAL_OFLOWCONTROL +# endif +# ifdef CONFIG_SERIAL_OFLOWCONTROL .oflow = false, -#endif +# endif .baud = CONFIG_USART5_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_USART5_BASE, .tx_gpio = GPIO_USART5_TX, .rx_gpio = GPIO_USART5_RX, -#ifdef CONFIG_SERIAL_OFLOWCONTROL +# ifdef CONFIG_SERIAL_OFLOWCONTROL .cts_gpio = 0, -#endif -#ifdef CONFIG_SERIAL_IFLOWCONTROL +# endif +# ifdef CONFIG_SERIAL_IFLOWCONTROL .rts_gpio = 0, -#endif -#ifdef CONFIG_USART5_RXDMA +# endif +# ifdef CONFIG_USART5_RXDMA .rxdma_channel = DMAMAP_USART5_RX, .rxfifo = g_usart5rxfifo, -#endif - -#ifdef CONFIG_USART5_RS485 - .rs485_dir_gpio = GPIO_USART5_RS485_DIR, -# if (CONFIG_USART5_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART5_RS485 + .rs485_dir_gpio = GPIO_USART5_RS485_DIR, +# if (CONFIG_USART5_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c b/arch/arm/src/stm32f0l0g0/stm32_usbdev.c index 7c5a86ddea..f681d58dae 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c +++ b/arch/arm/src/stm32f0l0g0/stm32_usbdev.c @@ -353,9 +353,9 @@ static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); static void stm32_dumpep(int epno); #else -# define stm32_getreg(addr) getreg16(addr) -# define stm32_putreg(val,addr) putreg16(val,addr) -# define stm32_dumpep(epno) +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +# define stm32_dumpep(epno) #endif /* Low-Level Helpers ********************************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32_sai.h b/arch/arm/src/stm32f7/hardware/stm32_sai.h index 85b9abd80e..755d194f81 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_sai.h +++ b/arch/arm/src/stm32f7/hardware/stm32_sai.h @@ -127,12 +127,12 @@ /* Bit 4: Reserved */ #define SAI_CR1_DS_SHIFT (5) /* Bits 5-7: Data size */ #define SAI_CR1_DS_MASK (7 << SAI_CR1_DS_SHIFT) -# define SAI_CR1_DS_8BITS (2 << SAI_CR1_DS_SHIFT) /* 8 bits */ -# define SAI_CR1_DS_10BITS (3 << SAI_CR1_DS_SHIFT) /* 10 bits */ -# define SAI_CR1_DS_16BITS (4 << SAI_CR1_DS_SHIFT) /* 16 bits */ -# define SAI_CR1_DS_20BITS (5 << SAI_CR1_DS_SHIFT) /* 20 bits */ -# define SAI_CR1_DS_24BITS (6 << SAI_CR1_DS_SHIFT) /* 24 bits */ -# define SAI_CR1_DS_32BITS (7 << SAI_CR1_DS_SHIFT) /* 32 bits */ +# define SAI_CR1_DS_8BITS (2 << SAI_CR1_DS_SHIFT) /* 8 bits */ +# define SAI_CR1_DS_10BITS (3 << SAI_CR1_DS_SHIFT) /* 10 bits */ +# define SAI_CR1_DS_16BITS (4 << SAI_CR1_DS_SHIFT) /* 16 bits */ +# define SAI_CR1_DS_20BITS (5 << SAI_CR1_DS_SHIFT) /* 20 bits */ +# define SAI_CR1_DS_24BITS (6 << SAI_CR1_DS_SHIFT) /* 24 bits */ +# define SAI_CR1_DS_32BITS (7 << SAI_CR1_DS_SHIFT) /* 32 bits */ #define SAI_CR1_LSBFIRST (1 << 8) /* Bit 8: Least significant bit first */ #define SAI_CR1_CKSTR (1 << 9) /* Bit 9: Clock strobing edge */ diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c index 0bfbef3582..1f918d21a3 100644 --- a/arch/arm/src/stm32f7/stm32_adc.c +++ b/arch/arm/src/stm32f7/stm32_adc.c @@ -156,13 +156,13 @@ #define ADC_MAX_FADC 36000000 #if STM32_PCLK2_FREQUENCY/2 <= ADC_MAX_FADC -# define ADC_CCR_ADCPRE_DIV ADC_CCR_ADCPRE_DIV2 +# define ADC_CCR_ADCPRE_DIV ADC_CCR_ADCPRE_DIV2 #elif STM32_PCLK2_FREQUENCY/4 <= ADC_MAX_FADC -# define ADC_CCR_ADCPRE_DIV ADC_CCR_ADCPRE_DIV4 +# define ADC_CCR_ADCPRE_DIV ADC_CCR_ADCPRE_DIV4 #elif STM32_PCLK2_FREQUENCY/6 <= ADC_MAX_FADC -# define ADC_CCR_ADCPRE_DIV ADC_CCR_ADCPRE_DIV6 +# define ADC_CCR_ADCPRE_DIV ADC_CCR_ADCPRE_DIV6 #elif STM32_PCLK2_FREQUENCY/8 <= ADC_MAX_FADC -# define ADC_CCR_ADCPRE_DIV ADC_CCR_ADCPRE_DIV8 +# define ADC_CCR_ADCPRE_DIV ADC_CCR_ADCPRE_DIV8 #else # error "PCLK2 too high - no divisor found " #endif diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 5116423e6d..d52ab837c3 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -681,9 +681,9 @@ static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); #else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(val,addr) putreg32(val,addr) -# define stm32_checksetup() +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) +# define stm32_checksetup() #endif /* Free buffer management */ diff --git a/arch/arm/src/stm32f7/stm32_lse.c b/arch/arm/src/stm32f7/stm32_lse.c index ad934a42ce..0829686a82 100644 --- a/arch/arm/src/stm32f7/stm32_lse.c +++ b/arch/arm/src/stm32f7/stm32_lse.c @@ -35,17 +35,17 @@ #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) #ifdef CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 -# error "Invalid LSE drive capability setting" -#endif +# if CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +# error "Invalid LSE drive capability setting" +# endif #endif #ifdef CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 -# error "Invalid LSE drive capability setting" -#endif +# if CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +# error "Invalid LSE drive capability setting" +# endif #endif /**************************************************************************** diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c index 568488aa10..9769ca98d4 100644 --- a/arch/arm/src/stm32f7/stm32_otghost.c +++ b/arch/arm/src/stm32f7/stm32_otghost.c @@ -276,8 +276,8 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t addr, uint32_t value); #else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(addr,val) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(addr,val) putreg32(val,addr) #endif static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c index 20285f0d19..e8a7cab9a3 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.c +++ b/arch/arm/src/stm32f7/stm32_qspi.c @@ -247,7 +247,7 @@ struct qspi_xctnspec_s static bool qspi_checkreg(struct stm32f7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else -# define qspi_checkreg(priv,wr,value,address) (false) +# define qspi_checkreg(priv,wr,value,address) (false) #endif static inline uint32_t qspi_getreg(struct stm32f7_qspidev_s *priv, @@ -259,13 +259,13 @@ static inline void qspi_putreg(struct stm32f7_qspidev_s *priv, static void qspi_dumpregs(struct stm32f7_qspidev_s *priv, const char *msg); #else -# define qspi_dumpregs(priv,msg) +# define qspi_dumpregs(priv,msg) #endif #if defined(CONFIG_DEBUG_SPI_INFO) && defined(CONFIG_DEBUG_GPIO) static void qspi_dumpgpioconfig(const char *msg); #else -# define qspi_dumpgpioconfig(msg) +# define qspi_dumpgpioconfig(msg) #endif /* Interrupts */ diff --git a/arch/arm/src/stm32f7/stm32_rtc.c b/arch/arm/src/stm32f7/stm32_rtc.c index 5121ddb051..673994ad55 100644 --- a/arch/arm/src/stm32f7/stm32_rtc.c +++ b/arch/arm/src/stm32f7/stm32_rtc.c @@ -975,7 +975,7 @@ int up_rtc_initialize(void) modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); -# if RCC_BDCR_RTCSEL == RCC_BDCR_RTCSEL_LSE +#if RCC_BDCR_RTCSEL == RCC_BDCR_RTCSEL_LSE /* Because of the Backup domain Reset - we must re enable the LSE * if it is used */ diff --git a/arch/arm/src/stm32f7/stm32_rtc.h b/arch/arm/src/stm32f7/stm32_rtc.h index 1fff831cb9..0d13136e69 100644 --- a/arch/arm/src/stm32f7/stm32_rtc.h +++ b/arch/arm/src/stm32f7/stm32_rtc.h @@ -45,7 +45,7 @@ #define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ #if !defined(CONFIG_STM32F7_RTC_MAGIC) -# define CONFIG_STM32F7_RTC_MAGIC (0xfacefeed) +# define CONFIG_STM32F7_RTC_MAGIC (0xfacefeed) #endif #if !defined(CONFIG_STM32F7_RTC_MAGIC_TIME_SET) @@ -53,7 +53,7 @@ #endif #if !defined(CONFIG_STM32F7_RTC_MAGIC_REG) -# define CONFIG_STM32F7_RTC_MAGIC_REG (0) +# define CONFIG_STM32F7_RTC_MAGIC_REG (0) #endif #define RTC_MAGIC CONFIG_STM32F7_RTC_MAGIC diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index 52fa4741a2..14b7c3cb14 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -381,7 +381,7 @@ * blocked. */ -# if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_IFLOWCONTROL) +# if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_IFLOWCONTROL) # warning "RXDMA and IFLOWCONTROL both enabled for USART1. \ This combination can lead to data loss." # endif diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c index a08d097ab5..cf86149f52 100644 --- a/arch/arm/src/stm32f7/stm32_tim.c +++ b/arch/arm/src/stm32f7/stm32_tim.c @@ -1000,7 +1000,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, case 2: stm32_tim_gpioconfig(GPIO_TIM9_CH3OUT, mode); break; -# endif +# endif # if defined(GPIO_TIM9_CH4OUT) case 3: stm32_tim_gpioconfig(GPIO_TIM9_CH4OUT, mode); diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h index 44aa1e21c4..6a10fea0a2 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h @@ -222,11 +222,11 @@ #define STM32_PWR_WKUPPUPD5_SHIFT (24) /* Bits 24-25: Wakeup pin pull config for WKUP5 */ #define STM32_PWR_WKUPPUPD6_SHIFT (26) /* Bits 26-27: Wakeup pin pull config for WKUP6 */ -# define STM32_PWR_WKUPPUPD_NONE (0) /* No pull-up */ -# define STM32_PWR_WKUPPUPD_PULLUP (1) /* Pull-up enabled */ -# define STM32_PWR_WKUPPUPD_PULLDN (2) /* Pull-down enabled */ - /* 3 is reserved */ -# define STM32_PWR_WKUPPUPD_MASK (3) - /* Bits 28-31: Reserved */ +# define STM32_PWR_WKUPPUPD_NONE (0) /* No pull-up */ +# define STM32_PWR_WKUPPUPD_PULLUP (1) /* Pull-up enabled */ +# define STM32_PWR_WKUPPUPD_PULLDN (2) /* Pull-down enabled */ + /* 3 is reserved */ +# define STM32_PWR_WKUPPUPD_MASK (3) + /* Bits 28-31: Reserved */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PWR_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h index 544d4c2e2c..cedfe52172 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h @@ -397,18 +397,17 @@ #define USART_PRESC_SHIFT (0) /* Bits 0-3: Clock prescaler */ #define USART_PRESC_MASK (15 << USART_PRESC_SHIFT) -# define USART_PRESC_NODIV (0 << USART_PRESC_SHIFT) /* Input clock not divided */ -# define USART_PRESC_DIV1 (1 << USART_PRESC_SHIFT) /* Input clock divided by 2 */ -# define USART_PRESC_DIV4 (2 << USART_PRESC_SHIFT) /* Input clock divided by 4 */ -# define USART_PRESC_DIV6 (3 << USART_PRESC_SHIFT) /* Input clock divided by 6 */ -# define USART_PRESC_DIV8 (4 << USART_PRESC_SHIFT) /* Input clock divided by 8 */ -# define USART_PRESC_DIV10 (5 << USART_PRESC_SHIFT) /* Input clock divided by 10 */ -# define USART_PRESC_DIV12 (6 << USART_PRESC_SHIFT) /* Input clock divided by 12 */ -# define USART_PRESC_DIV16 (7 << USART_PRESC_SHIFT) /* Input clock divided by 16 */ -# define USART_PRESC_DIV32 (8 << USART_PRESC_SHIFT) /* Input clock divided by 32 */ -# define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */ -# define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ -# define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ - +# define USART_PRESC_NODIV (0 << USART_PRESC_SHIFT) /* Input clock not divided */ +# define USART_PRESC_DIV1 (1 << USART_PRESC_SHIFT) /* Input clock divided by 2 */ +# define USART_PRESC_DIV4 (2 << USART_PRESC_SHIFT) /* Input clock divided by 4 */ +# define USART_PRESC_DIV6 (3 << USART_PRESC_SHIFT) /* Input clock divided by 6 */ +# define USART_PRESC_DIV8 (4 << USART_PRESC_SHIFT) /* Input clock divided by 8 */ +# define USART_PRESC_DIV10 (5 << USART_PRESC_SHIFT) /* Input clock divided by 10 */ +# define USART_PRESC_DIV12 (6 << USART_PRESC_SHIFT) /* Input clock divided by 12 */ +# define USART_PRESC_DIV16 (7 << USART_PRESC_SHIFT) /* Input clock divided by 16 */ +# define USART_PRESC_DIV32 (8 << USART_PRESC_SHIFT) /* Input clock divided by 32 */ +# define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */ +# define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ +# define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ #endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_UART_H */ diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c index 4017a7410f..728dbacb87 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.c +++ b/arch/arm/src/stm32h7/stm32_ethernet.c @@ -684,9 +684,9 @@ static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); #else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(val,addr) putreg32(val,addr) -# define stm32_checksetup() +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) +# define stm32_checksetup() #endif /* Free buffer management */ diff --git a/arch/arm/src/stm32h7/stm32_iwdg.c b/arch/arm/src/stm32h7/stm32_iwdg.c index b4227fc4b2..99fe68dae2 100644 --- a/arch/arm/src/stm32h7/stm32_iwdg.c +++ b/arch/arm/src/stm32h7/stm32_iwdg.c @@ -126,8 +126,8 @@ struct stm32_lowerhalf_s static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); #else -# define stm32_getreg(addr) getreg16(addr) -# define stm32_putreg(val,addr) putreg16(val,addr) +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) #endif static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv); diff --git a/arch/arm/src/stm32h7/stm32_lse.c b/arch/arm/src/stm32h7/stm32_lse.c index 0d9862d4d3..8f8446f366 100644 --- a/arch/arm/src/stm32h7/stm32_lse.c +++ b/arch/arm/src/stm32h7/stm32_lse.c @@ -36,17 +36,17 @@ #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) #ifdef CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 -# error "Invalid LSE drive capability setting" -#endif +# if CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +# error "Invalid LSE drive capability setting" +# endif #endif #ifdef CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 -# error "Invalid LSE drive capability setting" -#endif +# if CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +# error "Invalid LSE drive capability setting" +# endif #endif /**************************************************************************** diff --git a/arch/arm/src/stm32h7/stm32_otgdev.c b/arch/arm/src/stm32h7/stm32_otgdev.c index 80ef60ea1f..0fee200bb7 100644 --- a/arch/arm/src/stm32h7/stm32_otgdev.c +++ b/arch/arm/src/stm32h7/stm32_otgdev.c @@ -554,8 +554,8 @@ struct stm32_usbdev_s static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); #else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(val,addr) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) #endif /* Request queue operations *************************************************/ diff --git a/arch/arm/src/stm32h7/stm32_otghost.c b/arch/arm/src/stm32h7/stm32_otghost.c index 888c1c11b5..13a52a881b 100644 --- a/arch/arm/src/stm32h7/stm32_otghost.c +++ b/arch/arm/src/stm32h7/stm32_otghost.c @@ -303,8 +303,8 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t addr, uint32_t value); #else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(addr,val) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(addr,val) putreg32(val,addr) #endif static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c index 2566d5ac3b..52f5261e6f 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.c +++ b/arch/arm/src/stm32h7/stm32_qspi.c @@ -272,7 +272,7 @@ struct qspi_xctnspec_s static bool qspi_checkreg(struct stm32h7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else -# define qspi_checkreg(priv,wr,value,address) (false) +# define qspi_checkreg(priv,wr,value,address) (false) #endif static inline uint32_t qspi_getreg(struct stm32h7_qspidev_s *priv, @@ -284,13 +284,13 @@ static inline void qspi_putreg(struct stm32h7_qspidev_s *priv, static void qspi_dumpregs(struct stm32h7_qspidev_s *priv, const char *msg); #else -# define qspi_dumpregs(priv,msg) +# define qspi_dumpregs(priv,msg) #endif #if defined(CONFIG_DEBUG_SPI_INFO) && defined(CONFIG_DEBUG_GPIO) static void qspi_dumpgpioconfig(const char *msg); #else -# define qspi_dumpgpioconfig(msg) +# define qspi_dumpgpioconfig(msg) #endif /* Interrupts */ diff --git a/arch/arm/src/stm32h7/stm32_rtc.c b/arch/arm/src/stm32h7/stm32_rtc.c index 82630a0b0f..3edad720a8 100644 --- a/arch/arm/src/stm32h7/stm32_rtc.c +++ b/arch/arm/src/stm32h7/stm32_rtc.c @@ -975,7 +975,7 @@ int up_rtc_initialize(void) modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); -# if RCC_BDCR_RTCSEL == RCC_BDCR_RTCSEL_LSE +#if RCC_BDCR_RTCSEL == RCC_BDCR_RTCSEL_LSE /* Because of the Backup domain Reset - we must re enable the LSE * if it is used */ diff --git a/arch/arm/src/stm32h7/stm32_rtc.h b/arch/arm/src/stm32h7/stm32_rtc.h index f5057b4598..bc4ed385c5 100644 --- a/arch/arm/src/stm32h7/stm32_rtc.h +++ b/arch/arm/src/stm32h7/stm32_rtc.h @@ -45,7 +45,7 @@ #define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ #if !defined(CONFIG_STM32H7_RTC_MAGIC) -# define CONFIG_STM32H7_RTC_MAGIC (0xfacefeed) +# define CONFIG_STM32H7_RTC_MAGIC (0xfacefeed) #endif #if !defined(CONFIG_STM32H7_RTC_MAGIC_TIME_SET) @@ -53,7 +53,7 @@ #endif #if !defined(CONFIG_STM32H7_RTC_MAGIC_REG) -# define CONFIG_STM32H7_RTC_MAGIC_REG (0) +# define CONFIG_STM32H7_RTC_MAGIC_REG (0) #endif #define RTC_MAGIC CONFIG_STM32H7_RTC_MAGIC diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index 292c775e7e..4b8048ed58 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -528,7 +528,7 @@ * blocked. */ -# if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_IFLOWCONTROL) +# if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_IFLOWCONTROL) # warning "RXDMA and IFLOWCONTROL both enabled for USART1. \ This combination can lead to data loss." # endif diff --git a/arch/arm/src/stm32h7/stm32_wwdg.c b/arch/arm/src/stm32h7/stm32_wwdg.c index 339e58328e..11a77bfaaa 100644 --- a/arch/arm/src/stm32h7/stm32_wwdg.c +++ b/arch/arm/src/stm32h7/stm32_wwdg.c @@ -102,8 +102,8 @@ struct stm32_lowerhalf_s static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); #else -# define stm32_getreg(addr) getreg32(addr) -# define stm32_putreg(val,addr) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) #endif static void stm32_setwindow(struct stm32_lowerhalf_s *priv, uint8_t window); diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_sai.h b/arch/arm/src/stm32l4/hardware/stm32l4_sai.h index c01bf94d33..17cd5d620d 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_sai.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_sai.h @@ -127,12 +127,12 @@ /* Bit 4: Reserved */ #define SAI_CR1_DS_SHIFT (5) /* Bits 5-7: Data size */ #define SAI_CR1_DS_MASK (7 << SAI_CR1_DS_SHIFT) -# define SAI_CR1_DS_8BITS (2 << SAI_CR1_DS_SHIFT) /* 8 bits */ -# define SAI_CR1_DS_10BITS (3 << SAI_CR1_DS_SHIFT) /* 10 bits */ -# define SAI_CR1_DS_16BITS (4 << SAI_CR1_DS_SHIFT) /* 16 bits */ -# define SAI_CR1_DS_20BITS (5 << SAI_CR1_DS_SHIFT) /* 20 bits */ -# define SAI_CR1_DS_24BITS (6 << SAI_CR1_DS_SHIFT) /* 24 bits */ -# define SAI_CR1_DS_32BITS (7 << SAI_CR1_DS_SHIFT) /* 32 bits */ +# define SAI_CR1_DS_8BITS (2 << SAI_CR1_DS_SHIFT) /* 8 bits */ +# define SAI_CR1_DS_10BITS (3 << SAI_CR1_DS_SHIFT) /* 10 bits */ +# define SAI_CR1_DS_16BITS (4 << SAI_CR1_DS_SHIFT) /* 16 bits */ +# define SAI_CR1_DS_20BITS (5 << SAI_CR1_DS_SHIFT) /* 20 bits */ +# define SAI_CR1_DS_24BITS (6 << SAI_CR1_DS_SHIFT) /* 24 bits */ +# define SAI_CR1_DS_32BITS (7 << SAI_CR1_DS_SHIFT) /* 32 bits */ #define SAI_CR1_LSBFIRST (1 << 8) /* Bit 8: Least significant bit first */ #define SAI_CR1_CKSTR (1 << 9) /* Bit 9: Clock strobing edge */ diff --git a/arch/arm/src/stm32l4/stm32l4_iwdg.c b/arch/arm/src/stm32l4/stm32l4_iwdg.c index a2cb7ca8cb..316909ac88 100644 --- a/arch/arm/src/stm32l4/stm32l4_iwdg.c +++ b/arch/arm/src/stm32l4/stm32l4_iwdg.c @@ -106,8 +106,8 @@ struct stm32l4_lowerhalf_s static uint16_t stm32l4_getreg(uint32_t addr); static void stm32l4_putreg(uint16_t val, uint32_t addr); #else -# define stm32l4_getreg(addr) getreg16(addr) -# define stm32l4_putreg(val,addr) putreg16(val,addr) +# define stm32l4_getreg(addr) getreg16(addr) +# define stm32l4_putreg(val,addr) putreg16(val,addr) #endif static inline void diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.c b/arch/arm/src/stm32l4/stm32l4_lptim.c index 7f77de935b..79b18f71c9 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.c +++ b/arch/arm/src/stm32l4/stm32l4_lptim.c @@ -310,21 +310,21 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, case STM32L4_LPTIM1_BASE: switch (channel) { -# if defined(GPIO_LPTIM1_OUT_1) +# if defined(GPIO_LPTIM1_OUT_1) case 1: *cfg = GPIO_LPTIM1_OUT_1; break; -# endif -# if defined(GPIO_LPTIM1_OUT_2) +# endif +# if defined(GPIO_LPTIM1_OUT_2) case 2: *cfg = GPIO_LPTIM1_OUT_2; break; -# endif -# if defined(GPIO_LPTIM1_OUT_3) +# endif +# if defined(GPIO_LPTIM1_OUT_3) case 3: *cfg = GPIO_LPTIM1_OUT_3; break; -# endif +# endif default: return ERROR; } @@ -335,21 +335,21 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, case STM32L4_LPTIM2_BASE: switch (channel) { -# if defined(GPIO_LPTIM2_OUT_1) +# if defined(GPIO_LPTIM2_OUT_1) case 1: *cfg = GPIO_LPTIM2_OUT_1; break; -# endif -# if defined(GPIO_LPTIM2_OUT_2) +# endif +# if defined(GPIO_LPTIM2_OUT_2) case 2: *cfg = GPIO_LPTIM2_OUT_2; break; -# endif -# if defined(GPIO_LPTIM2_OUT_3) +# endif +# if defined(GPIO_LPTIM2_OUT_3) case 3: *cfg = GPIO_LPTIM2_OUT_3; break; -# endif +# endif default: return ERROR; } diff --git a/arch/arm/src/stm32l4/stm32l4_lse.c b/arch/arm/src/stm32l4/stm32l4_lse.c index 05290066ec..61ea594d6c 100644 --- a/arch/arm/src/stm32l4/stm32l4_lse.c +++ b/arch/arm/src/stm32l4/stm32l4_lse.c @@ -34,17 +34,17 @@ ****************************************************************************/ #ifdef CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 -# error "Invalid LSE drive capability setting" -#endif +# if CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +# error "Invalid LSE drive capability setting" +# endif #endif #ifdef CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 -# error "Invalid LSE drive capability setting" -#endif +# if CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +# error "Invalid LSE drive capability setting" +# endif #endif /**************************************************************************** diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c index b57b6a9473..410ec497d3 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c @@ -550,8 +550,8 @@ struct stm32l4_usbdev_s static uint32_t stm32l4_getreg(uint32_t addr); static void stm32l4_putreg(uint32_t val, uint32_t addr); #else -# define stm32l4_getreg(addr) getreg32(addr) -# define stm32l4_putreg(val,addr) putreg32(val,addr) +# define stm32l4_getreg(addr) getreg32(addr) +# define stm32l4_putreg(val,addr) putreg32(val,addr) #endif /* Request queue operations *************************************************/ @@ -5417,22 +5417,22 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval = OTGFS_GCCFG_PWRDWN; -# ifdef CONFIG_USBDEV_VBUSSENSING +#ifdef CONFIG_USBDEV_VBUSSENSING /* Enable Vbus sensing */ regval |= OTGFS_GCCFG_VBDEN; -# endif +#endif stm32l4_putreg(regval, STM32L4_OTGFS_GCCFG); up_mdelay(20); /* When VBUS sensing is not used we need to force the B session valid */ -# ifndef CONFIG_USBDEV_VBUSSENSING +#ifndef CONFIG_USBDEV_VBUSSENSING regval = stm32l4_getreg(STM32L4_OTGFS_GOTGCTL); regval |= (OTGFS_GOTGCTL_BVALOEN | OTGFS_GOTGCTL_BVALOVAL); stm32l4_putreg(regval, STM32L4_OTGFS_GOTGCTL); -# endif +#endif /* Force Device Mode */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c index c5933feb65..c29be2175f 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c @@ -273,8 +273,8 @@ static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32l4_getreg(uint32_t addr); static void stm32l4_putreg(uint32_t addr, uint32_t value); #else -# define stm32l4_getreg(addr) getreg32(addr) -# define stm32l4_putreg(addr,val) putreg32(val,addr) +# define stm32l4_getreg(addr) getreg32(addr) +# define stm32l4_putreg(addr,val) putreg32(val,addr) #endif static inline void stm32l4_modifyreg(uint32_t addr, uint32_t clrbits, diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index 05c3b8bd8c..39b6655073 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -245,7 +245,7 @@ struct qspi_xctnspec_s static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else -# define qspi_checkreg(priv,wr,value,address) (false) +# define qspi_checkreg(priv,wr,value,address) (false) #endif static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv, @@ -257,13 +257,13 @@ static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg); #else -# define qspi_dumpregs(priv,msg) +# define qspi_dumpregs(priv,msg) #endif #if defined(CONFIG_DEBUG_SPI_INFO) && defined(CONFIG_DEBUG_GPIO) static void qspi_dumpgpioconfig(const char *msg); #else -# define qspi_dumpgpioconfig(msg) +# define qspi_dumpgpioconfig(msg) #endif /* Interrupts */ diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index 8836539239..a1802aa4bb 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -37,18 +37,18 @@ ****************************************************************************/ #define STM32L4_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ -#define STM32L4_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ +#define STM32L4_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ #if !defined(CONFIG_STM32L4_RTC_MAGIC) -# define CONFIG_STM32L4_RTC_MAGIC (0xfacefeee) +# define CONFIG_STM32L4_RTC_MAGIC (0xfacefeee) #endif #if !defined(CONFIG_STM32L4_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32L4_RTC_MAGIC_TIME_SET (0xf00dface) +# define CONFIG_STM32L4_RTC_MAGIC_TIME_SET (0xf00dface) #endif #if !defined(CONFIG_STM32L4_RTC_MAGIC_REG) -# define CONFIG_STM32L4_RTC_MAGIC_REG (0) +# define CONFIG_STM32L4_RTC_MAGIC_REG (0) #endif #define RTC_MAGIC CONFIG_STM32L4_RTC_MAGIC diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index 6392b7c1a1..c6b4c90345 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -390,49 +390,49 @@ static const struct uart_ops_s g_uart_dma_ops = #ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; -# ifdef CONFIG_LPUART1_RXDMA +# ifdef CONFIG_LPUART1_RXDMA static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32L4_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; -# ifdef CONFIG_USART1_RXDMA +# ifdef CONFIG_USART1_RXDMA static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32L4_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; -# ifdef CONFIG_USART2_RXDMA +# ifdef CONFIG_USART2_RXDMA static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32L4_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; -# ifdef CONFIG_USART3_RXDMA +# ifdef CONFIG_USART3_RXDMA static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32L4_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; -# ifdef CONFIG_UART4_RXDMA +# ifdef CONFIG_UART4_RXDMA static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32L4_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; -# ifdef CONFIG_UART5_RXDMA +# ifdef CONFIG_UART5_RXDMA static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif /* This describes the state of the STM32 LPUART1 port. */ @@ -442,9 +442,9 @@ static struct stm32l4_serial_s g_lpuart1priv = { .dev = { -#if CONSOLE_UART == 1 +# if CONSOLE_UART == 1 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_LPUART1_RXBUFSIZE, @@ -455,11 +455,11 @@ static struct stm32l4_serial_s g_lpuart1priv = .size = CONFIG_LPUART1_TXBUFSIZE, .buffer = g_lpuart1txbuffer, }, -#ifdef CONFIG_LPUART1_RXDMA +# ifdef CONFIG_LPUART1_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_lpuart1priv, }, @@ -472,27 +472,27 @@ static struct stm32l4_serial_s g_lpuart1priv = .usartbase = STM32L4_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_LPUART1_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_LPUART1_RTS, -#endif -#ifdef CONFIG_LPUART1_RXDMA +# endif +# ifdef CONFIG_LPUART1_RXDMA .rxdma_channel = DMAMAP_LPUART1_RX, .rxfifo = g_lpuart1rxfifo, -#endif - -#ifdef CONFIG_LPUART1_RS485 - .rs485_dir_gpio = GPIO_LPUART1_RS485_DIR, -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_LPUART1_RS485 + .rs485_dir_gpio = GPIO_LPUART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -503,9 +503,9 @@ static struct stm32l4_serial_s g_usart1priv = { .dev = { -#if CONSOLE_UART == 2 +# if CONSOLE_UART == 2 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART1_RXBUFSIZE, @@ -516,11 +516,11 @@ static struct stm32l4_serial_s g_usart1priv = .size = CONFIG_USART1_TXBUFSIZE, .buffer = g_usart1txbuffer, }, -#ifdef CONFIG_USART1_RXDMA +# ifdef CONFIG_USART1_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart1priv, }, @@ -533,27 +533,27 @@ static struct stm32l4_serial_s g_usart1priv = .usartbase = STM32L4_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART1_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART1_RTS, -#endif -#ifdef CONFIG_USART1_RXDMA +# endif +# ifdef CONFIG_USART1_RXDMA .rxdma_channel = DMAMAP_USART1_RX, .rxfifo = g_usart1rxfifo, -#endif - -#ifdef CONFIG_USART1_RS485 - .rs485_dir_gpio = GPIO_USART1_RS485_DIR, -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART1_RS485 + .rs485_dir_gpio = GPIO_USART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -564,9 +564,9 @@ static struct stm32l4_serial_s g_usart2priv = { .dev = { -#if CONSOLE_UART == 3 +# if CONSOLE_UART == 3 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART2_RXBUFSIZE, @@ -577,11 +577,11 @@ static struct stm32l4_serial_s g_usart2priv = .size = CONFIG_USART2_TXBUFSIZE, .buffer = g_usart2txbuffer, }, -#ifdef CONFIG_USART2_RXDMA +# ifdef CONFIG_USART2_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart2priv, }, @@ -594,27 +594,27 @@ static struct stm32l4_serial_s g_usart2priv = .usartbase = STM32L4_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART2_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART2_RTS, -#endif -#ifdef CONFIG_USART2_RXDMA +# endif +# ifdef CONFIG_USART2_RXDMA .rxdma_channel = DMAMAP_USART2_RX, .rxfifo = g_usart2rxfifo, -#endif - -#ifdef CONFIG_USART2_RS485 - .rs485_dir_gpio = GPIO_USART2_RS485_DIR, -# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART2_RS485 + .rs485_dir_gpio = GPIO_USART2_RS485_DIR, +# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -625,9 +625,9 @@ static struct stm32l4_serial_s g_usart3priv = { .dev = { -#if CONSOLE_UART == 4 +# if CONSOLE_UART == 4 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART3_RXBUFSIZE, @@ -638,11 +638,11 @@ static struct stm32l4_serial_s g_usart3priv = .size = CONFIG_USART3_TXBUFSIZE, .buffer = g_usart3txbuffer, }, -#ifdef CONFIG_USART3_RXDMA +# ifdef CONFIG_USART3_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart3priv, }, @@ -655,27 +655,27 @@ static struct stm32l4_serial_s g_usart3priv = .usartbase = STM32L4_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART3_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART3_RTS, -#endif -#ifdef CONFIG_USART3_RXDMA +# endif +# ifdef CONFIG_USART3_RXDMA .rxdma_channel = DMAMAP_USART3_RX, .rxfifo = g_usart3rxfifo, -#endif - -#ifdef CONFIG_USART3_RS485 - .rs485_dir_gpio = GPIO_USART3_RS485_DIR, -# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART3_RS485 + .rs485_dir_gpio = GPIO_USART3_RS485_DIR, +# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -686,9 +686,9 @@ static struct stm32l4_serial_s g_uart4priv = { .dev = { -#if CONSOLE_UART == 5 +# if CONSOLE_UART == 5 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_UART4_RXBUFSIZE, @@ -699,11 +699,11 @@ static struct stm32l4_serial_s g_uart4priv = .size = CONFIG_UART4_TXBUFSIZE, .buffer = g_uart4txbuffer, }, -#ifdef CONFIG_UART4_RXDMA +# ifdef CONFIG_UART4_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart4priv, }, @@ -711,32 +711,32 @@ static struct stm32l4_serial_s g_uart4priv = .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_UART4_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART4_RTS, -#endif +# endif .baud = CONFIG_UART4_BAUD, .apbclock = STM32L4_PCLK1_FREQUENCY, .usartbase = STM32L4_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, -#ifdef CONFIG_UART4_RXDMA +# ifdef CONFIG_UART4_RXDMA .rxdma_channel = DMAMAP_UART4_RX, .rxfifo = g_uart4rxfifo, -#endif - -#ifdef CONFIG_UART4_RS485 - .rs485_dir_gpio = GPIO_UART4_RS485_DIR, -# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_UART4_RS485 + .rs485_dir_gpio = GPIO_UART4_RS485_DIR, +# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -747,9 +747,9 @@ static struct stm32l4_serial_s g_uart5priv = { .dev = { -#if CONSOLE_UART == 6 +# if CONSOLE_UART == 6 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_UART5_RXBUFSIZE, @@ -760,11 +760,11 @@ static struct stm32l4_serial_s g_uart5priv = .size = CONFIG_UART5_TXBUFSIZE, .buffer = g_uart5txbuffer, }, -#ifdef CONFIG_UART5_RXDMA +# ifdef CONFIG_UART5_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart5priv, }, @@ -772,32 +772,32 @@ static struct stm32l4_serial_s g_uart5priv = .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_UART5_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART5_RTS, -#endif +# endif .baud = CONFIG_UART5_BAUD, .apbclock = STM32L4_PCLK1_FREQUENCY, .usartbase = STM32L4_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, -#ifdef CONFIG_UART5_RXDMA +# ifdef CONFIG_UART5_RXDMA .rxdma_channel = DMAMAP_UART5_RX, .rxfifo = g_uart5rxfifo, -#endif - -#ifdef CONFIG_UART5_RS485 - .rs485_dir_gpio = GPIO_UART5_RS485_DIR, -# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_UART5_RS485 + .rs485_dir_gpio = GPIO_UART5_RS485_DIR, +# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.c b/arch/arm/src/stm32l4/stm32l4_usbdev.c index 7e7c83d115..af8c7579c0 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbdev.c +++ b/arch/arm/src/stm32l4/stm32l4_usbdev.c @@ -355,10 +355,10 @@ static void stm32l4_putreg(uint16_t val, uint32_t addr); static void stm32l4_checksetup(void); static void stm32l4_dumpep(int epno); #else -# define stm32l4_getreg(addr) getreg16(addr) -# define stm32l4_putreg(val,addr) putreg16(val,addr) -# define stm32l4_checksetup() -# define stm32l4_dumpep(epno) +# define stm32l4_getreg(addr) getreg16(addr) +# define stm32l4_putreg(val,addr) putreg16(val,addr) +# define stm32l4_checksetup() +# define stm32l4_dumpep(epno) #endif /* Low-Level Helpers ********************************************************/ diff --git a/arch/arm/src/stm32l5/stm32l5_lse.c b/arch/arm/src/stm32l5/stm32l5_lse.c index 3bc595b305..486ecf84af 100644 --- a/arch/arm/src/stm32l5/stm32l5_lse.c +++ b/arch/arm/src/stm32l5/stm32l5_lse.c @@ -36,10 +36,10 @@ #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) #ifdef CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 -# error "Invalid LSE drive capability setting" -#endif +# if CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +# error "Invalid LSE drive capability setting" +# endif #endif /**************************************************************************** diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index c7af93c502..ee3e466183 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -358,9 +358,9 @@ static const struct uart_ops_s g_uart_ops = .receive = stm32l5serial_receive, .rxint = stm32l5serial_rxint, .rxavailable = stm32l5serial_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL +# ifdef CONFIG_SERIAL_IFLOWCONTROL .rxflowcontrol = stm32l5serial_rxflowcontrol, -#endif +# endif .send = stm32l5serial_send, .txint = stm32l5serial_txint, .txready = stm32l5serial_txready, @@ -379,9 +379,9 @@ static const struct uart_ops_s g_uart_dma_ops = .receive = stm32l5serial_dmareceive, .rxint = stm32l5serial_dmarxint, .rxavailable = stm32l5serial_dmarxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL +# ifdef CONFIG_SERIAL_IFLOWCONTROL .rxflowcontrol = stm32l5serial_rxflowcontrol, -#endif +# endif .send = stm32l5serial_send, .txint = stm32l5serial_txint, .txready = stm32l5serial_txready, @@ -394,49 +394,49 @@ static const struct uart_ops_s g_uart_dma_ops = #ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; -# ifdef CONFIG_LPUART1_RXDMA +# ifdef CONFIG_LPUART1_RXDMA static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32L5_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; -# ifdef CONFIG_USART1_RXDMA +# ifdef CONFIG_USART1_RXDMA static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32L5_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; -# ifdef CONFIG_USART2_RXDMA +# ifdef CONFIG_USART2_RXDMA static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32L5_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; -# ifdef CONFIG_USART3_RXDMA +# ifdef CONFIG_USART3_RXDMA static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32L5_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; -# ifdef CONFIG_UART4_RXDMA +# ifdef CONFIG_UART4_RXDMA static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32L5_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; -# ifdef CONFIG_UART5_RXDMA +# ifdef CONFIG_UART5_RXDMA static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif /* This describes the state of the STM32 USART1 ports. */ @@ -446,9 +446,9 @@ static struct stm32l5_serial_s g_lpuart1priv = { .dev = { -#if CONSOLE_UART == 1 +# if CONSOLE_UART == 1 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_LPUART1_RXBUFSIZE, @@ -459,11 +459,11 @@ static struct stm32l5_serial_s g_lpuart1priv = .size = CONFIG_LPUART1_TXBUFSIZE, .buffer = g_lpuart1txbuffer, }, -#ifdef CONFIG_LPUART1_RXDMA +# ifdef CONFIG_LPUART1_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_lpuart1priv, }, @@ -476,27 +476,27 @@ static struct stm32l5_serial_s g_lpuart1priv = .usartbase = STM32L5_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_LPUART1_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_LPUART1_RTS, -#endif -#ifdef CONFIG_LPUART1_RXDMA +# endif +# ifdef CONFIG_LPUART1_RXDMA .rxdma_channel = DMAMAP_LPUSART_RX, .rxfifo = g_lpuart1rxfifo, -#endif - -#ifdef CONFIG_USART1_RS485 - .rs485_dir_gpio = GPIO_LPUART1_RS485_DIR, -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART1_RS485 + .rs485_dir_gpio = GPIO_LPUART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -505,9 +505,9 @@ static struct stm32l5_serial_s g_usart1priv = { .dev = { -#if CONSOLE_UART == 2 +# if CONSOLE_UART == 2 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART1_RXBUFSIZE, @@ -518,11 +518,11 @@ static struct stm32l5_serial_s g_usart1priv = .size = CONFIG_USART1_TXBUFSIZE, .buffer = g_usart1txbuffer, }, -#ifdef CONFIG_USART1_RXDMA +# ifdef CONFIG_USART1_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart1priv, }, @@ -535,27 +535,27 @@ static struct stm32l5_serial_s g_usart1priv = .usartbase = STM32L5_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART1_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART1_RTS, -#endif -#ifdef CONFIG_USART1_RXDMA +# endif +# ifdef CONFIG_USART1_RXDMA .rxdma_channel = DMAMAP_USART1_RX, .rxfifo = g_usart1rxfifo, -#endif - -#ifdef CONFIG_USART1_RS485 - .rs485_dir_gpio = GPIO_USART1_RS485_DIR, -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART1_RS485 + .rs485_dir_gpio = GPIO_USART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -566,9 +566,9 @@ static struct stm32l5_serial_s g_usart2priv = { .dev = { -#if CONSOLE_UART == 3 +# if CONSOLE_UART == 3 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART2_RXBUFSIZE, @@ -579,11 +579,11 @@ static struct stm32l5_serial_s g_usart2priv = .size = CONFIG_USART2_TXBUFSIZE, .buffer = g_usart2txbuffer, }, -#ifdef CONFIG_USART2_RXDMA +# ifdef CONFIG_USART2_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart2priv, }, @@ -596,27 +596,27 @@ static struct stm32l5_serial_s g_usart2priv = .usartbase = STM32L5_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART2_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART2_RTS, -#endif -#ifdef CONFIG_USART2_RXDMA +# endif +# ifdef CONFIG_USART2_RXDMA .rxdma_channel = DMAMAP_USART2_RX, .rxfifo = g_usart2rxfifo, -#endif - -#ifdef CONFIG_USART2_RS485 - .rs485_dir_gpio = GPIO_USART2_RS485_DIR, -# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART2_RS485 + .rs485_dir_gpio = GPIO_USART2_RS485_DIR, +# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -627,9 +627,9 @@ static struct stm32l5_serial_s g_usart3priv = { .dev = { -#if CONSOLE_UART == 4 +# if CONSOLE_UART == 4 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART3_RXBUFSIZE, @@ -640,11 +640,11 @@ static struct stm32l5_serial_s g_usart3priv = .size = CONFIG_USART3_TXBUFSIZE, .buffer = g_usart3txbuffer, }, -#ifdef CONFIG_USART3_RXDMA +# ifdef CONFIG_USART3_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart3priv, }, @@ -657,27 +657,27 @@ static struct stm32l5_serial_s g_usart3priv = .usartbase = STM32L5_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART3_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART3_RTS, -#endif -#ifdef CONFIG_USART3_RXDMA +# endif +# ifdef CONFIG_USART3_RXDMA .rxdma_channel = DMAMAP_USART3_RX, .rxfifo = g_usart3rxfifo, -#endif - -#ifdef CONFIG_USART3_RS485 - .rs485_dir_gpio = GPIO_USART3_RS485_DIR, -# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART3_RS485 + .rs485_dir_gpio = GPIO_USART3_RS485_DIR, +# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -688,9 +688,9 @@ static struct stm32l5_serial_s g_uart4priv = { .dev = { -#if CONSOLE_UART == 5 +# if CONSOLE_UART == 5 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_UART4_RXBUFSIZE, @@ -701,11 +701,11 @@ static struct stm32l5_serial_s g_uart4priv = .size = CONFIG_UART4_TXBUFSIZE, .buffer = g_uart4txbuffer, }, -#ifdef CONFIG_UART4_RXDMA +# ifdef CONFIG_UART4_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart4priv, }, @@ -713,32 +713,32 @@ static struct stm32l5_serial_s g_uart4priv = .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_UART4_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART4_RTS, -#endif +# endif .baud = CONFIG_UART4_BAUD, .apbclock = STM32L5_PCLK1_FREQUENCY, .usartbase = STM32L5_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, -#ifdef CONFIG_UART4_RXDMA +# ifdef CONFIG_UART4_RXDMA .rxdma_channel = DMAMAP_UART4_RX, .rxfifo = g_uart4rxfifo, -#endif - -#ifdef CONFIG_UART4_RS485 - .rs485_dir_gpio = GPIO_UART4_RS485_DIR, -# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_UART4_RS485 + .rs485_dir_gpio = GPIO_UART4_RS485_DIR, +# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -749,9 +749,9 @@ static struct stm32l5_serial_s g_uart5priv = { .dev = { -#if CONSOLE_UART == 6 +# if CONSOLE_UART == 6 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_UART5_RXBUFSIZE, @@ -762,11 +762,11 @@ static struct stm32l5_serial_s g_uart5priv = .size = CONFIG_UART5_TXBUFSIZE, .buffer = g_uart5txbuffer, }, -#ifdef CONFIG_UART5_RXDMA +# ifdef CONFIG_UART5_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart5priv, }, @@ -774,32 +774,32 @@ static struct stm32l5_serial_s g_uart5priv = .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_UART5_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART5_RTS, -#endif +# endif .baud = CONFIG_UART5_BAUD, .apbclock = STM32L5_PCLK1_FREQUENCY, .usartbase = STM32L5_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, -#ifdef CONFIG_UART5_RXDMA +# ifdef CONFIG_UART5_RXDMA .rxdma_channel = DMAMAP_UART5_RX, .rxfifo = g_uart5rxfifo, -#endif - -#ifdef CONFIG_UART5_RS485 - .rs485_dir_gpio = GPIO_UART5_RS485_DIR, -# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_UART5_RS485 + .rs485_dir_gpio = GPIO_UART5_RS485_DIR, +# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif diff --git a/arch/arm/src/stm32u5/stm32_lse.c b/arch/arm/src/stm32u5/stm32_lse.c index 938bdaf85d..6729eed399 100644 --- a/arch/arm/src/stm32u5/stm32_lse.c +++ b/arch/arm/src/stm32u5/stm32_lse.c @@ -36,10 +36,10 @@ #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) #ifdef CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 -# error "Invalid LSE drive capability setting" -#endif +# if CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +# error "Invalid LSE drive capability setting" +# endif #endif /**************************************************************************** diff --git a/arch/arm/src/stm32u5/stm32_serial.c b/arch/arm/src/stm32u5/stm32_serial.c index 98357025bb..5ce2fecfd7 100644 --- a/arch/arm/src/stm32u5/stm32_serial.c +++ b/arch/arm/src/stm32u5/stm32_serial.c @@ -358,9 +358,9 @@ static const struct uart_ops_s g_uart_ops = .receive = stm32serial_receive, .rxint = stm32serial_rxint, .rxavailable = stm32serial_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL +# ifdef CONFIG_SERIAL_IFLOWCONTROL .rxflowcontrol = stm32serial_rxflowcontrol, -#endif +# endif .send = stm32serial_send, .txint = stm32serial_txint, .txready = stm32serial_txready, @@ -379,9 +379,9 @@ static const struct uart_ops_s g_uart_dma_ops = .receive = stm32serial_dmareceive, .rxint = stm32serial_dmarxint, .rxavailable = stm32serial_dmarxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL +# ifdef CONFIG_SERIAL_IFLOWCONTROL .rxflowcontrol = stm32serial_rxflowcontrol, -#endif +# endif .send = stm32serial_send, .txint = stm32serial_txint, .txready = stm32serial_txready, @@ -394,49 +394,49 @@ static const struct uart_ops_s g_uart_dma_ops = #ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; -# ifdef CONFIG_LPUART1_RXDMA +# ifdef CONFIG_LPUART1_RXDMA static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32U5_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; -# ifdef CONFIG_USART1_RXDMA +# ifdef CONFIG_USART1_RXDMA static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32U5_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; -# ifdef CONFIG_USART2_RXDMA +# ifdef CONFIG_USART2_RXDMA static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32U5_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; -# ifdef CONFIG_USART3_RXDMA +# ifdef CONFIG_USART3_RXDMA static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32U5_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; -# ifdef CONFIG_UART4_RXDMA +# ifdef CONFIG_UART4_RXDMA static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32U5_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; -# ifdef CONFIG_UART5_RXDMA +# ifdef CONFIG_UART5_RXDMA static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif /* This describes the state of the STM32 USART1 ports. */ @@ -446,9 +446,9 @@ static struct stm32_serial_s g_lpuart1priv = { .dev = { -#if CONSOLE_UART == 1 +# if CONSOLE_UART == 1 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_LPUART1_RXBUFSIZE, @@ -459,11 +459,11 @@ static struct stm32_serial_s g_lpuart1priv = .size = CONFIG_LPUART1_TXBUFSIZE, .buffer = g_lpuart1txbuffer, }, -#ifdef CONFIG_LPUART1_RXDMA +# ifdef CONFIG_LPUART1_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_lpuart1priv, }, @@ -476,27 +476,27 @@ static struct stm32_serial_s g_lpuart1priv = .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_LPUART1_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_LPUART1_RTS, -#endif -#ifdef CONFIG_LPUART1_RXDMA +# endif +# ifdef CONFIG_LPUART1_RXDMA .rxdma_channel = DMAMAP_LPUSART_RX, .rxfifo = g_lpuart1rxfifo, -#endif - -#ifdef CONFIG_USART1_RS485 - .rs485_dir_gpio = GPIO_LPUART1_RS485_DIR, -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART1_RS485 + .rs485_dir_gpio = GPIO_LPUART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -505,9 +505,9 @@ static struct stm32_serial_s g_usart1priv = { .dev = { -#if CONSOLE_UART == 2 +# if CONSOLE_UART == 2 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART1_RXBUFSIZE, @@ -518,11 +518,11 @@ static struct stm32_serial_s g_usart1priv = .size = CONFIG_USART1_TXBUFSIZE, .buffer = g_usart1txbuffer, }, -#ifdef CONFIG_USART1_RXDMA +# ifdef CONFIG_USART1_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart1priv, }, @@ -535,27 +535,27 @@ static struct stm32_serial_s g_usart1priv = .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART1_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART1_RTS, -#endif -#ifdef CONFIG_USART1_RXDMA +# endif +# ifdef CONFIG_USART1_RXDMA .rxdma_channel = DMAMAP_USART1_RX, .rxfifo = g_usart1rxfifo, -#endif - -#ifdef CONFIG_USART1_RS485 - .rs485_dir_gpio = GPIO_USART1_RS485_DIR, -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART1_RS485 + .rs485_dir_gpio = GPIO_USART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -566,9 +566,9 @@ static struct stm32_serial_s g_usart2priv = { .dev = { -#if CONSOLE_UART == 3 +# if CONSOLE_UART == 3 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART2_RXBUFSIZE, @@ -579,11 +579,11 @@ static struct stm32_serial_s g_usart2priv = .size = CONFIG_USART2_TXBUFSIZE, .buffer = g_usart2txbuffer, }, -#ifdef CONFIG_USART2_RXDMA +# ifdef CONFIG_USART2_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart2priv, }, @@ -596,27 +596,27 @@ static struct stm32_serial_s g_usart2priv = .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART2_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART2_RTS, -#endif -#ifdef CONFIG_USART2_RXDMA +# endif +# ifdef CONFIG_USART2_RXDMA .rxdma_channel = DMAMAP_USART2_RX, .rxfifo = g_usart2rxfifo, -#endif - -#ifdef CONFIG_USART2_RS485 - .rs485_dir_gpio = GPIO_USART2_RS485_DIR, -# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART2_RS485 + .rs485_dir_gpio = GPIO_USART2_RS485_DIR, +# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -627,9 +627,9 @@ static struct stm32_serial_s g_usart3priv = { .dev = { -#if CONSOLE_UART == 4 +# if CONSOLE_UART == 4 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART3_RXBUFSIZE, @@ -640,11 +640,11 @@ static struct stm32_serial_s g_usart3priv = .size = CONFIG_USART3_TXBUFSIZE, .buffer = g_usart3txbuffer, }, -#ifdef CONFIG_USART3_RXDMA +# ifdef CONFIG_USART3_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart3priv, }, @@ -657,27 +657,27 @@ static struct stm32_serial_s g_usart3priv = .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART3_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART3_RTS, -#endif -#ifdef CONFIG_USART3_RXDMA +# endif +# ifdef CONFIG_USART3_RXDMA .rxdma_channel = DMAMAP_USART3_RX, .rxfifo = g_usart3rxfifo, -#endif - -#ifdef CONFIG_USART3_RS485 - .rs485_dir_gpio = GPIO_USART3_RS485_DIR, -# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART3_RS485 + .rs485_dir_gpio = GPIO_USART3_RS485_DIR, +# if (CONFIG_USART3_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -688,9 +688,9 @@ static struct stm32_serial_s g_uart4priv = { .dev = { -#if CONSOLE_UART == 5 +# if CONSOLE_UART == 5 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_UART4_RXBUFSIZE, @@ -701,11 +701,11 @@ static struct stm32_serial_s g_uart4priv = .size = CONFIG_UART4_TXBUFSIZE, .buffer = g_uart4txbuffer, }, -#ifdef CONFIG_UART4_RXDMA +# ifdef CONFIG_UART4_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart4priv, }, @@ -713,32 +713,32 @@ static struct stm32_serial_s g_uart4priv = .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_UART4_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART4_RTS, -#endif +# endif .baud = CONFIG_UART4_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, -#ifdef CONFIG_UART4_RXDMA +# ifdef CONFIG_UART4_RXDMA .rxdma_channel = DMAMAP_UART4_RX, .rxfifo = g_uart4rxfifo, -#endif - -#ifdef CONFIG_UART4_RS485 - .rs485_dir_gpio = GPIO_UART4_RS485_DIR, -# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_UART4_RS485 + .rs485_dir_gpio = GPIO_UART4_RS485_DIR, +# if (CONFIG_UART4_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -749,9 +749,9 @@ static struct stm32_serial_s g_uart5priv = { .dev = { -#if CONSOLE_UART == 6 +# if CONSOLE_UART == 6 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_UART5_RXBUFSIZE, @@ -762,11 +762,11 @@ static struct stm32_serial_s g_uart5priv = .size = CONFIG_UART5_TXBUFSIZE, .buffer = g_uart5txbuffer, }, -#ifdef CONFIG_UART5_RXDMA +# ifdef CONFIG_UART5_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_uart5priv, }, @@ -774,32 +774,32 @@ static struct stm32_serial_s g_uart5priv = .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_UART5_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART5_RTS, -#endif +# endif .baud = CONFIG_UART5_BAUD, .apbclock = STM32_PCLK1_FREQUENCY, .usartbase = STM32_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, -#ifdef CONFIG_UART5_RXDMA +# ifdef CONFIG_UART5_RXDMA .rxdma_channel = DMAMAP_UART5_RX, .rxfifo = g_uart5rxfifo, -#endif - -#ifdef CONFIG_UART5_RS485 - .rs485_dir_gpio = GPIO_UART5_RS485_DIR, -# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_UART5_RS485 + .rs485_dir_gpio = GPIO_UART5_RS485_DIR, +# if (CONFIG_UART5_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c index b757e68a0f..f0c0712d59 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c @@ -34,17 +34,17 @@ ****************************************************************************/ #ifdef CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 -# error "Invalid LSE drive capability setting" -#endif +# if CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +# error "Invalid LSE drive capability setting" +# endif #endif #ifdef CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 -# error "Invalid LSE drive capability setting" -#endif +# if CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +# error "Invalid LSE drive capability setting" +# endif #endif /**************************************************************************** diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.h b/arch/arm/src/stm32wb/stm32wb_rtc.h index 611ed08a3e..a7181cf9d6 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/stm32wb_rtc.h @@ -42,7 +42,7 @@ * of 16384 Hz */ #if !defined(CONFIG_STM32WB_RTC_MAGIC) -# define CONFIG_STM32WB_RTC_MAGIC (0xfacefeee) +# define CONFIG_STM32WB_RTC_MAGIC (0xfacefeee) #endif #if !defined(CONFIG_STM32WB_RTC_MAGIC_TIME_SET) @@ -50,7 +50,7 @@ #endif #if !defined(CONFIG_STM32WB_RTC_MAGIC_REG) -# define CONFIG_STM32WB_RTC_MAGIC_REG (0) +# define CONFIG_STM32WB_RTC_MAGIC_REG (0) #endif #define RTC_MAGIC CONFIG_STM32WB_RTC_MAGIC diff --git a/arch/arm/src/stm32wb/stm32wb_serial.c b/arch/arm/src/stm32wb/stm32wb_serial.c index 0a2295da3c..889061620c 100644 --- a/arch/arm/src/stm32wb/stm32wb_serial.c +++ b/arch/arm/src/stm32wb/stm32wb_serial.c @@ -334,17 +334,17 @@ static const struct uart_ops_s g_uart_dma_ops = #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; -# ifdef CONFIG_LPUART1_RXDMA +# ifdef CONFIG_LPUART1_RXDMA static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32WB_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; -# ifdef CONFIG_USART1_RXDMA +# ifdef CONFIG_USART1_RXDMA static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif /* This describes the state of the STM32WB LPUART1 port. */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_lse.c b/arch/arm/src/stm32wl5/stm32wl5_lse.c index 509290cff9..1035d49df6 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lse.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lse.c @@ -37,10 +37,10 @@ #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) #ifdef CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 -# error "Invalid LSE drive capability setting" -#endif +# if CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +# error "Invalid LSE drive capability setting" +# endif #endif /**************************************************************************** diff --git a/arch/arm/src/stm32wl5/stm32wl5_serial.c b/arch/arm/src/stm32wl5/stm32wl5_serial.c index 5d0deaf538..660ca12424 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_serial.c +++ b/arch/arm/src/stm32wl5/stm32wl5_serial.c @@ -366,25 +366,25 @@ static const struct uart_ops_s g_uart_dma_ops = #ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; -# ifdef CONFIG_LPUART1_RXDMA +# ifdef CONFIG_LPUART1_RXDMA static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; -# ifdef CONFIG_USART1_RXDMA +# ifdef CONFIG_USART1_RXDMA static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif #ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; -# ifdef CONFIG_USART2_RXDMA +# ifdef CONFIG_USART2_RXDMA static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; -# endif +# endif #endif /* This describes the state of the STM32 USART1 ports. */ @@ -394,9 +394,9 @@ static struct stm32wl5_serial_s g_lpuart1priv = { .dev = { -#if CONSOLE_UART == 1 +# if CONSOLE_UART == 1 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_LPUART1_RXBUFSIZE, @@ -407,11 +407,11 @@ static struct stm32wl5_serial_s g_lpuart1priv = .size = CONFIG_LPUART1_TXBUFSIZE, .buffer = g_lpuart1txbuffer, }, -#ifdef CONFIG_LPUART1_RXDMA +# ifdef CONFIG_LPUART1_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_lpuart1priv, }, @@ -424,27 +424,27 @@ static struct stm32wl5_serial_s g_lpuart1priv = .usartbase = STM32WL5_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_LPUART1_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_LPUART1_RTS, -#endif -#ifdef CONFIG_LPUART1_RXDMA +# endif +# ifdef CONFIG_LPUART1_RXDMA .rxdma_channel = DMAMAP_LPUSART_RX, .rxfifo = g_lpuart1rxfifo, -#endif - -#ifdef CONFIG_USART1_RS485 - .rs485_dir_gpio = GPIO_LPUART1_RS485_DIR, -# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART1_RS485 + .rs485_dir_gpio = GPIO_LPUART1_RS485_DIR, +# if (CONFIG_USART1_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif @@ -453,9 +453,9 @@ static struct stm32wl5_serial_s g_usart1priv = { .dev = { -#if CONSOLE_UART == 2 +# if CONSOLE_UART == 2 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART1_RXBUFSIZE, @@ -466,11 +466,11 @@ static struct stm32wl5_serial_s g_usart1priv = .size = CONFIG_USART1_TXBUFSIZE, .buffer = g_usart1txbuffer, }, -#ifdef CONFIG_USART1_RXDMA +# ifdef CONFIG_USART1_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart1priv, }, @@ -483,18 +483,18 @@ static struct stm32wl5_serial_s g_usart1priv = .usartbase = STM32WL5_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART1_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART1_RTS, -#endif -#ifdef CONFIG_USART1_RXDMA +# endif +# ifdef CONFIG_USART1_RXDMA .rxdma_channel = DMAMAP_USART1_RX, .rxfifo = g_usart1rxfifo, -#endif +# endif #ifdef CONFIG_USART1_RS485 .rs485_dir_gpio = GPIO_USART1_RS485_DIR, @@ -514,9 +514,9 @@ static struct stm32wl5_serial_s g_usart2priv = { .dev = { -#if CONSOLE_UART == 3 +# if CONSOLE_UART == 3 .isconsole = true, -#endif +# endif .recv = { .size = CONFIG_USART2_RXBUFSIZE, @@ -527,11 +527,11 @@ static struct stm32wl5_serial_s g_usart2priv = .size = CONFIG_USART2_TXBUFSIZE, .buffer = g_usart2txbuffer, }, -#ifdef CONFIG_USART2_RXDMA +# ifdef CONFIG_USART2_RXDMA .ops = &g_uart_dma_ops, -#else +# else .ops = &g_uart_ops, -#endif +# endif .priv = &g_usart2priv, }, @@ -544,27 +544,27 @@ static struct stm32wl5_serial_s g_usart2priv = .usartbase = STM32WL5_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, -#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) .oflow = true, .cts_gpio = GPIO_USART2_CTS, -#endif -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART2_RTS, -#endif -#ifdef CONFIG_USART2_RXDMA +# endif +# ifdef CONFIG_USART2_RXDMA .rxdma_channel = DMAMAP_USART2_RX, .rxfifo = g_usart2rxfifo, -#endif - -#ifdef CONFIG_USART2_RS485 - .rs485_dir_gpio = GPIO_USART2_RS485_DIR, -# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) - .rs485_dir_polarity = false, -# else - .rs485_dir_polarity = true, # endif -#endif + +# ifdef CONFIG_USART2_RS485 + .rs485_dir_gpio = GPIO_USART2_RS485_DIR, +# if (CONFIG_USART2_RS485_DIR_POLARITY == 0) + .rs485_dir_polarity = false, +# else + .rs485_dir_polarity = true, +# endif +# endif }; #endif diff --git a/arch/arm/src/tiva/common/tiva_sock_can.c b/arch/arm/src/tiva/common/tiva_sock_can.c index 033a5dfa4f..60ebd03e78 100644 --- a/arch/arm/src/tiva/common/tiva_sock_can.c +++ b/arch/arm/src/tiva/common/tiva_sock_can.c @@ -1774,12 +1774,12 @@ static int tivacan_setup(struct net_driver_s *dev) case 0: tivacan_bittiming_set(dev, CONFIG_TIVA_CAN0_BAUD * 1000); break; -# endif /* CONFIG_TIVA_CAN0 */ +#endif /* CONFIG_TIVA_CAN0 */ #ifdef CONFIG_TIVA_CAN1 case 1: tivacan_bittiming_set(dev, CONFIG_TIVA_CAN1_BAUD * 1000); break; -# endif /* CONFIG_TIVA_CAN1 */ +#endif /* CONFIG_TIVA_CAN1 */ } nxmutex_lock(&canmod->thd_iface_lock); diff --git a/arch/arm/src/tiva/tiva_gpio.h b/arch/arm/src/tiva/tiva_gpio.h index 4ac0730b2a..4a2919ebac 100644 --- a/arch/arm/src/tiva/tiva_gpio.h +++ b/arch/arm/src/tiva/tiva_gpio.h @@ -122,7 +122,7 @@ void tiva_gpio_lockport(pinconfig_t pinconfig, bool lock); #ifdef CONFIG_DEBUG_GPIO_INFO void tiva_gpio_dumpconfig(pinconfig_t pinconfig); #else -# define tiva_gpio_dumpconfig(p) +# define tiva_gpio_dumpconfig(p) #endif #ifdef CONFIG_TIVA_GPIO_IRQS diff --git a/arch/arm/src/tiva/tm4c/tm4c_ethernet.c b/arch/arm/src/tiva/tm4c/tm4c_ethernet.c index df9049d7ba..ee1d7efdbc 100644 --- a/arch/arm/src/tiva/tm4c/tm4c_ethernet.c +++ b/arch/arm/src/tiva/tm4c/tm4c_ethernet.c @@ -674,9 +674,9 @@ static uint32_t tiva_getreg(uint32_t addr); static void tiva_putreg(uint32_t val, uint32_t addr); static void tiva_checksetup(void); #else -# define tiva_getreg(addr) getreg32(addr) -# define tiva_putreg(val,addr) putreg32(val,addr) -# define tiva_checksetup() +# define tiva_getreg(addr) getreg32(addr) +# define tiva_putreg(val,addr) putreg32(val,addr) +# define tiva_checksetup() #endif /* Free buffer management */ diff --git a/arch/arm/src/tlsr82/tc32/tc32_initialstate.c b/arch/arm/src/tlsr82/tc32/tc32_initialstate.c index 404b2b9221..7a36db4523 100644 --- a/arch/arm/src/tlsr82/tc32/tc32_initialstate.c +++ b/arch/arm/src/tlsr82/tc32/tc32_initialstate.c @@ -144,9 +144,9 @@ void up_initial_state(struct tcb_s *tcb) /* Enable or disable interrupts, based on user configuration */ -# ifdef CONFIG_SUPPRESS_INTERRUPTS +#ifdef CONFIG_SUPPRESS_INTERRUPTS cpsr |= PSR_I_BIT; -# endif +#endif xcp->regs[REG_CPSR] = cpsr; } diff --git a/arch/arm/src/xmc4/xmc4_spi.c b/arch/arm/src/xmc4/xmc4_spi.c index 7c24edac97..efdc4a559e 100644 --- a/arch/arm/src/xmc4/xmc4_spi.c +++ b/arch/arm/src/xmc4/xmc4_spi.c @@ -222,7 +222,7 @@ static bool spi_checkreg(struct xmc4_spidev_s *spi, bool wr, uint32_t value, uint32_t address); #else -# define spi_checkreg(spi, wr, value, address) (false) +# define spi_checkreg(spi, wr, value, address) (false) #endif static inline uint32_t spi_getreg(struct xmc4_spidev_s *spi, @@ -234,7 +234,7 @@ static inline struct xmc4_spidev_s *spi_device(struct xmc4_spics_s *spics); #ifdef CONFIG_DEBUG_SPI_INFO static void spi_dumpregs(struct xmc4_spidev_s *spi, const char *msg); #else -# define spi_dumpregs(spi, msg) +# define spi_dumpregs(spi, msg) #endif static inline void spi_flush(struct xmc4_spidev_s *spi); diff --git a/arch/arm64/src/common/arm64_initialize.c b/arch/arm64/src/common/arm64_initialize.c index 16b6b2b8c9..a922569568 100644 --- a/arch/arm64/src/common/arm64_initialize.c +++ b/arch/arm64/src/common/arm64_initialize.c @@ -133,7 +133,7 @@ static void up_color_intstack(void) arm64_stack_color(ptr, INTSTACK_SIZE); } #else -# define up_color_intstack() +# define up_color_intstack() #endif /**************************************************************************** diff --git a/arch/arm64/src/common/arm64_internal.h b/arch/arm64/src/common/arm64_internal.h index 6ad103d75e..86d954d5c0 100644 --- a/arch/arm64/src/common/arm64_internal.h +++ b/arch/arm64/src/common/arm64_internal.h @@ -285,7 +285,7 @@ uint64_t *arm64_doirq(int irq, uint64_t *regs); #ifdef CONFIG_PAGING void arm64_pginitialize(void); #else /* CONFIG_PAGING */ -# define arm64_pginitialize() +# define arm64_pginitialize() #endif /* CONFIG_PAGING */ uint64_t * arm64_syscall_switch(uint64_t *regs); @@ -335,7 +335,7 @@ void weak_function arm64_dma_initialize(void); #if CONFIG_MM_REGIONS > 1 void arm64_addregion(void); #else -# define arm64_addregion() +# define arm64_addregion() #endif /* Networking */ @@ -354,7 +354,7 @@ void arm64_addregion(void); #if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void arm64_netinitialize(void); #else -# define arm64_netinitialize() +# define arm64_netinitialize() #endif /* USB */ @@ -363,8 +363,8 @@ void arm64_netinitialize(void); void arm64_usbinitialize(void); void arm64_usbuninitialize(void); #else -# define arm64_usbinitialize() -# define arm64_usbuninitialize() +# define arm64_usbinitialize() +# define arm64_usbuninitialize() #endif /* Debug */ diff --git a/arch/avr/include/avr/irq.h b/arch/avr/include/avr/irq.h index c63d776ae7..a0df8a95e2 100644 --- a/arch/avr/include/avr/irq.h +++ b/arch/avr/include/avr/irq.h @@ -79,7 +79,7 @@ #define REG_PC0 35 /* PC */ #define REG_PC1 36 #if AVR_PC_SIZE > 16 -# define REG_PC2 37 +# define REG_PC2 37 #endif #define XCPTCONTEXT_SIZE XCPTCONTEXT_REGS diff --git a/arch/avr/src/at32uc3/at32uc3_adc.h b/arch/avr/src/at32uc3/at32uc3_adc.h index 1b56d325e0..6b48b924fd 100644 --- a/arch/avr/src/at32uc3/at32uc3_adc.h +++ b/arch/avr/src/at32uc3/at32uc3_adc.h @@ -89,16 +89,16 @@ #define ADC_MR_TRGEN (1 << 0) /* Bit 0: Trigger Enable */ #define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */ #define ADC_MR_TRGSEL_MASK (7 << ADC_MR_TRGSEL_SHIFT) -# define ADC_MR_TRGSEL_TRIG(n) ((n) << ADC_MR_TRGSEL_SHIFT) /* Internal trigger n */ +# define ADC_MR_TRGSEL_TRIG(n) ((n) << ADC_MR_TRGSEL_SHIFT) /* Internal trigger n */ -# define ADC_MR_TRGSEL_TRIG0 (0 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 0 */ -# define ADC_MR_TRGSEL_TRIG1 (1 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 1 */ -# define ADC_MR_TRGSEL_TRIG2 (2 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 2 */ -# define ADC_MR_TRGSEL_TRIG3 (3 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 3 */ -# define ADC_MR_TRGSEL_TRIG4 (4 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 4 */ -# define ADC_MR_TRGSEL_TRIG5 (5 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 5 */ -# define ADC_MR_TRGSEL_TRIG6 (6 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 6 */ -# define ADC_MR_TRGSEL_EXT (7 << ADC_MR_TRGSEL_SHIFT) /* External trigger */ +# define ADC_MR_TRGSEL_TRIG0 (0 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 0 */ +# define ADC_MR_TRGSEL_TRIG1 (1 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 1 */ +# define ADC_MR_TRGSEL_TRIG2 (2 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 2 */ +# define ADC_MR_TRGSEL_TRIG3 (3 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 3 */ +# define ADC_MR_TRGSEL_TRIG4 (4 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 4 */ +# define ADC_MR_TRGSEL_TRIG5 (5 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 5 */ +# define ADC_MR_TRGSEL_TRIG6 (6 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 6 */ +# define ADC_MR_TRGSEL_EXT (7 << ADC_MR_TRGSEL_SHIFT) /* External trigger */ #define ADC_MR_LOWRES (1 << 4) /* Bit 4: Resolution */ #define ADC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */ diff --git a/arch/avr/src/common/avr_internal.h b/arch/avr/src/common/avr_internal.h index 8c31735def..ce7dc85ff5 100644 --- a/arch/avr/src/common/avr_internal.h +++ b/arch/avr/src/common/avr_internal.h @@ -46,7 +46,7 @@ /* Check if an interrupt stack size is configured */ #ifndef CONFIG_ARCH_INTERRUPTSTACK -# define CONFIG_ARCH_INTERRUPTSTACK 0 +# define CONFIG_ARCH_INTERRUPTSTACK 0 #endif /* This is the value used to mark the stack for subsequent stack monitoring @@ -125,7 +125,7 @@ void avr_lowputs(const char *str); #if CONFIG_MM_REGIONS > 1 void avr_addregion(void); #else -# define avr_addregion() +# define avr_addregion() #endif /* Defined in chip/xxx_lowinit.c. This function is called from the @@ -148,7 +148,7 @@ void avr_serialinit(void); #if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void avr_netinitialize(void); #else -# define avr_netinitialize() +# define avr_netinitialize() #endif /* Defined in chip/xxx_usbdev.c */ @@ -157,8 +157,8 @@ void avr_netinitialize(void); void avr_usbinitialize(void); void avr_usbuninitialize(void); #else -# define avr_usbinitialize() -# define avr_usbuninitialize() +# define avr_usbinitialize() +# define avr_usbuninitialize() #endif #ifdef CONFIG_STACK_COLORATION diff --git a/arch/ceva/include/xc5/irq.h b/arch/ceva/include/xc5/irq.h index a95479492e..cf77787e0a 100644 --- a/arch/ceva/include/xc5/irq.h +++ b/arch/ceva/include/xc5/irq.h @@ -139,14 +139,14 @@ struct xcptcontext uint32_t *saved_regs; -# ifdef CONFIG_BUILD_PROTECTED +# ifdef CONFIG_BUILD_PROTECTED /* This is the saved address to use when returning from a user-space * signal handler. */ uint32_t sigreturn; -# endif +# endif #endif #ifdef CONFIG_LIB_SYSCALL diff --git a/arch/ceva/include/xm6/irq.h b/arch/ceva/include/xm6/irq.h index c42d4a8249..0a735828ec 100644 --- a/arch/ceva/include/xm6/irq.h +++ b/arch/ceva/include/xm6/irq.h @@ -142,14 +142,14 @@ struct xcptcontext uint32_t *saved_regs; -# ifdef CONFIG_BUILD_PROTECTED +# ifdef CONFIG_BUILD_PROTECTED /* This is the saved address to use when returning from a user-space * signal handler. */ uint32_t sigreturn; -# endif +# endif #endif #ifdef CONFIG_LIB_SYSCALL diff --git a/arch/ceva/src/common/ceva_internal.h b/arch/ceva/src/common/ceva_internal.h index 8a2de7647e..8c07a858d7 100644 --- a/arch/ceva/src/common/ceva_internal.h +++ b/arch/ceva/src/common/ceva_internal.h @@ -272,7 +272,7 @@ void ceva_dma_initialize(void); #if CONFIG_MM_REGIONS > 1 void ceva_addregion(void); #else -# define ceva_addregion() +# define ceva_addregion() #endif /* Networking ***************************************************************/ @@ -280,7 +280,7 @@ void ceva_addregion(void); #if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void ceva_netinitialize(void); #else -# define ceva_netinitialize() +# define ceva_netinitialize() #endif /* USB **********************************************************************/ @@ -289,8 +289,8 @@ void ceva_netinitialize(void); void ceva_usbinitialize(void); void ceva_usbuninitialize(void); #else -# define ceva_usbinitialize() -# define ceva_usbuninitialize() +# define ceva_usbinitialize() +# define ceva_usbuninitialize() #endif /* Debug ********************************************************************/ diff --git a/arch/ceva/src/common/ceva_svcall.c b/arch/ceva/src/common/ceva_svcall.c index 5af40e6dfc..4142ec2e3a 100644 --- a/arch/ceva/src/common/ceva_svcall.c +++ b/arch/ceva/src/common/ceva_svcall.c @@ -60,9 +60,9 @@ int ceva_svcall(int irq, void *context, void *arg) */ #ifdef CONFIG_DEBUG_SYSCALL_INFO -# ifndef CONFIG_DEBUG_SVCALL +# ifndef CONFIG_DEBUG_SVCALL if (cmd > SYS_switch_context) -# endif +# endif { svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd); svcinfo("A0: %08x %08x %08x %08x %08x %08x %08x\n", @@ -70,11 +70,11 @@ int ceva_svcall(int irq, void *context, void *arg) regs[REG_A4], regs[REG_A5], regs[REG_A6]); svcinfo("FP: %08x LR: %08x PC: %08x IRQ: %08x OM: %08x\n", regs[REG_FP], regs[REG_LR], regs[REG_PC], regs[REG_IRQ], -# ifdef REG_OM +# ifdef REG_OM regs[REG_OM] -#else +# else 0x00000000 -#endif +# endif ); } #endif @@ -381,11 +381,11 @@ int ceva_svcall(int irq, void *context, void *arg) */ #ifdef CONFIG_DEBUG_SYSCALL_INFO -# ifndef CONFIG_DEBUG_SVCALL +# ifndef CONFIG_DEBUG_SVCALL if (cmd > SYS_switch_context) -# else +# else if (regs != CURRENT_REGS) -# endif +# endif { svcinfo("SVCall Return:\n"); svcinfo("A0: %08x %08x %08x %08x %08x %08x %08x\n", @@ -403,12 +403,12 @@ int ceva_svcall(int irq, void *context, void *arg) #endif ); } -# ifdef CONFIG_DEBUG_SVCALL +# ifdef CONFIG_DEBUG_SVCALL else { svcinfo("SVCall Return: %d\n", regs[REG_A0]); } -# endif +# endif #endif return OK; diff --git a/arch/ceva/src/xc5/xc5_hardfault.c b/arch/ceva/src/xc5/xc5_hardfault.c index 371cb88263..610ef02493 100644 --- a/arch/ceva/src/xc5/xc5_hardfault.c +++ b/arch/ceva/src/xc5/xc5_hardfault.c @@ -41,9 +41,9 @@ #define REG_DBG_GEN 0x028c #ifdef CONFIG_DEBUG_HARDFAULT -# define hfalert(format, ...) _alert(format, ##__VA_ARGS__) +# define hfalert(format, ...) _alert(format, ##__VA_ARGS__) #else -# define hfalert(x...) +# define hfalert(x...) #endif #define hfdumpreg1(reg) \ diff --git a/arch/ceva/src/xm6/xm6_hardfault.c b/arch/ceva/src/xm6/xm6_hardfault.c index 78fc72b587..fd059f15ff 100644 --- a/arch/ceva/src/xm6/xm6_hardfault.c +++ b/arch/ceva/src/xm6/xm6_hardfault.c @@ -56,9 +56,9 @@ #define REG_DBG_QMAN_ID 0x0d88 #ifdef CONFIG_DEBUG_HARDFAULT -# define hfalert(format, ...) _alert(format, ##__VA_ARGS__) +# define hfalert(format, ...) _alert(format, ##__VA_ARGS__) #else -# define hfalert(x...) +# define hfalert(x...) #endif #define hfdumpreg1(reg) \ diff --git a/arch/hc/include/hc12/types.h b/arch/hc/include/hc12/types.h index 85b08080ae..2a85a1a755 100644 --- a/arch/hc/include/hc12/types.h +++ b/arch/hc/include/hc12/types.h @@ -58,7 +58,7 @@ typedef unsigned short _uint16_t; * then an integer is 32-bits. GCC will defined __INT__ accordingly: */ -# if __INT__ == 16 +#if __INT__ == 16 typedef signed long _int32_t; typedef unsigned long _uint32_t; #else diff --git a/arch/hc/include/hcs12/types.h b/arch/hc/include/hcs12/types.h index da9ec26570..28e52459b3 100644 --- a/arch/hc/include/hcs12/types.h +++ b/arch/hc/include/hcs12/types.h @@ -59,7 +59,7 @@ typedef unsigned short _uint16_t; * then an integer is 32-bits. GCC will defined __INT__ accordingly: */ -# if __INT__ == 16 +#if __INT__ == 16 typedef signed long _int32_t; typedef unsigned long _uint32_t; #else diff --git a/arch/hc/include/m9s12/irq.h b/arch/hc/include/m9s12/irq.h index fcd1471c63..09812970bc 100644 --- a/arch/hc/include/m9s12/irq.h +++ b/arch/hc/include/m9s12/irq.h @@ -98,48 +98,48 @@ /* To conserve space, interrupts must also be configured, port by port */ -# define HCC12_IRQ_PGFIRST HCS12_IRQ_NVECTORS -# ifdef CONFIG_HCS12_PORTG_INTS -# define HCS12_IRQ_PGSET 0xff -# define HCS12_IRQ_PG0 (HCC12_IRQ_PGFIRST+0) -# define HCS12_IRQ_PG1 (HCC12_IRQ_PGFIRST+1) -# define HCS12_IRQ_PG2 (HCC12_IRQ_PGFIRST+2) -# define HCS12_IRQ_PG3 (HCC12_IRQ_PGFIRST+3) -# define HCS12_IRQ_PG4 (HCC12_IRQ_PGFIRST+4) -# define HCS12_IRQ_PG5 (HCC12_IRQ_PGFIRST+5) -# define HCS12_IRQ_PG6 (HCC12_IRQ_PGFIRST+6) -# define HCS12_IRQ_PG7 (HCC12_IRQ_PGFIRST+7) -# define HCC12_IRQ_PHFIRST (HCC12_IRQ_PGFIRST+8) -# else -# define HCC12_IRQ_PHFIRST HCC12_IRQ_PGFIRST -# endif +# define HCC12_IRQ_PGFIRST HCS12_IRQ_NVECTORS +# ifdef CONFIG_HCS12_PORTG_INTS +# define HCS12_IRQ_PGSET 0xff +# define HCS12_IRQ_PG0 (HCC12_IRQ_PGFIRST+0) +# define HCS12_IRQ_PG1 (HCC12_IRQ_PGFIRST+1) +# define HCS12_IRQ_PG2 (HCC12_IRQ_PGFIRST+2) +# define HCS12_IRQ_PG3 (HCC12_IRQ_PGFIRST+3) +# define HCS12_IRQ_PG4 (HCC12_IRQ_PGFIRST+4) +# define HCS12_IRQ_PG5 (HCC12_IRQ_PGFIRST+5) +# define HCS12_IRQ_PG6 (HCC12_IRQ_PGFIRST+6) +# define HCS12_IRQ_PG7 (HCC12_IRQ_PGFIRST+7) +# define HCC12_IRQ_PHFIRST (HCC12_IRQ_PGFIRST+8) +# else +# define HCC12_IRQ_PHFIRST HCC12_IRQ_PGFIRST +# endif -# ifdef CONFIG_HCS12_PORTH_INTS -# define HCS12_IRQ_PHSET 0x7f -# define HCS12_IRQ_PH0 (HCC12_IRQ_PHFIRST+0) -# define HCS12_IRQ_PH1 (HCC12_IRQ_PHFIRST+1) -# define HCS12_IRQ_PH2 (HCC12_IRQ_PHFIRST+2) -# define HCS12_IRQ_PH3 (HCC12_IRQ_PHFIRST+3) -# define HCS12_IRQ_PH4 (HCC12_IRQ_PHFIRST+4) -# define HCS12_IRQ_PH5 (HCC12_IRQ_PHFIRST+5) -# define HCS12_IRQ_PH6 (HCC12_IRQ_PHFIRST+6) -# define HCC12_IRQ_PJFIRST (HCC12_IRQ_PHFIRST+7) -# else -# define HCC12_IRQ_PJFIRST HCC12_IRQ_PHFIRST -# endif +# ifdef CONFIG_HCS12_PORTH_INTS +# define HCS12_IRQ_PHSET 0x7f +# define HCS12_IRQ_PH0 (HCC12_IRQ_PHFIRST+0) +# define HCS12_IRQ_PH1 (HCC12_IRQ_PHFIRST+1) +# define HCS12_IRQ_PH2 (HCC12_IRQ_PHFIRST+2) +# define HCS12_IRQ_PH3 (HCC12_IRQ_PHFIRST+3) +# define HCS12_IRQ_PH4 (HCC12_IRQ_PHFIRST+4) +# define HCS12_IRQ_PH5 (HCC12_IRQ_PHFIRST+5) +# define HCS12_IRQ_PH6 (HCC12_IRQ_PHFIRST+6) +# define HCC12_IRQ_PJFIRST (HCC12_IRQ_PHFIRST+7) +# else +# define HCC12_IRQ_PJFIRST HCC12_IRQ_PHFIRST +# endif -# ifdef CONFIG_HCS12_PORTJ_INTS -# define HCS12_IRQ_PJSET 0xcf -# define HCS12_IRQ_PJ0 (HCC12_IRQ_PJFIRST+0) -# define HCS12_IRQ_PJ1 (HCC12_IRQ_PJFIRST+1) -# define HCS12_IRQ_PJ2 (HCC12_IRQ_PJFIRST+2) -# define HCS12_IRQ_PJ3 (HCC12_IRQ_PJFIRST+3) -# define HCS12_IRQ_PJ6 (HCC12_IRQ_PJFIRST+4) -# define HCS12_IRQ_PJ7 (HCC12_IRQ_PJFIRST+5) -# define HCS12_IRQ_NIRQS (HCC12_IRQ_PJFIRST+6) -# else -# define HCS12_IRQ_NIRQS HCC12_IRQ_PJFIRST -# endif +# ifdef CONFIG_HCS12_PORTJ_INTS +# define HCS12_IRQ_PJSET 0xcf +# define HCS12_IRQ_PJ0 (HCC12_IRQ_PJFIRST+0) +# define HCS12_IRQ_PJ1 (HCC12_IRQ_PJFIRST+1) +# define HCS12_IRQ_PJ2 (HCC12_IRQ_PJFIRST+2) +# define HCS12_IRQ_PJ3 (HCC12_IRQ_PJFIRST+3) +# define HCS12_IRQ_PJ6 (HCC12_IRQ_PJFIRST+4) +# define HCS12_IRQ_PJ7 (HCC12_IRQ_PJFIRST+5) +# define HCS12_IRQ_NIRQS (HCC12_IRQ_PJFIRST+6) +# else +# define HCS12_IRQ_NIRQS HCC12_IRQ_PJFIRST +# endif #else # define HCS12_IRQ_NIRQS HCS12_IRQ_NVECTORS #endif /* CONFIG_HCS12_GPIOIRQ */ diff --git a/arch/hc/src/common/hc_internal.h b/arch/hc/src/common/hc_internal.h index a493daccda..b47d8f092b 100644 --- a/arch/hc/src/common/hc_internal.h +++ b/arch/hc/src/common/hc_internal.h @@ -172,7 +172,7 @@ void hc_lowputs(const char *str); #if CONFIG_MM_REGIONS > 1 void hc_addregion(void); #else -# define hc_addregion() +# define hc_addregion() #endif /* Sub-system/driver initialization */ @@ -184,15 +184,15 @@ void weak_function hc_dma_initialize(void); #if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void hc_netinitialize(void); #else -# define hc_netinitialize() +# define hc_netinitialize() #endif #ifdef CONFIG_USBDEV void hc_usbinitialize(void); void hc_usbuninitialize(void); #else -# define hc_usbinitialize() -# define hc_usbuninitialize() +# define hc_usbinitialize() +# define hc_usbuninitialize() #endif #endif /* __ASSEMBLY__ */ diff --git a/arch/hc/src/m9s12/m9s12_ethernet.c b/arch/hc/src/m9s12/m9s12_ethernet.c index df213fffd8..1bd2126376 100644 --- a/arch/hc/src/m9s12/m9s12_ethernet.c +++ b/arch/hc/src/m9s12/m9s12_ethernet.c @@ -53,7 +53,7 @@ */ #ifndef CONFIG_HCS12_NINTERFACES -# define CONFIG_HCS12_NINTERFACES 1 +# define CONFIG_HCS12_NINTERFACES 1 #endif /* TX timeout = 1 minute */ diff --git a/arch/hc/src/m9s12/m9s12_gpioirq.c b/arch/hc/src/m9s12/m9s12_gpioirq.c index bc7a1b84ce..e10a3c7704 100644 --- a/arch/hc/src/m9s12/m9s12_gpioirq.c +++ b/arch/hc/src/m9s12/m9s12_gpioirq.c @@ -220,15 +220,15 @@ void hcs12_gpioirqinitialize(void) /* Attach GPIO IRQ interrupt handlers */ #ifdef CONFIG_HCS12_GPIOIRQ -# ifdef CONFIG_HCS12_PORTG_INTS +# ifdef CONFIG_HCS12_PORTG_INTS irq_attach(HCS12_IRQ_VPORTG, hcs12_pginterrupt, NULL); -# endif -# ifdef CONFIG_HCS12_PORTH_INTS +# endif +# ifdef CONFIG_HCS12_PORTH_INTS irq_attach(HCS12_IRQ_VPORTH, hcs12_phinterrupt, NULL); -# endif -# ifdef CONFIG_HCS12_PORTJ_INTS +# endif +# ifdef CONFIG_HCS12_PORTJ_INTS irq_attach(HCS12_IRQ_VPORTJ, hcs12_pjinterrupt, NULL); -# endif +# endif #endif /* CONFIG_HCS12_GPIOIRQ */ } diff --git a/arch/hc/src/m9s12/m9s12_initialstate.c b/arch/hc/src/m9s12/m9s12_initialstate.c index 8cb46b14f4..2a33a0c53a 100644 --- a/arch/hc/src/m9s12/m9s12_initialstate.c +++ b/arch/hc/src/m9s12/m9s12_initialstate.c @@ -113,13 +113,13 @@ void up_initial_state(struct tcb_s *tcb) * Bit 7: S STOP instruction control bit */ -# ifdef CONFIG_SUPPRESS_INTERRUPTS +#ifdef CONFIG_SUPPRESS_INTERRUPTS /* Disable STOP, Mask I- and Z- interrupts */ xcp->regs[REG_CCR] = HCS12_CCR_S | HCS12_CCR_X | HCS12_CCR_I; -# else +#else /* Disable STOP, Enable I- and Z-interrupts */ xcp->regs[REG_CCR] = HCS12_CCR_S; -# endif +#endif } diff --git a/arch/mips/include/mips32/cp0.h b/arch/mips/include/mips32/cp0.h index 73d6f8333e..be9e252313 100644 --- a/arch/mips/include/mips32/cp0.h +++ b/arch/mips/include/mips32/cp0.h @@ -246,27 +246,27 @@ * Compliance Level: Required. */ -#define CP0_CAUSE_EXCCODE_SHIFT (2) /* Bits 2-6: Exception code */ -#define CP0_CAUSE_EXCCODE_MASK (31 << CP0_CAUSE_EXCCODE_SHIFT) -# define CP0_CAUSE_EXCCODE_INT (0 << CP0_CAUSE_EXCCODE_SHIFT) /* Interrupt */ -# define CP0_CAUSE_EXCCODE_TLBL (2 << CP0_CAUSE_EXCCODE_SHIFT) /* TLB exception (load or instruction fetch) */ -# define CP0_CAUSE_EXCCODE_TLBS (3 << CP0_CAUSE_EXCCODE_SHIFT) /* TLB exception (store) */ -# define CP0_CAUSE_EXCCODE_ADEL (4 << CP0_CAUSE_EXCCODE_SHIFT) /* Address error exception (load or instruction fetch) */ -# define CP0_CAUSE_EXCCODE_ADES (5 << CP0_CAUSE_EXCCODE_SHIFT) /* Address error exception (store) */ -# define CP0_CAUSE_EXCCODE_IBE (6 << CP0_CAUSE_EXCCODE_SHIFT) /* Bus error exception (instruction fetch) */ -# define CP0_CAUSE_EXCCODE_DBE (7 << CP0_CAUSE_EXCCODE_SHIFT) /* Bus error exception (data reference: load or store) */ -# define CP0_CAUSE_EXCCODE_SYS (8 << CP0_CAUSE_EXCCODE_SHIFT) /* Syscall exception */ -# define CP0_CAUSE_EXCCODE_BP (9 << CP0_CAUSE_EXCCODE_SHIFT) /* Breakpoint exception */ -# define CP0_CAUSE_EXCCODE_RI (10 << CP0_CAUSE_EXCCODE_SHIFT) /* Reserved instruction exception */ -# define CP0_CAUSE_EXCCODE_CPU (11 << CP0_CAUSE_EXCCODE_SHIFT) /* Coprocessor Unusable exception */ -# define CP0_CAUSE_EXCCODE_OV (12 << CP0_CAUSE_EXCCODE_SHIFT) /* Arithmetic Overflow exception */ -# define CP0_CAUSE_EXCCODE_TR (13 << CP0_CAUSE_EXCCODE_SHIFT) /* Trap exception */ -# define CP0_CAUSE_EXCCODE_FPE (15 << CP0_CAUSE_EXCCODE_SHIFT) /* Floating point exception */ -# define CP0_CAUSE_EXCCODE_C2E (18 << CP0_CAUSE_EXCCODE_SHIFT) /* Precise Coprocessor 2 exceptions */ -# define CP0_CAUSE_EXCCODE_MDMX (22 << CP0_CAUSE_EXCCODE_SHIFT) /* MDMX Unusable (MIPS64) */ -# define CP0_CAUSE_EXCCODE_WATCH (23 << CP0_CAUSE_EXCCODE_SHIFT) /* WatchHi/WatchLo address */ -# define CP0_CAUSE_EXCCODE_MCHECK (24 << CP0_CAUSE_EXCCODE_SHIFT) /* Machine check */ -# define CP0_CAUSE_EXCCODE_CACHEERR (30 << CP0_CAUSE_EXCCODE_SHIFT) /* Cache error */ +#define CP0_CAUSE_EXCCODE_SHIFT (2) /* Bits 2-6: Exception code */ +#define CP0_CAUSE_EXCCODE_MASK (31 << CP0_CAUSE_EXCCODE_SHIFT) +# define CP0_CAUSE_EXCCODE_INT (0 << CP0_CAUSE_EXCCODE_SHIFT) /* Interrupt */ +# define CP0_CAUSE_EXCCODE_TLBL (2 << CP0_CAUSE_EXCCODE_SHIFT) /* TLB exception (load or instruction fetch) */ +# define CP0_CAUSE_EXCCODE_TLBS (3 << CP0_CAUSE_EXCCODE_SHIFT) /* TLB exception (store) */ +# define CP0_CAUSE_EXCCODE_ADEL (4 << CP0_CAUSE_EXCCODE_SHIFT) /* Address error exception (load or instruction fetch) */ +# define CP0_CAUSE_EXCCODE_ADES (5 << CP0_CAUSE_EXCCODE_SHIFT) /* Address error exception (store) */ +# define CP0_CAUSE_EXCCODE_IBE (6 << CP0_CAUSE_EXCCODE_SHIFT) /* Bus error exception (instruction fetch) */ +# define CP0_CAUSE_EXCCODE_DBE (7 << CP0_CAUSE_EXCCODE_SHIFT) /* Bus error exception (data reference: load or store) */ +# define CP0_CAUSE_EXCCODE_SYS (8 << CP0_CAUSE_EXCCODE_SHIFT) /* Syscall exception */ +# define CP0_CAUSE_EXCCODE_BP (9 << CP0_CAUSE_EXCCODE_SHIFT) /* Breakpoint exception */ +# define CP0_CAUSE_EXCCODE_RI (10 << CP0_CAUSE_EXCCODE_SHIFT) /* Reserved instruction exception */ +# define CP0_CAUSE_EXCCODE_CPU (11 << CP0_CAUSE_EXCCODE_SHIFT) /* Coprocessor Unusable exception */ +# define CP0_CAUSE_EXCCODE_OV (12 << CP0_CAUSE_EXCCODE_SHIFT) /* Arithmetic Overflow exception */ +# define CP0_CAUSE_EXCCODE_TR (13 << CP0_CAUSE_EXCCODE_SHIFT) /* Trap exception */ +# define CP0_CAUSE_EXCCODE_FPE (15 << CP0_CAUSE_EXCCODE_SHIFT) /* Floating point exception */ +# define CP0_CAUSE_EXCCODE_C2E (18 << CP0_CAUSE_EXCCODE_SHIFT) /* Precise Coprocessor 2 exceptions */ +# define CP0_CAUSE_EXCCODE_MDMX (22 << CP0_CAUSE_EXCCODE_SHIFT) /* MDMX Unusable (MIPS64) */ +# define CP0_CAUSE_EXCCODE_WATCH (23 << CP0_CAUSE_EXCCODE_SHIFT) /* WatchHi/WatchLo address */ +# define CP0_CAUSE_EXCCODE_MCHECK (24 << CP0_CAUSE_EXCCODE_SHIFT) /* Machine check */ +# define CP0_CAUSE_EXCCODE_CACHEERR (30 << CP0_CAUSE_EXCCODE_SHIFT) /* Cache error */ #define CP0_CAUSE_IP0 (1 << 8) /* Bit 8: Controls request for software interrupt 0 */ #define CP0_CAUSE_IP1 (1 << 9) /* Bit 9: Controls request for software interrupt 1 */ @@ -336,9 +336,9 @@ #define CP0_CONFIG_BE (1 << 15) /* Bit 15: Processor is running in big-endian mode */ #define CP0_CONFIG_IMPL_SHIFT (16) /* Bits 16-30: Implementation dependent */ #define CP0_CONFIG_IMPL_MASK (0x7fff << CP0_CONFIG_IMPL_SHIFT) -#define CP0_CONFIG_M_SHIFT (31) -#define CP0_CONFIG_M_MASK (1 << CP0_CONFIG_M_SHIFT) -# define CP0_CONFIG_M (1 << CP0_CONFIG_M_SHIFT) /* Bit 31: Indicates the presence of a Config1 register */ +#define CP0_CONFIG_M_SHIFT (31) +#define CP0_CONFIG_M_MASK (1 << CP0_CONFIG_M_SHIFT) +# define CP0_CONFIG_M (1 << CP0_CONFIG_M_SHIFT) /* Bit 31: Indicates the presence of a Config1 register */ /* Register Number: 16 Sel: 1 Name: Config1 * Function: Configuration register 1 diff --git a/arch/mips/src/common/mips_internal.h b/arch/mips/src/common/mips_internal.h index 16bbc1c3de..cf8f30a236 100644 --- a/arch/mips/src/common/mips_internal.h +++ b/arch/mips/src/common/mips_internal.h @@ -211,7 +211,7 @@ void weak_function mips_dma_initialize(void); #if CONFIG_MM_REGIONS > 1 void mips_addregion(void); #else -# define mips_addregion() +# define mips_addregion() #endif /* Serial output */ @@ -231,7 +231,7 @@ void mips_serialinit(void); #if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void mips_netinitialize(void); #else -# define mips_netinitialize() +# define mips_netinitialize() #endif /* USB */ @@ -240,8 +240,8 @@ void mips_netinitialize(void); void mips_usbinitialize(void); void mips_usbuninitialize(void); #else -# define mips_usbinitialize() -# define mips_usbuninitialize() +# define mips_usbinitialize() +# define mips_usbuninitialize() #endif #endif /* __ASSEMBLY__ */ diff --git a/arch/mips/src/pic32mx/pic32mx_ethernet.c b/arch/mips/src/pic32mx/pic32mx_ethernet.c index 240edc15b2..c8bf69ae12 100644 --- a/arch/mips/src/pic32mx/pic32mx_ethernet.c +++ b/arch/mips/src/pic32mx/pic32mx_ethernet.c @@ -335,8 +335,8 @@ static void pic32mx_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t pic32mx_getreg(uint32_t addr); static void pic32mx_putreg(uint32_t val, uint32_t addr); #else -# define pic32mx_getreg(addr) getreg32(addr) -# define pic32mx_putreg(val,addr) putreg32(val,addr) +# define pic32mx_getreg(addr) getreg32(addr) +# define pic32mx_putreg(val,addr) putreg32(val,addr) #endif /* Buffer and descriptor management */ @@ -347,8 +347,8 @@ static void pic32mx_dumptxdesc(struct pic32mx_txdesc_s *txdesc, static void pic32mx_dumprxdesc(struct pic32mx_rxdesc_s *rxdesc, const char *msg); #else -# define pic32mx_dumptxdesc(txdesc,msg) -# define pic32mx_dumprxdesc(rxdesc,msg) +# define pic32mx_dumptxdesc(txdesc,msg) +# define pic32mx_dumprxdesc(rxdesc,msg) #endif static inline void pic32mx_bufferinit(struct pic32mx_driver_s *priv); diff --git a/arch/misoc/src/common/misoc_net.c b/arch/misoc/src/common/misoc_net.c index 4be42e22cc..f0a92b4534 100644 --- a/arch/misoc/src/common/misoc_net.c +++ b/arch/misoc/src/common/misoc_net.c @@ -72,7 +72,7 @@ */ #ifndef CONFIG_MISOC_NET_NINTERFACES -# define CONFIG_MISOC_NET_NINTERFACES 1 +# define CONFIG_MISOC_NET_NINTERFACES 1 #endif /* TX timeout = 1 minute */ diff --git a/arch/misoc/src/common/misoc_serial.c b/arch/misoc/src/common/misoc_serial.c index ce52d18a77..4337ba606f 100644 --- a/arch/misoc/src/common/misoc_serial.c +++ b/arch/misoc/src/common/misoc_serial.c @@ -185,7 +185,7 @@ static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; #ifdef CONFIG_MISOC_UART1 #ifndef CONFIG_MISOC_UART1PRIO -# define CONFIG_MISOC_UART1PRIO 4 +# define CONFIG_MISOC_UART1PRIO 4 #endif static struct misoc_dev_s g_uart1priv = diff --git a/arch/or1k/src/common/or1k_internal.h b/arch/or1k/src/common/or1k_internal.h index 6ea0c9fb2e..95a736c193 100644 --- a/arch/or1k/src/common/or1k_internal.h +++ b/arch/or1k/src/common/or1k_internal.h @@ -286,7 +286,7 @@ void or1k_l2ccinitialize(void); #if CONFIG_MM_REGIONS > 1 void or1k_addregion(void); #else -# define or1k_addregion() +# define or1k_addregion() #endif /* Networking ***************************************************************/ @@ -304,7 +304,7 @@ void or1k_addregion(void); #if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void or1k_etinitialize(void); #else -# define or1k_etinitialize() +# define or1k_etinitialize() #endif /* USB **********************************************************************/ @@ -313,8 +313,8 @@ void or1k_etinitialize(void); void or1k_usbinitialize(void); void or1k_usbuninitialize(void); #else -# define or1k_usbinitialize() -# define or1k_usbuninitialize() +# define or1k_usbinitialize() +# define or1k_usbuninitialize() #endif /* Debug ********************************************************************/ diff --git a/arch/renesas/include/rx65n/irq.h b/arch/renesas/include/rx65n/irq.h index cb932c0206..649af4ea43 100644 --- a/arch/renesas/include/rx65n/irq.h +++ b/arch/renesas/include/rx65n/irq.h @@ -49,38 +49,38 @@ #define RX65N_BUSERR_IRQBASE (RX65N_TRAP_IRQBASE+16) #if defined(CONFIG_BSC) || defined(CONFIG_RX65N_BSC) -# define RX65N_BUSERR_IRQ (RX65N_BUSERR_IRQBASE) -# define RX65N_RAMERR_IRQBASE (RX65N_BUSERR_IRQBASE + 1) +# define RX65N_BUSERR_IRQ (RX65N_BUSERR_IRQBASE) +# define RX65N_RAMERR_IRQBASE (RX65N_BUSERR_IRQBASE + 1) #else -# define RX65N_RAMERR_IRQBASE (RX65N_BUSERR_IRQBASE) +# define RX65N_RAMERR_IRQBASE (RX65N_BUSERR_IRQBASE) #endif #if defined(CONFIG_RAM) || defined(CONFIG_RX65N_RAM) -# define RX65N_RAMERR_IRQ (RX65N_RAMERR_IRQBASE) -# define RX65N_FIFERR_IRQBASE (RX65N_RAMERR_IRQBASE + 1) +# define RX65N_RAMERR_IRQ (RX65N_RAMERR_IRQBASE) +# define RX65N_FIFERR_IRQBASE (RX65N_RAMERR_IRQBASE + 1) #else -# define RX65N_FIFERR_IRQBASE (RX65N_RAMERR_IRQBASE) +# define RX65N_FIFERR_IRQBASE (RX65N_RAMERR_IRQBASE) #endif #if defined(CONFIG_FIFERR) || defined(CONFIG_RX65N_FIFERR) -# define RX65N_FIFERR_IRQ (RX65N_FIFERR_IRQBASE) -# define RX65N_FRDYI_IRQBASE (RX65N_FIFERR_IRQBASE + 1) +# define RX65N_FIFERR_IRQ (RX65N_FIFERR_IRQBASE) +# define RX65N_FRDYI_IRQBASE (RX65N_FIFERR_IRQBASE + 1) #else -# define RX65N_FRDYI_IRQBASE (RX65N_FIFERR_IRQBASE) +# define RX65N_FRDYI_IRQBASE (RX65N_FIFERR_IRQBASE) #endif #if defined(CONFIG_FRDYI) || defined(CONFIG_RX65N_FRDYI) -# define RX65N_FRDYI_IRQ (RX65N_FRDYI_IRQBASE) -# define RX65N_SWINT2_IRQBASE (RX65N_FRDYI_IRQBASE + 1) +# define RX65N_FRDYI_IRQ (RX65N_FRDYI_IRQBASE) +# define RX65N_SWINT2_IRQBASE (RX65N_FRDYI_IRQBASE + 1) #else -# define RX65N_SWINT2_IRQBASE (RX65N_FRDYI_IRQBASE) +# define RX65N_SWINT2_IRQBASE (RX65N_FRDYI_IRQBASE) #endif -# define RX65N_SWINT2_IRQ (RX65N_SWINT2_IRQBASE) -# define RX65N_SWINT_IRQBASE (RX65N_SWINT2_IRQBASE + 1) +# define RX65N_SWINT2_IRQ (RX65N_SWINT2_IRQBASE) +# define RX65N_SWINT_IRQBASE (RX65N_SWINT2_IRQBASE + 1) -# define RX65N_SWINT_IRQ (RX65N_SWINT_IRQBASE) -# define RX65N_CMT0_IRQBASE (RX65N_SWINT_IRQBASE+1) +# define RX65N_SWINT_IRQ (RX65N_SWINT_IRQBASE) +# define RX65N_CMT0_IRQBASE (RX65N_SWINT_IRQBASE+1) #define RX65N_CMI0_IRQ (RX65N_CMT0_IRQBASE) #define RX65N_CMT1_IRQBASE (RX65N_CMT0_IRQBASE + 1) diff --git a/arch/renesas/src/common/renesas_internal.h b/arch/renesas/src/common/renesas_internal.h index 694d7b9fb1..7a93b67bd8 100644 --- a/arch/renesas/src/common/renesas_internal.h +++ b/arch/renesas/src/common/renesas_internal.h @@ -180,8 +180,8 @@ void renesas_lowputc(char ch); void renesas_lcdinit(void); void renesas_lcdputc(char ch); #else -# define renesas_lcdinit() -# define renesas_lcdputc(ch) +# define renesas_lcdinit() +# define renesas_lcdputc(ch) #endif /* Defined in board/xyz_network.c */ @@ -189,7 +189,7 @@ void renesas_lcdputc(char ch); #if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void renesas_netinitialize(void); #else -# define renesas_netinitialize() +# define renesas_netinitialize() #endif /* USB */ @@ -198,8 +198,8 @@ void renesas_netinitialize(void); void renesas_usbinitialize(void); void renesas_usbuninitialize(void); #else -# define renesas_usbinitialize() -# define renesas_usbuninitialize() +# define renesas_usbinitialize() +# define renesas_usbuninitialize() #endif #endif /* __ASSEMBLY__ */ diff --git a/arch/renesas/src/rx65n/rx65n_eth.c b/arch/renesas/src/rx65n/rx65n_eth.c index f0b88475c7..ea5ed27ed1 100644 --- a/arch/renesas/src/rx65n/rx65n_eth.c +++ b/arch/renesas/src/rx65n/rx65n_eth.c @@ -426,9 +426,9 @@ static uint32_t rx65n_getreg(uint32_t addr); static void rx65n_putreg(uint32_t val, uint32_t addr); static void rx65n_checksetup(void); #else -# define rx65n_getreg(addr) getreg32(addr) -# define rx65n_putreg(val,addr) putreg32(val,addr) -# define rx65n_checksetup() +# define rx65n_getreg(addr) getreg32(addr) +# define rx65n_putreg(val,addr) putreg32(val,addr) +# define rx65n_checksetup() #endif /* Debug */ diff --git a/arch/renesas/src/rx65n/rx65n_riic.c b/arch/renesas/src/rx65n/rx65n_riic.c index c859e9f603..cf7b138196 100644 --- a/arch/renesas/src/rx65n/rx65n_riic.c +++ b/arch/renesas/src/rx65n/rx65n_riic.c @@ -40,8 +40,8 @@ * Pre-processor Definitions ****************************************************************************/ -# define rx65n_getreg(addr) getreg8(addr) -# define rx65n_putreg(val,addr) putreg8(val,addr) +# define rx65n_getreg(addr) getreg8(addr) +# define rx65n_putreg(val,addr) putreg8(val,addr) #if defined(CONFIG_RX65N_RIIC0) || defined(CONFIG_RX65N_RIIC1) || \ defined(CONFIG_RX65N_RIIC2) diff --git a/arch/renesas/src/rx65n/rx65n_rtc.c b/arch/renesas/src/rx65n/rx65n_rtc.c index 1edab689a0..094ab3ff36 100644 --- a/arch/renesas/src/rx65n/rx65n_rtc.c +++ b/arch/renesas/src/rx65n/rx65n_rtc.c @@ -43,8 +43,8 @@ * Pre-processor Definitions ****************************************************************************/ -# define rx65n_getreg(addr) getreg8(addr) -# define rx65n_putreg(val,addr) putreg8(val,addr) +# define rx65n_getreg(addr) getreg8(addr) +# define rx65n_putreg(val,addr) putreg8(val,addr) /* Configuration ************************************************************/ diff --git a/arch/renesas/src/rx65n/rx65n_rtc_lowerhalf.c b/arch/renesas/src/rx65n/rx65n_rtc_lowerhalf.c index 4262bbc0dc..05d269427a 100644 --- a/arch/renesas/src/rx65n/rx65n_rtc_lowerhalf.c +++ b/arch/renesas/src/rx65n/rx65n_rtc_lowerhalf.c @@ -42,9 +42,9 @@ * Pre-processor Definitions ****************************************************************************/ -# define rx65n_getreg(addr) getreg8(addr) -# define rx65n_putreg(val,addr) putreg8(val,addr) -# define RX65N_NALARMS 1 +# define rx65n_getreg(addr) getreg8(addr) +# define rx65n_putreg(val,addr) putreg8(val,addr) +# define RX65N_NALARMS 1 /* Configuration ************************************************************/ #if defined(CONFIG_RTC_ALARM) && !defined(CONFIG_SCHED_WORKQUEUE) diff --git a/arch/renesas/src/rx65n/rx65n_usbdev.c b/arch/renesas/src/rx65n/rx65n_usbdev.c index c8bc2ccf04..230ed5f6dc 100644 --- a/arch/renesas/src/rx65n/rx65n_usbdev.c +++ b/arch/renesas/src/rx65n/rx65n_usbdev.c @@ -291,12 +291,12 @@ uint8_t g_buffer[64] ; /* Register operations */ -# define rx65n_getreg8(addr) getreg8(addr) -# define rx65n_getreg16(addr) getreg16(addr) -# define rx65n_getreg32(addr) getreg32(addr) -# define rx65n_putreg8(val,addr) putreg8(val,addr) -# define rx65n_putreg16(val,addr) putreg16(val,addr) -# define rx65n_putreg32(val,addr) putreg32(val,addr) +# define rx65n_getreg8(addr) getreg8(addr) +# define rx65n_getreg16(addr) getreg16(addr) +# define rx65n_getreg32(addr) getreg32(addr) +# define rx65n_putreg8(val,addr) putreg8(val,addr) +# define rx65n_putreg16(val,addr) putreg16(val,addr) +# define rx65n_putreg32(val,addr) putreg32(val,addr) /* Request queue operations *************************************************/ diff --git a/arch/risc-v/src/bl602/bl602_netdev.c b/arch/risc-v/src/bl602/bl602_netdev.c index 39f7e1cccf..7351f575b5 100644 --- a/arch/risc-v/src/bl602/bl602_netdev.c +++ b/arch/risc-v/src/bl602/bl602_netdev.c @@ -263,13 +263,13 @@ static int bl602_net_txavail(struct net_driver_s *dev); #if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) static int bl602_net_addmac(struct net_driver_s *dev, const uint8_t *mac); -# ifdef CONFIG_NET_MCASTGROUP +# ifdef CONFIG_NET_MCASTGROUP static int bl602_net_rmmac(struct net_driver_s *dev, const uint8_t *mac); -# endif -# ifdef CONFIG_NET_ICMPv6 +# endif +# ifdef CONFIG_NET_ICMPv6 static void bl602_net_ipv6multicast(struct bl602_net_driver_s *priv); -# endif +# endif #endif #ifdef CONFIG_NETDEV_IOCTL diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h index 5dcfde75f2..f3a50d4c95 100644 --- a/arch/risc-v/src/common/riscv_internal.h +++ b/arch/risc-v/src/common/riscv_internal.h @@ -188,7 +188,7 @@ void modifyreg32(uintptr_t addr, uint32_t clearbits, uint32_t setbits); #if CONFIG_MM_REGIONS > 1 void riscv_addregion(void); #else -# define riscv_addregion() +# define riscv_addregion() #endif /* IRQ initialization *******************************************************/ @@ -260,7 +260,7 @@ void riscv_earlyserialinit(void); #if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void riscv_netinitialize(void); #else -# define riscv_netinitialize() +# define riscv_netinitialize() #endif /* Exception Handler ********************************************************/ diff --git a/arch/risc-v/src/common/riscv_pmp.c b/arch/risc-v/src/common/riscv_pmp.c index a802074ab7..9a19c94a39 100644 --- a/arch/risc-v/src/common/riscv_pmp.c +++ b/arch/risc-v/src/common/riscv_pmp.c @@ -202,7 +202,7 @@ static bool pmp_check_region_attrs(uintptr_t base, uintptr_t size) static uintptr_t pmp_read_region_cfg(uintptr_t region) { -# if (PMP_XLEN == 32) +#if (PMP_XLEN == 32) switch (region) { case 0 ... 3: @@ -220,7 +220,7 @@ static uintptr_t pmp_read_region_cfg(uintptr_t region) default: break; } -# elif (PMP_XLEN == 64) +#elif (PMP_XLEN == 64) switch (region) { case 0 ... 7: @@ -542,7 +542,7 @@ int riscv_config_pmp_region(uintptr_t region, uintptr_t attr, /* Set the configuration register value */ -# if (PMP_XLEN == 32) +#if (PMP_XLEN == 32) switch (region) { case 0 ... 3: @@ -572,7 +572,7 @@ int riscv_config_pmp_region(uintptr_t region, uintptr_t attr, default: break; } -# elif (PMP_XLEN == 64) +#elif (PMP_XLEN == 64) switch (region) { case 0 ... 7: @@ -590,9 +590,9 @@ int riscv_config_pmp_region(uintptr_t region, uintptr_t attr, default: break; } -# else -# error "XLEN of risc-v not supported" -# endif +#else +# error "XLEN of risc-v not supported" +#endif #ifdef CONFIG_ARCH_USE_S_MODE /* Fence is needed when page-based virtual memory is implemented. diff --git a/arch/risc-v/src/esp32c3/esp32c3_serial.c b/arch/risc-v/src/esp32c3/esp32c3_serial.c index 2e56e8441a..b38e22510e 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_serial.c +++ b/arch/risc-v/src/esp32c3/esp32c3_serial.c @@ -80,7 +80,7 @@ # define CONSOLE_DEV g_uart0_dev /* UART0 is console */ # define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */ # define UART0_ASSIGNED 1 -# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart1_dev /* UART1 is console */ # define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */ # define UART1_ASSIGNED 1 diff --git a/arch/risc-v/src/esp32c6/esp32c6_lowputc.c b/arch/risc-v/src/esp32c6/esp32c6_lowputc.c index 264f947a7e..88ca7a56c7 100644 --- a/arch/risc-v/src/esp32c6/esp32c6_lowputc.c +++ b/arch/risc-v/src/esp32c6/esp32c6_lowputc.c @@ -104,7 +104,7 @@ static struct esp32c6_uart_s g_console_config = .int_pri = 1 }; -# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) static struct esp32c6_uart_s g_uart1_config = { @@ -117,7 +117,7 @@ static struct esp32c6_uart_s g_uart1_config = .stop_b2 = CONFIG_UART1_2STOP, .int_pri = 1 }; -#endif /* CONFIG_UART0_SERIAL_CONSOLE */ +# endif /* CONFIG_UART0_SERIAL_CONSOLE */ #endif /* HAVE_SERIAL_CONSOLE */ #endif diff --git a/arch/risc-v/src/esp32c6/esp32c6_serial.c b/arch/risc-v/src/esp32c6/esp32c6_serial.c index a5fa6cd894..f7f4f333a1 100644 --- a/arch/risc-v/src/esp32c6/esp32c6_serial.c +++ b/arch/risc-v/src/esp32c6/esp32c6_serial.c @@ -70,7 +70,7 @@ # define CONSOLE_DEV g_uart0_dev /* UART0 is console */ # define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */ # define UART0_ASSIGNED 1 -# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart1_dev /* UART1 is console */ # define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */ # define UART1_ASSIGNED 1 diff --git a/arch/risc-v/src/espressif/esp_serial.c b/arch/risc-v/src/espressif/esp_serial.c index 31b0ee0e1a..08d6f014dd 100644 --- a/arch/risc-v/src/espressif/esp_serial.c +++ b/arch/risc-v/src/espressif/esp_serial.c @@ -78,7 +78,7 @@ # define CONSOLE_DEV g_uart0_dev /* UART0 is console */ # define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */ # define UART0_ASSIGNED 1 -# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart1_dev /* UART1 is console */ # define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */ # define UART1_ASSIGNED 1 diff --git a/arch/sim/src/sim/sim_ajoystick.c b/arch/sim/src/sim/sim_ajoystick.c index 98d947575f..dcb76cf1e9 100644 --- a/arch/sim/src/sim/sim_ajoystick.c +++ b/arch/sim/src/sim/sim_ajoystick.c @@ -39,7 +39,7 @@ * Pre-processor Definitions ****************************************************************************/ -# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ +# define AJOY_SUPPORTED (AJOY_BUTTON_1_BIT | AJOY_BUTTON_2_BIT | \ AJOY_BUTTON_3_BIT) /**************************************************************************** diff --git a/arch/sim/src/sim/sim_deviceimage.c b/arch/sim/src/sim/sim_deviceimage.c index d9e6777729..5cbad94740 100644 --- a/arch/sim/src/sim/sim_deviceimage.c +++ b/arch/sim/src/sim/sim_deviceimage.c @@ -45,9 +45,9 @@ ****************************************************************************/ #ifdef VFAT_STANDALONE -# define serr(format, ...) syslog(LOG_ERR, format, ##__VA_ARGS__) -# define kmm_malloc(size) malloc(size) -# define kmm_free(mem) free(mem) +# define serr(format, ...) syslog(LOG_ERR, format, ##__VA_ARGS__) +# define kmm_malloc(size) malloc(size) +# define kmm_free(mem) free(mem) #endif /**************************************************************************** diff --git a/arch/sparc/src/bm3803/bm3803_wdg.c b/arch/sparc/src/bm3803/bm3803_wdg.c index 92f9473307..8374d14389 100644 --- a/arch/sparc/src/bm3803/bm3803_wdg.c +++ b/arch/sparc/src/bm3803/bm3803_wdg.c @@ -77,8 +77,8 @@ struct bm3803_lowerhalf_s /* Register operations ******************************************************/ -# define bm3803_getreg(addr) getreg32(addr) -# define bm3803_putreg(val,addr) putreg32(val,addr) +# define bm3803_getreg(addr) getreg32(addr) +# define bm3803_putreg(val,addr) putreg32(val,addr) static inline void bm3803_setreload(struct bm3803_lowerhalf_s *priv); diff --git a/arch/sparc/src/common/sparc_internal.h b/arch/sparc/src/common/sparc_internal.h index e6e1524985..6762176956 100644 --- a/arch/sparc/src/common/sparc_internal.h +++ b/arch/sparc/src/common/sparc_internal.h @@ -77,7 +77,7 @@ /* Check if an interrupt stack size is configured */ #ifndef CONFIG_ARCH_INTERRUPTSTACK -# define CONFIG_ARCH_INTERRUPTSTACK 0 +# define CONFIG_ARCH_INTERRUPTSTACK 0 #endif #define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK) @@ -222,7 +222,7 @@ void weak_function sparc_dma_initialize(void); #if CONFIG_MM_REGIONS > 1 void sparc_addregion(void); #else -# define sparc_addregion() +# define sparc_addregion() #endif /* Serial output */ @@ -236,7 +236,7 @@ void sparc_serialinit(void); #if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void sparc_netinitialize(void); #else -# define sparc_netinitialize() +# define sparc_netinitialize() #endif /* USB */ @@ -245,8 +245,8 @@ void sparc_netinitialize(void); void sparc_usbinitialize(void); void sparc_usbuninitialize(void); #else -# define sparc_usbinitialize() -# define sparc_usbuninitialize() +# define sparc_usbinitialize() +# define sparc_usbuninitialize() #endif /* Debug ********************************************************************/ diff --git a/arch/x86/src/common/x86_internal.h b/arch/x86/src/common/x86_internal.h index cfaf5cccfa..b01a47e742 100644 --- a/arch/x86/src/common/x86_internal.h +++ b/arch/x86/src/common/x86_internal.h @@ -183,7 +183,7 @@ void x86_syscall(uint32_t *regs); #if CONFIG_MM_REGIONS > 1 void x86_addregion(void); #else -# define x86_addregion() +# define x86_addregion() #endif /* Defined in xyz_serial.c */ @@ -200,15 +200,15 @@ void x86_serialinit(void); #if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void x86_netinitialize(void); #else -# define x86_netinitialize() +# define x86_netinitialize() #endif #ifdef CONFIG_USBDEV void x86_usbinitialize(void); void x86_usbuninitialize(void); #else -# define x86_usbinitialize() -# define x86_usbuninitialize() +# define x86_usbinitialize() +# define x86_usbuninitialize() #endif #endif /* __ASSEMBLY__ */ diff --git a/arch/x86_64/include/intel64/arch.h b/arch/x86_64/include/intel64/arch.h index 9e534725f3..e685551822 100644 --- a/arch/x86_64/include/intel64/arch.h +++ b/arch/x86_64/include/intel64/arch.h @@ -74,10 +74,10 @@ #define X86_GDT_ENTRY_SIZE 0x8 #define X86_GDT_CODE_SEL_NUM 1 -# define X86_GDT_CODE_SEL (X86_GDT_CODE_SEL_NUM * X86_GDT_ENTRY_SIZE) +# define X86_GDT_CODE_SEL (X86_GDT_CODE_SEL_NUM * X86_GDT_ENTRY_SIZE) #define X86_GDT_DATA_SEL_NUM 2 -# define X86_GDT_DATA_SEL (X86_GDT_DATA_SEL_NUM * X86_GDT_ENTRY_SIZE) +# define X86_GDT_DATA_SEL (X86_GDT_DATA_SEL_NUM * X86_GDT_ENTRY_SIZE) #define X86_GDT_ISTL_SEL_NUM 6 #define X86_GDT_ISTH_SEL_NUM (X86_GDT_ISTL_SEL_NUM + 1) @@ -128,38 +128,38 @@ #define X86_NUM_PAGE_ENTRY (PAGE_SIZE / X86_PAGE_ENTRY_SIZE) #define PAGE_SIZE (0x1000) -# define PAGE_MASK (~(PAGE_SIZE - 1)) +# define PAGE_MASK (~(PAGE_SIZE - 1)) #define HUGE_PAGE_SIZE (0x200000) -# define HUGE_PAGE_MASK (~(HUGE_PAGE_SIZE - 1)) +# define HUGE_PAGE_MASK (~(HUGE_PAGE_SIZE - 1)) /* CPUID Leaf Definitions */ -#define X86_64_CPUID_CAP 0x01 -# define X86_64_CPUID_01_SSE3 (1 << 0) -# define X86_64_CPUID_01_PCID (1 << 17) -# define X86_64_CPUID_01_X2APIC (1 << 21) -# define X86_64_CPUID_01_TSCDEA (1 << 24) -# define X86_64_CPUID_01_XSAVE (1 << 26) -# define X86_64_CPUID_01_RDRAND (1 << 30) -#define X86_64_CPUID_TSC 0x15 +#define X86_64_CPUID_CAP 0x01 +# define X86_64_CPUID_01_SSE3 (1 << 0) +# define X86_64_CPUID_01_PCID (1 << 17) +# define X86_64_CPUID_01_X2APIC (1 << 21) +# define X86_64_CPUID_01_TSCDEA (1 << 24) +# define X86_64_CPUID_01_XSAVE (1 << 26) +# define X86_64_CPUID_01_RDRAND (1 << 30) +#define X86_64_CPUID_TSC 0x15 /* MSR Definitions */ #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ #define MSR_EFER 0xc0000080 -# define EFER_LME 0x00000100 +# define EFER_LME 0x00000100 #define MSR_MTRR_DEF_TYPE 0x000002ff -# define MTRR_ENABLE 0x00000800 +# define MTRR_ENABLE 0x00000800 #define MSR_IA32_TSC_DEADLINE 0x6e0 #define MSR_IA32_APIC_BASE 0x01b -# define MSR_IA32_APIC_EN 0x800 -# define MSR_IA32_APIC_X2APIC 0x400 -# define MSR_IA32_APIC_BSP 0x100 +# define MSR_IA32_APIC_EN 0x800 +# define MSR_IA32_APIC_X2APIC 0x400 +# define MSR_IA32_APIC_BSP 0x100 #define MSR_X2APIC_ID 0x802 #define MSR_X2APIC_VER 0x803 @@ -169,7 +169,7 @@ #define MSR_X2APIC_LDR 0x80d #define MSR_X2APIC_SPIV 0x80f -# define MSR_X2APIC_SPIV_EN 0x100 +# define MSR_X2APIC_SPIV_EN 0x100 #define MSR_X2APIC_ISR0 0x810 #define MSR_X2APIC_ISR1 0x811 @@ -200,25 +200,25 @@ #define MSR_X2APIC_ESR 0x828 #define MSR_X2APIC_ICR 0x830 -# define MSR_X2APIC_ICR_INIT 0x00000500 /* INIT/RESET */ -# define MSR_X2APIC_ICR_STARTUP 0x00000600 /* Startup IPI */ -# define MSR_X2APIC_ICR_DELIVS 0x00001000 /* Delivery status */ -# define MSR_X2APIC_ICR_ASSERT 0x00004000 /* Assert interrupt (vs deassert) */ -# define MSR_X2APIC_ICR_DEASSERT 0x00000000 -# define MSR_X2APIC_ICR_LEVEL 0x00008000 /* Level triggered */ -# define MSR_X2APIC_ICR_BCAST 0x00080000 /* Send to all APICs, including self. */ -# define MSR_X2APIC_ICR_BUSY 0x00001000 -# define MSR_X2APIC_ICR_FIXED 0x00000000 +# define MSR_X2APIC_ICR_INIT 0x00000500 /* INIT/RESET */ +# define MSR_X2APIC_ICR_STARTUP 0x00000600 /* Startup IPI */ +# define MSR_X2APIC_ICR_DELIVS 0x00001000 /* Delivery status */ +# define MSR_X2APIC_ICR_ASSERT 0x00004000 /* Assert interrupt (vs deassert) */ +# define MSR_X2APIC_ICR_DEASSERT 0x00000000 +# define MSR_X2APIC_ICR_LEVEL 0x00008000 /* Level triggered */ +# define MSR_X2APIC_ICR_BCAST 0x00080000 /* Send to all APICs, including self. */ +# define MSR_X2APIC_ICR_BUSY 0x00001000 +# define MSR_X2APIC_ICR_FIXED 0x00000000 #define MSR_X2APIC_LVTT 0x832 -# define MSR_X2APIC_LVTT_X1 0x0000000B /* divide counts by 1 */ -# define MSR_X2APIC_LVTT_PERIODIC 0x00020000 /* Periodic */ -# define MSR_X2APIC_LVTT_TSC_DEADLINE 0x00040000 /* Enable TSC DEADLINE One-shot timer */ +# define MSR_X2APIC_LVTT_X1 0x0000000B /* divide counts by 1 */ +# define MSR_X2APIC_LVTT_PERIODIC 0x00020000 /* Periodic */ +# define MSR_X2APIC_LVTT_TSC_DEADLINE 0x00040000 /* Enable TSC DEADLINE One-shot timer */ #define MSR_X2APIC_LVTTHER 0x833 #define MSR_X2APIC_LVTPMR 0x834 #define MSR_X2APIC_LINT0 0x835 #define MSR_X2APIC_LINT1 0x836 #define MSR_X2APIC_LERR 0x837 -# define MSR_X2APIC_MASKED 0x00010000 /* Interrupt masked */ +# define MSR_X2APIC_MASKED 0x00010000 /* Interrupt masked */ #define MSR_X2APIC_TMICT 0x838 #define MSR_X2APIC_TMCCT 0x839 #define MSR_X2APIC_TDCR 0x83e @@ -228,10 +228,10 @@ #define IOAPIC_BASE 0xfec00000 #define IOAPIC_REG_INDEX 0x00 #define IOAPIC_REG_DATA 0x10 -# define IOAPIC_REG_ID 0x00 /* Register index: ID */ -# define IOAPIC_REG_VER 0x01 /* Register index: version */ -# define IOAPIC_REG_TABLE 0x10 /* Redirection table base */ -# define IOAPIC_PIN_DISABLE (1 << 16) /* Disable */ +# define IOAPIC_REG_ID 0x00 /* Register index: ID */ +# define IOAPIC_REG_VER 0x01 /* Register index: version */ +# define IOAPIC_REG_TABLE 0x10 /* Redirection table base */ +# define IOAPIC_PIN_DISABLE (1 << 16) /* Disable */ /* PIC related Definitions */ diff --git a/arch/x86_64/src/common/x86_64_initialize.c b/arch/x86_64/src/common/x86_64_initialize.c index 8d8d5ae456..b9f32c2d25 100644 --- a/arch/x86_64/src/common/x86_64_initialize.c +++ b/arch/x86_64/src/common/x86_64_initialize.c @@ -56,7 +56,7 @@ static void up_calibratedelay(void) _warn("End 100s delay\n"); } #else -# define up_calibratedelay() +# define up_calibratedelay() #endif /**************************************************************************** diff --git a/arch/x86_64/src/common/x86_64_internal.h b/arch/x86_64/src/common/x86_64_internal.h index ec4b22769f..871c951933 100644 --- a/arch/x86_64/src/common/x86_64_internal.h +++ b/arch/x86_64/src/common/x86_64_internal.h @@ -87,7 +87,7 @@ /* Check if an interrupt stack size is configured */ #ifndef CONFIG_ARCH_INTERRUPTSTACK -# define CONFIG_ARCH_INTERRUPTSTACK 0 +# define CONFIG_ARCH_INTERRUPTSTACK 0 #endif /* The initial stack point is aligned at 16 bytes boundaries. If @@ -205,7 +205,7 @@ void x86_64_syscall(uint64_t *regs); #if CONFIG_MM_REGIONS > 1 void x86_64_addregion(void); #else -# define x86_64_addregion() +# define x86_64_addregion() #endif /* Defined in xyz_serial.c */ @@ -223,15 +223,15 @@ void x86_64_timer_initialize(void); #ifdef CONFIG_NET void x86_64_netinitialize(void); #else -# define x86_64_netinitialize() +# define x86_64_netinitialize() #endif #ifdef CONFIG_USBDEV void x86_64_usbinitialize(void); void x86_64_usbuninitialize(void); #else -# define x86_64_usbinitialize() -# define x86_64_usbuninitialize() +# define x86_64_usbinitialize() +# define x86_64_usbuninitialize() #endif #endif /* __ASSEMBLY__ */ diff --git a/arch/xtensa/include/xtensa/core.h b/arch/xtensa/include/xtensa/core.h index 1385abddb2..b1c02f7af5 100644 --- a/arch/xtensa/include/xtensa/core.h +++ b/arch/xtensa/include/xtensa/core.h @@ -1099,38 +1099,38 @@ /* Empty placeholder macros for undefined coprocessors: */ #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0 -# if XCHAL_CP0_SA_SIZE == 0 +# if XCHAL_CP0_SA_SIZE == 0 .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm -# endif -# if XCHAL_CP1_SA_SIZE == 0 +# endif +# if XCHAL_CP1_SA_SIZE == 0 .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm -# endif -# if XCHAL_CP2_SA_SIZE == 0 +# endif +# if XCHAL_CP2_SA_SIZE == 0 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm -# endif -# if XCHAL_CP3_SA_SIZE == 0 +# endif +# if XCHAL_CP3_SA_SIZE == 0 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm -# endif -# if XCHAL_CP4_SA_SIZE == 0 +# endif +# if XCHAL_CP4_SA_SIZE == 0 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm -# endif -# if XCHAL_CP5_SA_SIZE == 0 +# endif +# if XCHAL_CP5_SA_SIZE == 0 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm -# endif -# if XCHAL_CP6_SA_SIZE == 0 +# endif +# if XCHAL_CP6_SA_SIZE == 0 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm -# endif -# if XCHAL_CP7_SA_SIZE == 0 +# endif +# if XCHAL_CP7_SA_SIZE == 0 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm -# endif +# endif #endif /* Macros to create functions that save and restore the state of *any* TIE @@ -1147,54 +1147,54 @@ .macro xchal_cpi_store_funcbody #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) -# if XCHAL_CP0_SA_SIZE +# if XCHAL_CP0_SA_SIZE bnez a3, 99f xchal_cp0_store_a2 j 90f 99: -# endif -# if XCHAL_CP1_SA_SIZE +# endif +# if XCHAL_CP1_SA_SIZE bnei a3, 1, 99f xchal_cp1_store_a2 j 290f 99: -# endif -# if XCHAL_CP2_SA_SIZE +# endif +# if XCHAL_CP2_SA_SIZE bnei a3, 2, 99f xchal_cp2_store_a2 j 90f 99: -# endif -# if XCHAL_CP3_SA_SIZE +# endif +# if XCHAL_CP3_SA_SIZE bnei a3, 3, 99f xchal_cp3_store_a2 j 90f 99: -# endif -# if XCHAL_CP4_SA_SIZE +# endif +# if XCHAL_CP4_SA_SIZE bnei a3, 4, 99f xchal_cp4_store_a2 j 90f 99: -# endif -# if XCHAL_CP5_SA_SIZE +# endif +# if XCHAL_CP5_SA_SIZE bnei a3, 5, 99f xchal_cp5_store_a2 j 90f 99: -# endif -# if XCHAL_CP6_SA_SIZE +# endif +# if XCHAL_CP6_SA_SIZE bnei a3, 6, 99f xchal_cp6_store_a2 j 90f 99: -# endif -# if XCHAL_CP7_SA_SIZE +# endif +# if XCHAL_CP7_SA_SIZE bnei a3, 7, 99f xchal_cp7_store_a2 j 90f 99: -# endif +# endif 90: #endif .endm @@ -1209,54 +1209,54 @@ .macro xchal_cpi_load_funcbody #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) -# if XCHAL_CP0_SA_SIZE +# if XCHAL_CP0_SA_SIZE bnez a3, 99f xchal_cp0_load_a2 j 90f 99: -# endif -# if XCHAL_CP1_SA_SIZE +# endif +# if XCHAL_CP1_SA_SIZE bnei a3, 1, 99f xchal_cp1_load_a2 j 90f 99: -# endif -# if XCHAL_CP2_SA_SIZE +# endif +# if XCHAL_CP2_SA_SIZE bnei a3, 2, 99f xchal_cp2_load_a2 j 90f 99: -# endif -# if XCHAL_CP3_SA_SIZE +# endif +# if XCHAL_CP3_SA_SIZE bnei a3, 3, 99f xchal_cp3_load_a2 j 90f 99: -# endif -# if XCHAL_CP4_SA_SIZE +# endif +# if XCHAL_CP4_SA_SIZE bnei a3, 4, 99f xchal_cp4_load_a2 j 90f 99: -# endif -# if XCHAL_CP5_SA_SIZE +# endif +# if XCHAL_CP5_SA_SIZE bnei a3, 5, 99f xchal_cp5_load_a2 j 90f 99: -# endif -# if XCHAL_CP6_SA_SIZE +# endif +# if XCHAL_CP6_SA_SIZE bnei a3, 6, 99f xchal_cp6_load_a2 j 90f 99: -# endif -# if XCHAL_CP7_SA_SIZE +# endif +# if XCHAL_CP7_SA_SIZE bnei a3, 7, 99f xchal_cp7_load_a2 j 90f 99: -# endif +# endif 90: #endif .endm @@ -1419,20 +1419,20 @@ */ #if XCHAL_HW_CONFIGID_RELIABLE -# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) -# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) -# define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) -# define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0) +# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) +# define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0) #else -# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \ +# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \ : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \ : XTHAL_MAYBE ) -# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \ +# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \ : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \ : XTHAL_MAYBE ) -# define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \ +# define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \ ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE) -# define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0) +# define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0) #endif /* Specific errata: */ diff --git a/arch/xtensa/include/xtensa/core_macros.h b/arch/xtensa/include/xtensa/core_macros.h index 8bfd210913..4307cb52a2 100644 --- a/arch/xtensa/include/xtensa/core_macros.h +++ b/arch/xtensa/include/xtensa/core_macros.h @@ -36,7 +36,7 @@ __asm__ __volatile__("rsr.ccount %0":\ "=a"(__ccount)); __ccount; }) -# define XTHAL_SET_CCOUNT(v) do { int __ccount = (int)(v); \ +# define XTHAL_SET_CCOUNT(v) do { int __ccount = (int)(v); \ __asm__ __volatile__("wsr.ccount %0" :: "a"(__ccount):"memory");\ } while(0) diff --git a/arch/xtensa/include/xtensa/xtensa_corebits.h b/arch/xtensa/include/xtensa/xtensa_corebits.h index efe5c619ca..7b987a7f42 100644 --- a/arch/xtensa/include/xtensa/xtensa_corebits.h +++ b/arch/xtensa/include/xtensa/xtensa_corebits.h @@ -55,11 +55,11 @@ #define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */ #define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */ #define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */ -# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */ +# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */ #define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */ -# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */ +# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */ #define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */ -# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */ +# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */ #define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */ #define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */ #define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */ diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index fc88bfab33..f1e3babd1f 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -279,7 +279,7 @@ void weak_function xtensa_dma_initialize(void); #if CONFIG_MM_REGIONS > 1 void xtensa_add_region(void); #else -# define xtensa_add_region() +# define xtensa_add_region() #endif /* Watchdog timer ***********************************************************/ @@ -298,7 +298,7 @@ void xtensa_serialinit(void); #if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void xtensa_netinitialize(void); #else -# define xtensa_netinitialize() +# define xtensa_netinitialize() #endif /* USB */ @@ -307,8 +307,8 @@ void xtensa_netinitialize(void); void xtensa_usbinitialize(void); void xtensa_usbuninitialize(void); #else -# define xtensa_usbinitialize() -# define xtensa_usbuninitialize() +# define xtensa_usbinitialize() +# define xtensa_usbuninitialize() #endif /* Power management *********************************************************/ diff --git a/arch/xtensa/src/esp32s2/esp32s2_lowputc.c b/arch/xtensa/src/esp32s2/esp32s2_lowputc.c index 3674b64ce9..4a362a5d83 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_lowputc.c +++ b/arch/xtensa/src/esp32s2/esp32s2_lowputc.c @@ -742,11 +742,11 @@ void xtensa_lowputc(char ch) { #ifdef HAVE_SERIAL_CONSOLE -#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# if defined(CONFIG_UART0_SERIAL_CONSOLE) struct esp32s2_uart_s *priv = &g_uart0_config; -#elif defined (CONFIG_UART1_SERIAL_CONSOLE) +# elif defined (CONFIG_UART1_SERIAL_CONSOLE) struct esp32s2_uart_s *priv = &g_uart1_config; -# endif +# endif /* Wait until the TX FIFO has space to insert new char */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_serial.c b/arch/xtensa/src/esp32s2/esp32s2_serial.c index b24e877493..992d7a28b7 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_serial.c +++ b/arch/xtensa/src/esp32s2/esp32s2_serial.c @@ -69,7 +69,7 @@ # define CONSOLE_DEV g_uart0_dev /* UART0 is console */ # define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */ # define UART0_ASSIGNED 1 -# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart1_dev /* UART1 is console */ # define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */ # define UART1_ASSIGNED 1 diff --git a/arch/xtensa/src/esp32s3/esp32s3_serial.c b/arch/xtensa/src/esp32s3/esp32s3_serial.c index 9c7eed7df9..bc4ef4fe14 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_serial.c +++ b/arch/xtensa/src/esp32s3/esp32s3_serial.c @@ -77,7 +77,7 @@ # define CONSOLE_DEV g_uart0_dev /* UART0 is console */ # define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */ # define UART0_ASSIGNED 1 -# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) # define CONSOLE_DEV g_uart1_dev /* UART1 is console */ # define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */ # define UART1_ASSIGNED 1 diff --git a/arch/z16/src/common/z16_internal.h b/arch/z16/src/common/z16_internal.h index d0bd733544..575639887b 100644 --- a/arch/z16/src/common/z16_internal.h +++ b/arch/z16/src/common/z16_internal.h @@ -124,7 +124,7 @@ void z16_sigdeliver(void); #if defined(CONFIG_Z16_LOWPUTC) || defined(CONFIG_Z16_LOWGETC) void z16_lowputc(char ch); #else -# define z16_lowputc(ch) +# define z16_lowputc(ch) #endif /* Defined in xyz_allocateheap.c */ @@ -152,7 +152,7 @@ void z16_ack_irq(int irq); #if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void z16_netinitialize(void); #else -# define z16_netinitialize() +# define z16_netinitialize() #endif #endif /* __ASSEMBLY__ */ diff --git a/arch/z16/src/z16f/chip.h b/arch/z16/src/z16f/chip.h index 0ef0abcb1a..55b796b183 100644 --- a/arch/z16/src/z16f/chip.h +++ b/arch/z16/src/z16f/chip.h @@ -45,35 +45,35 @@ /* Hexadecimal Representation ***********************************************/ #ifdef __ASSEMBLY__ -# define _HX32(w) %##w -# define _HX8(b) %##b +# define _HX32(w) %##w +# define _HX8(b) %##b #else -# define _HX32(w) 0x##w -# define _HX8(b) 0x##b +# define _HX32(w) 0x##w +# define _HX8(b) 0x##b #endif /* Z16F Chip Variants *******************************************************/ #if defined(CONFIG_ARCH_CHIP_Z16F2810) -# define Z16F_INVMEM_SIZE (128*1024) -# define Z16F_IRAM_SIZE (4*1024) +# define Z16F_INVMEM_SIZE (128*1024) +# define Z16F_IRAM_SIZE (4*1024) # undef Z16F_HAVE_EXTMEM # undef Z16F_HAVE_GPIO_PORTJ # undef Z16F_HAVE_GPIO_PORTK #elif defined(CONFIG_ARCH_CHIP_Z16F2811) -# define Z16F_INVMEM_SIZE (128*1024) -# define Z16F_IRAM_SIZE (4*1024) -# define Z16F_HAVE_EXTMEM 1 -# define Z16F_HAVE_GPIO_PORTJ 1 -# define Z16F_HAVE_GPIO_PORTK 1 +# define Z16F_INVMEM_SIZE (128*1024) +# define Z16F_IRAM_SIZE (4*1024) +# define Z16F_HAVE_EXTMEM 1 +# define Z16F_HAVE_GPIO_PORTJ 1 +# define Z16F_HAVE_GPIO_PORTK 1 #elif defined(CONFIG_ARCH_CHIP_Z16F3211) -# define Z16F_INVMEM_SIZE (32*1024) -# define Z16F_IRAM_SIZE (2*1024) -# define Z16F_HAVE_EXTMEM 1 +# define Z16F_INVMEM_SIZE (32*1024) +# define Z16F_IRAM_SIZE (2*1024) +# define Z16F_HAVE_EXTMEM 1 #elif defined(CONFIG_ARCH_CHIP_Z16F6411) -# define Z16F_INVMEM_SIZE (64*1024) -# define Z16F_IRAM_SIZE (4*1024) -# define Z16F_HAVE_EXTMEM 1 +# define Z16F_INVMEM_SIZE (64*1024) +# define Z16F_IRAM_SIZE (4*1024) +# define Z16F_HAVE_EXTMEM 1 #else # error "Z16F chip variant not specified" #endif @@ -349,24 +349,24 @@ #define Z16F_GPIOH_SMRE _HX32(ffffe178) /* 8-bits: Port H Stop Mode Recovery En */ #ifdef Z16F_HAVE_GPIO_PORTJ -# define Z16F_GPIOJ_IN _HX32(ffffe180) /* 8-bits: Port J Input Data */ -# define Z16F_GPIOJ_OUT _HX32(ffffe181) /* 8-bits: Port J Output Data */ -# define Z16F_GPIOJ_DD _HX32(ffffe182) /* 8-bits: Port J Data Direction */ -# define Z16F_GPIOJ_HDE _HX32(ffffe183) /* 8-bits: Port J High Drive Enable */ -# define Z16F_GPIOJ_OC _HX32(ffffe186) /* 8-bits: Port J Output Control */ -# define Z16F_GPIOJ_PUE _HX32(ffffe187) /* 8-bits: Port J Pull-Up Enable */ -# define Z16F_GPIOJ_SMRE _HX32(ffffe188) /* 8-bits: Port J Stop Mode Recovery En */ +# define Z16F_GPIOJ_IN _HX32(ffffe180) /* 8-bits: Port J Input Data */ +# define Z16F_GPIOJ_OUT _HX32(ffffe181) /* 8-bits: Port J Output Data */ +# define Z16F_GPIOJ_DD _HX32(ffffe182) /* 8-bits: Port J Data Direction */ +# define Z16F_GPIOJ_HDE _HX32(ffffe183) /* 8-bits: Port J High Drive Enable */ +# define Z16F_GPIOJ_OC _HX32(ffffe186) /* 8-bits: Port J Output Control */ +# define Z16F_GPIOJ_PUE _HX32(ffffe187) /* 8-bits: Port J Pull-Up Enable */ +# define Z16F_GPIOJ_SMRE _HX32(ffffe188) /* 8-bits: Port J Stop Mode Recovery En */ #endif #ifdef Z16F_HAVE_GPIO_PORTK -# define Z16F_GPIOK_IN _HX32(ffffe190) /* 8-bits: Port K Input Data */ -# define Z16F_GPIOK_OUT _HX32(ffffe191) /* 8-bits: Port K Output Data */ -# define Z16F_GPIOK_DD _HX32(ffffe192) /* 8-bits: Port K Data Direction */ -# define Z16F_GPIOK_HDE _HX32(ffffe193) /* 8-bits: Port K High Drive Enable */ -# define Z16F_GPIOK_AFL _HX32(ffffe195) /* 8-bits: Port K Alternate Function Low */ -# define Z16F_GPIOK_OC _HX32(ffffe196) /* 8-bits: Port K Output Control */ -# define Z16F_GPIOK_PUE _HX32(ffffe197) /* 8-bits: Port K Pull-Up Enable */ -# define Z16F_GPIOK_SMRE _HX32(ffffe198) /* 8-bits: Port K Stop Mode Recovery En */ +# define Z16F_GPIOK_IN _HX32(ffffe190) /* 8-bits: Port K Input Data */ +# define Z16F_GPIOK_OUT _HX32(ffffe191) /* 8-bits: Port K Output Data */ +# define Z16F_GPIOK_DD _HX32(ffffe192) /* 8-bits: Port K Data Direction */ +# define Z16F_GPIOK_HDE _HX32(ffffe193) /* 8-bits: Port K High Drive Enable */ +# define Z16F_GPIOK_AFL _HX32(ffffe195) /* 8-bits: Port K Alternate Function Low */ +# define Z16F_GPIOK_OC _HX32(ffffe196) /* 8-bits: Port K Output Control */ +# define Z16F_GPIOK_PUE _HX32(ffffe197) /* 8-bits: Port K Pull-Up Enable */ +# define Z16F_GPIOK_SMRE _HX32(ffffe198) /* 8-bits: Port K Stop Mode Recovery En */ #endif /* UART Register Offsets ****************************************************/ @@ -539,7 +539,7 @@ # define Z16F_TIMER0_L _HX32(ffffe301) /* 8-bit: Timer 0 Low Byte */ #define Z16F_TIMER0_R _HX32(ffffe302) /* 16-bit: Timer 0 Reload */ # define Z16F_TIMER0_RH _HX32(ffffe302) /* 8-bit: Timer 0 Reload High Byte */ -# define Z16F_TIMER0_RL _HX32(ffffe303) /* 8-bit: Timer 0 Reload Low Byte */ +# define Z16F_TIMER0_RL _HX32(ffffe303) /* 8-bit: Timer 0 Reload Low Byte */ #define Z16F_TIMER0_PWM _HX32(ffffe304) /* 16-bit: Timer 0 PWM */ # define Z16F_TIMER0_PWMH _HX32(ffffe304) /* 8-bit: Timer 0 PWM High Byte */ # define Z16F_TIMER0_PWML _HX32(ffffe305) /* 8-bit: Timer 0 PWM Low Byte */ diff --git a/arch/z16/src/z16f/z16f_espi.c b/arch/z16/src/z16f/z16f_espi.c index 531f6f1447..5cc617eeee 100644 --- a/arch/z16/src/z16f/z16f_espi.c +++ b/arch/z16/src/z16f/z16f_espi.c @@ -81,15 +81,15 @@ static void spi_putreg8(FAR struct z16f_spi_s *priv, uint8_t regval, static void spi_putreg16(FAR struct z16f_spi_s *priv, uint16_t regval, uintptr_t regaddr); #else -# define spi_getreg8(priv,regaddr) getreg8(regaddr) -# define spi_putreg8(priv,regval,regaddr) putreg8(regval, regaddr) -# define spi_putreg16(priv,regval,regaddr) putreg16(regval, regaddr) +# define spi_getreg8(priv,regaddr) getreg8(regaddr) +# define spi_putreg8(priv,regval,regaddr) putreg8(regval, regaddr) +# define spi_putreg16(priv,regval,regaddr) putreg16(regval, regaddr) #endif #ifdef CONFIG_DEBUG_SPI_INFO static void spi_dumpregs(FAR struct z16f_spi_s *priv, const char *msg); #else -# define spi_dumpregs(priv,msg) +# define spi_dumpregs(priv,msg) #endif static void spi_flush(FAR struct z16f_spi_s *priv); diff --git a/arch/z16/src/z16f/z16f_serial.c b/arch/z16/src/z16f/z16f_serial.c index 8b7ce5cd2e..a177e98401 100644 --- a/arch/z16/src/z16f/z16f_serial.c +++ b/arch/z16/src/z16f/z16f_serial.c @@ -785,15 +785,15 @@ int up_putc(int ch) ****************************************************************************/ #ifdef CONFIG_UART1_SERIAL_CONSOLE -# define z16f_contrde() \ - ((getreg8(Z16F_UART1_STAT0) & Z16F_UARTSTAT0_TDRE) != 0) -# define z16f_contxd(ch) \ - putreg8((uint8_t)(ch), Z16F_UART1_TXD) +# define z16f_contrde() \ + ((getreg8(Z16F_UART1_STAT0) & Z16F_UARTSTAT0_TDRE) != 0) +# define z16f_contxd(ch) \ + putreg8((uint8_t)(ch), Z16F_UART1_TXD) #else -# define z16f_contrde() \ - ((getreg8(Z16F_UART0_STAT0) & Z16F_UARTSTAT0_TDRE) != 0) -# define z16f_contxd(ch) \ - putreg8((uint8_t)(ch), Z16F_UART0_TXD) +# define z16f_contrde() \ + ((getreg8(Z16F_UART0_STAT0) & Z16F_UARTSTAT0_TDRE) != 0) +# define z16f_contxd(ch) \ + putreg8((uint8_t)(ch), Z16F_UART0_TXD) #endif /**************************************************************************** diff --git a/arch/z80/src/common/z80_internal.h b/arch/z80/src/common/z80_internal.h index ff6e5cb1d3..22d217afdf 100644 --- a/arch/z80/src/common/z80_internal.h +++ b/arch/z80/src/common/z80_internal.h @@ -131,16 +131,16 @@ void z80_timerhook(void); #if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) int z80_netinitialize(void); void z80_netuninitialize(void); -# ifdef CONFIG_ARCH_MCFILTER +# ifdef CONFIG_ARCH_MCFILTER int z80_multicastfilter(FAR struct net_driver_s *dev, FAR uint8_t *mac, bool enable); -# else -# define z80_multicastfilter(dev, mac, enable) -# endif +# else +# define z80_multicastfilter(dev, mac, enable) +# endif #else -# define z80_netinitialize() -# define z80_netuninitialize() -# define z80_multicastfilter(dev, mac, enable) +# define z80_netinitialize() +# define z80_netuninitialize() +# define z80_multicastfilter(dev, mac, enable) #endif #ifdef __cplusplus diff --git a/arch/z80/src/ez80/ez80_serial.c b/arch/z80/src/ez80/ez80_serial.c index 073d6008e9..1884e18c64 100644 --- a/arch/z80/src/ez80/ez80_serial.c +++ b/arch/z80/src/ez80/ez80_serial.c @@ -207,24 +207,24 @@ static uart_dev_t g_uart1port = /* Now, which one with be tty0/console and which tty1? */ #if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_EZ80_UART0) -# define CONSOLE_DEV g_uart0port -# define TTYS0_DEV g_uart0port -# if defined(CONFIG_EZ80_UART1) -# define TTYS1_DEV g_uart1port -# endif +# define CONSOLE_DEV g_uart0port +# define TTYS0_DEV g_uart0port +# if defined(CONFIG_EZ80_UART1) +# define TTYS1_DEV g_uart1port +# endif #elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_EZ80_UART1) -# define CONSOLE_DEV g_uart1port -# define TTYS0_DEV g_uart1port -# if defined(CONFIG_EZ80_UART0) -# define TTYS1_DEV g_uart0port -# endif +# define CONSOLE_DEV g_uart1port +# define TTYS0_DEV g_uart1port +# if defined(CONFIG_EZ80_UART0) +# define TTYS1_DEV g_uart0port +# endif #elif defined(CONFIG_EZ80_UART0) -# define TTYS0_DEV g_uart0port -# if defined(CONFIG_EZ80_UART1) -# define TTYS1_DEV g_uart1port -# endif +# define TTYS0_DEV g_uart0port +# if defined(CONFIG_EZ80_UART1) +# define TTYS1_DEV g_uart1port +# endif #elif defined(CONFIG_EZ80_UART0) -# define TTYS0_DEV g_uart1port +# define TTYS0_DEV g_uart1port #endif /**************************************************************************** @@ -771,11 +771,11 @@ int up_putc(int ch) ****************************************************************************/ #ifdef CONFIG_UART1_SERIAL_CONSOLE -# define ez80_inp(offs) inp((EZ80_UART1_BASE+(offs))) -# define ez80_outp(offs,val) outp((EZ80_UART1_BASE+(offs)), (val)) +# define ez80_inp(offs) inp((EZ80_UART1_BASE+(offs))) +# define ez80_outp(offs,val) outp((EZ80_UART1_BASE+(offs)), (val)) #else -# define ez80_inp(offs) inp((EZ80_UART0_BASE+(offs))) -# define ez80_outp(offs,val) outp((EZ80_UART0_BASE+(offs)), (val)) +# define ez80_inp(offs) inp((EZ80_UART0_BASE+(offs))) +# define ez80_outp(offs,val) outp((EZ80_UART0_BASE+(offs)), (val)) #endif #define ez80_txready() ((ez80_inp(EZ80_UART_LSR) & EZ80_UARTLSR_THRE) != 0) diff --git a/arch/z80/src/z180/z180_scc.c b/arch/z80/src/z180/z180_scc.c index c3890e2fb9..5034f3c9d5 100644 --- a/arch/z80/src/z180/z180_scc.c +++ b/arch/z80/src/z180/z180_scc.c @@ -283,10 +283,10 @@ static uart_dev_t g_escca_port = # define TTYS0_DEV g_escca_port # if defined(CONFIG_Z180_ESCCB) # define TTYS1_DEV g_esccb_port -# endif +# endif #elif defined(CONFIG_Z180_ESCCB) -# define TTYS0_DEV g_esccb_port +# define TTYS0_DEV g_esccb_port #endif /**************************************************************************** diff --git a/arch/z80/src/z8/chip.h b/arch/z80/src/z8/chip.h index 09bc958b56..c92ec7cdfe 100644 --- a/arch/z80/src/z8/chip.h +++ b/arch/z80/src/z8/chip.h @@ -36,9 +36,9 @@ /* Hexadecimal Representation ***********************************************/ #ifdef __ASSEMBLY__ -# define _HX(h) %##h +# define _HX(h) %##h #else -# define _HX(h) 0x##h +# define _HX(h) 0x##h #endif /* Memory Map diff --git a/arch/z80/src/z8/z8_serial.c b/arch/z80/src/z8/z8_serial.c index 33384888dc..31c2e7a91b 100644 --- a/arch/z80/src/z8/z8_serial.c +++ b/arch/z80/src/z8/z8_serial.c @@ -214,13 +214,13 @@ static uart_dev_t g_uart1port = /* Now, which one with be tty0/console and which tty1? */ #ifdef CONFIG_UART1_SERIAL_CONSOLE -# define CONSOLE_DEV g_uart1port -# define TTYS0_DEV g_uart1port -# define TTYS1_DEV g_uart0port +# define CONSOLE_DEV g_uart1port +# define TTYS0_DEV g_uart1port +# define TTYS1_DEV g_uart0port #else -# define CONSOLE_DEV g_uart0port -# define TTYS0_DEV g_uart0port -# define TTYS1_DEV g_uart1port +# define CONSOLE_DEV g_uart0port +# define TTYS0_DEV g_uart0port +# define TTYS1_DEV g_uart1port #endif /**************************************************************************** @@ -763,15 +763,15 @@ int up_putc(int ch) ****************************************************************************/ #ifdef CONFIG_UART1_SERIAL_CONSOLE -# define z8_contrde() \ - ((getreg8(*(Z8_UART1_BASE+Z8_UART_STAT0)) & Z8_UARTSTAT0_TDRE) != 0) -# define z8_contxd(ch) \ - putreg8((uint8_t)(ch), *(Z8_UART1_BASE+Z8_UART_TXD)) +# define z8_contrde() \ + ((getreg8(*(Z8_UART1_BASE+Z8_UART_STAT0)) & Z8_UARTSTAT0_TDRE) != 0) +# define z8_contxd(ch) \ + putreg8((uint8_t)(ch), *(Z8_UART1_BASE+Z8_UART_TXD)) #else -# define z8_contrde() \ - ((getreg8(*(Z8_UART0_BASE+Z8_UART_STAT0)) & Z8_UARTSTAT0_TDRE) != 0) -# define z8_contxd(ch) \ - putreg8((uint8_t)(ch), *(Z8_UART0_BASE+Z8_UART_TXD)) +# define z8_contrde() \ + ((getreg8(*(Z8_UART0_BASE+Z8_UART_STAT0)) & Z8_UARTSTAT0_TDRE) != 0) +# define z8_contxd(ch) \ + putreg8((uint8_t)(ch), *(Z8_UART0_BASE+Z8_UART_TXD)) #endif /**************************************************************************** diff --git a/binfmt/elf.c b/binfmt/elf.c index 08f778632c..e1c14863ef 100644 --- a/binfmt/elf.c +++ b/binfmt/elf.c @@ -56,9 +56,9 @@ #endif #ifdef CONFIG_ELF_DUMPBUFFER -# define elf_dumpbuffer(m,b,n) binfodumpbuffer(m,b,n) +# define elf_dumpbuffer(m,b,n) binfodumpbuffer(m,b,n) #else -# define elf_dumpbuffer(m,b,n) +# define elf_dumpbuffer(m,b,n) #endif /**************************************************************************** @@ -161,7 +161,7 @@ static void elf_dumploadinfo(FAR struct elf_loadinfo_s *loadinfo) } } #else -# define elf_dumploadinfo(i) +# define elf_dumploadinfo(i) #endif /**************************************************************************** @@ -202,7 +202,7 @@ static void elf_dumpentrypt(FAR struct binary_s *binp, #endif } #else -# define elf_dumpentrypt(b,l) +# define elf_dumpentrypt(b,l) #endif /**************************************************************************** diff --git a/binfmt/libelf/libelf_bind.c b/binfmt/libelf/libelf_bind.c index dc8356e1ae..4b84b852a5 100644 --- a/binfmt/libelf/libelf_bind.c +++ b/binfmt/libelf/libelf_bind.c @@ -51,9 +51,9 @@ #endif #ifdef CONFIG_ELF_DUMPBUFFER -# define elf_dumpbuffer(m,b,n) binfodumpbuffer(m,b,n) +# define elf_dumpbuffer(m,b,n) binfodumpbuffer(m,b,n) #else -# define elf_dumpbuffer(m,b,n) +# define elf_dumpbuffer(m,b,n) #endif /**************************************************************************** diff --git a/binfmt/libelf/libelf_init.c b/binfmt/libelf/libelf_init.c index d2c1ba4ea5..640124888d 100644 --- a/binfmt/libelf/libelf_init.c +++ b/binfmt/libelf/libelf_init.c @@ -50,9 +50,9 @@ #endif #ifdef CONFIG_ELF_DUMPBUFFER -# define elf_dumpbuffer(m,b,n) binfodumpbuffer(m,b,n) +# define elf_dumpbuffer(m,b,n) binfodumpbuffer(m,b,n) #else -# define elf_dumpbuffer(m,b,n) +# define elf_dumpbuffer(m,b,n) #endif /**************************************************************************** diff --git a/binfmt/libnxflat/libnxflat_bind.c b/binfmt/libnxflat/libnxflat_bind.c index 87e9704cb8..8ef8393093 100644 --- a/binfmt/libnxflat/libnxflat_bind.c +++ b/binfmt/libnxflat/libnxflat_bind.c @@ -53,9 +53,9 @@ #endif #ifdef CONFIG_NXFLAT_DUMPBUFFER -# define nxflat_dumpbuffer(m,b,n) binfodumpbuffer(m,b,n) +# define nxflat_dumpbuffer(m,b,n) binfodumpbuffer(m,b,n) #else -# define nxflat_dumpbuffer(m,b,n) +# define nxflat_dumpbuffer(m,b,n) #endif /**************************************************************************** diff --git a/binfmt/libnxflat/libnxflat_init.c b/binfmt/libnxflat/libnxflat_init.c index 8c87b52a40..09816e1128 100644 --- a/binfmt/libnxflat/libnxflat_init.c +++ b/binfmt/libnxflat/libnxflat_init.c @@ -49,9 +49,9 @@ #endif #ifdef CONFIG_NXFLAT_DUMPBUFFER -# define nxflat_dumpbuffer(m,b,n) binfodumpbuffer(m,b,n) +# define nxflat_dumpbuffer(m,b,n) binfodumpbuffer(m,b,n) #else -# define nxflat_dumpbuffer(m,b,n) +# define nxflat_dumpbuffer(m,b,n) #endif /**************************************************************************** diff --git a/binfmt/nxflat.c b/binfmt/nxflat.c index 6f08075287..c3783f06b9 100644 --- a/binfmt/nxflat.c +++ b/binfmt/nxflat.c @@ -53,9 +53,9 @@ #endif #ifdef CONFIG_NXFLAT_DUMPBUFFER -# define nxflat_dumpbuffer(m,b,n) binfodumpbuffer(m,b,n) +# define nxflat_dumpbuffer(m,b,n) binfodumpbuffer(m,b,n) #else -# define nxflat_dumpbuffer(m,b,n) +# define nxflat_dumpbuffer(m,b,n) #endif /**************************************************************************** @@ -123,7 +123,7 @@ static void nxflat_dumploadinfo(FAR struct nxflat_loadinfo_s *loadinfo) binfo(" reloccount: %d\n", loadinfo->reloccount); } #else -# define nxflat_dumploadinfo(i) +# define nxflat_dumploadinfo(i) #endif /**************************************************************************** diff --git a/boards/arm/cxd56xx/spresense/include/board_lcdpins.h b/boards/arm/cxd56xx/spresense/include/board_lcdpins.h index f17d394fe2..04cddfb8ad 100644 --- a/boards/arm/cxd56xx/spresense/include/board_lcdpins.h +++ b/boards/arm/cxd56xx/spresense/include/board_lcdpins.h @@ -35,111 +35,111 @@ #if defined(CONFIG_LCD_RSTPIN_UART2_TX) \ || defined(CONFIG_LCD_RSTPIN_UART2_TX_E) -# define ILI934X_RST_PIN PIN_UART2_TXD +# define ILI934X_RST_PIN PIN_UART2_TXD #elif defined(CONFIG_LCD_RSTPIN_UART2_RX) \ || defined(CONFIG_LCD_RSTPIN_UART2_RX_E) -# define ILI934X_RST_PIN PIN_UART2_RXD +# define ILI934X_RST_PIN PIN_UART2_RXD #elif defined(CONFIG_LCD_RSTPIN_UART2_RTS) -# define ILI934X_RST_PIN PIN_UART2_RTS +# define ILI934X_RST_PIN PIN_UART2_RTS #elif defined(CONFIG_LCD_RSTPIN_UART2_CTS) -# define ILI934X_RST_PIN PIN_UART2_CTS +# define ILI934X_RST_PIN PIN_UART2_CTS #elif defined(CONFIG_LCD_RSTPIN_I2S0_BCK) -# define ILI934X_RST_PIN PIN_I2S0_BCK +# define ILI934X_RST_PIN PIN_I2S0_BCK #elif defined(CONFIG_LCD_RSTPIN_I2S0_LRCK) -# define ILI934X_RST_PIN PIN_I2S0_LRCK +# define ILI934X_RST_PIN PIN_I2S0_LRCK #elif defined(CONFIG_LCD_RSTPIN_SEN_IRQ_IN) -# define ILI934X_RST_PIN PIN_SEN_IRQ_IN +# define ILI934X_RST_PIN PIN_SEN_IRQ_IN #elif defined(CONFIG_LCD_RSTPIN_EMMC_DATA3) -# define ILI934X_RST_PIN PIN_EMMC_DATA3 +# define ILI934X_RST_PIN PIN_EMMC_DATA3 #elif defined(CONFIG_LCD_RSTPIN_EMMC_DATA2) -# define ILI934X_RST_PIN PIN_EMMC_DATA2 +# define ILI934X_RST_PIN PIN_EMMC_DATA2 #elif defined(CONFIG_LCD_RSTPIN_I2S0_DATA_IN) -# define ILI934X_RST_PIN PIN_I2S0_DATA_IN +# define ILI934X_RST_PIN PIN_I2S0_DATA_IN #elif defined(CONFIG_LCD_RSTPIN_I2S0_DATA_OUT) -# define ILI934X_RST_PIN PIN_I2S0_DATA_OUT +# define ILI934X_RST_PIN PIN_I2S0_DATA_OUT #elif defined(CONFIG_LCD_RSTPIN_I2C0_SCL) \ || defined(CONFIG_LCD_RSTPIN_I2C0_SCL_E) -# define ILI934X_RST_PIN PIN_I2C0_BCK +# define ILI934X_RST_PIN PIN_I2C0_BCK #elif defined(CONFIG_LCD_RSTPIN_I2C0_SDA) \ || defined(CONFIG_LCD_RSTPIN_I2C0_SDA_E) -# define ILI934X_RST_PIN PIN_I2C0_BDT +# define ILI934X_RST_PIN PIN_I2C0_BDT #elif defined(CONFIG_LCD_RSTPIN_PWM2) -# define ILI934X_RST_PIN PIN_PWM2 +# define ILI934X_RST_PIN PIN_PWM2 #elif defined(CONFIG_LCD_RSTPIN_SPI2_MISO) -# define ILI934X_RST_PIN PIN_SPI2_MISO +# define ILI934X_RST_PIN PIN_SPI2_MISO #elif defined(CONFIG_LCD_RSTPIN_SPI3_CS1_X) -# define ILI934X_RST_PIN PIN_SPI3_CS1_X +# define ILI934X_RST_PIN PIN_SPI3_CS1_X #elif defined(CONFIG_LCD_RSTPIN_PWM0) -# define ILI934X_RST_PIN PIN_PWM0 +# define ILI934X_RST_PIN PIN_PWM0 #elif defined(CONFIG_LCD_RSTPIN_PWM1) -# define ILI934X_RST_PIN PIN_PWM1 +# define ILI934X_RST_PIN PIN_PWM1 #elif defined(CONFIG_LCD_RSTPIN_SPI2_MOSI) -# define ILI934X_RST_PIN PIN_SPI2_MOSI +# define ILI934X_RST_PIN PIN_SPI2_MOSI #elif defined(CONFIG_LCD_RSTPIN_PWM3) -# define ILI934X_RST_PIN PIN_PWM3 +# define ILI934X_RST_PIN PIN_PWM3 #elif defined(CONFIG_LCD_RSTPIN_HIF_IRQ_OUT) -# define ILI934X_RST_PIN PIN_HIF_IRQ_OUT +# define ILI934X_RST_PIN PIN_HIF_IRQ_OUT #endif /* ILI934X DC pin definition */ #if defined(CONFIG_LCD_DCPIN_UART2_TX) \ || defined(CONFIG_LCD_DCPIN_UART2_TX_E) -# define ILI934X_DC_PIN PIN_UART2_TXD +# define ILI934X_DC_PIN PIN_UART2_TXD #elif defined(CONFIG_LCD_DCPIN_UART2_RX) \ || defined(CONFIG_LCD_DCPIN_UART2_RX_E) -# define ILI934X_DC_PIN PIN_UART2_RXD +# define ILI934X_DC_PIN PIN_UART2_RXD #elif defined(CONFIG_LCD_DCPIN_UART2_RTS) -# define ILI934X_DC_PIN PIN_UART2_RTS +# define ILI934X_DC_PIN PIN_UART2_RTS #elif defined(CONFIG_LCD_DCPIN_UART2_CTS) -# define ILI934X_DC_PIN PIN_UART2_CTS +# define ILI934X_DC_PIN PIN_UART2_CTS #elif defined(CONFIG_LCD_DCPIN_I2S0_BCK) -# define ILI934X_DC_PIN PIN_I2S0_BCK +# define ILI934X_DC_PIN PIN_I2S0_BCK #elif defined(CONFIG_LCD_DCPIN_I2S0_LRCK) -# define ILI934X_DC_PIN PIN_I2S0_LRCK +# define ILI934X_DC_PIN PIN_I2S0_LRCK #elif defined(CONFIG_LCD_DCPIN_SEN_IRQ_IN) -# define ILI934X_DC_PIN PIN_SEN_IRQ_IN +# define ILI934X_DC_PIN PIN_SEN_IRQ_IN #elif defined(CONFIG_LCD_DCPIN_EMMC_DATA3) -# define ILI934X_DC_PIN PIN_EMMC_DATA3 +# define ILI934X_DC_PIN PIN_EMMC_DATA3 #elif defined(CONFIG_LCD_DCPIN_EMMC_DATA2) -# define ILI934X_DC_PIN PIN_EMMC_DATA2 +# define ILI934X_DC_PIN PIN_EMMC_DATA2 #elif defined(CONFIG_LCD_DCPIN_I2S0_DATA_IN) -# define ILI934X_DC_PIN PIN_I2S0_DATA_IN +# define ILI934X_DC_PIN PIN_I2S0_DATA_IN #elif defined(CONFIG_LCD_DCPIN_I2S0_DATA_OUT) -# define ILI934X_DC_PIN PIN_I2S0_DATA_OUT +# define ILI934X_DC_PIN PIN_I2S0_DATA_OUT #elif defined(CONFIG_LCD_DCPIN_I2C0_SCL) \ || defined(CONFIG_LCD_DCPIN_I2C0_SCL_E) -# define ILI934X_DC_PIN PIN_I2C0_BCK +# define ILI934X_DC_PIN PIN_I2C0_BCK #elif defined(CONFIG_LCD_DCPIN_I2C0_SDA) \ || defined(CONFIG_LCD_DCPIN_I2C0_SDA_E) -# define ILI934X_DC_PIN PIN_I2C0_BDT +# define ILI934X_DC_PIN PIN_I2C0_BDT #elif defined(CONFIG_LCD_DCPIN_PWM2) -# define ILI934X_DC_PIN PIN_PWM2 +# define ILI934X_DC_PIN PIN_PWM2 #elif defined(CONFIG_LCD_DCPIN_SPI2_MISO) -# define ILI934X_DC_PIN PIN_SPI2_MISO +# define ILI934X_DC_PIN PIN_SPI2_MISO #elif defined(CONFIG_LCD_DCPIN_SPI3_CS1_X) -# define ILI934X_DC_PIN PIN_SPI3_CS1_X +# define ILI934X_DC_PIN PIN_SPI3_CS1_X #elif defined(CONFIG_LCD_DCPIN_PWM0) -# define ILI934X_DC_PIN PIN_PWM0 +# define ILI934X_DC_PIN PIN_PWM0 #elif defined(CONFIG_LCD_DCPIN_PWM1) -# define ILI934X_DC_PIN PIN_PWM1 +# define ILI934X_DC_PIN PIN_PWM1 #elif defined(CONFIG_LCD_DCPIN_SPI2_MOSI) -# define ILI934X_DC_PIN PIN_SPI2_MOSI +# define ILI934X_DC_PIN PIN_SPI2_MOSI #elif defined(CONFIG_LCD_DCPIN_PWM3) -# define ILI934X_DC_PIN PIN_PWM3 +# define ILI934X_DC_PIN PIN_PWM3 #elif defined(CONFIG_LCD_DCPIN_HIF_IRQ_OUT) -# define ILI934X_DC_PIN PIN_HIF_IRQ_OUT +# define ILI934X_DC_PIN PIN_HIF_IRQ_OUT #endif #if !defined(CONFIG_LCD) -# if !defined(ILI934X_RST_PIN) -# define ILI934X_RST_PIN 0 -# endif +# if !defined(ILI934X_RST_PIN) +# define ILI934X_RST_PIN 0 +# endif -# if !defined(ILI934X_DC_PIN) -# define ILI934X_DC_PIN 0 -# endif +# if !defined(ILI934X_DC_PIN) +# define ILI934X_DC_PIN 0 +# endif #endif diff --git a/boards/arm/imxrt/teensy-4.x/src/imxrt_bringup.c b/boards/arm/imxrt/teensy-4.x/src/imxrt_bringup.c index 5bbf1daad9..b0c180d2e9 100644 --- a/boards/arm/imxrt/teensy-4.x/src/imxrt_bringup.c +++ b/boards/arm/imxrt/teensy-4.x/src/imxrt_bringup.c @@ -135,9 +135,9 @@ int imxrt_bringup(void) #endif #if !defined(CONFIG_BOARDCTL_USBDEVCTRL) && !defined(CONFIG_USBDEV_COMPOSITE) -# ifdef CONFIG_CDCACM +# ifdef CONFIG_CDCACM cdcacm_initialize(0, NULL); -# endif +# endif #endif #if defined(CONFIG_I2C_DRIVER) diff --git a/boards/arm/imxrt/teensy-4.x/src/imxrt_flexcan.c b/boards/arm/imxrt/teensy-4.x/src/imxrt_flexcan.c index 729ce7fe2a..ea9af24440 100644 --- a/boards/arm/imxrt/teensy-4.x/src/imxrt_flexcan.c +++ b/boards/arm/imxrt/teensy-4.x/src/imxrt_flexcan.c @@ -52,7 +52,7 @@ int imxrt_can_setup(void) int ret; #ifdef CONFIG_IMXRT_FLEXCAN3_AS_CAN0 -# ifdef CONFIG_IMXRT_FLEXCAN3 +# ifdef CONFIG_IMXRT_FLEXCAN3 ret = imxrt_caninitialize(3); if (ret < 0) { @@ -60,7 +60,7 @@ int imxrt_can_setup(void) return -ENODEV; } -# endif +# endif #endif #ifdef CONFIG_IMXRT_FLEXCAN1 @@ -84,7 +84,7 @@ int imxrt_can_setup(void) #endif #ifndef CONFIG_IMXRT_FLEXCAN3_AS_CAN0 -# ifdef CONFIG_IMXRT_FLEXCAN3 +# ifdef CONFIG_IMXRT_FLEXCAN3 ret = imxrt_caninitialize(3); if (ret < 0) { @@ -92,7 +92,7 @@ int imxrt_can_setup(void) return -ENODEV; } -# endif +# endif #endif UNUSED(ret); return OK; diff --git a/boards/arm/kinetis/freedom-k64f/src/k64_i2c.c b/boards/arm/kinetis/freedom-k64f/src/k64_i2c.c index ac56bd85b6..047788299f 100644 --- a/boards/arm/kinetis/freedom-k64f/src/k64_i2c.c +++ b/boards/arm/kinetis/freedom-k64f/src/k64_i2c.c @@ -33,9 +33,9 @@ #if defined(CONFIG_KINETIS_I2C0) -# if defined(CONFIG_SENSORS_FXOS8700CQ) -# include "nuttx/sensors/fxos8700cq.h" -# endif +# if defined(CONFIG_SENSORS_FXOS8700CQ) +# include "nuttx/sensors/fxos8700cq.h" +# endif /**************************************************************************** * Public Data diff --git a/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c b/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c index edd0bdcdb3..69672eb75b 100644 --- a/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c +++ b/boards/arm/lpc31xx/ea3131/src/lpc31_mem.c @@ -148,10 +148,10 @@ static void lpc31_sdraminitialize(void) */ #ifdef CONFIG_LPC31_SDRAMHCLK -# define HCLK CONFIG_LPC31_SDRAMHCLK +# define HCLK CONFIG_LPC31_SDRAMHCLK #else uint32_t hclk = lpc31_clkfreq(CLKID_MPMCCFGCLK2, DOMAINID_SYS); -# define HCLK hclk +# define HCLK hclk #endif /* Check RTL for divide by 2 possible. @@ -165,9 +165,9 @@ static void lpc31_sdraminitialize(void) { hclk2 >>= 1; } -# define HCLK2 hclk2 +# define HCLK2 hclk2 #else -# define HCLK2 hclk +# define HCLK2 hclk #endif up_udelay(100); diff --git a/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c b/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c index b7b94cf60b..c4ce648fbb 100644 --- a/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c +++ b/boards/arm/lpc31xx/ea3152/src/lpc31_mem.c @@ -148,10 +148,10 @@ static void lpc31_sdraminitialize(void) */ #ifdef CONFIG_LPC31_SDRAMHCLK -# define HCLK CONFIG_LPC31_SDRAMHCLK +# define HCLK CONFIG_LPC31_SDRAMHCLK #else uint32_t hclk = lpc31_clkfreq(CLKID_MPMCCFGCLK2, DOMAINID_SYS); -# define HCLK hclk +# define HCLK hclk #endif /* Check RTL for divide by 2 possible. @@ -165,9 +165,9 @@ static void lpc31_sdraminitialize(void) { hclk2 >>= 1; } -# define HCLK2 hclk2 +# define HCLK2 hclk2 #else -# define HCLK2 hclk +# define HCLK2 hclk #endif up_udelay(100); diff --git a/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc31_mem.c b/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc31_mem.c index d7da3bc798..96deba4186 100644 --- a/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc31_mem.c +++ b/boards/arm/lpc31xx/olimex-lpc-h3131/src/lpc31_mem.c @@ -129,10 +129,10 @@ static inline void lpc31_sdraminitialize(void) */ #ifdef CONFIG_LPC31_SDRAMHCLK -# define HCLK CONFIG_LPC31_SDRAMHCLK +# define HCLK CONFIG_LPC31_SDRAMHCLK #else uint32_t hclk = lpc31_clkfreq(CLKID_MPMCCFGCLK2, DOMAINID_SYS); -# define HCLK hclk +# define HCLK hclk #endif /* Check RTL for divide by 2 possible. @@ -146,9 +146,9 @@ static inline void lpc31_sdraminitialize(void) { hclk2 >>= 1; } -# define HCLK2 hclk2 +# define HCLK2 hclk2 #else -# define HCLK2 hclk +# define HCLK2 hclk #endif up_udelay(100); diff --git a/boards/arm/rp2040/common/src/rp2040_common_bringup.c b/boards/arm/rp2040/common/src/rp2040_common_bringup.c index ac3adfe685..516d47658d 100644 --- a/boards/arm/rp2040/common/src/rp2040_common_bringup.c +++ b/boards/arm/rp2040/common/src/rp2040_common_bringup.c @@ -534,35 +534,35 @@ int rp2040_common_bringup(void) #if defined(CONFIG_ADC) && defined(CONFIG_RP2040_ADC) -# ifdef CONFIG_RPC2040_ADC_CHANNEL0 -# define ADC_0 true -# else -# define ADC_0 false -# endif +# ifdef CONFIG_RPC2040_ADC_CHANNEL0 +# define ADC_0 true +# else +# define ADC_0 false +# endif -# ifdef CONFIG_RPC2040_ADC_CHANNEL1 -# define ADC_1 true -# else -# define ADC_1 false -# endif +# ifdef CONFIG_RPC2040_ADC_CHANNEL1 +# define ADC_1 true +# else +# define ADC_1 false +# endif -# ifdef CONFIG_RPC2040_ADC_CHANNEL2 -# define ADC_2 true -# else -# define ADC_2 false -# endif +# ifdef CONFIG_RPC2040_ADC_CHANNEL2 +# define ADC_2 true +# else +# define ADC_2 false +# endif -# ifdef CONFIG_RPC2040_ADC_CHANNEL3 -# define ADC_3 true -# else -# define ADC_3 false -# endif +# ifdef CONFIG_RPC2040_ADC_CHANNEL3 +# define ADC_3 true +# else +# define ADC_3 false +# endif -# ifdef CONFIG_RPC2040_ADC_TEMPERATURE -# define ADC_TEMP true -# else -# define ADC_TEMP false -# endif +# ifdef CONFIG_RPC2040_ADC_TEMPERATURE +# define ADC_TEMP true +# else +# define ADC_TEMP false +# endif ret = rp2040_adc_setup("/dev/adc0", ADC_0, ADC_1, ADC_2, ADC_3, ADC_TEMP); if (ret != OK) diff --git a/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_bringup.c b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_bringup.c index fdaecf8361..c68e846133 100644 --- a/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_bringup.c +++ b/boards/arm/s32k1xx/s32k148evb/src/s32k1xx_bringup.c @@ -154,21 +154,21 @@ int s32k1xx_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_S32K1XX_ENET +# ifdef CONFIG_S32K1XX_ENET s32k1xx_netinitialize(0); -# endif +# endif -# ifdef CONFIG_S32K1XX_FLEXCAN0 +# ifdef CONFIG_S32K1XX_FLEXCAN0 s32k1xx_caninitialize(0); -# endif +# endif -# ifdef CONFIG_S32K1XX_FLEXCAN1 +# ifdef CONFIG_S32K1XX_FLEXCAN1 s32k1xx_caninitialize(1); -# endif +# endif -# ifdef CONFIG_S32K1XX_FLEXCAN2 +# ifdef CONFIG_S32K1XX_FLEXCAN2 s32k1xx_caninitialize(2); -# endif +# endif #endif diff --git a/boards/arm/sam34/sam3u-ek/src/sam3u-ek.h b/boards/arm/sam34/sam3u-ek/src/sam3u-ek.h index 3acec983dd..0a3c1214df 100644 --- a/boards/arm/sam34/sam3u-ek/src/sam3u-ek.h +++ b/boards/arm/sam34/sam3u-ek/src/sam3u-ek.h @@ -227,7 +227,7 @@ void weak_function sam_spidev_initialize(void); #ifdef CONFIG_SAM34_HSMCI int weak_function sam_hsmciinit(void); #else -# define sam_hsmciinit() +# define sam_hsmciinit() #endif /**************************************************************************** diff --git a/boards/arm/sam34/sam4e-ek/src/sam4e-ek.h b/boards/arm/sam34/sam4e-ek/src/sam4e-ek.h index f0c1f64fdc..ad8181329a 100644 --- a/boards/arm/sam34/sam4e-ek/src/sam4e-ek.h +++ b/boards/arm/sam34/sam4e-ek/src/sam4e-ek.h @@ -399,7 +399,7 @@ void weak_function sam_spidev_initialize(void); #ifdef HAVE_HSMCI int sam_hsmci_initialize(int minor); #else -# define sam_hsmci_initialize(minor) (-ENOSYS) +# define sam_hsmci_initialize(minor) (-ENOSYS) #endif /**************************************************************************** diff --git a/boards/arm/sam34/sam4s-xplained-pro/src/sam4s-xplained-pro.h b/boards/arm/sam34/sam4s-xplained-pro/src/sam4s-xplained-pro.h index 6071f013a5..6ff993e2c3 100644 --- a/boards/arm/sam34/sam4s-xplained-pro/src/sam4s-xplained-pro.h +++ b/boards/arm/sam34/sam4s-xplained-pro/src/sam4s-xplained-pro.h @@ -51,7 +51,7 @@ #undef HAVE_USBMONITOR #if defined(CONFIG_MMCSD_SPI) -# define HAVE_MMCSD_SPI 1 +# define HAVE_MMCSD_SPI 1 #endif /* HSMCI */ @@ -189,8 +189,8 @@ /* NAND */ #ifdef HAVE_NAND -# define NAND_MINOR 0 -# define SAM_SMC_CS0 0 /* GPIO_SMC_NCS0 connect SAM_SMC_CS0_BASE */ +# define NAND_MINOR 0 +# define SAM_SMC_CS0 0 /* GPIO_SMC_NCS0 connect SAM_SMC_CS0_BASE */ int sam_nand_automount(int minor); #endif /* HAVE_NAND */ @@ -205,7 +205,7 @@ int sam_nand_automount(int minor); #ifdef HAVE_HSMCI int sam_hsmci_initialize(void); #else -# define sam_hsmci_initialize() +# define sam_hsmci_initialize() #endif int sam_sdinitialize(int port, int minor); diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c b/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c index 22510fcceb..567e7dccf9 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c +++ b/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c @@ -398,10 +398,10 @@ static inline void lcd_gramselect(void) static void lcd_setcursor(unsigned int x, unsigned int y) { #if defined(CONFIG_LCD_PORTRAIT) || defined (CONFIG_LCD_RPORTRAIT) -# if defined (CONFIG_LCD_RPORTRAIT) +# if defined (CONFIG_LCD_RPORTRAIT) x = (LCD_XRES - 1) - x; y = (LCD_YRES - 1) - y; -# endif +# endif write_reg(0x20, x); /* Row */ write_reg(0x21, y); /* Line */ #endif diff --git a/boards/arm/stm32/nucleo-f429zi/include/board.h b/boards/arm/stm32/nucleo-f429zi/include/board.h index 071d604a7b..14368a687e 100644 --- a/boards/arm/stm32/nucleo-f429zi/include/board.h +++ b/boards/arm/stm32/nucleo-f429zi/include/board.h @@ -266,8 +266,8 @@ * -- ----- --------- ----- */ - # define GPIO_USART6_RX GPIO_USART6_RX_2 - # define GPIO_USART6_TX GPIO_USART6_TX_2 + # define GPIO_USART6_RX GPIO_USART6_RX_2 + # define GPIO_USART6_TX GPIO_USART6_TX_2 #endif /* USART3: @@ -275,8 +275,8 @@ */ #if defined(CONFIG_NUCLEO_F429ZI_CONSOLE_VIRTUAL) - # define GPIO_USART3_RX GPIO_USART3_RX_3 - # define GPIO_USART3_TX GPIO_USART3_TX_3 + # define GPIO_USART3_RX GPIO_USART3_RX_3 + # define GPIO_USART3_TX GPIO_USART3_TX_3 #endif /* DMA channels *************************************************************/ diff --git a/boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h b/boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h index 327f3ac4f6..957df9100b 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h +++ b/boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h @@ -99,7 +99,7 @@ #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) #if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) -# define HAVE_SDIO +# define HAVE_SDIO #endif #if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_MMCSD_SDIO) diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c index 53f15c32de..468287319c 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c +++ b/boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c @@ -58,7 +58,7 @@ # define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_NUCLEO_SPI1_TEST_MODEx defined" -# endif +# endif #endif #if defined(CONFIG_NUCLEO_SPI2_TEST) @@ -72,7 +72,7 @@ # define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_NUCLEO_SPI2_TEST_MODEx defined" -# endif +# endif #endif #if defined(CONFIG_NUCLEO_SPI3_TEST) @@ -86,7 +86,7 @@ # define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_NUCLEO_SPI3_TEST_MODEx defined" -# endif +# endif #endif /**************************************************************************** @@ -96,78 +96,78 @@ #if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { -#if defined(GPIO_SPI1_CS0) +# if defined(GPIO_SPI1_CS0) GPIO_SPI1_CS0, -#else +# else 0, -#endif -#if defined(GPIO_SPI1_CS1) +# endif +# if defined(GPIO_SPI1_CS1) GPIO_SPI1_CS1, -#else +# else 0, -#endif -#if defined(GPIO_SPI1_CS2) +# endif +# if defined(GPIO_SPI1_CS2) GPIO_SPI1_CS2, -#else +# else 0, -#endif -#if defined(GPIO_SPI1_CS3) +# endif +# if defined(GPIO_SPI1_CS3) GPIO_SPI1_CS3 -#else +# else 0 -#endif +# endif }; #endif #if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { -#if defined(GPIO_SPI2_CS0) +# if defined(GPIO_SPI2_CS0) GPIO_SPI2_CS0, -#else +# else 0, -#endif -#if defined(GPIO_SPI2_CS1) +# endif +# if defined(GPIO_SPI2_CS1) GPIO_SPI2_CS1, -#else +# else 0, -#endif -#if defined(GPIO_SPI2_CS2) +# endif +# if defined(GPIO_SPI2_CS2) GPIO_SPI2_CS2, -#else +# else 0, -#endif -#if defined(GPIO_SPI2_CS3) +# endif +# if defined(GPIO_SPI2_CS3) GPIO_SPI2_CS3 -#else +# else 0 -#endif +# endif }; #endif #if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { -#if defined(GPIO_SPI3_CS0) +# if defined(GPIO_SPI3_CS0) GPIO_SPI3_CS0, -#else +# else 0, -#endif -#if defined(GPIO_SPI3_CS1) +# endif +# if defined(GPIO_SPI3_CS1) GPIO_SPI3_CS1, -#else +# else 0, -#endif -#if defined(GPIO_SPI3_CS2) +# endif +# if defined(GPIO_SPI3_CS2) GPIO_SPI3_CS2, -#else +# else 0, -#endif -#if defined(GPIO_SPI3_CS3) +# endif +# if defined(GPIO_SPI3_CS3) GPIO_SPI3_CS3 -#else +# else 0 -#endif +# endif }; #endif diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c index 9b32b20bd1..673152e7a6 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c @@ -1004,9 +1004,9 @@ static int stm3210e_poweroff(void) /* Disable timer 1 clocking */ #if defined(CONFIG_STM3210E_LCD_BACKLIGHT) -# if defined(CONFIG_STM3210E_LCD_PWM) +# if defined(CONFIG_STM3210E_LCD_PWM) modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); -#endif +# endif /* Configure the PA8 pin as an output */ diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c index 935bccf642..97dc5c25a6 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c @@ -978,13 +978,13 @@ static inline void stm3220g_lcdinitialize(void) /* Save the LCD type (not actually used at for anything important) */ #if !defined(CONFIG_STM32_ILI9320_DISABLE) -# if !defined(CONFIG_STM32_ILI9325_DISABLE) +# if !defined(CONFIG_STM32_ILI9325_DISABLE) if (id == ILI9325_ID) { g_lcddev.type = LCD_TYPE_ILI9325; } else -# endif +# endif { g_lcddev.type = LCD_TYPE_ILI9320; stm3220g_writereg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ @@ -1038,9 +1038,9 @@ static inline void stm3220g_lcdinitialize(void) /* Adjust the Gamma Curve (ILI9320/1) */ #if !defined(CONFIG_STM32_ILI9320_DISABLE) -# if !defined(CONFIG_STM32_ILI9325_DISABLE) +# if !defined(CONFIG_STM32_ILI9325_DISABLE) if (g_lcddev.type == LCD_TYPE_ILI9320) -# endif +# endif { stm3220g_writereg(LCD_REG_48, 0x0006); stm3220g_writereg(LCD_REG_49, 0x0101); @@ -1058,9 +1058,9 @@ static inline void stm3220g_lcdinitialize(void) /* Adjust the Gamma Curve (ILI9325) */ #if !defined(CONFIG_STM32_ILI9325_DISABLE) -# if !defined(CONFIG_STM32_ILI9320_DISABLE) +# if !defined(CONFIG_STM32_ILI9320_DISABLE) else -# endif +# endif { stm3220g_writereg(LCD_REG_48, 0x0007); stm3220g_writereg(LCD_REG_49, 0x0302); diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c index a809724f95..6189d99ae8 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c +++ b/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c @@ -981,13 +981,13 @@ static inline void stm3240g_lcdinitialize(void) */ #if !defined(CONFIG_STM3240G_ILI9320_DISABLE) -# if !defined(CONFIG_STM3240G_ILI9325_DISABLE) +# if !defined(CONFIG_STM3240G_ILI9325_DISABLE) if (id == ILI9325_ID) { g_lcddev.type = LCD_TYPE_ILI9325; } else -# endif +# endif { g_lcddev.type = LCD_TYPE_ILI9320; stm3240g_writereg(LCD_REG_229, 0x8000); /* Set the internal vcore voltage */ @@ -1041,9 +1041,9 @@ static inline void stm3240g_lcdinitialize(void) /* Adjust the Gamma Curve (ILI9320/1) */ #if !defined(CONFIG_STM3240G_ILI9320_DISABLE) -# if !defined(CONFIG_STM3240G_ILI9325_DISABLE) +# if !defined(CONFIG_STM3240G_ILI9325_DISABLE) if (g_lcddev.type == LCD_TYPE_ILI9320) -# endif +# endif { stm3240g_writereg(LCD_REG_48, 0x0006); stm3240g_writereg(LCD_REG_49, 0x0101); @@ -1061,9 +1061,9 @@ static inline void stm3240g_lcdinitialize(void) /* Adjust the Gamma Curve (ILI9325) */ #if !defined(CONFIG_STM3240G_ILI9325_DISABLE) -# if !defined(CONFIG_STM3240G_ILI9320_DISABLE) +# if !defined(CONFIG_STM3240G_ILI9320_DISABLE) else -# endif +# endif { stm3240g_writereg(LCD_REG_48, 0x0007); stm3240g_writereg(LCD_REG_49, 0x0302); diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c index 15983fad19..7dfe7d4460 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c +++ b/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c @@ -123,11 +123,11 @@ #endif #ifdef CONFIG_SENSORS_HYT271 -# define HAVE_SENSORS_DEVICE +# define HAVE_SENSORS_DEVICE #endif #ifdef CONFIG_SENSORS_DS18B20 -# define HAVE_SENSORS_DEVICE +# define HAVE_SENSORS_DEVICE #endif #ifdef CONFIG_LCD_BACKPACK diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c index 7bde4a633c..799549427b 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c +++ b/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c @@ -49,7 +49,7 @@ #define LCD_SPI_PORTNO 1 /* On SPI1 */ #ifndef CONFIG_LCD_CONTRAST -# define CONFIG_LCD_CONTRAST 0x1f +# define CONFIG_LCD_CONTRAST 0x1f #endif /**************************************************************************** diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c index 01f2e0e1a1..dea2416f21 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c +++ b/boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c @@ -48,7 +48,7 @@ #define LCD_SPI_PORTNO 1 /* On SPI1 */ #ifndef CONFIG_LCD_CONTRAST -# define CONFIG_LCD_CONTRAST 60 +# define CONFIG_LCD_CONTRAST 60 #endif /**************************************************************************** diff --git a/boards/arm/stm32/stm32f429i-disco/include/board.h b/boards/arm/stm32/stm32f429i-disco/include/board.h index bb3b8bb989..cfa65ba030 100644 --- a/boards/arm/stm32/stm32f429i-disco/include/board.h +++ b/boards/arm/stm32/stm32f429i-disco/include/board.h @@ -300,11 +300,11 @@ #if defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_LANDSCAPE) || \ defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RLANDSCAPE) -# define BOARD_LTDC_WIDTH 320 -# define BOARD_LTDC_HEIGHT 240 +# define BOARD_LTDC_WIDTH 320 +# define BOARD_LTDC_HEIGHT 240 #else -# define BOARD_LTDC_WIDTH 240 -# define BOARD_LTDC_HEIGHT 320 +# define BOARD_LTDC_WIDTH 240 +# define BOARD_LTDC_HEIGHT 320 #endif #define BOARD_LTDC_OUTPUT_BPP 16 @@ -372,8 +372,8 @@ #else /* Custom LCD display configuration */ -# define BOARD_LTDC_WIDTH ??? -# define BOARD_LTDC_HEIGHT ??? +# define BOARD_LTDC_WIDTH ??? +# define BOARD_LTDC_HEIGHT ??? #define BOARD_LTDC_HFP ??? #define BOARD_LTDC_HBP ??? diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c index 5820ea759e..25e148d83c 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c @@ -44,9 +44,9 @@ ****************************************************************************/ #ifdef CONFIG_STM32F429I_DISCO_ILI9341_LCDDEVICE -# define ILI9341_LCD_DEVICE CONFIG_STM32F429I_DISCO_ILI9341_LCDDEVICE +# define ILI9341_LCD_DEVICE CONFIG_STM32F429I_DISCO_ILI9341_LCDDEVICE #else -# define ILI9341_LCD_DEVICE 0 +# define ILI9341_LCD_DEVICE 0 #endif #ifdef CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE @@ -234,15 +234,15 @@ /* Set the display orientation */ #if defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_LANDSCAPE) -# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_LANDSCAPE_PARAM1 +# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_LANDSCAPE_PARAM1 # warning "ILI9341 doesn't support full landscape with RGB interface" #elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_PORTRAIT) -# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_PORTRAIT_PARAM1 +# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_PORTRAIT_PARAM1 #elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RLANDSCAPE) -# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_RLANDSCAPE_PARAM1 +# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_RLANDSCAPE_PARAM1 # warning "ILI9341 doesn't support full landscape with RGB interface" #elif defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_RPORTRAIT) -# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_RPORTRAIT_PARAM1 +# define STM32_ILI9341_MADCTL_PARAM ILI9341_MADCTL_RPORTRAIT_PARAM1 #else # error "display orientation not defined" #endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_spi.c b/boards/arm/stm32/stm32f4discovery/src/stm32_spi.c index cdb8d75c61..6b94c2932d 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_spi.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_spi.c @@ -89,12 +89,12 @@ void weak_function stm32_spidev_initialize(void) #if defined(CONFIG_LCD_UG2864AMBAG01) || defined(CONFIG_LCD_UG2864HSWEG01) || \ defined(CONFIG_LCD_SSD1351) stm32_configgpio(GPIO_OLED_CS); /* OLED chip select */ -# if defined(CONFIG_LCD_UG2864AMBAG01) +# if defined(CONFIG_LCD_UG2864AMBAG01) stm32_configgpio(GPIO_OLED_A0); /* OLED Command/Data */ -# endif -# if defined(CONFIG_LCD_UG2864HSWEG01) || defined(CONFIG_LCD_SSD1351) +# endif +# if defined(CONFIG_LCD_UG2864HSWEG01) || defined(CONFIG_LCD_SSD1351) stm32_configgpio(GPIO_OLED_DC); /* OLED Command/Data */ -# endif +# endif #endif } @@ -316,12 +316,12 @@ int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * registers." */ -# if defined(CONFIG_LCD_UG2864AMBAG01) +# if defined(CONFIG_LCD_UG2864AMBAG01) stm32_gpiowrite(GPIO_OLED_A0, !cmd); -# endif -# if defined(CONFIG_LCD_UG2864HSWEG01) || defined(CONFIG_LCD_SSD1351) +# endif +# if defined(CONFIG_LCD_UG2864HSWEG01) || defined(CONFIG_LCD_SSD1351) stm32_gpiowrite(GPIO_OLED_DC, !cmd); -# endif +# endif return OK; } #endif diff --git a/boards/arm/stm32f7/nucleo-144/src/nucleo-144.h b/boards/arm/stm32f7/nucleo-144/src/nucleo-144.h index 838670c94e..ef673d0c84 100644 --- a/boards/arm/stm32f7/nucleo-144/src/nucleo-144.h +++ b/boards/arm/stm32f7/nucleo-144/src/nucleo-144.h @@ -99,7 +99,7 @@ #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) #if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) -# define HAVE_SDIO +# define HAVE_SDIO #endif #if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_MMCSD_SDIO) diff --git a/boards/arm/stm32f7/nucleo-144/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-144/src/stm32_spi.c index 1fbf6aeb40..bcadb0d0d3 100644 --- a/boards/arm/stm32f7/nucleo-144/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-144/src/stm32_spi.c @@ -58,7 +58,7 @@ # define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_NUCLEO_SPI1_TEST_MODEx defined" -# endif +# endif #endif #if defined(CONFIG_NUCLEO_SPI2_TEST) @@ -72,7 +72,7 @@ # define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_NUCLEO_SPI2_TEST_MODEx defined" -# endif +# endif #endif #if defined(CONFIG_NUCLEO_SPI3_TEST) @@ -86,7 +86,7 @@ # define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_NUCLEO_SPI3_TEST_MODEx defined" -# endif +# endif #endif /**************************************************************************** @@ -96,78 +96,78 @@ #if defined(CONFIG_STM32F7_SPI1) static const uint32_t g_spi1gpio[] = { -#if defined(GPIO_SPI1_CS0) +# if defined(GPIO_SPI1_CS0) GPIO_SPI1_CS0, -#else +# else 0, -#endif -#if defined(GPIO_SPI1_CS1) +# endif +# if defined(GPIO_SPI1_CS1) GPIO_SPI1_CS1, -#else +# else 0, -#endif -#if defined(GPIO_SPI1_CS2) +# endif +# if defined(GPIO_SPI1_CS2) GPIO_SPI1_CS2, -#else +# else 0, -#endif -#if defined(GPIO_SPI1_CS3) +# endif +# if defined(GPIO_SPI1_CS3) GPIO_SPI1_CS3 -#else +# else 0 -#endif +# endif }; #endif #if defined(CONFIG_STM32F7_SPI2) static const uint32_t g_spi2gpio[] = { -#if defined(GPIO_SPI2_CS0) +# if defined(GPIO_SPI2_CS0) GPIO_SPI2_CS0, -#else +# else 0, -#endif -#if defined(GPIO_SPI2_CS1) +# endif +# if defined(GPIO_SPI2_CS1) GPIO_SPI2_CS1, -#else +# else 0, -#endif -#if defined(GPIO_SPI2_CS2) +# endif +# if defined(GPIO_SPI2_CS2) GPIO_SPI2_CS2, -#else +# else 0, -#endif -#if defined(GPIO_SPI2_CS3) +# endif +# if defined(GPIO_SPI2_CS3) GPIO_SPI2_CS3 -#else +# else 0 -#endif +# endif }; #endif #if defined(CONFIG_STM32F7_SPI3) static const uint32_t g_spi3gpio[] = { -#if defined(GPIO_SPI3_CS0) +# if defined(GPIO_SPI3_CS0) GPIO_SPI3_CS0, -#else +# else 0, -#endif -#if defined(GPIO_SPI3_CS1) +# endif +# if defined(GPIO_SPI3_CS1) GPIO_SPI3_CS1, -#else +# else 0, -#endif -#if defined(GPIO_SPI3_CS2) +# endif +# if defined(GPIO_SPI3_CS2) GPIO_SPI3_CS2, -#else +# else 0, -#endif -#if defined(GPIO_SPI3_CS3) +# endif +# if defined(GPIO_SPI3_CS3) GPIO_SPI3_CS3 -#else +# else 0 -#endif +# endif }; #endif diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c index e4883906fc..d22275a3f8 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c @@ -51,9 +51,9 @@ */ #ifdef ADC_HAVE_DMA -# define ADC3_NCHANNELS 6 +# define ADC3_NCHANNELS 6 #else -# define ADC3_NCHANNELS 1 +# define ADC3_NCHANNELS 1 #endif /* The number of ADC channels in the conversion list */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h index 56bb67da5f..ac3a632094 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h +++ b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h @@ -153,7 +153,7 @@ #define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) -# define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ +#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6) #ifdef CONFIG_USBHOST diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h b/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h index 4dd87a0f07..18630e5d5f 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h @@ -89,7 +89,7 @@ #define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) -# define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ +#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN10) #ifdef CONFIG_USBHOST diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c index f7af394962..fd187a9d84 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c @@ -48,7 +48,7 @@ #define LCD_SPI_PORTNO 1 /* On SPI1 */ #ifndef CONFIG_LCD_CONTRAST -# define CONFIG_LCD_CONTRAST 60 +# define CONFIG_LCD_CONTRAST 60 #endif /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l496zg/include/board.h b/boards/arm/stm32l4/nucleo-l496zg/include/board.h index f493e76e4c..11b612bdfb 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l496zg/include/board.h @@ -570,8 +570,8 @@ * -- ----- --------- ----- */ - # define GPIO_USART6_RX GPIO_USART6_RX_2 - # define GPIO_USART6_TX GPIO_USART6_TX_2 + # define GPIO_USART6_RX GPIO_USART6_RX_2 + # define GPIO_USART6_TX GPIO_USART6_TX_2 #endif /* USART3: diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h b/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h index 841c67da06..36766ebbe4 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h +++ b/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h @@ -102,7 +102,7 @@ #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) #if defined(CONFIG_STM32L4_SDMMC1) || defined(CONFIG_STM32L4_SDMMC2) -# define HAVE_SDIO +# define HAVE_SDIO #endif #if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_MMCSD_SDIO) diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c index 0b7e1cdc4d..efc5e36d67 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c @@ -58,7 +58,7 @@ # define CONFIG_NUCLEO_SPI1_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_NUCLEO_SPI1_TEST_MODEx defined" -# endif +# endif #endif #if defined(CONFIG_NUCLEO_SPI2_TEST) @@ -72,7 +72,7 @@ # define CONFIG_NUCLEO_SPI2_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_NUCLEO_SPI2_TEST_MODEx defined" -# endif +# endif #endif #if defined(CONFIG_NUCLEO_SPI3_TEST) @@ -86,7 +86,7 @@ # define CONFIG_NUCLEO_SPI3_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_NUCLEO_SPI3_TEST_MODEx defined" -# endif +# endif #endif /**************************************************************************** @@ -96,78 +96,78 @@ #if defined(CONFIG_STM32L4_SPI1) static const uint32_t g_spi1gpio[] = { -#if defined(GPIO_SPI1_CS0) +# if defined(GPIO_SPI1_CS0) GPIO_SPI1_CS0, -#else +# else 0, -#endif -#if defined(GPIO_SPI1_CS1) +# endif +# if defined(GPIO_SPI1_CS1) GPIO_SPI1_CS1, -#else +# else 0, -#endif -#if defined(GPIO_SPI1_CS2) +# endif +# if defined(GPIO_SPI1_CS2) GPIO_SPI1_CS2, -#else +# else 0, -#endif -#if defined(GPIO_SPI1_CS3) +# endif +# if defined(GPIO_SPI1_CS3) GPIO_SPI1_CS3 -#else +# else 0 -#endif +# endif }; #endif #if defined(CONFIG_STM32L4_SPI2) static const uint32_t g_spi2gpio[] = { -#if defined(GPIO_SPI2_CS0) +# if defined(GPIO_SPI2_CS0) GPIO_SPI2_CS0, -#else +# else 0, -#endif -#if defined(GPIO_SPI2_CS1) +# endif +# if defined(GPIO_SPI2_CS1) GPIO_SPI2_CS1, -#else +# else 0, -#endif -#if defined(GPIO_SPI2_CS2) +# endif +# if defined(GPIO_SPI2_CS2) GPIO_SPI2_CS2, -#else +# else 0, -#endif -#if defined(GPIO_SPI2_CS3) +# endif +# if defined(GPIO_SPI2_CS3) GPIO_SPI2_CS3 -#else +# else 0 -#endif +# endif }; #endif #if defined(CONFIG_STM32L4_SPI3) static const uint32_t g_spi3gpio[] = { -#if defined(GPIO_SPI3_CS0) +# if defined(GPIO_SPI3_CS0) GPIO_SPI3_CS0, -#else +# else 0, -#endif -#if defined(GPIO_SPI3_CS1) +# endif +# if defined(GPIO_SPI3_CS1) GPIO_SPI3_CS1, -#else +# else 0, -#endif -#if defined(GPIO_SPI3_CS2) +# endif +# if defined(GPIO_SPI3_CS2) GPIO_SPI3_CS2, -#else +# else 0, -#endif -#if defined(GPIO_SPI3_CS3) +# endif +# if defined(GPIO_SPI3_CS3) GPIO_SPI3_CS3 -#else +# else 0 -#endif +# endif }; #endif diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c index 7e68e72758..c8b8264cdd 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c @@ -46,7 +46,7 @@ ****************************************************************************/ #ifndef CONFIG_LCD_CONTRAST -# define CONFIG_LCD_CONTRAST 0x5f +# define CONFIG_LCD_CONTRAST 0x5f #endif /**************************************************************************** diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c b/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c index 25160afe23..bd0b5032d8 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c @@ -93,17 +93,17 @@ static const struct touch_config_s tp_config = .slope = TOUCHPAD_SLOPE, .tie_opt = TOUCHPAD_TIE_OPT, .fsm_mode = TOUCHPAD_FSM_MODE, -# ifdef CONFIG_ESP32S2_TOUCH_FILTER +# ifdef CONFIG_ESP32S2_TOUCH_FILTER .filter_mode = TOUCHPAD_FILTER_MODE, .filter_debounce_cnt = TOUCHPAD_FILTER_DEBOUNCE, .filter_noise_thr = TOUCHPAD_FILTER_NOISE, .filter_jitter_step = TOUCHPAD_FILTER_JITTER, .filter_smh_lvl = TOUCHPAD_FILTER_SMH, -# endif -# ifdef CONFIG_ESP32S2_TOUCH_DENOISE +# endif +# ifdef CONFIG_ESP32S2_TOUCH_DENOISE .denoise_grade = TOUCHPAD_DENOISE_GRADE, .denoise_cap_level = TOUCHPAD_DENOISE_CAP -# endif +# endif }; #endif diff --git a/drivers/lcd/skeleton.c b/drivers/lcd/skeleton.c index 44caecd61b..62a80f4ec4 100644 --- a/drivers/lcd/skeleton.c +++ b/drivers/lcd/skeleton.c @@ -76,13 +76,13 @@ /* Debug ********************************************************************/ #ifdef CONFIG_LCD_SKELDEBUG -# define skelerr(format, ...) _err(format, ##__VA_ARGS__) -# define skelwarn(format, ...) _warn(format, ##__VA_ARGS__) -# define skelinfo(format, ...) _info(format, ##__VA_ARGS__) +# define skelerr(format, ...) _err(format, ##__VA_ARGS__) +# define skelwarn(format, ...) _warn(format, ##__VA_ARGS__) +# define skelinfo(format, ...) _info(format, ##__VA_ARGS__) #else -# define skelerr(x...) -# define skelwarn(x...) -# define skelinfo(x...) +# define skelerr(x...) +# define skelwarn(x...) +# define skelinfo(x...) #endif /**************************************************************************** diff --git a/drivers/mmcsd/mmcsd_sdio.c b/drivers/mmcsd/mmcsd_sdio.c index cc5cf8b0c2..b21a8fdea4 100644 --- a/drivers/mmcsd/mmcsd_sdio.c +++ b/drivers/mmcsd/mmcsd_sdio.c @@ -88,9 +88,9 @@ #define IS_EMPTY(priv) (priv->type == MMCSD_CARDTYPE_UNKNOWN) #if CONFIG_MMCSD_MULTIBLOCK_LIMIT == 0 -# define MMCSD_MULTIBLOCK_LIMIT SSIZE_MAX +# define MMCSD_MULTIBLOCK_LIMIT SSIZE_MAX #else -# define MMCSD_MULTIBLOCK_LIMIT CONFIG_MMCSD_MULTIBLOCK_LIMIT +# define MMCSD_MULTIBLOCK_LIMIT CONFIG_MMCSD_MULTIBLOCK_LIMIT #endif #define MMCSD_CAPACITY(b, s) ((s) >= 10 ? (b) << ((s) - 10) : (b) >> (10 - (s))) diff --git a/drivers/mtd/mx25lx.c b/drivers/mtd/mx25lx.c index 68257ab421..e977650c30 100644 --- a/drivers/mtd/mx25lx.c +++ b/drivers/mtd/mx25lx.c @@ -209,11 +209,11 @@ /* Debug ********************************************************************/ #ifdef CONFIG_MX25L_DEBUG -# define mxlerr(format, ...) _err(format, ##__VA_ARGS__) -# define mxlinfo(format, ...) _info(format, ##__VA_ARGS__) +# define mxlerr(format, ...) _err(format, ##__VA_ARGS__) +# define mxlinfo(format, ...) _info(format, ##__VA_ARGS__) #else -# define mxlerr(x...) -# define mxlinfo(x...) +# define mxlerr(x...) +# define mxlinfo(x...) #endif /**************************************************************************** diff --git a/drivers/mtd/mx35.c b/drivers/mtd/mx35.c index 992d5aef01..4e7d4f35df 100644 --- a/drivers/mtd/mx35.c +++ b/drivers/mtd/mx35.c @@ -64,11 +64,11 @@ /* Debug ********************************************************************/ #ifdef CONFIG_MX35_DEBUG -# define mx35err(format, ...) _err(format, ##__VA_ARGS__) -# define mx35info(format, ...) _info(format, ##__VA_ARGS__) +# define mx35err(format, ...) _err(format, ##__VA_ARGS__) +# define mx35info(format, ...) _info(format, ##__VA_ARGS__) #else -# define mx35err(x...) -# define mx35info(x...) +# define mx35err(x...) +# define mx35info(x...) #endif /* Identification register values *******************************************/ diff --git a/drivers/mtd/sst26.c b/drivers/mtd/sst26.c index 18a59a23cc..a2b41c8478 100644 --- a/drivers/mtd/sst26.c +++ b/drivers/mtd/sst26.c @@ -183,11 +183,11 @@ /* Debug ********************************************************************/ #ifdef CONFIG_SST26_DEBUG -# define ssterr(format, ...) _err(format, ##__VA_ARGS__) -# define sstinfo(format, ...) _info(format, ##__VA_ARGS__) +# define ssterr(format, ...) _err(format, ##__VA_ARGS__) +# define sstinfo(format, ...) _info(format, ##__VA_ARGS__) #else -# define ssterr(x...) -# define sstinfo(x...) +# define ssterr(x...) +# define sstinfo(x...) #endif /**************************************************************************** diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index 5d6986c0f3..bd2a1a1078 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -77,7 +77,7 @@ */ #ifndef CONFIG_FTMAC100_NINTERFACES -# define CONFIG_FTMAC100_NINTERFACES 1 +# define CONFIG_FTMAC100_NINTERFACES 1 #endif /* TX timeout = 1 minute */ @@ -102,24 +102,24 @@ #define ETH_ZLEN 60 #if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) -# define MACCR_ENABLE_ALL (FTMAC100_MACCR_XMT_EN | \ - FTMAC100_MACCR_RCV_EN | \ - FTMAC100_MACCR_XDMA_EN | \ - FTMAC100_MACCR_RDMA_EN | \ - FTMAC100_MACCR_CRC_APD | \ - FTMAC100_MACCR_FULLDUP | \ - FTMAC100_MACCR_RX_RUNT | \ - FTMAC100_MACCR_HT_MULTI_EN | \ - FTMAC100_MACCR_RX_BROADPKT) +# define MACCR_ENABLE_ALL (FTMAC100_MACCR_XMT_EN | \ + FTMAC100_MACCR_RCV_EN | \ + FTMAC100_MACCR_XDMA_EN | \ + FTMAC100_MACCR_RDMA_EN | \ + FTMAC100_MACCR_CRC_APD | \ + FTMAC100_MACCR_FULLDUP | \ + FTMAC100_MACCR_RX_RUNT | \ + FTMAC100_MACCR_HT_MULTI_EN | \ + FTMAC100_MACCR_RX_BROADPKT) #else -# define MACCR_ENABLE_ALL (FTMAC100_MACCR_XMT_EN | \ - FTMAC100_MACCR_RCV_EN | \ - FTMAC100_MACCR_XDMA_EN | \ - FTMAC100_MACCR_RDMA_EN | \ - FTMAC100_MACCR_CRC_APD | \ - FTMAC100_MACCR_FULLDUP | \ - FTMAC100_MACCR_RX_RUNT | \ - FTMAC100_MACCR_RX_BROADPKT) +# define MACCR_ENABLE_ALL (FTMAC100_MACCR_XMT_EN | \ + FTMAC100_MACCR_RCV_EN | \ + FTMAC100_MACCR_XDMA_EN | \ + FTMAC100_MACCR_RDMA_EN | \ + FTMAC100_MACCR_CRC_APD | \ + FTMAC100_MACCR_FULLDUP | \ + FTMAC100_MACCR_RX_RUNT | \ + FTMAC100_MACCR_RX_BROADPKT) #endif #define MACCR_DISABLE_ALL 0 diff --git a/drivers/net/skeleton.c b/drivers/net/skeleton.c index 7818d13da0..81d7a22690 100644 --- a/drivers/net/skeleton.c +++ b/drivers/net/skeleton.c @@ -72,7 +72,7 @@ */ #ifndef CONFIG_NET_SKELETON_NINTERFACES -# define CONFIG_NET_SKELETON_NINTERFACES 1 +# define CONFIG_NET_SKELETON_NINTERFACES 1 #endif /* TX timeout = 1 minute */ diff --git a/drivers/net/slip.c b/drivers/net/slip.c index c15220018a..ddccc0ae91 100644 --- a/drivers/net/slip.c +++ b/drivers/net/slip.c @@ -94,7 +94,7 @@ */ #ifndef CONFIG_NET_SLIP_NINTERFACES -# define CONFIG_NET_SLIP_NINTERFACES 1 +# define CONFIG_NET_SLIP_NINTERFACES 1 #endif /* SLIP special character codes ********************************************/ diff --git a/drivers/net/telnet.c b/drivers/net/telnet.c index 5d7bac4eeb..b86f35544a 100644 --- a/drivers/net/telnet.c +++ b/drivers/net/telnet.c @@ -142,7 +142,7 @@ struct telnet_dev_s static inline void telnet_dumpbuffer(FAR const char *msg, FAR const char *buffer, unsigned int nbytes); #else -# define telnet_dumpbuffer(msg,buffer,nbytes) +# define telnet_dumpbuffer(msg,buffer,nbytes) #endif static void telnet_getchar(FAR struct telnet_dev_s *priv, uint8_t ch, FAR char *dest, int *nread); diff --git a/drivers/usbdev/composite.h b/drivers/usbdev/composite.h index 41c02c016a..b81fcbfbeb 100644 --- a/drivers/usbdev/composite.h +++ b/drivers/usbdev/composite.h @@ -69,7 +69,7 @@ # ifndef CONFIG_COMPOSITE_VENDORSTR # warning "No Vendor string specified" # define CONFIG_COMPOSITE_VENDORSTR "NuttX" -# endif +# endif # ifndef CONFIG_COMPOSITE_PRODUCTSTR # warning "No Product string specified" diff --git a/drivers/usbdev/usbmsc.h b/drivers/usbdev/usbmsc.h index 2c501dbe06..d9b9b4f99c 100644 --- a/drivers/usbdev/usbmsc.h +++ b/drivers/usbdev/usbmsc.h @@ -173,7 +173,7 @@ # ifndef CONFIG_USBMSC_VENDORSTR # warning "No Vendor string specified" # define CONFIG_USBMSC_VENDORSTR "NuttX" -# endif +# endif # ifndef CONFIG_USBMSC_PRODUCTSTR # warning "No Product string specified" diff --git a/drivers/virtio/virtio-mmio-blk.c b/drivers/virtio/virtio-mmio-blk.c index 31e815c6b9..5fbd92c81c 100644 --- a/drivers/virtio/virtio-mmio-blk.c +++ b/drivers/virtio/virtio-mmio-blk.c @@ -60,7 +60,7 @@ */ #ifndef VIRTIO_BLK_NINTERFACES -# define VIRTIO_BLK_NINTERFACES 1 +# define VIRTIO_BLK_NINTERFACES 1 #endif /**************************************************************************** diff --git a/drivers/virtio/virtio-mmio-net.c b/drivers/virtio/virtio-mmio-net.c index 7e5ac7713c..cbf1127936 100644 --- a/drivers/virtio/virtio-mmio-net.c +++ b/drivers/virtio/virtio-mmio-net.c @@ -78,7 +78,7 @@ */ #ifndef VIRTIO_NET_NINTERFACES -# define VIRTIO_NET_NINTERFACES 1 +# define VIRTIO_NET_NINTERFACES 1 #endif /* TX timeout = 1 minute */ diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.c b/drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.c index c799865a83..f71c364c1a 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.c +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.c @@ -74,9 +74,9 @@ #if defined(CONFIG_SCHED_HPWORK) && \ (CONFIG_IEEE80211_BROADCOM_SCHED_PRIORITY >= CONFIG_SCHED_HPWORKPRIORITY) -# define BCMFWORK HPWORK +# define BCMFWORK HPWORK #else -# define BCMFWORK LPWORK +# define BCMFWORK LPWORK #endif /* CONFIG_IEEE80211_BROADCOM_NINTERFACES determines the number of physical @@ -84,13 +84,13 @@ */ #ifndef CONFIG_IEEE80211_BROADCOM_NINTERFACES -# define CONFIG_IEEE80211_BROADCOM_NINTERFACES 1 +# define CONFIG_IEEE80211_BROADCOM_NINTERFACES 1 #endif #ifdef CONFIG_IEEE80211_BROADCOM_LOWPOWER -# define LP_IFDOWN_TIMEOUT CONFIG_IEEE80211_BROADCOM_LP_IFDOWN_TIMEOUT -# define LP_DTIM_TIMEOUT CONFIG_IEEE80211_BROADCOM_LP_DTIM_TIMEOUT -# define LP_DTIM_INTERVAL CONFIG_IEEE80211_BROADCOM_LP_DTIM_INTERVAL +# define LP_IFDOWN_TIMEOUT CONFIG_IEEE80211_BROADCOM_LP_IFDOWN_TIMEOUT +# define LP_DTIM_TIMEOUT CONFIG_IEEE80211_BROADCOM_LP_DTIM_TIMEOUT +# define LP_DTIM_INTERVAL CONFIG_IEEE80211_BROADCOM_LP_DTIM_INTERVAL #endif /* This is a helper pointer for accessing the contents of Ethernet header */ diff --git a/fs/fat/fs_fat32.h b/fs/fat/fs_fat32.h index 6be55c1b2b..afff4598a0 100644 --- a/fs/fat/fs_fat32.h +++ b/fs/fat/fs_fat32.h @@ -274,50 +274,50 @@ /* Sizes and limits */ -# if CONFIG_FAT_MAXFNAME > CONFIG_NAME_MAX && CONFIG_NAME_MAX >= 12 -# warning CONFIG_FAT_MAXFNAME may not exceed NAME_MAX (CONFIG_NAME_MAX) -# undef CONFIG_FAT_MAXFNAME -# define CONFIG_FAT_MAXFNAME CONFIG_NAME_MAX -# endif +# if CONFIG_FAT_MAXFNAME > CONFIG_NAME_MAX && CONFIG_NAME_MAX >= 12 +# warning CONFIG_FAT_MAXFNAME may not exceed NAME_MAX (CONFIG_NAME_MAX) +# undef CONFIG_FAT_MAXFNAME +# define CONFIG_FAT_MAXFNAME CONFIG_NAME_MAX +# endif -# if CONFIG_FAT_MAXFNAME < 12 -# undef CONFIG_FAT_MAXFNAME -# define CONFIG_FAT_MAXFNAME 12 -# endif +# if CONFIG_FAT_MAXFNAME < 12 +# undef CONFIG_FAT_MAXFNAME +# define CONFIG_FAT_MAXFNAME 12 +# endif -# ifndef CONFIG_FAT_MAXFNAME /* The maximum support filename can be limited */ -# define LDIR_MAXFNAME 255 /* Max unicode characters in file name */ -# elif CONFIG_FAT_MAXFNAME <= 255 -# define LDIR_MAXFNAME CONFIG_FAT_MAXFNAME -# else -# error "Illegal value for CONFIG_FAT_MAXFNAME" -# endif +# ifndef CONFIG_FAT_MAXFNAME /* The maximum support filename can be limited */ +# define LDIR_MAXFNAME 255 /* Max unicode characters in file name */ +# elif CONFIG_FAT_MAXFNAME <= 255 +# define LDIR_MAXFNAME CONFIG_FAT_MAXFNAME +# else +# error "Illegal value for CONFIG_FAT_MAXFNAME" +# endif -# define LDIR_MAXLFNCHARS 13 /* Max unicode characters in one LFN entry */ -# define LDIR_MAXLFNS 20 /* Max number of LFN entries */ +# define LDIR_MAXLFNCHARS 13 /* Max unicode characters in one LFN entry */ +# define LDIR_MAXLFNS 20 /* Max number of LFN entries */ /* LFN directory entry offsets */ -# define LDIR_SEQ 0 /* 1@ 0: Sequence number */ -# define LDIR_WCHAR1_5 1 /* 10@ 1: File name characters 1-5 (5 Unicode characters) */ -# define LDIR_ATTRIBUTES 11 /* 1@11: File attributes (always 0x0f) */ -# define LDIR_NTRES 12 /* 1@12: Reserved for use by NT (always 0x00) */ -# define LDIR_CHECKSUM 13 /* 1@13: Checksum of the DOS filename */ -# define LDIR_WCHAR6_11 14 /* 12@14: File name characters 6-11 (6 Unicode characters) */ -# define LDIR_FSTCLUSTLO 26 /* 2@26: First cluster (always 0x0000) */ -# define LDIR_WCHAR12_13 28 /* 4@28: File name characters 12-13 (2 Unicode characters) */ +# define LDIR_SEQ 0 /* 1@ 0: Sequence number */ +# define LDIR_WCHAR1_5 1 /* 10@ 1: File name characters 1-5 (5 Unicode characters) */ +# define LDIR_ATTRIBUTES 11 /* 1@11: File attributes (always 0x0f) */ +# define LDIR_NTRES 12 /* 1@12: Reserved for use by NT (always 0x00) */ +# define LDIR_CHECKSUM 13 /* 1@13: Checksum of the DOS filename */ +# define LDIR_WCHAR6_11 14 /* 12@14: File name characters 6-11 (6 Unicode characters) */ +# define LDIR_FSTCLUSTLO 26 /* 2@26: First cluster (always 0x0000) */ +# define LDIR_WCHAR12_13 28 /* 4@28: File name characters 12-13 (2 Unicode characters) */ /* LFN sequence number and allocation status */ -# define LDIR0_EMPTY DIR0_EMPTY /* The directory entry is empty */ -# define LDIR0_ALLEMPTY DIR0_ALLEMPTY /* This entry and all following are empty */ -# define LDIR0_E5 DIR0_E5 /* The actual value is 0xe5 */ -# define LDIR0_LAST 0x40 /* Last LFN in file name (appears first) */ -# define LDIR0_SEQ_MASK 0x1f /* Mask for sequence number (1-20) */ +# define LDIR0_EMPTY DIR0_EMPTY /* The directory entry is empty */ +# define LDIR0_ALLEMPTY DIR0_ALLEMPTY /* This entry and all following are empty */ +# define LDIR0_E5 DIR0_E5 /* The actual value is 0xe5 */ +# define LDIR0_LAST 0x40 /* Last LFN in file name (appears first) */ +# define LDIR0_SEQ_MASK 0x1f /* Mask for sequence number (1-20) */ /* The LFN entry attribute */ -# define LDDIR_LFNATTR 0x0f +# define LDDIR_LFNATTR 0x0f #endif /* File system types */ @@ -385,17 +385,17 @@ /* Access to data in raw sector data */ -#define UBYTE_VAL(p,o) (((uint8_t*)(p))[o]) -#define UBYTE_PTR(p,o) &UBYTE_VAL(p,o) -#define UBYTE_PUT(p,o,v) (UBYTE_VAL(p,o)=(uint8_t)(v)) +#define UBYTE_VAL(p,o) (((uint8_t*)(p))[o]) +#define UBYTE_PTR(p,o) &UBYTE_VAL(p,o) +#define UBYTE_PUT(p,o,v) (UBYTE_VAL(p,o)=(uint8_t)(v)) -#define UINT16_PTR(p,o) ((uint16_t*)UBYTE_PTR(p,o)) -#define UINT16_VAL(p,o) (*UINT16_PTR(p,o)) -#define UINT16_PUT(p,o,v) (UINT16_VAL(p,o)=(uint16_t)(v)) +#define UINT16_PTR(p,o) ((uint16_t*)UBYTE_PTR(p,o)) +#define UINT16_VAL(p,o) (*UINT16_PTR(p,o)) +#define UINT16_PUT(p,o,v) (UINT16_VAL(p,o)=(uint16_t)(v)) -#define UINT32_PTR(p,o) ((uint32_t*)UBYTE_PTR(p,o)) -#define UINT32_VAL(p,o) (*UINT32_PTR(p,o)) -#define UINT32_PUT(p,o,v) (UINT32_VAL(p,o)=(uint32_t)(v)) +#define UINT32_PTR(p,o) ((uint32_t*)UBYTE_PTR(p,o)) +#define UINT32_VAL(p,o) (*UINT32_PTR(p,o)) +#define UINT32_PUT(p,o,v) (UINT32_VAL(p,o)=(uint32_t)(v)) /* Regardless of the endian-ness of the target or alignment of the data, no * special operations are required for byte, string or byte array accesses. @@ -403,70 +403,70 @@ * accessed byte-by-byte for big-endian targets. */ -#define MBR_GETSECPERCLUS(p) UBYTE_VAL(p,MBR_SECPERCLUS) -#define MBR_GETNUMFATS(p) UBYTE_VAL(p,MBR_NUMFATS) -#define MBR_GETMEDIA(p) UBYTE_VAL(p,MBR_MEDIA) -#define MBR_GETDRVNUM16(p) UBYTE_VAL(p,MBR16_DRVNUM) -#define MBR_GETDRVNUM32(p) UBYTE_VAL(p,MBR32_DRVNUM) -#define MBR_GETBOOTSIG16(p) UBYTE_VAL(p,MBR16_BOOTSIG) -#define MBR_GETBOOTSIG32(p) UBYTE_VAL(p,MBR32_BOOTSIG) +#define MBR_GETSECPERCLUS(p) UBYTE_VAL(p,MBR_SECPERCLUS) +#define MBR_GETNUMFATS(p) UBYTE_VAL(p,MBR_NUMFATS) +#define MBR_GETMEDIA(p) UBYTE_VAL(p,MBR_MEDIA) +#define MBR_GETDRVNUM16(p) UBYTE_VAL(p,MBR16_DRVNUM) +#define MBR_GETDRVNUM32(p) UBYTE_VAL(p,MBR32_DRVNUM) +#define MBR_GETBOOTSIG16(p) UBYTE_VAL(p,MBR16_BOOTSIG) +#define MBR_GETBOOTSIG32(p) UBYTE_VAL(p,MBR32_BOOTSIG) -#define FBR_GETSECPERCLUS(p) UBYTE_VAL(p,FBR_SECPERCLUS) -#define FBR_GETNUMFATS(p) UBYTE_VAL(p,FBR_NUMFATS) -#define FBR_GETMEDIA(p) UBYTE_VAL(p,FBR_MEDIA) -#define FBR_GETDRVNUM16(p) UBYTE_VAL(p,FBR16_DRVNUM) -#define FBR_GETDRVNUM32(p) UBYTE_VAL(p,FBR32_DRVNUM) -#define FBR_GETBOOTSIG16(p) UBYTE_VAL(p,FBR16_BOOTSIG) -#define FBR_GETBOOTSIG32(p) UBYTE_VAL(p,FBR32_BOOTSIG) +#define FBR_GETSECPERCLUS(p) UBYTE_VAL(p,FBR_SECPERCLUS) +#define FBR_GETNUMFATS(p) UBYTE_VAL(p,FBR_NUMFATS) +#define FBR_GETMEDIA(p) UBYTE_VAL(p,FBR_MEDIA) +#define FBR_GETDRVNUM16(p) UBYTE_VAL(p,FBR16_DRVNUM) +#define FBR_GETDRVNUM32(p) UBYTE_VAL(p,FBR32_DRVNUM) +#define FBR_GETBOOTSIG16(p) UBYTE_VAL(p,FBR16_BOOTSIG) +#define FBR_GETBOOTSIG32(p) UBYTE_VAL(p,FBR32_BOOTSIG) -#define PART_GETTYPE(n,p) UBYTE_VAL(p,PART_ENTRY(n)+PART_TYPE) -#define PART1_GETTYPE(p) UBYTE_VAL(p,PART_ENTRY1+PART_TYPE) -#define PART2_GETTYPE(p) UBYTE_VAL(p,PART_ENTRY2+PART_TYPE) -#define PART3_GETTYPE(p) UBYTE_VAL(p,PART_ENTRY3+PART_TYPE) -#define PART4_GETTYPE(p) UBYTE_VAL(p,PART_ENTRY4+PART_TYPE) +#define PART_GETTYPE(n,p) UBYTE_VAL(p,PART_ENTRY(n)+PART_TYPE) +#define PART1_GETTYPE(p) UBYTE_VAL(p,PART_ENTRY1+PART_TYPE) +#define PART2_GETTYPE(p) UBYTE_VAL(p,PART_ENTRY2+PART_TYPE) +#define PART3_GETTYPE(p) UBYTE_VAL(p,PART_ENTRY3+PART_TYPE) +#define PART4_GETTYPE(p) UBYTE_VAL(p,PART_ENTRY4+PART_TYPE) -#define DIR_GETATTRIBUTES(p) UBYTE_VAL(p,DIR_ATTRIBUTES) -#define DIR_GETNTRES(p) UBYTE_VAL(p,DIR_NTRES) -#define DIR_GETCRTTIMETENTH(p) UBYTE_VAL(p,DIR_CRTTIMETENTH) +#define DIR_GETATTRIBUTES(p) UBYTE_VAL(p,DIR_ATTRIBUTES) +#define DIR_GETNTRES(p) UBYTE_VAL(p,DIR_NTRES) +#define DIR_GETCRTTIMETENTH(p) UBYTE_VAL(p,DIR_CRTTIMETENTH) #ifdef CONFIG_FAT_LFN -# define LDIR_GETSEQ(p) UBYTE_VAL(p,LDIR_SEQ) -# define LDIR_GETATTRIBUTES(p) UBYTE_VAL(p,LDIR_ATTRIBUTES) -# define LDIR_GETNTRES(p) UBYTE_VAL(p,LDIR_NTRES) -# define LDIR_GETCHECKSUM(p) UBYTE_VAL(p,LDIR_CHECKSUM) +# define LDIR_GETSEQ(p) UBYTE_VAL(p,LDIR_SEQ) +# define LDIR_GETATTRIBUTES(p) UBYTE_VAL(p,LDIR_ATTRIBUTES) +# define LDIR_GETNTRES(p) UBYTE_VAL(p,LDIR_NTRES) +# define LDIR_GETCHECKSUM(p) UBYTE_VAL(p,LDIR_CHECKSUM) #endif -#define MBR_PUTSECPERCLUS(p,v) UBYTE_PUT(p,MBR_SECPERCLUS,v) -#define MBR_PUTNUMFATS(p,v) UBYTE_PUT(p,MBR_NUMFATS,v) -#define MBR_PUTMEDIA(p,v) UBYTE_PUT(p,MBR_MEDIA,v) -#define MBR_PUTDRVNUM16(p,v) UBYTE_PUT(p,MBR16_DRVNUM,v) -#define MBR_PUTDRVNUM32(p,v) UBYTE_PUT(p,MBR32_DRVNUM,v) -#define MBR_PUTBOOTSIG16(p,v) UBYTE_PUT(p,MBR16_BOOTSIG,v) -#define MBR_PUTBOOTSIG32(p,v) UBYTE_PUT(p,MBR32_BOOTSIG,v) +#define MBR_PUTSECPERCLUS(p,v) UBYTE_PUT(p,MBR_SECPERCLUS,v) +#define MBR_PUTNUMFATS(p,v) UBYTE_PUT(p,MBR_NUMFATS,v) +#define MBR_PUTMEDIA(p,v) UBYTE_PUT(p,MBR_MEDIA,v) +#define MBR_PUTDRVNUM16(p,v) UBYTE_PUT(p,MBR16_DRVNUM,v) +#define MBR_PUTDRVNUM32(p,v) UBYTE_PUT(p,MBR32_DRVNUM,v) +#define MBR_PUTBOOTSIG16(p,v) UBYTE_PUT(p,MBR16_BOOTSIG,v) +#define MBR_PUTBOOTSIG32(p,v) UBYTE_PUT(p,MBR32_BOOTSIG,v) -#define FBR_PUTSECPERCLUS(p,v) UBYTE_PUT(p,FBR_SECPERCLUS,v) -#define FBR_PUTNUMFATS(p,v) UBYTE_PUT(p,FBR_NUMFATS,v) -#define FBR_PUTMEDIA(p,v) UBYTE_PUT(p,FBR_MEDIA,v) -#define FBR_PUTDRVNUM16(p,v) UBYTE_PUT(p,FBR16_DRVNUM,v) -#define FBR_PUTDRVNUM32(p,v) UBYTE_PUT(p,FBR32_DRVNUM,v) -#define FBR_PUTBOOTSIG16(p,v) UBYTE_PUT(p,FBR16_BOOTSIG,v) -#define FBR_PUTBOOTSIG32(p,v) UBYTE_PUT(p,FBR32_BOOTSIG,v) +#define FBR_PUTSECPERCLUS(p,v) UBYTE_PUT(p,FBR_SECPERCLUS,v) +#define FBR_PUTNUMFATS(p,v) UBYTE_PUT(p,FBR_NUMFATS,v) +#define FBR_PUTMEDIA(p,v) UBYTE_PUT(p,FBR_MEDIA,v) +#define FBR_PUTDRVNUM16(p,v) UBYTE_PUT(p,FBR16_DRVNUM,v) +#define FBR_PUTDRVNUM32(p,v) UBYTE_PUT(p,FBR32_DRVNUM,v) +#define FBR_PUTBOOTSIG16(p,v) UBYTE_PUT(p,FBR16_BOOTSIG,v) +#define FBR_PUTBOOTSIG32(p,v) UBYTE_PUT(p,FBR32_BOOTSIG,v) -#define PART_PUTTYPE(n,p,v) UBYTE_PUT(p,PART_ENTRY(n)+PART_TYPE,v) -#define PART1_PUTTYPE(p,v) UBYTE_PUT(p,PART_ENTRY1+PART_TYPE,v) -#define PART2_PUTTYPE(p,v) UBYTE_PUT(p,PART_ENTRY2+PART_TYPE,v) -#define PART3_PUTTYPE(p,v) UBYTE_PUT(p,PART_ENTRY3+PART_TYPE,v) -#define PART4_PUTTYPE(p,v) UBYTE_PUT(p,PART_ENTRY4+PART_TYPE,v) +#define PART_PUTTYPE(n,p,v) UBYTE_PUT(p,PART_ENTRY(n)+PART_TYPE,v) +#define PART1_PUTTYPE(p,v) UBYTE_PUT(p,PART_ENTRY1+PART_TYPE,v) +#define PART2_PUTTYPE(p,v) UBYTE_PUT(p,PART_ENTRY2+PART_TYPE,v) +#define PART3_PUTTYPE(p,v) UBYTE_PUT(p,PART_ENTRY3+PART_TYPE,v) +#define PART4_PUTTYPE(p,v) UBYTE_PUT(p,PART_ENTRY4+PART_TYPE,v) -#define DIR_PUTATTRIBUTES(p,v) UBYTE_PUT(p,DIR_ATTRIBUTES,v) -#define DIR_PUTNTRES(p,v) UBYTE_PUT(p,DIR_NTRES,v) -#define DIR_PUTCRTTIMETENTH(p,v) UBYTE_PUT(p,DIR_CRTTIMETENTH,v) +#define DIR_PUTATTRIBUTES(p,v) UBYTE_PUT(p,DIR_ATTRIBUTES,v) +#define DIR_PUTNTRES(p,v) UBYTE_PUT(p,DIR_NTRES,v) +#define DIR_PUTCRTTIMETENTH(p,v) UBYTE_PUT(p,DIR_CRTTIMETENTH,v) #ifdef CONFIG_FAT_LFN -# define LDIR_PUTSEQ(p,v) UBYTE_PUT(p,LDIR_SEQ,v) -# define LDIR_PUTATTRIBUTES(p,v) UBYTE_PUT(p,LDIR_ATTRIBUTES,v) -# define LDIR_PUTNTRES(p,v) UBYTE_PUT(p,LDIR_NTRES,v) -# define LDIR_PUTCHECKSUM(p,v) UBYTE_PUT(p,LDIR_CHECKSUM,v) +# define LDIR_PUTSEQ(p,v) UBYTE_PUT(p,LDIR_SEQ,v) +# define LDIR_PUTATTRIBUTES(p,v) UBYTE_PUT(p,LDIR_ATTRIBUTES,v) +# define LDIR_PUTNTRES(p,v) UBYTE_PUT(p,LDIR_NTRES,v) +# define LDIR_PUTCHECKSUM(p,v) UBYTE_PUT(p,LDIR_CHECKSUM,v) #endif /* For the all targets, unaligned values need to be accessed byte-by-byte. @@ -476,56 +476,56 @@ /* Unaligned multi-byte access macros */ -#define MBR_GETBYTESPERSEC(p) fat_getuint16(UBYTE_PTR(p,MBR_BYTESPERSEC)) -#define MBR_GETROOTENTCNT(p) fat_getuint16(UBYTE_PTR(p,MBR_ROOTENTCNT)) -#define MBR_GETTOTSEC16(p) fat_getuint16(UBYTE_PTR(p,MBR_TOTSEC16)) -#define MBR_GETVOLID16(p) fat_getuint32(UBYTE_PTR(p,MBR16_VOLID)) -#define MBR_GETVOLID32(p) fat_getuint32(UBYTE_PTR(p,MBR32_VOLID)) +#define MBR_GETBYTESPERSEC(p) fat_getuint16(UBYTE_PTR(p,MBR_BYTESPERSEC)) +#define MBR_GETROOTENTCNT(p) fat_getuint16(UBYTE_PTR(p,MBR_ROOTENTCNT)) +#define MBR_GETTOTSEC16(p) fat_getuint16(UBYTE_PTR(p,MBR_TOTSEC16)) +#define MBR_GETVOLID16(p) fat_getuint32(UBYTE_PTR(p,MBR16_VOLID)) +#define MBR_GETVOLID32(p) fat_getuint32(UBYTE_PTR(p,MBR32_VOLID)) -#define FBR_GETBYTESPERSEC(p) fat_getuint16(UBYTE_PTR(p,FBR_BYTESPERSEC)) -#define FBR_GETROOTENTCNT(p) fat_getuint16(UBYTE_PTR(p,FBR_ROOTENTCNT)) -#define FBR_GETTOTSEC16(p) fat_getuint16(UBYTE_PTR(p,FBR_TOTSEC16)) -#define FBR_GETVOLID16(p) fat_getuint32(UBYTE_PTR(p,FBR16_VOLID)) -#define FBR_GETVOLID32(p) fat_getuint32(UBYTE_PTR(p,FBR32_VOLID)) +#define FBR_GETBYTESPERSEC(p) fat_getuint16(UBYTE_PTR(p,FBR_BYTESPERSEC)) +#define FBR_GETROOTENTCNT(p) fat_getuint16(UBYTE_PTR(p,FBR_ROOTENTCNT)) +#define FBR_GETTOTSEC16(p) fat_getuint16(UBYTE_PTR(p,FBR_TOTSEC16)) +#define FBR_GETVOLID16(p) fat_getuint32(UBYTE_PTR(p,FBR16_VOLID)) +#define FBR_GETVOLID32(p) fat_getuint32(UBYTE_PTR(p,FBR32_VOLID)) -#define PART_GETSTARTSECTOR(n,p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY(n)+PART_STARTSECTOR)) -#define PART_GETSIZE(n,p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY(n)+PART_SIZE)) -#define PART1_GETSTARTSECTOR(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY1+PART_STARTSECTOR)) -#define PART1_GETSIZE(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY1+PART_SIZE)) -#define PART2_GETSTARTSECTOR(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY2+PART_STARTSECTOR)) -#define PART2_GETSIZE(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY2+PART_SIZE)) -#define PART3_GETSTARTSECTOR(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY3+PART_STARTSECTOR)) -#define PART3_GETSIZE(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY3+PART_SIZE)) -#define PART4_GETSTARTSECTOR(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY4+PART_STARTSECTOR)) -#define PART4_GETSIZE(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY4+PART_SIZE)) +#define PART_GETSTARTSECTOR(n,p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY(n)+PART_STARTSECTOR)) +#define PART_GETSIZE(n,p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY(n)+PART_SIZE)) +#define PART1_GETSTARTSECTOR(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY1+PART_STARTSECTOR)) +#define PART1_GETSIZE(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY1+PART_SIZE)) +#define PART2_GETSTARTSECTOR(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY2+PART_STARTSECTOR)) +#define PART2_GETSIZE(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY2+PART_SIZE)) +#define PART3_GETSTARTSECTOR(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY3+PART_STARTSECTOR)) +#define PART3_GETSIZE(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY3+PART_SIZE)) +#define PART4_GETSTARTSECTOR(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY4+PART_STARTSECTOR)) +#define PART4_GETSIZE(p) fat_getuint32(UBYTE_PTR(p,PART_ENTRY4+PART_SIZE)) -#define MBR_PUTBYTESPERSEC(p,v) fat_putuint16(UBYTE_PTR(p,MBR_BYTESPERSEC),v) -#define MBR_PUTROOTENTCNT(p,v) fat_putuint16(UBYTE_PTR(p,MBR_ROOTENTCNT),v) -#define MBR_PUTTOTSEC16(p,v) fat_putuint16(UBYTE_PTR(p,MBR_TOTSEC16),v) -#define MBR_PUTVOLID16(p,v) fat_putuint32(UBYTE_PTR(p,MBR16_VOLID),v) -#define MBR_PUTVOLID32(p,v) fat_putuint32(UBYTE_PTR(p,MBR32_VOLID),v) +#define MBR_PUTBYTESPERSEC(p,v) fat_putuint16(UBYTE_PTR(p,MBR_BYTESPERSEC),v) +#define MBR_PUTROOTENTCNT(p,v) fat_putuint16(UBYTE_PTR(p,MBR_ROOTENTCNT),v) +#define MBR_PUTTOTSEC16(p,v) fat_putuint16(UBYTE_PTR(p,MBR_TOTSEC16),v) +#define MBR_PUTVOLID16(p,v) fat_putuint32(UBYTE_PTR(p,MBR16_VOLID),v) +#define MBR_PUTVOLID32(p,v) fat_putuint32(UBYTE_PTR(p,MBR32_VOLID),v) -#define FBR_PUTBYTESPERSEC(p,v) fat_putuint16(UBYTE_PTR(p,FBR_BYTESPERSEC),v) -#define FBR_PUTROOTENTCNT(p,v) fat_putuint16(UBYTE_PTR(p,FBR_ROOTENTCNT),v) -#define FBR_PUTTOTSEC16(p,v) fat_putuint16(UBYTE_PTR(p,FBR_TOTSEC16),v) -#define FBR_PUTVOLID16(p,v) fat_putuint32(UBYTE_PTR(p,FBR16_VOLID),v) -#define FBR_PUTVOLID32(p,v) fat_putuint32(UBYTE_PTR(p,FBR32_VOLID),v) +#define FBR_PUTBYTESPERSEC(p,v) fat_putuint16(UBYTE_PTR(p,FBR_BYTESPERSEC),v) +#define FBR_PUTROOTENTCNT(p,v) fat_putuint16(UBYTE_PTR(p,FBR_ROOTENTCNT),v) +#define FBR_PUTTOTSEC16(p,v) fat_putuint16(UBYTE_PTR(p,FBR_TOTSEC16),v) +#define FBR_PUTVOLID16(p,v) fat_putuint32(UBYTE_PTR(p,FBR16_VOLID),v) +#define FBR_PUTVOLID32(p,v) fat_putuint32(UBYTE_PTR(p,FBR32_VOLID),v) -#define PART_PUTSTARTSECTOR(n,p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY(n)+PART_STARTSECTOR),v) -#define PART_PUTSIZE(n,p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY(n)+PART_SIZE),v) -#define PART1_PUTSTARTSECTOR(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY1+PART_STARTSECTOR),v) -#define PART1_PUTSIZE(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY1+PART_SIZE),v) -#define PART2_PUTSTARTSECTOR(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY2+PART_STARTSECTOR),v) -#define PART2_PUTSIZE(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY2+PART_SIZE),v) -#define PART3_PUTSTARTSECTOR(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY3+PART_STARTSECTOR),v) -#define PART3_PUTSIZE(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY3+PART_SIZE),v) -#define PART4_PUTSTARTSECTOR(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY4+PART_STARTSECTOR),v) -#define PART4_PUTSIZE(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY4+PART_SIZE),v) +#define PART_PUTSTARTSECTOR(n,p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY(n)+PART_STARTSECTOR),v) +#define PART_PUTSIZE(n,p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY(n)+PART_SIZE),v) +#define PART1_PUTSTARTSECTOR(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY1+PART_STARTSECTOR),v) +#define PART1_PUTSIZE(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY1+PART_SIZE),v) +#define PART2_PUTSTARTSECTOR(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY2+PART_STARTSECTOR),v) +#define PART2_PUTSIZE(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY2+PART_SIZE),v) +#define PART3_PUTSTARTSECTOR(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY3+PART_STARTSECTOR),v) +#define PART3_PUTSIZE(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY3+PART_SIZE),v) +#define PART4_PUTSTARTSECTOR(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY4+PART_STARTSECTOR),v) +#define PART4_PUTSIZE(p,v) fat_putuint32(UBYTE_PTR(p,PART_ENTRY4+PART_SIZE),v) #ifdef CONFIG_FAT_LFN -# define LDIR_PTRWCHAR1_5(p) UBYTE_PTR(p,LDIR_WCHAR1_5) -# define LDIR_PTRWCHAR6_11(p) UBYTE_PTR(p,LDIR_WCHAR6_11) -# define LDIR_PTRWCHAR12_13(p) UBYTE_PTR(p,LDIR_WCHAR12_13) +# define LDIR_PTRWCHAR1_5(p) UBYTE_PTR(p,LDIR_WCHAR1_5) +# define LDIR_PTRWCHAR6_11(p) UBYTE_PTR(p,LDIR_WCHAR6_11) +# define LDIR_PTRWCHAR12_13(p) UBYTE_PTR(p,LDIR_WCHAR12_13) #endif /* But for multi-byte values, the endian-ness of the target vs. the little @@ -539,143 +539,143 @@ * accessed byte-by-byte. */ -# define MBR_GETRESVDSECCOUNT(p) fat_getuint16(UBYTE_PTR(p,MBR_RESVDSECCOUNT)) -# define MBR_GETFATSZ16(p) fat_getuint16(UBYTE_PTR(p,MBR_FATSZ16)) -# define MBR_GETSECPERTRK(p) fat_getuint16(UBYTE_PTR(p,MBR_SECPERTRK)) -# define MBR_GETNUMHEADS(p) fat_getuint16(UBYTE_PTR(p,MBR_NUMHEADS)) -# define MBR_GETHIDSEC(p) fat_getuint32(UBYTE_PTR(p,MBR_HIDSEC)) -# define MBR_GETTOTSEC32(p) fat_getuint32(UBYTE_PTR(p,MBR_TOTSEC32)) -# define MBR_GETFATSZ32(p) fat_getuint32(UBYTE_PTR(p,MBR32_FATSZ32)) -# define MBR_GETEXTFLAGS(p) fat_getuint16(UBYTE_PTR(p,MBR32_EXTFLAGS)) -# define MBR_GETFSVER(p) fat_getuint16(UBYTE_PTR(p,MBR32_FSVER)) -# define MBR_GETROOTCLUS(p) fat_getuint32(UBYTE_PTR(p,MBR32_ROOTCLUS)) -# define MBR_GETFSINFO(p) fat_getuint16(UBYTE_PTR(p,MBR32_FSINFO)) -# define MBR_GETBKBOOTSEC(p) fat_getuint16(UBYTE_PTR(p,MBR32_BKBOOTSEC)) -# define MBR_GETSIGNATURE(p) fat_getuint16(UBYTE_PTR(p,MBR_SIGNATURE)) +# define MBR_GETRESVDSECCOUNT(p) fat_getuint16(UBYTE_PTR(p,MBR_RESVDSECCOUNT)) +# define MBR_GETFATSZ16(p) fat_getuint16(UBYTE_PTR(p,MBR_FATSZ16)) +# define MBR_GETSECPERTRK(p) fat_getuint16(UBYTE_PTR(p,MBR_SECPERTRK)) +# define MBR_GETNUMHEADS(p) fat_getuint16(UBYTE_PTR(p,MBR_NUMHEADS)) +# define MBR_GETHIDSEC(p) fat_getuint32(UBYTE_PTR(p,MBR_HIDSEC)) +# define MBR_GETTOTSEC32(p) fat_getuint32(UBYTE_PTR(p,MBR_TOTSEC32)) +# define MBR_GETFATSZ32(p) fat_getuint32(UBYTE_PTR(p,MBR32_FATSZ32)) +# define MBR_GETEXTFLAGS(p) fat_getuint16(UBYTE_PTR(p,MBR32_EXTFLAGS)) +# define MBR_GETFSVER(p) fat_getuint16(UBYTE_PTR(p,MBR32_FSVER)) +# define MBR_GETROOTCLUS(p) fat_getuint32(UBYTE_PTR(p,MBR32_ROOTCLUS)) +# define MBR_GETFSINFO(p) fat_getuint16(UBYTE_PTR(p,MBR32_FSINFO)) +# define MBR_GETBKBOOTSEC(p) fat_getuint16(UBYTE_PTR(p,MBR32_BKBOOTSEC)) +# define MBR_GETSIGNATURE(p) fat_getuint16(UBYTE_PTR(p,MBR_SIGNATURE)) -# define FBR_GETRESVDSECCOUNT(p) fat_getuint16(UBYTE_PTR(p,FBR_RESVDSECCOUNT)) -# define FBR_GETFATSZ16(p) fat_getuint16(UBYTE_PTR(p,FBR_FATSZ16)) -# define FBR_GETSECPERTRK(p) fat_getuint16(UBYTE_PTR(p,FBR_SECPERTRK)) -# define FBR_GETNUMHEADS(p) fat_getuint16(UBYTE_PTR(p,FBR_NUMHEADS)) -# define FBR_GETHIDSEC(p) fat_getuint32(UBYTE_PTR(p,FBR_HIDSEC)) -# define FBR_GETTOTSEC32(p) fat_getuint32(UBYTE_PTR(p,FBR_TOTSEC32)) -# define FBR_GETFATSZ32(p) fat_getuint32(UBYTE_PTR(p,FBR_FATSZ32)) -# define FBR_GETEXTFLAGS(p) fat_getuint16(UBYTE_PTR(p,FBR_EXTFLAGS)) -# define FBR_GETFSVER(p) fat_getuint16(UBYTE_PTR(p,FBR_FSVER)) -# define FBR_GETROOTCLUS(p) fat_getuint32(UBYTE_PTR(p,FBR_ROOTCLUS)) -# define FBR_GETFSINFO(p) fat_getuint16(UBYTE_PTR(p,FBR_FSINFO)) -# define FBR_GETBKBOOTSEC(p) fat_getuint16(UBYTE_PTR(p,FBR_BKBOOTSEC)) -# define FBR_GETSIGNATURE(p) fat_getuint16(UBYTE_PTR(p,FBR_SIGNATURE)) +# define FBR_GETRESVDSECCOUNT(p) fat_getuint16(UBYTE_PTR(p,FBR_RESVDSECCOUNT)) +# define FBR_GETFATSZ16(p) fat_getuint16(UBYTE_PTR(p,FBR_FATSZ16)) +# define FBR_GETSECPERTRK(p) fat_getuint16(UBYTE_PTR(p,FBR_SECPERTRK)) +# define FBR_GETNUMHEADS(p) fat_getuint16(UBYTE_PTR(p,FBR_NUMHEADS)) +# define FBR_GETHIDSEC(p) fat_getuint32(UBYTE_PTR(p,FBR_HIDSEC)) +# define FBR_GETTOTSEC32(p) fat_getuint32(UBYTE_PTR(p,FBR_TOTSEC32)) +# define FBR_GETFATSZ32(p) fat_getuint32(UBYTE_PTR(p,FBR_FATSZ32)) +# define FBR_GETEXTFLAGS(p) fat_getuint16(UBYTE_PTR(p,FBR_EXTFLAGS)) +# define FBR_GETFSVER(p) fat_getuint16(UBYTE_PTR(p,FBR_FSVER)) +# define FBR_GETROOTCLUS(p) fat_getuint32(UBYTE_PTR(p,FBR_ROOTCLUS)) +# define FBR_GETFSINFO(p) fat_getuint16(UBYTE_PTR(p,FBR_FSINFO)) +# define FBR_GETBKBOOTSEC(p) fat_getuint16(UBYTE_PTR(p,FBR_BKBOOTSEC)) +# define FBR_GETSIGNATURE(p) fat_getuint16(UBYTE_PTR(p,FBR_SIGNATURE)) -# define FSI_GETLEADSIG(p) fat_getuint32(UBYTE_PTR(p,FSI_LEADSIG)) -# define FSI_GETSTRUCTSIG(p) fat_getuint32(UBYTE_PTR(p,FSI_STRUCTSIG)) -# define FSI_GETFREECOUNT(p) fat_getuint32(UBYTE_PTR(p,FSI_FREECOUNT)) -# define FSI_GETNXTFREE(p) fat_getuint32(UBYTE_PTR(p,FSI_NXTFREE)) -# define FSI_GETTRAILSIG(p) fat_getuint32(UBYTE_PTR(p,FSI_TRAILSIG)) +# define FSI_GETLEADSIG(p) fat_getuint32(UBYTE_PTR(p,FSI_LEADSIG)) +# define FSI_GETSTRUCTSIG(p) fat_getuint32(UBYTE_PTR(p,FSI_STRUCTSIG)) +# define FSI_GETFREECOUNT(p) fat_getuint32(UBYTE_PTR(p,FSI_FREECOUNT)) +# define FSI_GETNXTFREE(p) fat_getuint32(UBYTE_PTR(p,FSI_NXTFREE)) +# define FSI_GETTRAILSIG(p) fat_getuint32(UBYTE_PTR(p,FSI_TRAILSIG)) -# define DIR_GETCRTIME(p) fat_getuint16(UBYTE_PTR(p,DIR_CRTIME)) -# define DIR_GETCRDATE(p) fat_getuint16(UBYTE_PTR(p,DIR_CRDATE)) -# define DIR_GETLASTACCDATE(p) fat_getuint16(UBYTE_PTR(p,DIR_LASTACCDATE)) -# define DIR_GETFSTCLUSTHI(p) fat_getuint16(UBYTE_PTR(p,DIR_FSTCLUSTHI)) -# define DIR_GETWRTTIME(p) fat_getuint16(UBYTE_PTR(p,DIR_WRTTIME)) -# define DIR_GETWRTDATE(p) fat_getuint16(UBYTE_PTR(p,DIR_WRTDATE)) -# define DIR_GETFSTCLUSTLO(p) fat_getuint16(UBYTE_PTR(p,DIR_FSTCLUSTLO)) -# define DIR_GETFILESIZE(p) fat_getuint32(UBYTE_PTR(p,DIR_FILESIZE)) +# define DIR_GETCRTIME(p) fat_getuint16(UBYTE_PTR(p,DIR_CRTIME)) +# define DIR_GETCRDATE(p) fat_getuint16(UBYTE_PTR(p,DIR_CRDATE)) +# define DIR_GETLASTACCDATE(p) fat_getuint16(UBYTE_PTR(p,DIR_LASTACCDATE)) +# define DIR_GETFSTCLUSTHI(p) fat_getuint16(UBYTE_PTR(p,DIR_FSTCLUSTHI)) +# define DIR_GETWRTTIME(p) fat_getuint16(UBYTE_PTR(p,DIR_WRTTIME)) +# define DIR_GETWRTDATE(p) fat_getuint16(UBYTE_PTR(p,DIR_WRTDATE)) +# define DIR_GETFSTCLUSTLO(p) fat_getuint16(UBYTE_PTR(p,DIR_FSTCLUSTLO)) +# define DIR_GETFILESIZE(p) fat_getuint32(UBYTE_PTR(p,DIR_FILESIZE)) # ifdef CONFIG_FAT_LFN -# define LDIR_GETWCHAR1(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR1_5)) -# define LDIR_GETWCHAR2(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+2)) -# define LDIR_GETWCHAR3(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+4)) -# define LDIR_GETWCHAR4(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+6)) -# define LDIR_GETWCHAR5(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+8)) -# define LDIR_GETWCHAR6(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR6_11)) -# define LDIR_GETWCHAR7(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+2)) -# define LDIR_GETWCHAR8(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+4)) -# define LDIR_GETWCHAR9(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+6)) -# define LDIR_GETWCHAR10(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+8)) -# define LDIR_GETWCHAR11(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+10)) -# define LDIR_GETWCHAR12(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR12_13)) -# define LDIR_GETWCHAR13(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR12_13+2)) -# define LDIR_GETFSTCLUSTLO(p) fat_getuint16(UBYTE_PTR(p,LDIR_FSTCLUSTLO)) -# endif +# define LDIR_GETWCHAR1(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR1_5)) +# define LDIR_GETWCHAR2(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+2)) +# define LDIR_GETWCHAR3(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+4)) +# define LDIR_GETWCHAR4(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+6)) +# define LDIR_GETWCHAR5(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+8)) +# define LDIR_GETWCHAR6(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR6_11)) +# define LDIR_GETWCHAR7(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+2)) +# define LDIR_GETWCHAR8(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+4)) +# define LDIR_GETWCHAR9(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+6)) +# define LDIR_GETWCHAR10(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+8)) +# define LDIR_GETWCHAR11(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+10)) +# define LDIR_GETWCHAR12(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR12_13)) +# define LDIR_GETWCHAR13(p) fat_getuint16(UBYTE_PTR(p,LDIR_WCHAR12_13+2)) +# define LDIR_GETFSTCLUSTLO(p) fat_getuint16(UBYTE_PTR(p,LDIR_FSTCLUSTLO)) +# endif -# define FSI_GETLEADSIG(p) fat_getuint32(UBYTE_PTR(p,FSI_LEADSIG)) -# define FSI_GETSTRUCTSIG(p) fat_getuint32(UBYTE_PTR(p,FSI_STRUCTSIG)) -# define FSI_GETFREECOUNT(p) fat_getuint32(UBYTE_PTR(p,FSI_FREECOUNT)) -# define FSI_GETNXTFREE(p) fat_getuint32(UBYTE_PTR(p,FSI_NXTFREE)) -# define FSI_GETTRAILSIG(p) fat_getuint32(UBYTE_PTR(p,FSI_TRAILSIG)) +# define FSI_GETLEADSIG(p) fat_getuint32(UBYTE_PTR(p,FSI_LEADSIG)) +# define FSI_GETSTRUCTSIG(p) fat_getuint32(UBYTE_PTR(p,FSI_STRUCTSIG)) +# define FSI_GETFREECOUNT(p) fat_getuint32(UBYTE_PTR(p,FSI_FREECOUNT)) +# define FSI_GETNXTFREE(p) fat_getuint32(UBYTE_PTR(p,FSI_NXTFREE)) +# define FSI_GETTRAILSIG(p) fat_getuint32(UBYTE_PTR(p,FSI_TRAILSIG)) -# define FAT_GETFAT16(p,i) fat_getuint16(UBYTE_PTR(p,i)) -# define FAT_GETFAT32(p,i) fat_getuint32(UBYTE_PTR(p,i)) +# define FAT_GETFAT16(p,i) fat_getuint16(UBYTE_PTR(p,i)) +# define FAT_GETFAT32(p,i) fat_getuint32(UBYTE_PTR(p,i)) -# define MBR_PUTRESVDSECCOUNT(p,v) fat_putuint16(UBYTE_PTR(p,MBR_RESVDSECCOUNT),v) -# define MBR_PUTFATSZ16(p,v) fat_putuint16(UBYTE_PTR(p,MBR_FATSZ16),v) -# define MBR_PUTSECPERTRK(p,v) fat_putuint16(UBYTE_PTR(p,MBR_SECPERTRK),v) -# define MBR_PUTNUMHEADS(p,v) fat_putuint16(UBYTE_PTR(p,MBR_NUMHEADS),v) -# define MBR_PUTHIDSEC(p,v) fat_putuint32(UBYTE_PTR(p,MBR_HIDSEC),v) -# define MBR_PUTTOTSEC32(p,v) fat_putuint32(UBYTE_PTR(p,MBR_TOTSEC32),v) -# define MBR_PUTFATSZ32(p,v) fat_putuint32(UBYTE_PTR(p,MBR32_FATSZ32),v) -# define MBR_PUTEXTFLAGS(p,v) fat_putuint16(UBYTE_PTR(p,MBR32_EXTFLAGS),v) -# define MBR_PUTFSVER(p,v) fat_putuint16(UBYTE_PTR(p,MBR32_FSVER),v) -# define MBR_PUTROOTCLUS(p,v) fat_putuint32(UBYTE_PTR(p,MBR32_ROOTCLUS),v) -# define MBR_PUTFSINFO(p,v) fat_putuint16(UBYTE_PTR(p,MBR32_FSINFO),v) -# define MBR_PUTBKBOOTSEC(p,v) fat_putuint16(UBYTE_PTR(p,MBR32_BKBOOTSEC),v) -# define MBR_PUTSIGNATURE(p,v) fat_putuint16(UBYTE_PTR(p,MBR_SIGNATURE),v) +# define MBR_PUTRESVDSECCOUNT(p,v) fat_putuint16(UBYTE_PTR(p,MBR_RESVDSECCOUNT),v) +# define MBR_PUTFATSZ16(p,v) fat_putuint16(UBYTE_PTR(p,MBR_FATSZ16),v) +# define MBR_PUTSECPERTRK(p,v) fat_putuint16(UBYTE_PTR(p,MBR_SECPERTRK),v) +# define MBR_PUTNUMHEADS(p,v) fat_putuint16(UBYTE_PTR(p,MBR_NUMHEADS),v) +# define MBR_PUTHIDSEC(p,v) fat_putuint32(UBYTE_PTR(p,MBR_HIDSEC),v) +# define MBR_PUTTOTSEC32(p,v) fat_putuint32(UBYTE_PTR(p,MBR_TOTSEC32),v) +# define MBR_PUTFATSZ32(p,v) fat_putuint32(UBYTE_PTR(p,MBR32_FATSZ32),v) +# define MBR_PUTEXTFLAGS(p,v) fat_putuint16(UBYTE_PTR(p,MBR32_EXTFLAGS),v) +# define MBR_PUTFSVER(p,v) fat_putuint16(UBYTE_PTR(p,MBR32_FSVER),v) +# define MBR_PUTROOTCLUS(p,v) fat_putuint32(UBYTE_PTR(p,MBR32_ROOTCLUS),v) +# define MBR_PUTFSINFO(p,v) fat_putuint16(UBYTE_PTR(p,MBR32_FSINFO),v) +# define MBR_PUTBKBOOTSEC(p,v) fat_putuint16(UBYTE_PTR(p,MBR32_BKBOOTSEC),v) +# define MBR_PUTSIGNATURE(p,v) fat_putuint16(UBYTE_PTR(p,MBR_SIGNATURE),v) -# define FBR_PUTRESVDSECCOUNT(p,v) fat_putuint16(UBYTE_PTR(p,FBR_RESVDSECCOUNT),v) -# define FBR_PUTFATSZ16(p,v) fat_putuint16(UBYTE_PTR(p,FBR_FATSZ16),v) -# define FBR_PUTSECPERTRK(p,v) fat_putuint16(UBYTE_PTR(p,FBR_SECPERTRK),v) -# define FBR_PUTNUMHEADS(p,v) fat_putuint16(UBYTE_PTR(p,FBR_NUMHEADS),v) -# define FBR_PUTHIDSEC(p,v) fat_putuint32(UBYTE_PTR(p,FBR_HIDSEC),v) -# define FBR_PUTTOTSEC32(p,v) fat_putuint32(UBYTE_PTR(p,FBR_TOTSEC32),v) -# define FBR_PUTFATSZ32(p,v) fat_putuint32(UBYTE_PTR(p,FBR_FATSZ32),v) -# define FBR_PUTEXTFLAGS(p,v) fat_putuint16(UBYTE_PTR(p,FBR_EXTFLAGS),v) -# define FBR_PUTFSVER(p,v) fat_putuint16(UBYTE_PTR(p,FBR_FSVER),v) -# define FBR_PUTROOTCLUS(p,v) fat_putuint32(UBYTE_PTR(p,FBR_ROOTCLUS),v) -# define FBR_PUTFSINFO(p,v) fat_putuint16(UBYTE_PTR(p,FBR_FSINFO),v) -# define FBR_PUTBKBOOTSEC(p,v) fat_putuint16(UBYTE_PTR(p,FBR_BKBOOTSEC),v) -# define FBR_PUTSIGNATURE(p,v) fat_putuint16(UBYTE_PTR(p,FBR_SIGNATURE),v) +# define FBR_PUTRESVDSECCOUNT(p,v) fat_putuint16(UBYTE_PTR(p,FBR_RESVDSECCOUNT),v) +# define FBR_PUTFATSZ16(p,v) fat_putuint16(UBYTE_PTR(p,FBR_FATSZ16),v) +# define FBR_PUTSECPERTRK(p,v) fat_putuint16(UBYTE_PTR(p,FBR_SECPERTRK),v) +# define FBR_PUTNUMHEADS(p,v) fat_putuint16(UBYTE_PTR(p,FBR_NUMHEADS),v) +# define FBR_PUTHIDSEC(p,v) fat_putuint32(UBYTE_PTR(p,FBR_HIDSEC),v) +# define FBR_PUTTOTSEC32(p,v) fat_putuint32(UBYTE_PTR(p,FBR_TOTSEC32),v) +# define FBR_PUTFATSZ32(p,v) fat_putuint32(UBYTE_PTR(p,FBR_FATSZ32),v) +# define FBR_PUTEXTFLAGS(p,v) fat_putuint16(UBYTE_PTR(p,FBR_EXTFLAGS),v) +# define FBR_PUTFSVER(p,v) fat_putuint16(UBYTE_PTR(p,FBR_FSVER),v) +# define FBR_PUTROOTCLUS(p,v) fat_putuint32(UBYTE_PTR(p,FBR_ROOTCLUS),v) +# define FBR_PUTFSINFO(p,v) fat_putuint16(UBYTE_PTR(p,FBR_FSINFO),v) +# define FBR_PUTBKBOOTSEC(p,v) fat_putuint16(UBYTE_PTR(p,FBR_BKBOOTSEC),v) +# define FBR_PUTSIGNATURE(p,v) fat_putuint16(UBYTE_PTR(p,FBR_SIGNATURE),v) -# define FSI_PUTLEADSIG(p,v) fat_putuint32(UBYTE_PTR(p,FSI_LEADSIG),v) -# define FSI_PUTSTRUCTSIG(p,v) fat_putuint32(UBYTE_PTR(p,FSI_STRUCTSIG),v) -# define FSI_PUTFREECOUNT(p,v) fat_putuint32(UBYTE_PTR(p,FSI_FREECOUNT),v) -# define FSI_PUTNXTFREE(p,v) fat_putuint32(UBYTE_PTR(p,FSI_NXTFREE),v) -# define FSI_PUTTRAILSIG(p,v) fat_putuint32(UBYTE_PTR(p,FSI_TRAILSIG),v) +# define FSI_PUTLEADSIG(p,v) fat_putuint32(UBYTE_PTR(p,FSI_LEADSIG),v) +# define FSI_PUTSTRUCTSIG(p,v) fat_putuint32(UBYTE_PTR(p,FSI_STRUCTSIG),v) +# define FSI_PUTFREECOUNT(p,v) fat_putuint32(UBYTE_PTR(p,FSI_FREECOUNT),v) +# define FSI_PUTNXTFREE(p,v) fat_putuint32(UBYTE_PTR(p,FSI_NXTFREE),v) +# define FSI_PUTTRAILSIG(p,v) fat_putuint32(UBYTE_PTR(p,FSI_TRAILSIG),v) -# define DIR_PUTCRTIME(p,v) fat_putuint16(UBYTE_PTR(p,DIR_CRTIME),v) -# define DIR_PUTCRDATE(p,v) fat_putuint16(UBYTE_PTR(p,DIR_CRDATE),v) -# define DIR_PUTLASTACCDATE(p,v) fat_putuint16(UBYTE_PTR(p,DIR_LASTACCDATE),v) -# define DIR_PUTFSTCLUSTHI(p,v) fat_putuint16(UBYTE_PTR(p,DIR_FSTCLUSTHI),v) -# define DIR_PUTWRTTIME(p,v) fat_putuint16(UBYTE_PTR(p,DIR_WRTTIME),v) -# define DIR_PUTWRTDATE(p,v) fat_putuint16(UBYTE_PTR(p,DIR_WRTDATE),v) -# define DIR_PUTFSTCLUSTLO(p,v) fat_putuint16(UBYTE_PTR(p,DIR_FSTCLUSTLO),v) -# define DIR_PUTFILESIZE(p,v) fat_putuint32(UBYTE_PTR(p,DIR_FILESIZE),v) +# define DIR_PUTCRTIME(p,v) fat_putuint16(UBYTE_PTR(p,DIR_CRTIME),v) +# define DIR_PUTCRDATE(p,v) fat_putuint16(UBYTE_PTR(p,DIR_CRDATE),v) +# define DIR_PUTLASTACCDATE(p,v) fat_putuint16(UBYTE_PTR(p,DIR_LASTACCDATE),v) +# define DIR_PUTFSTCLUSTHI(p,v) fat_putuint16(UBYTE_PTR(p,DIR_FSTCLUSTHI),v) +# define DIR_PUTWRTTIME(p,v) fat_putuint16(UBYTE_PTR(p,DIR_WRTTIME),v) +# define DIR_PUTWRTDATE(p,v) fat_putuint16(UBYTE_PTR(p,DIR_WRTDATE),v) +# define DIR_PUTFSTCLUSTLO(p,v) fat_putuint16(UBYTE_PTR(p,DIR_FSTCLUSTLO),v) +# define DIR_PUTFILESIZE(p,v) fat_putuint32(UBYTE_PTR(p,DIR_FILESIZE),v) # ifdef CONFIG_FAT_LFN -# define LDIR_PUTWCHAR1(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR1_5),v) -# define LDIR_PUTWCHAR2(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+2),v) -# define LDIR_PUTWCHAR3(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+4),v) -# define LDIR_PUTWCHAR4(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+6),v) -# define LDIR_PUTWCHAR5(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+8),v) -# define LDIR_PUTWCHAR6(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR6_11),v) -# define LDIR_PUTWCHAR7(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+2),v) -# define LDIR_PUTWCHAR8(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+4),v) -# define LDIR_PUTWCHAR9(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+6),v) -# define LDIR_PUTWCHAR10(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+8),v) -# define LDIR_PUTWCHAR11(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+10),v) -# define LDIR_PUTWCHAR12(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR12_13),v) -# define LDIR_PUTWCHAR13(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR12_13+2),v) -# define LDIR_PUTFSTCLUSTLO(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_FSTCLUSTLO),v) -# endif +# define LDIR_PUTWCHAR1(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR1_5),v) +# define LDIR_PUTWCHAR2(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+2),v) +# define LDIR_PUTWCHAR3(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+4),v) +# define LDIR_PUTWCHAR4(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+6),v) +# define LDIR_PUTWCHAR5(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR1_5+8),v) +# define LDIR_PUTWCHAR6(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR6_11),v) +# define LDIR_PUTWCHAR7(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+2),v) +# define LDIR_PUTWCHAR8(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+4),v) +# define LDIR_PUTWCHAR9(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+6),v) +# define LDIR_PUTWCHAR10(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+8),v) +# define LDIR_PUTWCHAR11(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR6_11+10),v) +# define LDIR_PUTWCHAR12(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR12_13),v) +# define LDIR_PUTWCHAR13(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_WCHAR12_13+2),v) +# define LDIR_PUTFSTCLUSTLO(p,v) fat_putuint16(UBYTE_PTR(p,LDIR_FSTCLUSTLO),v) +# endif -# define FSI_PUTLEADSIG(p,v) fat_putuint32(UBYTE_PTR(p,FSI_LEADSIG),v) -# define FSI_PUTSTRUCTSIG(p,v) fat_putuint32(UBYTE_PTR(p,FSI_STRUCTSIG),v) -# define FSI_PUTFREECOUNT(p,v) fat_putuint32(UBYTE_PTR(p,FSI_FREECOUNT),v) -# define FSI_PUTNXTFREE(p,v) fat_putuint32(UBYTE_PTR(p,FSI_NXTFREE),v) -# define FSI_PUTTRAILSIG(p,v) fat_putuint32(UBYTE_PTR(p,FSI_TRAILSIG),v) +# define FSI_PUTLEADSIG(p,v) fat_putuint32(UBYTE_PTR(p,FSI_LEADSIG),v) +# define FSI_PUTSTRUCTSIG(p,v) fat_putuint32(UBYTE_PTR(p,FSI_STRUCTSIG),v) +# define FSI_PUTFREECOUNT(p,v) fat_putuint32(UBYTE_PTR(p,FSI_FREECOUNT),v) +# define FSI_PUTNXTFREE(p,v) fat_putuint32(UBYTE_PTR(p,FSI_NXTFREE),v) +# define FSI_PUTTRAILSIG(p,v) fat_putuint32(UBYTE_PTR(p,FSI_TRAILSIG),v) -# define FAT_PUTFAT16(p,i,v) fat_putuint16(UBYTE_PTR(p,i),v) -# define FAT_PUTFAT32(p,i,v) fat_putuint32(UBYTE_PTR(p,i),v) +# define FAT_PUTFAT16(p,i,v) fat_putuint16(UBYTE_PTR(p,i),v) +# define FAT_PUTFAT32(p,i,v) fat_putuint32(UBYTE_PTR(p,i),v) #else @@ -683,142 +683,142 @@ * to aligned multibyte values. */ -# define MBR_GETRESVDSECCOUNT(p) UINT16_VAL(p,MBR_RESVDSECCOUNT) -# define MBR_GETFATSZ16(p) UINT16_VAL(p,MBR_FATSZ16) -# define MBR_GETSECPERTRK(p) UINT16_VAL(p,MBR_SECPERTRK) -# define MBR_GETNUMHEADS(p) UINT16_VAL(p,MBR_NUMHEADS) -# define MBR_GETHIDSEC(p) UINT32_VAL(p,MBR_HIDSEC) -# define MBR_GETTOTSEC32(p) UINT32_VAL(p,MBR_TOTSEC32) -# define MBR_GETFATSZ32(p) UINT32_VAL(p,MBR32_FATSZ32) -# define MBR_GETEXTFLAGS(p) UINT16_VAL(p,MBR32_EXTFLAGS) -# define MBR_GETFSVER(p) UINT16_VAL(p,MBR32_FSVER) -# define MBR_GETROOTCLUS(p) UINT32_VAL(p,MBR32_ROOTCLUS) -# define MBR_GETFSINFO(p) UINT16_VAL(p,MBR32_FSINFO) -# define MBR_GETBKBOOTSEC(p) UINT16_VAL(p,MBR32_BKBOOTSEC) -# define MBR_GETSIGNATURE(p) UINT16_VAL(p,MBR_SIGNATURE) +# define MBR_GETRESVDSECCOUNT(p) UINT16_VAL(p,MBR_RESVDSECCOUNT) +# define MBR_GETFATSZ16(p) UINT16_VAL(p,MBR_FATSZ16) +# define MBR_GETSECPERTRK(p) UINT16_VAL(p,MBR_SECPERTRK) +# define MBR_GETNUMHEADS(p) UINT16_VAL(p,MBR_NUMHEADS) +# define MBR_GETHIDSEC(p) UINT32_VAL(p,MBR_HIDSEC) +# define MBR_GETTOTSEC32(p) UINT32_VAL(p,MBR_TOTSEC32) +# define MBR_GETFATSZ32(p) UINT32_VAL(p,MBR32_FATSZ32) +# define MBR_GETEXTFLAGS(p) UINT16_VAL(p,MBR32_EXTFLAGS) +# define MBR_GETFSVER(p) UINT16_VAL(p,MBR32_FSVER) +# define MBR_GETROOTCLUS(p) UINT32_VAL(p,MBR32_ROOTCLUS) +# define MBR_GETFSINFO(p) UINT16_VAL(p,MBR32_FSINFO) +# define MBR_GETBKBOOTSEC(p) UINT16_VAL(p,MBR32_BKBOOTSEC) +# define MBR_GETSIGNATURE(p) UINT16_VAL(p,MBR_SIGNATURE) -# define FBR_GETRESVDSECCOUNT(p) UINT16_VAL(p,FBR_RESVDSECCOUNT) -# define FBR_GETFATSZ16(p) UINT16_VAL(p,FBR_FATSZ16) -# define FBR_GETSECPERTRK(p) UINT16_VAL(p,FBR_SECPERTRK) -# define FBR_GETNUMHEADS(p) UINT16_VAL(p,FBR_NUMHEADS) -# define FBR_GETHIDSEC(p) UINT32_VAL(p,FBR_HIDSEC) -# define FBR_GETTOTSEC32(p) UINT32_VAL(p,FBR_TOTSEC32) -# define FBR_GETFATSZ32(p) UINT32_VAL(p,FBR_FATSZ32) -# define FBR_GETEXTFLAGS(p) UINT16_VAL(p,FBR_EXTFLAGS) -# define FBR_GETFSVER(p) UINT16_VAL(p,FBR_FSVER) -# define FBR_GETROOTCLUS(p) UINT32_VAL(p,FBR_ROOTCLUS) -# define FBR_GETFSINFO(p) UINT16_VAL(p,FBR_FSINFO) -# define FBR_GETBKBOOTSEC(p) UINT16_VAL(p,FBR_BKBOOTSEC) -# define FBR_GETSIGNATURE(p) UINT16_VAL(p,FBR_SIGNATURE) +# define FBR_GETRESVDSECCOUNT(p) UINT16_VAL(p,FBR_RESVDSECCOUNT) +# define FBR_GETFATSZ16(p) UINT16_VAL(p,FBR_FATSZ16) +# define FBR_GETSECPERTRK(p) UINT16_VAL(p,FBR_SECPERTRK) +# define FBR_GETNUMHEADS(p) UINT16_VAL(p,FBR_NUMHEADS) +# define FBR_GETHIDSEC(p) UINT32_VAL(p,FBR_HIDSEC) +# define FBR_GETTOTSEC32(p) UINT32_VAL(p,FBR_TOTSEC32) +# define FBR_GETFATSZ32(p) UINT32_VAL(p,FBR_FATSZ32) +# define FBR_GETEXTFLAGS(p) UINT16_VAL(p,FBR_EXTFLAGS) +# define FBR_GETFSVER(p) UINT16_VAL(p,FBR_FSVER) +# define FBR_GETROOTCLUS(p) UINT32_VAL(p,FBR_ROOTCLUS) +# define FBR_GETFSINFO(p) UINT16_VAL(p,FBR_FSINFO) +# define FBR_GETBKBOOTSEC(p) UINT16_VAL(p,FBR_BKBOOTSEC) +# define FBR_GETSIGNATURE(p) UINT16_VAL(p,FBR_SIGNATURE) -# define FSI_GETLEADSIG(p) UINT32_VAL(p,FSI_LEADSIG) -# define FSI_GETSTRUCTSIG(p) UINT32_VAL(p,FSI_STRUCTSIG) -# define FSI_GETFREECOUNT(p) UINT32_VAL(p,FSI_FREECOUNT) -# define FSI_GETNXTFREE(p) UINT32_VAL(p,FSI_NXTFREE) -# define FSI_GETTRAILSIG(p) UINT32_VAL(p,FSI_TRAILSIG) +# define FSI_GETLEADSIG(p) UINT32_VAL(p,FSI_LEADSIG) +# define FSI_GETSTRUCTSIG(p) UINT32_VAL(p,FSI_STRUCTSIG) +# define FSI_GETFREECOUNT(p) UINT32_VAL(p,FSI_FREECOUNT) +# define FSI_GETNXTFREE(p) UINT32_VAL(p,FSI_NXTFREE) +# define FSI_GETTRAILSIG(p) UINT32_VAL(p,FSI_TRAILSIG) -# define DIR_GETCRTIME(p) UINT16_VAL(p,DIR_CRTIME) -# define DIR_GETCRDATE(p) UINT16_VAL(p,DIR_CRDATE) -# define DIR_GETLASTACCDATE(p) UINT16_VAL(p,DIR_LASTACCDATE) -# define DIR_GETFSTCLUSTHI(p) UINT16_VAL(p,DIR_FSTCLUSTHI) -# define DIR_GETWRTTIME(p) UINT16_VAL(p,DIR_WRTTIME) -# define DIR_GETWRTDATE(p) UINT16_VAL(p,DIR_WRTDATE) -# define DIR_GETFSTCLUSTLO(p) UINT16_VAL(p,DIR_FSTCLUSTLO) -# define DIR_GETFILESIZE(p) UINT32_VAL(p,DIR_FILESIZE) +# define DIR_GETCRTIME(p) UINT16_VAL(p,DIR_CRTIME) +# define DIR_GETCRDATE(p) UINT16_VAL(p,DIR_CRDATE) +# define DIR_GETLASTACCDATE(p) UINT16_VAL(p,DIR_LASTACCDATE) +# define DIR_GETFSTCLUSTHI(p) UINT16_VAL(p,DIR_FSTCLUSTHI) +# define DIR_GETWRTTIME(p) UINT16_VAL(p,DIR_WRTTIME) +# define DIR_GETWRTDATE(p) UINT16_VAL(p,DIR_WRTDATE) +# define DIR_GETFSTCLUSTLO(p) UINT16_VAL(p,DIR_FSTCLUSTLO) +# define DIR_GETFILESIZE(p) UINT32_VAL(p,DIR_FILESIZE) # ifdef CONFIG_FAT_LFN -# define LDIR_GETWCHAR1(p) UINT16_VAL(p,LDIR_WCHAR1_5) -# define LDIR_GETWCHAR2(p) UINT16_VAL(p,LDIR_WCHAR1_5+2) -# define LDIR_GETWCHAR3(p) UINT16_VAL(p,LDIR_WCHAR1_5+4) -# define LDIR_GETWCHAR4(p) UINT16_VAL(p,LDIR_WCHAR1_5+6) -# define LDIR_GETWCHAR5(p) UINT16_VAL(p,LDIR_WCHAR1_5+8) -# define LDIR_GETWCHAR6(p) UINT16_VAL(p,LDIR_WCHAR6_11) -# define LDIR_GETWCHAR7(p) UINT16_VAL(p,LDIR_WCHAR6_11+2) -# define LDIR_GETWCHAR8(p) UINT16_VAL(p,LDIR_WCHAR6_11+4) -# define LDIR_GETWCHAR9(p) UINT16_VAL(p,LDIR_WCHAR6_11+6) -# define LDIR_GETWCHAR10(p) UINT16_VAL(p,LDIR_WCHAR6_11+8) -# define LDIR_GETWCHAR11(p) UINT16_VAL(p,LDIR_WCHAR6_11+10) -# define LDIR_GETWCHAR12(p) UINT16_VAL(p,LDIR_WCHAR12_13) -# define LDIR_GETWCHAR13(p) UINT16_VAL(p,LDIR_WCHAR12_13+2) -# endif +# define LDIR_GETWCHAR1(p) UINT16_VAL(p,LDIR_WCHAR1_5) +# define LDIR_GETWCHAR2(p) UINT16_VAL(p,LDIR_WCHAR1_5+2) +# define LDIR_GETWCHAR3(p) UINT16_VAL(p,LDIR_WCHAR1_5+4) +# define LDIR_GETWCHAR4(p) UINT16_VAL(p,LDIR_WCHAR1_5+6) +# define LDIR_GETWCHAR5(p) UINT16_VAL(p,LDIR_WCHAR1_5+8) +# define LDIR_GETWCHAR6(p) UINT16_VAL(p,LDIR_WCHAR6_11) +# define LDIR_GETWCHAR7(p) UINT16_VAL(p,LDIR_WCHAR6_11+2) +# define LDIR_GETWCHAR8(p) UINT16_VAL(p,LDIR_WCHAR6_11+4) +# define LDIR_GETWCHAR9(p) UINT16_VAL(p,LDIR_WCHAR6_11+6) +# define LDIR_GETWCHAR10(p) UINT16_VAL(p,LDIR_WCHAR6_11+8) +# define LDIR_GETWCHAR11(p) UINT16_VAL(p,LDIR_WCHAR6_11+10) +# define LDIR_GETWCHAR12(p) UINT16_VAL(p,LDIR_WCHAR12_13) +# define LDIR_GETWCHAR13(p) UINT16_VAL(p,LDIR_WCHAR12_13+2) +# endif -# define FSI_GETLEADSIG(p) UINT32_VAL(p,FSI_LEADSIG) -# define FSI_GETSTRUCTSIG(p) UINT32_VAL(p,FSI_STRUCTSIG) -# define FSI_GETFREECOUNT(p) UINT32_VAL(p,FSI_FREECOUNT) -# define FSI_GETNXTFREE(p) UINT32_VAL(p,FSI_NXTFREE) -# define FSI_GETTRAILSIG(p) UINT32_VAL(p,FSI_TRAILSIG) +# define FSI_GETLEADSIG(p) UINT32_VAL(p,FSI_LEADSIG) +# define FSI_GETSTRUCTSIG(p) UINT32_VAL(p,FSI_STRUCTSIG) +# define FSI_GETFREECOUNT(p) UINT32_VAL(p,FSI_FREECOUNT) +# define FSI_GETNXTFREE(p) UINT32_VAL(p,FSI_NXTFREE) +# define FSI_GETTRAILSIG(p) UINT32_VAL(p,FSI_TRAILSIG) -# define FAT_GETFAT16(p,i) UINT16_VAL(p,i) -# define FAT_GETFAT32(p,i) UINT32_VAL(p,i) +# define FAT_GETFAT16(p,i) UINT16_VAL(p,i) +# define FAT_GETFAT32(p,i) UINT32_VAL(p,i) -# define MBR_PUTRESVDSECCOUNT(p,v) UINT16_PUT(p,MBR_RESVDSECCOUNT,v) -# define MBR_PUTFATSZ16(p,v) UINT16_PUT(p,MBR_FATSZ16,v) -# define MBR_PUTSECPERTRK(p,v) UINT16_PUT(p,MBR_SECPERTRK,v) -# define MBR_PUTNUMHEADS(p,v) UINT16_PUT(p,MBR_NUMHEADS,v) -# define MBR_PUTHIDSEC(p,v) UINT32_PUT(p,MBR_HIDSEC,v) -# define MBR_PUTTOTSEC32(p,v) UINT32_PUT(p,MBR_TOTSEC32,v) -# define MBR_PUTFATSZ32(p,v) UINT32_PUT(p,MBR32_FATSZ32,v) -# define MBR_PUTEXTFLAGS(p,v) UINT16_PUT(p,MBR32_EXTFLAGS,v) -# define MBR_PUTFSVER(p,v) UINT16_PUT(p,MBR32_FSVER,v) -# define MBR_PUTROOTCLUS(p,v) UINT32_PUT(p,MBR32_ROOTCLUS,v) -# define MBR_PUTFSINFO(p,v) UINT16_PUT(p,MBR32_FSINFO,v) -# define MBR_PUTBKBOOTSEC(p,v) UINT16_PUT(p,MBR32_BKBOOTSEC,v) -# define MBR_PUTSIGNATURE(p,v) UINT16_PUT(p,MBR_SIGNATURE,v) +# define MBR_PUTRESVDSECCOUNT(p,v) UINT16_PUT(p,MBR_RESVDSECCOUNT,v) +# define MBR_PUTFATSZ16(p,v) UINT16_PUT(p,MBR_FATSZ16,v) +# define MBR_PUTSECPERTRK(p,v) UINT16_PUT(p,MBR_SECPERTRK,v) +# define MBR_PUTNUMHEADS(p,v) UINT16_PUT(p,MBR_NUMHEADS,v) +# define MBR_PUTHIDSEC(p,v) UINT32_PUT(p,MBR_HIDSEC,v) +# define MBR_PUTTOTSEC32(p,v) UINT32_PUT(p,MBR_TOTSEC32,v) +# define MBR_PUTFATSZ32(p,v) UINT32_PUT(p,MBR32_FATSZ32,v) +# define MBR_PUTEXTFLAGS(p,v) UINT16_PUT(p,MBR32_EXTFLAGS,v) +# define MBR_PUTFSVER(p,v) UINT16_PUT(p,MBR32_FSVER,v) +# define MBR_PUTROOTCLUS(p,v) UINT32_PUT(p,MBR32_ROOTCLUS,v) +# define MBR_PUTFSINFO(p,v) UINT16_PUT(p,MBR32_FSINFO,v) +# define MBR_PUTBKBOOTSEC(p,v) UINT16_PUT(p,MBR32_BKBOOTSEC,v) +# define MBR_PUTSIGNATURE(p,v) UINT16_PUT(p,MBR_SIGNATURE,v) -# define FBR_PUTRESVDSECCOUNT(p,v) UINT16_PUT(p,FBR_RESVDSECCOUNT,v) -# define FBR_PUTFATSZ16(p,v) UINT16_PUT(p,FBR_FATSZ16,v) -# define FBR_PUTSECPERTRK(p,v) UINT16_PUT(p,FBR_SECPERTRK,v) -# define FBR_PUTNUMHEADS(p,v) UINT16_PUT(p,FBR_NUMHEADS,v) -# define FBR_PUTHIDSEC(p,v) UINT32_PUT(p,FBR_HIDSEC,v) -# define FBR_PUTTOTSEC32(p,v) UINT32_PUT(p,FBR_TOTSEC32,v) -# define FBR_PUTFATSZ32(p,v) UINT32_PUT(p,FBR_FATSZ32,v) -# define FBR_PUTEXTFLAGS(p,v) UINT16_PUT(p,FBR_EXTFLAGS,v) -# define FBR_PUTFSVER(p,v) UINT16_PUT(p,FBR_FSVER,v) -# define FBR_PUTROOTCLUS(p,v) UINT32_PUT(p,FBR_ROOTCLUS,v) -# define FBR_PUTFSINFO(p,v) UINT16_PUT(p,FBR_FSINFO,v) -# define FBR_PUTBKBOOTSEC(p,v) UINT16_PUT(p,FBR_BKBOOTSEC,v) -# define FBR_PUTSIGNATURE(p,v) UINT16_PUT(p,FBR_SIGNATURE,v) +# define FBR_PUTRESVDSECCOUNT(p,v) UINT16_PUT(p,FBR_RESVDSECCOUNT,v) +# define FBR_PUTFATSZ16(p,v) UINT16_PUT(p,FBR_FATSZ16,v) +# define FBR_PUTSECPERTRK(p,v) UINT16_PUT(p,FBR_SECPERTRK,v) +# define FBR_PUTNUMHEADS(p,v) UINT16_PUT(p,FBR_NUMHEADS,v) +# define FBR_PUTHIDSEC(p,v) UINT32_PUT(p,FBR_HIDSEC,v) +# define FBR_PUTTOTSEC32(p,v) UINT32_PUT(p,FBR_TOTSEC32,v) +# define FBR_PUTFATSZ32(p,v) UINT32_PUT(p,FBR_FATSZ32,v) +# define FBR_PUTEXTFLAGS(p,v) UINT16_PUT(p,FBR_EXTFLAGS,v) +# define FBR_PUTFSVER(p,v) UINT16_PUT(p,FBR_FSVER,v) +# define FBR_PUTROOTCLUS(p,v) UINT32_PUT(p,FBR_ROOTCLUS,v) +# define FBR_PUTFSINFO(p,v) UINT16_PUT(p,FBR_FSINFO,v) +# define FBR_PUTBKBOOTSEC(p,v) UINT16_PUT(p,FBR_BKBOOTSEC,v) +# define FBR_PUTSIGNATURE(p,v) UINT16_PUT(p,FBR_SIGNATURE,v) -# define FSI_PUTLEADSIG(p,v) UINT32_PUT(p,FSI_LEADSIG,v) -# define FSI_PUTSTRUCTSIG(p,v) UINT32_PUT(p,FSI_STRUCTSIG,v) -# define FSI_PUTFREECOUNT(p,v) UINT32_PUT(p,FSI_FREECOUNT,v) -# define FSI_PUTNXTFREE(p,v) UINT32_PUT(p,FSI_NXTFREE,v) -# define FSI_PUTTRAILSIG(p,v) UINT32_PUT(p,FSI_TRAILSIG,v) +# define FSI_PUTLEADSIG(p,v) UINT32_PUT(p,FSI_LEADSIG,v) +# define FSI_PUTSTRUCTSIG(p,v) UINT32_PUT(p,FSI_STRUCTSIG,v) +# define FSI_PUTFREECOUNT(p,v) UINT32_PUT(p,FSI_FREECOUNT,v) +# define FSI_PUTNXTFREE(p,v) UINT32_PUT(p,FSI_NXTFREE,v) +# define FSI_PUTTRAILSIG(p,v) UINT32_PUT(p,FSI_TRAILSIG,v) -# define DIR_PUTCRTIME(p,v) UINT16_PUT(p,DIR_CRTIME,v) -# define DIR_PUTCRDATE(p,v) UINT16_PUT(p,DIR_CRDATE,v) -# define DIR_PUTLASTACCDATE(p,v) UINT16_PUT(p,DIR_LASTACCDATE,v) -# define DIR_PUTFSTCLUSTHI(p,v) UINT16_PUT(p,DIR_FSTCLUSTHI,v) -# define DIR_PUTWRTTIME(p,v) UINT16_PUT(p,DIR_WRTTIME,v) -# define DIR_PUTWRTDATE(p,v) UINT16_PUT(p,DIR_WRTDATE,v) -# define DIR_PUTFSTCLUSTLO(p,v) UINT16_PUT(p,DIR_FSTCLUSTLO,v) -# define DIR_PUTFILESIZE(p,v) UINT32_PUT(p,DIR_FILESIZE,v) +# define DIR_PUTCRTIME(p,v) UINT16_PUT(p,DIR_CRTIME,v) +# define DIR_PUTCRDATE(p,v) UINT16_PUT(p,DIR_CRDATE,v) +# define DIR_PUTLASTACCDATE(p,v) UINT16_PUT(p,DIR_LASTACCDATE,v) +# define DIR_PUTFSTCLUSTHI(p,v) UINT16_PUT(p,DIR_FSTCLUSTHI,v) +# define DIR_PUTWRTTIME(p,v) UINT16_PUT(p,DIR_WRTTIME,v) +# define DIR_PUTWRTDATE(p,v) UINT16_PUT(p,DIR_WRTDATE,v) +# define DIR_PUTFSTCLUSTLO(p,v) UINT16_PUT(p,DIR_FSTCLUSTLO,v) +# define DIR_PUTFILESIZE(p,v) UINT32_PUT(p,DIR_FILESIZE,v) # ifdef CONFIG_FAT_LFN -# define LDIR_PUTWCHAR1(p,v) UINT16_PUT(p,LDIR_WCHAR1_5,v) -# define LDIR_PUTWCHAR2(p,v) UINT16_PUT(p,LDIR_WCHAR1_5+2,v) -# define LDIR_PUTWCHAR3(p,v) UINT16_PUT(p,LDIR_WCHAR1_5+4,v) -# define LDIR_PUTWCHAR4(p,v) UINT16_PUT(p,LDIR_WCHAR1_5+6,v) -# define LDIR_PUTWCHAR5(p,v) UINT16_PUT(p,LDIR_WCHAR1_5+8,v) -# define LDIR_PUTWCHAR6(p,v) UINT16_PUT(p,LDIR_WCHAR6_11,v) -# define LDIR_PUTWCHAR7(p,v) UINT16_PUT(p,LDIR_WCHAR6_11+2,v) -# define LDIR_PUTWCHAR8(p,v) UINT16_PUT(p,LDIR_WCHAR6_11+4,v) -# define LDIR_PUTWCHAR9(p,v) UINT16_PUT(p,LDIR_WCHAR6_11+6,v) -# define LDIR_PUTWCHAR10(p,v) UINT16_PUT(p,LDIR_WCHAR6_11+8,v) -# define LDIR_PUTWCHAR11(p,v) UINT16_PUT(p,LDIR_WCHAR6_11+10,v) -# define LDIR_PUTWCHAR12(p,v) UINT16_PUT(p,LDIR_WCHAR12_13,v) -# define LDIR_PUTWCHAR13(p,v) UINT16_PUT(p,LDIR_WCHAR12_13+2,v) -# define LDIR_PUTFSTCLUSTLO(p,v) UINT16_PUT(p,LDIR_FSTCLUSTLO,v) -# endif +# define LDIR_PUTWCHAR1(p,v) UINT16_PUT(p,LDIR_WCHAR1_5,v) +# define LDIR_PUTWCHAR2(p,v) UINT16_PUT(p,LDIR_WCHAR1_5+2,v) +# define LDIR_PUTWCHAR3(p,v) UINT16_PUT(p,LDIR_WCHAR1_5+4,v) +# define LDIR_PUTWCHAR4(p,v) UINT16_PUT(p,LDIR_WCHAR1_5+6,v) +# define LDIR_PUTWCHAR5(p,v) UINT16_PUT(p,LDIR_WCHAR1_5+8,v) +# define LDIR_PUTWCHAR6(p,v) UINT16_PUT(p,LDIR_WCHAR6_11,v) +# define LDIR_PUTWCHAR7(p,v) UINT16_PUT(p,LDIR_WCHAR6_11+2,v) +# define LDIR_PUTWCHAR8(p,v) UINT16_PUT(p,LDIR_WCHAR6_11+4,v) +# define LDIR_PUTWCHAR9(p,v) UINT16_PUT(p,LDIR_WCHAR6_11+6,v) +# define LDIR_PUTWCHAR10(p,v) UINT16_PUT(p,LDIR_WCHAR6_11+8,v) +# define LDIR_PUTWCHAR11(p,v) UINT16_PUT(p,LDIR_WCHAR6_11+10,v) +# define LDIR_PUTWCHAR12(p,v) UINT16_PUT(p,LDIR_WCHAR12_13,v) +# define LDIR_PUTWCHAR13(p,v) UINT16_PUT(p,LDIR_WCHAR12_13+2,v) +# define LDIR_PUTFSTCLUSTLO(p,v) UINT16_PUT(p,LDIR_FSTCLUSTLO,v) +# endif -# define FSI_PUTLEADSIG(p,v) UINT32_PUT(p,FSI_LEADSIG,v) -# define FSI_PUTSTRUCTSIG(p,v) UINT32_PUT(p,FSI_STRUCTSIG,v) -# define FSI_PUTFREECOUNT(p,v) UINT32_PUT(p,FSI_FREECOUNT,v) -# define FSI_PUTNXTFREE(p,v) UINT32_PUT(p,FSI_NXTFREE,v) -# define FSI_PUTTRAILSIG(p,v) UINT32_PUT(p,FSI_TRAILSIG,v) +# define FSI_PUTLEADSIG(p,v) UINT32_PUT(p,FSI_LEADSIG,v) +# define FSI_PUTSTRUCTSIG(p,v) UINT32_PUT(p,FSI_STRUCTSIG,v) +# define FSI_PUTFREECOUNT(p,v) UINT32_PUT(p,FSI_FREECOUNT,v) +# define FSI_PUTNXTFREE(p,v) UINT32_PUT(p,FSI_NXTFREE,v) +# define FSI_PUTTRAILSIG(p,v) UINT32_PUT(p,FSI_TRAILSIG,v) -# define FAT_PUTFAT16(p,i,v) UINT16_PUT(p,i,v) -# define FAT_PUTFAT32(p,i,v) UINT32_PUT(p,i,v) +# define FAT_PUTFAT16(p,i,v) UINT16_PUT(p,i,v) +# define FAT_PUTFAT32(p,i,v) UINT32_PUT(p,i,v) #endif diff --git a/fs/procfs/fs_procfsuptime.c b/fs/procfs/fs_procfsuptime.c index 1425cd498f..4d4d49f546 100644 --- a/fs/procfs/fs_procfsuptime.c +++ b/fs/procfs/fs_procfsuptime.c @@ -190,11 +190,11 @@ static ssize_t uptime_read(FAR struct file *filep, FAR char *buffer, #if defined(CONFIG_HAVE_DOUBLE) && defined(CONFIG_LIBC_FLOATINGPOINT) double now; #else -# if defined(CONFIG_SYSTEM_TIME64) +# if defined(CONFIG_SYSTEM_TIME64) uint64_t sec; -# else +# else uint32_t sec; -# endif +# endif unsigned int remainder; unsigned int csec; #endif diff --git a/graphics/nxglib/fb/nxglib_copyrectangle.c b/graphics/nxglib/fb/nxglib_copyrectangle.c index 1a028939d1..a13e766e53 100644 --- a/graphics/nxglib/fb/nxglib_copyrectangle.c +++ b/graphics/nxglib/fb/nxglib_copyrectangle.c @@ -81,21 +81,21 @@ void NXGL_FUNCNAME(nxgl_copyrectangle, NXGLIB_SUFFIX) #if NXGLIB_BITSPERPIXEL < 8 /* REVISIT: Doesn't the following assume 8 pixels in a byte */ -# ifdef CONFIG_NX_PACKEDMSFIRST +# ifdef CONFIG_NX_PACKEDMSFIRST /* Get the mask for pixels that are ordered so that they pack from the * MS byte down. */ leadmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(dest->pt1.x))); tailmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(dest->pt2.x - 1))); -# else +# else /* Get the mask for pixels that are ordered so that they pack from the * LS byte up. */ leadmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(dest->pt1.x))); tailmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(dest->pt1.x - 1))); -# endif +# endif #endif /* Then copy the image */ diff --git a/graphics/nxglib/fb/nxglib_fillrectangle.c b/graphics/nxglib/fb/nxglib_fillrectangle.c index 1ff636a0a2..0681cee824 100644 --- a/graphics/nxglib/fb/nxglib_fillrectangle.c +++ b/graphics/nxglib/fb/nxglib_fillrectangle.c @@ -85,7 +85,7 @@ void NXGL_FUNCNAME(nxgl_fillrectangle, NXGLIB_SUFFIX) line = pinfo->fbmem + rect->pt1.y * stride + NXGL_SCALEX(rect->pt1.x); #if NXGLIB_BITSPERPIXEL < 8 -# ifdef CONFIG_NX_PACKEDMSFIRST +# ifdef CONFIG_NX_PACKEDMSFIRST /* Get the mask for pixels that are ordered so that they pack from the * MS byte down. @@ -93,14 +93,14 @@ void NXGL_FUNCNAME(nxgl_fillrectangle, NXGLIB_SUFFIX) leadmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(rect->pt1.x))); tailmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(rect->pt2.x - 1))); -# else +# else /* Get the mask for pixels that are ordered so that they pack from the * LS byte up. */ leadmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(rect->pt1.x))); tailmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(rect->pt1.x - 1))); -# endif +# endif #endif /* Then fill the rectangle line-by-line */ diff --git a/graphics/nxglib/fb/nxglib_getrectangle.c b/graphics/nxglib/fb/nxglib_getrectangle.c index b60aad11c0..1499f4c815 100644 --- a/graphics/nxglib/fb/nxglib_getrectangle.c +++ b/graphics/nxglib/fb/nxglib_getrectangle.c @@ -127,7 +127,7 @@ void NXGL_FUNCNAME(nxgl_getrectangle, NXGLIB_SUFFIX) rows = rect->pt2.y - rect->pt1.y + 1; #if NXGLIB_BITSPERPIXEL < 8 -# ifdef CONFIG_NX_PACKEDMSFIRST +# ifdef CONFIG_NX_PACKEDMSFIRST /* Get the mask for pixels that are ordered so that they pack from the * MS byte down. @@ -135,14 +135,14 @@ void NXGL_FUNCNAME(nxgl_getrectangle, NXGLIB_SUFFIX) leadmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(rect->pt1.x))); tailmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(rect->pt2.x - 1))); -# else +# else /* Get the mask for pixels that are ordered so that they pack from the * LS byte up. */ leadmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(rect->pt1.x))); tailmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(rect->pt1.x - 1))); -# endif +# endif #endif /* sline = address of the first pixel in the top row of the source in diff --git a/graphics/nxglib/fb/nxglib_moverectangle.c b/graphics/nxglib/fb/nxglib_moverectangle.c index 76ecf159ac..4b0fa1ee71 100644 --- a/graphics/nxglib/fb/nxglib_moverectangle.c +++ b/graphics/nxglib/fb/nxglib_moverectangle.c @@ -129,7 +129,7 @@ void NXGL_FUNCNAME(nxgl_moverectangle, NXGLIB_SUFFIX) rows = rect->pt2.y - rect->pt1.y + 1; #if NXGLIB_BITSPERPIXEL < 8 -# ifdef CONFIG_NX_PACKEDMSFIRST +# ifdef CONFIG_NX_PACKEDMSFIRST /* Get the mask for pixels that are ordered so that they pack from the * MS byte down. @@ -137,14 +137,14 @@ void NXGL_FUNCNAME(nxgl_moverectangle, NXGLIB_SUFFIX) leadmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(rect->pt1.x))); tailmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(rect->pt2.x - 1))); -# else +# else /* Get the mask for pixels that are ordered so that they pack from the * LS byte up. */ leadmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(rect->pt1.x))); tailmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(rect->pt1.x - 1))); -# endif +# endif #endif /* sline = address of the first pixel in the top row of the source in diff --git a/graphics/nxglib/fb/nxglib_setpixel.c b/graphics/nxglib/fb/nxglib_setpixel.c index 205f4ee9fe..78e52077a2 100644 --- a/graphics/nxglib/fb/nxglib_setpixel.c +++ b/graphics/nxglib/fb/nxglib_setpixel.c @@ -76,42 +76,42 @@ void NXGL_FUNCNAME(nxgl_setpixel, NXGLIB_SUFFIX) /* Shift the color into the proper position */ -# ifdef CONFIG_NX_PACKEDMSFIRST +# ifdef CONFIG_NX_PACKEDMSFIRST -#if NXGLIB_BITSPERPIXEL == 1 +# if NXGLIB_BITSPERPIXEL == 1 shift = (7 - (pos->x & 7)); /* Shift is 0, 1, ... 7 */ mask = (1 << shift); /* Mask is 0x01, 0x02, .. 0x80 */ color <<= shift; /* Color is positioned under the mask */ -#elif NXGLIB_BITSPERPIXEL == 2 +# elif NXGLIB_BITSPERPIXEL == 2 shift = (6 - ((pos->x & 3) << 1)); /* Shift is 0, 2, 4, or 6 */ mask = (3 << shift); /* Mask is 0x03, 0x0c, 0x30, or 0xc0 */ color <<= shift; /* Color is positioned under the mask */ -#elif NXGLIB_BITSPERPIXEL == 4 +# elif NXGLIB_BITSPERPIXEL == 4 shift = (4 - ((pos->x & 1) << 2)); /* Shift is 0 or 4 */ mask = (15 << shift); /* Mask is 0x0f or 0xf0 */ color <<= shift; /* Color is positioned under the mask */ -#else -# error "Unsupported pixel depth" -#endif +# else +# error "Unsupported pixel depth" +# endif -# else /* CONFIG_NX_PACKEDMSFIRST */ +# else /* CONFIG_NX_PACKEDMSFIRST */ -#if NXGLIB_BITSPERPIXEL == 1 +# if NXGLIB_BITSPERPIXEL == 1 shift = (pos->x & 7); /* Shift is 0, 1, ... 7 */ mask = (1 << shift); /* Mask is 0x01, 0x02, .. 0x80 */ color <<= shift; /* Color is positioned under the mask */ -#elif NXGLIB_BITSPERPIXEL == 2 +# elif NXGLIB_BITSPERPIXEL == 2 shift = (pos->x & 3) << 1; /* Shift is 0, 2, 4, or 6 */ mask = (3 << shift); /* Mask is 0x03, 0x0c, 0x30, or 0xc0 */ color <<= shift; /* Color is positioned under the mask */ -#elif NXGLIB_BITSPERPIXEL == 4 +# elif NXGLIB_BITSPERPIXEL == 4 shift = (pos->x & 1) << 2; /* Shift is 0 or 4 */ mask = (15 << shift); /* Mask is 0x0f or 0xf0 */ color <<= shift; /* Color is positioned under the mask */ -#else -# error "Unsupported pixel depth" -#endif -#endif /* CONFIG_NX_PACKEDMSFIRST */ +# else +# error "Unsupported pixel depth" +# endif +# endif /* CONFIG_NX_PACKEDMSFIRST */ /* Handle masking of the fractional byte */ diff --git a/graphics/nxglib/lcd/nxglib_setpixel.c b/graphics/nxglib/lcd/nxglib_setpixel.c index 055081cd2c..4a9e58506e 100644 --- a/graphics/nxglib/lcd/nxglib_setpixel.c +++ b/graphics/nxglib/lcd/nxglib_setpixel.c @@ -73,39 +73,39 @@ void NXGL_FUNCNAME(nxgl_setpixel, NXGLIB_SUFFIX) # ifdef CONFIG_NX_PACKEDMSFIRST -#if NXGLIB_BITSPERPIXEL == 1 +# if NXGLIB_BITSPERPIXEL == 1 shift = (7 - (pos->x & 7)); /* Shift is 0, 1, ... 7 */ mask = (1 << shift); /* Mask is 0x01, 0x02, .. 0x80 */ color <<= shift; /* Color is positioned under the mask */ -#elif NXGLIB_BITSPERPIXEL == 2 +# elif NXGLIB_BITSPERPIXEL == 2 shift = (6 - ((pos->x & 3) << 1)); /* Shift is 0, 2, 4, or 6 */ mask = (3 << shift); /* Mask is 0x03, 0x0c, 0x30, or 0xc0 */ color <<= shift; /* Color is positioned under the mask */ -#elif NXGLIB_BITSPERPIXEL == 4 +# elif NXGLIB_BITSPERPIXEL == 4 shift = (4 - ((pos->x & 1) << 2)); /* Shift is 0 or 4 */ mask = (15 << shift); /* Mask is 0x0f or 0xf0 */ color <<= shift; /* Color is positioned under the mask */ -#else -# error "Unsupported pixel depth" -#endif +# else +# error "Unsupported pixel depth" +# endif -# else /* CONFIG_NX_PACKEDMSFIRST */ +#else /* CONFIG_NX_PACKEDMSFIRST */ -#if NXGLIB_BITSPERPIXEL == 1 +# if NXGLIB_BITSPERPIXEL == 1 shift = (pos->x & 7); /* Shift is 0, 1, ... 7 */ mask = (1 << shift); /* Mask is 0x01, 0x02, .. 0x80 */ color <<= shift; /* Color is positioned under the mask */ -#elif NXGLIB_BITSPERPIXEL == 2 +# elif NXGLIB_BITSPERPIXEL == 2 shift = (pos->x & 3) << 1; /* Shift is 0, 2, 4, or 6 */ mask = (3 << shift); /* Mask is 0x03, 0x0c, 0x30, or 0xc0 */ color <<= shift; /* Color is positioned under the mask */ -#elif NXGLIB_BITSPERPIXEL == 4 +# elif NXGLIB_BITSPERPIXEL == 4 shift = (pos->x & 1) << 2; /* Shift is 0 or 4 */ mask = (15 << shift); /* Mask is 0x0f or 0xf0 */ color <<= shift; /* Color is positioned under the mask */ -#else -# error "Unsupported pixel depth" -#endif +# else +# error "Unsupported pixel depth" +# endif #endif /* CONFIG_NX_PACKEDMSFIRST */ /* Handle masking of the fractional byte */ diff --git a/graphics/nxglib/nxglib.h b/graphics/nxglib/nxglib.h index bae69291fc..3196ae18bc 100644 --- a/graphics/nxglib/nxglib.h +++ b/graphics/nxglib/nxglib.h @@ -38,11 +38,11 @@ #undef EXTERN #if defined(__cplusplus) -# define EXTERN extern "C" +# define EXTERN extern "C" extern "C" { #else -# define EXTERN extern +# define EXTERN extern #endif /**************************************************************************** diff --git a/graphics/nxglib/pwfb/pwfb_copyrectangle.c b/graphics/nxglib/pwfb/pwfb_copyrectangle.c index 528f523536..afdfd9cd32 100644 --- a/graphics/nxglib/pwfb/pwfb_copyrectangle.c +++ b/graphics/nxglib/pwfb/pwfb_copyrectangle.c @@ -81,21 +81,21 @@ void NXGL_FUNCNAME(pwfb_copyrectangle, NXGLIB_SUFFIX) #if NXGLIB_BITSPERPIXEL < 8 /* REVISIT: Doesn't the following assume 8 pixels in a byte */ -# ifdef CONFIG_NX_PACKEDMSFIRST +# ifdef CONFIG_NX_PACKEDMSFIRST /* Get the mask for pixels that are ordered so that they pack from the * MS byte down. */ leadmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(dest->pt1.x))); tailmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(dest->pt2.x - 1))); -# else +# else /* Get the mask for pixels that are ordered so that they pack from the * LS byte up. */ leadmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(dest->pt1.x))); tailmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(dest->pt1.x - 1))); -# endif +# endif #endif /* Then copy the image */ diff --git a/graphics/nxglib/pwfb/pwfb_fillrectangle.c b/graphics/nxglib/pwfb/pwfb_fillrectangle.c index df208d342e..0b5239504f 100644 --- a/graphics/nxglib/pwfb/pwfb_fillrectangle.c +++ b/graphics/nxglib/pwfb/pwfb_fillrectangle.c @@ -86,7 +86,7 @@ void NXGL_FUNCNAME(pwfb_fillrectangle, NXGLIB_SUFFIX) NXGL_SCALEX(rect->pt1.x); #if NXGLIB_BITSPERPIXEL < 8 -# ifdef CONFIG_NX_PACKEDMSFIRST +# ifdef CONFIG_NX_PACKEDMSFIRST /* Get the mask for pixels that are ordered so that they pack from the * MS byte down. @@ -94,14 +94,14 @@ void NXGL_FUNCNAME(pwfb_fillrectangle, NXGLIB_SUFFIX) leadmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(rect->pt1.x))); tailmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(rect->pt2.x - 1))); -# else +# else /* Get the mask for pixels that are ordered so that they pack from the * LS byte up. */ leadmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(rect->pt1.x))); tailmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(rect->pt1.x - 1))); -# endif +# endif #endif /* Then fill the rectangle line-by-line */ diff --git a/graphics/nxglib/pwfb/pwfb_getrectangle.c b/graphics/nxglib/pwfb/pwfb_getrectangle.c index edbeececa5..3e87aeda23 100644 --- a/graphics/nxglib/pwfb/pwfb_getrectangle.c +++ b/graphics/nxglib/pwfb/pwfb_getrectangle.c @@ -128,7 +128,7 @@ void NXGL_FUNCNAME(pwfb_getrectangle, NXGLIB_SUFFIX) rows = rect->pt2.y - rect->pt1.y + 1; #if NXGLIB_BITSPERPIXEL < 8 -# ifdef CONFIG_NX_PACKEDMSFIRST +# ifdef CONFIG_NX_PACKEDMSFIRST /* Get the mask for pixels that are ordered so that they pack from the * MS byte down. @@ -136,14 +136,14 @@ void NXGL_FUNCNAME(pwfb_getrectangle, NXGLIB_SUFFIX) leadmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(rect->pt1.x))); tailmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(rect->pt2.x - 1))); -# else +# else /* Get the mask for pixels that are ordered so that they pack from the * LS byte up. */ leadmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(rect->pt1.x))); tailmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(rect->pt1.x - 1))); -# endif +# endif #endif /* sline = address of the first pixel in the top row of the source in diff --git a/graphics/nxglib/pwfb/pwfb_moverectangle.c b/graphics/nxglib/pwfb/pwfb_moverectangle.c index ba86f00a89..516c4a1e1e 100644 --- a/graphics/nxglib/pwfb/pwfb_moverectangle.c +++ b/graphics/nxglib/pwfb/pwfb_moverectangle.c @@ -129,7 +129,7 @@ void NXGL_FUNCNAME(pwfb_moverectangle, NXGLIB_SUFFIX) rows = rect->pt2.y - rect->pt1.y + 1; #if NXGLIB_BITSPERPIXEL < 8 -# ifdef CONFIG_NX_PACKEDMSFIRST +# ifdef CONFIG_NX_PACKEDMSFIRST /* Get the mask for pixels that are ordered so that they pack from the * MS byte down. @@ -137,14 +137,14 @@ void NXGL_FUNCNAME(pwfb_moverectangle, NXGLIB_SUFFIX) leadmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(rect->pt1.x))); tailmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(rect->pt2.x - 1))); -# else +# else /* Get the mask for pixels that are ordered so that they pack from the * LS byte up. */ leadmask = (uint8_t)(0xff << (8 - NXGL_REMAINDERX(rect->pt1.x))); tailmask = (uint8_t)(0xff >> (8 - NXGL_REMAINDERX(rect->pt1.x - 1))); -# endif +# endif #endif /* sline = address of the first pixel in the top row of the source in diff --git a/graphics/nxglib/pwfb/pwfb_setpixel.c b/graphics/nxglib/pwfb/pwfb_setpixel.c index 7e38d7b911..04c4086f7f 100644 --- a/graphics/nxglib/pwfb/pwfb_setpixel.c +++ b/graphics/nxglib/pwfb/pwfb_setpixel.c @@ -77,42 +77,42 @@ void NXGL_FUNCNAME(pwfb_setpixel, NXGLIB_SUFFIX) /* Shift the color into the proper position */ -# ifdef CONFIG_NX_PACKEDMSFIRST +# ifdef CONFIG_NX_PACKEDMSFIRST -#if NXGLIB_BITSPERPIXEL == 1 +# if NXGLIB_BITSPERPIXEL == 1 shift = (7 - (pos->x & 7)); /* Shift is 0, 1, ... 7 */ mask = (1 << shift); /* Mask is 0x01, 0x02, .. 0x80 */ color <<= shift; /* Color is positioned under the mask */ -#elif NXGLIB_BITSPERPIXEL == 2 +# elif NXGLIB_BITSPERPIXEL == 2 shift = (6 - ((pos->x & 3) << 1)); /* Shift is 0, 2, 4, or 6 */ mask = (3 << shift); /* Mask is 0x03, 0x0c, 0x30, or 0xc0 */ color <<= shift; /* Color is positioned under the mask */ -#elif NXGLIB_BITSPERPIXEL == 4 +# elif NXGLIB_BITSPERPIXEL == 4 shift = (4 - ((pos->x & 1) << 2)); /* Shift is 0 or 4 */ mask = (15 << shift); /* Mask is 0x0f or 0xf0 */ color <<= shift; /* Color is positioned under the mask */ -#else -# error "Unsupported pixel depth" -#endif +# else +# error "Unsupported pixel depth" +# endif -# else /* CONFIG_NX_PACKEDMSFIRST */ +# else /* CONFIG_NX_PACKEDMSFIRST */ -#if NXGLIB_BITSPERPIXEL == 1 +# if NXGLIB_BITSPERPIXEL == 1 shift = (pos->x & 7); /* Shift is 0, 1, ... 7 */ mask = (1 << shift); /* Mask is 0x01, 0x02, .. 0x80 */ color <<= shift; /* Color is positioned under the mask */ -#elif NXGLIB_BITSPERPIXEL == 2 +# elif NXGLIB_BITSPERPIXEL == 2 shift = (pos->x & 3) << 1; /* Shift is 0, 2, 4, or 6 */ mask = (3 << shift); /* Mask is 0x03, 0x0c, 0x30, or 0xc0 */ color <<= shift; /* Color is positioned under the mask */ -#elif NXGLIB_BITSPERPIXEL == 4 +# elif NXGLIB_BITSPERPIXEL == 4 shift = (pos->x & 1) << 2; /* Shift is 0 or 4 */ mask = (15 << shift); /* Mask is 0x0f or 0xf0 */ color <<= shift; /* Color is positioned under the mask */ -#else -# error "Unsupported pixel depth" -#endif -#endif /* CONFIG_NX_PACKEDMSFIRST */ +# else +# error "Unsupported pixel depth" +# endif +# endif /* CONFIG_NX_PACKEDMSFIRST */ /* Handle masking of the fractional byte */ diff --git a/include/debug.h b/include/debug.h index eb133d902b..daee3a4162 100644 --- a/include/debug.h +++ b/include/debug.h @@ -815,12 +815,12 @@ # ifdef CONFIG_DEBUG_INFO # define infodumpbuffer(m,b,n) lib_dumpbuffer(m,b,n) # else -# define infodumpbuffer(m,b,n) +# define infodumpbuffer(m,b,n) # endif #else -# define errdumpbuffer(m,b,n) -# define infodumpbuffer(m,b,n) -# endif +# define errdumpbuffer(m,b,n) +# define infodumpbuffer(m,b,n) +# endif /* Subsystem specific debug */ diff --git a/include/execinfo.h b/include/execinfo.h index 2eb3778013..ae3a555daa 100644 --- a/include/execinfo.h +++ b/include/execinfo.h @@ -39,13 +39,13 @@ * ARRAY and return the exact number of values stored. */ -# define backtrace(buffer, size) sched_backtrace(_SCHED_GETTID(), \ +# define backtrace(buffer, size) sched_backtrace(_SCHED_GETTID(), \ buffer, size, 0) -# define dump_stack() sched_dumpstack(_SCHED_GETTID()) +# define dump_stack() sched_dumpstack(_SCHED_GETTID()) #else -# define backtrace(buffer, size) 0 -# define dump_stack() +# define backtrace(buffer, size) 0 +# define dump_stack() #endif /**************************************************************************** diff --git a/include/limits.h b/include/limits.h index c0a322148a..c0f8017f27 100644 --- a/include/limits.h +++ b/include/limits.h @@ -174,9 +174,9 @@ #define _POSIX_TIMER_MAX 32 #ifdef CONFIG_USEC_PER_TICK -# define _POSIX_CLOCKRES_MIN ((CONFIG_USEC_PER_TICK)*1000) +# define _POSIX_CLOCKRES_MIN ((CONFIG_USEC_PER_TICK)*1000) #else -# define _POSIX_CLOCKRES_MIN (10*1000000) +# define _POSIX_CLOCKRES_MIN (10*1000000) #endif /* Required for asynchronous I/O */ diff --git a/include/lzf.h b/include/lzf.h index f73b85b295..d7c8211468 100644 --- a/include/lzf.h +++ b/include/lzf.h @@ -87,10 +87,10 @@ struct lzf_type1_header_s /* Compressed data header */ /* LZF hash table */ #if LZF_USE_OFFSETS -# define LZF_HSLOT_BIAS ((const uint8_t *)in_data) +# define LZF_HSLOT_BIAS ((const uint8_t *)in_data) typedef unsigned int lzf_hslot_t; #else -# define LZF_HSLOT_BIAS 0 +# define LZF_HSLOT_BIAS 0 typedef const uint8_t *lzf_hslot_t; #endif diff --git a/include/netinet/icmp6.h b/include/netinet/icmp6.h index eb85b6f86e..532d95b360 100644 --- a/include/netinet/icmp6.h +++ b/include/netinet/icmp6.h @@ -316,11 +316,11 @@ struct rr_pco_use /* use prefix part */ #define ICMP6_RR_PCOUSE_RAFLAGS_AUTO 0x10 #if __BYTE_ORDER == __BIG_ENDIAN -# define ICMP6_RR_PCOUSE_FLAGS_DECRVLTIME 0x80000000 -# define ICMP6_RR_PCOUSE_FLAGS_DECRPLTIME 0x40000000 +# define ICMP6_RR_PCOUSE_FLAGS_DECRVLTIME 0x80000000 +# define ICMP6_RR_PCOUSE_FLAGS_DECRPLTIME 0x40000000 #elif __BYTE_ORDER == __LITTLE_ENDIAN -# define ICMP6_RR_PCOUSE_FLAGS_DECRVLTIME 0x80 -# define ICMP6_RR_PCOUSE_FLAGS_DECRPLTIME 0x40 +# define ICMP6_RR_PCOUSE_FLAGS_DECRVLTIME 0x80 +# define ICMP6_RR_PCOUSE_FLAGS_DECRPLTIME 0x40 #endif struct rr_result /* router renumbering result message */ @@ -333,11 +333,11 @@ struct rr_result /* router renumbering result message */ }; #if __BYTE_ORDER == __BIG_ENDIAN -# define ICMP6_RR_RESULT_FLAGS_OOB 0x0002 -# define ICMP6_RR_RESULT_FLAGS_FORBIDDEN 0x0001 +# define ICMP6_RR_RESULT_FLAGS_OOB 0x0002 +# define ICMP6_RR_RESULT_FLAGS_FORBIDDEN 0x0001 #elif __BYTE_ORDER == __LITTLE_ENDIAN -# define ICMP6_RR_RESULT_FLAGS_OOB 0x0200 -# define ICMP6_RR_RESULT_FLAGS_FORBIDDEN 0x0100 +# define ICMP6_RR_RESULT_FLAGS_OOB 0x0200 +# define ICMP6_RR_RESULT_FLAGS_FORBIDDEN 0x0100 #endif /* Mobile IPv6 extension: Advertisement Interval. */ diff --git a/include/nuttx/board.h b/include/nuttx/board.h index 05b324b780..44467c8c22 100644 --- a/include/nuttx/board.h +++ b/include/nuttx/board.h @@ -547,7 +547,7 @@ void board_lcd_uninitialize(void); #ifdef CONFIG_ARCH_LEDS void board_autoled_initialize(void); #else -# define board_autoled_initialize() +# define board_autoled_initialize() #endif /**************************************************************************** @@ -582,7 +582,7 @@ void board_autoled_initialize(void); #ifdef CONFIG_ARCH_LEDS void board_autoled_on(int led); #else -# define board_autoled_on(led) +# define board_autoled_on(led) #endif /**************************************************************************** @@ -613,7 +613,7 @@ void board_autoled_on(int led); #ifdef CONFIG_ARCH_LEDS void board_autoled_off(int led); #else -# define board_autoled_off(led) +# define board_autoled_off(led) #endif /**************************************************************************** diff --git a/include/nuttx/clock.h b/include/nuttx/clock.h index 0ca726e0ce..8ec8a689d6 100644 --- a/include/nuttx/clock.h +++ b/include/nuttx/clock.h @@ -135,9 +135,9 @@ */ #ifdef CONFIG_USEC_PER_TICK -# define USEC_PER_TICK (CONFIG_USEC_PER_TICK) +# define USEC_PER_TICK (CONFIG_USEC_PER_TICK) #else -# define USEC_PER_TICK (10000) +# define USEC_PER_TICK (10000) #endif /* MSEC_PER_TICK can be very inaccurate if CONFIG_USEC_PER_TICK is not an diff --git a/include/nuttx/lcd/ili9325.h b/include/nuttx/lcd/ili9325.h index 530c347ebc..4ebdadef43 100644 --- a/include/nuttx/lcd/ili9325.h +++ b/include/nuttx/lcd/ili9325.h @@ -334,7 +334,7 @@ # define ILI9325_GAMMA_CTRL7_KN2(n) ((uint16_t)(n) << ILI9325_GAMMA_CTRL7_KN2_SHIFT) #define ILI9325_GAMMA_CTRL7_KN3_SHIFT 8 #define ILI9325_GAMMA_CTRL7_KN3_MASK (7 << ILI9325_GAMMA_CTRL7_KN3_SHIFT) -# define ILI9325_GAMMA_CTRL7_KN3(n) ((uint16_t)(n) << ILI9325_GAMMA_CTRL7_KN3_SHIFT) +# define ILI9325_GAMMA_CTRL7_KN3(n) ((uint16_t)(n) << ILI9325_GAMMA_CTRL7_KN3_SHIFT) /* ILI9325_GAMMA_CTRL8, Gamma Control 8, Offset: 0x39 */ diff --git a/include/nuttx/lib/modlib.h b/include/nuttx/lib/modlib.h index 6b72429cee..205981d817 100644 --- a/include/nuttx/lib/modlib.h +++ b/include/nuttx/lib/modlib.h @@ -64,9 +64,9 @@ #endif #ifdef CONFIG_MODLIB_DUMPBUFFER -# define modlib_dumpbuffer(m,b,n) sinfodumpbuffer(m,b,n) +# define modlib_dumpbuffer(m,b,n) sinfodumpbuffer(m,b,n) #else -# define modlib_dumpbuffer(m,b,n) +# define modlib_dumpbuffer(m,b,n) #endif /* Module names. These are only used by the kernel module and will be diff --git a/include/nuttx/mqueue.h b/include/nuttx/mqueue.h index 0b4f6cb19a..1c4731d2a7 100644 --- a/include/nuttx/mqueue.h +++ b/include/nuttx/mqueue.h @@ -79,14 +79,14 @@ #endif #if CONFIG_FS_MQUEUE_NPOLLWAITERS > 0 -# define nxmq_pollnotify(msgq, eventset) \ - poll_notify(msgq->fds, CONFIG_FS_MQUEUE_NPOLLWAITERS, eventset) +# define nxmq_pollnotify(msgq, eventset) \ + poll_notify(msgq->fds, CONFIG_FS_MQUEUE_NPOLLWAITERS, eventset) #else -# define nxmq_pollnotify(msgq, eventset) +# define nxmq_pollnotify(msgq, eventset) #endif -# define MQ_WNELIST(cmn) (&((cmn).waitfornotempty)) -# define MQ_WNFLIST(cmn) (&((cmn).waitfornotfull)) +# define MQ_WNELIST(cmn) (&((cmn).waitfornotempty)) +# define MQ_WNFLIST(cmn) (&((cmn).waitfornotfull)) /**************************************************************************** * Public Type Declarations diff --git a/include/nuttx/mtd/onfi.h b/include/nuttx/mtd/onfi.h index 6e579babfb..653ad49eb2 100644 --- a/include/nuttx/mtd/onfi.h +++ b/include/nuttx/mtd/onfi.h @@ -152,7 +152,7 @@ bool onfi_embeddedecc(FAR const struct onfi_pgparam_s *onfi, uintptr_t cmdaddr, uintptr_t addraddr, uintptr_t dataaddr, bool enable); #else -# define onfi_embeddedecc(o,c,a,d,e) (false) +# define onfi_embeddedecc(o,c,a,d,e) (false) #endif /**************************************************************************** diff --git a/include/nuttx/net/igmp.h b/include/nuttx/net/igmp.h index 338036d0dc..ba382b4638 100644 --- a/include/nuttx/net/igmp.h +++ b/include/nuttx/net/igmp.h @@ -148,9 +148,9 @@ struct igmp_stats_s net_stats_t report_received; }; -# define IGMP_STATINCR(p) ((p)++) +# define IGMP_STATINCR(p) ((p)++) #else -# define IGMP_STATINCR(p) +# define IGMP_STATINCR(p) #endif /**************************************************************************** diff --git a/include/nuttx/net/mld.h b/include/nuttx/net/mld.h index 5472ff5e53..3390f3d060 100644 --- a/include/nuttx/net/mld.h +++ b/include/nuttx/net/mld.h @@ -391,9 +391,9 @@ struct mld_stats_s net_stats_t done_received; /* DONE packets received */ }; -# define MLD_STATINCR(p) ((p)++) +# define MLD_STATINCR(p) ((p)++) #else -# define MLD_STATINCR(p) +# define MLD_STATINCR(p) #endif /**************************************************************************** diff --git a/include/nuttx/net/netdev.h b/include/nuttx/net/netdev.h index cb6d69d58c..9e279a0fe0 100644 --- a/include/nuttx/net/netdev.h +++ b/include/nuttx/net/netdev.h @@ -278,18 +278,18 @@ struct net_driver_s defined(CONFIG_NET_TUN) union { -# if defined(CONFIG_NET_ETHERNET) || defined(CONFIG_NET_TUN) +# if defined(CONFIG_NET_ETHERNET) || defined(CONFIG_NET_TUN) /* Ethernet device identity */ struct ether_addr ether; /* Device Ethernet MAC address */ -# endif +# endif -# if defined(CONFIG_NET_6LOWPAN) || defined(CONFIG_NET_BLUETOOTH) || \ - defined(CONFIG_NET_IEEE802154) +# if defined(CONFIG_NET_6LOWPAN) || defined(CONFIG_NET_BLUETOOTH) || \ + defined(CONFIG_NET_IEEE802154) /* The address assigned to an IEEE 802.15.4 or generic packet radio. */ struct netdev_varaddr_s radio; -# endif +# endif } d_mac; #endif diff --git a/include/nuttx/nx/nxfonts.h b/include/nuttx/nx/nxfonts.h index 16bb00e930..77bebf168f 100644 --- a/include/nuttx/nx/nxfonts.h +++ b/include/nuttx/nx/nxfonts.h @@ -45,147 +45,147 @@ /* Sans serif fonts */ #if defined(CONFIG_NXFONT_SANS23X27) /* The "legacy," tiny NuttX font */ -# define NXFONT_DEFAULT FONTID_SANS23X27 +# define NXFONT_DEFAULT FONTID_SANS23X27 #elif defined(CONFIG_NXFONT_SANS17X22) -# define NXFONT_DEFAULT FONTID_SANS17X22 +# define NXFONT_DEFAULT FONTID_SANS17X22 #elif defined(CONFIG_NXFONT_SANS20X26) -# define NXFONT_DEFAULT FONTID_SANS20X26 +# define NXFONT_DEFAULT FONTID_SANS20X26 #elif defined(CONFIG_NXFONT_SANS22X29) -# define NXFONT_DEFAULT FONTID_SANS22X29 +# define NXFONT_DEFAULT FONTID_SANS22X29 #elif defined(CONFIG_NXFONT_SANS28X37) -# define NXFONT_DEFAULT FONTID_SANS28X37 +# define NXFONT_DEFAULT FONTID_SANS28X37 #elif defined(CONFIG_NXFONT_SANS39X48) -# define NXFONT_DEFAULT FONTID_SANS39X48 +# define NXFONT_DEFAULT FONTID_SANS39X48 /* Sans serif bold fonts */ #elif defined(CONFIG_NXFONT_SANS17X23B) -# define NXFONT_DEFAULT FONTID_SANS17X23B +# define NXFONT_DEFAULT FONTID_SANS17X23B #elif defined(CONFIG_NXFONT_SANS20X27B) -# define NXFONT_DEFAULT FONTID_SANS20X27B +# define NXFONT_DEFAULT FONTID_SANS20X27B #elif defined(CONFIG_NXFONT_SANS22X29B) -# define NXFONT_DEFAULT FONTID_SANS22X29B +# define NXFONT_DEFAULT FONTID_SANS22X29B #elif defined(CONFIG_NXFONT_SANS28X37B) -# define NXFONT_DEFAULT FONTID_SANS28X37B +# define NXFONT_DEFAULT FONTID_SANS28X37B #elif defined(CONFIG_NXFONT_SANS40X49B) -# define NXFONT_DEFAULT FONTID_SANS40X49B +# define NXFONT_DEFAULT FONTID_SANS40X49B /* Serif fonts */ #elif defined(CONFIG_NXFONT_SERIF22X29) -# define NXFONT_DEFAULT FONTID_SERIF22X29 +# define NXFONT_DEFAULT FONTID_SERIF22X29 #elif defined(CONFIG_NXFONT_SERIF29X37) -# define NXFONT_DEFAULT FONTID_SERIF29X37 +# define NXFONT_DEFAULT FONTID_SERIF29X37 #elif defined(CONFIG_NXFONT_SERIF38X48) -# define NXFONT_DEFAULT FONTID_SERIF38X48 +# define NXFONT_DEFAULT FONTID_SERIF38X48 /* Serif bold fonts */ #elif defined(CONFIG_NXFONT_SERIF22X28B) -# define NXFONT_DEFAULT FONTID_SERIF22X28B +# define NXFONT_DEFAULT FONTID_SERIF22X28B #elif defined(CONFIG_NXFONT_SERIF27X38B) -# define NXFONT_DEFAULT FONTID_SERIF27X38B +# define NXFONT_DEFAULT FONTID_SERIF27X38B #elif defined(CONFIG_NXFONT_SERIF38X49B) -# define NXFONT_DEFAULT FONTID_SERIF38X49B +# define NXFONT_DEFAULT FONTID_SERIF38X49B /* Pixel fonts */ #elif defined(CONFIG_NXFONT_PIXEL_UNICODE) -# define NXFONT_DEFAULT FONTID_PIXEL_UNICODE +# define NXFONT_DEFAULT FONTID_PIXEL_UNICODE #elif defined(CONFIG_NXFONT_PIXEL_LCD_MACHINE) -# define NXFONT_DEFAULT FONTID_PIXEL_LCD_MACHINE +# define NXFONT_DEFAULT FONTID_PIXEL_LCD_MACHINE /* X11 misc fixed fonts */ #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_4X6) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_4X6 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_4X6 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_5X7) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_5X7 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_5X7 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_5X8) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_5X8 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_5X8 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_6X9) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X9 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X9 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_6X10) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X10 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X10 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_6X12) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X12 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X12 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_6X13) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X13 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X13 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_6X13B) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X13B +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X13B #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_6X13O) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X13O +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_6X13O #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_7X13) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X13 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X13 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_7X13B) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X13B +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X13B #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_7X13O) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X13O +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X13O #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_7X14) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X14 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X14 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_7X14B) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X14B +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_7X14B #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_8X13) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_8X13 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_8X13 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_8X13B) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_8X13B +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_8X13B #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_8X13O) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_8X13O +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_8X13O #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_9X15) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_9X15 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_9X15 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_9X15B) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_9X15B +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_9X15B #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_9X18) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_9X18 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_9X18 #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_9X18B) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_9X18B +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_9X18B #elif defined(CONFIG_NXFONT_X11_MISC_FIXED_10X20) -# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_10X20 +# define NXFONT_DEFAULT FONTID_X11_MISC_FIXED_10X20 /* Mono-space fonts */ #elif defined(CONFIG_NXFONT_MONO5X8) -# define NXFONT_DEFAULT FONTID_MONO5X8 +# define NXFONT_DEFAULT FONTID_MONO5X8 /* Tom Thumb mono-space 4x6 font */ #elif defined(CONFIG_NXFONT_TOM_THUMB_4X6) -# define NXFONT_DEFAULT FONTID_TOM_THUMB_4X6 +# define NXFONT_DEFAULT FONTID_TOM_THUMB_4X6 #endif @@ -468,11 +468,11 @@ struct nxfonts_glyph_s #undef EXTERN #if defined(__cplusplus) -# define EXTERN extern "C" +# define EXTERN extern "C" extern "C" { #else -# define EXTERN extern +# define EXTERN extern #endif /**************************************************************************** diff --git a/include/nuttx/nx/nxglib.h b/include/nuttx/nx/nxglib.h index 589c113d26..57254df5e0 100644 --- a/include/nuttx/nx/nxglib.h +++ b/include/nuttx/nx/nxglib.h @@ -98,11 +98,11 @@ #undef EXTERN #if defined(__cplusplus) -# define EXTERN extern "C" +# define EXTERN extern "C" extern "C" { #else -# define EXTERN extern +# define EXTERN extern #endif /**************************************************************************** diff --git a/include/nuttx/nx/nxterm.h b/include/nuttx/nx/nxterm.h index 9b7e3e5fc6..40e0997351 100644 --- a/include/nuttx/nx/nxterm.h +++ b/include/nuttx/nx/nxterm.h @@ -266,11 +266,11 @@ struct nxtermioc_resize_s #undef EXTERN #if defined(__cplusplus) -# define EXTERN extern "C" +# define EXTERN extern "C" extern "C" { #else -# define EXTERN extern +# define EXTERN extern #endif /**************************************************************************** diff --git a/include/nuttx/nx/nxtk.h b/include/nuttx/nx/nxtk.h index 6c6aabf430..7c14bca90c 100644 --- a/include/nuttx/nx/nxtk.h +++ b/include/nuttx/nx/nxtk.h @@ -89,11 +89,11 @@ typedef FAR void *NXTKWINDOW; #undef EXTERN #if defined(__cplusplus) -# define EXTERN extern "C" +# define EXTERN extern "C" extern "C" { #else -# define EXTERN extern +# define EXTERN extern #endif /**************************************************************************** diff --git a/include/nuttx/power/bq2429x.h b/include/nuttx/power/bq2429x.h index 67a323818a..a8951b9890 100644 --- a/include/nuttx/power/bq2429x.h +++ b/include/nuttx/power/bq2429x.h @@ -163,10 +163,10 @@ /* Fast Charge Timer Settings */ #define BQ2429XR5_CHG_TIMER_SHIFT 1 #define BQ2429XR5_CHG_TIMER_MASK (3 << BQ2429XR5_CHG_TIMER_SHIFT) -# define BQ2429XR5_CHG_TIMER_05hrs (0 << BQ2429XR5_CHG_TIMER_SHIFT) -# define BQ2429XR5_CHG_TIMER_08hrs (1 << BQ2429XR5_CHG_TIMER_SHIFT) -# define BQ2429XR5_CHG_TIMER_12hrs (2 << BQ2429XR5_CHG_TIMER_SHIFT) -# define BQ2429XR5_CHG_TIMER_20hrs (3 << BQ2429XR5_CHG_TIMER_SHIFT) +# define BQ2429XR5_CHG_TIMER_05hrs (0 << BQ2429XR5_CHG_TIMER_SHIFT) +# define BQ2429XR5_CHG_TIMER_08hrs (1 << BQ2429XR5_CHG_TIMER_SHIFT) +# define BQ2429XR5_CHG_TIMER_12hrs (2 << BQ2429XR5_CHG_TIMER_SHIFT) +# define BQ2429XR5_CHG_TIMER_20hrs (3 << BQ2429XR5_CHG_TIMER_SHIFT) #define BQ2429XR5_RESERVED0 (1 << 0) /* REG06 Boost Voltage/Thermal Regulation Control register */ diff --git a/include/nuttx/semaphore.h b/include/nuttx/semaphore.h index 9f59b221de..eebb3cc833 100644 --- a/include/nuttx/semaphore.h +++ b/include/nuttx/semaphore.h @@ -39,22 +39,23 @@ /* Initializers */ #ifdef CONFIG_PRIORITY_INHERITANCE -# if CONFIG_SEM_PREALLOCHOLDERS > 0 +# if CONFIG_SEM_PREALLOCHOLDERS > 0 /* semcount, flags, waitlist, hhead */ -# define NXSEM_INITIALIZER(c, f) \ - {(c), (f), SEM_WAITLIST_INITIALIZER, NULL} -# else +# define NXSEM_INITIALIZER(c, f) \ + {(c), (f), SEM_WAITLIST_INITIALIZER, NULL} +# else /* semcount, flags, waitlist, holder[2] */ -# define NXSEM_INITIALIZER(c, f) \ - {(c), (f), SEM_WAITLIST_INITIALIZER, {SEMHOLDER_INITIALIZER, SEMHOLDER_INITIALIZER}} -# endif +# define NXSEM_INITIALIZER(c, f) \ + {(c), (f), SEM_WAITLIST_INITIALIZER, \ + {SEMHOLDER_INITIALIZER, SEMHOLDER_INITIALIZER}} +# endif #else /* CONFIG_PRIORITY_INHERITANCE */ /* semcount, flags, waitlist */ # define NXSEM_INITIALIZER(c, f) \ - {(c), (f), SEM_WAITLIST_INITIALIZER} + {(c), (f), SEM_WAITLIST_INITIALIZER} #endif /* CONFIG_PRIORITY_INHERITANCE */ /* Most internal nxsem_* interfaces are not available in the user space in diff --git a/include/nuttx/sensors/ds18b20.h b/include/nuttx/sensors/ds18b20.h index 7b8204c767..44afe14163 100644 --- a/include/nuttx/sensors/ds18b20.h +++ b/include/nuttx/sensors/ds18b20.h @@ -51,9 +51,9 @@ struct ds18b20_alarm_s { int8_t thigh; /* Upper alarm temperature */ int8_t tlow; /* Lower alarm temperature */ -# ifdef CONFIG_SENSORS_DS18B20_POLL +# ifdef CONFIG_SENSORS_DS18B20_POLL bool wakeup; /* Wakeup poll requests only when alarm detected */ -# endif +# endif }; /**************************************************************************** diff --git a/include/nuttx/timers/cs2100-cp.h b/include/nuttx/timers/cs2100-cp.h index 459aaa9c7d..a28c770eeb 100644 --- a/include/nuttx/timers/cs2100-cp.h +++ b/include/nuttx/timers/cs2100-cp.h @@ -43,7 +43,7 @@ #endif #ifndef CONFIG_TIMERS_CS2100CP_CLKINBW -# define CONFIG_TIMERS_CS2100CP_CLKINBW 16 +# define CONFIG_TIMERS_CS2100CP_CLKINBW 16 #endif #ifndef CONFIG_DEBUG_FEATURES diff --git a/include/nuttx/usb/audio.h b/include/nuttx/usb/audio.h index ea0bc85bd7..6d98cb5123 100644 --- a/include/nuttx/usb/audio.h +++ b/include/nuttx/usb/audio.h @@ -1583,11 +1583,11 @@ struct adc_hires_timestamp_s #undef EXTERN #if defined(__cplusplus) -# define EXTERN extern "C" +# define EXTERN extern "C" extern "C" { #else -# define EXTERN extern +# define EXTERN extern #endif #undef EXTERN diff --git a/include/nuttx/usb/cdcacm.h b/include/nuttx/usb/cdcacm.h index ca3ce822f8..cda993b697 100644 --- a/include/nuttx/usb/cdcacm.h +++ b/include/nuttx/usb/cdcacm.h @@ -284,11 +284,11 @@ #undef EXTERN #if defined(__cplusplus) -# define EXTERN extern "C" +# define EXTERN extern "C" extern "C" { #else -# define EXTERN extern +# define EXTERN extern #endif /* Reported serial events. Data is associated with CDCACM_EVENT_LINECODING diff --git a/include/nuttx/usb/hid.h b/include/nuttx/usb/hid.h index c59136dcc4..5b9f3839e0 100644 --- a/include/nuttx/usb/hid.h +++ b/include/nuttx/usb/hid.h @@ -677,11 +677,11 @@ struct usbhid_jsreport_s #undef EXTERN #if defined(__cplusplus) -# define EXTERN extern "C" +# define EXTERN extern "C" extern "C" { #else -# define EXTERN extern +# define EXTERN extern #endif #undef EXTERN diff --git a/include/nuttx/usb/hid_parser.h b/include/nuttx/usb/hid_parser.h index d71ebab3f5..180dc30102 100644 --- a/include/nuttx/usb/hid_parser.h +++ b/include/nuttx/usb/hid_parser.h @@ -233,11 +233,11 @@ typedef CODE bool (*hid_rptfilter_t)(FAR struct hid_rptitem_s *item); #undef EXTERN #if defined(__cplusplus) -# define EXTERN extern "C" +# define EXTERN extern "C" extern "C" { #else -# define EXTERN extern +# define EXTERN extern #endif /**************************************************************************** diff --git a/include/nuttx/usb/usbdev_trace.h b/include/nuttx/usb/usbdev_trace.h index 572fc9fd5e..9246c44963 100644 --- a/include/nuttx/usb/usbdev_trace.h +++ b/include/nuttx/usb/usbdev_trace.h @@ -427,11 +427,11 @@ typedef CODE int (*trprintf_t)(FAR const char *fmt, ...) printf_like(1, 2); #undef EXTERN #if defined(__cplusplus) -# define EXTERN extern "C" +# define EXTERN extern "C" extern "C" { #else -# define EXTERN extern +# define EXTERN extern #endif /* If CONFIG_USBDEV_TRACE_STRINGS is defined, then the USB class driver and diff --git a/include/nuttx/usb/usbhost_trace.h b/include/nuttx/usb/usbhost_trace.h index 53d7c3342e..ceb4f8b531 100644 --- a/include/nuttx/usb/usbhost_trace.h +++ b/include/nuttx/usb/usbhost_trace.h @@ -82,11 +82,11 @@ typedef CODE int (*usbhost_trcallback_t)(FAR uint32_t trace, FAR void *arg); #undef EXTERN #if defined(__cplusplus) -# define EXTERN extern "C" +# define EXTERN extern "C" extern "C" { #else -# define EXTERN extern +# define EXTERN extern #endif /**************************************************************************** diff --git a/include/nuttx/video/fb.h b/include/nuttx/video/fb.h index 770e2c9069..e93042c57a 100644 --- a/include/nuttx/video/fb.h +++ b/include/nuttx/video/fb.h @@ -758,7 +758,7 @@ struct fb_vtable_s int (*setarea)(FAR struct fb_vtable_s *vtable, FAR const struct fb_overlayinfo_s *oinfo); -# ifdef CONFIG_FB_OVERLAY_BLIT +# ifdef CONFIG_FB_OVERLAY_BLIT /* The following are provided only if the video hardware supports * blit operation between overlays. */ @@ -772,7 +772,7 @@ struct fb_vtable_s int (*blend)(FAR struct fb_vtable_s *vtable, FAR const struct fb_overlayblend_s *blend); -# endif +# endif #endif /* Pan display for multiple buffers. */ diff --git a/include/pwd.h b/include/pwd.h index 216ddbd04c..aff3613749 100644 --- a/include/pwd.h +++ b/include/pwd.h @@ -35,9 +35,9 @@ ****************************************************************************/ #ifdef CONFIG_LIBC_PASSWD_LINESIZE -# define NSS_BUFLEN_PASSWD CONFIG_LIBC_PASSWD_LINESIZE +# define NSS_BUFLEN_PASSWD CONFIG_LIBC_PASSWD_LINESIZE #else -# define NSS_BUFLEN_PASSWD 256 +# define NSS_BUFLEN_PASSWD 256 #endif /**************************************************************************** diff --git a/include/semaphore.h b/include/semaphore.h index f3f1087972..93a5a46120 100644 --- a/include/semaphore.h +++ b/include/semaphore.h @@ -110,11 +110,11 @@ struct sem_s dq_queue_t waitlist; #ifdef CONFIG_PRIORITY_INHERITANCE -# if CONFIG_SEM_PREALLOCHOLDERS > 0 +# if CONFIG_SEM_PREALLOCHOLDERS > 0 FAR struct semholder_s *hhead; /* List of holders of semaphore counts */ -# else +# else struct semholder_s holder[2]; /* Slot for old and new holder */ -# endif +# endif #endif }; @@ -123,25 +123,26 @@ typedef struct sem_s sem_t; /* Initializers */ #ifdef CONFIG_PRIORITY_INHERITANCE -# if CONFIG_SEM_PREALLOCHOLDERS > 0 +# if CONFIG_SEM_PREALLOCHOLDERS > 0 /* semcount, flags, waitlist, hhead */ -# define SEM_INITIALIZER(c) \ - {(c), 0, SEM_WAITLIST_INITIALIZER, NULL} -# else +# define SEM_INITIALIZER(c) \ + {(c), 0, SEM_WAITLIST_INITIALIZER, NULL} +# else /* semcount, flags, waitlist, holder[2] */ -# define SEM_INITIALIZER(c) \ - {(c), 0, SEM_WAITLIST_INITIALIZER, {SEMHOLDER_INITIALIZER, SEMHOLDER_INITIALIZER}} -# endif +# define SEM_INITIALIZER(c) \ + {(c), 0, SEM_WAITLIST_INITIALIZER, \ + {SEMHOLDER_INITIALIZER, SEMHOLDER_INITIALIZER}} +# endif #else /* semcount, flags, waitlist */ # define SEM_INITIALIZER(c) \ - {(c), 0, SEM_WAITLIST_INITIALIZER} + {(c), 0, SEM_WAITLIST_INITIALIZER} #endif -# define SEM_WAITLIST(sem) (&((sem)->waitlist)) +#define SEM_WAITLIST(sem) (&((sem)->waitlist)) /**************************************************************************** * Public Data diff --git a/include/time.h b/include/time.h index 5de07b6ace..6f08b4a02b 100644 --- a/include/time.h +++ b/include/time.h @@ -46,11 +46,11 @@ */ #ifdef CONFIG_USEC_PER_TICK -# define CLK_TCK (1000000/CONFIG_USEC_PER_TICK) -# define CLOCKS_PER_SEC (1000000/CONFIG_USEC_PER_TICK) +# define CLK_TCK (1000000/CONFIG_USEC_PER_TICK) +# define CLOCKS_PER_SEC (1000000/CONFIG_USEC_PER_TICK) #else -# define CLK_TCK (100) -# define CLOCKS_PER_SEC (100) +# define CLK_TCK (100) +# define CLOCKS_PER_SEC (100) #endif /* CLOCK_REALTIME refers to the standard time source. For most diff --git a/libs/libc/dlfcn/lib_dlopen.c b/libs/libc/dlfcn/lib_dlopen.c index fb1a48f3c3..592e6f5b69 100644 --- a/libs/libc/dlfcn/lib_dlopen.c +++ b/libs/libc/dlfcn/lib_dlopen.c @@ -100,7 +100,7 @@ static void dldump_loadinfo(FAR struct mod_loadinfo_s *loadinfo) } } #else -# define dldump_loadinfo(i) +# define dldump_loadinfo(i) #endif #endif @@ -117,7 +117,7 @@ static void dldump_initializer(mod_initializer_t initializer, MIN(loadinfo->textsize - loadinfo->ehdr.e_entry, 512)); } #else -# define dldump_initializer(b,l) +# define dldump_initializer(b,l) #endif #endif diff --git a/libs/libc/libc.h b/libs/libc/libc.h index cb869043ee..2073233b63 100644 --- a/libs/libc/libc.h +++ b/libs/libc/libc.h @@ -50,7 +50,7 @@ */ #ifndef CONFIG_LIBC_HOMEDIR -# define CONFIG_LIBC_HOMEDIR "/" +# define CONFIG_LIBC_HOMEDIR "/" #endif #define LIB_BUFLEN_UNKNOWN INT_MAX diff --git a/libs/libc/machine/arm/arm_asm.h b/libs/libc/machine/arm/arm_asm.h index a96dddd55c..2142f0cb53 100644 --- a/libs/libc/machine/arm/arm_asm.h +++ b/libs/libc/machine/arm/arm_asm.h @@ -34,32 +34,32 @@ #include "arm-acle-compat.h" #if __ARM_ARCH >= 7 && defined (__ARM_ARCH_ISA_ARM) -# define _ISA_ARM_7 +# define _ISA_ARM_7 #endif #if __ARM_ARCH >= 6 && defined (__ARM_ARCH_ISA_ARM) -# define _ISA_ARM_6 +# define _ISA_ARM_6 #endif #if __ARM_ARCH >= 5 -# define _ISA_ARM_5 +# define _ISA_ARM_5 #endif #if __ARM_ARCH >= 4 && __ARM_ARCH_ISA_THUMB >= 1 -# define _ISA_ARM_4T +# define _ISA_ARM_4T #endif #if __ARM_ARCH >= 4 && __ARM_ARCH_ISA_THUMB == 0 -# define _ISA_ARM_4 +# define _ISA_ARM_4 #endif #if __ARM_ARCH_ISA_THUMB >= 2 -# define _ISA_THUMB_2 +# define _ISA_THUMB_2 #endif #if __ARM_ARCH_ISA_THUMB >= 1 -# define _ISA_THUMB_1 +# define _ISA_THUMB_1 #endif /* Check whether leaf function PAC signing has been requested in the @@ -67,10 +67,10 @@ #define LEAF_PROTECT_BIT 2 #ifdef __ARM_FEATURE_PAC_DEFAULT -# define HAVE_PAC_LEAF \ +# define HAVE_PAC_LEAF \ ((__ARM_FEATURE_PAC_DEFAULT & (1 << LEAF_PROTECT_BIT)) && 1) #else -# define HAVE_PAC_LEAF 0 +# define HAVE_PAC_LEAF 0 #endif /* Provide default parameters for PAC-code handling in leaf-functions. */ @@ -80,7 +80,7 @@ # endif #else /* !HAVE_PAC_LEAF */ # undef PAC_LEAF_PUSH_IP -# define PAC_LEAF_PUSH_IP 0 +# define PAC_LEAF_PUSH_IP 0 #endif /* HAVE_PAC_LEAF */ #define STACK_ALIGN_ENFORCE 0 diff --git a/libs/libc/modlib/modlib_init.c b/libs/libc/modlib/modlib_init.c index 1588c42ed8..d26efca8c1 100644 --- a/libs/libc/modlib/modlib_init.c +++ b/libs/libc/modlib/modlib_init.c @@ -50,9 +50,9 @@ #endif #ifdef CONFIG_MODLIB_DUMPBUFFER -# define modlib_dumpbuffer(m,b,n) binfodumpbuffer(m,b,n) +# define modlib_dumpbuffer(m,b,n) binfodumpbuffer(m,b,n) #else -# define modlib_dumpbuffer(m,b,n) +# define modlib_dumpbuffer(m,b,n) #endif /**************************************************************************** diff --git a/libs/libc/stdio/lib_perror.c b/libs/libc/stdio/lib_perror.c index 6e4b9ce543..60e74e1eb1 100644 --- a/libs/libc/stdio/lib_perror.c +++ b/libs/libc/stdio/lib_perror.c @@ -59,16 +59,16 @@ void perror(FAR const char *s) /* If strerror() is not enabled, then just print the error number */ #ifdef CONFIG_LIBC_STRERROR -# ifdef CONFIG_FILE_STREAM +# ifdef CONFIG_FILE_STREAM fprintf(PERROR_STREAM, "%s: %s\n", s, strerror(get_errno())); -# else +# else dprintf(PERROR_FILENO, "%s: %s\n", s, strerror(get_errno())); -# endif +# endif #else -# ifdef CONFIG_FILE_STREAM +# ifdef CONFIG_FILE_STREAM fprintf(PERROR_STREAM, "%s: Error %d\n", s, get_errno()); -# else +# else dprintf(PERROR_FILENO, "%s: Error %d\n", s, get_errno()); -# endif +# endif #endif } diff --git a/libs/libm/newlib/include/complex.h b/libs/libm/newlib/include/complex.h index 2dc80aae3f..5b6c398e94 100644 --- a/libs/libm/newlib/include/complex.h +++ b/libs/libm/newlib/include/complex.h @@ -178,9 +178,9 @@ long double creall(long double complex); double complex clog10(double complex); float complex clog10f(float complex); -# if defined(__CYGWIN__) +# if defined(__CYGWIN__) long double complex clog10l(long double complex); -# endif +# endif #ifdef __cplusplus } diff --git a/libs/libm/newlib/include/machine/ieeefp.h b/libs/libm/newlib/include/machine/ieeefp.h index bca1481d34..9739b97f5f 100644 --- a/libs/libm/newlib/include/machine/ieeefp.h +++ b/libs/libm/newlib/include/machine/ieeefp.h @@ -103,13 +103,13 @@ # define __OBSOLETE_MATH_DEFAULT 0 # endif #else -# define __IEEE_BIG_ENDIAN +# define __IEEE_BIG_ENDIAN # ifdef __ARMEL__ # define __IEEE_BYTES_LITTLE_ENDIAN # endif #endif #ifndef __SOFTFP__ -# define _SUPPORTS_ERREXCEPT +# define _SUPPORTS_ERREXCEPT #endif /* As per ISO/IEC TS 18661 '__FLT_EVAL_METHOD__' will be defined to 16 * (if compiling with +fp16 support) so it can't be used by math.h to @@ -129,7 +129,7 @@ #endif #define __OBSOLETE_MATH_DEFAULT 0 #ifdef __ARM_FP -# define _SUPPORTS_ERREXCEPT +# define _SUPPORTS_ERREXCEPT #endif /* As per ISO/IEC TS 18661 '__FLT_EVAL_METHOD__' will be defined to 16 * (if compiling with +fp16 support) so it can't be used by math.h to @@ -193,7 +193,7 @@ #if defined(__mc68hc11__) || defined(__mc68hc12__) || defined(__mc68hc1x__) #define __IEEE_BIG_ENDIAN #ifdef __HAVE_SHORT_DOUBLE__ -# define _DOUBLE_IS_32BITS +# define _DOUBLE_IS_32BITS #endif #endif @@ -230,7 +230,7 @@ #ifdef __i386__ #define __IEEE_LITTLE_ENDIAN -# define _SUPPORTS_ERREXCEPT +# define _SUPPORTS_ERREXCEPT #endif #ifdef __riscv @@ -240,12 +240,12 @@ #define __IEEE_LITTLE_ENDIAN #endif #ifdef __riscv_flen -# define _SUPPORTS_ERREXCEPT +# define _SUPPORTS_ERREXCEPT #endif #if __riscv_flen == 64 -# define __OBSOLETE_MATH_DEFAULT 0 +# define __OBSOLETE_MATH_DEFAULT 0 #else -# define __OBSOLETE_MATH_DEFAULT 1 +# define __OBSOLETE_MATH_DEFAULT 1 #endif #endif @@ -448,7 +448,7 @@ #ifdef __x86_64__ #define __IEEE_LITTLE_ENDIAN -# define _SUPPORTS_ERREXCEPT +# define _SUPPORTS_ERREXCEPT #endif #ifdef __mep__ diff --git a/libs/libm/newlib/include/math.h b/libs/libm/newlib/include/math.h index df4c17c04c..be308410ca 100644 --- a/libs/libm/newlib/include/math.h +++ b/libs/libm/newlib/include/math.h @@ -230,17 +230,17 @@ extern int isnan (double); #define FP_NORMAL 4 #ifndef FP_ILOGB0 -# define FP_ILOGB0 (-__INT_MAX__) +# define FP_ILOGB0 (-__INT_MAX__) #endif #ifndef FP_ILOGBNAN -# define FP_ILOGBNAN __INT_MAX__ +# define FP_ILOGBNAN __INT_MAX__ #endif #ifndef MATH_ERRNO -# define MATH_ERRNO 1 +# define MATH_ERRNO 1 #endif #ifndef MATH_ERREXCEPT -# define MATH_ERREXCEPT 2 +# define MATH_ERREXCEPT 2 #endif #ifndef math_errhandling # ifdef _IEEE_LIBM @@ -253,7 +253,7 @@ extern int isnan (double); # else # define _MATH_ERRHANDLING_ERREXCEPT 0 # endif -# define math_errhandling (_MATH_ERRHANDLING_ERRNO | _MATH_ERRHANDLING_ERREXCEPT) +# define math_errhandling (_MATH_ERRHANDLING_ERRNO | _MATH_ERRHANDLING_ERREXCEPT) #endif extern int __isinff (float); diff --git a/libs/libnx/nxfonts/nxfonts.h b/libs/libnx/nxfonts/nxfonts.h index ff73816407..3caddf8967 100644 --- a/libs/libnx/nxfonts/nxfonts.h +++ b/libs/libnx/nxfonts/nxfonts.h @@ -45,11 +45,11 @@ #undef EXTERN #if defined(__cplusplus) -# define EXTERN extern "C" +# define EXTERN extern "C" extern "C" { #else -# define EXTERN extern +# define EXTERN extern #endif EXTERN struct nx_fontset_s g_7bitfonts; diff --git a/libs/libnx/nxtk/nxtk.h b/libs/libnx/nxtk/nxtk.h index 012b00bb6e..0c63f13eb8 100644 --- a/libs/libnx/nxtk/nxtk.h +++ b/libs/libnx/nxtk/nxtk.h @@ -69,11 +69,11 @@ struct nxtk_framedwindow_s #undef EXTERN #if defined(__cplusplus) -# define EXTERN extern "C" +# define EXTERN extern "C" extern "C" { #else -# define EXTERN extern +# define EXTERN extern #endif /* That is the callback for the framed window */ diff --git a/mm/mm_heap/mm.h b/mm/mm_heap/mm.h index c787ace6af..4cbfdf7f02 100644 --- a/mm/mm_heap/mm.h +++ b/mm/mm_heap/mm.h @@ -127,9 +127,9 @@ #define MM_PREVFREE_BIT 0x2 #define MM_MASK_BIT (MM_ALLOC_BIT | MM_PREVFREE_BIT) #ifdef CONFIG_MM_SMALL -# define MMSIZE_MAX UINT16_MAX +# define MMSIZE_MAX UINT16_MAX #else -# define MMSIZE_MAX UINT32_MAX +# define MMSIZE_MAX UINT32_MAX #endif /* What is the size of the allocnode? */ diff --git a/mm/mm_heap/mm_foreach.c b/mm/mm_heap/mm_foreach.c index 23255bf8a5..b529bfddbd 100644 --- a/mm/mm_heap/mm_foreach.c +++ b/mm/mm_heap/mm_foreach.c @@ -52,7 +52,7 @@ void mm_foreach(FAR struct mm_heap_s *heap, mm_node_handler_t handler, #if CONFIG_MM_REGIONS > 1 int region; #else -# define region 0 +# define region 0 #endif DEBUGASSERT(handler); diff --git a/mm/mm_heap/mm_initialize.c b/mm/mm_heap/mm_initialize.c index 2bf2f267a8..3135f55e1c 100644 --- a/mm/mm_heap/mm_initialize.c +++ b/mm/mm_heap/mm_initialize.c @@ -117,7 +117,7 @@ void mm_addregion(FAR struct mm_heap_s *heap, FAR void *heapstart, } #else -# define IDX 0 +# define IDX 0 #endif #if defined(CONFIG_MM_SMALL) && !defined(CONFIG_SMALL_MEMORY) diff --git a/mm/mm_heap/mm_mallinfo.c b/mm/mm_heap/mm_mallinfo.c index 78f52f4cdb..6a6b1c3407 100644 --- a/mm/mm_heap/mm_mallinfo.c +++ b/mm/mm_heap/mm_mallinfo.c @@ -120,7 +120,7 @@ int mm_mallinfo(FAR struct mm_heap_s *heap, FAR struct mallinfo *info) #if CONFIG_MM_REGIONS > 1 int region = heap->mm_nregions; #else -# define region 1 +# define region 1 #endif DEBUGASSERT(info); diff --git a/mm/tlsf/mm_tlsf.c b/mm/tlsf/mm_tlsf.c index 36059c17f3..639e877b42 100644 --- a/mm/tlsf/mm_tlsf.c +++ b/mm/tlsf/mm_tlsf.c @@ -479,7 +479,7 @@ void mm_addregion(FAR struct mm_heap_s *heap, FAR void *heapstart, } #else -# define idx 0 +# define idx 0 #endif /* Register to KASan for access check */ @@ -575,7 +575,7 @@ void mm_checkcorruption(FAR struct mm_heap_s *heap) #if CONFIG_MM_REGIONS > 1 int region; #else -# define region 0 +# define region 0 #endif /* Visit each region */ @@ -849,7 +849,7 @@ int mm_mallinfo(FAR struct mm_heap_s *heap, FAR struct mallinfo *info) #if CONFIG_MM_REGIONS > 1 int region; #else -# define region 0 +# define region 0 #endif DEBUGASSERT(info); @@ -926,7 +926,7 @@ void mm_memdump(FAR struct mm_heap_s *heap, pid_t pid) #if CONFIG_MM_REGIONS > 1 int region; #else -# define region 0 +# define region 0 #endif struct mallinfo_task info; diff --git a/net/arp/arp.h b/net/arp/arp.h index b642c41ef2..7e2c9887c2 100644 --- a/net/arp/arp.h +++ b/net/arp/arp.h @@ -208,7 +208,7 @@ void arp_format(FAR struct net_driver_s *dev, in_addr_t ipaddr); #ifdef CONFIG_NET_ARP_IPIN void arp_ipin(FAR struct net_driver_s *dev); #else -# define arp_ipin(dev) +# define arp_ipin(dev) #endif /**************************************************************************** diff --git a/net/can/can.h b/net/can/can.h index afab38fedc..7c86473729 100644 --- a/net/can/can.h +++ b/net/can/can.h @@ -101,14 +101,14 @@ struct can_conn_s #ifdef CONFIG_NET_CANPROTO_OPTIONS int32_t loopback; int32_t recv_own_msgs; -#ifdef CONFIG_NET_CAN_CANFD +# ifdef CONFIG_NET_CAN_CANFD int32_t fd_frames; -#endif +# endif struct can_filter filters[CONFIG_NET_CAN_RAW_FILTER_MAX]; int32_t filter_count; -# ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE +# ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE int32_t tx_deadline; -# endif +# endif #endif #ifdef CONFIG_NET_TIMESTAMP int32_t timestamp; /* Socket timestamp enabled/disabled */ diff --git a/net/devif/devif_poll.c b/net/devif/devif_poll.c index 24f0b87be1..f4492c2cfb 100644 --- a/net/devif/devif_poll.c +++ b/net/devif/devif_poll.c @@ -624,7 +624,7 @@ static inline int devif_poll_tcp_connections(FAR struct net_driver_s *dev, return bstop; } #else -# define devif_poll_tcp_connections(dev, callback) (0) +# define devif_poll_tcp_connections(dev, callback) (0) #endif /**************************************************************************** diff --git a/sched/module/mod_insmod.c b/sched/module/mod_insmod.c index 44023c3294..7faff98b96 100644 --- a/sched/module/mod_insmod.c +++ b/sched/module/mod_insmod.c @@ -102,7 +102,7 @@ static void mod_dumploadinfo(FAR struct mod_loadinfo_s *loadinfo) } } #else -# define mod_dumploadinfo(i) +# define mod_dumploadinfo(i) #endif /**************************************************************************** @@ -117,7 +117,7 @@ static void mod_dumpinitializer(mod_initializer_t initializer, MIN(loadinfo->textsize - loadinfo->ehdr.e_entry, 512)); } #else -# define mod_dumpinitializer(b,l) +# define mod_dumpinitializer(b,l) #endif /**************************************************************************** diff --git a/sched/mqueue/mqueue.h b/sched/mqueue/mqueue.h index 9011a8d7ce..a2325dbd7a 100644 --- a/sched/mqueue/mqueue.h +++ b/sched/mqueue/mqueue.h @@ -118,7 +118,7 @@ void nxmq_wait_irq(FAR struct tcb_s *wtcb, int errcode); #ifdef CONFIG_DEBUG_FEATURES int nxmq_verify_receive(FAR struct file *mq, FAR char *msg, size_t msglen); #else -# define nxmq_verify_receive(msgq, msg, msglen) OK +# define nxmq_verify_receive(msgq, msg, msglen) OK #endif int nxmq_wait_receive(FAR struct mqueue_inode_s *msgq, int oflags, FAR struct mqueue_msg_s **rcvmsg); @@ -132,7 +132,7 @@ ssize_t nxmq_do_receive(FAR struct mqueue_inode_s *msgq, int nxmq_verify_send(FAR struct file *mq, FAR const char *msg, size_t msglen, unsigned int prio); #else -# define nxmq_verify_send(mq, msg, msglen, prio) OK +# define nxmq_verify_send(mq, msg, msglen, prio) OK #endif FAR struct mqueue_msg_s *nxmq_alloc_msg(void); int nxmq_wait_send(FAR struct mqueue_inode_s *msgq, int oflags); diff --git a/wireless/ieee802154/mac802154_netdev.c b/wireless/ieee802154/mac802154_netdev.c index 494ba49ad8..ec9984c6b5 100644 --- a/wireless/ieee802154/mac802154_netdev.c +++ b/wireless/ieee802154/mac802154_netdev.c @@ -79,7 +79,7 @@ */ #ifndef CONFIG_IEEE802154_NETDEV_NINTERFACES -# define CONFIG_IEEE802154_NETDEV_NINTERFACES 1 +# define CONFIG_IEEE802154_NETDEV_NINTERFACES 1 #endif /* Preferred address size */