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Indent the define statement by two spaces

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follow the code style convention

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2023-05-20 06:32:34 +08:00 committed by Alan Carvalho de Assis
parent ae1fd83a46
commit 7990f90915
390 changed files with 4060 additions and 4063 deletions
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4
arch/arm/src/arm/arm_initialstate.c
View File

@ -141,9 +141,9 @@ void up_initial_state(struct tcb_s *tcb)
/* Enable or disable interrupts, based on user configuration */
# ifdef CONFIG_SUPPRESS_INTERRUPTS
#ifdef CONFIG_SUPPRESS_INTERRUPTS
cpsr |= PSR_I_BIT;
# endif
#endif
#ifdef CONFIG_ARM_THUMB
cpsr |= PSR_T_BIT;

6
arch/arm/src/armv6-m/arm_svcall.c
View File

@ -446,14 +446,14 @@ int arm_svcall(int irq, void *context, void *arg)
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
#ifdef CONFIG_BUILD_PROTECTED
# ifdef CONFIG_BUILD_PROTECTED
svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
CURRENT_REGS[REG_EXC_RETURN]);
#else
# else
svcinfo(" PSR: %08x PRIMASK: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
#endif
# endif
}
# ifdef CONFIG_DEBUG_SVCALL
else

2
arch/arm/src/gd32f4/gd32f4xx_enet.c
View File

@ -3383,7 +3383,7 @@ static inline void gd32_enet_gpio_config(struct gd32_enet_mac_s *priv)
gd32_gpio_config(GPIO_ENET_RMII_TXD0);
gd32_gpio_config(GPIO_ENET_RMII_TXD1);
#endif
# endif
#endif
#ifdef CONFIG_GD32F4_ENET_PTP

4
arch/arm/src/imxrt/imxrt_flexcan.c
View File

@ -821,10 +821,10 @@ static void imxrt_receive(struct imxrt_driver_s *priv,
uint32_t mbi;
uint32_t mbj;
struct mb_s *rf;
# ifdef CONFIG_NET_CAN_CANFD
#ifdef CONFIG_NET_CAN_CANFD
uint32_t *frame_data_word;
uint32_t i;
# endif
#endif
uint32_t f;
while ((f = flags) != 0)

300
arch/arm/src/imxrt/imxrt_serial.c
View File

@ -804,15 +804,15 @@ static struct imxrt_uart_s g_lpuart1priv =
.size = CONFIG_LPUART1_TXBUFSIZE,
.buffer = g_lpuart1txbuffer,
},
#if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA)
# if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA)
.ops = &g_lpuart_rxtxdma_ops,
#elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA)
# elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA)
.ops = &g_lpuart_rxdma_ops,
#elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA)
# elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA)
.ops = &g_lpuart_txdma_ops,
#else
# else
.ops = &g_lpuart_ops,
#endif
# endif
.priv = &g_lpuart1priv,
},
@ -822,38 +822,38 @@ static struct imxrt_uart_s g_lpuart1priv =
.parity = CONFIG_LPUART1_PARITY,
.bits = CONFIG_LPUART1_BITS,
.stopbits2 = CONFIG_LPUART1_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
.iflow = 1,
#endif
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART1_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART1_TX,
#endif
# endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART1_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART1_TXDMA
# ifdef CONFIG_LPUART1_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART1_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART1_RXDMA
# endif
# ifdef CONFIG_LPUART1_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART1_RX,
.rxfifo = g_lpuart1rxfifo,
#endif
# endif
};
#endif
@ -892,37 +892,37 @@ static struct imxrt_uart_s g_lpuart2priv =
.parity = CONFIG_LPUART2_PARITY,
.bits = CONFIG_LPUART2_BITS,
.stopbits2 = CONFIG_LPUART2_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART2_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)
.iflow = 1,
#endif
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART2_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART2_TX,
#endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# endif
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART2_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART2_TXDMA
# ifdef CONFIG_LPUART2_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART2_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART2_RXDMA
# endif
# ifdef CONFIG_LPUART2_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART2_RX,
.rxfifo = g_lpuart2rxfifo,
#endif
# endif
};
#endif
@ -941,15 +941,15 @@ static struct imxrt_uart_s g_lpuart3priv =
.size = CONFIG_LPUART3_TXBUFSIZE,
.buffer = g_lpuart3txbuffer,
},
#if defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA)
# if defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA)
.ops = &g_lpuart_rxtxdma_ops,
#elif defined(CONFIG_LPUART3_RXDMA) && !defined(CONFIG_LPUART3_TXDMA)
# elif defined(CONFIG_LPUART3_RXDMA) && !defined(CONFIG_LPUART3_TXDMA)
.ops = &g_lpuart_rxdma_ops,
#elif !defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA)
# elif !defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA)
.ops = &g_lpuart_txdma_ops,
#else
# else
.ops = &g_lpuart_ops,
#endif
# endif
.priv = &g_lpuart3priv,
},
@ -959,37 +959,37 @@ static struct imxrt_uart_s g_lpuart3priv =
.parity = CONFIG_LPUART3_PARITY,
.bits = CONFIG_LPUART3_BITS,
.stopbits2 = CONFIG_LPUART3_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART3_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART3_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART3_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)
.iflow = 1,
#endif
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART3_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART3_TX,
#endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# endif
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART3_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART3_TXDMA
# ifdef CONFIG_LPUART3_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART3_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART3_RXDMA
# endif
# ifdef CONFIG_LPUART3_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART3_RX,
.rxfifo = g_lpuart3rxfifo,
#endif
# endif
};
#endif
@ -1026,37 +1026,37 @@ static struct imxrt_uart_s g_lpuart4priv =
.parity = CONFIG_LPUART4_PARITY,
.bits = CONFIG_LPUART4_BITS,
.stopbits2 = CONFIG_LPUART4_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART4_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART4_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART4_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)
.iflow = 1,
#endif
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART4_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART4_TX,
#endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# endif
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART4_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART4_TXDMA
# ifdef CONFIG_LPUART4_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART4_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART4_RXDMA
# endif
# ifdef CONFIG_LPUART4_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART4_RX,
.rxfifo = g_lpuart4rxfifo,
#endif
# endif
};
#endif
@ -1075,15 +1075,15 @@ static struct imxrt_uart_s g_lpuart5priv =
.size = CONFIG_LPUART5_TXBUFSIZE,
.buffer = g_lpuart5txbuffer,
},
#if defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA)
# if defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA)
.ops = &g_lpuart_rxtxdma_ops,
#elif defined(CONFIG_LPUART5_RXDMA) && !defined(CONFIG_LPUART5_TXDMA)
# elif defined(CONFIG_LPUART5_RXDMA) && !defined(CONFIG_LPUART5_TXDMA)
.ops = &g_lpuart_rxdma_ops,
#elif !defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA)
# elif !defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA)
.ops = &g_lpuart_txdma_ops,
#else
# else
.ops = &g_lpuart_ops,
#endif
# endif
.priv = &g_lpuart5priv,
},
@ -1093,37 +1093,37 @@ static struct imxrt_uart_s g_lpuart5priv =
.parity = CONFIG_LPUART5_PARITY,
.bits = CONFIG_LPUART5_BITS,
.stopbits2 = CONFIG_LPUART5_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART5_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART5_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART5_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)
.iflow = 1,
#endif
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART5_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART5_TX,
#endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# endif
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART5_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART5_TXDMA
# ifdef CONFIG_LPUART5_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART5_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART5_RXDMA
# endif
# ifdef CONFIG_LPUART5_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART5_RX,
.rxfifo = g_lpuart5rxfifo,
#endif
# endif
};
#endif
@ -1142,15 +1142,15 @@ static struct imxrt_uart_s g_lpuart6priv =
.size = CONFIG_LPUART6_TXBUFSIZE,
.buffer = g_lpuart6txbuffer,
},
#if defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA)
# if defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA)
.ops = &g_lpuart_rxtxdma_ops,
#elif defined(CONFIG_LPUART6_RXDMA) && !defined(CONFIG_LPUART6_TXDMA)
# elif defined(CONFIG_LPUART6_RXDMA) && !defined(CONFIG_LPUART6_TXDMA)
.ops = &g_lpuart_rxdma_ops,
#elif !defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA)
# elif !defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA)
.ops = &g_lpuart_txdma_ops,
#else
# else
.ops = &g_lpuart_ops,
#endif
# endif
.priv = &g_lpuart6priv,
},
@ -1160,37 +1160,37 @@ static struct imxrt_uart_s g_lpuart6priv =
.parity = CONFIG_LPUART6_PARITY,
.bits = CONFIG_LPUART6_BITS,
.stopbits2 = CONFIG_LPUART6_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART6_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART6_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART6_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)
.iflow = 1,
#endif
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART6_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART6_TX,
#endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# endif
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART6_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART6_TXDMA
# ifdef CONFIG_LPUART6_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART6_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART6_RXDMA
# endif
# ifdef CONFIG_LPUART6_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART6_RX,
.rxfifo = g_lpuart6rxfifo,
#endif
# endif
};
#endif
@ -1209,15 +1209,15 @@ static struct imxrt_uart_s g_lpuart7priv =
.size = CONFIG_LPUART7_TXBUFSIZE,
.buffer = g_lpuart7txbuffer,
},
#if defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA)
# if defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA)
.ops = &g_lpuart_rxtxdma_ops,
#elif defined(CONFIG_LPUART7_RXDMA) && !defined(CONFIG_LPUART7_TXDMA)
# elif defined(CONFIG_LPUART7_RXDMA) && !defined(CONFIG_LPUART7_TXDMA)
.ops = &g_lpuart_rxdma_ops,
#elif !defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA)
# elif !defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA)
.ops = &g_lpuart_txdma_ops,
#else
# else
.ops = &g_lpuart_ops,
#endif
# endif
.priv = &g_lpuart7priv,
},
@ -1227,37 +1227,37 @@ static struct imxrt_uart_s g_lpuart7priv =
.parity = CONFIG_LPUART7_PARITY,
.bits = CONFIG_LPUART7_BITS,
.stopbits2 = CONFIG_LPUART7_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART7_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART7_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART7_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)
.iflow = 1,
#endif
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART7_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART7_TX,
#endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# endif
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART7_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART7_TXDMA
# ifdef CONFIG_LPUART7_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART7_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART7_RXDMA
# endif
# ifdef CONFIG_LPUART7_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART7_RX,
.rxfifo = g_lpuart7rxfifo,
#endif
# endif
};
#endif
@ -1276,15 +1276,15 @@ static struct imxrt_uart_s g_lpuart8priv =
.size = CONFIG_LPUART8_TXBUFSIZE,
.buffer = g_lpuart8txbuffer,
},
#if defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA)
# if defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA)
.ops = &g_lpuart_rxtxdma_ops,
#elif defined(CONFIG_LPUART8_RXDMA) && !defined(CONFIG_LPUART8_TXDMA)
# elif defined(CONFIG_LPUART8_RXDMA) && !defined(CONFIG_LPUART8_TXDMA)
.ops = &g_lpuart_rxdma_ops,
#elif !defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA)
# elif !defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA)
.ops = &g_lpuart_txdma_ops,
#else
# else
.ops = &g_lpuart_ops,
#endif
# endif
.priv = &g_lpuart8priv,
},
@ -1294,37 +1294,37 @@ static struct imxrt_uart_s g_lpuart8priv =
.parity = CONFIG_LPUART8_PARITY,
.bits = CONFIG_LPUART8_BITS,
.stopbits2 = CONFIG_LPUART8_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART8_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART8_OFLOWCONTROL)
.oflow = 1,
.cts_gpio = GPIO_LPUART8_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)
.iflow = 1,
#endif
# endif
# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) \
|| (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)))
.rts_gpio = GPIO_LPUART8_RTS,
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
# endif
# ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
.tx_gpio = GPIO_LPUART8_TX,
#endif
#if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
# endif
# if (((defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL))) \
&& defined(CONFIG_LPUART8_INVERTIFLOWCONTROL))
.inviflow = 1,
#endif
# endif
#if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)
# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)
.rs485mode = 1,
#endif
# endif
#ifdef CONFIG_LPUART8_TXDMA
# ifdef CONFIG_LPUART8_TXDMA
.dma_txreqsrc = IMXRT_DMACHAN_LPUART8_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_LPUART8_RXDMA
# endif
# ifdef CONFIG_LPUART8_RXDMA
.dma_rxreqsrc = IMXRT_DMACHAN_LPUART8_RX,
.rxfifo = g_lpuart8rxfifo,
#endif
# endif
};
#endif

2
arch/arm/src/kinetis/hardware/kinetis_flexbus.h
View File

@ -68,8 +68,6 @@
/* Register Addresses *******************************************************/
# define 0x4000c000 /* FlexBus */
#define KINETIS_FB_CS_BASE(n) (KINETIS_FLEXBUSC_BASE+KINETIS_FB_CS_OFFSET(n))
#define KINETIS_FB_CSAR(n) (KINETIS_FB_CS_BASE(n)+KINETIS_FB_CSAR_OFFSET)
#define KINETIS_FB_CSMR(n) (KINETIS_FB_CS_BASE(n)+KINETIS_FB_CSMR_OFFSET)

4
arch/arm/src/kinetis/hardware/kinetis_k40memorymap.h
View File

@ -46,10 +46,10 @@
#define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read-
* only data (Includes exception
* vectors in first 1024 bytes) */
# if !defined(KINETIS_FLEXMEM_SIZE)
#if !defined(KINETIS_FLEXMEM_SIZE)
# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */
# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */
# endif
#endif
#define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM
* (ICODE/DCODE) */
#define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband

132
arch/arm/src/kinetis/kinetis_serial.c
View File

@ -464,25 +464,25 @@ static struct up_dev_s g_uart0priv =
.uartbase = KINETIS_UART0_BASE,
.clock = BOARD_CORECLK_FREQ,
.baud = CONFIG_UART0_BAUD,
#ifdef CONFIG_DEBUG_FEATURES
# ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART0E,
#endif
# endif
.irqs = KINETIS_IRQ_UART0S,
.parity = CONFIG_UART0_PARITY,
.bits = CONFIG_UART0_BITS,
.stop2 = CONFIG_UART0_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART0_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART0_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART0_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART0_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART0_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART0_RTS,
#endif
#ifdef CONFIG_KINETIS_UART0_RXDMA
# endif
# ifdef CONFIG_KINETIS_UART0_RXDMA
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART0_RX,
.rxfifo = g_uart0rxfifo,
#endif
# endif
};
static uart_dev_t g_uart0port =
@ -497,11 +497,11 @@ static uart_dev_t g_uart0port =
.size = CONFIG_UART0_TXBUFSIZE,
.buffer = g_uart0txbuffer,
},
#ifdef CONFIG_KINETIS_UART0_RXDMA
# ifdef CONFIG_KINETIS_UART0_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart0priv,
};
#endif
@ -514,25 +514,25 @@ static struct up_dev_s g_uart1priv =
.uartbase = KINETIS_UART1_BASE,
.clock = BOARD_CORECLK_FREQ,
.baud = CONFIG_UART1_BAUD,
#ifdef CONFIG_DEBUG_FEATURES
# ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART1E,
#endif
# endif
.irqs = KINETIS_IRQ_UART1S,
.parity = CONFIG_UART1_PARITY,
.bits = CONFIG_UART1_BITS,
.stop2 = CONFIG_UART1_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART1_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART1_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART1_RTS,
#endif
#ifdef CONFIG_KINETIS_UART1_RXDMA
# endif
# ifdef CONFIG_KINETIS_UART1_RXDMA
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART1_RX,
.rxfifo = g_uart1rxfifo,
#endif
# endif
};
static uart_dev_t g_uart1port =
@ -547,11 +547,11 @@ static uart_dev_t g_uart1port =
.size = CONFIG_UART1_TXBUFSIZE,
.buffer = g_uart1txbuffer,
},
#ifdef CONFIG_KINETIS_UART1_RXDMA
# ifdef CONFIG_KINETIS_UART1_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart1priv,
};
#endif
@ -564,25 +564,25 @@ static struct up_dev_s g_uart2priv =
.uartbase = KINETIS_UART2_BASE,
.clock = BOARD_BUS_FREQ,
.baud = CONFIG_UART2_BAUD,
#ifdef CONFIG_DEBUG_FEATURES
# ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART2E,
#endif
# endif
.irqs = KINETIS_IRQ_UART2S,
.parity = CONFIG_UART2_PARITY,
.bits = CONFIG_UART2_BITS,
.stop2 = CONFIG_UART2_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART2_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART2_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART2_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART2_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART2_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART2_RTS,
#endif
#ifdef CONFIG_KINETIS_UART2_RXDMA
# endif
# ifdef CONFIG_KINETIS_UART2_RXDMA
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART2_RX,
.rxfifo = g_uart2rxfifo,
#endif
# endif
};
static uart_dev_t g_uart2port =
@ -597,11 +597,11 @@ static uart_dev_t g_uart2port =
.size = CONFIG_UART2_TXBUFSIZE,
.buffer = g_uart2txbuffer,
},
#ifdef CONFIG_KINETIS_UART2_RXDMA
# ifdef CONFIG_KINETIS_UART2_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart2priv,
};
#endif
@ -614,25 +614,25 @@ static struct up_dev_s g_uart3priv =
.uartbase = KINETIS_UART3_BASE,
.clock = BOARD_BUS_FREQ,
.baud = CONFIG_UART3_BAUD,
#ifdef CONFIG_DEBUG_FEATURES
# ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART3E,
#endif
# endif
.irqs = KINETIS_IRQ_UART3S,
.parity = CONFIG_UART3_PARITY,
.bits = CONFIG_UART3_BITS,
.stop2 = CONFIG_UART3_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART3_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART3_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART3_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART3_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART3_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART3_RTS,
#endif
#ifdef CONFIG_KINETIS_UART3_RXDMA
# endif
# ifdef CONFIG_KINETIS_UART3_RXDMA
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART3_RX,
.rxfifo = g_uart3rxfifo,
#endif
# endif
};
static uart_dev_t g_uart3port =
@ -647,11 +647,11 @@ static uart_dev_t g_uart3port =
.size = CONFIG_UART3_TXBUFSIZE,
.buffer = g_uart3txbuffer,
},
#ifdef CONFIG_KINETIS_UART3_RXDMA
# ifdef CONFIG_KINETIS_UART3_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart3priv,
};
#endif
@ -664,25 +664,25 @@ static struct up_dev_s g_uart4priv =
.uartbase = KINETIS_UART4_BASE,
.clock = BOARD_BUS_FREQ,
.baud = CONFIG_UART4_BAUD,
#ifdef CONFIG_DEBUG_FEATURES
# ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART4E,
#endif
# endif
.irqs = KINETIS_IRQ_UART4S,
.parity = CONFIG_UART4_PARITY,
.bits = CONFIG_UART4_BITS,
.stop2 = CONFIG_UART4_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART4_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART4_RTS,
#endif
#ifdef CONFIG_KINETIS_UART4_RXDMA
# endif
# ifdef CONFIG_KINETIS_UART4_RXDMA
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART4_RXTX,
.rxfifo = g_uart4rxfifo,
#endif
# endif
};
static uart_dev_t g_uart4port =
@ -697,11 +697,11 @@ static uart_dev_t g_uart4port =
.size = CONFIG_UART4_TXBUFSIZE,
.buffer = g_uart4txbuffer,
},
#ifdef CONFIG_KINETIS_UART4_RXDMA
# ifdef CONFIG_KINETIS_UART4_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart4priv,
};
#endif
@ -714,25 +714,25 @@ static struct up_dev_s g_uart5priv =
.uartbase = KINETIS_UART5_BASE,
.clock = BOARD_BUS_FREQ,
.baud = CONFIG_UART5_BAUD,
#ifdef CONFIG_DEBUG_FEATURES
# ifdef CONFIG_DEBUG_FEATURES
.irqe = KINETIS_IRQ_UART5E,
#endif
# endif
.irqs = KINETIS_IRQ_UART5S,
.parity = CONFIG_UART5_PARITY,
.bits = CONFIG_UART5_BITS,
.stop2 = CONFIG_UART5_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL)
.oflow = true,
.cts_gpio = PIN_UART5_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)
.iflow = true,
.rts_gpio = PIN_UART5_RTS,
#endif
#ifdef CONFIG_KINETIS_UART5_RXDMA
# endif
# ifdef CONFIG_KINETIS_UART5_RXDMA
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART5_RX,
.rxfifo = g_uart5rxfifo,
#endif
# endif
};
static uart_dev_t g_uart5port =
@ -747,11 +747,11 @@ static uart_dev_t g_uart5port =
.size = CONFIG_UART5_TXBUFSIZE,
.buffer = g_uart5txbuffer,
},
#ifdef CONFIG_KINETIS_UART5_RXDMA
# ifdef CONFIG_KINETIS_UART5_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart5priv,
};
#endif

630
arch/arm/src/s32k3xx/s32k3xx_serial.c
View File

File diff suppressed because it is too large Load Diff

54
arch/arm/src/samv7/sam_serial.c
View File

@ -717,10 +717,10 @@ static struct sam_dev_s g_usart0priv =
.parity = CONFIG_USART0_PARITY,
.bits = CONFIG_USART0_BITS,
.stopbits2 = CONFIG_USART0_2STOP,
#if defined(CONFIG_USART0_OFLOWCONTROL) || defined(CONFIG_USART0_IFLOWCONTROL)
# if defined(CONFIG_USART0_OFLOWCONTROL) || defined(CONFIG_USART0_IFLOWCONTROL)
.flowc = true,
#endif
#ifdef CONFIG_USART0_RXDMA
# endif
# ifdef CONFIG_USART0_RXDMA
.buf_idx = 0,
.nextcache = 0,
.rxbuf =
@ -732,11 +732,11 @@ static struct sam_dev_s g_usart0priv =
&g_usart0rxdesc[0], &g_usart0rxdesc[1]
},
.has_rxdma = true,
#endif
#ifdef CONFIG_SAMV7_USART0_RS485MODE
# endif
# ifdef CONFIG_SAMV7_USART0_RS485MODE
.has_rs485 = true,
.rs485_dir_gpio = GPIO_USART0_RTS,
#endif
# endif
};
static uart_dev_t g_usart0port =
@ -751,11 +751,11 @@ static uart_dev_t g_usart0port =
.size = CONFIG_USART0_TXBUFSIZE,
.buffer = g_usart0txbuffer,
},
#ifdef CONFIG_USART0_RXDMA
# ifdef CONFIG_USART0_RXDMA
.ops = &g_uart_rxdma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart0priv,
};
#endif
@ -772,10 +772,10 @@ static struct sam_dev_s g_usart1priv =
.parity = CONFIG_USART1_PARITY,
.bits = CONFIG_USART1_BITS,
.stopbits2 = CONFIG_USART1_2STOP,
#if defined(CONFIG_USART1_OFLOWCONTROL) || defined(CONFIG_USART1_IFLOWCONTROL)
# if defined(CONFIG_USART1_OFLOWCONTROL) || defined(CONFIG_USART1_IFLOWCONTROL)
.flowc = true,
#endif
#ifdef CONFIG_USART1_RXDMA
# endif
# ifdef CONFIG_USART1_RXDMA
.buf_idx = 0,
.nextcache = 0,
.rxbuf =
@ -787,11 +787,11 @@ static struct sam_dev_s g_usart1priv =
&g_usart1rxdesc[0], &g_usart1rxdesc[1]
},
.has_rxdma = true,
#endif
#ifdef CONFIG_SAMV7_USART1_RS485MODE
# endif
# ifdef CONFIG_SAMV7_USART1_RS485MODE
.has_rs485 = true,
.rs485_dir_gpio = GPIO_USART1_RTS,
#endif
# endif
};
static uart_dev_t g_usart1port =
@ -806,11 +806,11 @@ static uart_dev_t g_usart1port =
.size = CONFIG_USART1_TXBUFSIZE,
.buffer = g_usart1txbuffer,
},
#ifdef CONFIG_USART1_RXDMA
# ifdef CONFIG_USART1_RXDMA
.ops = &g_uart_rxdma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart1priv,
};
#endif
@ -827,10 +827,10 @@ static struct sam_dev_s g_usart2priv =
.parity = CONFIG_USART2_PARITY,
.bits = CONFIG_USART2_BITS,
.stopbits2 = CONFIG_USART2_2STOP,
#if defined(CONFIG_USART2_OFLOWCONTROL) || defined(CONFIG_USART2_IFLOWCONTROL)
# if defined(CONFIG_USART2_OFLOWCONTROL) || defined(CONFIG_USART2_IFLOWCONTROL)
.flowc = true,
#endif
#ifdef CONFIG_USART2_RXDMA
# endif
# ifdef CONFIG_USART2_RXDMA
.buf_idx = 0,
.nextcache = 0,
.rxbuf =
@ -842,11 +842,11 @@ static struct sam_dev_s g_usart2priv =
&g_usart2rxdesc[0], &g_usart2rxdesc[1]
},
.has_rxdma = true,
#endif
#ifdef CONFIG_SAMV7_USART2_RS485MODE
# endif
# ifdef CONFIG_SAMV7_USART2_RS485MODE
.has_rs485 = true,
.rs485_dir_gpio = GPIO_USART2_RTS,
#endif
# endif
};
static uart_dev_t g_usart2port =
@ -861,11 +861,11 @@ static uart_dev_t g_usart2port =
.size = CONFIG_USART2_TXBUFSIZE,
.buffer = g_usart2txbuffer,
},
#ifdef CONFIG_USART2_RXDMA
# ifdef CONFIG_USART2_RXDMA
.ops = &g_uart_rxdma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart2priv,
};
#endif

6
arch/arm/src/stm32/stm32_eth.c
View File

@ -3365,7 +3365,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
/* Set up the MII interface */
#if defined(CONFIG_STM32_MII)
# if defined(CONFIG_STM32_MII)
/* Select the MII interface */
@ -3427,7 +3427,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
/* Set up the RMII interface. */
#elif defined(CONFIG_STM32_RMII)
# elif defined(CONFIG_STM32_RMII)
/* Select the RMII interface */
@ -3479,7 +3479,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv)
stm32_configgpio(GPIO_ETH_RMII_TXD1);
stm32_configgpio(GPIO_ETH_RMII_TX_EN);
#endif
# endif
#endif
#ifdef CONFIG_STM32_ETH_PTP

92
arch/arm/src/stm32/stm32_hciuart.c
View File

@ -381,26 +381,26 @@ static const struct hciuart_config_s g_hciusart1_config =
.rxbuffer = g_usart1_rxbuffer,
.txbuffer = g_usart1_txbuffer,
#ifdef CONFIG_STM32_HCIUART1_RXDMA
# ifdef CONFIG_STM32_HCIUART1_RXDMA
.rxdmabuffer = g_usart1_rxdmabuffer,
#endif
# endif
.rxbufsize = CONFIG_STM32_HCIUART1_RXBUFSIZE,
.txbufsize = CONFIG_STM32_HCIUART1_TXBUFSIZE,
#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW
# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW
.rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART1_RXBUFSIZE),
.rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART1_RXBUFSIZE),
#endif
#ifdef CONFIG_STM32_HCIUART_RXDMA
# endif
# ifdef CONFIG_STM32_HCIUART_RXDMA
.rxdmachan = DMAMAP_USART1_RX,
#endif
# endif
.irq = STM32_IRQ_USART1,
.baud = CONFIG_STM32_HCIUART1_BAUD,
#if defined(CONFIG_STM32_STM32F33XX)
# if defined(CONFIG_STM32_STM32F33XX)
.apbclock = STM32_PCLK1_FREQUENCY, /* Errata 2.5.1 */
#else
# else
.apbclock = STM32_PCLK2_FREQUENCY,
#endif
# endif
.usartbase = STM32_USART1_BASE,
.tx_gpio = GPIO_USART1_TX,
.rx_gpio = GPIO_USART1_RX,
@ -445,18 +445,18 @@ static const struct hciuart_config_s g_hciusart2_config =
.rxbuffer = g_usart2_rxbuffer,
.txbuffer = g_usart2_txbuffer,
#ifdef CONFIG_STM32_HCIUART2_RXDMA
# ifdef CONFIG_STM32_HCIUART2_RXDMA
.rxdmabuffer = g_usart2_rxdmabuffer,
#endif
# endif
.rxbufsize = CONFIG_STM32_HCIUART2_RXBUFSIZE,
.txbufsize = CONFIG_STM32_HCIUART2_TXBUFSIZE,
#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW
# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW
.rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART2_RXBUFSIZE),
.rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART2_RXBUFSIZE),
#endif
#ifdef CONFIG_STM32_HCIUART_RXDMA
# endif
# ifdef CONFIG_STM32_HCIUART_RXDMA
.rxdmachan = DMAMAP_USART2_RX,
#endif
# endif
.irq = STM32_IRQ_USART2,
.baud = CONFIG_STM32_HCIUART2_BAUD,
@ -476,9 +476,9 @@ static const struct hciuart_config_s g_hciusart2_config =
static uint8_t g_usart3_rxbuffer[CONFIG_STM32_HCIUART3_RXBUFSIZE];
static uint8_t g_usart3_txbuffer[CONFIG_STM32_HCIUART3_TXBUFSIZE];
#ifdef CONFIG_STM32_HCIUART3_RXDMA
# ifdef CONFIG_STM32_HCIUART3_RXDMA
static uint8_t g_usart3_rxdmabuffer[RXDMA_BUFFER_SIZE];
#endif
# endif
/* HCI USART3 variable state information */
@ -505,18 +505,18 @@ static const struct hciuart_config_s g_hciusart3_config =
.rxbuffer = g_usart3_rxbuffer,
.txbuffer = g_usart3_txbuffer,
#ifdef CONFIG_STM32_HCIUART3_RXDMA
# ifdef CONFIG_STM32_HCIUART3_RXDMA
.rxdmabuffer = g_usart3_rxdmabuffer,
#endif
# endif
.rxbufsize = CONFIG_STM32_HCIUART3_RXBUFSIZE,
.txbufsize = CONFIG_STM32_HCIUART3_TXBUFSIZE,
#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW
# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW
.rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART3_RXBUFSIZE),
.rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART3_RXBUFSIZE),
#endif
#ifdef CONFIG_STM32_HCIUART_RXDMA
# endif
# ifdef CONFIG_STM32_HCIUART_RXDMA
.rxdmachan = DMAMAP_USART3_RX,
#endif
# endif
.irq = STM32_IRQ_USART3,
.baud = CONFIG_STM32_HCIUART3_BAUD,
@ -534,13 +534,11 @@ static const struct hciuart_config_s g_hciusart3_config =
#ifdef CONFIG_STM32_USART6_HCIUART
/* I/O buffers */
#ifdef CONFIG_STM32_USART6_HCIUART
static uint8_t g_usart6_rxbuffer[CONFIG_STM32_HCIUART6_RXBUFSIZE];
static uint8_t g_usart6_txbuffer[CONFIG_STM32_HCIUART6_TXBUFSIZE];
# ifdef CONFIG_STM32_HCIUART6_RXDMA
static uint8_t g_usart6_rxdmabuffer[RXDMA_BUFFER_SIZE];
# endif
#endif
/* HCI USART6 variable state information */
@ -567,18 +565,18 @@ static const struct hciuart_config_s g_hciusart6_config =
.rxbuffer = g_usart6_rxbuffer,
.txbuffer = g_usart6_txbuffer,
#ifdef CONFIG_STM32_HCIUART6_RXDMA
# ifdef CONFIG_STM32_HCIUART6_RXDMA
.rxdmabuffer = g_usart6_rxdmabuffer,
#endif
# endif
.rxbufsize = CONFIG_STM32_HCIUART6_RXBUFSIZE,
.txbufsize = CONFIG_STM32_HCIUART6_TXBUFSIZE,
#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW
# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW
.rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART6_RXBUFSIZE),
.rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART6_RXBUFSIZE),
#endif
#ifdef CONFIG_STM32_HCIUART_RXDMA
# endif
# ifdef CONFIG_STM32_HCIUART_RXDMA
.rxdmachan = DMAMAP_USART6_RX,
#endif
# endif
.irq = STM32_IRQ_USART6,
.baud = CONFIG_STM32_HCIUART6_BAUD,
@ -598,9 +596,9 @@ static const struct hciuart_config_s g_hciusart6_config =
static uint8_t g_uart7_rxbuffer[CONFIG_STM32_HCIUART7_RXBUFSIZE];
static uint8_t g_uart7_txbuffer[CONFIG_STM32_HCIUART7_TXBUFSIZE];
#ifdef CONFIG_STM32_HCIUART7_RXDMA
# ifdef CONFIG_STM32_HCIUART7_RXDMA
static uint8_t g_uart7_rxdmabuffer[RXDMA_BUFFER_SIZE];
#endif
# endif
/* HCI UART7 variable state information */
@ -627,18 +625,18 @@ static const struct hciuart_config_s g_hciuart7_config =
.rxbuffer = g_uart7_rxbuffer,
.txbuffer = g_uart7_txbuffer,
#ifdef CONFIG_STM32_HCIUART7_RXDMA
# ifdef CONFIG_STM32_HCIUART7_RXDMA
.rxdmabuffer = g_uart7_rxdmabuffer,
#endif
# endif
.rxbufsize = CONFIG_STM32_HCIUART7_RXBUFSIZE,
.txbufsize = CONFIG_STM32_HCIUART7_TXBUFSIZE,
#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW
# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW
.rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART7_RXBUFSIZE),
.rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART7_RXBUFSIZE),
#endif
#ifdef CONFIG_STM32_HCIUART_RXDMA
# endif
# ifdef CONFIG_STM32_HCIUART_RXDMA
.rxdmachan = DMAMAP_UART7_RX,
#endif
# endif
.irq = STM32_IRQ_UART7,
.baud = CONFIG_STM32_HCIUART7_BAUD,
@ -658,9 +656,9 @@ static const struct hciuart_config_s g_hciuart7_config =
static uint8_t g_uart8_rxbuffer[CONFIG_STM32_HCIUART8_RXBUFSIZE];
static uint8_t g_uart8_txbuffer[CONFIG_STM32_HCIUART8_TXBUFSIZE];
#ifdef CONFIG_STM32_HCIUART8_RXDMA
# ifdef CONFIG_STM32_HCIUART8_RXDMA
static uint8_t g_uart8_rxdmabuffer[RXDMA_BUFFER_SIZE];
#endif
# endif
/* HCI UART8 variable state information */
@ -687,18 +685,18 @@ static const struct hciuart_config_s g_hciuart8_config =
.rxbuffer = g_uart8_rxbuffer,
.txbuffer = g_uart8_txbuffer,
#ifdef CONFIG_STM32_HCIUART8_RXDMA
# ifdef CONFIG_STM32_HCIUART8_RXDMA
.rxdmabuffer = g_uart8_rxdmabuffer,
#endif
# endif
.rxbufsize = CONFIG_STM32_HCIUART8_RXBUFSIZE,
.txbufsize = CONFIG_STM32_HCIUART8_TXBUFSIZE,
#ifdef CONFIG_STM32_HCIUART_SW_RXFLOW
# ifdef CONFIG_STM32_HCIUART_SW_RXFLOW
.rxupper = RXFLOW_UPPER(CONFIG_STM32_HCIUART8_RXBUFSIZE),
.rxlower = RXFLOW_LOWER(CONFIG_STM32_HCIUART8_RXBUFSIZE),
#endif
#ifdef CONFIG_STM32_HCIUART_RXDMA
# endif
# ifdef CONFIG_STM32_HCIUART_RXDMA
.rxdmachan = DMAMAP_UART8_RX,
#endif
# endif
.irq = STM32_IRQ_UART8,
.baud = CONFIG_STM32_HCIUART8_BAUD,

278
arch/arm/src/stm32/stm32_serial.c
View File

@ -702,9 +702,9 @@ static struct up_dev_s g_usart1priv =
{
.dev =
{
#if CONSOLE_UART == 1
# if CONSOLE_UART == 1
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART1_RXBUFSIZE,
@ -715,15 +715,15 @@ static struct up_dev_s g_usart1priv =
.size = CONFIG_USART1_TXBUFSIZE,
.buffer = g_usart1txbuffer,
},
#if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA)
# if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_USART1_RXDMA) && !defined(CONFIG_USART1_TXDMA)
# elif defined(CONFIG_USART1_RXDMA) && !defined(CONFIG_USART1_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA)
# elif !defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA)
.ops = &g_uart_txdma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart1priv,
},
@ -732,38 +732,38 @@ static struct up_dev_s g_usart1priv =
.bits = CONFIG_USART1_BITS,
.stopbits2 = CONFIG_USART1_2STOP,
.baud = CONFIG_USART1_BAUD,
#if defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F302)
# if defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F302)
.apbclock = STM32_PCLK1_FREQUENCY, /* Errata 2.5.1 */
#else
# else
.apbclock = STM32_PCLK2_FREQUENCY,
#endif
# endif
.usartbase = STM32_USART1_BASE,
.tx_gpio = GPIO_USART1_TX,
.rx_gpio = GPIO_USART1_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART1_RTS,
#endif
#ifdef CONFIG_USART1_TXDMA
# endif
# ifdef CONFIG_USART1_TXDMA
.txdma_channel = DMAMAP_USART1_TX,
#endif
#ifdef CONFIG_USART1_RXDMA
# endif
# ifdef CONFIG_USART1_RXDMA
.rxdma_channel = DMAMAP_USART1_RX,
.rxfifo = g_usart1rxfifo,
#endif
# endif
#ifdef CONFIG_USART1_RS485
# ifdef CONFIG_USART1_RS485
.rs485_dir_gpio = GPIO_USART1_RS485_DIR,
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -774,9 +774,9 @@ static struct up_dev_s g_usart2priv =
{
.dev =
{
#if CONSOLE_UART == 2
# if CONSOLE_UART == 2
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART2_RXBUFSIZE,
@ -787,15 +787,15 @@ static struct up_dev_s g_usart2priv =
.size = CONFIG_USART2_TXBUFSIZE,
.buffer = g_usart2txbuffer,
},
#if defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA)
# if defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_USART2_RXDMA) && !defined(CONFIG_USART2_TXDMA)
# elif defined(CONFIG_USART2_RXDMA) && !defined(CONFIG_USART2_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA)
# elif !defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA)
.ops = &g_uart_txdma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart2priv,
},
@ -808,30 +808,30 @@ static struct up_dev_s g_usart2priv =
.usartbase = STM32_USART2_BASE,
.tx_gpio = GPIO_USART2_TX,
.rx_gpio = GPIO_USART2_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART2_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART2_RTS,
#endif
#ifdef CONFIG_USART2_TXDMA
# endif
# ifdef CONFIG_USART2_TXDMA
.txdma_channel = DMAMAP_USART2_TX,
#endif
#ifdef CONFIG_USART2_RXDMA
# endif
# ifdef CONFIG_USART2_RXDMA
.rxdma_channel = DMAMAP_USART2_RX,
.rxfifo = g_usart2rxfifo,
#endif
# endif
#ifdef CONFIG_USART2_RS485
# ifdef CONFIG_USART2_RS485
.rs485_dir_gpio = GPIO_USART2_RS485_DIR,
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -842,9 +842,9 @@ static struct up_dev_s g_usart3priv =
{
.dev =
{
#if CONSOLE_UART == 3
# if CONSOLE_UART == 3
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART3_RXBUFSIZE,
@ -855,15 +855,15 @@ static struct up_dev_s g_usart3priv =
.size = CONFIG_USART3_TXBUFSIZE,
.buffer = g_usart3txbuffer,
},
#if defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA)
# if defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_USART3_RXDMA) && !defined(CONFIG_USART3_TXDMA)
# elif defined(CONFIG_USART3_RXDMA) && !defined(CONFIG_USART3_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA)
# elif !defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_TXDMA)
.ops = &g_uart_txdma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart3priv,
},
@ -876,30 +876,30 @@ static struct up_dev_s g_usart3priv =
.usartbase = STM32_USART3_BASE,
.tx_gpio = GPIO_USART3_TX,
.rx_gpio = GPIO_USART3_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART3_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART3_RTS,
#endif
#ifdef CONFIG_USART3_TXDMA
# endif
# ifdef CONFIG_USART3_TXDMA
.txdma_channel = DMAMAP_USART3_TX,
#endif
#ifdef CONFIG_USART3_RXDMA
# endif
# ifdef CONFIG_USART3_RXDMA
.rxdma_channel = DMAMAP_USART3_RX,
.rxfifo = g_usart3rxfifo,
#endif
# endif
#ifdef CONFIG_USART3_RS485
# ifdef CONFIG_USART3_RS485
.rs485_dir_gpio = GPIO_USART3_RS485_DIR,
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -910,9 +910,9 @@ static struct up_dev_s g_uart4priv =
{
.dev =
{
#if CONSOLE_UART == 4
# if CONSOLE_UART == 4
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_UART4_RXBUFSIZE,
@ -923,15 +923,15 @@ static struct up_dev_s g_uart4priv =
.size = CONFIG_UART4_TXBUFSIZE,
.buffer = g_uart4txbuffer,
},
#if defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA)
# if defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_UART4_RXDMA) && !defined(CONFIG_UART4_TXDMA)
# elif defined(CONFIG_UART4_RXDMA) && !defined(CONFIG_UART4_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA)
# elif !defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_TXDMA)
.ops = &g_uart_txdma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart4priv,
},
@ -939,35 +939,35 @@ static struct up_dev_s g_uart4priv =
.parity = CONFIG_UART4_PARITY,
.bits = CONFIG_UART4_BITS,
.stopbits2 = CONFIG_UART4_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_UART4_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_UART4_RTS,
#endif
# endif
.baud = CONFIG_UART4_BAUD,
.apbclock = STM32_PCLK1_FREQUENCY,
.usartbase = STM32_UART4_BASE,
.tx_gpio = GPIO_UART4_TX,
.rx_gpio = GPIO_UART4_RX,
#ifdef CONFIG_UART4_TXDMA
# ifdef CONFIG_UART4_TXDMA
.txdma_channel = DMAMAP_UART4_TX,
#endif
#ifdef CONFIG_UART4_RXDMA
# endif
# ifdef CONFIG_UART4_RXDMA
.rxdma_channel = DMAMAP_UART4_RX,
.rxfifo = g_uart4rxfifo,
#endif
# endif
#ifdef CONFIG_UART4_RS485
# ifdef CONFIG_UART4_RS485
.rs485_dir_gpio = GPIO_UART4_RS485_DIR,
# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -978,9 +978,9 @@ static struct up_dev_s g_uart5priv =
{
.dev =
{
#if CONSOLE_UART == 5
# if CONSOLE_UART == 5
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_UART5_RXBUFSIZE,
@ -991,15 +991,15 @@ static struct up_dev_s g_uart5priv =
.size = CONFIG_UART5_TXBUFSIZE,
.buffer = g_uart5txbuffer,
},
#if defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA)
# if defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_UART5_RXDMA) && !defined(CONFIG_UART5_TXDMA)
# elif defined(CONFIG_UART5_RXDMA) && !defined(CONFIG_UART5_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA)
# elif !defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_TXDMA)
.ops = &g_uart_txdma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart5priv,
},
@ -1007,35 +1007,35 @@ static struct up_dev_s g_uart5priv =
.parity = CONFIG_UART5_PARITY,
.bits = CONFIG_UART5_BITS,
.stopbits2 = CONFIG_UART5_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_UART5_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_UART5_RTS,
#endif
# endif
.baud = CONFIG_UART5_BAUD,
.apbclock = STM32_PCLK1_FREQUENCY,
.usartbase = STM32_UART5_BASE,
.tx_gpio = GPIO_UART5_TX,
.rx_gpio = GPIO_UART5_RX,
#ifdef CONFIG_UART5_TXDMA
# ifdef CONFIG_UART5_TXDMA
.txdma_channel = DMAMAP_UART5_TX,
#endif
#ifdef CONFIG_UART5_RXDMA
# endif
# ifdef CONFIG_UART5_RXDMA
.rxdma_channel = DMAMAP_UART5_RX,
.rxfifo = g_uart5rxfifo,
#endif
# endif
#ifdef CONFIG_UART5_RS485
# ifdef CONFIG_UART5_RS485
.rs485_dir_gpio = GPIO_UART5_RS485_DIR,
# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -1046,9 +1046,9 @@ static struct up_dev_s g_usart6priv =
{
.dev =
{
#if CONSOLE_UART == 6
# if CONSOLE_UART == 6
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART6_RXBUFSIZE,
@ -1059,15 +1059,15 @@ static struct up_dev_s g_usart6priv =
.size = CONFIG_USART6_TXBUFSIZE,
.buffer = g_usart6txbuffer,
},
#if defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA)
# if defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_USART6_RXDMA) && !defined(CONFIG_USART6_TXDMA)
# elif defined(CONFIG_USART6_RXDMA) && !defined(CONFIG_USART6_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA)
# elif !defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_TXDMA)
.ops = &g_uart_txdma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart6priv,
},
@ -1080,30 +1080,30 @@ static struct up_dev_s g_usart6priv =
.usartbase = STM32_USART6_BASE,
.tx_gpio = GPIO_USART6_TX,
.rx_gpio = GPIO_USART6_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART6_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART6_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART6_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART6_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART6_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART6_RTS,
#endif
#ifdef CONFIG_USART6_TXDMA
# endif
# ifdef CONFIG_USART6_TXDMA
.txdma_channel = DMAMAP_USART6_TX,
#endif
#ifdef CONFIG_USART6_RXDMA
# endif
# ifdef CONFIG_USART6_RXDMA
.rxdma_channel = DMAMAP_USART6_RX,
.rxfifo = g_usart6rxfifo,
#endif
# endif
#ifdef CONFIG_USART6_RS485
# ifdef CONFIG_USART6_RS485
.rs485_dir_gpio = GPIO_USART6_RS485_DIR,
# if (CONFIG_USART6_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -1114,9 +1114,9 @@ static struct up_dev_s g_uart7priv =
{
.dev =
{
#if CONSOLE_UART == 7
# if CONSOLE_UART == 7
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_UART7_RXBUFSIZE,
@ -1127,15 +1127,15 @@ static struct up_dev_s g_uart7priv =
.size = CONFIG_UART7_TXBUFSIZE,
.buffer = g_uart7txbuffer,
},
#if defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA)
# if defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_UART7_RXDMA) && !defined(CONFIG_UART7_TXDMA)
# elif defined(CONFIG_UART7_RXDMA) && !defined(CONFIG_UART7_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA)
# elif !defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_TXDMA)
.ops = &g_uart_txdma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart7priv,
},
@ -1148,30 +1148,30 @@ static struct up_dev_s g_uart7priv =
.usartbase = STM32_UART7_BASE,
.tx_gpio = GPIO_UART7_TX,
.rx_gpio = GPIO_UART7_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART7_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART7_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_UART7_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART7_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART7_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_UART7_RTS,
#endif
#ifdef CONFIG_UART7_TXDMA
# endif
# ifdef CONFIG_UART7_TXDMA
.txdma_channel = DMAMAP_UART7_TX,
#endif
#ifdef CONFIG_UART7_RXDMA
# endif
# ifdef CONFIG_UART7_RXDMA
.rxdma_channel = DMAMAP_UART7_RX,
.rxfifo = g_uart7rxfifo,
#endif
# endif
#ifdef CONFIG_UART7_RS485
# ifdef CONFIG_UART7_RS485
.rs485_dir_gpio = GPIO_UART7_RS485_DIR,
# if (CONFIG_UART7_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -1182,9 +1182,9 @@ static struct up_dev_s g_uart8priv =
{
.dev =
{
#if CONSOLE_UART == 8
# if CONSOLE_UART == 8
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_UART8_RXBUFSIZE,
@ -1195,15 +1195,15 @@ static struct up_dev_s g_uart8priv =
.size = CONFIG_UART8_TXBUFSIZE,
.buffer = g_uart8txbuffer,
},
#if defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA)
# if defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_UART8_RXDMA) && !defined(CONFIG_UART8_TXDMA)
# elif defined(CONFIG_UART8_RXDMA) && !defined(CONFIG_UART8_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA)
# elif !defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_TXDMA)
.ops = &g_uart_txdma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart8priv,
},
@ -1216,30 +1216,30 @@ static struct up_dev_s g_uart8priv =
.usartbase = STM32_UART8_BASE,
.tx_gpio = GPIO_UART8_TX,
.rx_gpio = GPIO_UART8_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART8_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART8_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_UART8_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART8_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART8_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_UART8_RTS,
#endif
#ifdef CONFIG_UART8_TXDMA
# endif
# ifdef CONFIG_UART8_TXDMA
.txdma_channel = DMAMAP_UART8_TX,
#endif
#ifdef CONFIG_UART8_RXDMA
# endif
# ifdef CONFIG_UART8_RXDMA
.rxdma_channel = DMAMAP_UART8_RX,
.rxfifo = g_uart8rxfifo,
#endif
# endif
#ifdef CONFIG_UART8_RS485
# ifdef CONFIG_UART8_RS485
.rs485_dir_gpio = GPIO_UART8_RS485_DIR,
# if (CONFIG_UART8_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif

2
arch/arm/src/stm32/stm32f37xxx_rcc.c
View File

@ -528,7 +528,7 @@ static void stm32_stdclockconfig(void)
regval = STM32_CFGR2_PREDIV;
putreg32(regval, STM32_RCC_CFGR2);
# endif
#endif
/* Enable FLASH prefetch buffer and set FLASH wait states */

24
arch/arm/src/stm32/stm32f40xxx_i2c.c
View File

@ -431,10 +431,10 @@ static const struct stm32_i2c_config_s stm32_i2c2_config =
.reset_bit = RCC_APB1RSTR_I2C2RST,
.scl_pin = GPIO_I2C2_SCL,
.sda_pin = GPIO_I2C2_SDA,
#ifndef CONFIG_I2C_POLLED
# ifndef CONFIG_I2C_POLLED
.ev_irq = STM32_IRQ_I2C2EV,
.er_irq = STM32_IRQ_I2C2ER
#endif
# endif
};
static struct stm32_i2c_priv_s stm32_i2c2_priv =
@ -443,9 +443,9 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv =
.config = &stm32_i2c2_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_I2C_POLLED
# ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
# endif
.intstate = INTSTATE_IDLE,
.msgc = 0,
.msgv = NULL,
@ -453,13 +453,13 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv =
.dcnt = 0,
.flags = 0,
.status = 0,
#ifdef CONFIG_STM32_I2C_DMA
# ifdef CONFIG_STM32_I2C_DMA
# ifndef CONFIG_STM32_DMA1
# error "I2C2 enabled with DMA but corresponding DMA controller 1 is not enabled!"
# endif
.rxch = DMAMAP_I2C2_RX,
.txch = DMAMAP_I2C2_TX,
#endif
# endif
};
#endif
@ -471,10 +471,10 @@ static const struct stm32_i2c_config_s stm32_i2c3_config =
.reset_bit = RCC_APB1RSTR_I2C3RST,
.scl_pin = GPIO_I2C3_SCL,
.sda_pin = GPIO_I2C3_SDA,
#ifndef CONFIG_I2C_POLLED
# ifndef CONFIG_I2C_POLLED
.ev_irq = STM32_IRQ_I2C3EV,
.er_irq = STM32_IRQ_I2C3ER
#endif
# endif
};
static struct stm32_i2c_priv_s stm32_i2c3_priv =
@ -483,9 +483,9 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
.config = &stm32_i2c3_config,
.refs = 0,
.lock = NXMUTEX_INITIALIZER,
#ifndef CONFIG_I2C_POLLED
# ifndef CONFIG_I2C_POLLED
.sem_isr = SEM_INITIALIZER(0),
#endif
# endif
.intstate = INTSTATE_IDLE,
.msgc = 0,
.msgv = NULL,
@ -493,13 +493,13 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv =
.dcnt = 0,
.flags = 0,
.status = 0,
#ifdef CONFIG_STM32_I2C_DMA
# ifdef CONFIG_STM32_I2C_DMA
# ifndef CONFIG_STM32_DMA1
# error "I2C3 enabled with DMA but corresponding DMA controller 1 is not enabled!"
# endif
.rxch = DMAMAP_I2C3_RX,
.txch = DMAMAP_I2C3_TX,
#endif
# endif
};
#endif

154
arch/arm/src/stm32f0l0g0/stm32_serial_v1.c
View File

@ -311,9 +311,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = stm32serial_receive,
.rxint = stm32serial_rxint,
.rxavailable = stm32serial_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
# ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = stm32serial_rxflowcontrol,
#endif
# endif
.send = stm32serial_send,
.txint = stm32serial_txint,
.txready = stm32serial_txready,
@ -332,9 +332,9 @@ static const struct uart_ops_s g_uart_dma_ops =
.receive = stm32serial_dmareceive,
.rxint = stm32serial_dmarxint,
.rxavailable = stm32serial_dmarxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
# ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = stm32serial_rxflowcontrol,
#endif
# endif
.send = stm32serial_send,
.txint = stm32serial_txint,
.txready = stm32serial_txready,
@ -391,9 +391,9 @@ static struct stm32_serial_s g_usart1priv =
{
.dev =
{
#if CONSOLE_USART == 1
# if CONSOLE_USART == 1
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART1_RXBUFSIZE,
@ -404,11 +404,11 @@ static struct stm32_serial_s g_usart1priv =
.size = CONFIG_USART1_TXBUFSIZE,
.buffer = g_usart1txbuffer,
},
#ifdef CONFIG_USART1_RXDMA
# ifdef CONFIG_USART1_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart1priv,
},
@ -421,27 +421,27 @@ static struct stm32_serial_s g_usart1priv =
.usartbase = STM32_USART1_BASE,
.tx_gpio = GPIO_USART1_TX,
.rx_gpio = GPIO_USART1_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART1_RTS,
#endif
#ifdef CONFIG_USART1_RXDMA
# endif
# ifdef CONFIG_USART1_RXDMA
.rxdma_channel = DMAMAP_USART1_RX,
.rxfifo = g_usart1rxfifo,
#endif
# endif
#ifdef CONFIG_USART1_RS485
# ifdef CONFIG_USART1_RS485
.rs485_dir_gpio = GPIO_USART1_RS485_DIR,
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -452,9 +452,9 @@ static struct stm32_serial_s g_usart2priv =
{
.dev =
{
#if CONSOLE_USART == 2
# if CONSOLE_USART == 2
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART2_RXBUFSIZE,
@ -465,11 +465,11 @@ static struct stm32_serial_s g_usart2priv =
.size = CONFIG_USART2_TXBUFSIZE,
.buffer = g_usart2txbuffer,
},
#ifdef CONFIG_USART2_RXDMA
# ifdef CONFIG_USART2_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart2priv,
},
@ -482,27 +482,27 @@ static struct stm32_serial_s g_usart2priv =
.usartbase = STM32_USART2_BASE,
.tx_gpio = GPIO_USART2_TX,
.rx_gpio = GPIO_USART2_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART2_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART2_RTS,
#endif
#ifdef CONFIG_USART2_RXDMA
# endif
# ifdef CONFIG_USART2_RXDMA
.rxdma_channel = DMAMAP_USART2_RX,
.rxfifo = g_usart2rxfifo,
#endif
# endif
#ifdef CONFIG_USART2_RS485
# ifdef CONFIG_USART2_RS485
.rs485_dir_gpio = GPIO_USART2_RS485_DIR,
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -513,9 +513,9 @@ static struct stm32_serial_s g_usart3priv =
{
.dev =
{
#if CONSOLE_USART == 3
# if CONSOLE_USART == 3
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART3_RXBUFSIZE,
@ -526,11 +526,11 @@ static struct stm32_serial_s g_usart3priv =
.size = CONFIG_USART3_TXBUFSIZE,
.buffer = g_usart3txbuffer,
},
#ifdef CONFIG_USART3_RXDMA
# ifdef CONFIG_USART3_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart3priv,
},
@ -543,27 +543,27 @@ static struct stm32_serial_s g_usart3priv =
.usartbase = STM32_USART3_BASE,
.tx_gpio = GPIO_USART3_TX,
.rx_gpio = GPIO_USART3_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART3_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART3_RTS,
#endif
#ifdef CONFIG_USART3_RXDMA
# endif
# ifdef CONFIG_USART3_RXDMA
.rxdma_channel = DMAMAP_USART3_RX,
.rxfifo = g_usart3rxfifo,
#endif
# endif
#ifdef CONFIG_USART3_RS485
# ifdef CONFIG_USART3_RS485
.rs485_dir_gpio = GPIO_USART3_RS485_DIR,
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -574,9 +574,9 @@ static struct stm32_serial_s g_usart4priv =
{
.dev =
{
#if CONSOLE_USART == 4
# if CONSOLE_USART == 4
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART4_RXBUFSIZE,
@ -587,11 +587,11 @@ static struct stm32_serial_s g_usart4priv =
.size = CONFIG_USART4_TXBUFSIZE,
.buffer = g_usart4txbuffer,
},
#ifdef CONFIG_USART4_RXDMA
# ifdef CONFIG_USART4_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart4priv,
},
@ -599,36 +599,36 @@ static struct stm32_serial_s g_usart4priv =
.parity = CONFIG_USART4_PARITY,
.bits = CONFIG_USART4_BITS,
.stopbits2 = CONFIG_USART4_2STOP,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
# ifdef CONFIG_SERIAL_IFLOWCONTROL
.iflow = false,
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
# endif
# ifdef CONFIG_SERIAL_OFLOWCONTROL
.oflow = false,
#endif
# endif
.baud = CONFIG_USART4_BAUD,
.apbclock = STM32_PCLK1_FREQUENCY,
.usartbase = STM32_USART4_BASE,
.tx_gpio = GPIO_USART4_TX,
.rx_gpio = GPIO_USART4_RX,
#ifdef CONFIG_SERIAL_OFLOWCONTROL
# ifdef CONFIG_SERIAL_OFLOWCONTROL
.cts_gpio = 0,
#endif
#ifdef CONFIG_SERIAL_IFLOWCONTROL
# endif
# ifdef CONFIG_SERIAL_IFLOWCONTROL
.rts_gpio = 0,
#endif
#ifdef CONFIG_USART4_RXDMA
# endif
# ifdef CONFIG_USART4_RXDMA
.rxdma_channel = DMAMAP_USART4_RX,
.rxfifo = g_usart4rxfifo,
#endif
# endif
#ifdef CONFIG_USART4_RS485
# ifdef CONFIG_USART4_RS485
.rs485_dir_gpio = GPIO_USART4_RS485_DIR,
# if (CONFIG_USART4_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -639,9 +639,9 @@ static struct stm32_serial_s g_usart5priv =
{
.dev =
{
#if CONSOLE_USART == 5
# if CONSOLE_USART == 5
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART5_RXBUFSIZE,
@ -652,11 +652,11 @@ static struct stm32_serial_s g_usart5priv =
.size = CONFIG_USART5_TXBUFSIZE,
.buffer = g_usart5txbuffer,
},
#ifdef CONFIG_USART5_RXDMA
# ifdef CONFIG_USART5_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart5priv,
},
@ -664,36 +664,36 @@ static struct stm32_serial_s g_usart5priv =
.parity = CONFIG_USART5_PARITY,
.bits = CONFIG_USART5_BITS,
.stopbits2 = CONFIG_USART5_2STOP,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
# ifdef CONFIG_SERIAL_IFLOWCONTROL
.iflow = false,
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
# endif
# ifdef CONFIG_SERIAL_OFLOWCONTROL
.oflow = false,
#endif
# endif
.baud = CONFIG_USART5_BAUD,
.apbclock = STM32_PCLK1_FREQUENCY,
.usartbase = STM32_USART5_BASE,
.tx_gpio = GPIO_USART5_TX,
.rx_gpio = GPIO_USART5_RX,
#ifdef CONFIG_SERIAL_OFLOWCONTROL
# ifdef CONFIG_SERIAL_OFLOWCONTROL
.cts_gpio = 0,
#endif
#ifdef CONFIG_SERIAL_IFLOWCONTROL
# endif
# ifdef CONFIG_SERIAL_IFLOWCONTROL
.rts_gpio = 0,
#endif
#ifdef CONFIG_USART5_RXDMA
# endif
# ifdef CONFIG_USART5_RXDMA
.rxdma_channel = DMAMAP_USART5_RX,
.rxfifo = g_usart5rxfifo,
#endif
# endif
#ifdef CONFIG_USART5_RS485
# ifdef CONFIG_USART5_RS485
.rs485_dir_gpio = GPIO_USART5_RS485_DIR,
# if (CONFIG_USART5_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif

4
arch/arm/src/stm32f7/stm32_lse.c
View File

@ -38,14 +38,14 @@
# if CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
# endif
#endif
#ifdef CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY
# if CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \
CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
# endif
#endif
/****************************************************************************

2
arch/arm/src/stm32f7/stm32_rtc.c
View File

@ -975,7 +975,7 @@ int up_rtc_initialize(void)
modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST);
modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0);
# if RCC_BDCR_RTCSEL == RCC_BDCR_RTCSEL_LSE
#if RCC_BDCR_RTCSEL == RCC_BDCR_RTCSEL_LSE
/* Because of the Backup domain Reset - we must re enable the LSE
* if it is used
*/

1
arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h
View File

@ -409,6 +409,5 @@
# define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */
# define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */
# define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */
#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_UART_H */

4
arch/arm/src/stm32h7/stm32_lse.c
View File

@ -39,14 +39,14 @@
# if CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
# endif
#endif
#ifdef CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY
# if CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \
CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
# endif
#endif
/****************************************************************************

2
arch/arm/src/stm32h7/stm32_rtc.c
View File

@ -975,7 +975,7 @@ int up_rtc_initialize(void)
modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST);
modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0);
# if RCC_BDCR_RTCSEL == RCC_BDCR_RTCSEL_LSE
#if RCC_BDCR_RTCSEL == RCC_BDCR_RTCSEL_LSE
/* Because of the Backup domain Reset - we must re enable the LSE
* if it is used
*/

4
arch/arm/src/stm32l4/stm32l4_lse.c
View File

@ -37,14 +37,14 @@
# if CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
# endif
#endif
#ifdef CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY
# if CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \
CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
# endif
#endif
/****************************************************************************

8
arch/arm/src/stm32l4/stm32l4_otgfsdev.c
View File

@ -5417,22 +5417,22 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv)
regval = OTGFS_GCCFG_PWRDWN;
# ifdef CONFIG_USBDEV_VBUSSENSING
#ifdef CONFIG_USBDEV_VBUSSENSING
/* Enable Vbus sensing */
regval |= OTGFS_GCCFG_VBDEN;
# endif
#endif
stm32l4_putreg(regval, STM32L4_OTGFS_GCCFG);
up_mdelay(20);
/* When VBUS sensing is not used we need to force the B session valid */
# ifndef CONFIG_USBDEV_VBUSSENSING
#ifndef CONFIG_USBDEV_VBUSSENSING
regval = stm32l4_getreg(STM32L4_OTGFS_GOTGCTL);
regval |= (OTGFS_GOTGCTL_BVALOEN | OTGFS_GOTGCTL_BVALOVAL);
stm32l4_putreg(regval, STM32L4_OTGFS_GOTGCTL);
# endif
#endif
/* Force Device Mode */

156
arch/arm/src/stm32l4/stm32l4_serial.c
View File

@ -442,9 +442,9 @@ static struct stm32l4_serial_s g_lpuart1priv =
{
.dev =
{
#if CONSOLE_UART == 1
# if CONSOLE_UART == 1
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_LPUART1_RXBUFSIZE,
@ -455,11 +455,11 @@ static struct stm32l4_serial_s g_lpuart1priv =
.size = CONFIG_LPUART1_TXBUFSIZE,
.buffer = g_lpuart1txbuffer,
},
#ifdef CONFIG_LPUART1_RXDMA
# ifdef CONFIG_LPUART1_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_lpuart1priv,
},
@ -472,27 +472,27 @@ static struct stm32l4_serial_s g_lpuart1priv =
.usartbase = STM32L4_LPUART1_BASE,
.tx_gpio = GPIO_LPUART1_TX,
.rx_gpio = GPIO_LPUART1_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_LPUART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_LPUART1_RTS,
#endif
#ifdef CONFIG_LPUART1_RXDMA
# endif
# ifdef CONFIG_LPUART1_RXDMA
.rxdma_channel = DMAMAP_LPUART1_RX,
.rxfifo = g_lpuart1rxfifo,
#endif
# endif
#ifdef CONFIG_LPUART1_RS485
# ifdef CONFIG_LPUART1_RS485
.rs485_dir_gpio = GPIO_LPUART1_RS485_DIR,
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -503,9 +503,9 @@ static struct stm32l4_serial_s g_usart1priv =
{
.dev =
{
#if CONSOLE_UART == 2
# if CONSOLE_UART == 2
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART1_RXBUFSIZE,
@ -516,11 +516,11 @@ static struct stm32l4_serial_s g_usart1priv =
.size = CONFIG_USART1_TXBUFSIZE,
.buffer = g_usart1txbuffer,
},
#ifdef CONFIG_USART1_RXDMA
# ifdef CONFIG_USART1_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart1priv,
},
@ -533,27 +533,27 @@ static struct stm32l4_serial_s g_usart1priv =
.usartbase = STM32L4_USART1_BASE,
.tx_gpio = GPIO_USART1_TX,
.rx_gpio = GPIO_USART1_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART1_RTS,
#endif
#ifdef CONFIG_USART1_RXDMA
# endif
# ifdef CONFIG_USART1_RXDMA
.rxdma_channel = DMAMAP_USART1_RX,
.rxfifo = g_usart1rxfifo,
#endif
# endif
#ifdef CONFIG_USART1_RS485
# ifdef CONFIG_USART1_RS485
.rs485_dir_gpio = GPIO_USART1_RS485_DIR,
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -564,9 +564,9 @@ static struct stm32l4_serial_s g_usart2priv =
{
.dev =
{
#if CONSOLE_UART == 3
# if CONSOLE_UART == 3
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART2_RXBUFSIZE,
@ -577,11 +577,11 @@ static struct stm32l4_serial_s g_usart2priv =
.size = CONFIG_USART2_TXBUFSIZE,
.buffer = g_usart2txbuffer,
},
#ifdef CONFIG_USART2_RXDMA
# ifdef CONFIG_USART2_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart2priv,
},
@ -594,27 +594,27 @@ static struct stm32l4_serial_s g_usart2priv =
.usartbase = STM32L4_USART2_BASE,
.tx_gpio = GPIO_USART2_TX,
.rx_gpio = GPIO_USART2_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART2_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART2_RTS,
#endif
#ifdef CONFIG_USART2_RXDMA
# endif
# ifdef CONFIG_USART2_RXDMA
.rxdma_channel = DMAMAP_USART2_RX,
.rxfifo = g_usart2rxfifo,
#endif
# endif
#ifdef CONFIG_USART2_RS485
# ifdef CONFIG_USART2_RS485
.rs485_dir_gpio = GPIO_USART2_RS485_DIR,
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -625,9 +625,9 @@ static struct stm32l4_serial_s g_usart3priv =
{
.dev =
{
#if CONSOLE_UART == 4
# if CONSOLE_UART == 4
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART3_RXBUFSIZE,
@ -638,11 +638,11 @@ static struct stm32l4_serial_s g_usart3priv =
.size = CONFIG_USART3_TXBUFSIZE,
.buffer = g_usart3txbuffer,
},
#ifdef CONFIG_USART3_RXDMA
# ifdef CONFIG_USART3_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart3priv,
},
@ -655,27 +655,27 @@ static struct stm32l4_serial_s g_usart3priv =
.usartbase = STM32L4_USART3_BASE,
.tx_gpio = GPIO_USART3_TX,
.rx_gpio = GPIO_USART3_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART3_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART3_RTS,
#endif
#ifdef CONFIG_USART3_RXDMA
# endif
# ifdef CONFIG_USART3_RXDMA
.rxdma_channel = DMAMAP_USART3_RX,
.rxfifo = g_usart3rxfifo,
#endif
# endif
#ifdef CONFIG_USART3_RS485
# ifdef CONFIG_USART3_RS485
.rs485_dir_gpio = GPIO_USART3_RS485_DIR,
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -686,9 +686,9 @@ static struct stm32l4_serial_s g_uart4priv =
{
.dev =
{
#if CONSOLE_UART == 5
# if CONSOLE_UART == 5
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_UART4_RXBUFSIZE,
@ -699,11 +699,11 @@ static struct stm32l4_serial_s g_uart4priv =
.size = CONFIG_UART4_TXBUFSIZE,
.buffer = g_uart4txbuffer,
},
#ifdef CONFIG_UART4_RXDMA
# ifdef CONFIG_UART4_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart4priv,
},
@ -711,32 +711,32 @@ static struct stm32l4_serial_s g_uart4priv =
.parity = CONFIG_UART4_PARITY,
.bits = CONFIG_UART4_BITS,
.stopbits2 = CONFIG_UART4_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_UART4_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_UART4_RTS,
#endif
# endif
.baud = CONFIG_UART4_BAUD,
.apbclock = STM32L4_PCLK1_FREQUENCY,
.usartbase = STM32L4_UART4_BASE,
.tx_gpio = GPIO_UART4_TX,
.rx_gpio = GPIO_UART4_RX,
#ifdef CONFIG_UART4_RXDMA
# ifdef CONFIG_UART4_RXDMA
.rxdma_channel = DMAMAP_UART4_RX,
.rxfifo = g_uart4rxfifo,
#endif
# endif
#ifdef CONFIG_UART4_RS485
# ifdef CONFIG_UART4_RS485
.rs485_dir_gpio = GPIO_UART4_RS485_DIR,
# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -747,9 +747,9 @@ static struct stm32l4_serial_s g_uart5priv =
{
.dev =
{
#if CONSOLE_UART == 6
# if CONSOLE_UART == 6
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_UART5_RXBUFSIZE,
@ -760,11 +760,11 @@ static struct stm32l4_serial_s g_uart5priv =
.size = CONFIG_UART5_TXBUFSIZE,
.buffer = g_uart5txbuffer,
},
#ifdef CONFIG_UART5_RXDMA
# ifdef CONFIG_UART5_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart5priv,
},
@ -772,32 +772,32 @@ static struct stm32l4_serial_s g_uart5priv =
.parity = CONFIG_UART5_PARITY,
.bits = CONFIG_UART5_BITS,
.stopbits2 = CONFIG_UART5_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_UART5_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_UART5_RTS,
#endif
# endif
.baud = CONFIG_UART5_BAUD,
.apbclock = STM32L4_PCLK1_FREQUENCY,
.usartbase = STM32L4_UART5_BASE,
.tx_gpio = GPIO_UART5_TX,
.rx_gpio = GPIO_UART5_RX,
#ifdef CONFIG_UART5_RXDMA
# ifdef CONFIG_UART5_RXDMA
.rxdma_channel = DMAMAP_UART5_RX,
.rxfifo = g_uart5rxfifo,
#endif
# endif
#ifdef CONFIG_UART5_RS485
# ifdef CONFIG_UART5_RS485
.rs485_dir_gpio = GPIO_UART5_RS485_DIR,
# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif

2
arch/arm/src/stm32l5/stm32l5_lse.c
View File

@ -39,7 +39,7 @@
# if CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
# endif
#endif
/****************************************************************************

164
arch/arm/src/stm32l5/stm32l5_serial.c
View File

@ -358,9 +358,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = stm32l5serial_receive,
.rxint = stm32l5serial_rxint,
.rxavailable = stm32l5serial_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
# ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = stm32l5serial_rxflowcontrol,
#endif
# endif
.send = stm32l5serial_send,
.txint = stm32l5serial_txint,
.txready = stm32l5serial_txready,
@ -379,9 +379,9 @@ static const struct uart_ops_s g_uart_dma_ops =
.receive = stm32l5serial_dmareceive,
.rxint = stm32l5serial_dmarxint,
.rxavailable = stm32l5serial_dmarxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
# ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = stm32l5serial_rxflowcontrol,
#endif
# endif
.send = stm32l5serial_send,
.txint = stm32l5serial_txint,
.txready = stm32l5serial_txready,
@ -446,9 +446,9 @@ static struct stm32l5_serial_s g_lpuart1priv =
{
.dev =
{
#if CONSOLE_UART == 1
# if CONSOLE_UART == 1
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_LPUART1_RXBUFSIZE,
@ -459,11 +459,11 @@ static struct stm32l5_serial_s g_lpuart1priv =
.size = CONFIG_LPUART1_TXBUFSIZE,
.buffer = g_lpuart1txbuffer,
},
#ifdef CONFIG_LPUART1_RXDMA
# ifdef CONFIG_LPUART1_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_lpuart1priv,
},
@ -476,27 +476,27 @@ static struct stm32l5_serial_s g_lpuart1priv =
.usartbase = STM32L5_LPUART1_BASE,
.tx_gpio = GPIO_LPUART1_TX,
.rx_gpio = GPIO_LPUART1_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_LPUART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_LPUART1_RTS,
#endif
#ifdef CONFIG_LPUART1_RXDMA
# endif
# ifdef CONFIG_LPUART1_RXDMA
.rxdma_channel = DMAMAP_LPUSART_RX,
.rxfifo = g_lpuart1rxfifo,
#endif
# endif
#ifdef CONFIG_USART1_RS485
# ifdef CONFIG_USART1_RS485
.rs485_dir_gpio = GPIO_LPUART1_RS485_DIR,
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -505,9 +505,9 @@ static struct stm32l5_serial_s g_usart1priv =
{
.dev =
{
#if CONSOLE_UART == 2
# if CONSOLE_UART == 2
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART1_RXBUFSIZE,
@ -518,11 +518,11 @@ static struct stm32l5_serial_s g_usart1priv =
.size = CONFIG_USART1_TXBUFSIZE,
.buffer = g_usart1txbuffer,
},
#ifdef CONFIG_USART1_RXDMA
# ifdef CONFIG_USART1_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart1priv,
},
@ -535,27 +535,27 @@ static struct stm32l5_serial_s g_usart1priv =
.usartbase = STM32L5_USART1_BASE,
.tx_gpio = GPIO_USART1_TX,
.rx_gpio = GPIO_USART1_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART1_RTS,
#endif
#ifdef CONFIG_USART1_RXDMA
# endif
# ifdef CONFIG_USART1_RXDMA
.rxdma_channel = DMAMAP_USART1_RX,
.rxfifo = g_usart1rxfifo,
#endif
# endif
#ifdef CONFIG_USART1_RS485
# ifdef CONFIG_USART1_RS485
.rs485_dir_gpio = GPIO_USART1_RS485_DIR,
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -566,9 +566,9 @@ static struct stm32l5_serial_s g_usart2priv =
{
.dev =
{
#if CONSOLE_UART == 3
# if CONSOLE_UART == 3
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART2_RXBUFSIZE,
@ -579,11 +579,11 @@ static struct stm32l5_serial_s g_usart2priv =
.size = CONFIG_USART2_TXBUFSIZE,
.buffer = g_usart2txbuffer,
},
#ifdef CONFIG_USART2_RXDMA
# ifdef CONFIG_USART2_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart2priv,
},
@ -596,27 +596,27 @@ static struct stm32l5_serial_s g_usart2priv =
.usartbase = STM32L5_USART2_BASE,
.tx_gpio = GPIO_USART2_TX,
.rx_gpio = GPIO_USART2_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART2_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART2_RTS,
#endif
#ifdef CONFIG_USART2_RXDMA
# endif
# ifdef CONFIG_USART2_RXDMA
.rxdma_channel = DMAMAP_USART2_RX,
.rxfifo = g_usart2rxfifo,
#endif
# endif
#ifdef CONFIG_USART2_RS485
# ifdef CONFIG_USART2_RS485
.rs485_dir_gpio = GPIO_USART2_RS485_DIR,
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -627,9 +627,9 @@ static struct stm32l5_serial_s g_usart3priv =
{
.dev =
{
#if CONSOLE_UART == 4
# if CONSOLE_UART == 4
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART3_RXBUFSIZE,
@ -640,11 +640,11 @@ static struct stm32l5_serial_s g_usart3priv =
.size = CONFIG_USART3_TXBUFSIZE,
.buffer = g_usart3txbuffer,
},
#ifdef CONFIG_USART3_RXDMA
# ifdef CONFIG_USART3_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart3priv,
},
@ -657,27 +657,27 @@ static struct stm32l5_serial_s g_usart3priv =
.usartbase = STM32L5_USART3_BASE,
.tx_gpio = GPIO_USART3_TX,
.rx_gpio = GPIO_USART3_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART3_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART3_RTS,
#endif
#ifdef CONFIG_USART3_RXDMA
# endif
# ifdef CONFIG_USART3_RXDMA
.rxdma_channel = DMAMAP_USART3_RX,
.rxfifo = g_usart3rxfifo,
#endif
# endif
#ifdef CONFIG_USART3_RS485
# ifdef CONFIG_USART3_RS485
.rs485_dir_gpio = GPIO_USART3_RS485_DIR,
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -688,9 +688,9 @@ static struct stm32l5_serial_s g_uart4priv =
{
.dev =
{
#if CONSOLE_UART == 5
# if CONSOLE_UART == 5
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_UART4_RXBUFSIZE,
@ -701,11 +701,11 @@ static struct stm32l5_serial_s g_uart4priv =
.size = CONFIG_UART4_TXBUFSIZE,
.buffer = g_uart4txbuffer,
},
#ifdef CONFIG_UART4_RXDMA
# ifdef CONFIG_UART4_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart4priv,
},
@ -713,32 +713,32 @@ static struct stm32l5_serial_s g_uart4priv =
.parity = CONFIG_UART4_PARITY,
.bits = CONFIG_UART4_BITS,
.stopbits2 = CONFIG_UART4_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_UART4_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_UART4_RTS,
#endif
# endif
.baud = CONFIG_UART4_BAUD,
.apbclock = STM32L5_PCLK1_FREQUENCY,
.usartbase = STM32L5_UART4_BASE,
.tx_gpio = GPIO_UART4_TX,
.rx_gpio = GPIO_UART4_RX,
#ifdef CONFIG_UART4_RXDMA
# ifdef CONFIG_UART4_RXDMA
.rxdma_channel = DMAMAP_UART4_RX,
.rxfifo = g_uart4rxfifo,
#endif
# endif
#ifdef CONFIG_UART4_RS485
# ifdef CONFIG_UART4_RS485
.rs485_dir_gpio = GPIO_UART4_RS485_DIR,
# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -749,9 +749,9 @@ static struct stm32l5_serial_s g_uart5priv =
{
.dev =
{
#if CONSOLE_UART == 6
# if CONSOLE_UART == 6
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_UART5_RXBUFSIZE,
@ -762,11 +762,11 @@ static struct stm32l5_serial_s g_uart5priv =
.size = CONFIG_UART5_TXBUFSIZE,
.buffer = g_uart5txbuffer,
},
#ifdef CONFIG_UART5_RXDMA
# ifdef CONFIG_UART5_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart5priv,
},
@ -774,32 +774,32 @@ static struct stm32l5_serial_s g_uart5priv =
.parity = CONFIG_UART5_PARITY,
.bits = CONFIG_UART5_BITS,
.stopbits2 = CONFIG_UART5_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_UART5_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_UART5_RTS,
#endif
# endif
.baud = CONFIG_UART5_BAUD,
.apbclock = STM32L5_PCLK1_FREQUENCY,
.usartbase = STM32L5_UART5_BASE,
.tx_gpio = GPIO_UART5_TX,
.rx_gpio = GPIO_UART5_RX,
#ifdef CONFIG_UART5_RXDMA
# ifdef CONFIG_UART5_RXDMA
.rxdma_channel = DMAMAP_UART5_RX,
.rxfifo = g_uart5rxfifo,
#endif
# endif
#ifdef CONFIG_UART5_RS485
# ifdef CONFIG_UART5_RS485
.rs485_dir_gpio = GPIO_UART5_RS485_DIR,
# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif

2
arch/arm/src/stm32u5/stm32_lse.c
View File

@ -39,7 +39,7 @@
# if CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
# endif
#endif
/****************************************************************************

164
arch/arm/src/stm32u5/stm32_serial.c
View File

@ -358,9 +358,9 @@ static const struct uart_ops_s g_uart_ops =
.receive = stm32serial_receive,
.rxint = stm32serial_rxint,
.rxavailable = stm32serial_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
# ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = stm32serial_rxflowcontrol,
#endif
# endif
.send = stm32serial_send,
.txint = stm32serial_txint,
.txready = stm32serial_txready,
@ -379,9 +379,9 @@ static const struct uart_ops_s g_uart_dma_ops =
.receive = stm32serial_dmareceive,
.rxint = stm32serial_dmarxint,
.rxavailable = stm32serial_dmarxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
# ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = stm32serial_rxflowcontrol,
#endif
# endif
.send = stm32serial_send,
.txint = stm32serial_txint,
.txready = stm32serial_txready,
@ -446,9 +446,9 @@ static struct stm32_serial_s g_lpuart1priv =
{
.dev =
{
#if CONSOLE_UART == 1
# if CONSOLE_UART == 1
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_LPUART1_RXBUFSIZE,
@ -459,11 +459,11 @@ static struct stm32_serial_s g_lpuart1priv =
.size = CONFIG_LPUART1_TXBUFSIZE,
.buffer = g_lpuart1txbuffer,
},
#ifdef CONFIG_LPUART1_RXDMA
# ifdef CONFIG_LPUART1_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_lpuart1priv,
},
@ -476,27 +476,27 @@ static struct stm32_serial_s g_lpuart1priv =
.usartbase = STM32_LPUART1_BASE,
.tx_gpio = GPIO_LPUART1_TX,
.rx_gpio = GPIO_LPUART1_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_LPUART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_LPUART1_RTS,
#endif
#ifdef CONFIG_LPUART1_RXDMA
# endif
# ifdef CONFIG_LPUART1_RXDMA
.rxdma_channel = DMAMAP_LPUSART_RX,
.rxfifo = g_lpuart1rxfifo,
#endif
# endif
#ifdef CONFIG_USART1_RS485
# ifdef CONFIG_USART1_RS485
.rs485_dir_gpio = GPIO_LPUART1_RS485_DIR,
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -505,9 +505,9 @@ static struct stm32_serial_s g_usart1priv =
{
.dev =
{
#if CONSOLE_UART == 2
# if CONSOLE_UART == 2
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART1_RXBUFSIZE,
@ -518,11 +518,11 @@ static struct stm32_serial_s g_usart1priv =
.size = CONFIG_USART1_TXBUFSIZE,
.buffer = g_usart1txbuffer,
},
#ifdef CONFIG_USART1_RXDMA
# ifdef CONFIG_USART1_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart1priv,
},
@ -535,27 +535,27 @@ static struct stm32_serial_s g_usart1priv =
.usartbase = STM32_USART1_BASE,
.tx_gpio = GPIO_USART1_TX,
.rx_gpio = GPIO_USART1_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART1_RTS,
#endif
#ifdef CONFIG_USART1_RXDMA
# endif
# ifdef CONFIG_USART1_RXDMA
.rxdma_channel = DMAMAP_USART1_RX,
.rxfifo = g_usart1rxfifo,
#endif
# endif
#ifdef CONFIG_USART1_RS485
# ifdef CONFIG_USART1_RS485
.rs485_dir_gpio = GPIO_USART1_RS485_DIR,
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -566,9 +566,9 @@ static struct stm32_serial_s g_usart2priv =
{
.dev =
{
#if CONSOLE_UART == 3
# if CONSOLE_UART == 3
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART2_RXBUFSIZE,
@ -579,11 +579,11 @@ static struct stm32_serial_s g_usart2priv =
.size = CONFIG_USART2_TXBUFSIZE,
.buffer = g_usart2txbuffer,
},
#ifdef CONFIG_USART2_RXDMA
# ifdef CONFIG_USART2_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart2priv,
},
@ -596,27 +596,27 @@ static struct stm32_serial_s g_usart2priv =
.usartbase = STM32_USART2_BASE,
.tx_gpio = GPIO_USART2_TX,
.rx_gpio = GPIO_USART2_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART2_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART2_RTS,
#endif
#ifdef CONFIG_USART2_RXDMA
# endif
# ifdef CONFIG_USART2_RXDMA
.rxdma_channel = DMAMAP_USART2_RX,
.rxfifo = g_usart2rxfifo,
#endif
# endif
#ifdef CONFIG_USART2_RS485
# ifdef CONFIG_USART2_RS485
.rs485_dir_gpio = GPIO_USART2_RS485_DIR,
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -627,9 +627,9 @@ static struct stm32_serial_s g_usart3priv =
{
.dev =
{
#if CONSOLE_UART == 4
# if CONSOLE_UART == 4
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART3_RXBUFSIZE,
@ -640,11 +640,11 @@ static struct stm32_serial_s g_usart3priv =
.size = CONFIG_USART3_TXBUFSIZE,
.buffer = g_usart3txbuffer,
},
#ifdef CONFIG_USART3_RXDMA
# ifdef CONFIG_USART3_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart3priv,
},
@ -657,27 +657,27 @@ static struct stm32_serial_s g_usart3priv =
.usartbase = STM32_USART3_BASE,
.tx_gpio = GPIO_USART3_TX,
.rx_gpio = GPIO_USART3_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART3_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART3_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART3_RTS,
#endif
#ifdef CONFIG_USART3_RXDMA
# endif
# ifdef CONFIG_USART3_RXDMA
.rxdma_channel = DMAMAP_USART3_RX,
.rxfifo = g_usart3rxfifo,
#endif
# endif
#ifdef CONFIG_USART3_RS485
# ifdef CONFIG_USART3_RS485
.rs485_dir_gpio = GPIO_USART3_RS485_DIR,
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -688,9 +688,9 @@ static struct stm32_serial_s g_uart4priv =
{
.dev =
{
#if CONSOLE_UART == 5
# if CONSOLE_UART == 5
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_UART4_RXBUFSIZE,
@ -701,11 +701,11 @@ static struct stm32_serial_s g_uart4priv =
.size = CONFIG_UART4_TXBUFSIZE,
.buffer = g_uart4txbuffer,
},
#ifdef CONFIG_UART4_RXDMA
# ifdef CONFIG_UART4_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart4priv,
},
@ -713,32 +713,32 @@ static struct stm32_serial_s g_uart4priv =
.parity = CONFIG_UART4_PARITY,
.bits = CONFIG_UART4_BITS,
.stopbits2 = CONFIG_UART4_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_UART4_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_UART4_RTS,
#endif
# endif
.baud = CONFIG_UART4_BAUD,
.apbclock = STM32_PCLK1_FREQUENCY,
.usartbase = STM32_UART4_BASE,
.tx_gpio = GPIO_UART4_TX,
.rx_gpio = GPIO_UART4_RX,
#ifdef CONFIG_UART4_RXDMA
# ifdef CONFIG_UART4_RXDMA
.rxdma_channel = DMAMAP_UART4_RX,
.rxfifo = g_uart4rxfifo,
#endif
# endif
#ifdef CONFIG_UART4_RS485
# ifdef CONFIG_UART4_RS485
.rs485_dir_gpio = GPIO_UART4_RS485_DIR,
# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -749,9 +749,9 @@ static struct stm32_serial_s g_uart5priv =
{
.dev =
{
#if CONSOLE_UART == 6
# if CONSOLE_UART == 6
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_UART5_RXBUFSIZE,
@ -762,11 +762,11 @@ static struct stm32_serial_s g_uart5priv =
.size = CONFIG_UART5_TXBUFSIZE,
.buffer = g_uart5txbuffer,
},
#ifdef CONFIG_UART5_RXDMA
# ifdef CONFIG_UART5_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_uart5priv,
},
@ -774,32 +774,32 @@ static struct stm32_serial_s g_uart5priv =
.parity = CONFIG_UART5_PARITY,
.bits = CONFIG_UART5_BITS,
.stopbits2 = CONFIG_UART5_2STOP,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_UART5_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_UART5_RTS,
#endif
# endif
.baud = CONFIG_UART5_BAUD,
.apbclock = STM32_PCLK1_FREQUENCY,
.usartbase = STM32_UART5_BASE,
.tx_gpio = GPIO_UART5_TX,
.rx_gpio = GPIO_UART5_RX,
#ifdef CONFIG_UART5_RXDMA
# ifdef CONFIG_UART5_RXDMA
.rxdma_channel = DMAMAP_UART5_RX,
.rxfifo = g_uart5rxfifo,
#endif
# endif
#ifdef CONFIG_UART5_RS485
# ifdef CONFIG_UART5_RS485
.rs485_dir_gpio = GPIO_UART5_RS485_DIR,
# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif

4
arch/arm/src/stm32wb/stm32wb_rcc_lse.c
View File

@ -37,14 +37,14 @@
# if CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
# endif
#endif
#ifdef CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY
# if CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \
CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
# endif
#endif
/****************************************************************************

2
arch/arm/src/stm32wl5/stm32wl5_lse.c
View File

@ -40,7 +40,7 @@
# if CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
# endif
#endif
/****************************************************************************

74
arch/arm/src/stm32wl5/stm32wl5_serial.c
View File

@ -394,9 +394,9 @@ static struct stm32wl5_serial_s g_lpuart1priv =
{
.dev =
{
#if CONSOLE_UART == 1
# if CONSOLE_UART == 1
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_LPUART1_RXBUFSIZE,
@ -407,11 +407,11 @@ static struct stm32wl5_serial_s g_lpuart1priv =
.size = CONFIG_LPUART1_TXBUFSIZE,
.buffer = g_lpuart1txbuffer,
},
#ifdef CONFIG_LPUART1_RXDMA
# ifdef CONFIG_LPUART1_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_lpuart1priv,
},
@ -424,27 +424,27 @@ static struct stm32wl5_serial_s g_lpuart1priv =
.usartbase = STM32WL5_LPUART1_BASE,
.tx_gpio = GPIO_LPUART1_TX,
.rx_gpio = GPIO_LPUART1_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_LPUART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_LPUART1_RTS,
#endif
#ifdef CONFIG_LPUART1_RXDMA
# endif
# ifdef CONFIG_LPUART1_RXDMA
.rxdma_channel = DMAMAP_LPUSART_RX,
.rxfifo = g_lpuart1rxfifo,
#endif
# endif
#ifdef CONFIG_USART1_RS485
# ifdef CONFIG_USART1_RS485
.rs485_dir_gpio = GPIO_LPUART1_RS485_DIR,
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif
@ -453,9 +453,9 @@ static struct stm32wl5_serial_s g_usart1priv =
{
.dev =
{
#if CONSOLE_UART == 2
# if CONSOLE_UART == 2
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART1_RXBUFSIZE,
@ -466,11 +466,11 @@ static struct stm32wl5_serial_s g_usart1priv =
.size = CONFIG_USART1_TXBUFSIZE,
.buffer = g_usart1txbuffer,
},
#ifdef CONFIG_USART1_RXDMA
# ifdef CONFIG_USART1_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart1priv,
},
@ -483,18 +483,18 @@ static struct stm32wl5_serial_s g_usart1priv =
.usartbase = STM32WL5_USART1_BASE,
.tx_gpio = GPIO_USART1_TX,
.rx_gpio = GPIO_USART1_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART1_RTS,
#endif
#ifdef CONFIG_USART1_RXDMA
# endif
# ifdef CONFIG_USART1_RXDMA
.rxdma_channel = DMAMAP_USART1_RX,
.rxfifo = g_usart1rxfifo,
#endif
# endif
#ifdef CONFIG_USART1_RS485
.rs485_dir_gpio = GPIO_USART1_RS485_DIR,
@ -514,9 +514,9 @@ static struct stm32wl5_serial_s g_usart2priv =
{
.dev =
{
#if CONSOLE_UART == 3
# if CONSOLE_UART == 3
.isconsole = true,
#endif
# endif
.recv =
{
.size = CONFIG_USART2_RXBUFSIZE,
@ -527,11 +527,11 @@ static struct stm32wl5_serial_s g_usart2priv =
.size = CONFIG_USART2_TXBUFSIZE,
.buffer = g_usart2txbuffer,
},
#ifdef CONFIG_USART2_RXDMA
# ifdef CONFIG_USART2_RXDMA
.ops = &g_uart_dma_ops,
#else
# else
.ops = &g_uart_ops,
#endif
# endif
.priv = &g_usart2priv,
},
@ -544,27 +544,27 @@ static struct stm32wl5_serial_s g_usart2priv =
.usartbase = STM32WL5_USART2_BASE,
.tx_gpio = GPIO_USART2_TX,
.rx_gpio = GPIO_USART2_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART2_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL)
# endif
# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART2_RTS,
#endif
#ifdef CONFIG_USART2_RXDMA
# endif
# ifdef CONFIG_USART2_RXDMA
.rxdma_channel = DMAMAP_USART2_RX,
.rxfifo = g_usart2rxfifo,
#endif
# endif
#ifdef CONFIG_USART2_RS485
# ifdef CONFIG_USART2_RS485
.rs485_dir_gpio = GPIO_USART2_RS485_DIR,
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
# endif
};
#endif

4
arch/arm/src/tiva/common/tiva_sock_can.c
View File

@ -1774,12 +1774,12 @@ static int tivacan_setup(struct net_driver_s *dev)
case 0:
tivacan_bittiming_set(dev, CONFIG_TIVA_CAN0_BAUD * 1000);
break;
# endif /* CONFIG_TIVA_CAN0 */
#endif /* CONFIG_TIVA_CAN0 */
#ifdef CONFIG_TIVA_CAN1
case 1:
tivacan_bittiming_set(dev, CONFIG_TIVA_CAN1_BAUD * 1000);
break;
# endif /* CONFIG_TIVA_CAN1 */
#endif /* CONFIG_TIVA_CAN1 */
}
nxmutex_lock(&canmod->thd_iface_lock);

4
arch/arm/src/tlsr82/tc32/tc32_initialstate.c
View File

@ -144,9 +144,9 @@ void up_initial_state(struct tcb_s *tcb)
/* Enable or disable interrupts, based on user configuration */
# ifdef CONFIG_SUPPRESS_INTERRUPTS
#ifdef CONFIG_SUPPRESS_INTERRUPTS
cpsr |= PSR_I_BIT;
# endif
#endif
xcp->regs[REG_CPSR] = cpsr;
}

4
arch/ceva/src/common/ceva_svcall.c
View File

@ -72,9 +72,9 @@ int ceva_svcall(int irq, void *context, void *arg)
regs[REG_FP], regs[REG_LR], regs[REG_PC], regs[REG_IRQ],
# ifdef REG_OM
regs[REG_OM]
#else
# else
0x00000000
#endif
# endif
);
}
#endif

2
arch/hc/include/hc12/types.h
View File

@ -58,7 +58,7 @@ typedef unsigned short _uint16_t;
* then an integer is 32-bits. GCC will defined __INT__ accordingly:
*/
# if __INT__ == 16
#if __INT__ == 16
typedef signed long _int32_t;
typedef unsigned long _uint32_t;
#else

2
arch/hc/include/hcs12/types.h
View File

@ -59,7 +59,7 @@ typedef unsigned short _uint16_t;
* then an integer is 32-bits. GCC will defined __INT__ accordingly:
*/
# if __INT__ == 16
#if __INT__ == 16
typedef signed long _int32_t;
typedef unsigned long _uint32_t;
#else

6
arch/hc/src/m9s12/m9s12_initialstate.c
View File

@ -113,13 +113,13 @@ void up_initial_state(struct tcb_s *tcb)
* Bit 7: S STOP instruction control bit
*/
# ifdef CONFIG_SUPPRESS_INTERRUPTS
#ifdef CONFIG_SUPPRESS_INTERRUPTS
/* Disable STOP, Mask I- and Z- interrupts */
xcp->regs[REG_CCR] = HCS12_CCR_S | HCS12_CCR_X | HCS12_CCR_I;
# else
#else
/* Disable STOP, Enable I- and Z-interrupts */
xcp->regs[REG_CCR] = HCS12_CCR_S;
# endif
#endif
}

12
arch/risc-v/src/common/riscv_pmp.c
View File

@ -202,7 +202,7 @@ static bool pmp_check_region_attrs(uintptr_t base, uintptr_t size)
static uintptr_t pmp_read_region_cfg(uintptr_t region)
{
# if (PMP_XLEN == 32)
#if (PMP_XLEN == 32)
switch (region)
{
case 0 ... 3:
@ -220,7 +220,7 @@ static uintptr_t pmp_read_region_cfg(uintptr_t region)
default:
break;
}
# elif (PMP_XLEN == 64)
#elif (PMP_XLEN == 64)
switch (region)
{
case 0 ... 7:
@ -542,7 +542,7 @@ int riscv_config_pmp_region(uintptr_t region, uintptr_t attr,
/* Set the configuration register value */
# if (PMP_XLEN == 32)
#if (PMP_XLEN == 32)
switch (region)
{
case 0 ... 3:
@ -572,7 +572,7 @@ int riscv_config_pmp_region(uintptr_t region, uintptr_t attr,
default:
break;
}
# elif (PMP_XLEN == 64)
#elif (PMP_XLEN == 64)
switch (region)
{
case 0 ... 7:
@ -590,9 +590,9 @@ int riscv_config_pmp_region(uintptr_t region, uintptr_t attr,
default:
break;
}
# else
#else
# error "XLEN of risc-v not supported"
# endif
#endif
#ifdef CONFIG_ARCH_USE_S_MODE
/* Fence is needed when page-based virtual memory is implemented.

2
arch/risc-v/src/esp32c6/esp32c6_lowputc.c
View File

@ -117,7 +117,7 @@ static struct esp32c6_uart_s g_uart1_config =
.stop_b2 = CONFIG_UART1_2STOP,
.int_pri = 1
};
#endif /* CONFIG_UART0_SERIAL_CONSOLE */
# endif /* CONFIG_UART0_SERIAL_CONSOLE */
#endif /* HAVE_SERIAL_CONSOLE */
#endif

4
arch/xtensa/src/esp32s2/esp32s2_lowputc.c
View File

@ -742,9 +742,9 @@ void xtensa_lowputc(char ch)
{
#ifdef HAVE_SERIAL_CONSOLE
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
# if defined(CONFIG_UART0_SERIAL_CONSOLE)
struct esp32s2_uart_s *priv = &g_uart0_config;
#elif defined (CONFIG_UART1_SERIAL_CONSOLE)
# elif defined (CONFIG_UART1_SERIAL_CONSOLE)
struct esp32s2_uart_s *priv = &g_uart1_config;
# endif

72
boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c
View File

@ -96,78 +96,78 @@
#if defined(CONFIG_STM32_SPI1)
static const uint32_t g_spi1gpio[] =
{
#if defined(GPIO_SPI1_CS0)
# if defined(GPIO_SPI1_CS0)
GPIO_SPI1_CS0,
#else
# else
0,
#endif
#if defined(GPIO_SPI1_CS1)
# endif
# if defined(GPIO_SPI1_CS1)
GPIO_SPI1_CS1,
#else
# else
0,
#endif
#if defined(GPIO_SPI1_CS2)
# endif
# if defined(GPIO_SPI1_CS2)
GPIO_SPI1_CS2,
#else
# else
0,
#endif
#if defined(GPIO_SPI1_CS3)
# endif
# if defined(GPIO_SPI1_CS3)
GPIO_SPI1_CS3
#else
# else
0
#endif
# endif
};
#endif
#if defined(CONFIG_STM32_SPI2)
static const uint32_t g_spi2gpio[] =
{
#if defined(GPIO_SPI2_CS0)
# if defined(GPIO_SPI2_CS0)
GPIO_SPI2_CS0,
#else
# else
0,
#endif
#if defined(GPIO_SPI2_CS1)
# endif
# if defined(GPIO_SPI2_CS1)
GPIO_SPI2_CS1,
#else
# else
0,
#endif
#if defined(GPIO_SPI2_CS2)
# endif
# if defined(GPIO_SPI2_CS2)
GPIO_SPI2_CS2,
#else
# else
0,
#endif
#if defined(GPIO_SPI2_CS3)
# endif
# if defined(GPIO_SPI2_CS3)
GPIO_SPI2_CS3
#else
# else
0
#endif
# endif
};
#endif
#if defined(CONFIG_STM32_SPI3)
static const uint32_t g_spi3gpio[] =
{
#if defined(GPIO_SPI3_CS0)
# if defined(GPIO_SPI3_CS0)
GPIO_SPI3_CS0,
#else
# else
0,
#endif
#if defined(GPIO_SPI3_CS1)
# endif
# if defined(GPIO_SPI3_CS1)
GPIO_SPI3_CS1,
#else
# else
0,
#endif
#if defined(GPIO_SPI3_CS2)
# endif
# if defined(GPIO_SPI3_CS2)
GPIO_SPI3_CS2,
#else
# else
0,
#endif
#if defined(GPIO_SPI3_CS3)
# endif
# if defined(GPIO_SPI3_CS3)
GPIO_SPI3_CS3
#else
# else
0
#endif
# endif
};
#endif

2
boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c
View File

@ -1006,7 +1006,7 @@ static int stm3210e_poweroff(void)
#if defined(CONFIG_STM3210E_LCD_BACKLIGHT)
# if defined(CONFIG_STM3210E_LCD_PWM)
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
#endif
# endif
/* Configure the PA8 pin as an output */

72
boards/arm/stm32f7/nucleo-144/src/stm32_spi.c
View File

@ -96,78 +96,78 @@
#if defined(CONFIG_STM32F7_SPI1)
static const uint32_t g_spi1gpio[] =
{
#if defined(GPIO_SPI1_CS0)
# if defined(GPIO_SPI1_CS0)
GPIO_SPI1_CS0,
#else
# else
0,
#endif
#if defined(GPIO_SPI1_CS1)
# endif
# if defined(GPIO_SPI1_CS1)
GPIO_SPI1_CS1,
#else
# else
0,
#endif
#if defined(GPIO_SPI1_CS2)
# endif
# if defined(GPIO_SPI1_CS2)
GPIO_SPI1_CS2,
#else
# else
0,
#endif
#if defined(GPIO_SPI1_CS3)
# endif
# if defined(GPIO_SPI1_CS3)
GPIO_SPI1_CS3
#else
# else
0
#endif
# endif
};
#endif
#if defined(CONFIG_STM32F7_SPI2)
static const uint32_t g_spi2gpio[] =
{
#if defined(GPIO_SPI2_CS0)
# if defined(GPIO_SPI2_CS0)
GPIO_SPI2_CS0,
#else
# else
0,
#endif
#if defined(GPIO_SPI2_CS1)
# endif
# if defined(GPIO_SPI2_CS1)
GPIO_SPI2_CS1,
#else
# else
0,
#endif
#if defined(GPIO_SPI2_CS2)
# endif
# if defined(GPIO_SPI2_CS2)
GPIO_SPI2_CS2,
#else
# else
0,
#endif
#if defined(GPIO_SPI2_CS3)
# endif
# if defined(GPIO_SPI2_CS3)
GPIO_SPI2_CS3
#else
# else
0
#endif
# endif
};
#endif
#if defined(CONFIG_STM32F7_SPI3)
static const uint32_t g_spi3gpio[] =
{
#if defined(GPIO_SPI3_CS0)
# if defined(GPIO_SPI3_CS0)
GPIO_SPI3_CS0,
#else
# else
0,
#endif
#if defined(GPIO_SPI3_CS1)
# endif
# if defined(GPIO_SPI3_CS1)
GPIO_SPI3_CS1,
#else
# else
0,
#endif
#if defined(GPIO_SPI3_CS2)
# endif
# if defined(GPIO_SPI3_CS2)
GPIO_SPI3_CS2,
#else
# else
0,
#endif
#if defined(GPIO_SPI3_CS3)
# endif
# if defined(GPIO_SPI3_CS3)
GPIO_SPI3_CS3
#else
# else
0
#endif
# endif
};
#endif

2
boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h
View File

@ -153,7 +153,7 @@
#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
# define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6)
#ifdef CONFIG_USBHOST

2
boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h
View File

@ -89,7 +89,7 @@
#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
# define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \
GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN10)
#ifdef CONFIG_USBHOST

72
boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c
View File

@ -96,78 +96,78 @@
#if defined(CONFIG_STM32L4_SPI1)
static const uint32_t g_spi1gpio[] =
{
#if defined(GPIO_SPI1_CS0)
# if defined(GPIO_SPI1_CS0)
GPIO_SPI1_CS0,
#else
# else
0,
#endif
#if defined(GPIO_SPI1_CS1)
# endif
# if defined(GPIO_SPI1_CS1)
GPIO_SPI1_CS1,
#else
# else
0,
#endif
#if defined(GPIO_SPI1_CS2)
# endif
# if defined(GPIO_SPI1_CS2)
GPIO_SPI1_CS2,
#else
# else
0,
#endif
#if defined(GPIO_SPI1_CS3)
# endif
# if defined(GPIO_SPI1_CS3)
GPIO_SPI1_CS3
#else
# else
0
#endif
# endif
};
#endif
#if defined(CONFIG_STM32L4_SPI2)
static const uint32_t g_spi2gpio[] =
{
#if defined(GPIO_SPI2_CS0)
# if defined(GPIO_SPI2_CS0)
GPIO_SPI2_CS0,
#else
# else
0,
#endif
#if defined(GPIO_SPI2_CS1)
# endif
# if defined(GPIO_SPI2_CS1)
GPIO_SPI2_CS1,
#else
# else
0,
#endif
#if defined(GPIO_SPI2_CS2)
# endif
# if defined(GPIO_SPI2_CS2)
GPIO_SPI2_CS2,
#else
# else
0,
#endif
#if defined(GPIO_SPI2_CS3)
# endif
# if defined(GPIO_SPI2_CS3)
GPIO_SPI2_CS3
#else
# else
0
#endif
# endif
};
#endif
#if defined(CONFIG_STM32L4_SPI3)
static const uint32_t g_spi3gpio[] =
{
#if defined(GPIO_SPI3_CS0)
# if defined(GPIO_SPI3_CS0)
GPIO_SPI3_CS0,
#else
# else
0,
#endif
#if defined(GPIO_SPI3_CS1)
# endif
# if defined(GPIO_SPI3_CS1)
GPIO_SPI3_CS1,
#else
# else
0,
#endif
#if defined(GPIO_SPI3_CS2)
# endif
# if defined(GPIO_SPI3_CS2)
GPIO_SPI3_CS2,
#else
# else
0,
#endif
#if defined(GPIO_SPI3_CS3)
# endif
# if defined(GPIO_SPI3_CS3)
GPIO_SPI3_CS3
#else
# else
0
#endif
# endif
};
#endif

22
graphics/nxglib/fb/nxglib_setpixel.c
View File

@ -78,40 +78,40 @@ void NXGL_FUNCNAME(nxgl_setpixel, NXGLIB_SUFFIX)
# ifdef CONFIG_NX_PACKEDMSFIRST
#if NXGLIB_BITSPERPIXEL == 1
# if NXGLIB_BITSPERPIXEL == 1
shift = (7 - (pos->x & 7)); /* Shift is 0, 1, ... 7 */
mask = (1 << shift); /* Mask is 0x01, 0x02, .. 0x80 */
color <<= shift; /* Color is positioned under the mask */
#elif NXGLIB_BITSPERPIXEL == 2
# elif NXGLIB_BITSPERPIXEL == 2
shift = (6 - ((pos->x & 3) << 1)); /* Shift is 0, 2, 4, or 6 */
mask = (3 << shift); /* Mask is 0x03, 0x0c, 0x30, or 0xc0 */
color <<= shift; /* Color is positioned under the mask */
#elif NXGLIB_BITSPERPIXEL == 4
# elif NXGLIB_BITSPERPIXEL == 4
shift = (4 - ((pos->x & 1) << 2)); /* Shift is 0 or 4 */
mask = (15 << shift); /* Mask is 0x0f or 0xf0 */
color <<= shift; /* Color is positioned under the mask */
#else
# else
# error "Unsupported pixel depth"
#endif
# endif
# else /* CONFIG_NX_PACKEDMSFIRST */
#if NXGLIB_BITSPERPIXEL == 1
# if NXGLIB_BITSPERPIXEL == 1
shift = (pos->x & 7); /* Shift is 0, 1, ... 7 */
mask = (1 << shift); /* Mask is 0x01, 0x02, .. 0x80 */
color <<= shift; /* Color is positioned under the mask */
#elif NXGLIB_BITSPERPIXEL == 2
# elif NXGLIB_BITSPERPIXEL == 2
shift = (pos->x & 3) << 1; /* Shift is 0, 2, 4, or 6 */
mask = (3 << shift); /* Mask is 0x03, 0x0c, 0x30, or 0xc0 */
color <<= shift; /* Color is positioned under the mask */
#elif NXGLIB_BITSPERPIXEL == 4
# elif NXGLIB_BITSPERPIXEL == 4
shift = (pos->x & 1) << 2; /* Shift is 0 or 4 */
mask = (15 << shift); /* Mask is 0x0f or 0xf0 */
color <<= shift; /* Color is positioned under the mask */
#else
# else
# error "Unsupported pixel depth"
#endif
#endif /* CONFIG_NX_PACKEDMSFIRST */
# endif
# endif /* CONFIG_NX_PACKEDMSFIRST */
/* Handle masking of the fractional byte */

22
graphics/nxglib/lcd/nxglib_setpixel.c
View File

@ -73,39 +73,39 @@ void NXGL_FUNCNAME(nxgl_setpixel, NXGLIB_SUFFIX)
# ifdef CONFIG_NX_PACKEDMSFIRST
#if NXGLIB_BITSPERPIXEL == 1
# if NXGLIB_BITSPERPIXEL == 1
shift = (7 - (pos->x & 7)); /* Shift is 0, 1, ... 7 */
mask = (1 << shift); /* Mask is 0x01, 0x02, .. 0x80 */
color <<= shift; /* Color is positioned under the mask */
#elif NXGLIB_BITSPERPIXEL == 2
# elif NXGLIB_BITSPERPIXEL == 2
shift = (6 - ((pos->x & 3) << 1)); /* Shift is 0, 2, 4, or 6 */
mask = (3 << shift); /* Mask is 0x03, 0x0c, 0x30, or 0xc0 */
color <<= shift; /* Color is positioned under the mask */
#elif NXGLIB_BITSPERPIXEL == 4
# elif NXGLIB_BITSPERPIXEL == 4
shift = (4 - ((pos->x & 1) << 2)); /* Shift is 0 or 4 */
mask = (15 << shift); /* Mask is 0x0f or 0xf0 */
color <<= shift; /* Color is positioned under the mask */
#else
# else
# error "Unsupported pixel depth"
#endif
# endif
# else /* CONFIG_NX_PACKEDMSFIRST */
#else /* CONFIG_NX_PACKEDMSFIRST */
#if NXGLIB_BITSPERPIXEL == 1
# if NXGLIB_BITSPERPIXEL == 1
shift = (pos->x & 7); /* Shift is 0, 1, ... 7 */
mask = (1 << shift); /* Mask is 0x01, 0x02, .. 0x80 */
color <<= shift; /* Color is positioned under the mask */
#elif NXGLIB_BITSPERPIXEL == 2
# elif NXGLIB_BITSPERPIXEL == 2
shift = (pos->x & 3) << 1; /* Shift is 0, 2, 4, or 6 */
mask = (3 << shift); /* Mask is 0x03, 0x0c, 0x30, or 0xc0 */
color <<= shift; /* Color is positioned under the mask */
#elif NXGLIB_BITSPERPIXEL == 4
# elif NXGLIB_BITSPERPIXEL == 4
shift = (pos->x & 1) << 2; /* Shift is 0 or 4 */
mask = (15 << shift); /* Mask is 0x0f or 0xf0 */
color <<= shift; /* Color is positioned under the mask */
#else
# else
# error "Unsupported pixel depth"
#endif
# endif
#endif /* CONFIG_NX_PACKEDMSFIRST */
/* Handle masking of the fractional byte */

22
graphics/nxglib/pwfb/pwfb_setpixel.c
View File

@ -79,40 +79,40 @@ void NXGL_FUNCNAME(pwfb_setpixel, NXGLIB_SUFFIX)
# ifdef CONFIG_NX_PACKEDMSFIRST
#if NXGLIB_BITSPERPIXEL == 1
# if NXGLIB_BITSPERPIXEL == 1
shift = (7 - (pos->x & 7)); /* Shift is 0, 1, ... 7 */
mask = (1 << shift); /* Mask is 0x01, 0x02, .. 0x80 */
color <<= shift; /* Color is positioned under the mask */
#elif NXGLIB_BITSPERPIXEL == 2
# elif NXGLIB_BITSPERPIXEL == 2
shift = (6 - ((pos->x & 3) << 1)); /* Shift is 0, 2, 4, or 6 */
mask = (3 << shift); /* Mask is 0x03, 0x0c, 0x30, or 0xc0 */
color <<= shift; /* Color is positioned under the mask */
#elif NXGLIB_BITSPERPIXEL == 4
# elif NXGLIB_BITSPERPIXEL == 4
shift = (4 - ((pos->x & 1) << 2)); /* Shift is 0 or 4 */
mask = (15 << shift); /* Mask is 0x0f or 0xf0 */
color <<= shift; /* Color is positioned under the mask */
#else
# else
# error "Unsupported pixel depth"
#endif
# endif
# else /* CONFIG_NX_PACKEDMSFIRST */
#if NXGLIB_BITSPERPIXEL == 1
# if NXGLIB_BITSPERPIXEL == 1
shift = (pos->x & 7); /* Shift is 0, 1, ... 7 */
mask = (1 << shift); /* Mask is 0x01, 0x02, .. 0x80 */
color <<= shift; /* Color is positioned under the mask */
#elif NXGLIB_BITSPERPIXEL == 2
# elif NXGLIB_BITSPERPIXEL == 2
shift = (pos->x & 3) << 1; /* Shift is 0, 2, 4, or 6 */
mask = (3 << shift); /* Mask is 0x03, 0x0c, 0x30, or 0xc0 */
color <<= shift; /* Color is positioned under the mask */
#elif NXGLIB_BITSPERPIXEL == 4
# elif NXGLIB_BITSPERPIXEL == 4
shift = (pos->x & 1) << 2; /* Shift is 0 or 4 */
mask = (15 << shift); /* Mask is 0x0f or 0xf0 */
color <<= shift; /* Color is positioned under the mask */
#else
# else
# error "Unsupported pixel depth"
#endif
#endif /* CONFIG_NX_PACKEDMSFIRST */
# endif
# endif /* CONFIG_NX_PACKEDMSFIRST */
/* Handle masking of the fractional byte */

3
include/nuttx/semaphore.h
View File

@ -48,7 +48,8 @@
/* semcount, flags, waitlist, holder[2] */
# define NXSEM_INITIALIZER(c, f) \
{(c), (f), SEM_WAITLIST_INITIALIZER, {SEMHOLDER_INITIALIZER, SEMHOLDER_INITIALIZER}}
{(c), (f), SEM_WAITLIST_INITIALIZER, \
{SEMHOLDER_INITIALIZER, SEMHOLDER_INITIALIZER}}
# endif
#else /* CONFIG_PRIORITY_INHERITANCE */
/* semcount, flags, waitlist */

5
include/semaphore.h
View File

@ -132,7 +132,8 @@ typedef struct sem_s sem_t;
/* semcount, flags, waitlist, holder[2] */
# define SEM_INITIALIZER(c) \
{(c), 0, SEM_WAITLIST_INITIALIZER, {SEMHOLDER_INITIALIZER, SEMHOLDER_INITIALIZER}}
{(c), 0, SEM_WAITLIST_INITIALIZER, \
{SEMHOLDER_INITIALIZER, SEMHOLDER_INITIALIZER}}
# endif
#else
/* semcount, flags, waitlist */
@ -141,7 +142,7 @@ typedef struct sem_s sem_t;
{(c), 0, SEM_WAITLIST_INITIALIZER}
#endif
# define SEM_WAITLIST(sem) (&((sem)->waitlist))
#define SEM_WAITLIST(sem) (&((sem)->waitlist))
/****************************************************************************
* Public Data

4
net/can/can.h
View File

@ -101,9 +101,9 @@ struct can_conn_s
#ifdef CONFIG_NET_CANPROTO_OPTIONS
int32_t loopback;
int32_t recv_own_msgs;
#ifdef CONFIG_NET_CAN_CANFD
# ifdef CONFIG_NET_CAN_CANFD
int32_t fd_frames;
#endif
# endif
struct can_filter filters[CONFIG_NET_CAN_RAW_FILTER_MAX];
int32_t filter_count;
# ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE