diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index 124f800b5b..46154061f3 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -234,9 +234,9 @@ #define ESP32_IRQ_CPU_CPU2 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CPU_CPU2) #define ESP32_IRQ_CPU_CPU3 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_CPU_CPU3) #define ESP32_IRQ_SPI0 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI0) -#define ESP32_IRQ_SPI1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI1 +#define ESP32_IRQ_SPI1 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI1) #define ESP32_IRQ_SPI2 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI2) -#define ESP32_IRQ_SPI3 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI3 +#define ESP32_IRQ_SPI3 (XTENSA_IRQ_FIRSTPERIPH+ESP32_PERIPH_SPI3) #define ESP32_IRQ_SREG0 ESP32_IRQ_MAC #define ESP32_NIRQS_SREG0 32 diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig index 4a320d3325..8dfb28e279 100644 --- a/arch/xtensa/src/esp32/Kconfig +++ b/arch/xtensa/src/esp32/Kconfig @@ -81,25 +81,23 @@ config ESP32_SDMMC ---help--- No yet implemented -config ESP32_SPI0 - bool "SPI 0" +config ESP32_SPI + bool default n - depends on EXPERIMENTAL - ---help--- - No yet implemented - -config ESP32_SPI1 - bool "SPI 1" - default n - depends on EXPERIMENTAL - ---help--- - No yet implemented config ESP32_SPI2 bool "SPI 2" default n - ---help--- - No yet implemented + select ESP32_SPI + select ESP32_GPIO_IRQ + select SPI + +config ESP32_SPI3 + bool "SPI 3" + default n + select ESP32_SPI + select ESP32_GPIO_IRQ + select SPI config XTENSA_TIMER1 bool "Xtensa Timer 1" @@ -309,4 +307,58 @@ endif # SERIAL_IFLOWCONTROL || SERIAL_OFLOWCONTROL endif # ESP32_UART2 endmenu # UART configuration + +menu "SPI configuration" + depends on ESP32_SPI + +if ESP32_SPI2 + +config ESP32_SPI2_CSPIN + int "SPI2 CS Pin" + default 13 + range 0 39 + +config ESP32_SPI2_CLKPIN + int "SPI2 CLK Pin" + default 14 + range 0 39 + +config ESP32_SPI2_MOSIPIN + int "SPI2 MOSI Pin" + default 15 + range 0 39 + +config ESP32_SPI2_MISOPIN + int "SPI2 MISO Pin" + default 2 + range 0 39 + +endif # ESP32_SPI2 + +if ESP32_SPI3 + +config ESP32_SPI3_CSPIN + int "SPI3 CS Pin" + default 13 + range 0 39 + +config ESP32_SPI3_CLKPIN + int "SPI3 CLK Pin" + default 14 + range 0 39 + +config ESP32_SPI3_MOSIPIN + int "SPI3 MOSI Pin" + default 15 + range 0 39 + +config ESP32_SPI3_MISOPIN + int "SPI3 MISO Pin" + default 2 + range 0 39 + +endif # ESP32_SPI3 + +endmenu # ESP32_SPI + endif # ARCH_CHIP_ESP32 diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 67d1e6340c..c5e4b4aa73 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -100,6 +100,13 @@ CHIP_CSRCS += esp32_gpio.c esp32_intdecode.c esp32_irq.c esp32_region.c CHIP_CSRCS += esp32_timerisr.c CHIP_CSRCS += esp32_user.c +ifeq ($(CONFIG_ESP32_SPI),y) +CHIP_CSRCS += esp32_spi.c + ifeq ($(CONFIG_SPI_SLAVE),y) + CHIP_CSRCS += esp32_spi_slave.c + endif +endif + # Configuration-dependent ESP32 files ifeq ($(CONFIG_SMP),y) diff --git a/arch/xtensa/src/esp32/esp32_spi.c b/arch/xtensa/src/esp32/esp32_spi.c new file mode 100644 index 0000000000..9a274125f8 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_spi.c @@ -0,0 +1,1017 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_ESP32_SPI + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include "esp32_spi.h" +#include "esp32_gpio.h" +#include "esp32_cpuint.h" + +#include "xtensa.h" +#include "hardware/esp32_gpio_sigmap.h" +#include "hardware/esp32_dport.h" +#include "hardware/esp32_spi.h" +#include "hardware/esp32_soc.h" +#include "rom/esp32_gpio.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* SPI Default speed (limited by clock divider) */ + +#define SPI_FREQ_DEFAULT 400000 + +/* SPI Device hardware configuration */ + +struct esp32_spi_config_s +{ + uint32_t reg_base; /* SPI register base address */ + + uint32_t clk_freq; /* SPI clock frequency */ + enum spi_mode_e mode; /* SPI default mode */ + + uint8_t cs_pin; /* GPIO configuration for CS */ + uint8_t mosi_pin; /* GPIO configuration for MOSI */ + uint8_t miso_pin; /* GPIO configuration for MISO */ + uint8_t clk_pin; /* GPIO configuration for CLK */ + + uint8_t cpu; /* CPU ID */ + uint8_t periph; /* peripher ID */ + uint8_t irq; /* Interrupt ID */ + + uint32_t clk_bit; /* Clock enable bit */ + uint32_t rst_bit; /* SPI reset bit */ + + uint32_t cs_insig; /* SPI CS input signal index */ + uint32_t cs_outsig; /* SPI CS output signal index */ + uint32_t mosi_insig; /* SPI MOSI input signal index */ + uint32_t mosi_outsig; /* SPI MOSI output signal index */ + uint32_t miso_insig; /* SPI MISO input signal index */ + uint32_t miso_outsig; /* SPI MISO output signal index */ + uint32_t clk_insig; /* SPI CLK input signal index */ + uint32_t clk_outsig; /* SPI CLK output signal index */ +}; + +struct esp32_spi_priv_s +{ + /* Externally visible part of the SPI interface */ + + struct spi_dev_s spi_dev; + + /* Port configuration */ + + const struct esp32_spi_config_s *config; + + int refs; /* Referernce count */ + + /* Held while chip is selected for mutual exclusion */ + + sem_t exclsem; + + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + + enum spi_mode_e mode; /* Actual SPI hardware mode */ + + /* Actual SPI send/receive bits once transmission */ + + uint8_t nbits; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int esp32_spi_lock(FAR struct spi_dev_s *dev, bool lock); +static void esp32_spi_select(FAR struct spi_dev_s *dev, + uint32_t devid, + bool selected); +static uint32_t esp32_spi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency); +static void esp32_spi_setmode(FAR struct spi_dev_s *dev, + enum spi_mode_e mode); +static void esp32_spi_setbits(FAR struct spi_dev_s *dev, int nbits); +#ifdef CONFIG_SPI_HWFEATURES +static int esp32_spi_hwfeatures(FAR struct spi_dev_s *dev, + spi_hwfeatures_t features); +#endif +static uint32_t esp32_spi_send(FAR struct spi_dev_s *dev, uint32_t wd); +static void esp32_spi_exchange(FAR struct spi_dev_s *dev, + FAR const void *txbuffer, + FAR void *rxbuffer, size_t nwords); +#ifndef CONFIG_SPI_EXCHANGE +static void esp32_spi_sndblock(FAR struct spi_dev_s *dev, + FAR const void *txbuffer, + size_t nwords); +static void esp32_spi_recvblock(FAR struct spi_dev_s *dev, + FAR void *rxbuffer, + size_t nwords); +#endif +#ifdef CONFIG_SPI_TRIGGER +static int esp32_spi_trigger(FAR struct spi_dev_s *dev); +#endif +static void esp32_spi_init(FAR struct spi_dev_s *dev); +static void esp32_spi_deinit(FAR struct spi_dev_s *dev); + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_ESP32_SPI2 +static const struct esp32_spi_config_s esp32_spi2_config = +{ + .reg_base = REG_SPI_BASE(2), + .clk_freq = SPI_FREQ_DEFAULT, + .mode = SPIDEV_MODE0, + .cs_pin = CONFIG_ESP32_SPI2_CSPIN, + .mosi_pin = CONFIG_ESP32_SPI2_MOSIPIN, + .miso_pin = CONFIG_ESP32_SPI2_MISOPIN, + .clk_pin = CONFIG_ESP32_SPI2_CLKPIN, + .cpu = 0, + .periph = ESP32_PERIPH_SPI2, + .irq = ESP32_IRQ_SPI2, + .clk_bit = DPORT_SPI_CLK_EN_2, + .rst_bit = DPORT_SPI_RST_2, + .cs_insig = HSPICS0_IN_IDX, + .cs_outsig = HSPICS0_OUT_IDX, + .mosi_insig = HSPID_IN_IDX, + .mosi_outsig = HSPID_OUT_IDX, + .miso_insig = HSPIQ_IN_IDX, + .miso_outsig = HSPIQ_OUT_IDX, + .clk_insig = HSPICLK_IN_IDX, + .clk_outsig = HSPICLK_OUT_IDX +}; + +static const struct spi_ops_s esp32_spi2_ops = +{ + .lock = esp32_spi_lock, + .select = esp32_spi2_select, + .setfrequency = esp32_spi_setfrequency, + .setmode = esp32_spi_setmode, + .setbits = esp32_spi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = esp32_spi_hwfeatures, +#endif + .status = esp32_spi2_status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = esp32_spi2_cmddata, +#endif + .send = esp32_spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = esp32_spi_exchange, +#else + .sndblock = esp32_spi_sndblock, + .recvblock = esp32_spi_recvblock, +#endif +#ifdef CONFIG_SPI_TRIGGER + .trigger = esp32_spi_trigger, +#endif + .registercallback = NULL, +}; + +static struct esp32_spi_priv_s esp32_spi2_priv = +{ + .spi_dev = + { + .ops = &esp32_spi2_ops + }, + .config = &esp32_spi2_config +}; +#endif /* CONFIG_ESP32_SPI2 */ + +#ifdef CONFIG_ESP32_SPI3 +static const struct esp32_spi_config_s esp32_spi3_config = +{ + .reg_base = REG_SPI_BASE(3), + .clk_freq = SPI_FREQ_DEFAULT, + .mode = SPIDEV_MODE0, + .cs_pin = CONFIG_ESP32_SPI3_CSPIN, + .mosi_pin = CONFIG_ESP32_SPI3_MOSIPIN, + .miso_pin = CONFIG_ESP32_SPI3_MISOPIN, + .clk_pin = CONFIG_ESP32_SPI3_CLKPIN, + .cpu = 0, + .periph = ESP32_PERIPH_SPI3, + .irq = ESP32_IRQ_SPI3, + .clk_bit = DPORT_SPI_CLK_EN, + .rst_bit = DPORT_SPI_RST, + .cs_insig = VSPICS0_IN_IDX, + .cs_outsig = VSPICS0_OUT_IDX, + .mosi_insig = VSPID_IN_IDX, + .mosi_outsig = VSPID_OUT_IDX, + .miso_insig = VSPIQ_IN_IDX, + .miso_outsig = VSPIQ_OUT_IDX, + .clk_insig = VSPICLK_IN_IDX, + .clk_outsig = VSPICLK_OUT_MUX_IDX +}; + +static const struct spi_ops_s esp32_spi3_ops = +{ + .lock = esp32_spi_lock, + .select = esp32_spi3_select, + .setfrequency = esp32_spi_setfrequency, + .setmode = esp32_spi_setmode, + .setbits = esp32_spi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = esp32_spi_hwfeatures, +#endif + .status = esp32_spi3_status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = esp32_spi3_cmddata, +#endif + .send = esp32_spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = esp32_spi_exchange, +#else + .sndblock = esp32_spi_sndblock, + .recvblock = esp32_spi_recvblock, +#endif +#ifdef CONFIG_SPI_TRIGGER + .trigger = esp32_spi_trigger, +#endif + .registercallback = NULL, +}; + +static struct esp32_spi_priv_s esp32_spi3_priv = +{ + .spi_dev = + { + .ops = &esp32_spi3_ops + }, + .config = &esp32_spi3_config +}; +#endif /* CONFIG_ESP32_SPI3 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_spi_set_reg + * + * Description: + * Set the contents of the SPI register at offset + * + * Input Parameters: + * priv - Private SPI device structure + * offset - Offset to the register of interest + * value - Value to be written + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void esp32_spi_set_reg(struct esp32_spi_priv_s *priv, + int offset, + uint32_t value) +{ + putreg32(value, priv->config->reg_base + offset); +} + +/**************************************************************************** + * Name: esp32_spi_get_reg + * + * Description: + * Get the contents of the SPI register at offset + * + * Input Parameters: + * priv - Private SPI device structure + * offset - Offset to the register of interest + * + * Returned Value: + * The contents of the register + * + ****************************************************************************/ + +static inline uint32_t esp32_spi_get_reg(struct esp32_spi_priv_s *priv, + int offset) +{ + return getreg32(priv->config->reg_base + offset); +} + +/**************************************************************************** + * Name: esp32_spi_set_regbits + * + * Description: + * Set the bits of the SPI register at offset + * + * Input Parameters: + * priv - Private SPI device structure + * offset - Offset to the register of interest + * bits - Bits to be set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void esp32_spi_set_regbits(struct esp32_spi_priv_s *priv, + int offset, + uint32_t bits) +{ + uint32_t tmp = getreg32(priv->config->reg_base + offset); + + putreg32(tmp | bits, priv->config->reg_base + offset); +} + +/**************************************************************************** + * Name: esp32_spi_reset_regbits + * + * Description: + * Clear the bits of the SPI register at offset + * + * Input Parameters: + * priv - Private SPI device structure + * offset - Offset to the register of interest + * bits - Bits to be cleared + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void esp32_spi_reset_regbits(struct esp32_spi_priv_s *priv, + int offset, + uint32_t bits) +{ + uint32_t tmp = getreg32(priv->config->reg_base + offset); + + putreg32(tmp & (~bits), priv->config->reg_base + offset); +} + +/**************************************************************************** + * Name: esp32_spi_lock + * + * Description: + * Lock or unlock the SPI device + * + * Input Parameters: + * priv - Private SPI device structure + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * The result of lock or unlock the SPI device + * + ****************************************************************************/ + +static int esp32_spi_lock(FAR struct spi_dev_s *dev, bool lock) +{ + int ret; + FAR struct esp32_spi_priv_s *priv = (FAR struct esp32_spi_priv_s *)dev; + + if (lock) + { + ret = nxsem_wait_uninterruptible(&priv->exclsem); + } + else + { + ret = nxsem_post(&priv->exclsem); + } + + return ret; +} + +/**************************************************************************** + * Name: esp32_spi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32_t esp32_spi_setfrequency(FAR struct spi_dev_s *dev, + uint32_t frequency) +{ + uint32_t reg_val; + FAR struct esp32_spi_priv_s *priv = (FAR struct esp32_spi_priv_s *)dev; + const uint32_t duty_cycle = 128; + + if (priv->frequency == frequency) + { + /* We are already at this frequency. Return the actual. */ + + return priv->actual; + } + + if (frequency > ((APB_CLK_FREQ / 4) * 3)) + { + reg_val = SPI_CLK_EQU_SYSCLK_M; + priv->actual = APB_CLK_FREQ; + } + else + { + int pre; + int n; + int h; + int l; + int bestn = -1; + int bestpre = -1; + int besterr = 0; + int errval; + + for (n = 2; n <= 64; n++) + { + pre = ((APB_CLK_FREQ / n) + (frequency / 2)) / frequency; + + if (pre <= 0) + { + pre = 1; + } + + if (pre > 8192) + { + pre = 8192; + } + + errval = abs(APB_CLK_FREQ / (pre * n) - frequency); + if (bestn == -1 || errval <= besterr) + { + besterr = errval; + bestn = n; + bestpre = pre; + } + } + + n = bestn; + pre = bestpre; + l = n; + h = (duty_cycle * n + 127) / 256; + if (h <= 0) + { + h = 1; + } + + reg_val = ((l - 1) << SPI_CLKCNT_L_S) | + ((h - 1) << SPI_CLKCNT_H_S) | + ((n - 1) << SPI_CLKCNT_N_S) | + ((pre - 1) << SPI_CLKDIV_PRE_S); + + priv->actual = APB_CLK_FREQ / (n * pre); + } + + priv->frequency = frequency; + + esp32_spi_set_reg(priv, SPI_CLOCK_OFFSET, reg_val); + + spiinfo("frequency=%d, actual=%d\n", priv->frequency, priv->actual); + + return priv->actual; +} + +/**************************************************************************** + * Name: esp32_spi_setmode + * + * Description: + * Set the SPI mode. + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void esp32_spi_setmode(FAR struct spi_dev_s *dev, + enum spi_mode_e mode) +{ + uint32_t ck_idle_edge; + uint32_t ck_out_edge; + uint32_t delay_mode; + FAR struct esp32_spi_priv_s *priv = (FAR struct esp32_spi_priv_s *)dev; + + spiinfo("mode=%d\n", mode); + + /* Has the mode changed? */ + + if (mode != priv->mode) + { + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ + ck_idle_edge = 0; + ck_out_edge = 0; + delay_mode = 0; + break; + + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ + ck_idle_edge = 0; + ck_out_edge = 1; + delay_mode = 2; + break; + + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ + ck_idle_edge = 1; + ck_out_edge = 1; + delay_mode = 2; + break; + + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ + ck_idle_edge = 1; + ck_out_edge = 0; + delay_mode = 0; + break; + + default: + return; + } + + esp32_spi_reset_regbits(priv, SPI_PIN_OFFSET, SPI_CK_IDLE_EDGE_M); + esp32_spi_set_regbits(priv, SPI_PIN_OFFSET, + (ck_idle_edge << SPI_CK_IDLE_EDGE_S)); + + esp32_spi_reset_regbits(priv, SPI_USER_OFFSET, + SPI_CK_OUT_EDGE_M); + esp32_spi_set_regbits(priv, SPI_USER_OFFSET, + (ck_out_edge << SPI_CK_OUT_EDGE_S)); + + esp32_spi_reset_regbits(priv, SPI_CTRL2_OFFSET, + SPI_MISO_DELAY_MODE_M | + SPI_MISO_DELAY_NUM_M | + SPI_MOSI_DELAY_NUM_M | + SPI_MOSI_DELAY_MODE_M); + + esp32_spi_set_regbits(priv, SPI_CTRL2_OFFSET, + (delay_mode << SPI_MISO_DELAY_MODE_S) | + (delay_mode << SPI_MOSI_DELAY_MODE_S)); + + priv->mode = mode; + } +} + +/**************************************************************************** + * Name: esp32_spi_setbits + * + * Description: + * Set the number if bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits in an SPI word. + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void esp32_spi_setbits(FAR struct spi_dev_s *dev, int nbits) +{ + FAR struct esp32_spi_priv_s *priv = (FAR struct esp32_spi_priv_s *)dev; + + spiinfo("nbits=%d\n", nbits); + + /* Has the number of bits changed? */ + + if (nbits != priv->nbits) + { + /** + * Save the selection so the subsequence re-configurations + * will be faster. + */ + + priv->nbits = nbits; + + esp32_spi_set_reg(priv, SPI_MISO_DLEN_OFFSET, + (priv->nbits - 1) << SPI_USR_MISO_DBITLEN_S); + esp32_spi_set_reg(priv, SPI_MOSI_DLEN_OFFSET, + (priv->nbits - 1) << SPI_USR_MOSI_DBITLEN_S); + } +} + +/**************************************************************************** + * Name: esp32_spi_hwfeatures + * + * Description: + * Set hardware-specific feature flags. + * + * Input Parameters: + * dev - Device-specific state data + * features - H/W feature flags + * + * Returned Value: + * Zero (OK) if the selected H/W features are enabled; A negated errno + * value if any H/W feature is not supportable. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_HWFEATURES +static int esp32_spi_hwfeatures(FAR struct spi_dev_s *dev, + spi_hwfeatures_t features) +{ + /* Other H/W features are not supported */ + + return (features == 0) ? OK : -ENOSYS; +} +#endif + +/**************************************************************************** + * Name: esp32_spi_send + * + * Description: + * Exchange one word on SPI. + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * Received value + * + ****************************************************************************/ + +static uint32_t esp32_spi_send(FAR struct spi_dev_s *dev, uint32_t wd) +{ + uint32_t val; + FAR struct esp32_spi_priv_s *priv = (FAR struct esp32_spi_priv_s *)dev; + + esp32_spi_set_reg(priv, SPI_W0_OFFSET, wd); + + esp32_spi_set_regbits(priv, SPI_CMD_OFFSET, SPI_USR_M); + + while (esp32_spi_get_reg(priv, SPI_CMD_OFFSET) & SPI_USR_M) + { + ; + } + + val = esp32_spi_get_reg(priv, SPI_W0_OFFSET); + + spiinfo("send=%x and recv=%x\n", wd, val); + + return val; +} + +/**************************************************************************** + * Name: esp32_spi_exchange + * + * Description: + * Exchange a block of data from SPI. + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to the buffer in which to receive data + * nwords - the length of data that to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32_spi_exchange(FAR struct spi_dev_s *dev, + FAR const void *txbuffer, + FAR void *rxbuffer, + size_t nwords) +{ + int i; + FAR struct esp32_spi_priv_s *priv = (FAR struct esp32_spi_priv_s *)dev; + + for (i = 0 ; i < nwords; i++) + { + uint32_t w_wd = 0; + uint32_t r_wd; + + if (txbuffer) + { + if (priv->nbits == 8) + { + w_wd = ((uint8_t *)txbuffer)[i]; + } + else + { + w_wd = ((uint16_t *)txbuffer)[i]; + } + } + + r_wd = esp32_spi_send(dev, w_wd); + + if (rxbuffer) + { + if (priv->nbits == 8) + { + ((uint8_t *)rxbuffer)[i] = r_wd; + } + else + { + ((uint16_t *)rxbuffer)[i] = r_wd; + } + } + } +} + +#ifndef CONFIG_SPI_EXCHANGE + +/**************************************************************************** + * Name: esp32_spi_sndblock + * + * Description: + * Send a block of data on SPI. + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32_spi_sndblock(FAR struct spi_dev_s *dev, + FAR const void *txbuffer, + size_t nwords) +{ + spiinfo("txbuffer=%p nwords=%d\n", txbuffer, nwords); + + esp32_spi_exchange(dev, txbuffer, NULL, nwords); +} + +/**************************************************************************** + * Name: esp32_spi_recvblock + * + * Description: + * Receive a block of data from SPI. + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer in which to receive data + * nwords - the length of data that can be received in the buffer in number + * of words. The wordsize is determined by the number of bits- + * per-word selected for the SPI interface. If nbits <= 8, the + * data is packed into uint8_t's; if nbits >8, the data is packed + * into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32_spi_recvblock(FAR struct spi_dev_s *dev, + FAR void *rxbuffer, + size_t nwords) +{ + spiinfo("rxbuffer=%p nwords=%d\n", rxbuffer, nwords); + + esp32_spi_exchange(dev, NULL, rxbuffer, nwords); +} +#endif + +/**************************************************************************** + * Name: esp32_spi_trigger + * + * Description: + * Trigger a previously configured DMA transfer. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * OK - Trigger was fired + * -ENOSYS - Trigger not fired due to lack of DMA or low level support + * -EIO - Trigger not fired because not previously primed + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_TRIGGER +static int esp32_spi_trigger(FAR struct spi_dev_s *dev) +{ + return -ENOSYS; +} +#endif + +/**************************************************************************** + * Name: esp32_spi_init + * + * Description: + * Initialize ESP32 SPI hardware interface + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32_spi_init(FAR struct spi_dev_s *dev) +{ + FAR struct esp32_spi_priv_s *priv = (FAR struct esp32_spi_priv_s *)dev; + const struct esp32_spi_config_s *config = priv->config; + + /* Initialize the SPI semaphore that enforces mutually exclusive access */ + + nxsem_init(&priv->exclsem, 0, 1); + + esp32_gpiowrite(config->cs_pin, 1); + esp32_gpiowrite(config->mosi_pin, 1); + esp32_gpiowrite(config->miso_pin, 1); + esp32_gpiowrite(config->clk_pin, 1); + + esp32_configgpio(config->cs_pin, OUTPUT | PULLUP | FUNCTION_2); + gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0); + gpio_matrix_in(config->cs_pin, config->cs_insig, 0); + + esp32_configgpio(config->mosi_pin, OUTPUT | PULLUP | FUNCTION_2); + gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0); + gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0); + + esp32_configgpio(config->miso_pin, INPUT | PULLUP | FUNCTION_2); + gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0); + gpio_matrix_in(config->miso_pin, config->miso_insig, 0); + + esp32_configgpio(config->clk_pin, OUTPUT | PULLUP | FUNCTION_2); + gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0); + gpio_matrix_in(config->clk_pin, config->clk_insig, 0); + + modifyreg32(DPORT_PERIP_CLK_EN_REG, 0, config->clk_bit); + modifyreg32(DPORT_PERIP_RST_EN_REG, config->rst_bit, 0); + + esp32_spi_set_reg(priv, SPI_USER_OFFSET, SPI_DOUTDIN_M | + SPI_USR_MISO_M | + SPI_USR_MOSI_M | + SPI_CS_HOLD_M); + esp32_spi_set_reg(priv, SPI_USER1_OFFSET, 0); + esp32_spi_set_reg(priv, SPI_SLAVE_OFFSET, 0); + esp32_spi_set_reg(priv, SPI_PIN_OFFSET, SPI_CS1_DIS_M | SPI_CS2_DIS_M); + esp32_spi_set_reg(priv, SPI_CTRL_OFFSET, 0); + esp32_spi_set_reg(priv, SPI_CTRL2_OFFSET, (0 << SPI_HOLD_TIME_S)); + + esp32_spi_setfrequency(dev, config->clk_freq); + esp32_spi_setbits(dev, 8); + esp32_spi_setmode(dev, config->mode); +} + +/**************************************************************************** + * Name: esp32_spi_deinit + * + * Description: + * Deinitialize ESP32 SPI hardware interface + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32_spi_deinit(FAR struct spi_dev_s *dev) +{ + FAR struct esp32_spi_priv_s *priv = (FAR struct esp32_spi_priv_s *)dev; + + modifyreg32(DPORT_PERIP_CLK_EN_REG, priv->config->clk_bit, 0); +} + +/**************************************************************************** + * Name: esp32_spibus_initialize + * + * Description: + * Initialize the selected SPI bus + * + * Input Parameters: + * Port number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *esp32_spibus_initialize(int port) +{ + FAR struct spi_dev_s *spi_dev; + FAR struct esp32_spi_priv_s *priv; + irqstate_t flags; + + switch (port) + { +#ifdef CONFIG_ESP32_SPI2 + case 2: + priv = &esp32_spi2_priv; + break; +#endif +#ifdef CONFIG_ESP32_SPI3 + case 3: + priv = &esp32_spi3_priv; + break; +#endif + default: + return NULL; + } + + spi_dev = (FAR struct spi_dev_s *)priv; + + flags = enter_critical_section(); + + if ((volatile int)priv->refs++ != 0) + { + leave_critical_section(flags); + + return spi_dev; + } + + esp32_spi_init(spi_dev); + + leave_critical_section(flags); + + return spi_dev; +} + +/**************************************************************************** + * Name: esp32_spibus_uninitialize + * + * Description: + * Uninitialize an SPI bus + * + ****************************************************************************/ + +int esp32_spibus_uninitialize(FAR struct spi_dev_s *dev) +{ + irqstate_t flags; + FAR struct esp32_spi_priv_s *priv = (FAR struct esp32_spi_priv_s *)dev; + + DEBUGASSERT(dev); + + if (priv->refs == 0) + { + return ERROR; + } + + flags = enter_critical_section(); + + if (--priv->refs) + { + leave_critical_section(flags); + return OK; + } + + leave_critical_section(flags); + + esp32_spi_deinit(dev); + + nxsem_destroy(&priv->exclsem); + + return OK; +} + +#endif /* CONFIG_ESP32_SPI */ diff --git a/arch/xtensa/src/esp32/esp32_spi.h b/arch/xtensa/src/esp32/esp32_spi.h new file mode 100644 index 0000000000..9c0f716fd7 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_spi.h @@ -0,0 +1,163 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_spi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_SPI_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#ifdef CONFIG_ESP32_SPI + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_spibus_initialize + * + * Description: + * Initialize the selected SPI bus + * + * Input Parameters: + * Port number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_dev_s *esp32_spibus_initialize(int port); + +/**************************************************************************** + * Name: esp32_spi0/1/...select and esp32_spi0/1/...status + * + * Description: + * The external functions, esp32_spi0/1/...select, esp32_spi0/1/...status, + * and esp32_spi0/1/...cmddata must be provided by board-specific logic. + * These are implementations of the select, status, and cmddata methods of + * the SPI interface defined by struct spi_ops_s (include/nuttx/spi/spi.h). + * All other methods (including esp32_spibus_initialize()) are provided by + * common ESP32 logic. To use this common SPI logic on your board: + * + * 1. Provide logic in esp32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide esp32_spi0/1/...select() and esp32_spi0/1/...status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. + * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, +* then provide esp32_spi0/1/...cmddata() functions in your + * board-specific logic. These functions will perform cmd/data selection + * operations using GPIOs in the way your board is configured. + * 4. Add a calls to esp32_spibus_initialize() in your low level + * application initialization logic. + * 5. The handle returned by esp32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_SPI2 +void esp32_spi2_select(FAR struct spi_dev_s *dev, uint32_t devid, + bool selected); +uint8_t esp32_spi2_status(FAR struct spi_dev_s *dev, uint32_t devid); +int esp32_spi2_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); +#endif + +#ifdef CONFIG_ESP32_SPI3 +void esp32_spi3_select(FAR struct spi_dev_s *dev, uint32_t devid, + bool selected); +uint8_t esp32_spi3_status(FAR struct spi_dev_s *dev, uint32_t devid); +int esp32_spi3_cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd); +#endif + +/**************************************************************************** + * Name: esp32_spibus_uninitialize + * + * Description: + * Uninitialize an SPI bus + * + ****************************************************************************/ + +int esp32_spibus_uninitialize(FAR struct spi_dev_s *dev); + +/**************************************************************************** + * Name: esp32_spislv_sctrlr_initialize + * + * Description: + * Initialize the selected SPI slave bus + * + * Input Parameters: + * Port number (for hardware that has multiple SPI slave interfaces) + * + * Returned Value: + * Valid SPI slave device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_sctrlr_s *esp32_spislv_sctrlr_initialize(int port); + +/**************************************************************************** + * Name: esp32_spislv_sctrlr_uninitialize + * + * Description: + * Uninitialize an SPI slave bus + * + * Input Parameters: + * sctrlr - SPI slave controller interface instance + * + * Returned Value: + * OK if success or fail + * + ****************************************************************************/ + +int esp32_spislv_sctrlr_uninitialize(FAR struct spi_sctrlr_s *sctrlr); + +#endif /* CONFIG_ESP32_SPI */ + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_SPI_H */ diff --git a/arch/xtensa/src/esp32/esp32_spi_slave.c b/arch/xtensa/src/esp32/esp32_spi_slave.c new file mode 100644 index 0000000000..be0a44183b --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_spi_slave.c @@ -0,0 +1,1038 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_spislv_slave.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_ESP32_SPI + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "esp32_spi.h" +#include "esp32_gpio.h" +#include "esp32_cpuint.h" + +#include "xtensa.h" +#include "hardware/esp32_gpio_sigmap.h" +#include "hardware/esp32_dport.h" +#include "hardware/esp32_spi.h" +#include "hardware/esp32_soc.h" +#include "rom/esp32_gpio.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifndef CONFIG_ESP_SPI_SLAVE_QSIZE + #define CONFIG_ESP_SPI_SLAVE_QSIZE 1024 +#endif + +/* SPI Device hardware configuration */ + +struct esp32_spislv_config_s +{ + uint32_t reg_base; /* SPI register base address */ + + enum spi_mode_e mode; /* SPI default mode */ + + uint8_t cs_pin; /* GPIO configuration for CS */ + uint8_t mosi_pin; /* GPIO configuration for MOSI */ + uint8_t miso_pin; /* GPIO configuration for MISO */ + uint8_t clk_pin; /* GPIO configuration for CLK */ + + uint8_t cpu; /* CPU ID */ + uint8_t periph; /* peripher ID */ + uint8_t irq; /* Interrupt ID */ + + uint32_t clk_bit; /* Clock enable bit */ + uint32_t rst_bit; /* I2C reset bit */ + + uint32_t cs_insig; /* SPI CS input signal index */ + uint32_t cs_outsig; /* SPI CS output signal index */ + uint32_t mosi_insig; /* SPI MOSI input signal index */ + uint32_t mosi_outsig; /* SPI MOSI output signal index */ + uint32_t miso_insig; /* SPI MISO input signal index */ + uint32_t miso_outsig; /* SPI MISO output signal index */ + uint32_t clk_insig; /* SPI CLK input signal index */ + uint32_t clk_outsig; /* SPI CLK output signal index */ +}; + +struct esp32_spislv_priv_s +{ + /* Externally visible part of the SPI slave controller interface */ + + struct spi_sctrlr_s sctrlr; + + struct spi_sdev_s *sdev; /* Externally visible part of the SPI interface */ + + const struct esp32_spislv_config_s *config; /* Port configuration */ + + uint32_t cpuint; /* SPI interrupt ID */ + + enum spi_mode_e mode; /* Actual SPI hardware mode */ + uint8_t nbits; /* Actual SPI send/receive bits once transmission */ + int refs; /* Check if it is initialized */ + + uint32_t head; /* Location of next value */ + uint32_t tail; /* Index of first value */ + + /* SPI slave output queue buffer */ + + uint16_t outq[CONFIG_ESP_SPI_SLAVE_QSIZE]; + + uint32_t outval; /* Default shift-out value */ + + bool process; /* If SPI Slave process */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void esp32_spislv_setmode(FAR struct spi_sctrlr_s *dev, + enum spi_mode_e mode); +static void esp32_spislv_setbits(FAR struct spi_sctrlr_s *dev, int nbits); +static int esp32_spislv_interrupt(int irq, void *context, FAR void *arg); +static void esp32_spislv_initialize(FAR struct spi_sctrlr_s *dev); +static void esp32_spislv_bind(struct spi_sctrlr_s *sctrlr, + struct spi_sdev_s *sdev, + enum spi_smode_e mode, + int nbits); +static void esp32_spislv_unbind(struct spi_sctrlr_s *sctrlr); +static int esp32_spislv_enqueue(struct spi_sctrlr_s *sctrlr, + FAR const void *data, + size_t nwords); +static bool esp32_spislv_qfull(struct spi_sctrlr_s *sctrlr); +static void esp32_spislv_qflush(struct spi_sctrlr_s *sctrlr); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_ESP32_SPI2 +static const struct esp32_spislv_config_s esp32_spi2_config = +{ + .reg_base = REG_SPI_BASE(2), + .mode = SPIDEV_MODE0, + .cs_pin = CONFIG_ESP32_SPI2_CSPIN, + .mosi_pin = CONFIG_ESP32_SPI2_MOSIPIN, + .miso_pin = CONFIG_ESP32_SPI2_MISOPIN, + .clk_pin = CONFIG_ESP32_SPI2_CLKPIN, + .cpu = 0, + .periph = ESP32_PERIPH_SPI2, + .irq = ESP32_IRQ_SPI2, + .clk_bit = DPORT_SPI_CLK_EN_2, + .rst_bit = DPORT_SPI_RST_2, + .cs_insig = HSPICS0_IN_IDX, + .cs_outsig = HSPICS0_OUT_IDX, + .mosi_insig = HSPID_IN_IDX, + .mosi_outsig = HSPID_OUT_IDX, + .miso_insig = HSPIQ_IN_IDX, + .miso_outsig = HSPIQ_OUT_IDX, + .clk_insig = HSPICLK_IN_IDX, + .clk_outsig = HSPICLK_OUT_IDX +}; + +static const struct spi_sctrlrops_s esp32_spi2slv_ops = +{ + .bind = esp32_spislv_bind, + .unbind = esp32_spislv_unbind, + .enqueue = esp32_spislv_enqueue, + .qfull = esp32_spislv_qfull, + .qflush = esp32_spislv_qflush +}; + +static struct esp32_spislv_priv_s esp32_spi2slv_priv = +{ + .sctrlr = + { + .ops = &esp32_spi2slv_ops + }, + .config = &esp32_spi2_config, + .mode = SPIDEV_MODE3 +}; +#endif /* CONFIG_ESP32_SPI2 */ + +#ifdef CONFIG_ESP32_SPI3 +static const struct esp32_spislv_config_s esp32_spi3_config = +{ + .reg_base = REG_SPI_BASE(3), + .mode = SPIDEV_MODE0, + .cs_pin = CONFIG_ESP32_SPI3_CSPIN, + .mosi_pin = CONFIG_ESP32_SPI3_MOSIPIN, + .miso_pin = CONFIG_ESP32_SPI3_MISOPIN, + .clk_pin = CONFIG_ESP32_SPI3_CLKPIN, + .cpu = 0, + .periph = ESP32_PERIPH_SPI3, + .irq = ESP32_IRQ_SPI3, + .clk_bit = DPORT_SPI_CLK_EN, + .rst_bit = DPORT_SPI_RST, + .cs_insig = VSPICS0_IN_IDX, + .cs_outsig = VSPICS0_OUT_IDX, + .mosi_insig = VSPID_IN_IDX, + .mosi_outsig = VSPID_OUT_IDX, + .miso_insig = VSPIQ_IN_IDX, + .miso_outsig = VSPIQ_OUT_IDX, + .clk_insig = VSPICLK_IN_IDX, + .clk_outsig = VSPICLK_OUT_MUX_IDX +}; + +static const struct spi_sctrlrops_s esp32_spi3slv_ops = +{ + .bind = esp32_spislv_bind, + .unbind = esp32_spislv_unbind, + .enqueue = esp32_spislv_enqueue, + .qfull = esp32_spislv_qfull, + .qflush = esp32_spislv_qflush +}; + +static struct esp32_spislv_priv_s esp32_spi3slv_priv = +{ + .sctrlr = + { + .ops = &esp32_spi3slv_ops + }, + .config = &esp32_spi3_config, + .mode = SPIDEV_MODE3 +}; +#endif /* CONFIG_ESP32_SPI3 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_spi_set_reg + * + * Description: + * Set the contents of the SPI register at offset + * + * Input Parameters: + * priv - Private SPI device structure + * offset - Offset to the register of interest + * value - Value to be written + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void esp32_spi_set_reg(struct esp32_spislv_priv_s *priv, + int offset, + uint32_t value) +{ + putreg32(value, priv->config->reg_base + offset); +} + +/**************************************************************************** + * Name: esp32_spi_get_reg + * + * Description: + * Get the contents of the SPI register at offset + * + * Input Parameters: + * priv - Private SPI device structure + * offset - Offset to the register of interest + * + * Returned Value: + * The contents of the register + * + ****************************************************************************/ + +static inline uint32_t esp32_spi_get_reg(struct esp32_spislv_priv_s *priv, + int offset) +{ + return getreg32(priv->config->reg_base + offset); +} + +/**************************************************************************** + * Name: esp32_spi_set_regbits + * + * Description: + * Set the bits of the SPI register at offset + * + * Input Parameters: + * priv - Private SPI device structure + * offset - Offset to the register of interest + * bits - Bits to be set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void esp32_spi_set_regbits(struct esp32_spislv_priv_s *priv, + int offset, + uint32_t bits) +{ + uint32_t tmp = getreg32(priv->config->reg_base + offset); + + putreg32(tmp | bits, priv->config->reg_base + offset); +} + +/**************************************************************************** + * Name: esp32_spi_reset_regbits + * + * Description: + * Clear the bits of the SPI register at offset + * + * Input Parameters: + * priv - Private SPI device structure + * offset - Offset to the register of interest + * bits - Bits to be cleared + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void esp32_spi_reset_regbits(struct esp32_spislv_priv_s *priv, + int offset, + uint32_t bits) +{ + uint32_t tmp = getreg32(priv->config->reg_base + offset); + + putreg32(tmp & (~bits), priv->config->reg_base + offset); +} + +/**************************************************************************** + * Name: esp32_spislv_setmode + * + * Description: + * Set the SPI mode. + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void esp32_spislv_setmode(FAR struct spi_sctrlr_s *dev, + enum spi_mode_e mode) +{ + uint32_t ck_idle_edge; + uint32_t ck_in_edge; + uint32_t miso_delay_mode; + uint32_t miso_delay_num; + uint32_t mosi_delay_mode; + uint32_t mosi_delay_num; + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)dev; + + spiinfo("mode=%d\n", mode); + + /* Has the mode changed? */ + + if (mode != priv->mode) + { + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ + ck_idle_edge = 1; + ck_in_edge = 0; + miso_delay_mode = 0; + miso_delay_num = 0; + mosi_delay_mode = 2; + mosi_delay_num = 2; + break; + + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ + ck_idle_edge = 1; + ck_in_edge = 1; + miso_delay_mode = 2; + miso_delay_num = 0; + mosi_delay_mode = 0; + mosi_delay_num = 0; + break; + + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ + ck_idle_edge = 0; + ck_in_edge = 1; + miso_delay_mode = 0; + miso_delay_num = 0; + mosi_delay_mode = 1; + mosi_delay_num = 2; + break; + + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ + ck_idle_edge = 0; + ck_in_edge = 0; + miso_delay_mode = 1; + miso_delay_num = 0; + mosi_delay_mode = 0; + mosi_delay_num = 0; + break; + + default: + return; + } + + esp32_spi_reset_regbits(priv, + SPI_PIN_OFFSET, + SPI_CK_IDLE_EDGE_M); + esp32_spi_set_regbits(priv, + SPI_PIN_OFFSET, + (ck_idle_edge << SPI_CK_IDLE_EDGE_S)); + + esp32_spi_reset_regbits(priv, + SPI_USER_OFFSET, + SPI_CK_I_EDGE_M); + esp32_spi_set_regbits(priv, + SPI_USER_OFFSET, + (ck_in_edge << SPI_CK_I_EDGE_S)); + + esp32_spi_reset_regbits(priv, + SPI_CTRL2_OFFSET, + SPI_MISO_DELAY_MODE_M | + SPI_MISO_DELAY_NUM_M | + SPI_MOSI_DELAY_NUM_M | + SPI_MOSI_DELAY_MODE_M); + esp32_spi_set_regbits(priv, + SPI_CTRL2_OFFSET, + (miso_delay_mode << SPI_MISO_DELAY_MODE_S) | + (miso_delay_num << SPI_MISO_DELAY_NUM_S) | + (mosi_delay_mode << SPI_MOSI_DELAY_MODE_S) | + (mosi_delay_num << SPI_MOSI_DELAY_NUM_S)); + + priv->mode = mode; + } +} + +/**************************************************************************** + * Name: esp32_spislv_setbits + * + * Description: + * Set the number if bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits in an SPI word. + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void esp32_spislv_setbits(FAR struct spi_sctrlr_s *dev, int nbits) +{ + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)dev; + + spiinfo("nbits=%d\n", nbits); + + if (nbits != priv->nbits) + { + priv->nbits = nbits; + + esp32_spi_set_reg(priv, SPI_SLV_WRBUF_DLEN_OFFSET, nbits - 1); + esp32_spi_set_reg(priv, SPI_SLV_RDBUF_DLEN_OFFSET, nbits - 1); + } +} + +/**************************************************************************** + * Name: spi_dequeue + * + * Description: + * Get the next queued output value. + * + * Input Parameters: + * priv - SPI controller CS state + * pdata - output data buffer + * + * Returned Value: + * true if there is data or fail + * + * Assumptions: + * Called only from the SPI interrupt handler so all interrupts are + * disabled. + * + ****************************************************************************/ + +static int spi_dequeue(struct esp32_spislv_priv_s *priv, uint32_t *pdata) +{ + int ret = false; + int next; + + if (priv->head != priv->tail) + { + *pdata = priv->outq[priv->tail]; + + next = priv->tail + 1; + if (next >= CONFIG_ESP_SPI_SLAVE_QSIZE) + { + next = 0; + } + + priv->tail = next; + + ret = true; + } + + return ret; +} + +/**************************************************************************** + * Name: esp32_io_interrupt + * + * Description: + * Common I/O interrupt handler + * + * Input Parameters: + * arg - I/O controller private data + * + * Returned Value: + * Standard interrupt return value. + * + ****************************************************************************/ + +static int esp32_io_interrupt(int irq, void *context, FAR void *arg) +{ + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)arg; + + priv->process = false; + SPI_SDEV_SELECT(priv->sdev, false); + + return 0; +} + +/**************************************************************************** + * Name: esp32_spislv_interrupt + * + * Description: + * Common SPI interrupt handler + * + * Input Parameters: + * arg - SPI controller private data + * + * Returned Value: + * Standard interrupt return value. + * + ****************************************************************************/ + +static int esp32_spislv_interrupt(int irq, void *context, FAR void *arg) +{ + uint32_t rd; + uint32_t wd; + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)arg; + irqstate_t flags; + + flags = enter_critical_section(); + + esp32_spi_reset_regbits(priv, SPI_SLAVE_OFFSET, SPI_TRANS_DONE_M); + + if (!priv->process) + { + SPI_SDEV_SELECT(priv->sdev, true); + priv->process = true; + } + + rd = esp32_spi_get_reg(priv, SPI_W0_OFFSET); + if (spi_dequeue(priv, &wd)) + { + esp32_spi_set_reg(priv, SPI_W0_OFFSET, wd); + esp32_spi_set_regbits(priv, SPI_CMD_OFFSET, SPI_USR_M); + } + + SPI_SDEV_RECEIVE(priv->sdev, &rd, 1); + + if (priv->process == false) + { + SPI_SDEV_SELECT(priv->sdev, false); + } + + leave_critical_section(flags); + + return 0; +} + +/**************************************************************************** + * Name: esp32_spislv_initialize + * + * Description: + * Initialize ESP32 SPI hardware interface + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32_spislv_initialize(FAR struct spi_sctrlr_s *dev) +{ + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)dev; + const struct esp32_spislv_config_s *config = priv->config; + + esp32_gpiowrite(config->cs_pin, 1); + esp32_gpiowrite(config->mosi_pin, 1); + esp32_gpiowrite(config->miso_pin, 1); + esp32_gpiowrite(config->clk_pin, 1); + + esp32_configgpio(config->cs_pin, INPUT | PULLUP | FUNCTION_2); + gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0); + gpio_matrix_in(config->cs_pin, config->cs_insig, 0); + + esp32_configgpio(config->mosi_pin, INPUT | PULLUP | FUNCTION_2); + gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0); + gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0); + + esp32_configgpio(config->miso_pin, OUTPUT | PULLUP | FUNCTION_2); + gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0); + gpio_matrix_in(config->miso_pin, config->miso_insig, 0); + + esp32_configgpio(config->clk_pin, INPUT | PULLUP | FUNCTION_2); + gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0); + gpio_matrix_in(config->clk_pin, config->clk_insig, 0); + + modifyreg32(DPORT_PERIP_CLK_EN_REG, 0, config->clk_bit); + modifyreg32(DPORT_PERIP_RST_EN_REG, config->rst_bit, 0); + + esp32_spi_set_reg(priv, SPI_USER_OFFSET, SPI_DOUTDIN_M | + SPI_USR_MOSI_M | + SPI_USR_MISO_M); + esp32_spi_set_reg(priv, SPI_USER1_OFFSET, 0); + esp32_spi_set_reg(priv, SPI_PIN_OFFSET, SPI_CS1_DIS_M | SPI_CS2_DIS_M); + esp32_spi_set_reg(priv, SPI_CTRL_OFFSET, 0); + esp32_spi_set_reg(priv, SPI_CTRL2_OFFSET, 0); + esp32_spi_set_reg(priv, SPI_USER2_OFFSET, 0); + esp32_spi_set_reg(priv, SPI_CLOCK_OFFSET, 0); + esp32_spi_set_reg(priv, SPI_SLAVE_OFFSET, SPI_SLAVE_MODE_M | + SPI_SLV_WR_RD_BUF_EN_M | + SPI_INT_EN_M); + + esp32_spislv_setmode(dev, config->mode); + esp32_spislv_setbits(dev, 8); + + esp32_spi_set_regbits(priv, SPI_SLAVE_OFFSET, SPI_SYNC_RESET_M); + esp32_spi_reset_regbits(priv, SPI_SLAVE_OFFSET, SPI_SYNC_RESET_M); + + esp32_gpioirqenable(ESP32_PIN2IRQ(config->cs_pin), RISING); +} + +/**************************************************************************** + * Name: esp32_spislv_deinit + * + * Description: + * Deinitialize ESP32 SPI hardware interface + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32_spislv_deinit(FAR struct spi_sctrlr_s *dev) +{ + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)dev; + + esp32_gpioirqdisable(ESP32_PIN2IRQ(priv->config->cs_pin)); + esp32_spi_reset_regbits(priv, SPI_SLAVE_OFFSET, SPI_INT_EN_M); + modifyreg32(DPORT_PERIP_CLK_EN_REG, priv->config->clk_bit, 0); +} + +/**************************************************************************** + * Name: esp32_spislv_bind + * + * Description: + * Bind the SPI slave device interface to the SPI slave controller + * interface and configure the SPI interface. Upon return, the SPI + * slave controller driver is fully operational and ready to perform + * transfers. + * + * Input Parameters: + * sctrlr - SPI slave controller interface instance + * sdev - SPI slave device interface instance + * mode - The SPI mode requested + * nbits - The number of bits requests + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void esp32_spislv_bind(struct spi_sctrlr_s *sctrlr, + struct spi_sdev_s *sdev, + enum spi_smode_e mode, + int nbits) +{ + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)sctrlr; + irqstate_t flags; + FAR const void *data; + int ret; + + spiinfo("sdev=%p mode=%d nbits=%d\n", sdv, mode, nbits); + + DEBUGASSERT(priv != NULL && priv->sdev == NULL && sdev != NULL); + + flags = enter_critical_section(); + + priv->sdev = sdev; + + SPI_SDEV_SELECT(sdev, false); + + SPI_SDEV_CMDDATA(sdev, false); + + esp32_spislv_initialize(sctrlr); + + esp32_spislv_setmode(sctrlr, mode); + esp32_spislv_setbits(sctrlr, nbits); + + priv->head = 0; + priv->tail = 0; + + ret = SPI_SDEV_GETDATA(sdev, &data); + if (ret == 1) + { + priv->outval = *(const uint16_t *)data; + } + + esp32_spi_set_reg(priv, SPI_W0_OFFSET, priv->outval); + esp32_spi_set_regbits(priv, SPI_CMD_OFFSET, SPI_USR_M); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp32_spislv_unbind + * + * Description: + * Un-bind the SPI slave device interface from the SPI slave controller + * interface. Reset the SPI interface and restore the SPI slave + * controller driver to its initial state, + * + * Input Parameters: + * sctrlr - SPI slave controller interface instance + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void esp32_spislv_unbind(struct spi_sctrlr_s *sctrlr) +{ + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)sctrlr; + irqstate_t flags; + + DEBUGASSERT(priv != NULL); + + spiinfo("Unbinding %p\n", priv->sdev); + + DEBUGASSERT(priv->sdev != NULL); + + flags = enter_critical_section(); + + priv->sdev = NULL; + + esp32_gpioirqdisable(ESP32_PIN2IRQ(priv->config->cs_pin)); + esp32_spi_reset_regbits(priv, SPI_SLAVE_OFFSET, SPI_INT_EN_M); + modifyreg32(DPORT_PERIP_CLK_EN_REG, priv->config->clk_bit, 0); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp32_spislv_enqueue + * + * Description: + * Enqueue the next value to be shifted out from the interface. This adds + * the word the controller driver for a subsequent transfer but has no + * effect on anyin-process or currently "committed" transfers + * + * Input Parameters: + * sctrlr - SPI slave controller interface instance + * data - Command/data mode data value to be shifted out. The width of + * the data must be the same as the nbits parameter previously + * provided to the bind() methods. + * + * Returned Value: + * Zero if the word was successfully queue; A negated errno valid is + * returned on any failure to enqueue the word (such as if the queue is + * full). + * + ****************************************************************************/ + +static int esp32_spislv_enqueue(struct spi_sctrlr_s *sctrlr, + FAR const void *data, + size_t nwords) +{ + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)sctrlr; + irqstate_t flags; + uint32_t next; + int ret; + + spiinfo("spi_enqueue(sctrlr=%p, data=%p, nwords=%d)\n", + sctrlr, data, nwords); + DEBUGASSERT(priv != NULL && priv->sdev != NULL); + + if (!nwords || nwords > 1) + { + return -EINVAL; + } + + flags = enter_critical_section(); + next = priv->head + 1; + if (next >= CONFIG_ESP_SPI_SLAVE_QSIZE) + { + next = 0; + } + + if (next == priv->tail) + { + ret = -ENOSPC; + } + else + { + priv->outq[priv->head] = *(uint16_t *)data; + priv->head = next; + ret = OK; + + if (!priv->process) + { + esp32_spi_set_regbits(priv, SPI_SLAVE_OFFSET, SPI_TRANS_DONE_M); + } + } + + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: esp32_spislv_qfull + * + * Description: + * Return true if the queue is full or false if there is space to add an + * additional word to the queue. + * + * Input Parameters: + * sctrlr - SPI slave controller interface instance + * + * Returned Value: + * true if the output wueue is full + * + ****************************************************************************/ + +static bool esp32_spislv_qfull(struct spi_sctrlr_s *sctrlr) +{ + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)sctrlr; + irqstate_t flags; + uint32_t next; + bool ret; + + DEBUGASSERT(priv != NULL && priv->sdev != NULL); + + spiinfo("spi_qfull(sctrlr=%p)\n", sctrlr); + + flags = enter_critical_section(); + next = priv->head + 1; + if (next >= CONFIG_ESP_SPI_SLAVE_QSIZE) + { + next = 0; + } + + ret = (next == priv->tail); + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: esp32_spislv_qflush + * + * Description: + * Discard all saved values in the output queue. On return from this + * function the output queue will be empty. Any in-progress or otherwise + * "committed" output values may not be flushed. + * + * Input Parameters: + * sctrlr - SPI slave controller interface instance + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32_spislv_qflush(struct spi_sctrlr_s *sctrlr) +{ + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)sctrlr; + irqstate_t flags; + + spiinfo("data=%04x\n", data); + + DEBUGASSERT(priv != NULL && priv->sdev != NULL); + + flags = enter_critical_section(); + priv->head = 0; + priv->tail = 0; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp32_spislv_sctrlr_initialize + * + * Description: + * Initialize the selected SPI slave bus + * + * Input Parameters: + * Port number (for hardware that has multiple SPI slave interfaces) + * + * Returned Value: + * Valid SPI slave device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +FAR struct spi_sctrlr_s *esp32_spislv_sctrlr_initialize(int port) +{ + int ret; + FAR struct spi_sctrlr_s *spislv_dev; + FAR struct esp32_spislv_priv_s *priv; + irqstate_t flags; + + switch (port) + { +#ifdef CONFIG_ESP32_SPI2 + case 2: + priv = &esp32_spi2slv_priv; + break; +#endif +#ifdef CONFIG_ESP32_SPI3 + case 3: + priv = &esp32_spi3slv_priv; + break; +#endif + default: + return NULL; + } + + spislv_dev = (FAR struct spi_sctrlr_s *)priv; + + flags = enter_critical_section(); + + if ((volatile int)priv->refs++ != 0) + { + leave_critical_section(flags); + + return spislv_dev; + } + + DEBUGVERIFY(irq_attach(ESP32_PIN2IRQ(priv->config->cs_pin), + esp32_io_interrupt, + priv)); + + priv->cpuint = esp32_alloc_levelint(1); + if (priv->cpuint < 0) + { + leave_critical_section(flags); + + return NULL; + } + + up_disable_irq(priv->cpuint); + esp32_attach_peripheral(priv->config->cpu, + priv->config->periph, + priv->cpuint); + + ret = irq_attach(priv->config->irq, esp32_spislv_interrupt, priv); + if (ret != OK) + { + esp32_detach_peripheral(priv->config->cpu, + priv->config->periph, + priv->cpuint); + esp32_free_cpuint(priv->cpuint); + + leave_critical_section(flags); + + return NULL; + } + + up_enable_irq(priv->cpuint); + + leave_critical_section(flags); + + return spislv_dev; +} + +/**************************************************************************** + * Name: esp32_spislv_sctrlr_uninitialize + * + * Description: + * Uninitialize an SPI slave bus + * + * Input Parameters: + * sctrlr - SPI slave controller interface instance + * + * Returned Value: + * OK if success or fail + * + ****************************************************************************/ + +int esp32_spislv_sctrlr_uninitialize(FAR struct spi_sctrlr_s *sctrlr) +{ + irqstate_t flags; + struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)sctrlr; + + DEBUGASSERT(sctrlr); + + if (priv->refs == 0) + { + return ERROR; + } + + flags = enter_critical_section(); + + if (--priv->refs) + { + leave_critical_section(flags); + return OK; + } + + up_disable_irq(priv->cpuint); + + esp32_spislv_deinit(sctrlr); + + leave_critical_section(flags); + + return OK; +} + +#endif /* CONFIG_ESP32_SPI */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_spi.h b/arch/xtensa/src/esp32/hardware/esp32_spi.h new file mode 100644 index 0000000000..3accff8671 --- /dev/null +++ b/arch/xtensa/src/esp32/hardware/esp32_spi.h @@ -0,0 +1,2833 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/hardware/esp32_spi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SPI_H +#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32_soc.h" + +#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1)* 0x1000 ))) + +#define SPI_CMD_OFFSET (0x0) +#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + SPI_CMD_OFFSET) + +/* SPI_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +/* Description: Read flash enable. Read flash operation will be triggered + * when the bit is set. The bit will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_READ (BIT(31)) +#define SPI_FLASH_READ_M (BIT(31)) +#define SPI_FLASH_READ_V 0x1 +#define SPI_FLASH_READ_S 31 + +/* SPI_FLASH_WREN : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: Write flash enable. Write enable command will be sent when + * the bit is set. The bit will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_WREN (BIT(30)) +#define SPI_FLASH_WREN_M (BIT(30)) +#define SPI_FLASH_WREN_V 0x1 +#define SPI_FLASH_WREN_S 30 + +/* SPI_FLASH_WRDI : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: Write flash disable. Write disable command will be sent when + * the bit is set. The bit will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_WRDI (BIT(29)) +#define SPI_FLASH_WRDI_M (BIT(29)) +#define SPI_FLASH_WRDI_V 0x1 +#define SPI_FLASH_WRDI_S 29 + +/* SPI_FLASH_RDID : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +/* Description: Read JEDEC ID . Read ID command will be sent when the bit is + * set. The bit will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_RDID (BIT(28)) +#define SPI_FLASH_RDID_M (BIT(28)) +#define SPI_FLASH_RDID_V 0x1 +#define SPI_FLASH_RDID_S 28 + +/* SPI_FLASH_RDSR : R/W ;bitpos:[27] ;default: 1'b0 ; */ + +/* Description: Read status register-1. Read status operation will be + * triggered when the bit is set. The bit will be cleared once the operation + * done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_RDSR (BIT(27)) +#define SPI_FLASH_RDSR_M (BIT(27)) +#define SPI_FLASH_RDSR_V 0x1 +#define SPI_FLASH_RDSR_S 27 + +/* SPI_FLASH_WRSR : R/W ;bitpos:[26] ;default: 1'b0 ; */ + +/* Description: Write status register enable. Write status operation will + * be triggered when the bit is set. The bit will be cleared once the + * operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_WRSR (BIT(26)) +#define SPI_FLASH_WRSR_M (BIT(26)) +#define SPI_FLASH_WRSR_V 0x1 +#define SPI_FLASH_WRSR_S 26 + +/* SPI_FLASH_PP : R/W ;bitpos:[25] ;default: 1'b0 ; */ + +/* Description: Page program enable(1 byte ~256 bytes data to be programmed). + * Page program operation will be triggered when the bit is set. The bit will + * be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_PP (BIT(25)) +#define SPI_FLASH_PP_M (BIT(25)) +#define SPI_FLASH_PP_V 0x1 +#define SPI_FLASH_PP_S 25 + +/* SPI_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */ + +/* Description: Sector erase enable. A 4KB sector is erased via SPI command + * 20H. Sector erase operation will be triggered when the bit is set. The bit + * will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_SE (BIT(24)) +#define SPI_FLASH_SE_M (BIT(24)) +#define SPI_FLASH_SE_V 0x1 +#define SPI_FLASH_SE_S 24 + +/* SPI_FLASH_BE : R/W ;bitpos:[23] ;default: 1'b0 ; */ + +/* Description: Block erase enable. A 64KB block is erased via SPI command + * D8H. Block erase operation will be triggered when the bit is set. The bit + * will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_BE (BIT(23)) +#define SPI_FLASH_BE_M (BIT(23)) +#define SPI_FLASH_BE_V 0x1 +#define SPI_FLASH_BE_S 23 + +/* SPI_FLASH_CE : R/W ;bitpos:[22] ;default: 1'b0 ; */ + +/* Description: Chip erase enable. Chip erase operation will be triggered + * when the bit is set. The bit will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_CE (BIT(22)) +#define SPI_FLASH_CE_M (BIT(22)) +#define SPI_FLASH_CE_V 0x1 +#define SPI_FLASH_CE_S 22 + +/* SPI_FLASH_DP : R/W ;bitpos:[21] ;default: 1'b0 ; */ + +/* Description: Drive Flash into power down. An operation will be triggered + * when the bit is set. The bit will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_DP (BIT(21)) +#define SPI_FLASH_DP_M (BIT(21)) +#define SPI_FLASH_DP_V 0x1 +#define SPI_FLASH_DP_S 21 + +/* SPI_FLASH_RES : R/W ;bitpos:[20] ;default: 1'b0 ; */ + +/* Description: This bit combined with reg_resandres bit releases Flash from + * the power-down state or high performance mode and obtains the devices ID. + * The bit will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_RES (BIT(20)) +#define SPI_FLASH_RES_M (BIT(20)) +#define SPI_FLASH_RES_V 0x1 +#define SPI_FLASH_RES_S 20 + +/* SPI_FLASH_HPM : R/W ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: Drive Flash into high performance mode. The bit will be + * cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_HPM (BIT(19)) +#define SPI_FLASH_HPM_M (BIT(19)) +#define SPI_FLASH_HPM_V 0x1 +#define SPI_FLASH_HPM_S 19 + +/* SPI_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */ + +/* Description: User define command enable. An operation will be triggered + * when the bit is set. The bit will be cleared once the operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_USR (BIT(18)) +#define SPI_USR_M (BIT(18)) +#define SPI_USR_V 0x1 +#define SPI_USR_S 18 + +/* SPI_FLASH_PES : R/W ;bitpos:[17] ;default: 1'b0 ; */ + +/* Description: program erase suspend bit program erase suspend operation + * will be triggered when the bit is set. The bit will be cleared once the + * operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_PES (BIT(17)) +#define SPI_FLASH_PES_M (BIT(17)) +#define SPI_FLASH_PES_V 0x1 +#define SPI_FLASH_PES_S 17 + +/* SPI_FLASH_PER : R/W ;bitpos:[16] ;default: 1'b0 ; */ + +/* Description: program erase resume bit program erase suspend operation + * will be triggered when the bit is set. The bit will be cleared once the + * operation done. + * 1: enable + * 0: disable. + */ + +#define SPI_FLASH_PER (BIT(16)) +#define SPI_FLASH_PER_M (BIT(16)) +#define SPI_FLASH_PER_V 0x1 +#define SPI_FLASH_PER_S 16 + +#define SPI_ADDR_OFFSET (0x4) +#define SPI_ADDR_REG (i) (REG_SPI_BASE(i) + SPI_ADDR_OFFSET) + +/* The CSV actually is wrong here. It indicates that the lower 8 bits of + * this register are reserved. This is not true, all 32 bits of + * SPI_ADDR_REG are usable/used. + */ + +#define SPI_CTRL_OFFSET (0x8) +#define SPI_CTRL_REG (i) (REG_SPI_BASE(i) + SPI_CTRL_OFFSET) + +/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */ + +/* Description: In command address write-data (MOSI) phases + * 1: LSB first + * 0: MSB first + */ + +#define SPI_WR_BIT_ORDER (BIT(26)) +#define SPI_WR_BIT_ORDER_M (BIT(26)) +#define SPI_WR_BIT_ORDER_V 0x1 +#define SPI_WR_BIT_ORDER_S 26 + +/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */ + +/* Description: In read-data (MISO) phase + * 1: LSB first + * 0: MSB first + */ + +#define SPI_RD_BIT_ORDER (BIT(25)) +#define SPI_RD_BIT_ORDER_M (BIT(25)) +#define SPI_RD_BIT_ORDER_V 0x1 +#define SPI_RD_BIT_ORDER_S 25 + +/* SPI_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ + +/* Description: In the read operations address phase and read-data phase + * apply 4 signals. + * 1: enable + * 0: disable. + */ + +#define SPI_FREAD_QIO (BIT(24)) +#define SPI_FREAD_QIO_M (BIT(24)) +#define SPI_FREAD_QIO_V 0x1 +#define SPI_FREAD_QIO_S 24 + +/* SPI_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ + +/* Description: In the read operations address phase and read-data phase + * apply 2 signals. + * 1: enable + * 0: disable. + */ + +#define SPI_FREAD_DIO (BIT(23)) +#define SPI_FREAD_DIO_M (BIT(23)) +#define SPI_FREAD_DIO_V 0x1 +#define SPI_FREAD_DIO_S 23 + +/* SPI_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ + +/* Description: two bytes data will be written to status register when it + * is set. + * 1: enable + * 0: disable. + */ + +#define SPI_WRSR_2B (BIT(22)) +#define SPI_WRSR_2B_M (BIT(22)) +#define SPI_WRSR_2B_V 0x1 +#define SPI_WRSR_ 2B_S 22 + +/* SPI_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ + +/* Description: Write protect signal output when SPI is idle. + * 1: output high + * 0: output low. + */ + +#define SPI_WP_REG (BIT(21)) +#define SPI_WP_REG_M (BIT(21)) +#define SPI_WP_REG_V 0x1 +#define SPI_WP_REG_S 21 + +/* SPI_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ + +/* Description: In the read operations read-data phase apply 4 signals. + * 1: enable + * 0: disable. + */ + +#define SPI_FREAD_QUAD (BIT(20)) +#define SPI_FREAD_QUAD_M (BIT(20)) +#define SPI_FREAD_QUAD_V 0x1 +#define SPI_FREAD_QUAD_S 20 + +/* SPI_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ + +/* Description: The Device ID is read out to SPI_RD_STATUS register, this + * bit combine with spi_flash_res bit. + * 1: enable + * 0: disable. + */ + +#define SPI_RESANDRES (BIT(15)) +#define SPI_RESANDRES_M (BIT(15)) +#define SPI_RESANDRES_V 0x1 +#define SPI_RESANDRES_S 15 + +/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +/* Description: In the read operations read-data phase apply 2 signals. + * 1: enable + * 0: disable. + */ + +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (BIT(14)) +#define SPI_FREAD_DUAL_V 0x1 +#define SPI_FREAD_DUAL_S 14 + +/* SPI_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ + +/* Description: This bit enable the bits: + * spi_fread_qio, spi_fread_dio, spi_fread_qout and spi_fread_dout. + * 1: enable + * 0: disable. + */ + +#define SPI_FASTRD_MODE (BIT(13)) +#define SPI_FASTRD_MODE_M (BIT(13)) +#define SPI_FASTRD_MODE_V 0x1 +#define SPI_FASTRD_MODE_S 13 + +/* SPI_WAIT_FLASH_IDLE_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +/* Description: wait flash idle when program flash or erase flash. + * 1: enable + * 0: disable. + */ + +#define SPI_WAIT_FLASH_IDLE_EN (BIT(12)) +#define SPI_WAIT_FLASH_IDLE_EN_M (BIT(12)) +#define SPI_WAIT_FLASH_IDLE_EN_V 0x1 +#define SPI_WAIT_FLASH_IDLE_EN_S 12 + +/* SPI_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +/* Description: For SPI1 enable crc32 when writing encrypted data to flash. + * 1: enable + * 0: disable + */ + +#define SPI_TX_CRC_EN (BIT(11)) +#define SPI_TX_CRC_EN_M (BIT(11)) +#define SPI_TX_CRC_EN_V 0x1 +#define SPI_TX_CRC_EN_S 11 + +/* SPI_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ + +/* Description: For SPI1 initialize crc32 module before writing encrypted + * data to flash. Active low. + */ + +#define SPI_FCS_CRC_EN (BIT(10)) +#define SPI_FCS_CRC_EN_M (BIT(10)) +#define SPI_FCS_CRC_EN_V 0x1 +#define SPI_FCS_CRC_EN_S 10 + +#define SPI_CTRL1_OFFSET (0xC) +#define SPI_CTRL1_REG (i) (REG_SPI_BASE(i) + SPI_CTRL1_OFFSET) + +/* SPI_CS_HOLD_DELAY : R/W ;bitpos:[31:28] ;default: 4'h5 ; */ + +/* Description: SPI cs signal is delayed by spi clock cycles */ + +#define SPI_CS_HOLD_DELAY 0x0000000F +#define SPI_CS_HOLD_DELAY_M ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S)) +#define SPI_CS_HOLD_DELAY_V 0xF +#define SPI_CS_HOLD_DELAY_S 28 + +/* SPI_CS_HOLD_DELAY_RES : R/W ;bitpos:[27:16] ;default: 12'hfff ; */ + +/* Description: Delay cycles of resume Flash when resume Flash is enable + * by spi clock. + */ + +#define SPI_CS_HOLD_DELAY_RES 0x00000FFF +#define SPI_CS_HOLD_DELAY_RES_M ((SPI_CS_HOLD_DELAY_RES_V)<<(SPI_CS_HOLD_DELAY_RES_S)) +#define SPI_CS_HOLD_DELAY_RES_V 0xFFF +#define SPI_CS_HOLD_DELAY_RES_S 16 + +#define SPI_RD_STATUS_OFFSET (0x10) +#define SPI_RD_STATUS_REG (i) (REG_SPI_BASE(i) + SPI_RD_STATUS_OFFSET) + +/* SPI_STATUS_EXT : R/W ;bitpos:[31:24] ;default: 8'h00 ; */ + +/* Description: In the slave mode,it is the status for master to read out. */ + +#define SPI_STATUS_EXT 0x000000FF +#define SPI_STATUS_EXT_M ((SPI_STATUS_EXT_V)<<(SPI_STATUS_EXT_S)) +#define SPI_STATUS_EXT_V 0xFF +#define SPI_STATUS_EXT_S 24 + +/* SPI_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ + +/* Description: Mode bits in the flash fast read mode, it is combined with + * spi_fastrd_mode bit. + */ + +#define SPI_WB_MODE 0x000000FF +#define SPI_WB_MODE_M ((SPI_WB_MODE_V)<<(SPI_WB_MODE_S)) +#define SPI_WB_MODE_V 0xFF +#define SPI_WB_MODE_S 16 + +/* SPI_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ + +/* Description: In the slave mode, it is the status for master to read out. */ + +#define SPI_S_STATUS 0x0000FFFF +#define SPI_S_STATUS_M ((SPI_STATUS_V)<<(SPI_STATUS_S)) +#define SPI_S_STATUS_V 0xFFFF +#define SPI_S_STATUS_S 0 + +#define SPI_CTRL2_OFFSET (0x14) +#define SPI_CTRL2_REG (i) (REG_SPI_BASE(i) + SPI_CTRL2_OFFSET) + +/* SPI_CS_DELAY_NUM : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ + +/* Description: spi_cs signal is delayed by system clock cycles */ + +#define SPI_CS_DELAY_NUM 0x0000000F +#define SPI_CS_DELAY_NUM_M ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S)) +#define SPI_CS_DELAY_NUM_V 0xF +#define SPI_CS_DELAY_NUM_S 28 + +/* SPI_CS_DELAY_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */ + +/* Description: spi_cs signal is delayed by spi_clk. + * 0: zero + * 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle + * else delayed by one cycle + * 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle + * else delayed by half cycle + * 3: delayed one cycle + */ + +#define SPI_CS_DELAY_MODE 0x00000003 +#define SPI_CS_DELAY_MODE_M ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S)) +#define SPI_CS_DELAY_MODE_V 0x3 +#define SPI_CS_DELAY_MODE_S 26 + +/* SPI_MOSI_DELAY_NUM : R/W ;bitpos:[25:23] ;default: 3'h0 ; */ + +/* Description: MOSI signals are delayed by system clock cycles */ + +#define SPI_MOSI_DELAY_NUM 0x00000007 +#define SPI_MOSI_DELAY_NUM_M ((SPI_MOSI_DELAY_NUM_V)<<(SPI_MOSI_DELAY_NUM_S)) +#define SPI_MOSI_DELAY_NUM_V 0x7 +#define SPI_MOSI_DELAY_NUM_S 23 + +/* SPI_MOSI_DELAY_MODE : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ + +/* Description: MOSI signals are delayed by spi_clk. + * 0: zero + * 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle + * else delayed by one cycle + * 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle + * else delayed by half cycle + * 3: delayed one cycle + */ + +#define SPI_MOSI_DELAY_MODE 0x00000003 +#define SPI_MOSI_DELAY_MODE_M ((SPI_MOSI_DELAY_MODE_V)<<(SPI_MOSI_DELAY_MODE_S)) +#define SPI_MOSI_DELAY_MODE_V 0x3 +#define SPI_MOSI_DELAY_MODE_S 21 + +/* SPI_MISO_DELAY_NUM : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ + +/* Description: MISO signals are delayed by system clock cycles */ + +#define SPI_MISO_DELAY_NUM 0x00000007 +#define SPI_MISO_DELAY_NUM_M ((SPI_MISO_DELAY_NUM_V)<<(SPI_MISO_DELAY_NUM_S)) +#define SPI_MISO_DELAY_NUM_V 0x7 +#define SPI_MISO_DELAY_NUM_S 18 + +/* SPI_MISO_DELAY_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ + +/* Description: MISO signals are delayed by spi_clk. + * 0: zero + * 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle + * else delayed by one cycle + * 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle + * else delayed by half cycle + * 3: delayed one cycle + */ + +#define SPI_MISO_DELAY_MODE 0x00000003 +#define SPI_MISO_DELAY_MODE_M ((SPI_MISO_DELAY_MODE_V)<<(SPI_MISO_DELAY_MODE_S)) +#define SPI_MISO_DELAY_MODE_V 0x3 +#define SPI_MISO_DELAY_MODE_S 16 + +/* SPI_CK_OUT_HIGH_MODE : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ + +/* Description: modify spi clock duty ratio when the value is lager than 8, + * the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits. + */ + +#define SPI_CK_OUT_HIGH_MODE 0x0000000F +#define SPI_CK_OUT_HIGH_MODE_M ((SPI_CK_OUT_HIGH_MODE_V)<<(SPI_CK_OUT_HIGH_MODE_S)) +#define SPI_CK_OUT_HIGH_MODE_V 0xF +#define SPI_CK_OUT_HIGH_MODE_S 12 + +/* SPI_CK_OUT_LOW_MODE : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ + +/* Description: modify spi clock duty ratio when the value is lager than 8, + * the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits. + */ + +#define SPI_CK_OUT_LOW_MODE 0x0000000F +#define SPI_CK_OUT_LOW_MODE_M ((SPI_CK_OUT_LOW_MODE_V)<<(SPI_CK_OUT_LOW_MODE_S)) +#define SPI_CK_OUT_LOW_MODE_V 0xF +#define SPI_CK_OUT_LOW_MODE_S 8 + +/* SPI_HOLD_TIME : R/W ;bitpos:[7:4] ;default: 4'h1 ; */ + +/* Description: delay cycles of cs pin by spi clock, this bits combined with + * spi_cs_hold bit. + */ + +#define SPI_HOLD_TIME 0x0000000F +#define SPI_HOLD_TIME_M ((SPI_HOLD_TIME_V)<<(SPI_HOLD_TIME_S)) +#define SPI_HOLD_TIME_V 0xF +#define SPI_HOLD_TIME_S 4 + +/* SPI_SETUP_TIME : R/W ;bitpos:[3:0] ;default: 4'h1 ; */ + +/* Description: (cycles-1) of ¡°prepare¡± phase by spi clock, this bits + * combined with spi_cs_setup bit. + */ + +#define SPI_SETUP_TIME 0x0000000F +#define SPI_SETUP_TIME_M ((SPI_SETUP_TIME_V)<<(SPI_SETUP_TIME_S)) +#define SPI_SETUP_TIME_V 0xF +#define SPI_SETUP_TIME_S 0 + +#define SPI_CLOCK_OFFSET (0x18) +#define SPI_CLOCK_REG (i) (REG_SPI_BASE(i) + SPI_CLOCK_OFFSET) + +/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ + +/* Description: In the master mode 1: spi_clk is equal to system 0: spi_clk + * is divided from system clock. + */ + +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_V 0x1 +#define SPI_CLK_EQU_SYSCLK_S 31 + +/* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */ + +/* Description: In the master mode it is pre-divider of spi_clk. */ + +#define SPI_CLKDIV_PRE 0x00001FFF +#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S)) +#define SPI_CLKDIV_PRE_V 0x1FFF +#define SPI_CLKDIV_PRE_S 18 + +/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */ + +/* Description: In the master mode it is the divider of spi_clk. So spi_clk + * frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1) + */ + +#define SPI_CLKCNT_N 0x0000003F +#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S)) +#define SPI_CLKCNT_N_V 0x3F +#define SPI_CLKCNT_N_S 12 + +/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */ + +/* Description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). + * In the slave mode it must be 0. + */ + +#define SPI_CLKCNT_H 0x0000003F +#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S)) +#define SPI_CLKCNT_H_V 0x3F +#define SPI_CLKCNT_H_S 6 + +/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ + +/* Description: In the master mode it must be equal to spi_clkcnt_N. + * In the slave mode it must be 0. + */ + +#define SPI_CLKCNT_L 0x0000003F +#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S)) +#define SPI_CLKCNT_L_V 0x3F +#define SPI_CLKCNT_L_S 0 + +#define SPI_USER_OFFSET (0x1C) +#define SPI_USER_REG (i) (REG_SPI_BASE(i) + SPI_USER_OFFSET) + +/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ + +/* Description: This bit enable the command phase of an operation. */ + +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (BIT(31)) +#define SPI_USR_COMMAND_V 0x1 +#define SPI_USR_COMMAND_S 31 + +/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: This bit enable the address phase of an operation. */ + +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (BIT(30)) +#define SPI_USR_ADDR_V 0x1 +#define SPI_USR_ADDR_S 30 + +/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: This bit enable the dummy phase of an operation. */ + +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (BIT(29)) +#define SPI_USR_DUMMY_V 0x1 +#define SPI_USR_DUMMY_S 29 + +/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +/* Description: This bit enable the read-data phase of an operation. */ + +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (BIT(28)) +#define SPI_USR_MISO_V 0x1 +#define SPI_USR_MISO_S 28 + +/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ + +/* Description: This bit enable the write-data phase of an operation. */ + +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (BIT(27)) +#define SPI_USR_MOSI_V 0x1 +#define SPI_USR_MOSI_S 27 + +/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ + +/* Description: spi clock is disable in dummy phase when the bit is enable. */ + +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_USR_DUMMY_IDLE_V 0x1 +#define SPI_USR_DUMMY_IDLE_S 26 + +/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ + +/* Description: write-data phase only access to high-part of the buffer + * spi_w8~spi_w15. + * 1: enable + * 0: disable. + */ + +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_V 0x1 +#define SPI_USR_MOSI_HIGHPART_S 25 + +/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ + +/* Description: read-data phase only access to high-part of the buffer + * spi_w8~spi_w15. + * 1: enable + * 0: disable. + */ + +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_USR_MISO_HIGHPART_V 0x1 +#define SPI_USR_MISO_HIGHPART_S 24 + +/* SPI_USR_PREP_HOLD : R/W ;bitpos:[23] ;default: 1'b0 ; */ + +/* Description: spi is hold at prepare state the bit combined with + * spi_usr_hold_pol bit. + */ + +#define SPI_USR_PREP_HOLD (BIT(23)) +#define SPI_USR_PREP_HOLD_M (BIT(23)) +#define SPI_USR_PREP_HOLD_V 0x1 +#define SPI_USR_PREP_HOLD_S 23 + +/* SPI_USR_CMD_HOLD : R/W ;bitpos:[22] ;default: 1'b0 ; */ + +/* Description: spi is hold at command state the bit combined with + * spi_usr_hold_pol bit. + */ + +#define SPI_USR_CMD_HOLD (BIT(22)) +#define SPI_USR_CMD_HOLD_M (BIT(22)) +#define SPI_USR_CMD_HOLD_V 0x1 +#define SPI_USR_CMD_HOLD_S 22 + +/* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ + +/* Description: spi is hold at address state the bit combined with + * spi_usr_hold_pol bit. + */ + +#define SPI_USR_ADDR_HOLD (BIT(21)) +#define SPI_USR_ADDR_HOLD_M (BIT(21)) +#define SPI_USR_ADDR_HOLD_V 0x1 +#define SPI_USR_ADDR_HOLD_S 21 + +/* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ + +/* Description: spi is hold at dummy state the bit combined with + * spi_usr_hold_pol bit. + */ + +#define SPI_USR_DUMMY_HOLD (BIT(20)) +#define SPI_USR_DUMMY_HOLD_M (BIT(20)) +#define SPI_USR_DUMMY_HOLD_V 0x1 +#define SPI_USR_DUMMY_HOLD_S 20 + +/* SPI_USR_DIN_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ + +/* Description: spi is hold at data in state the bit combined with + * spi_usr_hold_pol bit. + */ + +#define SPI_USR_DIN_HOLD (BIT(19)) +#define SPI_USR_DIN_HOLD_M (BIT(19)) +#define SPI_USR_DIN_HOLD_V 0x1 +#define SPI_USR_DIN_HOLD_S 19 + +/* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ + +/* Description: spi is hold at data out state the bit combined with + * spi_usr_hold_pol bit. + */ + +#define SPI_USR_DOUT_HOLD (BIT(18)) +#define SPI_USR_DOUT_HOLD_M (BIT(18)) +#define SPI_USR_DOUT_HOLD_V 0x1 +#define SPI_USR_DOUT_HOLD_S 18 + +/* SPI_USR_HOLD_POL : R/W ;bitpos:[17] ;default: 1'b0 ; */ + +/* Description: It is combined with hold bits to set the polarity of spi + * hold line + * 1: spi will be held when spi hold line is high + * 0: spi will be held when spi hold line is low + */ + +#define SPI_USR_HOLD_POL (BIT(17)) +#define SPI_USR_HOLD_POL_M (BIT(17)) +#define SPI_USR_HOLD_POL_V 0x1 +#define SPI_USR_HOLD_POL_S 17 + +/* SPI_SIO : R/W ;bitpos:[16] ;default: 1'b0 ; */ + +/* Description: Set the bit to enable 3-line half duplex communication mosi + * and miso signals share the same pin. + * 1: enable + * 0: disable. + */ + +#define SPI_SIO (BIT(16)) +#define SPI_SIO_M (BIT(16)) +#define SPI_SIO_V 0x1 +#define SPI_SIO_S 16 + +/* SPI_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: In the write operations address phase and read-data phase + * apply 4 signals. + */ + +#define SPI_FWRITE_QIO (BIT(15)) +#define SPI_FWRITE_QIO_M (BIT(15)) +#define SPI_FWRITE_QIO_V 0x1 +#define SPI_FWRITE_QIO_S 15 + +/* SPI_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +/* Description: In the write operations address phase and read-data phase + * apply 2 signals. + */ + +#define SPI_FWRITE_DIO (BIT(14)) +#define SPI_FWRITE_DIO_M (BIT(14)) +#define SPI_FWRITE_DIO_V 0x1 +#define SPI_FWRITE_DIO_S 14 + +/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +/* Description: In the write operations read-data phase apply 4 signals */ + +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (BIT(13)) +#define SPI_FWRITE_QUAD_V 0x1 +#define SPI_FWRITE_QUAD_S 13 + +/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +/* Description: In the write operations read-data phase apply 2 signals */ + +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (BIT(12)) +#define SPI_FWRITE_DUAL_V 0x1 +#define SPI_FWRITE_DUAL_S 12 + +/* SPI_WR_BYTE_ORDER : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +/* Description: In command address write-data (MOSI) phases + * 1: big-endian + * 0: litte_endian + */ + +#define SPI_WR_BYTE_ORDER (BIT(11)) +#define SPI_WR_BYTE_ORDER_M (BIT(11)) +#define SPI_WR_BYTE_ORDER_V 0x1 +#define SPI_WR_BYTE_ORDER_S 11 + +/* SPI_RD_BYTE_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: In read-data (MISO) phase + * 1: big-endian + * 0: little_endian + */ + +#define SPI_RD_BYTE_ORDER (BIT(10)) +#define SPI_RD_BYTE_ORDER_M (BIT(10)) +#define SPI_RD_BYTE_ORDER_V 0x1 +#define SPI_RD_BYTE_ORDER_S 10 + +/* SPI_CK_OUT_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: the bit combined with spi_mosi_delay_mode bits to set mosi + * signal delay mode. + */ + +#define SPI_CK_OUT_EDGE (BIT(7)) +#define SPI_CK_OUT_EDGE_M (BIT(7)) +#define SPI_CK_OUT_EDGE_V 0x1 +#define SPI_CK_OUT_EDGE_S 7 + +/* SPI_CK_I_EDGE : R/W ;bitpos:[6] ;default: 1'b1 ; */ + +/* Description: In the slave mode the bit is same as spi_ck_out_edge in + * master mode. It is combined with spi_miso_delay_mode bits. + */ + +#define SPI_CK_I_EDGE (BIT(6)) +#define SPI_CK_I_EDGE_M (BIT(6)) +#define SPI_CK_I_EDGE_V 0x1 +#define SPI_CK_I_EDGE_S 6 + +/* SPI_CS_SETUP : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: spi cs is enable when ospi is in "prepare" phase. + * 1: enable + * 0: disable. + */ + +#define SPI_CS_SETUP (BIT(5)) +#define SPI_CS_SETUP_M (BIT(5)) +#define SPI_CS_SETUP_V 0x1 +#define SPI_CS_SETUP_S 5 + +/* SPI_CS_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: spi cs keep low when spi is in ¡°done¡± phase. + * 1: enable + * 0: disable. + */ + +#define SPI_CS_HOLD (BIT(4)) +#define SPI_CS_HOLD_M (BIT(4)) +#define SPI_CS_HOLD_V 0x1 +#define SPI_CS_HOLD_S 4 + +/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: Set the bit to enable full duplex communication. + * 1: enable + * 0: disable. + */ + +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (BIT(0)) +#define SPI_DOUTDIN_V 0x1 +#define SPI_DOUTDIN_S 0 + +#define SPI_USER1_OFFSET (0x20) +#define SPI_USER1_REG (i) (REG_SPI_BASE(i) + SPI_USER1_OFFSET) + +/* SPI_USR_ADDR_BITLEN : RO ;bitpos:[31:26] ;default: 6'd23 ; */ + +/* Description: The length in bits of address phase. The register value shall + * be (bit_num-1). + */ + +#define SPI_USR_ADDR_BITLEN 0x0000003F +#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S)) +#define SPI_USR_ADDR_BITLEN_V 0x3F +#define SPI_USR_ADDR_BITLEN_S 26 + +/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */ + +/* Description: The length in spi_clk cycles of dummy phase. The register + * value shall be (cycle_num-1). + */ + +#define SPI_USR_DUMMY_CYCLELEN 0x000000FF +#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S)) +#define SPI_USR_DUMMY_CYCLELEN_V 0xFF +#define SPI_USR_DUMMY_CYCLELEN_S 0 + +#define SPI_USER2_OFFSET (0x24) +#define SPI_USER2_REG (i) (REG_SPI_BASE(i) + SPI_USER2_OFFSET) + +/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ + +/* Description: The length in bits of command phase. The register value shall + * be (bit_num-1) + */ + +#define SPI_USR_COMMAND_BITLEN 0x0000000F +#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S)) +#define SPI_USR_COMMAND_BITLEN_V 0xF +#define SPI_USR_COMMAND_BITLEN_S 28 + +/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ + +/* Description: The value of command. */ + +#define SPI_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S)) +#define SPI_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_USR_COMMAND_VALUE_S 0 + +#define SPI_MOSI_DLEN_OFFSET (0x28) +#define SPI_MOSI_DLEN_REG (i) (REG_SPI_BASE(i) + SPI_MOSI_DLEN_OFFSET) + +/* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ + +/* Description: The length in bits of write-data. The register value shall be + * (bit_num-1). + */ + +#define SPI_USR_MOSI_DBITLEN 0x00FFFFFF +#define SPI_USR_MOSI_DBITLEN_M ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S)) +#define SPI_USR_MOSI_DBITLEN_V 0xFFFFFF +#define SPI_USR_MOSI_DBITLEN_S 0 + +#define SPI_MISO_DLEN_OFFSET (0x2C) +#define SPI_MISO_DLEN_REG (i) (REG_SPI_BASE(i) + SPI_MISO_DLEN_OFFSET) + +/* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ + +/* Description: The length in bits of read-data. The register value shall be + * (bit_num-1). + */ + +#define SPI_USR_MISO_DBITLEN 0x00FFFFFF +#define SPI_USR_MISO_DBITLEN_M ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S)) +#define SPI_USR_MISO_DBITLEN_V 0xFFFFFF +#define SPI_USR_MISO_DBITLEN_S 0 + +#define SPI_SLV_WR_STATUS_OFFSET (0x30) +#define SPI_SLV_WR_STATUS_REG(i) (REG_SPI_BASE(i) + SPI_SLV_WR_STATUS_OFFSET) + +/* SPI_SLV_WR_ST : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: In the slave mode this register are the status register for + * the master to write into. In the master mode this register are the higher + * 32bits in the 64 bits address condition. + */ + +#define SPI_SLV_WR_ST 0xFFFFFFFF +#define SPI_SLV_WR_ST_M ((SPI_SLV_WR_ST_V)<<(SPI_SLV_WR_ST_S)) +#define SPI_SLV_WR_ST_V 0xFFFFFFFF +#define SPI_SLV_WR_ST_S 0 + +#define SPI_PIN_OFFSET (0x34) +#define SPI_PIN_REG(i) (REG_SPI_BASE(i) + SPI_PIN_OFFSET) + +/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: spi cs line keep low when the bit is set. */ + +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_V 0x1 +#define SPI_CS_KEEP_ACTIVE_S 30 + +/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: + * 1: spi clk line is high when idle + * 0: spi clk line is low when idle. + */ + +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (BIT(29)) +#define SPI_CK_IDLE_EDGE_V 0x1 +#define SPI_CK_IDLE_EDGE_S 29 + +/* SPI_MASTER_CK_SEL : R/W ;bitpos:[13:11] ;default: 3'b0 ; */ + +/* Description: In the master mode spi cs line is enable as spi clk it is + * combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis. + */ + +#define SPI_MASTER_CK_SEL 0x00000007 +#define SPI_MASTER_CK_SEL_M ((SPI_MASTER_CK_SEL_V)<<(SPI_MASTER_CK_SEL_S)) +#define SPI_MASTER_CK_SEL_V 0x07 +#define SPI_MASTER_CK_SEL_S 11 + +/* SPI_MASTER_CS_POL : R/W ;bitpos:[8:6] ;default: 3'b0 ; */ + +/* Description: In the master mode the bits are the polarity of spi cs + * line the value is equivalent to spi_cs ^ spi_master_cs_pol. + */ + +#define SPI_MASTER_CS_POL 0x00000007 +#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S)) +#define SPI_MASTER_CS_POL_V 0x7 +#define SPI_MASTER_CS_POL_S 6 + +/* SPI_CK_DIS : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: 1: spi clk out disable 0: spi clk out enable */ + +#define SPI_CK_DIS (BIT(5)) +#define SPI_CK_DIS_M (BIT(5)) +#define SPI_CK_DIS_V 0x1 +#define SPI_CK_DIS_S 5 + +/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */ + +/* Description: SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is + * from/to CS2 pin + */ + +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (BIT(2)) +#define SPI_CS2_DIS_V 0x1 +#define SPI_CS2_DIS_S 2 + +/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ + +/* Description: SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is + * from/to CS1 pin + */ + +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (BIT(1)) +#define SPI_CS1_DIS_V 0x1 +#define SPI_CS 1_DIS_S 1 + +/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is + * from/to CS0 pin + */ + +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (BIT(0)) +#define SPI_CS0_DIS_V 0x1 +#define SPI_CS0_DIS_S 0 + +#define SPI_SLAVE_OFFSET (0x38) +#define SPI_SLAVE_REG (i) (REG_SPI_BASE(i) + SPI_SLAVE_OFFSET) + +/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +/* Description: Software reset enable, reset the spi clock line cs line + * and data lines. + */ + +#define SPI_SYNC_RESET (BIT(31)) +#define SPI_SYNC_RESET_M (BIT(31)) +#define SPI_SYNC_RESET_V 0x1 +#define SPI_SYNC_RESET_S 31 + +/* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: + * 1: slave mode + * 0: master mode. + */ + +#define SPI_SLAVE_MODE (BIT(30)) +#define SPI_SLAVE_MODE_M (BIT(30)) +#define SPI_SLAVE_MODE_V 0x1 +#define SPI_SLAVE_MODE_S 30 + +/* SPI_SLV_WR_RD_BUF_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: write and read buffer enable in the slave mode */ + +#define SPI_SLV_WR_RD_BUF_EN (BIT(29)) +#define SPI_SLV_WR_RD_BUF_EN_M (BIT(29)) +#define SPI_SLV_WR_RD_BUF_EN_V 0x1 +#define SPI_SLV_WR_RD_BUF_EN_S 29 + +/* SPI_SLV_WR_RD_STA_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +/* Description: write and read status enable in the slave mode */ + +#define SPI_SLV_WR_RD_STA_EN (BIT(28)) +#define SPI_SLV_WR_RD_STA_EN_M (BIT(28)) +#define SPI_SLV_WR_RD_STA_EN_V 0x1 +#define SPI_SLV_WR_RD_STA_EN_S 28 + +/* SPI_SLV_CMD_DEFINE : R/W ;bitpos:[27] ;default: 1'b0 ; */ + +/* Description: 1: slave mode commands are defined in SPI_SLAVE3. + * 0: slave mode commands are fixed as: + * 1: write-status + * 2: write-buffer and + * 3: read-buffer. + */ + +#define SPI_SLV_CMD_DEFINE (BIT(27)) +#define SPI_SLV_CMD_DEFINE_M (BIT(27)) +#define SPI_SLV_CMD_DEFINE_V 0x1 +#define SPI_SLV_CMD_DEFINE_S 27 + +/* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */ + +/* Description: The operations counter in both the master mode and the slave + * mode. 4: read-status + */ + +#define SPI_TRANS_CNT 0x0000000F +#define SPI_TRANS_CNT_M ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S)) +#define SPI_TRANS_CNT_V 0xF +#define SPI_TRANS_CNT_S 23 + +/* SPI_SLV_LAST_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */ + +/* Description: In the slave mode it is the state of spi state machine. */ + +#define SPI_SLV_LAST_STATE 0x00000007 +#define SPI_SLV_LAST_STATE_M ((SPI_SLV_LAST_STATE_V)<<(SPI_SLV_LAST_STATE_S)) +#define SPI_SLV_LAST_STATE_V 0x7 +#define SPI_SLV_LAST_STATE_S 20 + +/* SPI_SLV_LAST_COMMAND : RO ;bitpos:[19:17] ;default: 3'b0 ; */ + +/* Description: In the slave mode it is the value of command. */ + +#define SPI_SLV_LAST_COMMAND 0x00000007 +#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S)) +#define SPI_SLV_LAST_COMMAND_V 0x7 +#define SPI_SLV_LAST_COMMAND_S 17 + +/* SPI_CS_I_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ + +/* Description: In the slave mode this bits used to synchronize the input + * spi cs signal and eliminate spi cs jitter. + */ + +#define SPI_CS_I_MODE 0x00000003 +#define SPI_CS_I_MODE_M ((SPI_CS_I_MODE_V)<<(SPI_CS_I_MODE_S)) +#define SPI_CS_I_MODE_V 0x3 +#define SPI_CS_I_MODE_S 10 + +/* SPI_INT_EN : R/W ;bitpos:[9:5] ;default: 5'b1_0000 ; */ + +/* Description: Interrupt enable bits for the below 5 sources */ + +#define SPI_INT_EN 0x0000001F +#define SPI_INT_EN_M ((SPI_INT_EN_V)<<(SPI_INT_EN_S)) +#define SPI_INT_EN_V 0x1F +#define SPI_INT_EN_S 5 + +/* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: The interrupt raw bit for the completion of any operation + * in both the master mode and the slave mode. + */ + +#define SPI_TRANS_DONE (BIT(4)) +#define SPI_TRANS_DONE_M (BIT(4)) +#define SPI_TRANS_DONE_V 0x1 +#define SPI_TRANS_DONE_S 4 + +/* SPI_SLV_WR_STA_DONE : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: The interrupt raw bit for the completion of write-status + * operation in the slave mode. + */ + +#define SPI_SLV_WR_STA_DONE (BIT(3)) +#define SPI_SLV_WR_STA_DONE_M (BIT(3)) +#define SPI_SLV_WR_STA_DONE_V 0x1 +#define SPI_SLV_WR_STA_DONE_S 3 + +/* SPI_SLV_RD_STA_DONE : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: The interrupt raw bit for the completion of read-status + * operation in the slave mode. + */ + +#define SPI_SLV_RD_STA_DONE (BIT(2)) +#define SPI_SLV_RD_STA_DONE_M (BIT(2)) +#define SPI_SLV_RD_STA_DONE_V 0x1 +#define SPI_SLV_RD_STA_DONE_S 2 + +/* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: The interrupt raw bit for the completion of write-buffer + * operation in the slave mode. + */ + +#define SPI_SLV_WR_BUF_DONE (BIT(1)) +#define SPI_SLV_WR_BUF_DONE_M (BIT(1)) +#define SPI_SLV_WR_BUF_DONE_V 0x1 +#define SPI_SLV_WR_BUF_DONE_S 1 + +/* SPI_SLV_RD_BUF_DONE : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: The interrupt raw bit for the completion of read-buffer + * operation in the slave mode. + */ + +#define SPI_SLV_RD_BUF_DONE (BIT(0)) +#define SPI_SLV_RD_BUF_DONE_M (BIT(0)) +#define SPI_SLV_RD_BUF_DONE_V 0x1 +#define SPI_SLV_RD_BUF_DONE_S 0 + +#define SPI_SLAVE1_OFFSET (0x3C) +#define SPI_SLAVE1_REG (i) (REG_SPI_BASE(i) + SPI_SLAVE1_OFFSET) + +/* SPI_SLV_STATUS_BITLEN : R/W ;bitpos:[31:27] ;default: 5'b0 ; */ + +/* Description: In the slave mode it is the length of status bit. */ + +#define SPI_SLV_STATUS_BITLEN 0x0000001F +#define SPI_SLV_STATUS_BITLEN_M ((SPI_SLV_STATUS_BITLEN_V)<<(SPI_SLV_STATUS_BITLEN_S)) +#define SPI_SLV_STATUS_BITLEN_V 0x1F +#define SPI_SLV_STATUS_BITLEN_S 27 + +/* SPI_SLV_STATUS_FAST_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ + +/* Description: In the slave mode enable fast read status. */ + +#define SPI_SLV_STATUS_FAST_EN (BIT(26)) +#define SPI_SLV_STATUS_FAST_EN_M (BIT(26)) +#define SPI_SLV_STATUS_FAST_EN_V 0x1 +#define SPI_SLV_STATUS_FAST_EN_S 26 + +/* SPI_SLV_STATUS_READBACK : R/W ;bitpos:[25] ;default: 1'b1 ; */ + +/* Description: In the slave mode + * 1:read register of SPI_SLV_WR_STATUS + * 0: read register of SPI_RD_STATUS. + */ + +#define SPI_SLV_STATUS_READBACK (BIT(25)) +#define SPI_SLV_STATUS_READBACK_M (BIT(25)) +#define SPI_SLV_STATUS_READBACK_V 0x1 +#define SPI_SLV_STATUS_READBACK_S 25 + +/* SPI_SLV_RD_ADDR_BITLEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ + +/* Description: In the slave mode it is the address length in bits for + * read-buffer operation. The register value shall be (bit_num-1). + */ + +#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F +#define SPI_SLV_RD_ADDR_BITLEN_M ((SPI_SLV_RD_ADDR_BITLEN_V)<<(SPI_SLV_RD_ADDR_BITLEN_S)) +#define SPI_SLV_RD_ADDR_BITLEN_V 0x3F +#define SPI_SLV_RD_ADDR_BITLEN_S 10 + +/* SPI_SLV_WR_ADDR_BITLEN : R/W ;bitpos:[9:4] ;default: 6'h0 ; */ + +/* Description: In the slave mode it is the address length in bits for + * write-buffer operation. The register value shall be (bit_num-1). + */ + +#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F +#define SPI_SLV_WR_ADDR_BITLEN_M ((SPI_SLV_WR_ADDR_BITLEN_V)<<(SPI_SLV_WR_ADDR_BITLEN_S)) +#define SPI_SLV_WR_ADDR_BITLEN_V 0x3F +#define SPI_SLV_WR_ADDR_BITLEN_S 4 + +/* SPI_SLV_WRSTA_DUMMY_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: In the slave mode it is the enable bit of dummy phase for + * write-status operations. + */ + +#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3)) +#define SPI_SLV_WRSTA_DUMMY_EN_M (BIT(3)) +#define SPI_SLV_WRSTA_DUMMY_EN_V 0x1 +#define SPI_SLV_WRSTA_DUMMY_EN_S 3 + +/* SPI_SLV_RDSTA_DUMMY_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: In the slave mode it is the enable bit of dummy phase for + * read-status operations. + */ + +#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2)) +#define SPI_SLV_RDSTA_DUMMY_EN_M (BIT(2)) +#define SPI_SLV_RDSTA_DUMMY_EN_V 0x1 +#define SPI_SLV_RDSTA_DUMMY_EN_S 2 + +/* SPI_SLV_WRBUF_DUMMY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: In the slave mode it is the enable bit of dummy phase for + * write-buffer operations. + */ + +#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1)) +#define SPI_SLV_WRBUF_DUMMY_EN_M (BIT(1)) +#define SPI_SLV_WRBUF_DUMMY_EN_V 0x1 +#define SPI_SLV_WRBUF_DUMMY_EN_S 1 + +/* SPI_SLV_RDBUF_DUMMY_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: In the slave mode it is the enable bit of dummy phase for + * read-buffer operations. + */ + +#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0)) +#define SPI_SLV_RDBUF_DUMMY_EN_M (BIT(0)) +#define SPI_SLV_RDBUF_DUMMY_EN_V 0x1 +#define SPI_SLV_RDBUF_DUMMY_EN_S 0 + +#define SPI_SLAVE2_OFFSET (0x40) +#define SPI_SLAVE2_REG (i) (REG_SPI_BASE(i) + SPI_SLAVE2_OFFSET) + +/* SPI_SLV_WRBUF_DUMMY_CYCLELEN : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ + +/* Description: In the slave mode it is the length in spi_clk cycles of dummy + * phase for write-buffer operations. The register value shall be + * (cycle_num-1). + */ + +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_M ((SPI_SLV_WRBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRBUF_DUMMY_CYCLELEN_S)) +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24 + +/* SPI_SLV_RDBUF_DUMMY_CYCLELEN : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ + +/* Description: In the slave mode it is the length in spi_clk cycles of + * dummy phase for read-buffer operations. The register value shall be + * (cycle_num-1). + */ + +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_M ((SPI_SLV_RDBUF_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDBUF_DUMMY_CYCLELEN_S)) +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16 + +/* SPI_SLV_WRSTA_DUMMY_CYCLELEN : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ + +/* Description: In the slave mode it is the length in spi_clk cycles of + * dummy phase for write-status operations. The register value shall be + * (cycle_num-1). + */ + +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_M ((SPI_SLV_WRSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_WRSTA_DUMMY_CYCLELEN_S)) +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_WRSTA_DUMMY_CYCLELEN_S 8 + +/* SPI_SLV_RDSTA_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ + +/* Description: In the slave mode it is the length in spi_clk cycles of + * dummy phase for read-status operations. The register value shall be + * (cycle_num-1). + */ + +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN 0x000000FF +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_M ((SPI_SLV_RDSTA_DUMMY_CYCLELEN_V)<<(SPI_SLV_RDSTA_DUMMY_CYCLELEN_S)) +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_V 0xFF +#define SPI_SLV_RDSTA_DUMMY_CYCLELEN_S 0 + +#define SPI_SLAVE3_OFFSET (0x44) +#define SPI_SLAVE3_REG (i) (REG_SPI_BASE(i) + SPI_SLAVE3_OFFSET) + +/* SPI_SLV_WRSTA_CMD_VALUE : R/W ;bitpos:[31:24] ;default: 8'b0 ; */ + +/* Description: In the slave mode it is the value of write-status command. */ + +#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF +#define SPI_SLV_WRSTA_CMD_VALUE_M ((SPI_SLV_WRSTA_CMD_VALUE_V)<<(SPI_SLV_WRSTA_CMD_VALUE_S)) +#define SPI_SLV_WRSTA_CMD_VALUE_V 0xFF +#define SPI_SLV_WRSTA_CMD_VALUE_S 24 + +/* SPI_SLV_RDSTA_CMD_VALUE : R/W ;bitpos:[23:16] ;default: 8'b0 ; */ + +/* Description: In the slave mode it is the value of read-status command. */ + +#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF +#define SPI_SLV_RDSTA_CMD_VALUE_M ((SPI_SLV_RDSTA_CMD_VALUE_V)<<(SPI_SLV_RDSTA_CMD_VALUE_S)) +#define SPI_SLV_RDSTA_CMD_VALUE_V 0xFF +#define SPI_SLV_RDSTA_CMD_VALUE_S 16 + +/* SPI_SLV_WRBUF_CMD_VALUE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ + +/* Description: In the slave mode it is the value of write-buffer command. */ + +#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF +#define SPI_SLV_WRBUF_CMD_VALUE_M ((SPI_SLV_WRBUF_CMD_VALUE_V)<<(SPI_SLV_WRBUF_CMD_VALUE_S)) +#define SPI_SLV_WRBUF_CMD_VALUE_V 0xFF +#define SPI_SLV_WRBUF_CMD_VALUE_S 8 + +/* SPI_SLV_RDBUF_CMD_VALUE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ + +/* Description: In the slave mode it is the value of read-buffer command. */ + +#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF +#define SPI_SLV_RDBUF_CMD_VALUE_M ((SPI_SLV_RDBUF_CMD_VALUE_V)<<(SPI_SLV_RDBUF_CMD_VALUE_S)) +#define SPI_SLV_RDBUF_CMD_VALUE_V 0xFF +#define SPI_SLV_RDBUF_CMD_VALUE_S 0 + +#define SPI_SLV_WRBUF_DLEN_OFFSET (0x48) +#define SPI_SLV_WRBUF_DLEN_REG(i) (REG_SPI_BASE(i) + SPI_SLV_WRBUF_DLEN_OFFSET) + +/* SPI_SLV_WRBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ + +/* Description: In the slave mode it is the length in bits for write-buffer + * operations. The register value shall be (bit_num-1). + */ + +#define SPI_SLV_WRBUF_DBITLEN 0x00FFFFFF +#define SPI_SLV_WRBUF_DBITLEN_M ((SPI_SLV_WRBUF_DBITLEN_V)<<(SPI_SLV_WRBUF_DBITLEN_S)) +#define SPI_SLV_WRBUF_DBITLEN_V 0xFFFFFF +#define SPI_SLV_WRBUF_DBITLEN_S 0 + +#define SPI_SLV_RDBUF_DLEN_OFFSET (0x4C) +#define SPI_SLV_RDBUF_DLEN_REG(i) (REG_SPI_BASE(i) + SPI_SLV_RDBUF_DLEN_OFFSET) + +/* SPI_SLV_RDBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ + +/* Description: In the slave mode it is the length in bits for read-buffer + * operations. The register value shall be (bit_num-1). + */ + +#define SPI_SLV_RDBUF_DBITLEN 0x00FFFFFF +#define SPI_SLV_RDBUF_DBITLEN_M ((SPI_SLV_RDBUF_DBITLEN_V)<<(SPI_SLV_RDBUF_DBITLEN_S)) +#define SPI_SLV_RDBUF_DBITLEN_V 0xFFFFFF +#define SPI_SLV_RDBUF_DBITLEN_S 0 + +#define SPI_CACHE_FCTRL_OFFSET (0x50) +#define SPI_CACHE_FCTRL_REG (i) (REG_SPI_BASE(i) + SPI_CACHE_FCTRL_OFFSET) + +/* SPI_CACHE_FLASH_PES_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: For SPI0 spi1 send suspend command before cache read flash + * 1: enable + * 0: disable. + */ + +#define SPI_CACHE_FLASH_PES_EN (BIT(3)) +#define SPI_CACHE_FLASH_PES_EN_M (BIT(3)) +#define SPI_CACHE_FLASH_PES_EN_V 0x1 +#define SPI_CACHE_FLASH_PES_EN_S 3 + +/* SPI_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: For SPI0 cache read flash for user define command + * 1: enable + * 0: disable. + */ + +#define SPI_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_CACHE_FLASH_USR_CMD_M (BIT(2)) +#define SPI_CACHE_FLASH_USR_CMD_V 0x1 +#define SPI_CACHE_FLASH_USR_CMD_S 2 + +/* SPI_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: For SPI0 cache read flash with 4 bytes command + * 1: enable + * 0: disable. + */ + +#define SPI_CACHE_USR_CMD_4BYTE (BIT(1)) +#define SPI_CACHE_USR_CMD_4BYTE_M (BIT(1)) +#define SPI_CACHE_USR_CMD_4BYTE_V 0x1 +#define SPI_CACHE_USR_CMD_4BYTE_S 1 + +/* SPI_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: For SPI0 Cache access enable + * 1: enable + * 0: disable. + */ + +#define SPI_CACHE_REQ_EN (BIT(0)) +#define SPI_CACHE_REQ_EN_M (BIT(0)) +#define SPI_CACHE_REQ_EN_V 0x1 +#define SPI_CACHE_REQ_EN_S 0 + +#define SPI_CACHE_SCTRL_OFFSET (0x54) +#define SPI_CACHE_SCTRL_REG (i) (REG_SPI_BASE(i) + SPI_CACHE_SCTRL_OFFSET) + +/* SPI_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[28] ;default: 1'b1 ; */ + +/* Description: For SPI0 In the spi sram mode cache write sram for user + * define command + */ + +#define SPI_CACHE_SRAM_USR_WCMD (BIT(28)) +#define SPI_CACHE_SRAM_USR_WCMD_M (BIT(28)) +#define SPI_CACHE_SRAM_USR_WCMD_V 0x1 +#define SPI_CACHE_SRAM_USR_WCMD_S 28 + +/* SPI_SRAM_ADDR_BITLEN : R/W ;bitpos:[27:22] ;default: 6'd23 ; */ + +/* Description: For SPI0 In the sram mode it is the length in bits of + * address phase. The register value shall be (bit_num-1). + */ + +#define SPI_SRAM_ADDR_BITLEN 0x0000003F +#define SPI_SRAM_ADDR_BITLEN_M ((SPI_SRAM_ADDR_BITLEN_V)<<(SPI_SRAM_ADDR_BITLEN_S)) +#define SPI_SRAM_ADDR_BITLEN_V 0x3F +#define SPI_SRAM_ADDR_BITLEN_S 22 + +/* SPI_SRAM_DUMMY_CYCLELEN : R/W ;bitpos:[21:14] ;default: 8'b1 ; */ + +/* Description: For SPI0 In the sram mode it is the length in bits of address + * phase. The register value shall be (bit_num-1). + */ + +#define SPI_SRAM_DUMMY_CYCLELEN 0x000000FF +#define SPI_SRAM_DUMMY_CYCLELEN_M ((SPI_SRAM_DUMMY_CYCLELEN_V)<<(SPI_SRAM_DUMMY_CYCLELEN_S)) +#define SPI_SRAM_DUMMY_CYCLELEN_V 0xFF +#define SPI_SRAM_DUMMY_CYCLELEN_S 14 + +/* SPI_SRAM_BYTES_LEN : R/W ;bitpos:[13:6] ;default: 8'b32 ; */ + +/* Description: For SPI0 In the sram mode it is the byte length of spi read + * sram data. + */ + +#define SPI_SRAM_BYTES_LEN 0x000000FF +#define SPI_SRAM_BYTES_LEN_M ((SPI_SRAM_BYTES_LEN_V)<<(SPI_SRAM_BYTES_LEN_S)) +#define SPI_SRAM_BYTES_LEN_V 0xFF +#define SPI_SRAM_BYTES_LEN_S 6 + +/* SPI_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */ + +/* Description: For SPI0 In the spi sram mode cache read sram for user + * define command. + */ + +#define SPI_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_CACHE_SRAM_USR_RCMD_M (BIT(5)) +#define SPI_CACHE_SRAM_USR_RCMD_V 0x1 +#define SPI_CACHE_SRAM_USR_RCMD_S 5 + +/* SPI_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */ + +/* Description: For SPI0 In the spi sram mode it is the enable bit of dummy + * phase for read operations. + */ + +#define SPI_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_USR_RD_SRAM_DUMMY_M (BIT(4)) +#define SPI_USR_RD_SRAM_DUMMY_V 0x1 +#define SPI_USR_RD_SRAM_DUMMY_S 4 + +/* SPI_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: For SPI0 In the spi sram mode it is the enable bit of dummy + * phase for write operations. + */ + +#define SPI_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_USR_WR_SRAM_DUMMY_M (BIT(3)) +#define SPI_USR_WR_SRAM_DUMMY_V 0x1 +#define SPI_USR_WR_SRAM_DUMMY_S 3 + +/* SPI_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: For SPI0 In the spi sram mode spi quad I/O mode enable + * 1: enable + * 0: disable + */ + +#define SPI_USR_SRAM_QIO (BIT(2)) +#define SPI_USR_SRAM_QIO_M (BIT(2)) +#define SPI_USR_SRAM_QIO_V 0x1 +#define SPI_USR_SRAM_QIO_S 2 + +/* SPI_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: For SPI0 In the spi sram mode spi dual I/O mode enable + * 1: enable + * 0: disable + */ + +#define SPI_USR_SRAM_DIO (BIT(1)) +#define SPI_USR_SRAM_DIO_M (BIT(1)) +#define SPI_USR_SRAM_DIO_V 0x1 +#define SPI_USR_SRAM_DIO_S 1 + +#define SPI_SRAM_CMD_OFFSET (0x58) +#define SPI_SRAM_CMD_REG (i) (REG_SPI_BASE(i) + SPI_SRAM_CMD_OFFSET) + +/* SPI_SRAM_RSTIO : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: For SPI0 SRAM IO mode reset enable. SRAM IO mode reset + * operation will be triggered when the bit is set. The bit will be cleared + * once the operation done + */ + +#define SPI_SRAM_RSTIO (BIT(4)) +#define SPI_SRAM_RSTIO_M (BIT(4)) +#define SPI_SRAM_RSTIO_V 0x1 +#define SPI_SRAM_RSTIO_S 4 + +/* SPI_SRAM_QIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: For SPI0 SRAM QIO mode enable . SRAM QIO enable command + * will be send when the bit is set. The bit will be cleared once the + * operation done. + */ + +#define SPI_SRAM_QIO (BIT(1)) +#define SPI_SRAM_QIO_M (BIT(1)) +#define SPI_SRAM_QIO_V 0x1 +#define SPI_SRAM_QIO_S 1 + +/* SPI_SRAM_DIO : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: For SPI0 SRAM DIO mode enable . SRAM DIO enable command + * will be send when the bit is set. The bit will be cleared once the + * operation done. + */ + +#define SPI_SRAM_DIO (BIT(0)) +#define SPI_SRAM_DIO_M (BIT(0)) +#define SPI_SRAM_DIO_V 0x1 +#define SPI_SRAM_DIO_S 0 + +#define SPI_SRAM_DRD_CMD_OFFSET (0x5C) +#define SPI_SRAM_DRD_CMD_REG(i) (REG_SPI_BASE(i) + SPI_SRAM_DRD_CMD_OFFSET) + +/* SPI_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ + +/* Description: For SPI0 When cache mode is enable it is the length in bits + * of command phase for SRAM. The register value shall be (bit_num-1). + */ + +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF +#define SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 + +/* SPI_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ + +/* Description: For SPI0 When cache mode is enable it is the read command + * value of command phase for SRAM. + */ + +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S)) +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF +#define SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 + +#define SPI_SRAM_DWR_CMD_OFFSET (0x60) +#define SPI_SRAM_DWR_CMD_REG(i) (REG_SPI_BASE(i) + SPI_SRAM_DWR_CMD_OFFSET) + +/* SPI_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ + +/* Description: For SPI0 When cache mode is enable it is the in bits of + * command phase for SRAM. The register value shall be (bit_num-1). + */ + +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF +#define SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 + +/* SPI_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ + +/* Description: For SPI0 When cache mode is enable it is the write command + * value of command phase for SRAM. + */ + +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S)) +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF +#define SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 + +#define SPI_SLV_RD_BIT_OFFSET (0x64) +#define SPI_SLV_RD_BIT_REG (i) (REG_SPI_BASE(i) + SPI_SLV_RD_BIT_OFFSET) + +/* SPI_SLV_RDATA_BIT : RW ;bitpos:[23:0] ;default: 24'b0 ; */ + +/* Description: In the slave mode it is the bit length of read data. + * The value is the length - 1. + */ + +#define SPI_SLV_RDATA_BIT 0x00FFFFFF +#define SPI_SLV_RDATA_BIT_M ((SPI_SLV_RDATA_BIT_V)<<(SPI_SLV_RDATA_BIT_S)) +#define SPI_SLV_RDATA_BIT_V 0xFFFFFF +#define SPI_SLV_RDATA_BIT_S 0 + +#define SPI_W0_OFFSET (0x80) +#define SPI_W0_REG(i) (REG_SPI_BASE(i) + SPI_W0_OFFSET) + +/* SPI_BUF0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF0 0xFFFFFFFF +#define SPI_BUF0_M ((SPI_BUF0_V)<<(SPI_BUF0_S)) +#define SPI_BUF0_V 0xFFFFFFFF +#define SPI_BUF0_S 0 + +#define SPI_W1_OFFSET (0x84) +#define SPI_W1_REG (i) (REG_SPI_BASE(i) + SPI_W1_OFFSET) + +/* SPI_BUF1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF1 0xFFFFFFFF +#define SPI_BUF1_M ((SPI_BUF1_V)<<(SPI_BUF1_S)) +#define SPI_BUF1_V 0xFFFFFFFF +#define SPI_BUF1_S 0 + +#define SPI_W2_OFFSET (0x88) +#define SPI_W2_REG (i) (REG_SPI_BASE(i) + SPI_W2_OFFSET) + +/* SPI_BUF2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF2 0xFFFFFFFF +#define SPI_BUF2_M ((SPI_BUF2_V)<<(SPI_BUF2_S)) +#define SPI_BUF2_V 0xFFFFFFFF +#define SPI_BUF2_S 0 + +#define SPI_W3_OFFSET (0x8C) +#define SPI_W3_REG (i) (REG_SPI_BASE(i) + SPI_W3_OFFSET) + +/* SPI_BUF3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF3 0xFFFFFFFF +#define SPI_BUF3_M ((SPI_BUF3_V)<<(SPI_BUF3_S)) +#define SPI_BUF3_V 0xFFFFFFFF +#define SPI_BUF3_S 0 + +#define SPI_W4_OFFSET (0x90) +#define SPI_W4_REG (i) (REG_SPI_BASE(i) + SPI_W4_OFFSET) + +/* SPI_BUF4 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF4 0xFFFFFFFF +#define SPI_BUF4_M ((SPI_BUF4_V)<<(SPI_BUF4_S)) +#define SPI_BUF4_V 0xFFFFFFFF +#define SPI_BUF4_S 0 + +#define SPI_W5_OFFSET (0x94) +#define SPI_W5_REG (i) (REG_SPI_BASE(i) + SPI_W5_OFFSET) + +/* SPI_BUF5 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF5 0xFFFFFFFF +#define SPI_BUF5_M ((SPI_BUF5_V)<<(SPI_BUF5_S)) +#define SPI_BUF5_V 0xFFFFFFFF +#define SPI_BUF5_S 0 + +#define SPI_W6_OFFSET (0x98) +#define SPI_W6_REG (i) (REG_SPI_BASE(i) + SPI_W6_OFFSET) + +/* SPI_BUF6 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF6 0xFFFFFFFF +#define SPI_BUF6_M ((SPI_BUF6_V)<<(SPI_BUF6_S)) +#define SPI_BUF6_V 0xFFFFFFFF +#define SPI_BUF6_S 0 + +#define SPI_W7_OFFSET (0x9C) +#define SPI_W7_REG (i) (REG_SPI_BASE(i) + SPI_W7_OFFSET) + +/* SPI_BUF7 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF7 0xFFFFFFFF +#define SPI_BUF7_M ((SPI_BUF7_V)<<(SPI_BUF7_S)) +#define SPI_BUF7_V 0xFFFFFFFF +#define SPI_BUF7_S 0 + +#define SPI_W8_OFFSET (0xA0) +#define SPI_W8_REG (i) (REG_SPI_BASE(i) + SPI_W8_OFFSET) + +/* SPI_BUF8 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF8 0xFFFFFFFF +#define SPI_BUF8_M ((SPI_BUF8_V)<<(SPI_BUF8_S)) +#define SPI_BUF8_V 0xFFFFFFFF +#define SPI_BUF8_S 0 + +#define SPI_W9_OFFSET (0xA4) +#define SPI_W9_REG (i) (REG_SPI_BASE(i) + SPI_W9_OFFSET) + +/* SPI_BUF9 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF9 0xFFFFFFFF +#define SPI_BUF9_M ((SPI_BUF9_V)<<(SPI_BUF9_S)) +#define SPI_BUF9_V 0xFFFFFFFF +#define SPI_BUF9_S 0 + +#define SPI_W10_OFFSET (0xA8) +#define SPI_W10_REG (i) (REG_SPI_BASE(i) + SPI_W10_OFFSET) + +/* SPI_BUF10 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF10 0xFFFFFFFF +#define SPI_BUF10_M ((SPI_BUF10_V)<<(SPI_BUF10_S)) +#define SPI_BUF10_V 0xFFFFFFFF +#define SPI_BUF10_S 0 + +#define SPI_W11_OFFSET (0xAC) +#define SPI_W11_REG (i) (REG_SPI_BASE(i) + SPI_W11_OFFSET) + +/* SPI_BUF11 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF11 0xFFFFFFFF +#define SPI_BUF11_M ((SPI_BUF11_V)<<(SPI_BUF11_S)) +#define SPI_BUF11_V 0xFFFFFFFF +#define SPI_BUF11_S 0 + +#define SPI_W12_OFFSET (0xB0) +#define SPI_W12_REG(i) (REG_SPI_BASE(i) + SPI_W12_OFFSET) + +/* SPI_BUF12 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF12 0xFFFFFFFF +#define SPI_BUF12_M ((SPI_BUF12_V)<<(SPI_BUF12_S)) +#define SPI_BUF12_V 0xFFFFFFFF +#define SPI_BUF12_S 0 + +#define SPI_W13_OFFSET (0xB4) +#define SPI_W13_REG(i) (REG_SPI_BASE(i) + SPI_W13_OFFSET) + +/* SPI_BUF13 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF13 0xFFFFFFFF +#define SPI_BUF13_M ((SPI_BUF13_V)<<(SPI_BUF13_S)) +#define SPI_BUF13_V 0xFFFFFFFF +#define SPI_BUF13_S 0 + +#define SPI_W14_OFFSET (0xB8) +#define SPI_W14_REG(i) (REG_SPI_BASE(i) + SPI_W14_OFFSET) + +/* SPI_BUF14 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF14 0xFFFFFFFF +#define SPI_BUF14_M ((SPI_BUF14_V)<<(SPI_BUF14_S)) +#define SPI_BUF14_V 0xFFFFFFFF +#define SPI_BUF14_S 0 + +#define SPI_W15_OFFSET (0xBC) +#define SPI_W15_REG(i) (REG_SPI_BASE(i) + SPI_W15_OFFSET) + +/* SPI_BUF15 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: data buffer */ + +#define SPI_BUF15 0xFFFFFFFF +#define SPI_BUF15_M ((SPI_BUF15_V)<<(SPI_BUF15_S)) +#define SPI_BUF15_V 0xFFFFFFFF +#define SPI_BUF15_S 0 + +#define SPI_TX_CRC_OFFSET (0xC0) +#define SPI_TX_CRC_REG (i) (REG_SPI_BASE(i) + SPI_TX_CRC_OFFSET) + +/* SPI_TX_CRC_DATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: For SPI1 the value of crc32 for 256 bits data. */ + +#define SPI_TX_CRC_DATA 0xFFFFFFFF +#define SPI_TX_CRC_DATA_M ((SPI_TX_CRC_DATA_V)<<(SPI_TX_CRC_DATA_S)) +#define SPI_TX_CRC_DATA_V 0xFFFFFFFF +#define SPI_TX_CRC_DATA_S 0 + +#define SPI_EXT0_OFFSET (0xF0) +#define SPI_EXT0_REG (i) (REG_SPI_BASE(i) + SPI_EXT0_OFFSET) + +/* SPI_T_PP_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */ + +/* Description: page program delay enable. */ + +#define SPI_T_PP_ENA (BIT(31)) +#define SPI_T_PP_ENA_M (BIT(31)) +#define SPI_T_PP_ENA_V 0x1 +#define SPI_T_PP_ENA_S 31 + +/* SPI_T_PP_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd10 ; */ + +/* Description: page program delay time shift. */ + +#define SPI_T_PP_SHIFT 0x0000000F +#define SPI_T_PP_SHIFT_M ((SPI_T_PP_SHIFT_V)<<(SPI_T_PP_SHIFT_S)) +#define SPI_T_PP_SHIFT_V 0xF +#define SPI_T_PP_SHIFT_S 16 + +/* SPI_T_PP_TIME : R/W ;bitpos:[11:0] ;default: 12'd80 ; */ + +/* Description: page program delay time by system clock. */ + +#define SPI_T_PP_TIME 0x00000FFF +#define SPI_T_PP_TIME_M ((SPI_T_PP_TIME_V)<<(SPI_T_PP_TIME_S)) +#define SPI_T_PP_TIME_V 0xFFF +#define SPI_T_PP_TIME_S 0 + +#define SPI_EXT1_OFFSET (0xF4) +#define SPI_EXT1_REG (i) (REG_SPI_BASE(i) + SPI_EXT1_OFFSET) + +/* SPI_T_ERASE_ENA : R/W ;bitpos:[31] ;default: 1'b1 ; */ + +/* Description: erase flash delay enable. */ + +#define SPI_T_ERASE_ENA (BIT(31)) +#define SPI_T_ERASE_ENA_M (BIT(31)) +#define SPI_T_ERASE_ENA_V 0x1 +#define SPI_T_ERASE_ENA_S 31 + +/* SPI_T_ERASE_SHIFT : R/W ;bitpos:[19:16] ;default: 4'd15 ; */ + +/* Description: erase flash delay time shift. */ + +#define SPI_T_ERASE_SHIFT 0x0000000F +#define SPI_T_ERASE_SHIFT_M ((SPI_T_ERASE_SHIFT_V)<<(SPI_T_ERASE_SHIFT_S)) +#define SPI_T_ERASE_SHIFT_V 0xF +#define SPI_T_ERASE_SHIFT_S 16 + +/* SPI_T_ERASE_TIME : R/W ;bitpos:[11:0] ;default: 12'd0 ; */ + +/* Description: erase flash delay time by system clock. */ + +#define SPI_T_ERASE_TIME 0x00000FFF +#define SPI_T_ERASE_TIME_M ((SPI_T_ERASE_TIME_V)<<(SPI_T_ERASE_TIME_S)) +#define SPI_T_ERASE_TIME_V 0xFFF +#define SPI_T_ERASE_TIME_S 0 + +#define SPI_EXT2_OFFSET (0xF8) +#define SPI_EXT2_REG (i) (REG_SPI_BASE(i) + SPI_EXT2_OFFSET) + +/* SPI_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ + +/* Description: The status of spi state machine. */ + +#define SPI_ST 0x00000007 +#define SPI_ST_M ((SPI_ST_V)<<(SPI_ST_S)) +#define SPI_ST_V 0x7 +#define SPI_ST_S 0 + +#define SPI_EXT3_OFFSET (0xFC) +#define SPI_EXT3_REG (i) (REG_SPI_BASE(i) + SPI_EXT3_OFFSET) + +/* SPI_INT_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ + +/* Description: This register is for two SPI masters to share the same cs + * clock and data signals. The bits of one SPI are set if the other SPI is + * busy the SPI will be hold. + * 1(3): hold at "idle" phase + * 2: hold at "prepare" phase. + */ + +#define SPI_INT_HOLD_ENA 0x00000003 +#define SPI_INT_HOLD_ENA_M ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S)) +#define SPI_INT_HOLD_ENA_V 0x3 +#define SPI_INT_HOLD_ENA_S 0 + +#define SPI_DMA_CONF_OFFSET (0x100) +#define SPI_DMA_CONF_REG (i) (REG_SPI_BASE(i) + SPI_DMA_CONF_OFFSET) + +/* SPI_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */ + +/* Description: spi dma continue tx/rx data. */ + +#define SPI_DMA_CONTINUE (BIT(16)) +#define SPI_DMA_CONTINUE_M (BIT(16)) +#define SPI_DMA_CONTINUE_V 0x1 +#define SPI_DMA_CONTINUE_S 16 + +/* SPI_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */ + +/* Description: spi dma write data stop when in continue tx/rx mode. */ + +#define SPI_DMA_TX_STOP (BIT(15)) +#define SPI_DMA_TX_STOP_M (BIT(15)) +#define SPI_DMA_TX_STOP_V 0x1 +#define SPI_DMA_TX_STOP_S 15 + +/* SPI_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +/* Description: spi dma read data stop when in continue tx/rx mode. */ + +#define SPI_DMA_RX_STOP (BIT(14)) +#define SPI_DMA_RX_STOP_M (BIT(14)) +#define SPI_DMA_RX_STOP_V 0x1 +#define SPI_DMA_RX_STOP_S 14 + +/* SPI_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +/* Description: spi dma read data from memory in burst mode. */ + +#define SPI_OUT_DATA_BURST_EN (BIT(12)) +#define SPI_OUT_DATA_BURST_EN_M (BIT(12)) +#define SPI_OUT_DATA_BURST_EN_V 0x1 +#define SPI_OUT_DATA_BURST_EN_S 12 + +/* SPI_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +/* Description: read descriptor use burst mode when write data to memory. */ + +#define SPI_INDSCR_BURST_EN (BIT(11)) +#define SPI_INDSCR_BURST_EN_M (BIT(11)) +#define SPI_INDSCR_BURST_EN_V 0x1 +#define SPI_INDSCR_BURST_EN_S 11 + +/* SPI_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +/* Description: read descriptor use burst mode when read data for memory. */ + +#define SPI_OUTDSCR_BURST_EN (BIT(10)) +#define SPI_OUTDSCR_BURST_EN_M (BIT(10)) +#define SPI_OUTDSCR_BURST_EN_V 0x1 +#define SPI_OUTDSCR_BURST_EN_S 10 + +/* SPI_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */ + +/* Description: out eof flag generation mode. + * 1: when dma pop all data from fifo + * 0: when ahb push all data to fifo. + */ + +#define SPI_OUT_EOF_MODE (BIT(9)) +#define SPI_OUT_EOF_MODE_M (BIT(9)) +#define SPI_OUT_EOF_MODE_V 0x1 +#define SPI_OUT_EOF_MODE_S 9 + +/* SPI_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: when the link is empty jump to next automatically. */ + +#define SPI_OUT_AUTO_WRBACK (BIT(8)) +#define SPI_OUT_AUTO_WRBACK_M (BIT(8)) +#define SPI_OUT_AUTO_WRBACK_V 0x1 +#define SPI_OUT_AUTO_WRBACK_S 8 + +/* SPI_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: Set bit to test out link. */ + +#define SPI_OUT_LOOP_TEST (BIT(7)) +#define SPI_OUT_LOOP_TEST_M (BIT(7)) +#define SPI_OUT_LOOP_TEST_V 0x1 +#define SPI_OUT_LOOP_TEST_S 7 + +/* SPI_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: Set bit to test in link. */ + +#define SPI_IN_LOOP_TEST (BIT(6)) +#define SPI_IN_LOOP_TEST_M (BIT(6)) +#define SPI_IN_LOOP_TEST_V 0x1 +#define SPI_IN_LOOP_TEST_S 6 + +/* SPI_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: reset spi dma ahb master. */ + +#define SPI_AHBM_RST (BIT(5)) +#define SPI_AHBM_RST_M (BIT(5)) +#define SPI_AHBM_RST_V 0x1 +#define SPI_AHBM_RST_S 5 + +/* SPI_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: reset spi dma ahb master fifo pointer. */ + +#define SPI_AHBM_FIFO_RST (BIT(4)) +#define SPI_AHBM_FIFO_RST_M (BIT(4)) +#define SPI_AHBM_FIFO_RST_V 0x1 +#define SPI_AHBM_FIFO_RST_S 4 + +/* SPI_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: The bit is used to reset out dma fsm and out data fifo + * pointer. + */ + +#define SPI_OUT_RST (BIT(3)) +#define SPI_OUT_RST_M (BIT(3)) +#define SPI_OUT_RST_V 0x1 +#define SPI_OUT_RST_S 3 + +/* SPI_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: The bit is used to reset in dma fsm and in data fifo + * pointer. + */ + +#define SPI_IN_RST (BIT(2)) +#define SPI_IN_RST_M (BIT(2)) +#define SPI_IN_RST_V 0x1 +#define SPI_IN_RST_S 2 + +#define SPI_DMA_OUT_LINK_OFFSET (0x104) +#define SPI_DMA_OUT_LINK_REG (i) (REG_SPI_BASE(i) + SPI_DMA_OUT_LINK_OFFSET) + +/* SPI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: Set the bit to mount on new outlink descriptors. */ + +#define SPI_OUTLINK_RESTART (BIT(30)) +#define SPI_OUTLINK_RESTART_M (BIT(30)) +#define SPI_OUTLINK_RESTART_V 0x1 +#define SPI_OUTLINK_RESTART_S 30 + +/* SPI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: Set the bit to start to use outlink descriptor. */ + +#define SPI_OUTLINK_START (BIT(29)) +#define SPI_OUTLINK_START_M (BIT(29)) +#define SPI_OUTLINK_START_V 0x1 +#define SPI_OUTLINK_START_S 29 + +/* SPI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +/* Description: Set the bit to stop to use outlink descriptor. */ + +#define SPI_OUTLINK_STOP (BIT(28)) +#define SPI_OUTLINK_STOP_M (BIT(28)) +#define SPI_OUTLINK_STOP_V 0x1 +#define SPI_OUTLINK_STOP_S 28 + +/* SPI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ + +/* Description: The address of the first outlink descriptor. */ + +#define SPI_OUTLINK_ADDR 0x000FFFFF +#define SPI_OUTLINK_ADDR_M ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S)) +#define SPI_OUTLINK_ADDR_V 0xFFFFF +#define SPI_OUTLINK_ADDR_S 0 + +#define SPI_DMA_IN_LINK_OFFSET (0x108) +#define SPI_DMA_IN_LINK_REG (i) (REG_SPI_BASE(i) + SPI_DMA_IN_LINK_OFFSET) + +/* SPI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ + +/* Description: Set the bit to mount on new inlink descriptors. */ + +#define SPI_INLINK_RESTART (BIT(30)) +#define SPI_INLINK_RESTART_M (BIT(30)) +#define SPI_INLINK_RESTART_V 0x1 +#define SPI_INLINK_RESTART_S 30 + +/* SPI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ + +/* Description: Set the bit to start to use inlink descriptor. */ + +#define SPI_INLINK_START (BIT(29)) +#define SPI_INLINK_START_M (BIT(29)) +#define SPI_INLINK_START_V 0x1 +#define SPI_INLINK_START_S 29 + +/* SPI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ + +/* Description: Set the bit to stop to use inlink descriptor. */ + +#define SPI_INLINK_STOP (BIT(28)) +#define SPI_INLINK_STOP_M (BIT(28)) +#define SPI_INLINK_STOP_V 0x1 +#define SPI_INLINK_STOP_S 28 + +/* SPI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */ + +/* Description: when the bit is set inlink descriptor returns to the next + * descriptor while a packet is wrong + */ + +#define SPI_INLINK_AUTO_RET (BIT(20)) +#define SPI_INLINK_AUTO_RET_M (BIT(20)) +#define SPI_INLINK_AUTO_RET_V 0x1 +#define SPI_INLINK_AUTO_RET_S 20 + +/* SPI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ + +/* Description: The address of the first inlink descriptor. */ + +#define SPI_INLINK_ADDR 0x000FFFFF +#define SPI_INLINK_ADDR_M ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S)) +#define SPI_INLINK_ADDR_V 0xFFFFF +#define SPI_INLINK_ADDR_S 0 + +#define SPI_DMA_STATUS_OFFSET (0x10C) +#define SPI_DMA_STATUS_REG (i) (REG_SPI_BASE(i) + SPI_DMA_STATUS_OFFSET) + +/* SPI_DMA_TX_EN : RO ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: spi dma write data status bit. */ + +#define SPI_DMA_TX_EN (BIT(1)) +#define SPI_DMA_TX_EN_M (BIT(1)) +#define SPI_DMA_TX_EN_V 0x1 +#define SPI_DMA_TX_EN_S 1 + +/* SPI_DMA_RX_EN : RO ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: spi dma read data status bit. */ + +#define SPI_DMA_RX_EN (BIT(0)) +#define SPI_DMA_RX_EN_M (BIT(0)) +#define SPI_DMA_RX_EN_V 0x1 +#define SPI_DMA_RX_EN_S 0 + +#define SPI_DMA_INT_ENA_OFFSET (0x110) +#define SPI_DMA_INT_ENA_REG (i) (REG_SPI_BASE(i) + SPI_DMA_INT_ENA_OFFSET) + +/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: The enable bit for sending all the packets to host done. */ + +#define SPI_OUT_TOTAL_EOF_INT_ENA (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ENA_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ENA_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_ENA_S 8 + +/* SPI_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: The enable bit for sending a packet to host done. */ + +#define SPI_OUT_EOF_INT_ENA (BIT(7)) +#define SPI_OUT_EOF_INT_ENA_M (BIT(7)) +#define SPI_OUT_EOF_INT_ENA_V 0x1 +#define SPI_OUT_EOF_INT_ENA_S 7 + +/* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: The enable bit for completing usage of a outlink + * descriptor. + */ + +#define SPI_OUT_DONE_INT_ENA (BIT(6)) +#define SPI_OUT_DONE_INT_ENA_M (BIT(6)) +#define SPI_OUT_DONE_INT_ENA_V 0x1 +#define SPI_OUT_DONE_INT_ENA_S 6 + +/* SPI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: The enable bit for completing receiving all the packets from + * host. + */ + +#define SPI_IN_SUC_EOF_INT_ENA (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ENA_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ENA_V 0x1 +#define SPI_IN_SUC_EOF_INT_ENA_S 5 + +/* SPI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: The enable bit for receiving error. */ + +#define SPI_IN_ERR_EOF_INT_ENA (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ENA_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ENA_V 0x1 +#define SPI_IN_ERR_EOF_INT_ENA_S 4 + +/* SPI_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: The enable bit for completing usage of a inlink descriptor. */ + +#define SPI_IN_DONE_INT_ENA (BIT(3)) +#define SPI_IN_DONE_INT_ENA_M (BIT(3)) +#define SPI_IN_DONE_INT_ENA_V 0x1 +#define SPI_IN_DONE_INT_ENA_S 3 + +/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: The enable bit for inlink descriptor error. */ + +#define SPI_INLINK_DSCR_ERROR_INT_ENA (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ENA_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ENA_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_ENA_S 2 + +/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: The enable bit for outlink descriptor error. */ + +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S 1 + +/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: The enable bit for lack of enough inlink descriptors. */ + +#define SPI_INLINK_DSCR_EMPTY_INT_ENA (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S 0 + +#define SPI_DMA_INT_RAW_OFFSET (0x114) +#define SPI_DMA_INT_RAW_REG (i) (REG_SPI_BASE(i) + SPI_DMA_INT_RAW_OFFSET) + +/* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: The raw bit for sending all the packets to host done. */ + +#define SPI_OUT_TOTAL_EOF_INT_RAW (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_RAW_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_RAW_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_RAW_S 8 + +/* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: The raw bit for sending a packet to host done. */ + +#define SPI_OUT_EOF_INT_RAW (BIT(7)) +#define SPI_OUT_EOF_INT_RAW_M (BIT(7)) +#define SPI_OUT_EOF_INT_RAW_V 0x1 +#define SPI_OUT_EOF_INT_RAW_S 7 + +/* SPI_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: The raw bit for completing usage of a outlink descriptor. */ +#define SPI_OUT_DONE_INT_RAW (BIT(6)) +#define SPI_OUT_DONE_INT_RAW_M (BIT(6)) +#define SPI_OUT_DONE_INT_RAW_V 0x1 +#define SPI_OUT_DONE_INT_RAW_S 6 + +/* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: The raw bit for completing receiving all the packets from + * host. + */ + +#define SPI_IN_SUC_EOF_INT_RAW (BIT(5)) +#define SPI_IN_SUC_EOF_INT_RAW_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_RAW_V 0x1 +#define SPI_IN_SUC_EOF_INT_RAW_S 5 + +/* SPI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: The raw bit for receiving error. */ + +#define SPI_IN_ERR_EOF_INT_RAW (BIT(4)) +#define SPI_IN_ERR_EOF_INT_RAW_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_RAW_V 0x1 +#define SPI_IN_ERR_EOF_INT_RAW_S 4 + +/* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: The raw bit for completing usage of a inlink descriptor. */ + +#define SPI_IN_DONE_INT_RAW (BIT(3)) +#define SPI_IN_DONE_INT_RAW_M (BIT(3)) +#define SPI_IN_DONE_INT_RAW_V 0x1 +#define SPI_IN_DONE_INT_RAW_S 3 + +/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: The raw bit for inlink descriptor error. */ + +#define SPI_INLINK_DSCR_ERROR_INT_RAW (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_RAW_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_RAW_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_RAW_S 2 + +/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: The raw bit for outlink descriptor error. */ + +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S 1 + +/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: The raw bit for lack of enough inlink descriptors. */ + +#define SPI_INLINK_DSCR_EMPTY_INT_RAW (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S 0 + +#define SPI_DMA_INT_ST_OFFSET (0x118) +#define SPI_DMA_INT_ST_REG (i) (REG_SPI_BASE(i) + SPI_DMA_INT_ST_OFFSET) + +/* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: The status bit for sending all the packets to host done. */ + +#define SPI_OUT_TOTAL_EOF_INT_ST (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ST_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_ST_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_ST_S 8 + +/* SPI_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: The status bit for sending a packet to host done. */ + +#define SPI_OUT_EOF_INT_ST (BIT(7)) +#define SPI_OUT_EOF_INT_ST_M (BIT(7)) +#define SPI_OUT_EOF_INT_ST_V 0x1 +#define SPI_OUT_EOF_INT_ST_S 7 + +/* SPI_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: The status bit for completing usage of a outlink descriptor */ + +#define SPI_OUT_DONE_INT_ST (BIT(6)) +#define SPI_OUT_DONE_INT_ST_M (BIT(6)) +#define SPI_OUT_DONE_INT_ST_V 0x1 +#define SPI_OUT_DONE_INT_ST_S 6 + +/* SPI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: The status bit for completing receiving all the packets from + * host. + */ + +#define SPI_IN_SUC_EOF_INT_ST (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ST_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_ST_V 0x1 +#define SPI_IN_SUC_EOF_INT_ST_S 5 + +/* SPI_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: The status bit for receiving error. */ + +#define SPI_IN_ERR_EOF_INT_ST (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ST_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_ST_V 0x1 +#define SPI_IN_ERR_EOF_INT_ST_S 4 + +/* SPI_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: The status bit for completing usage of a inlink descriptor. */ + +#define SPI_IN_DONE_INT_ST (BIT(3)) +#define SPI_IN_DONE_INT_ST_M (BIT(3)) +#define SPI_IN_DONE_INT_ST_V 0x1 +#define SPI_IN_DONE_INT_ST_S 3 + +/* SPI_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: The status bit for inlink descriptor error. */ + +#define SPI_INLINK_DSCR_ERROR_INT_ST (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ST_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_ST_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_ST_S 2 + +/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: The status bit for outlink descriptor error. */ + +#define SPI_OUTLINK_DSCR_ERROR_INT_ST (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S 1 + +/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: The status bit for lack of enough inlink descriptors. */ + +#define SPI_INLINK_DSCR_EMPTY_INT_ST (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ST_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_ST_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_ST_S 0 + +#define SPI_DMA_INT_CLR_OFFSET (0x11C) +#define SPI_DMA_INT_CLR_REG (i) (REG_SPI_BASE(i) + SPI_DMA_INT_CLR_OFFSET) + +/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +/* Description: The clear bit for sending all the packets to host done. */ + +#define SPI_OUT_TOTAL_EOF_INT_CLR (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_CLR_M (BIT(8)) +#define SPI_OUT_TOTAL_EOF_INT_CLR_V 0x1 +#define SPI_OUT_TOTAL_EOF_INT_CLR_S 8 + +/* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +/* Description: The clear bit for sending a packet to host done. */ + +#define SPI_OUT_EOF_INT_CLR (BIT(7)) +#define SPI_OUT_EOF_INT_CLR_M (BIT(7)) +#define SPI_OUT_EOF_INT_CLR_V 0x1 +#define SPI_OUT_EOF_INT_CLR_S 7 + +/* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +/* Description: The clear bit for completing usage of a outlink descriptor. */ + +#define SPI_OUT_DONE_INT_CLR (BIT(6)) +#define SPI_OUT_DONE_INT_CLR_M (BIT(6)) +#define SPI_OUT_DONE_INT_CLR_V 0x1 +#define SPI_OUT_DONE_INT_CLR_S 6 + +/* SPI_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +/* Description: The clear bit for completing receiving all the packets from + * host. + */ + +#define SPI_IN_SUC_EOF_INT_CLR (BIT(5)) +#define SPI_IN_SUC_EOF_INT_CLR_M (BIT(5)) +#define SPI_IN_SUC_EOF_INT_CLR_V 0x1 +#define SPI_IN_SUC_EOF_INT_CLR_S 5 + +/* SPI_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +/* Description: The clear bit for receiving error. */ + +#define SPI_IN_ERR_EOF_INT_CLR (BIT(4)) +#define SPI_IN_ERR_EOF_INT_CLR_M (BIT(4)) +#define SPI_IN_ERR_EOF_INT_CLR_V 0x1 +#define SPI_IN_ERR_EOF_INT_CLR_S 4 + +/* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +/* Description: The clear bit for completing usage of a inlink descriptor. */ + +#define SPI_IN_DONE_INT_CLR (BIT(3)) +#define SPI_IN_DONE_INT_CLR_M (BIT(3)) +#define SPI_IN_DONE_INT_CLR_V 0x1 +#define SPI_IN_DONE_INT_CLR_S 3 + +/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +/* Description: The clear bit for inlink descriptor error. */ + +#define SPI_INLINK_DSCR_ERROR_INT_CLR (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_CLR_M (BIT(2)) +#define SPI_INLINK_DSCR_ERROR_INT_CLR_V 0x1 +#define SPI_INLINK_DSCR_ERROR_INT_CLR_S 2 + +/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +/* Description: The clear bit for outlink descriptor error. */ + +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M (BIT(1)) +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V 0x1 +#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S 1 + +/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +/* Description: The clear bit for lack of enough inlink descriptors. */ + +#define SPI_INLINK_DSCR_EMPTY_INT_CLR (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M (BIT(0)) +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V 0x1 +#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S 0 + +#define SPI_IN_ERR_EOF_DES_ADDR_OFFSET (0x120) +#define SPI_IN_ERR_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + SPI_IN_ERR_EOF_DES_ADDR_OFFSET) + +/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: The inlink descriptor address when spi dma produce receiving + * error. + */ + +#define SPI_DMA_IN_ERR_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S)) +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S 0 + +#define SPI_IN_SUC_EOF_DES_ADDR_OFFSET (0x124) +#define SPI_IN_SUC_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + SPI_IN_SUC_EOF_DES_ADDR_OFFSET) + +/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: The last inlink descriptor address when spi dma produce + * from_suc_eof. + */ + +#define SPI_DMA_IN_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S)) +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S 0 + +#define SPI_INLINK_DSCR_OFFSET (0x128) +#define SPI_INLINK_DSCR_REG(i) (REG_SPI_BASE(i) + SPI_INLINK_DSCR_OFFSET) + +/* SPI_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: The content of current in descriptor pointer. */ + +#define SPI_DMA_INLINK_DSCR 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_M ((SPI_DMA_INLINK_DSCR_V)<<(SPI_DMA_INLINK_DSCR_S)) +#define SPI_DMA_INLINK_DSCR_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_S 0 + +#define SPI_INLINK_DSCR_BF0_OFFSET (0x12C) +#define SPI_INLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + SPI_INLINK_DSCR_BF0_OFFSET) + +/* SPI_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: The content of next in descriptor pointer. */ + +#define SPI_DMA_INLINK_DSCR_BF0 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF0_M ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S)) +#define SPI_DMA_INLINK_DSCR_BF0_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF0_S 0 + +#define SPI_INLINK_DSCR_BF1_OFFSET (0x130) +#define SPI_INLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + SPI_INLINK_DSCR_BF1_OFFSET) + +/* SPI_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: The content of current in descriptor data buffer pointer. */ + +#define SPI_DMA_INLINK_DSCR_BF1 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF1_M ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S)) +#define SPI_DMA_INLINK_DSCR_BF1_V 0xFFFFFFFF +#define SPI_DMA_INLINK_DSCR_BF1_S 0 + +#define SPI_OUT_EOF_BFR_DES_ADDR_OFFSET (0x134) +#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i) (REG_SPI_BASE(i) + SPI_OUT_EOF_BFR_DES_ADDR_OFFSETs) + +/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: The address of buffer relative to the outlink descriptor + * that produce eof. + */ + +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M ((SPI_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_BFR_DES_ADDR_S)) +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S 0 + +#define SPI_OUT_EOF_DES_ADDR_OFFSET (0x138) +#define SPI_OUT_EOF_DES_ADDR_REG(i) (REG_SPI_BASE(i) + SPI_OUT_EOF_DES_ADDR_OFFSET) + +/* SPI_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: The last outlink descriptor address when spi dma produce + * to_eof. + */ + +#define SPI_DMA_OUT_EOF_DES_ADDR 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_DES_ADDR_M ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S)) +#define SPI_DMA_OUT_EOF_DES_ADDR_V 0xFFFFFFFF +#define SPI_DMA_OUT_EOF_DES_ADDR_S 0 + +#define SPI_OUTLINK_DSCR_OFFSET (0x13C) +#define SPI_OUTLINK_DSCR_REG(i) (REG_SPI_BASE(i) + SPI_OUTLINK_DSCR_OFFSET) + +/* SPI_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: The content of current out descriptor pointer. */ + +#define SPI_DMA_OUTLINK_DSCR 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_M ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S)) +#define SPI_DMA_OUTLINK_DSCR_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_S 0 + +#define SPI_OUTLINK_DSCR_BF0_OFFSET (0x140) +#define SPI_OUTLINK_DSCR_BF0_REG(i) (REG_SPI_BASE(i) + SPI_OUTLINK_DSCR_BF0_OFFSET) + +/* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: The content of next out descriptor pointer. */ + +#define SPI_DMA_OUTLINK_DSCR_BF0 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF0_M ((SPI_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_DMA_OUTLINK_DSCR_BF0_S)) +#define SPI_DMA_OUTLINK_DSCR_BF0_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF0_S 0 + +#define SPI_OUTLINK_DSCR_BF1_OFFSET (0x144) +#define SPI_OUTLINK_DSCR_BF1_REG(i) (REG_SPI_BASE(i) + SPI_OUTLINK_DSCR_BF1_OFFSET) + +/* SPI_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: The content of current out descriptor data buffer pointer. */ + +#define SPI_DMA_OUTLINK_DSCR_BF1 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF1_M ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S)) +#define SPI_DMA_OUTLINK_DSCR_BF1_V 0xFFFFFFFF +#define SPI_DMA_OUTLINK_DSCR_BF1_S 0 + +#define SPI_DMA_RSTATUS_OFFSET (0x148) +#define SPI_DMA_RSTATUS_REG(i) (REG_SPI_BASE(i) + SPI_DMA_RSTATUS_OFFSET) + +/* SPI_DMA_OUT_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: spi dma read data from memory status. */ + +#define SPI_DMA_OUT_STATUS 0xFFFFFFFF +#define SPI_DMA_OUT_STATUS_M ((SPI_DMA_OUT_STATUS_V)<<(SPI_DMA_OUT_STATUS_S)) +#define SPI_DMA_OUT_STATUS_V 0xFFFFFFFF +#define SPI_DMA_OUT_STATUS_S 0 + +#define SPI_DMA_TSTATUS_OFFSET (0x14C) +#define SPI_DMA_TSTATUS_REG (i) (REG_SPI_BASE(i) + SPI_DMA_TSTATUS_OFFSET) + +/* SPI_DMA_IN_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */ + +/* Description: spi dma write data to memory status. */ + +#define SPI_DMA_IN_STATUS 0xFFFFFFFF +#define SPI_DMA_IN_STATUS_M ((SPI_DMA_IN_STATUS_V)<<(SPI_DMA_IN_STATUS_S)) +#define SPI_DMA_IN_STATUS_V 0xFFFFFFFF +#define SPI_DMA_IN_STATUS_S 0 + +#define SPI_DATE_OFFSET (0x3FC) +#define SPI_DATE_REG (i) (REG_SPI_BASE(i) + SPI_DATE_OFFSET) + +/* SPI_DATE : RO ;bitpos:[27:0] ;default: 32'h1604270 ; */ + +/* Description: SPI register version. */ + +#define SPI_DATE 0x0FFFFFFF +#define SPI_DATE_M ((SPI_DATE_V)<<(SPI_DATE_S)) +#define SPI_DATE_V 0xFFFFFFF +#define SPI_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SPI_H */