Finish code for basic STM3240 port
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4124 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
76bb54a502
commit
79b13e12e6
@ -170,6 +170,8 @@
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#define NVIC_IRQ232_235_PRIORITY_OFFSET 0x04e8 /* IRQ 232-235 priority register */
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#define NVIC_IRQ236_239_PRIORITY_OFFSET 0x04ec /* IRQ 236-239 priority register */
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/* System Control Block (SCB) */
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#define NVIC_CPUID_BASE_OFFSET 0x0d00 /* CPUID base register */
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#define NVIC_INTCTRL_OFFSET 0x0d04 /* Interrupt control state register */
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#define NVIC_VECTAB_OFFSET 0x0d08 /* Vector table offset register */
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@ -200,6 +202,7 @@
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#define NVIC_ISAR2_OFFSET 0x0d68 /* ISA feature register 2 */
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#define NVIC_ISAR3_OFFSET 0x0d6c /* ISA feature register 3 */
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#define NVIC_ISAR4_OFFSET 0x0d70 /* ISA feature register 4 */
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#define NVIC_CPACR_OFFSET 0x0d88 /* Coprocessor Access Control Register */
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#define NVIC_STIR_OFFSET 0x0f00 /* Software trigger interrupt register */
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#define NVIC_PID4_OFFSET 0x0fd0 /* Peripheral identification register (PID4) */
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#define NVIC_PID5_OFFSET 0x0fd4 /* Peripheral identification register (PID5) */
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@ -363,6 +366,7 @@
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#define NVIC_ISAR2 (ARMV7M_NVIC_BASE + NVIC_ISAR2_OFFSET)
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#define NVIC_ISAR3 (ARMV7M_NVIC_BASE + NVIC_ISAR3_OFFSET)
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#define NVIC_ISAR4 (ARMV7M_NVIC_BASE + NVIC_ISAR4_OFFSET)
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#define NVIC_CPACR (ARMV7M_NVIC_BASE + NVIC_CPACR_OFFSET)
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#define NVIC_STIR (ARMV7M_NVIC_BASE + NVIC_STIR_OFFSET)
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#define NVIC_PID4 (ARMV7M_NVIC_BASE + NVIC_PID4_OFFSET)
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#define NVIC_PID5 (ARMV7M_NVIC_BASE + NVIC_PID5_OFFSET)
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@ -36,7 +36,7 @@
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HEAD_ASRC = stm32_vectors.S
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CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
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CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
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CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c \
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up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
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up_initialize.c up_initialstate.c up_interruptcontext.c \
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up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
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@ -49,10 +49,11 @@ CMN_CSRCS += up_checkstack.c
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endif
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CHIP_ASRCS =
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CHIP_CSRCS = stm32_start.c stm32_rcc.c stm32_gpio.c stm32_exti.c stm32_flash.c \
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stm32_irq.c stm32_timerisr.c stm32_dma.c stm32_lowputc.c \
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stm32_serial.c stm32_spi.c stm32_usbdev.c stm32_sdio.c \
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stm32_tim.c stm32_i2c.c stm32_pwr.c stm32_idle.c stm32_waste.c
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CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c \
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stm32_gpio.c stm32_exti.c stm32_flash.c stm32_irq.c \
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stm32_timerisr.c stm32_dma.c stm32_lowputc.c stm32_serial.c \
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stm32_spi.c stm32_usbdev.c stm32_sdio.c stm32_tim.c stm32_i2c.c \
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stm32_pwr.c stm32_idle.c stm32_waste.c
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ifeq ($(CONFIG_STM32_RCCLOCK),y)
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CHIP_CSRCS += stm32_rcclock.c
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@ -512,10 +512,10 @@
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#define GPIO_USART1_CK (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8)
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#define GPIO_USART1_CTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11)
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#define GPIO_USART1_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12)
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#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN10)
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#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN7)
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#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN9)
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#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN6)
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#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
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#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
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#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
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#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
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#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN4)
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#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN7)
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@ -523,10 +523,10 @@
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#define GPIO_USART2_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN3)
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#define GPIO_USART2_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1)
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#define GPIO_USART2_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN4)
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#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN3)
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#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN6)
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#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN2)
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#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN5)
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#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
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#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6)
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#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
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#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN5)
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#define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN12)
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#define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN12)
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@ -535,20 +535,20 @@
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#define GPIO_USART3_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN11)
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#define GPIO_USART3_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14)
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#define GPIO_USART3_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN12)
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#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN11)
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#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN11)
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#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN9)
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#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN10)
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#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN10)
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#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN8)
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#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
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#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
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#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN9)
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#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
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#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
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#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN8)
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#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN1)
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#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN11)
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#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN0)
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#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN10)
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#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
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#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
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#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
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#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
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#define GPIO_UART5_RX (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN2)
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#define GPIO_UART5_TX (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN12)
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#define GPIO_UART5_RX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
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#define GPIO_UART5_TX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN12)
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#define GPIO_USART6_CK_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN8)
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#define GPIO_USART6_CK_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN7)
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@ -556,10 +556,10 @@
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#define GPIO_USART6_CTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN15)
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#define GPIO_USART6_RTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN12)
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#define GPIO_USART6_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN8)
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#define GPIO_USART6_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN7)
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#define GPIO_USART6_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN9)
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#define GPIO_USART6_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN6)
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#define GPIO_USART6_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN14)
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#define GPIO_USART6_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
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#define GPIO_USART6_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9)
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#define GPIO_USART6_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
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#define GPIO_USART6_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_PINMAP_H */
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161
arch/arm/src/stm32/stm32_allocateheap.c
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161
arch/arm/src/stm32/stm32_allocateheap.c
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@ -0,0 +1,161 @@
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/****************************************************************************
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* arch/arm/src/stm32/up_allocateheap.c
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "chip.h"
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#include "up_arch.h"
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#include "up_internal.h"
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/****************************************************************************
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* Private Definitions
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****************************************************************************/
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/* For the STM312F10xxx family, all SRAM is in a contiguous block starting
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* at g_heapbase and extending through CONFIG_DRAM_END (my apologies for
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* the bad naming).
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*/
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#if defined(CONFIG_STM32_STM32F10XX)
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# define SRAM1_END CONFIG_DRAM_END
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/* All members of the STM32F40xxx family have 192Kb in three banks:
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*
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* 1) 112Kb of SRAM beginning at address 0x2000:0000
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* 2) 16Kb of SRAM beginning at address 0x2001:c000
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* 3) 64Kb of TCM SRAM beginning at address 0x1000:0000
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*
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* As determined by ld.script, g_heapbase lies in the 112Kb memory
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* region and that extends to 0x2001:0000. But the first and second memory
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* regions are contiguous and treated as one in this logic that extends to
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* 0x2002:0000.
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*/
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#elif defined(CONFIG_STM32_STM32F40XX)
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# define SRAM1_END 0x20020000
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# define SRAM2_START 0x10000000
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# define SRAM2_END 0x10010000
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#else
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# error "Unsupported STM32 chip"
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_allocate_heap
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*
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* Description:
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* The heap may be statically allocated by
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* defining CONFIG_HEAP_BASE and CONFIG_HEAP_SIZE. If these
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* are not defined, then this function will be called to
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* dynamically set aside the heap region.
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*
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****************************************************************************/
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void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
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{
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up_ledon(LED_HEAPALLOCATE);
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*heap_start = (FAR void*)g_heapbase;
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*heap_size = SRAM1_END - g_heapbase;
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}
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/****************************************************************************
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* Name: up_addregion
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*
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* Description:
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* Memory may be added in non-contiguous chunks. Additional chunks are
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* added by calling this function.
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*
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****************************************************************************/
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#if CONFIG_MM_REGIONS > 1
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# if defined(CONFIG_STM32_STM32F40XX)
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# if defined(CONFIG_HEAP2_BASE) && defined(CONFIG_HEAP2_END)
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# if CONFIG_MM_REGIONS > 3
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# error "CONFIG_MM_REGIONS > 3 but I don't know what all of the regions are"
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# endif
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# elif CONFIG_MM_REGIONS > 2
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# error "CONFIG_MM_REGIONS > 2 but I don't know what all of the regions are"
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# endif
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void up_addregion(void)
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{
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/* Add the STM32F40xxx TCM SRAM heap region. */
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mm_addregion((FAR void*)SRAM2_START, SRAM2_END-SRAM2_START);
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/* Add the user specified heap region. */
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# if CONFIG_MM_REGIONS > 2 && defined(CONFIG_HEAP2_BASE) && defined(CONFIG_HEAP2_END)
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mm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_END - CONFIG_HEAP2_BASE);
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# endif
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}
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# elif defined(CONFIG_HEAP2_BASE) && defined(CONFIG_HEAP2_END)
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# if CONFIG_MM_REGIONS > 2
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# error "CONFIG_MM_REGIONS > 2 but I don't know what all of the regions are"
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# endif
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void up_addregion(void)
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{
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/* Add the user specified heap region. */
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mm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_END - CONFIG_HEAP2_BASE);
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}
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# else
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# error "CONFIG_MM_REGIONS > 1 but I don't know what any of the region(s) are"
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# endif
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#endif
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@ -500,7 +500,7 @@ int stm32_configgpio(uint32_t cfgset)
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setting = GPIO_OSPEED_25MHz;
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break;
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case GPIO_SPEED_20MHz: /* 50 MHz Fast speed output */
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case GPIO_SPEED_50MHz: /* 50 MHz Fast speed output */
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setting = GPIO_OSPEED_50MHz;
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break;
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@ -296,7 +296,7 @@ extern "C" {
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#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT)
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# define GPIO_SPEED_2MHz (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */
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# define GPIO_SPEED_25MHz (1 << GPIO_SPEED_SHIFT) /* 25 MHz Medium speed output */
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# define GPIO_SPEED_20MHz (2 << GPIO_SPEED_SHIFT) /* 50 MHz Fast speed output */
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# define GPIO_SPEED_50MHz (2 << GPIO_SPEED_SHIFT) /* 50 MHz Fast speed output */
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# define GPIO_SPEED_100MHz (3 << GPIO_SPEED_SHIFT) /* 100 MHz High speed output */
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/* Output/Alt function type selection:
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93
arch/arm/src/stm32/stm32_lse.c
Normal file
93
arch/arm/src/stm32/stm32_lse.c
Normal file
@ -0,0 +1,93 @@
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/****************************************************************************
|
||||
* arch/arm/src/stm32/stm32_lse.c
|
||||
*
|
||||
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "stm32_rcc.h"
|
||||
#include "stm32_waste.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_enablelse
|
||||
*
|
||||
* Todo:
|
||||
* Check for LSE good timeout and return with -1,
|
||||
* possible ISR optimization? or at least ISR should be cough in case of\
|
||||
* failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_rcc_enablelse(void)
|
||||
{
|
||||
/* Enable LSE */
|
||||
|
||||
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
|
||||
|
||||
/* We could wait for ISR here ... */
|
||||
|
||||
while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0)
|
||||
{
|
||||
up_waste();
|
||||
}
|
||||
|
||||
/* Select LSE as RTC Clock Source */
|
||||
|
||||
modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
|
||||
|
||||
/* Enable Clock */
|
||||
|
||||
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
|
||||
}
|
||||
@ -49,6 +49,9 @@
|
||||
#include "stm32_internal.h"
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
# include "nvic.h"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: showprogress
|
||||
@ -64,6 +67,33 @@
|
||||
# define showprogress(c)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fpuconfig
|
||||
*
|
||||
* Description:
|
||||
* Configure the FPU. The the MCU has an FPU, then enable full access
|
||||
* to coprocessors CP10 and CP11.
|
||||
*
|
||||
* This is implemented as a macro because the stack has not yet been
|
||||
* initialized.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
# define stm32_fpuconfig() \
|
||||
{ \
|
||||
uint32_t regval = getreg32(NVIC_CPACR); \
|
||||
regval |= ((3 << (2*10)) | (3 << (2*11))); \
|
||||
putreg32(regval, NVIC_CPACR); \
|
||||
}
|
||||
#else
|
||||
# define stm32_fpuconfig()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@ -84,6 +114,7 @@ void __start(void)
|
||||
/* Configure the uart so that we can get debug output as soon as possible */
|
||||
|
||||
stm32_clockconfig();
|
||||
stm32_fpuconfig();
|
||||
stm32_lowsetup();
|
||||
stm32_gpioinit();
|
||||
showprogress('A');
|
||||
|
||||
@ -36,13 +36,7 @@
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32_WASTE_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32_WASTE_H
|
||||
|
||||
/** \file
|
||||
* \author Uros Platise
|
||||
* \brief Waste CPU Time
|
||||
*
|
||||
* \addtogroup STM32_WASTE
|
||||
* \{
|
||||
*/
|
||||
/* Waste CPU Time */
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -58,7 +52,6 @@ extern "C" {
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@ -76,10 +69,10 @@ extern "C" {
|
||||
|
||||
EXTERN void up_waste(void);
|
||||
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_RRC_H */
|
||||
|
||||
@ -512,31 +512,3 @@ static inline void rcc_enableperipherals(void)
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_enablelse
|
||||
*
|
||||
* Todo:
|
||||
* Check for LSE good timeout and return with -1,
|
||||
* possible ISR optimization? or at least ISR should be cough in case of failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_rcc_enablelse(void)
|
||||
{
|
||||
/* Enable LSE */
|
||||
|
||||
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
|
||||
|
||||
/* We could wait for ISR here ... */
|
||||
|
||||
while( !(getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) ) up_waste();
|
||||
|
||||
/* Select LSE as RTC Clock Source */
|
||||
|
||||
modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
|
||||
|
||||
/* Enable Clock */
|
||||
|
||||
modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user