From 79b3bec208a15e5a0653fe7ac7479b0e75d5a7ae Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sat, 16 Feb 2019 20:53:16 +0000 Subject: [PATCH] Merged in raiden00/nuttx_lora (pull request #825) Master arch/arm/src/stm32f0l0: SPI support for F0 arch/arm/src/stm32f0l0/Kconfig: L0 parts should select STM32F0L0_STM32L0 arch/arm/src/stm32f0l0/hardware: unify names for ADC/DAC/DMA/CAN drivers/wireless/lpwan/sx127x/sx127x.c: return immediately when ISR0 is called but sx127x is not initialized configs/nucleo-f091rc: support for sx127x configs/nucleo-l073rz: cosmetics configs/b-l072z-lrwan1/include/board.h: use HSI as default clock source and fix typo in SPI1 pins Approved-by: GregoryN --- arch/arm/src/stm32f0l0/Kconfig | 33 +- arch/arm/src/stm32f0l0/Make.defs | 10 +- arch/arm/src/stm32f0l0/hardware/stm32_spi.h | 86 +-- .../src/stm32f0l0/hardware/stm32f05x_pinmap.h | 34 +- .../hardware/stm32f05xf07xf09x_memorymap.h | 6 +- .../src/stm32f0l0/hardware/stm32f07x_pinmap.h | 48 +- .../src/stm32f0l0/hardware/stm32f09x_pinmap.h | 48 +- arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h | 10 +- .../stm32f0l0/hardware/stm32l0_memorymap.h | 4 +- .../src/stm32f0l0/hardware/stm32l0_pinmap.h | 2 +- arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h | 12 +- arch/arm/src/stm32f0l0/stm32_clockconfig.c | 147 ----- arch/arm/src/stm32f0l0/stm32_clockconfig.h | 77 --- arch/arm/src/stm32f0l0/stm32_rcc.c | 7 +- arch/arm/src/stm32f0l0/stm32_rcc.h | 12 + arch/arm/src/stm32f0l0/stm32_spi.c | 138 +++-- arch/arm/src/stm32f0l0/stm32_start.c | 2 +- arch/arm/src/stm32f0l0/stm32f0_rcc.c | 506 ++++++++++++++++++ arch/arm/src/stm32f0l0/stm32l0_rcc.c | 12 +- configs/b-l072z-lrwan1/include/board.h | 17 +- configs/b-l072z-lrwan1/src/stm32_sx127x.c | 2 +- configs/nucleo-f091rc/include/board.h | 12 + configs/nucleo-f091rc/src/Makefile | 8 + configs/nucleo-f091rc/src/nucleo-f091rc.h | 35 ++ configs/nucleo-f091rc/src/stm32_boot.c | 6 + configs/nucleo-f091rc/src/stm32_bringup.c | 8 + configs/nucleo-f091rc/src/stm32_spi.c | 196 +++++++ configs/nucleo-f091rc/src/stm32_sx127x.c | 159 ++++++ configs/nucleo-l073rz/src/nucleo-l073rz.h | 4 +- configs/nucleo-l073rz/src/stm32_boot.c | 1 - configs/nucleo-l073rz/src/stm32_sx127x.c | 4 +- drivers/wireless/lpwan/sx127x/sx127x.c | 9 + 32 files changed, 1210 insertions(+), 445 deletions(-) delete mode 100644 arch/arm/src/stm32f0l0/stm32_clockconfig.c delete mode 100644 arch/arm/src/stm32f0l0/stm32_clockconfig.h create mode 100644 arch/arm/src/stm32f0l0/stm32f0_rcc.c create mode 100644 configs/nucleo-f091rc/src/stm32_spi.c create mode 100644 configs/nucleo-f091rc/src/stm32_sx127x.c diff --git a/arch/arm/src/stm32f0l0/Kconfig b/arch/arm/src/stm32f0l0/Kconfig index d7bc7547e8..7343e27278 100644 --- a/arch/arm/src/stm32f0l0/Kconfig +++ b/arch/arm/src/stm32f0l0/Kconfig @@ -451,82 +451,82 @@ config ARCH_CHIP_STM32F098VC config ARCH_CHIP_STM32L072V8 bool "STM32L072V8" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072VB bool "STM32L072VB" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072VZ bool "STM32L072VZ" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072KB bool "STM32L072KB" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072KZ bool "STM32L072KZ" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072CB bool "STM32L072CB" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072CZ bool "STM32L072CZ" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072RB bool "STM32L072RB" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072RZ bool "STM32L072RZ" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073V8 bool "STM32L073V8" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073VB bool "STM32L073VB" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073VZ bool "STM32L073VZ" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073CB bool "STM32L073CB" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073CZ bool "STM32L073CZ" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073RB bool "STM32L073RB" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073RZ bool "STM32L073RZ" - select STM32F0L0_ENERGYLITE + select STM32F0L0_STM32L0 depends on ARCH_CHIP_STM32L0 endchoice # ST STM32F0/L0 Chip Selection @@ -607,6 +607,7 @@ config STM32F0L0_STM32F0 config STM32F0L0_STM32L0 bool + select STM32F0L0_ENERGYLITE default n config STM32F0L0_STM32F03X diff --git a/arch/arm/src/stm32f0l0/Make.defs b/arch/arm/src/stm32f0l0/Make.defs index 05edb1cc12..e3ef2f8b8f 100644 --- a/arch/arm/src/stm32f0l0/Make.defs +++ b/arch/arm/src/stm32f0l0/Make.defs @@ -66,15 +66,7 @@ endif CHIP_ASRCS = CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c # stm32_dma_v1.c -CHIP_CSRCS += stm32_lse.c stm32_lowputc.c stm32_serial.c - -# Configuration-dependent STM32F0/L0 files - -ifeq ($(CONFIG_ARCH_CHIP_STM32F0),y) -CHIP_CSRCS += stm32_clockconfig.c -else ifeq ($(CONFIG_ARCH_CHIP_STM32L0),y) -CHIP_CSRCS += stm32_rcc.c -endif +CHIP_CSRCS += stm32_lse.c stm32_lowputc.c stm32_serial.c stm32_rcc.c ifeq ($(CONFIG_STM32F0L0_PWR),y) CHIP_CSRCS += stm32_pwr.c diff --git a/arch/arm/src/stm32f0l0/hardware/stm32_spi.h b/arch/arm/src/stm32f0l0/hardware/stm32_spi.h index 4f78fc1dcb..7d8efa1e03 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32_spi.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32_spi.h @@ -43,6 +43,16 @@ #include #include "chip.h" +/* Select STM32 SPI IP core */ + +#if defined(CONFIG_STM32F0L0_STM32F0) +# define HAVE_IP_SPI_V2 +#elif defined(CONFIG_STM32F0L0_STM32L0) +# define HAVE_IP_SPI_V1 +#else +# error Unsupported family +#endif + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -157,7 +167,11 @@ #define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */ #define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */ #define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */ -#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */ +# ifdef HAVE_IP_SPI_V2 +# define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */ +#else +# define SPI_CR1_DFF (1 << 11) /* Bit 11: Data frame format */ +#endif #define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */ #define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */ #define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */ @@ -168,30 +182,34 @@ #define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */ #define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */ #define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */ -#define SPI_CR2_NSSP (1 << 3) /* Bit 3 NSSP: NSS pulse management */ +#ifdef HAVE_IP_SPI_V2 +# define SPI_CR2_NSSP (1 << 3) /* Bit 3 NSSP: NSS pulse management */ +#endif #define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */ #define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */ #define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */ #define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */ -#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */ -#define SPI_CR2_DS_MASK (0xf << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_VAL(bits) (((bits)-1) << SPI_CR2_DS_SHIFT) -# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL(4) -# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL(5) -# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL(6) -# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL(7) -# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL(8) -# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL(9) -# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10) -# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11) -# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12) -# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13) -# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14) -# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15) -# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16) -#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */ -#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */ -#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */ +#ifdef HAVE_IP_SPI_V2 +# define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */ +# define SPI_CR2_DS_MASK (0xf << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_VAL(bits) (((bits)-1) << SPI_CR2_DS_SHIFT) +# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL(4) +# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL(5) +# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL(6) +# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL(7) +# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL(8) +# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL(9) +# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10) +# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11) +# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12) +# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13) +# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14) +# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15) +# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16) +# define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */ +# define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */ +# define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */ +#endif /* SPI status register */ @@ -204,18 +222,20 @@ #define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */ #define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */ #define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */ -#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ -#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT) -# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */ -# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ -# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ -# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ -#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ -#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT) -# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ -# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */ -# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ -# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ +#ifdef HAVE_IP_SPI_V2 +# define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */ +# define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT) +# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */ +# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */ +# define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */ +# define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT) +# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */ +# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */ +# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */ +# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */ +#endif /* I2S configuration register */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h b/arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h index f7ff344143..153a4c1a38 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32f05x_pinmap.h @@ -68,24 +68,24 @@ * pins in this file. */ -/* ADC */ +/* ADC 1 */ -#define GPIO_ADC_IN0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) -#define GPIO_ADC_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_ADC_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) -#define GPIO_ADC_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_ADC_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) -#define GPIO_ADC_IN5 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_ADC_IN6 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) -#define GPIO_ADC_IN7 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_ADC_IN8 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_ADC_IN9 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_ADC_IN10 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0) -#define GPIO_ADC_IN11 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1) -#define GPIO_ADC_IN12 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2) -#define GPIO_ADC_IN13 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3) -#define GPIO_ADC_IN14 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4) -#define GPIO_ADC_IN15 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) +#define GPIO_ADC1_IN0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) +#define GPIO_ADC1_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_ADC1_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) +#define GPIO_ADC1_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_ADC1_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) +#define GPIO_ADC1_IN5 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) +#define GPIO_ADC1_IN6 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) +#define GPIO_ADC1_IN7 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_ADC1_IN8 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_ADC1_IN9 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) +#define GPIO_ADC1_IN10 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0) +#define GPIO_ADC1_IN11 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1) +#define GPIO_ADC1_IN12 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2) +#define GPIO_ADC1_IN13 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3) +#define GPIO_ADC1_IN14 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4) +#define GPIO_ADC1_IN15 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) /* TIMERS */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h b/arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h index bf2a6b13be..7aed68d2dd 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32f05xf07xf09x_memorymap.h @@ -106,10 +106,10 @@ #define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */ #define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB device FS */ #define STM32_USBRAM_BASE 0x40006000 /* 0x40006000-0x400063ff USB SRAM 512B */ -#define STM32_CAN_BASE 0x40006400 /* 0x40006400-0x400067ff bxCAN */ +#define STM32_CAN1_BASE 0x40006400 /* 0x40006400-0x400067ff bxCAN 1 */ #define STM32_CRS_BASE 0x40006c00 /* 0x40006c00-0x40006fff CRS */ #define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */ -#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff DAC */ +#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff DAC 1 */ #define STM32_CEC_BASE 0x40007800 /* 0x40007800-0x40007bff HDMI CEC */ /* APB2 Base Addresses **************************************************************/ @@ -119,7 +119,7 @@ #define STM32_USART6_BASE 0x40011400 /* 0x40011400-0x400117ff USART6 */ #define STM32_USART7_BASE 0x40011800 /* 0x40011800-0x40011bff USART7 */ #define STM32_USART8_BASE 0x40011c00 /* 0x40011c00-0x40011fff USART8 */ -#define STM32_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */ +#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC 1 */ #define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */ #define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ #define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h b/arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h index 9a794c9f3a..18cf426856 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32f07x_pinmap.h @@ -67,33 +67,33 @@ * pins in this file. */ -/* ADC */ +/* ADC 1 */ -#define GPIO_ADC_IN0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) -#define GPIO_ADC_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_ADC_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) -#define GPIO_ADC_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_ADC_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) -#define GPIO_ADC_IN5 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_ADC_IN6 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) -#define GPIO_ADC_IN7 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_ADC_IN8 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_ADC_IN9 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_ADC_IN10 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0) -#define GPIO_ADC_IN11 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1) -#define GPIO_ADC_IN12 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2) -#define GPIO_ADC_IN13 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3) -#define GPIO_ADC_IN14 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4) -#define GPIO_ADC_IN15 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) +#define GPIO_ADC1_IN0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) +#define GPIO_ADC1_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_ADC1_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) +#define GPIO_ADC1_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_ADC1_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) +#define GPIO_ADC1_IN5 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) +#define GPIO_ADC1_IN6 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) +#define GPIO_ADC1_IN7 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_ADC1_IN8 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_ADC1_IN9 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) +#define GPIO_ADC1_IN10 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0) +#define GPIO_ADC1_IN11 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1) +#define GPIO_ADC1_IN12 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2) +#define GPIO_ADC1_IN13 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3) +#define GPIO_ADC1_IN14 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4) +#define GPIO_ADC1_IN15 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -/* CAN */ +/* CAN 1 */ -#define GPIO_CAN_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN0) -#define GPIO_CAN_RX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN11) -#define GPIO_CAN_RX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN8) -#define GPIO_CAN_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN1) -#define GPIO_CAN_TX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN12) -#define GPIO_CAN_TX_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN9) +#define GPIO_CAN1_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN0) +#define GPIO_CAN1_RX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_CAN1_RX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN8) +#define GPIO_CAN1_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN1) +#define GPIO_CAN1_TX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN12) +#define GPIO_CAN1_TX_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN9) /* HDMI-CEC */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h b/arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h index 7d1c429117..5c55782f86 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32f09x_pinmap.h @@ -67,33 +67,33 @@ * pins in this file. */ -/* ADC */ +/* ADC 1 */ -#define GPIO_ADC_IN0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) -#define GPIO_ADC_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) -#define GPIO_ADC_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) -#define GPIO_ADC_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) -#define GPIO_ADC_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) -#define GPIO_ADC_IN5 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#define GPIO_ADC_IN6 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) -#define GPIO_ADC_IN7 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) -#define GPIO_ADC_IN8 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) -#define GPIO_ADC_IN9 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) -#define GPIO_ADC_IN10 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0) -#define GPIO_ADC_IN11 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1) -#define GPIO_ADC_IN12 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2) -#define GPIO_ADC_IN13 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3) -#define GPIO_ADC_IN14 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4) -#define GPIO_ADC_IN15 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) +#define GPIO_ADC1_IN0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN0) +#define GPIO_ADC1_IN1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) +#define GPIO_ADC1_IN2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN2) +#define GPIO_ADC1_IN3 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN3) +#define GPIO_ADC1_IN4 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) +#define GPIO_ADC1_IN5 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) +#define GPIO_ADC1_IN6 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) +#define GPIO_ADC1_IN7 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) +#define GPIO_ADC1_IN8 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN0) +#define GPIO_ADC1_IN9 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN1) +#define GPIO_ADC1_IN10 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN0) +#define GPIO_ADC1_IN11 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN1) +#define GPIO_ADC1_IN12 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN2) +#define GPIO_ADC1_IN13 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN3) +#define GPIO_ADC1_IN14 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN4) +#define GPIO_ADC1_IN15 (GPIO_ANALOG | GPIO_PORTC | GPIO_PIN5) -/* CAN */ +/* CAN 1 */ -#define GPIO_CAN_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN0) -#define GPIO_CAN_RX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN11) -#define GPIO_CAN_RX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN8) -#define GPIO_CAN_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN1) -#define GPIO_CAN_TX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN12) -#define GPIO_CAN_TX_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN9) +#define GPIO_CAN1_RX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN0) +#define GPIO_CAN1_RX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN11) +#define GPIO_CAN1_RX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN8) +#define GPIO_CAN1_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN1) +#define GPIO_CAN1_TX_3 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN12) +#define GPIO_CAN1_TX_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTB | GPIO_PIN9) /* HDMI-CEC */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h b/arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h index 125677606e..b21f2977df 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32f0_rcc.h @@ -210,7 +210,7 @@ #define RCC_APB2RSTR_USART6RST (1 << 5) /* Bit 5: USART6 reset */ #define RCC_APB2RSTR_USART7RST (1 << 6) /* Bit 6: USART7 reset */ #define RCC_APB2RSTR_USART8RST (1 << 7) /* Bit 7: USART8 reset */ -#define RCC_APB2RSTR_ADCRST (1 << 9) /* Bit 9: ADC interface reset */ +#define RCC_APB2RSTR_ADC1RST (1 << 9) /* Bit 9: ADC1 interface reset */ #define RCC_APB2RSTR_TIM1RST (1 << 11) /* Bit 11: TIM1 Timer reset */ #define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI 1 reset */ #define RCC_APB2RSTR_USART1RST (1 << 14) /* Bit 14: USART1 reset */ @@ -238,7 +238,7 @@ #define RCC_APB1RSTR_CAN1RST (1 << 25) /* Bit 25: CAN1 reset */ #define RCC_APB1RSTR_CRSRST (1 << 27) /* Bit 27: CRS / Backup interface reset */ #define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */ -#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC interface reset */ +#define RCC_APB1RSTR_DAC1RST (1 << 29) /* Bit 29: DAC1 interface reset */ #define RCC_APB1RSTR_CECRST (1 << 30) /* Bit 30: CEC reset */ /* AHB Peripheral Clock enable register */ @@ -262,7 +262,7 @@ #define RCC_APB2ENR_USART6EN (1 << 5) /* Bit 5: USART6 clock enable */ #define RCC_APB2ENR_USART7EN (1 << 6) /* Bit 6: USART7 clock enable */ #define RCC_APB2ENR_USART8EN (1 << 7) /* Bit 7: USART8 & COMP clock enable */ -#define RCC_APB2ENR_ADCEN (1 << 9) /* Bit 10: ADC interface clock enable */ +#define RCC_APB2ENR_ADC1EN (1 << 9) /* Bit 10: ADC1 interface clock enable */ #define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 Timer clock enable */ #define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI 1 clock enable */ #define RCC_APB2ENR_USART1EN (1 << 14) /* Bit 14: USART1 clock enable */ @@ -288,10 +288,10 @@ #define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 clock enable */ #define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 clock enable */ #define RCC_APB1ENR_USBEN (1 << 23) /* Bit 23: USB clock enable */ -#define RCC_APB1ENR_CANEN (1 << 25) /* Bit 25: CAN clock enable */ +#define RCC_APB1ENR_CAN1EN (1 << 25) /* Bit 25: CAN 1 clock enable */ #define RCC_APB1ENR_CRSEN (1 << 27) /* Bit 27: CRS / Backup interface clock enable */ #define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */ -#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */ +#define RCC_APB1ENR_DAC1EN (1 << 29) /* Bit 29: DAC1 interface clock enable */ #define RCC_APB1ENR_CECEN (1 << 30) /* Bit 30: CEC clock enable */ /* RTC domain control register */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h b/arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h index a565f0ad97..f6ac7a385c 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32l0_memorymap.h @@ -92,7 +92,7 @@ #define STM32_USBRAM_BASE 0x40006000 /* 0x40006000-0x400063ff USB SRAM 512B */ #define STM32_CRS_BASE 0x40006c00 /* 0x40006c00-0x40006fff PWR */ #define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */ -#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff DAC (dual) */ +#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff DAC 1 (dual) */ #define STM32_I2C3_BASE 0x40007800 /* 0x40007800-0x40007bff I2C3 */ #define STM32_LPTIM1_BASE 0x40007C00 /* 0x40007c00-0x40007fff LPTIM1 */ @@ -103,7 +103,7 @@ #define STM32_TIM21_BASE 0x40010800 /* 0x40010800-0x40010bff TIM21 */ #define STM32_TIM22_BASE 0x40014000 /* 0x40014000-0x400117ff TIM22 */ #define STM32_FIREWALL_BASE 0x4001c000 /* 0x4001c000-0x400113ff Firewall */ -#define STM32_ADC_BASE 0x40012400 /* 0x40012400-0x400127ff ADC */ +#define STM32_ADC1_BASE 0x40012400 /* 0x40012400-0x400127ff ADC1 */ #define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */ #define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */ #define STM32_DBGMCU_BASE 0x40015800 /* 0x40015800-0x40015bff DBGMCU */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h b/arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h index 3d8986ea65..fc2a6e3111 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32l0_pinmap.h @@ -94,7 +94,7 @@ /* DAC */ -#define GPIO_DAC_OUT1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) +#define GPIO_DAC1_OUT1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4) /* I2C */ diff --git a/arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h b/arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h index 581444aa00..0b2736d183 100644 --- a/arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h +++ b/arch/arm/src/stm32f0l0/hardware/stm32l0_rcc.h @@ -272,7 +272,7 @@ /* AHB peripheral reset register */ -#define RCC_AHBRSTR_DMARST (0) /* Bit 0: DMA reset */ +#define RCC_AHBRSTR_DMA1RST (0) /* Bit 0: DMA 1 reset */ /* Bits 1-7: Reserved */ #define RCC_AHBRSTR_MIFRST (8) /* Bit 8: Memory interface reset */ /* Bits 9-11: Reserved */ @@ -326,7 +326,7 @@ /* Bits 24-26: Reserved */ #define RCC_APB1RSTR_CRSRST (1 << 27) /* Bit 27: Clock recovery system reset */ #define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */ -#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC interface reset */ +#define RCC_APB1RSTR_DAC1RST (1 << 29) /* Bit 29: DAC 1 interface reset */ #define RCC_APB1RSTR_I2C3RST (1 << 30) /* Bit 30: I2C3 reset */ #define RCC_APB1RSTR_LPTIM1RST (1 << 31) /* Bit 31: Low-power timer reset */ @@ -342,7 +342,7 @@ /* AHB Peripheral Clock enable register */ -#define RCC_AHBENR_DMAEN (0) /* Bit 0: DMA clock enable */ +#define RCC_AHBENR_DMA1EN (0) /* Bit 0: DMA 1 clock enable */ /* Bits 1-7: Reserved */ #define RCC_AHBENR_MIFEN (8) /* Bit 8: Memory interface clock enable */ /* Bits 9-11: Reserved */ @@ -396,7 +396,7 @@ /* Bits 24-26: Reserved */ #define RCC_APB1ENR_CRSEN (1 << 27) /* Bit 27: Clock recovery system clock enable */ #define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */ -#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */ +#define RCC_APB1ENR_DAC1EN (1 << 29) /* Bit 29: DAC 1 interface clock enable */ #define RCC_APB1ENR_I2C3EN (1 << 30) /* Bit 30: I2C3 clock enable */ #define RCC_APB1ENR_LPTIM1EN (1 << 31) /* Bit 31: Low-power timer clock enable */ @@ -412,7 +412,7 @@ /* AHB peripheral clock enable in Sleep mode register */ -#define RCC_AHBSMENR_DMASMEN (0) /* Bit 0: DMA clock enable in Sleep mode */ +#define RCC_AHBSMENR_DMA1SMEN (0) /* Bit 0: DMA 1 clock enable in Sleep mode */ /* Bits 1-7: Reserved */ #define RCC_AHBSMENR_MIFSMEN (8) /* Bit 8: Memory interface clock enable in Sleep mode */ /* Bits 9-11: Reserved */ @@ -466,7 +466,7 @@ /* Bits 24-26: Reserved */ #define RCC_APB1SMENR_CRSSMEN (1 << 27) /* Bit 27: Clock recovery system clock enable in Sleep mode */ #define RCC_APB1SMENR_PWRSMEN (1 << 28) /* Bit 28: Power interface clock enable in Sleep mode */ -#define RCC_APB1SMENR_DACSMEN (1 << 29) /* Bit 29: DAC interface clock enable in Sleep mode */ +#define RCC_APB1SMENR_DAC1SMEN (1 << 29) /* Bit 29: DAC 1 interface clock enable in Sleep mode */ #define RCC_APB1SMENR_I2C3SMEN (1 << 30) /* Bit 30: I2C3 clock enable in Sleep mode */ #define RCC_APB1SMENR_LPTIM1SMEN (1 << 31) /* Bit 31: Low-power timer clock enable in Sleep mode */ diff --git a/arch/arm/src/stm32f0l0/stm32_clockconfig.c b/arch/arm/src/stm32f0l0/stm32_clockconfig.c deleted file mode 100644 index 0356d4ee2e..0000000000 --- a/arch/arm/src/stm32f0l0/stm32_clockconfig.c +++ /dev/null @@ -1,147 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0/stm32_clockconfig.c - * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Alan Carvalho de Assis - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include - -#include "up_arch.h" -#include "up_internal.h" -#include "stm32_rcc.h" -#include "stm32_clockconfig.h" -#include "hardware/stm32_syscfg.h" -#include "hardware/stm32_flash.h" -#include "hardware/stm32_gpio.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_clockconfig - * - * Description: - * Called to initialize the STM32F0xx. This does whatever setup is needed - * to put the SoC in a usable state. This includes the initialization of - * clocking using the settings in board.h. - * - ****************************************************************************/ - -void stm32_clockconfig(void) -{ - uint32_t regval; - - /* Verify if PLL is already setup. If so configure to use HSI mode */ - - if ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) == RCC_CFGR_SWS_PLL) - { - /* Select HSI mode */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~RCC_CFGR_SW_MASK; - putreg32(regval, STM32_RCC_CFGR); - - while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_HSI); - } - - /* Disable the PLL */ - - regval = getreg32(STM32_RCC_CR); - regval &= ~RCC_CR_PLLON; - putreg32(regval, STM32_RCC_CR); - while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) != 0); - - /* Enable FLASH prefetch buffer and set flash latency */ - - regval = getreg32(STM32_FLASH_ACR); - regval &= ~FLASH_ACR_LATENCY_MASK; - regval |= (FLASH_ACR_LATENCY_1 | FLASH_ACR_PRTFBE); - putreg32(regval, STM32_FLASH_ACR); - - /* Set HCLK = SYSCLK */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~RCC_CFGR_HPRE_MASK; - regval |= RCC_CFGR_HPRE_SYSCLK; - putreg32(regval, STM32_RCC_CFGR); - - /* Set PCLK = HCLK */ - - regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= RCC_CFGR_PPRE1_HCLK; - putreg32(regval, STM32_RCC_CFGR); - - /* Configure the PLL to generate the system clock - * - * 1. Use source = HSI/2 - * 2. Use PREDIV = 1 - * 3. Use multiplier from board.h - */ - - regval &= ~(RCC_CFGR_PLLSRC_MASK | RCC_CFGR_PLLXTPRE_MASK | RCC_CFGR_PLLMUL_MASK); - regval |= (RCC_CFGR_PLLSRC_HSId2 | RCC_CFGR_PLLXTPRE_DIV1 | STM32_CFGR_PLLMUL); - putreg32(regval, STM32_RCC_CFGR); - - /* Enable the PLL */ - - regval = getreg32(STM32_RCC_CR); - regval |= RCC_CR_PLLON; - putreg32(regval, STM32_RCC_CR); - while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0); - - /* Configure to use the PLL */ - - regval = getreg32(STM32_RCC_CFGR); - regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32_RCC_CFGR); - while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL); - - /* Enable basic peripheral support */ - /* Enable all GPIO modules */ - - regval = getreg32(STM32_RCC_AHBENR); - regval |= RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPBEN | RCC_AHBENR_IOPCEN |\ - RCC_AHBENR_IOPDEN | RCC_AHBENR_IOPEEN | RCC_AHBENR_IOPFEN; - putreg32(regval, STM32_RCC_AHBENR); -} diff --git a/arch/arm/src/stm32f0l0/stm32_clockconfig.h b/arch/arm/src/stm32f0l0/stm32_clockconfig.h deleted file mode 100644 index af1c4ac975..0000000000 --- a/arch/arm/src/stm32f0l0/stm32_clockconfig.h +++ /dev/null @@ -1,77 +0,0 @@ -/************************************************************************************ - * arch/arm/src/stm32f0l0/stm32_clockconfig.h - * - * Copyright (C) 2017 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Alan Carvalho de Assis - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0_STM32_CLOCKCONFIG_H -#define __ARCH_ARM_SRC_STM32F0L0_STM32_CLOCKCONFIG_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" -{ -#endif - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -/************************************************************************************ - * Name: stm32_clockconfig - * - * Description: - * Called to initialize the STM32F0XX. This does whatever setup is needed to put - * the MCU in a usable state. This includes the initialization of clocking using - * the settings in board.h. - * - ************************************************************************************/ - -void stm32_clockconfig(void); - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_STM32F0L0_STM32_CLOCKCONFIG_H */ diff --git a/arch/arm/src/stm32f0l0/stm32_rcc.c b/arch/arm/src/stm32f0l0/stm32_rcc.c index 272674e998..65a1e5c724 100644 --- a/arch/arm/src/stm32f0l0/stm32_rcc.c +++ b/arch/arm/src/stm32f0l0/stm32_rcc.c @@ -50,9 +50,8 @@ #include "up_arch.h" #include "hardware/stm32_flash.h" -#include "hardware/stm32_rcc.h" #include "stm32_gpio.h" -#include "stm32_clockconfig.h" +#include "stm32_rcc.h" /**************************************************************************** * Pre-processor Definitions @@ -71,7 +70,9 @@ /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_ARCH_CHIP_STM32L0) +#if defined(CONFIG_ARCH_CHIP_STM32F0) +# include "stm32f0_rcc.c" +#elif defined(CONFIG_ARCH_CHIP_STM32L0) # include "stm32l0_rcc.c" #else # error "Unsupported STM32F0/L0 RCC" diff --git a/arch/arm/src/stm32f0l0/stm32_rcc.h b/arch/arm/src/stm32f0l0/stm32_rcc.h index cfc00aa2db..d157305efb 100644 --- a/arch/arm/src/stm32f0l0/stm32_rcc.h +++ b/arch/arm/src/stm32f0l0/stm32_rcc.h @@ -52,6 +52,18 @@ * Public Function Protoypes ************************************************************************************/ +/************************************************************************************ + * Name: stm32_clockconfig + * + * Description: + * Called to initialize the STM32F0XX. This does whatever setup is needed to put + * the MCU in a usable state. This includes the initialization of clocking using + * the settings in board.h. + * + ************************************************************************************/ + +void stm32_clockconfig(void); + /************************************************************************************ * Name: stm32_rcc_enablelse * diff --git a/arch/arm/src/stm32f0l0/stm32_spi.c b/arch/arm/src/stm32f0l0/stm32_spi.c index 454093534f..779ec0f62a 100644 --- a/arch/arm/src/stm32f0l0/stm32_spi.c +++ b/arch/arm/src/stm32f0l0/stm32_spi.c @@ -95,10 +95,6 @@ #ifdef CONFIG_STM32F0L0_SPI -#ifdef ARCH_CHIP_STM32F0 -# error SPI driver not tested for F0 yet -#endif - /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -505,37 +501,39 @@ static inline void spi_writeword(FAR struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0) + { + } - /* Then send the byte */ + /* Then send the word */ - spi_putreg(priv, STM32_SPI_DR_OFFSET, word); -} +#ifdef HAVE_IP_SPI_V2 + /* "When the data frame size fits into one byte (less than or equal to 8 bits), + * data packing is used automatically when any read or write 16-bit access is + * performed on the SPIx_DR register. The double data frame pattern is handled + * in parallel in this case. At first, the SPI operates using the pattern + * stored in the LSB of the accessed word, then with the other half stored in + * the MSB... + * + * "A specific problem appears if an odd number of such "fit into one byte" + * data frames must be handled. On the transmitter side, writing the last + * data frame of any odd sequence with an 8-bit access to SPIx_DR is enough. + * ..." + * + * REVISIT: "...The receiver has to change the Rx_FIFO threshold level for the + * last data frame received in the odd sequence of frames in order to generate + * the RXNE event." + */ -/************************************************************************************ - * Name: spi_writebyte - * - * Description: - * Write one 8-bit frame to the SPI FIFO - * - * Input Parameters: - * priv - Device-specific state data - * byte - Byte to send - * - * Returned Value: - * None - * - ************************************************************************************/ - -static inline void spi_writebyte(FAR struct stm32_spidev_s *priv, uint8_t byte) -{ - /* Wait until the transmit buffer is empty */ - - while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); - - /* Then send the byte */ - - spi_putreg8(priv, STM32_SPI_DR_OFFSET, byte); + if (priv->nbits < 9) + { + spi_putreg8(priv, STM32_SPI_DR_OFFSET, (uint8_t)word); + } + else +#endif + { + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); + } } /************************************************************************************ @@ -554,7 +552,11 @@ static inline void spi_writebyte(FAR struct stm32_spidev_s *priv, uint8_t byte) static inline bool spi_16bitmode(FAR struct stm32_spidev_s *priv) { +#ifdef HAVE_IP_SPI_V2 return (priv->nbits > 8); +#else + return ((spi_getreg(priv, STM32_SPI_CR1_OFFSET) & SPI_CR1_DFF) != 0); +#endif } /************************************************************************************ @@ -1101,6 +1103,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) if (nbits != priv->nbits) { +#ifdef HAVE_IP_SPI_V2 /* Yes... Set CR2 appropriately */ /* Set the number of bits (valid range 4-16) */ @@ -1129,6 +1132,29 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); +#else + /* Yes... Set CR1 appropriately */ + + switch (nbits) + { + case 8: + setbits = 0; + clrbits = SPI_CR1_DFF; + break; + + case 16: + setbits = SPI_CR1_DFF; + clrbits = 0; + break; + + default: + return; + } + + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); +#endif /* Save the selection so the subsequence re-configurations will be faster */ @@ -1226,38 +1252,16 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd) DEBUGASSERT(priv && priv->spibase); - /* According to the number of bits, access data register as word or byte - * This is absolutely required because of packing. With <=8 bit frames, - * two bytes are received by a 16-bit read of the data register! - */ + spi_writeword(priv, wd); + ret = spi_readword(priv); - if (spi_16bitmode(priv)) - { - spi_writeword(priv, wd); - ret = spi_readword(priv); - } - else - { - spi_writebyte(priv, (uint8_t)(wd & 0xFF)); - ret = (uint16_t)spi_readbyte(priv); - } - - /* Check and clear any error flags (Reading from the SR clears the error - * flags). - */ + /* Check and clear any error flags (Reading from the SR clears the error flags) */ regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); - if (spi_16bitmode(priv)) - { - spiinfo("Sent: %04x Return: %04x Status: %02x\n", wd, ret, regval); - } - else - { - spiinfo("Sent: %02x Return: %02x Status: %02x\n", wd, ret, regval); - } - + spiinfo("Sent: %04x Return: %04x Status: %02x\n", wd, ret, regval); UNUSED(regval); + return ret; } @@ -1637,6 +1641,7 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv) int ret; #endif +#ifdef HAVE_IP_SPI_V2 /* Configure CR1 and CR2. Default configuration: * Mode 0: CR1.CPHA=0 and CR1.CPOL=0 * Master: CR1.MSTR=1 @@ -1654,6 +1659,21 @@ static void spi_bus_initialize(FAR struct stm32_spidev_s *priv) clrbits = SPI_CR2_DS_MASK; setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); +#else + /* Configure CR1. Default configuration: + * Mode 0: CPHA=0 and CPOL=0 + * Master: MSTR=1 + * 8-bit: DFF=0 + * MSB transmitted first: LSBFIRST=0 + * Replace NSS with SSI & SSI=1: SSI=1 SSM=1 (prevents MODF error) + * Two lines full duplex: BIDIMODE=0 BIDIOIE=(Don't care) and RXONLY=0 + */ + + clrbits = SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_BR_MASK | SPI_CR1_LSBFIRST | + SPI_CR1_RXONLY | SPI_CR1_DFF | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; + setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); +#endif priv->frequency = 0; priv->nbits = 8; diff --git a/arch/arm/src/stm32f0l0/stm32_start.c b/arch/arm/src/stm32f0l0/stm32_start.c index d63513a792..b2176ef187 100644 --- a/arch/arm/src/stm32f0l0/stm32_start.c +++ b/arch/arm/src/stm32f0l0/stm32_start.c @@ -50,7 +50,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "stm32_clockconfig.h" +#include "stm32_rcc.h" #include "stm32_lowputc.h" #include "stm32_start.h" diff --git a/arch/arm/src/stm32f0l0/stm32f0_rcc.c b/arch/arm/src/stm32f0l0/stm32f0_rcc.c new file mode 100644 index 0000000000..2d29296228 --- /dev/null +++ b/arch/arm/src/stm32f0l0/stm32f0_rcc.c @@ -0,0 +1,506 @@ +/**************************************************************************** + * arch/arm/src/stm32f0l0/stm32f0_rcc.c + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Alan Carvalho de Assis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "stm32_rcc.h" +#include "hardware/stm32_syscfg.h" +#include "hardware/stm32_flash.h" +#include "hardware/stm32_gpio.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_reset + * + * Description: + * Put all RCC registers in reset state + * + ****************************************************************************/ + +static inline void rcc_reset(void) +{ + /* Nothing here for now */ +} + +/**************************************************************************** + * Name: rcc_enableio + * + * Description: + * Enable selected GPIO + * + ****************************************************************************/ + +static inline void rcc_enableio(void) +{ + uint32_t regval = 0; + + /* Enable basic peripheral support */ + /* Enable all GPIO modules */ + + regval = getreg32(STM32_RCC_AHBENR); + regval |= RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPBEN | RCC_AHBENR_IOPCEN |\ + RCC_AHBENR_IOPDEN | RCC_AHBENR_IOPEEN | RCC_AHBENR_IOPFEN; + putreg32(regval, STM32_RCC_AHBENR); +} + +/**************************************************************************** + * Name: rcc_enableahb + * + * Description: + * Enable selected AHB peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb(void) +{ + uint32_t regval = 0; + + /* Set the appropriate bits in the AHBENR register to enabled the + * selected AHBENR peripherals. + */ + + regval = getreg32(STM32_RCC_AHBENR); + +#ifdef CONFIG_STM32F0L0_DMA1 + /* DMA 1 clock enable */ + + regval |= RCC_AHBENR_DMA1EN; +#endif + +#ifdef CONFIG_STM32F0L0_DMA2 + /* DMA 2 clock enable */ + + regval |= RCC_AHBENR_DMA2EN; +#endif + +#ifdef CONFIG_STM32F0L0_CRC + /* CRC clock enable */ + + regval |= RCC_AHBENR_CRCEN; +#endif + +#ifdef CONFIG_STM32F0L0_TSC + /* TSC clock enable */ + + regval |= RCC_AHBENR_TSCEN; +#endif + + putreg32(regval, STM32_RCC_AHBENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb1 + * + * Description: + * Enable selected APB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb1(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB1ENR register to enabled the + * selected APB1 peripherals. + */ + + regval = getreg32(STM32_RCC_APB1ENR); + +#ifdef CONFIG_STM32F0L0_TIM2 + /* Timer 2 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB1ENR_TIM2EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_TIM3 + /* Timer 3 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB1ENR_TIM3EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_TIM4 + /* Timer 4 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB1ENR_TIM4EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_TIM6 + /* Timer 6 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB1ENR_TIM6EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_TIM7 + /* Timer 7 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB1ENR_TIM7EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_TIM14 + /* Timer 14 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB1ENR_TIM14EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_WWDG + /* Window Watchdog clock enable */ + + regval |= RCC_APB1ENR_WWDGEN; +#endif + +#ifdef CONFIG_STM32F0L0_SPI2 + /* SPI 2 clock enable */ + + regval |= RCC_APB1ENR_SPI2EN; +#endif + +#ifdef CONFIG_STM32F0L0_USART2 + /* USART 2 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB1ENR_USART2EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_USART3 + /* USART 3 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB1ENR_USART3EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_USART4 + /* USART 4 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB1ENR_USART4EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_USART5 + /* USART 5 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB1ENR_USART5EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_I2C1 + /* I2C 1 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB1ENR_I2C1EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_I2C2 + /* I2C 2 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB1ENR_I2C2EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_USB + /* USB clock enable */ + + regval |= RCC_APB1ENR_USBEN; +#endif + +#ifdef CONFIG_STM32F0L0_CAN1 + /* CAN1 clock enable */ + + regval |= RCC_APB1ENR_CAN1EN; +#endif + +#ifdef CONFIG_STM32F0L0_CRS + /* Clock recovery system clock enable */ + + regval |= RCC_APB1ENR_CRSEN; +#endif + +#ifdef CONFIG_STM32F0L0_PWR + /* Power interface clock enable */ + + regval |= RCC_APB1ENR_PWREN; +#endif + +#ifdef CONFIG_STM32F0L0_DAC1 + /* DAC 1 interface clock enable */ + + regval |= RCC_APB1ENR_DAC1EN; +#endif + +#ifdef CONFIG_STM32F0L0_CEC + /* CEC interface clock enable */ + + regval |= RCC_APB1ENR_CECEN; +#endif + + putreg32(regval, STM32_RCC_APB1ENR); +} + +/**************************************************************************** + * Name: rcc_enableapb2 + * + * Description: + * Enable selected APB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB2ENR register to enabled the + * selected APB2 peripherals. + */ + + regval = getreg32(STM32_RCC_APB2ENR); + +#ifdef CONFIG_STM32F0L0_SYSCFG + /* SYSCFG clock */ + + regval |= RCC_APB2ENR_SYSCFGCOMPEN; +#endif + +#ifdef CONFIG_STM32F0L0_USART6 + /* USART 6 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB2ENR_USART6EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_USART7 + /* USART 7 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB2ENR_USART7EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_USART8 + /* USART 8 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB2ENR_USART8EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_ADC1 + /* ADC 1 clock enable */ + + regval |= RCC_APB2ENR_ADC1EN; +#endif + +#ifdef CONFIG_STM32F0L0_TIM1 + /* Timer 1 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB2ENR_TIM1EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_SPI1 + /* SPI 1 clock enable */ + + regval |= RCC_APB2ENR_SPI1EN; +#endif + +#ifdef CONFIG_STM32F0L0_USART1 + /* USART1 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB2ENR_USART1EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_TIM15 + /* Timer 15 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB2ENR_TIM15EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_TIM16 + /* Timer 16 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB2ENR_TIM16EN; +#endif +#endif + +#ifdef CONFIG_STM32F0L0_TIM17 + /* Timer 17 clock enable */ + +#ifdef CONFIG_STM32F0L0_FORCEPOWER + regval |= RCC_APB2ENR_TIM17EN; +#endif +#endif + +#if 0 + /* DBG clock enable */ + + regval |= RCC_APB2ENR_DBGMCUEN; +#endif + + putreg32(regval, STM32_RCC_APB2ENR); +} + +/**************************************************************************** + * Name: stm32_stdclockconfig + * + * Description: + * Called to change to new clock based on settings in board.h. + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes or any clocking other than PLL driven by the HSE. + * + ****************************************************************************/ + +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +static void stm32_stdclockconfig(void) +{ + uint32_t regval; + + /* Verify if PLL is already setup. If so configure to use HSI mode */ + + if ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) == RCC_CFGR_SWS_PLL) + { + /* Select HSI mode */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_SW_MASK; + putreg32(regval, STM32_RCC_CFGR); + + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_HSI); + } + + /* Disable the PLL */ + + regval = getreg32(STM32_RCC_CR); + regval &= ~RCC_CR_PLLON; + putreg32(regval, STM32_RCC_CR); + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) != 0); + + /* Enable FLASH prefetch buffer and set flash latency */ + + regval = getreg32(STM32_FLASH_ACR); + regval &= ~FLASH_ACR_LATENCY_MASK; + regval |= (FLASH_ACR_LATENCY_1 | FLASH_ACR_PRTFBE); + putreg32(regval, STM32_FLASH_ACR); + + /* Set HCLK = SYSCLK */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_HPRE_MASK; + regval |= RCC_CFGR_HPRE_SYSCLK; + putreg32(regval, STM32_RCC_CFGR); + + /* Set PCLK = HCLK */ + + regval &= ~RCC_CFGR_PPRE1_MASK; + regval |= RCC_CFGR_PPRE1_HCLK; + putreg32(regval, STM32_RCC_CFGR); + + /* Configure the PLL to generate the system clock + * + * 1. Use source = HSI/2 + * 2. Use PREDIV = 1 + * 3. Use multiplier from board.h + */ + + regval &= ~(RCC_CFGR_PLLSRC_MASK | RCC_CFGR_PLLXTPRE_MASK | RCC_CFGR_PLLMUL_MASK); + regval |= (RCC_CFGR_PLLSRC_HSId2 | RCC_CFGR_PLLXTPRE_DIV1 | STM32_CFGR_PLLMUL); + putreg32(regval, STM32_RCC_CFGR); + + /* Enable the PLL */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLON; + putreg32(regval, STM32_RCC_CR); + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0); + + /* Configure to use the PLL */ + + regval = getreg32(STM32_RCC_CFGR); + regval |= RCC_CFGR_SW_PLL; + putreg32(regval, STM32_RCC_CFGR); + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL); +} +#endif + +/**************************************************************************** + * Name: rcc_enableperiphals + ****************************************************************************/ + +static inline void rcc_enableperipherals(void) +{ + rcc_enableio(); + rcc_enableahb(); + rcc_enableapb2(); + rcc_enableapb1(); +} diff --git a/arch/arm/src/stm32f0l0/stm32l0_rcc.c b/arch/arm/src/stm32f0l0/stm32l0_rcc.c index 4a015bbd1a..fc83e0c134 100644 --- a/arch/arm/src/stm32f0l0/stm32l0_rcc.c +++ b/arch/arm/src/stm32f0l0/stm32l0_rcc.c @@ -122,6 +122,12 @@ static inline void rcc_enableahb(void) { uint32_t regval = 0; + /* Set the appropriate bits in the AHBENR register to enabled the + * selected AHBENR peripherals. + */ + + regval = getreg32(STM32_RCC_AHBENR); + #ifdef CONFIG_STM32F0L0_DMA1 /* DMA 1 clock enable */ @@ -295,10 +301,10 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_PWREN; #endif -#ifdef CONFIG_STM32F0L0_DAC - /* DAC interface clock enable */ +#ifdef CONFIG_STM32F0L0_DAC1 + /* DAC 1 interface clock enable */ - regval |= RCC_APB1ENR_DACEN; + regval |= RCC_APB1ENR_DAC1EN; #endif #ifdef CONFIG_STM32F0L0_I2C3 diff --git a/configs/b-l072z-lrwan1/include/board.h b/configs/b-l072z-lrwan1/include/board.h index c55cbe95d4..d4a2dbafb4 100644 --- a/configs/b-l072z-lrwan1/include/board.h +++ b/configs/b-l072z-lrwan1/include/board.h @@ -54,26 +54,25 @@ /* Clocking *****************************************************************/ -/* HSI - Internal 8 MHz RC Oscillator +/* HSI - Internal 16 MHz RC Oscillator * LSI - 32 KHz RC - * HSE - 8 MHz from MCO output of ST-LINK + * HSE - 8 MHz from MCO output of ST-LINK (default OFF on board) * LSE - 32.768 kHz */ #define STM32_BOARD_XTAL 8000000ul -#define STM32_HSEBYP_ENABLE -#define STM32_HSI_FREQUENCY 8000000ul +#define STM32_HSI_FREQUENCY 16000000ul #define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */ #define STM32_HSE_FREQUENCY STM32_BOARD_XTAL #define STM32_LSE_FREQUENCY 32768 /* X2 on board */ -/* PLL source is HSE/1, PLL multipler is 8: PLL frequency is 8MHz (XTAL) x 8 = 64MHz */ +/* PLL source is HSI/1, PLL multipler is 4: PLL frequency is 16MHz (XTAL) x 4 = 64MHz */ -#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC +#define STM32_CFGR_PLLSRC 0 #define STM32_CFGR_PLLXTPRE 0 -#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx8 -#define STM32_PLL_FREQUENCY (8*STM32_BOARD_XTAL) +#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx4 +#define STM32_PLL_FREQUENCY (4*STM32_HSI_FREQUENCY) /* Use the PLL and set the SYSCLK source to be the PLL/2 (32MHz) */ @@ -228,7 +227,7 @@ /* SPI1 is connected to SX1276 radio */ #define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2 /* PA7 */ -#define GPIO_SPI1_MISO GPIO_SPI1_MOSI_2 /* PA6 */ +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_2 /* PA6 */ #define GPIO_SPI1_SCK GPIO_SPI1_SCK_2 /* PB3 */ #define GPIO_SPI1_NSS GPIO_SPI1_NSS_1 /* PA15 */ diff --git a/configs/b-l072z-lrwan1/src/stm32_sx127x.c b/configs/b-l072z-lrwan1/src/stm32_sx127x.c index 1ff39f48d6..0fd52ac08f 100644 --- a/configs/b-l072z-lrwan1/src/stm32_sx127x.c +++ b/configs/b-l072z-lrwan1/src/stm32_sx127x.c @@ -108,7 +108,7 @@ static void sx127x_chip_reset(void) /* Configure reset as output */ stm32_configgpio(GPIO_SX127X_RESET | GPIO_OUTPUT | GPIO_SPEED_HIGH | - GPIO_OUTPUT_SET); + GPIO_OUTPUT_CLEAR); /* Set pin to zero */ diff --git a/configs/nucleo-f091rc/include/board.h b/configs/nucleo-f091rc/include/board.h index a3e796aca1..02fea16229 100644 --- a/configs/nucleo-f091rc/include/board.h +++ b/configs/nucleo-f091rc/include/board.h @@ -228,6 +228,18 @@ #define BUTTON_USER_BIT (1 << BUTTON_USER) /* Alternate Pin Functions **********************************************************/ + +/* I2C */ + +#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 /* D15 - PB8 */ +#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* D14 - PB9 */ + +/* SPI */ + +#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* D12 - PA6 */ +#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1 /* D11 - PA7 */ +#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 /* D13 - PA5 */ + /* USART 1 */ #define GPIO_USART1_TX GPIO_USART1_TX_2 diff --git a/configs/nucleo-f091rc/src/Makefile b/configs/nucleo-f091rc/src/Makefile index 03c9119f06..31f84b485a 100644 --- a/configs/nucleo-f091rc/src/Makefile +++ b/configs/nucleo-f091rc/src/Makefile @@ -49,8 +49,16 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif +ifeq ($(CONFIG_STM32F0L0_SPI),y) +CSRCS += stm32_spi.c +endif + ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += stm32_appinit.c endif +ifeq ($(CONFIG_LPWAN_SX127X),y) +CSRCS += stm32_sx127x.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/nucleo-f091rc/src/nucleo-f091rc.h b/configs/nucleo-f091rc/src/nucleo-f091rc.h index c96012ae29..0b261515dd 100644 --- a/configs/nucleo-f091rc/src/nucleo-f091rc.h +++ b/configs/nucleo-f091rc/src/nucleo-f091rc.h @@ -89,6 +89,18 @@ #define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \ GPIO_PORTC | GPIO_PIN13) +/* Dragino LORA shield (v1.4) - RF98 module (based on SX127X) + * RESET - PC7 (D9) + * CS - PB6 (D10) + * DIO0 - PA10 (D2) + */ + +#define GPIO_SX127X_RESET (GPIO_PORTC | GPIO_PIN7) +#define GPIO_SX127X_CS (GPIO_OUTPUT | GPIO_SPEED_HIGH | \ + GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6) +#define GPIO_SX127X_DIO0 (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \ + GPIO_PORTA | GPIO_PIN10) + /**************************************************************************** * Public Types ****************************************************************************/ @@ -119,5 +131,28 @@ int stm32_bringup(void); +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-H743ZI board. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F0L0_SPI +void stm32_spidev_initialize(void); +#endif + +/***************************************************************************** + * Name: stm32_lpwaninitialize + * + * Description: + * Initialize SX127X LPWAN interaface. + ****************************************************************************/ + +#ifdef CONFIG_LPWAN_SX127X +int stm32_lpwaninitialize(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_NUCLEO_F091RC_SRC_NUCLEO_F091RC_H */ diff --git a/configs/nucleo-f091rc/src/stm32_boot.c b/configs/nucleo-f091rc/src/stm32_boot.c index b1f7cb9151..b0a730949b 100644 --- a/configs/nucleo-f091rc/src/stm32_boot.c +++ b/configs/nucleo-f091rc/src/stm32_boot.c @@ -69,6 +69,12 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif + +#ifdef CONFIG_STM32F0L0_SPI + /* Configure SPI chip selects */ + + stm32_spidev_initialize(); +#endif } /**************************************************************************** diff --git a/configs/nucleo-f091rc/src/stm32_bringup.c b/configs/nucleo-f091rc/src/stm32_bringup.c index bae9f6aa2c..9c787ece4f 100644 --- a/configs/nucleo-f091rc/src/stm32_bringup.c +++ b/configs/nucleo-f091rc/src/stm32_bringup.c @@ -77,6 +77,14 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_LPWAN_SX127X + ret = stm32_lpwaninitialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", ret); + } +#endif /* CONFIG_LPWAN_SX127X */ + UNUSED(ret); return OK; } diff --git a/configs/nucleo-f091rc/src/stm32_spi.c b/configs/nucleo-f091rc/src/stm32_spi.c new file mode 100644 index 0000000000..cbfac40aa2 --- /dev/null +++ b/configs/nucleo-f091rc/src/stm32_spi.c @@ -0,0 +1,196 @@ +/**************************************************************************** + * configs/nucleo-f091rc/src/stm32_spi.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Author: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_spi.h" + +#include "nucleo-f091rc.h" +#include + +#ifdef CONFIG_STM32F0L0_SPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. + * + ****************************************************************************/ + +void stm32_spidev_initialize(void) +{ + /* NOTE: Clocking for SPI1 and/or SPI3 was already provided in stm32_rcc.c. + * Configurations of SPI pins is performed in stm32_spi.c. + * Here, we only initialize chip select pins unique to the board + * architecture. + */ + +#ifdef CONFIG_STM32F0L0_SPI1 + +# ifdef CONFIG_LPWAN_SX127X + /* Configure the SPI-based SX127X chip select GPIO */ + + spiinfo("Configure GPIO for SX127X SPI1/CS\n"); + + stm32_configgpio(GPIO_SX127X_CS); + stm32_gpiowrite(GPIO_SX127X_CS, true); +# endif + +#endif /* CONFIG_STM32F0L0_SPI1 */ +} + +/**************************************************************************** + * Name: stm32_spi1/2/select and stm32_spi1/2/status + * + * Description: + * The external functions, stm32_spi1/2select and stm32_spi1/2status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. To use this + * common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level application + * initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to bind + * the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F0L0_SPI1 +void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + + switch (devid) + { +#ifdef CONFIG_LPWAN_SX127X + case SPIDEV_LPWAN(0): + { + spiinfo("SX127X device %s\n", selected ? "asserted" : "de-asserted"); + + /* Set the GPIO low to select and high to de-select */ + + stm32_gpiowrite(GPIO_SX127X_CS, !selected); + break; + } +#endif + default: + { + break; + } + } +} + +uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + + switch (devid) + { +#ifdef CONFIG_LPWAN_SX127X + case SPIDEV_LPWAN(0): + { + status |= SPI_STATUS_PRESENT; + break; + } +#endif + default: + { + break; + } + } + + return status; +} +#endif /* CONFIG_STM32F0L0_SPI1 */ + +#ifdef CONFIG_STM32F0L0_SPI2 +void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif /* CONFIG_STM32F0L0_SPI2 */ + +#endif diff --git a/configs/nucleo-f091rc/src/stm32_sx127x.c b/configs/nucleo-f091rc/src/stm32_sx127x.c new file mode 100644 index 0000000000..459f5a3047 --- /dev/null +++ b/configs/nucleo-f091rc/src/stm32_sx127x.c @@ -0,0 +1,159 @@ +/**************************************************************************** + * configs/nucleo-f091rc/src/stm32_sx127x.c + * + * Copyright (C) 2019 Gregory Nutt. All rights reserved. + * Authors: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_exti.h" +#include "stm32_spi.h" + +#include "nucleo-f091rc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SX127X on SPI1 bus */ + +#define SX127X_SPI 1 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void sx127x_chip_reset(void); +static int sx127x_irq0_attach(xcpt_t isr, FAR void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct sx127x_lower_s lower = +{ + .irq0attach = sx127x_irq0_attach, + .reset = sx127x_chip_reset +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int sx127x_irq0_attach(xcpt_t isr, FAR void *arg) +{ + wlinfo("Attach DIO0 IRQ\n"); + + /* IRQ on rising edge */ + + (void)stm32_gpiosetevent(GPIO_SX127X_DIO0, true, false, false, isr, arg); + return OK; +} + +static void sx127x_chip_reset(void) +{ + wlinfo("SX127X RESET\n"); + + /* Configure reset as output */ + + stm32_configgpio(GPIO_SX127X_RESET | GPIO_OUTPUT | GPIO_SPEED_HIGH | + GPIO_OUTPUT_CLEAR); + + /* Set pin to zero */ + + stm32_gpiowrite(GPIO_SX127X_RESET, false); + + /* Wait 1 ms */ + + usleep(1000); + + /* Configure reset as input */ + + stm32_configgpio(GPIO_SX127X_RESET | GPIO_INPUT | GPIO_FLOAT); + + /* Wait 10 ms */ + + usleep(10000); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_lpwaninitialize(void) +{ + FAR struct spi_dev_s *spidev; + int ret = OK; + + wlinfo("Register the sx127x module\n"); + + /* Setup DIO0 */ + + stm32_configgpio(GPIO_SX127X_DIO0); + + /* Init SPI bus */ + + spidev = stm32_spibus_initialize(SX127X_SPI); + if (!spidev) + { + wlerr("ERROR: Failed to initialize SPI %d bus\n", SX127X_SPI); + ret = -ENODEV; + goto errout; + } + + /* Initialize SX127X */ + + ret = sx127x_register(spidev, &lower); + if (ret < 0) + { + wlerr("ERROR: Failed to register sx127x\n"); + goto errout; + } + +errout: + return ret; +} diff --git a/configs/nucleo-l073rz/src/nucleo-l073rz.h b/configs/nucleo-l073rz/src/nucleo-l073rz.h index 13ec9ba61b..f042b32d8c 100644 --- a/configs/nucleo-l073rz/src/nucleo-l073rz.h +++ b/configs/nucleo-l073rz/src/nucleo-l073rz.h @@ -100,8 +100,8 @@ #define GPIO_NRF24L01_IRQ (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTC | GPIO_PIN7) /* Dragino LORA shield (v1.4) - RF98 module (based on SX127X) - * RESET - PC7 (PD9) - * CS - PB6 (PD10) + * RESET - PC7 (D9) + * CS - PB6 (D10) * DIO0 - PA10 (D2) */ diff --git a/configs/nucleo-l073rz/src/stm32_boot.c b/configs/nucleo-l073rz/src/stm32_boot.c index cb69d7a886..f53c620588 100644 --- a/configs/nucleo-l073rz/src/stm32_boot.c +++ b/configs/nucleo-l073rz/src/stm32_boot.c @@ -77,7 +77,6 @@ void stm32_boardinitialize(void) { - #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/configs/nucleo-l073rz/src/stm32_sx127x.c b/configs/nucleo-l073rz/src/stm32_sx127x.c index 4baf6f456a..f48b6149fb 100644 --- a/configs/nucleo-l073rz/src/stm32_sx127x.c +++ b/configs/nucleo-l073rz/src/stm32_sx127x.c @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/nucleo-l073rz/src/stm32_rfm9x.c + * configs/nucleo-l073rz/src/stm32_sx127x.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. * Authors: Mateusz Szafoni @@ -101,7 +101,7 @@ static void sx127x_chip_reset(void) /* Configure reset as output */ stm32_configgpio(GPIO_SX127X_RESET | GPIO_OUTPUT | GPIO_SPEED_HIGH | - GPIO_OUTPUT_SET); + GPIO_OUTPUT_CLEAR); /* Set pin to zero */ diff --git a/drivers/wireless/lpwan/sx127x/sx127x.c b/drivers/wireless/lpwan/sx127x/sx127x.c index c3d1770ab6..2ad0a6e41a 100644 --- a/drivers/wireless/lpwan/sx127x/sx127x.c +++ b/drivers/wireless/lpwan/sx127x/sx127x.c @@ -1505,6 +1505,15 @@ static void sx127x_isr0_process(FAR void *arg) FAR struct sx127x_dev_s *dev = (struct sx127x_dev_s *)arg; int ret = OK; + /* Return immediately if isr0_process is not initialized */ + + if (dev->ops.isr0_process == NULL) + { + return; + } + + /* isr0_process depends on the current modulation scheme */ + ret = dev->ops.isr0_process(dev); if (ret < 0) {