From 79cc12c034b18d05662f5fe9f4b1ec22e3fdf0f8 Mon Sep 17 00:00:00 2001 From: Abdelatif Guettouche Date: Tue, 17 Aug 2021 21:31:48 +0200 Subject: [PATCH] arch/xtesna/esp32: Merge the contents of esp32_cpuint and esp32_irq. They do the same thing (manipulate interrupts) keeping them separated was making things harder. Signed-off-by: Abdelatif Guettouche --- arch/xtensa/src/esp32/Make.defs | 4 +- arch/xtensa/src/esp32/esp32_cpuint.c | 627 --------------------- arch/xtensa/src/esp32/esp32_cpuint.h | 131 ----- arch/xtensa/src/esp32/esp32_cpustart.c | 4 +- arch/xtensa/src/esp32/esp32_emac.c | 2 +- arch/xtensa/src/esp32/esp32_gpio.c | 5 +- arch/xtensa/src/esp32/esp32_i2c.c | 2 +- arch/xtensa/src/esp32/esp32_intdecode.c | 2 +- arch/xtensa/src/esp32/esp32_irq.c | 500 +++++++++++++++- arch/xtensa/src/esp32/esp32_irq.h | 97 ++++ arch/xtensa/src/esp32/esp32_serial.c | 2 +- arch/xtensa/src/esp32/esp32_spi.c | 2 +- arch/xtensa/src/esp32/esp32_spi_slave.c | 2 +- arch/xtensa/src/esp32/esp32_tim.c | 3 +- arch/xtensa/src/esp32/esp32_wdt.c | 2 +- arch/xtensa/src/esp32/esp32_wifi_adapter.c | 2 +- 16 files changed, 615 insertions(+), 772 deletions(-) delete mode 100644 arch/xtensa/src/esp32/esp32_cpuint.c delete mode 100644 arch/xtensa/src/esp32/esp32_cpuint.h diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index fafe727bdf..7d6a681e5e 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -69,8 +69,8 @@ endif # Required ESP32 files (arch/xtensa/src/lx6) -CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_cpuint.c -CHIP_CSRCS += esp32_gpio.c esp32_intdecode.c esp32_irq.c esp32_region.c +CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_gpio.c +CHIP_CSRCS += esp32_intdecode.c esp32_irq.c esp32_region.c CHIP_CSRCS += esp32_user.c CHIP_CSRCS += esp32_dma.c diff --git a/arch/xtensa/src/esp32/esp32_cpuint.c b/arch/xtensa/src/esp32/esp32_cpuint.c deleted file mode 100644 index 398ff4740b..0000000000 --- a/arch/xtensa/src/esp32/esp32_cpuint.c +++ /dev/null @@ -1,627 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_cpuint.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "xtensa.h" - -#include "hardware/esp32_dport.h" - -#include "esp32_irq.h" - -#include "esp32_cpuint.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Mapping Peripheral IDs to map register addresses - * - * PERIPHERAL ID DPORT REGISTER OFFSET - * MNEMONIC VAL PRO CPU APP CPU - * -------------------------- --- ------- ------- - * ESP32_PERIPH_MAC 0 0x104 0x218 - * ESP32_PERIPH_MAC_NMI 1 0x108 0x21c - * ESP32_PERIPH_BB 2 0x10c 0x220 - * ESP32_PERIPH_BB_MAC 3 0x110 0x224 - * ESP32_PERIPH_BT_BB 4 0x114 0x228 - * ESP32_PERIPH_BT_BB_NMI 5 0x118 0x22c - * ESP32_PERIPH_RWBT_IRQ 6 0x11c 0x230 - * ESP32_PERIPH_RWBLE_IRQ 7 0x120 0x234 - * ESP32_PERIPH_RWBT_NMI 8 0x124 0x238 - * ESP32_PERIPH_RWBLE_NMI 9 0x128 0x23c - * ESP32_PERIPH_SLC0 10 0x12c 0x240 - * ESP32_PERIPH_SLC1 11 0x130 0x244 - * ESP32_PERIPH_UHCI0 12 0x134 0x248 - * ESP32_PERIPH_UHCI1 13 0x138 0x24c - * ESP32_PERIPH_TG_T0_LEVEL 14 0x13c 0x250 - * ESP32_PERIPH_TG_T1_LEVEL 15 0x140 0x254 - * ESP32_PERIPH_TG_WDT_LEVEL 16 0x144 0x258 - * ESP32_PERIPH_TG_LACT_LEVEL 17 0x148 0x25c - * ESP32_PERIPH_TG1_T0_LEVEL 18 0x14c 0x260 - * ESP32_PERIPH_TG1_T1_LEVEL 19 0x150 0x264 - * ESP32_PERIPH_TG1_WDT_LEVEL 20 0x154 0x268 - * ESP32_PERIPH_G1_LACT_LEVEL 21 0x158 0x26c - * ESP32_PERIPH_CPU_GPIO 22 0x15c 0x270 - * ESP32_PERIPH_CPU_NMI 23 0x160 0x274 - * ESP32_PERIPH_CPU_CPU0 24 0x164 0x278 - * ESP32_PERIPH_CPU_CPU1 25 0x168 0x27c - * ESP32_PERIPH_CPU_CPU2 26 0x16c 0x280 - * ESP32_PERIPH_CPU_CPU3 27 0x170 0x284 - * ESP32_PERIPH_SPI0 28 0x174 0x288 - * ESP32_PERIPH_SPI1 29 0x178 0x28c - * ESP32_PERIPH_SPI2 30 0x17c 0x290 - * ESP32_PERIPH_SPI3 31 0x180 0x294 - * ESP32_PERIPH_I2S0 32 0x184 0x298 - * ESP32_PERIPH_I2S1 33 0x188 0x29c - * ESP32_PERIPH_UART 34 0x18c 0x2a0 - * ESP32_PERIPH_UART1 35 0x190 0x2a4 - * ESP32_PERIPH_UART2 36 0x194 0x2a8 - * ESP32_PERIPH_SDIO_HOST 37 0x198 0x2ac - * ESP32_PERIPH_EMAC 38 0x19c 0x2b0 - * ESP32_PERIPH_PWM0 39 0x1a0 0x2b4 - * ESP32_PERIPH_PWM1 40 0x1a4 0x2b8 - * ESP32_PERIPH_PWM2 41 0x1a8 0x2bc - * ESP32_PERIPH_PWM3 42 0x1ac 0x2c0 - * ESP32_PERIPH_LEDC 43 0x1b0 0x2c4 - * ESP32_PERIPH_EFUSE 44 0x1b4 0x2c8 - * ESP32_PERIPH_CAN 45 0x1b8 0x2cc - * ESP32_PERIPH_RTC_CORE 46 0x1bc 0x2d0 - * ESP32_PERIPH_RMT 47 0x1c0 0x2d4 - * ESP32_PERIPH_PCNT 48 0x1c4 0x2d8 - * ESP32_PERIPH_I2C_EXT0 49 0x1c8 0x2dc - * ESP32_PERIPH_I2C_EXT1 50 0x1cc 0x2e0 - * ESP32_PERIPH_RSA 51 0x1d0 0x2e4 - * ESP32_PERIPH_SPI1_DMA 52 0x1d4 0x2e8 - * ESP32_PERIPH_SPI2_DMA 53 0x1d8 0x2ec - * ESP32_PERIPH_SPI3_DMA 54 0x1dc 0x2f0 - * ESP32_PERIPH_WDG 55 0x1e0 0x2f4 - * ESP32_PERIPH_TIMER1 56 0x1e4 0x2f8 - * ESP32_PERIPH_TIMER2 57 0x1e8 0x2fc - * ESP32_PERIPH_TG_T0_EDGE 58 0x1ec 0x300 - * ESP32_PERIPH_TG_T1_EDGE 59 0x1f0 0x304 - * ESP32_PERIPH_TG_WDT_EDGE 60 0x1F4 0x308 - * ESP32_PERIPH_TG_LACT_EDGE 61 0x1F8 0x30c - * ESP32_PERIPH_TG1_T0_EDGE 62 0x1fc 0x310 - * ESP32_PERIPH_TG1_T1_EDGE 63 0x200 0x314 - * ESP32_PERIPH_TG1_WDT_EDGE 64 0x204 0x318 - * ESP32_PERIPH_TG1_LACT_EDGE 65 0x208 0x31c - * ESP32_PERIPH_MMU_IA 66 0x20c 0x320 - * ESP32_PERIPH_MPU_IA 67 0x210 0x324 - * ESP32_PERIPH_CACHE_IA 68 0x214 0x328 - */ - -#define DPORT_PRO_MAP_REGADDR(n) (DR_REG_DPORT_BASE + 0x104 + ((n) << 2)) -#define DPORT_APP_MAP_REGADDR(n) (DR_REG_DPORT_BASE + 0x218 + ((n) << 2)) - -/* CPU interrupts can be detached from any peripheral source by setting the - * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29). - */ - -#define NO_CPUINT ESP32_CPUINT_TIMER0 - -/* Priority range is 1-5 */ - -#define ESP32_MIN_PRIORITY 1 -#define ESP32_MAX_PRIORITY 5 -#define ESP32_PRIO_INDEX(p) ((p) - ESP32_MIN_PRIORITY) - -#ifdef CONFIG_ESP32_WIRELESS -# define ESP32_WIRELESS_RESERVE_INT (1 << ESP32_CPUINT_MAC) -#else -# define ESP32_WIRELESS_RESERVE_INT 0 -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ - -uint8_t g_cpu0_intmap[ESP32_NCPUINTS]; -#ifdef CONFIG_SMP -uint8_t g_cpu1_intmap[ESP32_NCPUINTS]; -#endif - -/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register - * content. - */ - -#ifdef CONFIG_SMP -uint32_t g_intenable[CONFIG_SMP_NCPUS]; -#else -uint32_t g_intenable[1]; -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Bitsets for free, unallocated CPU interrupts available to peripheral - * devices. - */ - -static uint32_t g_cpu0_freeints = ESP32_CPUINT_PERIPHSET & - (~ESP32_WIRELESS_RESERVE_INT); -#ifdef CONFIG_SMP -static uint32_t g_cpu1_freeints = ESP32_CPUINT_PERIPHSET & - (~ESP32_WIRELESS_RESERVE_INT); -#endif - -/* Bitsets for each interrupt priority 1-5 */ - -static const uint32_t g_priority[5] = -{ - ESP32_INTPRI1_MASK, - ESP32_INTPRI2_MASK, - ESP32_INTPRI3_MASK, - ESP32_INTPRI4_MASK, - ESP32_INTPRI5_MASK -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: xtensa_disable_all - ****************************************************************************/ - -static inline void xtensa_disable_all(void) -{ - __asm__ __volatile__ - ( - "movi a2, 0\n" - "xsr a2, INTENABLE\n" - : : : "a2" - ); -} - -/**************************************************************************** - * Name: esp32_intinfo - * - * Description: - * Return the CPU interrupt map of the given CPU and the register map - * of the given peripheral. - * - ****************************************************************************/ - -static void esp32_intinfo(int cpu, int periphid, - uintptr_t *regaddr, uint8_t **intmap) -{ -#ifdef CONFIG_SMP - DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); - - if (cpu != 0) - { - *regaddr = DPORT_APP_MAP_REGADDR(periphid); - *intmap = g_cpu1_intmap; - } - else -#endif - { - *regaddr = DPORT_PRO_MAP_REGADDR(periphid); - *intmap = g_cpu0_intmap; - } -} - -/**************************************************************************** - * Name: esp32_getcpuint - * - * Description: - * Get a free CPU interrupt for a peripheral device. This function will - * not ignore all of the pre-allocated CPU interrupts for internal - * devices. - * - * Input Parameters: - * intmask - mask of candidate CPU interrupts. The CPU interrupt will be - * be allocated from free interrupts within this set - * - * Returned Value: - * On success, a CPU interrupt number is returned. - * A negated errno is returned on failure. - * - ****************************************************************************/ - -static int esp32_getcpuint(uint32_t intmask) -{ - uint32_t *freeints; - uint32_t bitmask; - uint32_t intset; - int cpuint; - int ret = -ENOMEM; - int cpu = 0; - - /* Check if there are CPU interrupts with the requested properties - * available. - */ - - cpu = up_cpu_index(); -#ifdef CONFIG_SMP - if (cpu != 0) - { - freeints = &g_cpu1_freeints; - } - else -#endif - { - freeints = &g_cpu0_freeints; - } - - intset = *freeints & intmask; - if (intset != 0) - { - /* Skip over initial unavailable CPU interrupts quickly in groups - * of 8 interrupt. - */ - - for (cpuint = 0, bitmask = 0xff; - cpuint <= ESP32_CPUINT_MAX && (intset & bitmask) == 0; - cpuint += 8, bitmask <<= 8); - - /* Search for an unallocated CPU interrupt number in the remaining - * intset. - */ - - for (; cpuint <= ESP32_CPUINT_MAX; cpuint++) - { - /* If the bit corresponding to the CPU interrupt is '1', then - * that CPU interrupt is available. - */ - - bitmask = (1ul << cpuint); - if ((intset & bitmask) != 0) - { - /* Got it! */ - - *freeints &= ~bitmask; - ret = cpuint; - break; - } - } - } - - /* Make sure the CPU interrupt is disabled. */ - - if (ret >= 0) - { - xtensa_disable_cpuint(&g_intenable[cpu], (1ul << ret)); - } - - return ret; -} - -/**************************************************************************** - * Name: esp32_alloc_cpuint - * - * Description: - * Allocate a level CPU interrupt - * - * Input Parameters: - * priority - Priority of the CPU interrupt (1-5) - * type - Interrupt type (level or edge). - * - * Returned Value: - * On success, the allocated CPU interrupt number is returned. - * A negated errno is returned on failure. The only possible failure - * is that all CPU interrupts of the requested type have already been - * allocated. - * - ****************************************************************************/ - -static int esp32_alloc_cpuint(int priority, int type) -{ - uint32_t mask; - - DEBUGASSERT(priority >= ESP32_MIN_PRIORITY && - priority <= ESP32_MAX_PRIORITY); - DEBUGASSERT(type == ESP32_CPUINT_LEVEL || - type == ESP32_CPUINT_EDGE); - - if (type == ESP32_CPUINT_LEVEL) - { - /* Check if there are any level CPU interrupts available at the - * requested interrupt priority. - */ - - mask = g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_CPUINT_LEVELSET; - } - else - { - /* Check if there are any edge CPU interrupts available at the - * requested interrupt priority. - */ - - mask = g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_CPUINT_EDGESET; - } - - return esp32_getcpuint(mask); -} - -/**************************************************************************** - * Name: esp32_free_cpuint - * - * Description: - * Free a previously allocated CPU interrupt - * - * Input Parameters: - * The CPU interrupt number to be freed - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32_free_cpuint(int cpuint) -{ - uint32_t *freeints; - uint32_t bitmask; - - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX); - - /* Mark the CPU interrupt as available */ - - bitmask = (1ul << cpuint); - -#ifdef CONFIG_SMP - if (up_cpu_index() != 0) - { - freeints = &g_cpu1_freeints; - } - else -#endif - { - freeints = &g_cpu0_freeints; - } - - DEBUGASSERT((*freeints & bitmask) == 0); - *freeints |= bitmask; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_cpuint_initialize - * - * Description: - * Initialize CPU interrupts - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp32_cpuint_initialize(void) -{ - uintptr_t regaddr; - uint8_t *intmap; -#ifdef CONFIG_SMP - int cpu; -#endif - int i; - -#ifdef CONFIG_SMP - /* Which CPU are we initializing */ - - cpu = up_cpu_index(); - DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); -#endif - - /* Disable all CPU interrupts on this CPU */ - - xtensa_disable_all(); - - /* Detach all peripheral sources PRO CPU interrupts */ - - for (i = 0; i < ESP32_NPERIPHERALS; i++) - { -#ifdef CONFIG_SMP - if (cpu != 0) - { - regaddr = DPORT_APP_MAP_REGADDR(i); - } - else -#endif - { - regaddr = DPORT_PRO_MAP_REGADDR(i); - } - - putreg32(NO_CPUINT, regaddr); - } - - /* Initialize CPU interrupt-to-IRQ mapping table */ - -#ifdef CONFIG_SMP - if (cpu != 0) - { - intmap = g_cpu1_intmap; - } - else -#endif - { - intmap = g_cpu0_intmap; - } - - /* Indicate that no peripheral interrupts are assigned to CPU interrupts */ - - memset(intmap, CPUINT_UNASSIGNED, ESP32_NCPUINTS); - - /* Special case the 6 internal interrupts. - * - * CPU interrupt bit IRQ number - * --------------------------- --------------------- - * ESP32_CPUINT_MAC 0 ESP32_IRQ_MAC 4 - * ESP32_CPUINT_TIMER0 6 XTENSA_IRQ_TIMER0 0 - * ESP32_CPUINT_SOFTWARE0 7 Not yet defined - * ESP32_CPUINT_PROFILING 11 Not yet defined - * ESP32_CPUINT_TIMER1 15 XTENSA_IRQ_TIMER1 1 - * ESP32_CPUINT_TIMER2 16 XTENSA_IRQ_TIMER2 2 - * ESP32_CPUINT_SOFTWARE1 29 Not yet defined - */ - - intmap[ESP32_CPUINT_TIMER0] = XTENSA_IRQ_TIMER0; - intmap[ESP32_CPUINT_TIMER1] = XTENSA_IRQ_TIMER1; - intmap[ESP32_CPUINT_TIMER2] = XTENSA_IRQ_TIMER2; - - /* Reserve CPU interrupt for some special drivers */ - -#ifdef CONFIG_ESP32_WIRELESS - intmap[ESP32_CPUINT_MAC] = ESP32_IRQ_MAC; -#endif - - return OK; -} - -/**************************************************************************** - * Name: esp32_setup_irq - * - * Description: - * This function sets up the IRQ. It allocates a CPU interrupt of the given - * priority and type and attaches it to the given peripheral. - * - * Input Parameters: - * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from irq.h to be assigned to - * a CPU interrupt. - * priority - Interrupt's priority (1 - 5). - * type - Interrupt's type (level or edge). - * - * Returned Value: - * The allocated CPU interrupt on success, a negated errno value on - * failure. - * - ****************************************************************************/ - -int esp32_setup_irq(int cpu, int periphid, int priority, int type) -{ - irqstate_t irqstate; - uintptr_t regaddr; - uint8_t *intmap; - int irq; - int cpuint; - - irqstate = enter_critical_section(); - - /* Setting up an IRQ includes the following steps: - * 1. Allocate a CPU interrupt. - * 2. Attach that CPU interrup to the peripheral. - * 3. Map the CPU interrupt to the IRQ to ease searching later. - */ - - cpuint = esp32_alloc_cpuint(priority, type); - if (cpuint < 0) - { - irqerr("Unable to allocate CPU interrupt for priority=%d and type=%d", - priority, type); - leave_critical_section(irqstate); - - return cpuint; - } - - irq = ESP32_PERIPH2IRQ(periphid); - - DEBUGASSERT(periphid >= 0 && periphid < ESP32_NPERIPHERALS); - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX); - - esp32_intinfo(cpu, periphid, ®addr, &intmap); - - DEBUGASSERT(intmap[cpuint] == CPUINT_UNASSIGNED); - - intmap[cpuint] = periphid + XTENSA_IRQ_FIRSTPERIPH; - esp32_mapirq(irq, cpu, cpuint); - - putreg32(cpuint, regaddr); - - leave_critical_section(irqstate); - - return cpuint; -} - -/**************************************************************************** - * Name: esp32_teardown_irq - * - * Description: - * This function undoes the operations done by esp32_setup_irq. - * It detaches a peripheral interrupt from a CPU interrupt and frees the - * CPU interrupt. - * - * Input Parameters: - * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from irq.h to be detached from the - * CPU interrupt. - * cpuint - The CPU interrupt from which the peripheral interrupt will - * be detached. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_teardown_irq(int cpu, int periphid, int cpuint) -{ - irqstate_t irqstate; - uintptr_t regaddr; - uint8_t *intmap; - int irq; - - irqstate = enter_critical_section(); - - /* Tearing down an IRQ includes the following steps: - * 1. Free the previously allocated CPU interrupt. - * 2. Detach the interrupt from the peripheral. - * 3. Unmap the IRQ from the IRQ-to-cpuint map. - */ - - esp32_free_cpuint(cpuint); - - irq = ESP32_PERIPH2IRQ(periphid); - - DEBUGASSERT(periphid >= 0 && periphid < ESP32_NPERIPHERALS); - - esp32_intinfo(cpu, periphid, ®addr, &intmap); - - DEBUGASSERT(intmap[cpuint] != CPUINT_UNASSIGNED); - intmap[cpuint] = CPUINT_UNASSIGNED; - esp32_unmapirq(irq); - - putreg32(NO_CPUINT, regaddr); - - leave_critical_section(irqstate); -} diff --git a/arch/xtensa/src/esp32/esp32_cpuint.h b/arch/xtensa/src/esp32/esp32_cpuint.h deleted file mode 100644 index cc6a2c6318..0000000000 --- a/arch/xtensa/src/esp32/esp32_cpuint.h +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_cpuint.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_CPUINT_H -#define __ARCH_XTENSA_SRC_ESP32_ESP32_CPUINT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* No peripheral assigned to this CPU interrupt */ - -#define CPUINT_UNASSIGNED 0xff - -/* CPU interrupt types. */ - -#define ESP32_CPUINT_LEVEL 0 -#define ESP32_CPUINT_EDGE 1 - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ - -extern uint8_t g_cpu0_intmap[ESP32_NCPUINTS]; -#ifdef CONFIG_SMP -extern uint8_t g_cpu1_intmap[ESP32_NCPUINTS]; -#endif - -/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register - * content. - */ - -#ifdef CONFIG_SMP -extern uint32_t g_intenable[CONFIG_SMP_NCPUS]; -#else -extern uint32_t g_intenable[1]; -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_cpuint_initialize - * - * Description: - * Initialize CPU interrupts - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp32_cpuint_initialize(void); - -/**************************************************************************** - * Name: esp32_setup_irq - * - * Description: - * This function sets up the IRQ. It allocates a CPU interrupt of the given - * priority and type and attaches it to the given peripheral. - * - * Input Parameters: - * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from irq.h to be assigned to - * a CPU interrupt. - * priority - Interrupt's priority (1 - 5). - * type - Interrupt's type (level or edge). - * - * Returned Value: - * The allocated CPU interrupt on success, a negated errno value on - * failure. - * - ****************************************************************************/ - -int esp32_setup_irq(int cpu, int periphid, int priority, int type); - -/**************************************************************************** - * Name: esp32_teardown_irq - * - * Description: - * This function undoes the operations done by esp32_setup_irq. - * It detaches a peripheral interrupt from a CPU interrupt and frees the - * CPU interrupt. - * - * Input Parameters: - * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from irq.h to be detached from the - * CPU interrupt. - * cpuint - The CPU interrupt from which the peripheral interrupt will - * be detached. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_teardown_irq(int cpu, int periphid, int cpuint); - -#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CPUINT_H */ diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 09d52b45ff..ccef8e1079 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -37,10 +37,12 @@ #include "sched/sched.h" #include "xtensa.h" + #include "hardware/esp32_dport.h" #include "hardware/esp32_rtccntl.h" + #include "esp32_region.h" -#include "esp32_cpuint.h" +#include "esp32_irq.h" #include "esp32_smp.h" #ifdef CONFIG_SMP diff --git a/arch/xtensa/src/esp32/esp32_emac.c b/arch/xtensa/src/esp32/esp32_emac.c index 4c1a92f7c6..9ab447c7f0 100644 --- a/arch/xtensa/src/esp32/esp32_emac.c +++ b/arch/xtensa/src/esp32/esp32_emac.c @@ -61,7 +61,7 @@ #include "hardware/esp32_dport.h" #include "hardware/esp32_emac.h" #include "esp32_gpio.h" -#include "esp32_cpuint.h" +#include "esp32_irq.h" #include diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c index f53c63353f..c3f4f9ef4f 100644 --- a/arch/xtensa/src/esp32/esp32_gpio.c +++ b/arch/xtensa/src/esp32/esp32_gpio.c @@ -34,10 +34,13 @@ #include #include "xtensa.h" + #include "hardware/esp32_iomux.h" #include "hardware/esp32_gpio.h" -#include "esp32_cpuint.h" + +#include "esp32_irq.h" #include "esp32_rtc_gpio.h" + #include "esp32_gpio.h" /**************************************************************************** diff --git a/arch/xtensa/src/esp32/esp32_i2c.c b/arch/xtensa/src/esp32/esp32_i2c.c index 8077936486..0353862b06 100644 --- a/arch/xtensa/src/esp32/esp32_i2c.c +++ b/arch/xtensa/src/esp32/esp32_i2c.c @@ -47,7 +47,7 @@ #include "esp32_i2c.h" #include "esp32_gpio.h" -#include "esp32_cpuint.h" +#include "esp32_irq.h" #include "xtensa.h" #include "hardware/esp32_gpio_sigmap.h" diff --git a/arch/xtensa/src/esp32/esp32_intdecode.c b/arch/xtensa/src/esp32/esp32_intdecode.c index 36dcc4c044..1bdfc6d9f7 100644 --- a/arch/xtensa/src/esp32/esp32_intdecode.c +++ b/arch/xtensa/src/esp32/esp32_intdecode.c @@ -31,7 +31,7 @@ #include #include "xtensa.h" -#include "esp32_cpuint.h" +#include "esp32_irq.h" /**************************************************************************** * Private Functions diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 933d92f16a..a0b873f779 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -25,7 +25,9 @@ #include #include +#include #include +#include #include #include @@ -34,7 +36,8 @@ #include "xtensa.h" -#include "esp32_cpuint.h" +#include "hardware/esp32_dport.h" + #include "esp32_smp.h" #include "esp32_gpio.h" @@ -55,6 +58,29 @@ #define IRQ_GETCPUINT(m) ((m) & 0x7f) #define IRQ_MKMAP(c, i) (((c) << 0x07) | (i)) +/* Mapping Peripheral IDs to map register addresses. */ + +#define DPORT_PRO_MAP_REGADDR(n) (DR_REG_DPORT_BASE + 0x104 + ((n) << 2)) +#define DPORT_APP_MAP_REGADDR(n) (DR_REG_DPORT_BASE + 0x218 + ((n) << 2)) + +/* CPU interrupts can be detached from any peripheral source by setting the + * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29). + */ + +#define NO_CPUINT ESP32_CPUINT_TIMER0 + +/* Priority range is 1-5 */ + +#define ESP32_MIN_PRIORITY 1 +#define ESP32_MAX_PRIORITY 5 +#define ESP32_PRIO_INDEX(p) ((p) - ESP32_MIN_PRIORITY) + +#ifdef CONFIG_ESP32_WIRELESS +# define ESP32_WIRELESS_RESERVE_INT (1 << ESP32_CPUINT_MAC) +#else +# define ESP32_WIRELESS_RESERVE_INT 0 +#endif + /**************************************************************************** * Public Data ****************************************************************************/ @@ -98,6 +124,49 @@ uintptr_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] = static volatile uint8_t g_irqmap[NR_IRQS]; +/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ + +uint8_t g_cpu0_intmap[ESP32_NCPUINTS]; +#ifdef CONFIG_SMP +uint8_t g_cpu1_intmap[ESP32_NCPUINTS]; +#endif + +/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register + * content. + */ + +#ifdef CONFIG_SMP +uint32_t g_intenable[CONFIG_SMP_NCPUS]; +#else +uint32_t g_intenable[1]; +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Bitsets for free, unallocated CPU interrupts available to peripheral + * devices. + */ + +static uint32_t g_cpu0_freeints = ESP32_CPUINT_PERIPHSET & + (~ESP32_WIRELESS_RESERVE_INT); +#ifdef CONFIG_SMP +static uint32_t g_cpu1_freeints = ESP32_CPUINT_PERIPHSET & + (~ESP32_WIRELESS_RESERVE_INT); +#endif + +/* Bitsets for each interrupt priority 1-5 */ + +static const uint32_t g_priority[5] = +{ + ESP32_INTPRI1_MASK, + ESP32_INTPRI2_MASK, + ESP32_INTPRI3_MASK, + ESP32_INTPRI4_MASK, + ESP32_INTPRI5_MASK +}; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -147,6 +216,221 @@ static inline void xtensa_attach_fromcpu1_interrupt(void) } #endif +/**************************************************************************** + * Name: xtensa_disable_all + ****************************************************************************/ + +static inline void xtensa_disable_all(void) +{ + __asm__ __volatile__ + ( + "movi a2, 0\n" + "xsr a2, INTENABLE\n" + : : : "a2" + ); +} + +/**************************************************************************** + * Name: esp32_intinfo + * + * Description: + * Return the CPU interrupt map of the given CPU and the register map + * of the given peripheral. + * + ****************************************************************************/ + +static void esp32_intinfo(int cpu, int periphid, + uintptr_t *regaddr, uint8_t **intmap) +{ +#ifdef CONFIG_SMP + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); + + if (cpu != 0) + { + *regaddr = DPORT_APP_MAP_REGADDR(periphid); + *intmap = g_cpu1_intmap; + } + else +#endif + { + *regaddr = DPORT_PRO_MAP_REGADDR(periphid); + *intmap = g_cpu0_intmap; + } +} + +/**************************************************************************** + * Name: esp32_getcpuint + * + * Description: + * Get a free CPU interrupt for a peripheral device. This function will + * not ignore all of the pre-allocated CPU interrupts for internal + * devices. + * + * Input Parameters: + * intmask - mask of candidate CPU interrupts. The CPU interrupt will be + * be allocated from free interrupts within this set + * + * Returned Value: + * On success, a CPU interrupt number is returned. + * A negated errno is returned on failure. + * + ****************************************************************************/ + +static int esp32_getcpuint(uint32_t intmask) +{ + uint32_t *freeints; + uint32_t bitmask; + uint32_t intset; + int cpuint; + int ret = -ENOMEM; + int cpu = 0; + + /* Check if there are CPU interrupts with the requested properties + * available. + */ + + cpu = up_cpu_index(); +#ifdef CONFIG_SMP + if (cpu != 0) + { + freeints = &g_cpu1_freeints; + } + else +#endif + { + freeints = &g_cpu0_freeints; + } + + intset = *freeints & intmask; + if (intset != 0) + { + /* Skip over initial unavailable CPU interrupts quickly in groups + * of 8 interrupt. + */ + + for (cpuint = 0, bitmask = 0xff; + cpuint <= ESP32_CPUINT_MAX && (intset & bitmask) == 0; + cpuint += 8, bitmask <<= 8); + + /* Search for an unallocated CPU interrupt number in the remaining + * intset. + */ + + for (; cpuint <= ESP32_CPUINT_MAX; cpuint++) + { + /* If the bit corresponding to the CPU interrupt is '1', then + * that CPU interrupt is available. + */ + + bitmask = (1ul << cpuint); + if ((intset & bitmask) != 0) + { + /* Got it! */ + + *freeints &= ~bitmask; + ret = cpuint; + break; + } + } + } + + /* Make sure the CPU interrupt is disabled. */ + + if (ret >= 0) + { + xtensa_disable_cpuint(&g_intenable[cpu], (1ul << ret)); + } + + return ret; +} + +/**************************************************************************** + * Name: esp32_alloc_cpuint + * + * Description: + * Allocate a level CPU interrupt + * + * Input Parameters: + * priority - Priority of the CPU interrupt (1-5) + * type - Interrupt type (level or edge). + * + * Returned Value: + * On success, the allocated CPU interrupt number is returned. + * A negated errno is returned on failure. The only possible failure + * is that all CPU interrupts of the requested type have already been + * allocated. + * + ****************************************************************************/ + +static int esp32_alloc_cpuint(int priority, int type) +{ + uint32_t mask; + + DEBUGASSERT(priority >= ESP32_MIN_PRIORITY && + priority <= ESP32_MAX_PRIORITY); + DEBUGASSERT(type == ESP32_CPUINT_LEVEL || + type == ESP32_CPUINT_EDGE); + + if (type == ESP32_CPUINT_LEVEL) + { + /* Check if there are any level CPU interrupts available at the + * requested interrupt priority. + */ + + mask = g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_CPUINT_LEVELSET; + } + else + { + /* Check if there are any edge CPU interrupts available at the + * requested interrupt priority. + */ + + mask = g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_CPUINT_EDGESET; + } + + return esp32_getcpuint(mask); +} + +/**************************************************************************** + * Name: esp32_free_cpuint + * + * Description: + * Free a previously allocated CPU interrupt + * + * Input Parameters: + * The CPU interrupt number to be freed + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32_free_cpuint(int cpuint) +{ + uint32_t *freeints; + uint32_t bitmask; + + DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX); + + /* Mark the CPU interrupt as available */ + + bitmask = (1ul << cpuint); + +#ifdef CONFIG_SMP + if (up_cpu_index() != 0) + { + freeints = &g_cpu1_freeints; + } + else +#endif + { + freeints = &g_cpu0_freeints; + } + + DEBUGASSERT((*freeints & bitmask) == 0); + *freeints |= bitmask; +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -330,3 +614,217 @@ uintptr_t xtensa_intstack_alloc(void) return g_cpu_intstack_top[up_cpu_index()] - INTSTACK_SIZE; } #endif + +/**************************************************************************** + * Name: esp32_cpuint_initialize + * + * Description: + * Initialize CPU interrupts + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp32_cpuint_initialize(void) +{ + uintptr_t regaddr; + uint8_t *intmap; +#ifdef CONFIG_SMP + int cpu; +#endif + int i; + +#ifdef CONFIG_SMP + /* Which CPU are we initializing */ + + cpu = up_cpu_index(); + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); +#endif + + /* Disable all CPU interrupts on this CPU */ + + xtensa_disable_all(); + + /* Detach all peripheral sources PRO CPU interrupts */ + + for (i = 0; i < ESP32_NPERIPHERALS; i++) + { +#ifdef CONFIG_SMP + if (cpu != 0) + { + regaddr = DPORT_APP_MAP_REGADDR(i); + } + else +#endif + { + regaddr = DPORT_PRO_MAP_REGADDR(i); + } + + putreg32(NO_CPUINT, regaddr); + } + + /* Initialize CPU interrupt-to-IRQ mapping table */ + +#ifdef CONFIG_SMP + if (cpu != 0) + { + intmap = g_cpu1_intmap; + } + else +#endif + { + intmap = g_cpu0_intmap; + } + + /* Indicate that no peripheral interrupts are assigned to CPU interrupts */ + + memset(intmap, CPUINT_UNASSIGNED, ESP32_NCPUINTS); + + /* Special case the 6 internal interrupts. + * + * CPU interrupt bit IRQ number + * --------------------------- --------------------- + * ESP32_CPUINT_MAC 0 ESP32_IRQ_MAC 4 + * ESP32_CPUINT_TIMER0 6 XTENSA_IRQ_TIMER0 0 + * ESP32_CPUINT_SOFTWARE0 7 Not yet defined + * ESP32_CPUINT_PROFILING 11 Not yet defined + * ESP32_CPUINT_TIMER1 15 XTENSA_IRQ_TIMER1 1 + * ESP32_CPUINT_TIMER2 16 XTENSA_IRQ_TIMER2 2 + * ESP32_CPUINT_SOFTWARE1 29 Not yet defined + */ + + intmap[ESP32_CPUINT_TIMER0] = XTENSA_IRQ_TIMER0; + intmap[ESP32_CPUINT_TIMER1] = XTENSA_IRQ_TIMER1; + intmap[ESP32_CPUINT_TIMER2] = XTENSA_IRQ_TIMER2; + + /* Reserve CPU interrupt for some special drivers */ + +#ifdef CONFIG_ESP32_WIRELESS + intmap[ESP32_CPUINT_MAC] = ESP32_IRQ_MAC; +#endif + + return OK; +} + +/**************************************************************************** + * Name: esp32_setup_irq + * + * Description: + * This function sets up the IRQ. It allocates a CPU interrupt of the given + * priority and type and attaches it to the given peripheral. + * + * Input Parameters: + * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU + * periphid - The peripheral number from irq.h to be assigned to + * a CPU interrupt. + * priority - Interrupt's priority (1 - 5). + * type - Interrupt's type (level or edge). + * + * Returned Value: + * The allocated CPU interrupt on success, a negated errno value on + * failure. + * + ****************************************************************************/ + +int esp32_setup_irq(int cpu, int periphid, int priority, int type) +{ + irqstate_t irqstate; + uintptr_t regaddr; + uint8_t *intmap; + int irq; + int cpuint; + + irqstate = enter_critical_section(); + + /* Setting up an IRQ includes the following steps: + * 1. Allocate a CPU interrupt. + * 2. Attach that CPU interrupt to the peripheral. + * 3. Map the CPU interrupt to the IRQ to ease searching later. + */ + + cpuint = esp32_alloc_cpuint(priority, type); + if (cpuint < 0) + { + irqerr("Unable to allocate CPU interrupt for priority=%d and type=%d", + priority, type); + leave_critical_section(irqstate); + + return cpuint; + } + + irq = ESP32_PERIPH2IRQ(periphid); + + DEBUGASSERT(periphid >= 0 && periphid < ESP32_NPERIPHERALS); + DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX); + + esp32_intinfo(cpu, periphid, ®addr, &intmap); + + DEBUGASSERT(intmap[cpuint] == CPUINT_UNASSIGNED); + + intmap[cpuint] = periphid + XTENSA_IRQ_FIRSTPERIPH; + esp32_mapirq(irq, cpu, cpuint); + + putreg32(cpuint, regaddr); + + leave_critical_section(irqstate); + + return cpuint; +} + +/**************************************************************************** + * Name: esp32_teardown_irq + * + * Description: + * This function undoes the operations done by esp32_setup_irq. + * It detaches a peripheral interrupt from a CPU interrupt and frees the + * CPU interrupt. + * + * Input Parameters: + * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU + * periphid - The peripheral number from irq.h to be detached from the + * CPU interrupt. + * cpuint - The CPU interrupt from which the peripheral interrupt will + * be detached. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32_teardown_irq(int cpu, int periphid, int cpuint) +{ + irqstate_t irqstate; + uintptr_t regaddr; + uint8_t *intmap; + int irq; + + irqstate = enter_critical_section(); + + /* Tearing down an IRQ includes the following steps: + * 1. Free the previously allocated CPU interrupt. + * 2. Detach the interrupt from the peripheral. + * 3. Unmap the IRQ from the IRQ-to-cpuint map. + */ + + esp32_free_cpuint(cpuint); + + irq = ESP32_PERIPH2IRQ(periphid); + + DEBUGASSERT(periphid >= 0 && periphid < ESP32_NPERIPHERALS); + + esp32_intinfo(cpu, periphid, ®addr, &intmap); + + DEBUGASSERT(intmap[cpuint] != CPUINT_UNASSIGNED); + intmap[cpuint] = CPUINT_UNASSIGNED; + esp32_unmapirq(irq); + + putreg32(NO_CPUINT, regaddr); + + leave_critical_section(irqstate); +} + diff --git a/arch/xtensa/src/esp32/esp32_irq.h b/arch/xtensa/src/esp32/esp32_irq.h index 65a0429ed3..5357f2b47e 100644 --- a/arch/xtensa/src/esp32/esp32_irq.h +++ b/arch/xtensa/src/esp32/esp32_irq.h @@ -27,6 +27,8 @@ #include +#include + #ifndef __ASSEMBLY__ #undef EXTERN @@ -38,6 +40,40 @@ extern "C" #define EXTERN extern #endif +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* No peripheral assigned to this CPU interrupt */ + +#define CPUINT_UNASSIGNED 0xff + +/* CPU interrupt types. */ + +#define ESP32_CPUINT_LEVEL 0 +#define ESP32_CPUINT_EDGE 1 + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ + +extern uint8_t g_cpu0_intmap[ESP32_NCPUINTS]; +#ifdef CONFIG_SMP +extern uint8_t g_cpu1_intmap[ESP32_NCPUINTS]; +#endif + +/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register + * content. + */ + +#ifdef CONFIG_SMP +extern uint32_t g_intenable[CONFIG_SMP_NCPUS]; +#else +extern uint32_t g_intenable[1]; +#endif + /**************************************************************************** * Public Functions Prototypes ****************************************************************************/ @@ -76,6 +112,67 @@ void esp32_mapirq(int irq, int cpu, int cpuint); void esp32_unmapirq(int irq); +/**************************************************************************** + * Name: esp32_cpuint_initialize + * + * Description: + * Initialize CPU interrupts + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp32_cpuint_initialize(void); + +/**************************************************************************** + * Name: esp32_setup_irq + * + * Description: + * This function sets up the IRQ. It allocates a CPU interrupt of the given + * priority and type and attaches it to the given peripheral. + * + * Input Parameters: + * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU + * periphid - The peripheral number from irq.h to be assigned to + * a CPU interrupt. + * priority - Interrupt's priority (1 - 5). + * type - Interrupt's type (level or edge). + * + * Returned Value: + * The allocated CPU interrupt on success, a negated errno value on + * failure. + * + ****************************************************************************/ + +int esp32_setup_irq(int cpu, int periphid, int priority, int type); + +/**************************************************************************** + * Name: esp32_teardown_irq + * + * Description: + * This function undoes the operations done by esp32_setup_irq. + * It detaches a peripheral interrupt from a CPU interrupt and frees the + * CPU interrupt. + * + * Input Parameters: + * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU + * periphid - The peripheral number from irq.h to be detached from the + * CPU interrupt. + * cpuint - The CPU interrupt from which the peripheral interrupt will + * be detached. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32_teardown_irq(int cpu, int periphid, int cpuint); + #undef EXTERN #if defined(__cplusplus) } diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 074c9073f9..a6a59cef6c 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -53,7 +53,7 @@ #include "hardware/esp32_dma.h" #include "esp32_config.h" #include "esp32_gpio.h" -#include "esp32_cpuint.h" +#include "esp32_irq.h" #include "esp32_dma.h" #include "hardware/esp32_dport.h" diff --git a/arch/xtensa/src/esp32/esp32_spi.c b/arch/xtensa/src/esp32/esp32_spi.c index e9182de1d0..ce06abebcd 100644 --- a/arch/xtensa/src/esp32/esp32_spi.c +++ b/arch/xtensa/src/esp32/esp32_spi.c @@ -45,7 +45,7 @@ #include "esp32_spi.h" #include "esp32_gpio.h" -#include "esp32_cpuint.h" +#include "esp32_irq.h" #include "esp32_dma.h" #include "xtensa.h" diff --git a/arch/xtensa/src/esp32/esp32_spi_slave.c b/arch/xtensa/src/esp32/esp32_spi_slave.c index 9eb2274749..dd8a365b65 100644 --- a/arch/xtensa/src/esp32/esp32_spi_slave.c +++ b/arch/xtensa/src/esp32/esp32_spi_slave.c @@ -48,7 +48,7 @@ #include "esp32_spi.h" #include "esp32_gpio.h" -#include "esp32_cpuint.h" +#include "esp32_irq.h" #include "esp32_dma.h" #include "xtensa.h" diff --git a/arch/xtensa/src/esp32/esp32_tim.c b/arch/xtensa/src/esp32/esp32_tim.c index 2886123508..9b53e0a827 100644 --- a/arch/xtensa/src/esp32/esp32_tim.c +++ b/arch/xtensa/src/esp32/esp32_tim.c @@ -33,8 +33,9 @@ #include "hardware/esp32_tim.h" +#include "esp32_irq.h" + #include "esp32_tim.h" -#include "esp32_cpuint.h" /**************************************************************************** * Private Types diff --git a/arch/xtensa/src/esp32/esp32_wdt.c b/arch/xtensa/src/esp32/esp32_wdt.c index a25e8687f1..4f142c0b7f 100644 --- a/arch/xtensa/src/esp32/esp32_wdt.c +++ b/arch/xtensa/src/esp32/esp32_wdt.c @@ -31,7 +31,7 @@ #include "hardware/esp32_tim.h" #include "hardware/esp32_rtccntl.h" #include "esp32_wdt.h" -#include "esp32_cpuint.h" +#include "esp32_irq.h" #include "esp32_rtc.h" /**************************************************************************** diff --git a/arch/xtensa/src/esp32/esp32_wifi_adapter.c b/arch/xtensa/src/esp32/esp32_wifi_adapter.c index 985ab28a1f..84af1029ad 100644 --- a/arch/xtensa/src/esp32/esp32_wifi_adapter.c +++ b/arch/xtensa/src/esp32/esp32_wifi_adapter.c @@ -56,7 +56,7 @@ #include "hardware/esp32_dport.h" #include "hardware/esp32_emac.h" #include "hardware/esp32_soc.h" -#include "esp32_cpuint.h" +#include "esp32_irq.h" #include "esp32_wifi_adapter.h" #include "esp32_rt_timer.h" #include "esp32_wifi_utils.h"