Update some recent Tiva changes so that old LM3S parts at least still build (but have not been retested)
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@ -129,7 +129,7 @@
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# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
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# define TIVA_TIMER3_BASE (TIVA_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
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/* -0x37fff: Reserved */
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# define TIVA_ADC_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
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# define TIVA_ADC0_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
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/* -0x3bfff: Reserved */
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# define TIVA_CMP_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
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/* -0x47fff: Reserved */
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@ -167,7 +167,7 @@
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# define TIVA_TIMER1_BASE (TIVA_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
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# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
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/* -0x37fff: Reserved */
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# define TIVA_ADC_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
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# define TIVA_ADC0_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
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/* -0x3bfff: Reserved */
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# define TIVA_CMP_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
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/* -0x47fff: Reserved */
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@ -212,7 +212,7 @@
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# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
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# define TIVA_TIMER3_BASE (TIVA_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
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/* -0x37fff: Reserved */
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# define TIVA_ADC_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
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# define TIVA_ADC0_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
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/* -0x3bfff: Reserved */
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# define TIVA_CMP_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
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/* -0x47fff: Reserved */
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@ -254,7 +254,7 @@
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# define TIVA_TIMER2_BASE (TIVA_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
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# define TIVA_TIMER3_BASE (TIVA_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
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/* -0x37fff: Reserved */
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# define TIVA_ADC_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
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# define TIVA_ADC0_BASE (TIVA_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
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/* -0x3bfff: Reserved */
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# define TIVA_CMP_BASE (TIVA_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
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/* -0x3fffff: Reserved */
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@ -499,8 +499,10 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
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uint32_t pdrclr = 0;
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uint32_t denset = 0;
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uint32_t denclr = 0;
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#if defined(LM4F) || defined(TM4C)
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uint32_t amselset = 0;
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uint32_t amselclr = 0;
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#endif
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/* Set the pin type. */
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@ -512,7 +514,9 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
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purclr = pin;
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pdrclr = pin;
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denset = pin;
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#if defined(LM4F) || defined(TM4C)
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amselclr = pin;
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#endif
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}
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break;
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@ -522,7 +526,9 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
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purset = pin;
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pdrclr = pin;
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denset = pin;
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#if defined(LM4F) || defined(TM4C)
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amselclr = pin;
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#endif
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}
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break;
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@ -532,7 +538,9 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
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purclr = pin;
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pdrset = pin;
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denset = pin;
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#if defined(LM4F) || defined(TM4C)
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amselclr = pin;
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#endif
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}
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break;
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@ -542,7 +550,9 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
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purclr = pin;
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pdrclr = pin;
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denset = pin;
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#if defined(LM4F) || defined(TM4C)
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amselclr = pin;
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#endif
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}
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break;
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@ -552,7 +562,9 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
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purset = pin;
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pdrclr = pin;
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denclr = pin;
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#if defined(LM4F) || defined(TM4C)
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amselclr = pin;
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#endif
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}
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break;
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@ -562,7 +574,9 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
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purclr = pin;
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pdrset = pin;
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denclr = pin;
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#if defined(LM4F) || defined(TM4C)
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amselclr = pin;
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#endif
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}
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break;
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@ -572,7 +586,9 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
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purclr = pin;
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pdrclr = pin;
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denclr = pin;
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#if defined(LM4F) || defined(TM4C)
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amselset = pin;
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#endif
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}
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break;
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@ -584,7 +600,10 @@ static inline void tiva_gpiopadtype(uint32_t base, uint32_t pin,
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modifyreg32(base + TIVA_GPIO_PUR_OFFSET, purclr, purset);
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modifyreg32(base + TIVA_GPIO_PDR_OFFSET, pdrclr, pdrset);
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modifyreg32(base + TIVA_GPIO_DEN_OFFSET, denclr, denset);
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#if defined(LM4F) || defined(TM4C)
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modifyreg32(base + TIVA_GPIO_AMSEL_OFFSET, amselclr, amselset);
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#endif
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#ifdef CONFIG_ARCH_CHIP_TM4C129
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/* Set the wake pin enable register and the wake level register. These
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