Minor style: # if pre-processor command should be in columnn 1

arch/arm/src/a1x/chip/a10_memorymap.h

@@ -467,7 +467,7 @@
    * in the way at that position.
    */
 
-  #if defined(CONFIG_ARCH_LOWVECTORS)
+#  if defined(CONFIG_ARCH_LOWVECTORS)
   /* In this case, table must lie in SRAM A2 after the vectors in SRAM A1 */
 
 #    define PGTABLE_BASE_PADDR  A1X_SRAMA2_PADDR

arch/arm/src/arm/cache.h

@@ -74,5 +74,5 @@ unsigned int cp15_read_icachelockdown(void);
 void         cp15_write_icachelockdown(unsigned int value);
 #endif
 
-#endif // #ifndef __ARCH_ARM_SRC_ARM_CACHE_H
+#endif /* __ARCH_ARM_SRC_ARM_CACHE_H */
 

arch/arm/src/lpc17xx/lpc17_usbhost.c

@@ -3228,7 +3228,7 @@ static int lpc17_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
 
   ed->xfrinfo       = xfrinfo;
 
-  #if LPC17_IOBUFFERS > 0
+#if LPC17_IOBUFFERS > 0
   /* Allocate an IO buffer if the user buffer does not lie in AHB SRAM */
 
   ret = lpc17_dma_alloc(priv, ed, buffer, buflen, &xfrinfo->alloc);

arch/arm/src/lpc43xx/lpc43_ethernet.c

@@ -2554,7 +2554,7 @@ static int lpc43_txavail(struct net_driver_s *dev)
 
   lpc43_txavail_process(priv);
   irqrestore(flags);
-  #endif
+#endif
 
   return OK;
 }

arch/arm/src/lpc43xx/lpc43_serial.c

@@ -651,29 +651,29 @@ static void up_shutdown(struct uart_dev_s *dev)
 
   switch (priv->id)
     {
-  #ifdef CONFIG_LPC43_USART0
+#ifdef CONFIG_LPC43_USART0
       case 0:
         lpc43_usart0_reset();
         break;
-  #endif
+#endif
 
-  #ifdef CONFIG_LPC43_UART1
+#ifdef CONFIG_LPC43_UART1
       case 1:
         lpc43_uart1_reset();
         break;
-  #endif
+#endif
 
-  #ifdef CONFIG_LPC43_USART2
+#ifdef CONFIG_LPC43_USART2
       case 2:
         lpc43_usart2_reset();
         break;
-  #endif
+#endif
 
-  #ifdef CONFIG_LPC43_USART3
+#ifdef CONFIG_LPC43_USART3
       case 3:
         lpc43_usart3_reset();
         break;
-  #endif
+#endif
 
       default:
         break;

arch/arm/src/stm32/stm32_adc.c

@@ -892,7 +892,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
       {
         ccer &= ~(GTIM_CCER_CC1NP | GTIM_CCER_CC2NP | GTIM_CCER_CC3NP);
       }
-  #endif
+#  endif
 
 #else
 

arch/arm/src/stm32/stm32f30xxx_rcc.c

@@ -198,7 +198,7 @@ static inline void rcc_enableapb1(void)
 
   regval  = getreg32(STM32_RCC_APB1ENR);
 
-  #ifdef CONFIG_STM32_TIM2
+#ifdef CONFIG_STM32_TIM2
   /* Timer 2 clock enable */
 
 #ifdef CONFIG_STM32_FORCEPOWER