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This commit is contained in:
Gregory Nutt 2015-10-04 16:00:42 -06:00
parent aaa697ec83
commit 7a63e976ad
24 changed files with 442 additions and 405 deletions
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21
arch/arm/src/calypso/calypso_timer.c
View File

@ -52,13 +52,15 @@
#define TIMER_REG(n, m) (((n)-1) ? (BASE_ADDR_TIMER + TIMER2_OFFSET + (m)) : (BASE_ADDR_TIMER + (m)))
enum timer_reg {
enum timer_reg
{
CNTL_TIMER = 0x00,
LOAD_TIMER = 0x02,
READ_TIMER = 0x04,
};
enum timer_ctl {
enum timer_ctl
{
CNTL_START = (1 << 0),
CNTL_AUTO_RELOAD = (1 << 1),
CNTL_CLOCK_ENABLE = (1 << 5),
@ -70,7 +72,8 @@ void hwtimer_enable(int num, int on)
{
uint8_t ctl;
if (num < 1 || num > 2) {
if (num < 1 || num > 2)
{
printf("Unknown timer %d\n", num);
return;
}
@ -80,6 +83,7 @@ void hwtimer_enable(int num, int on)
ctl |= CNTL_START|CNTL_CLOCK_ENABLE;
else
ctl &= ~CNTL_START;
putreg8(ctl, TIMER_REG(num, CNTL_TIMER));
}
@ -104,8 +108,10 @@ uint16_t hwtimer_read(int num)
uint8_t ctl = getreg8(TIMER_REG(num, CNTL_TIMER));
/* somehow a read results in an abort */
if ((ctl & (CNTL_START|CNTL_CLOCK_ENABLE)) != (CNTL_START|CNTL_CLOCK_ENABLE))
return 0xFFFF;
return getreg16(TIMER_REG(num, READ_TIMER));
}
@ -146,7 +152,8 @@ static void wdog_irq(__unused enum irq_nr nr)
void wdog_enable(int on)
{
if (!on) {
if (!on)
{
putreg16(WD_MODE_DIS_ARM, WDOG_REG(WD_MODE));
putreg16(WD_MODE_DIS_CONFIRM, WDOG_REG(WD_MODE));
}
@ -155,8 +162,11 @@ void wdog_enable(int on)
void wdog_reset(void)
{
// enable watchdog
putreg16(WD_MODE_ENABLE, WDOG_REG(WD_MODE));
// force expiration
putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
}
@ -199,12 +209,13 @@ void up_timer_initialize(void)
/* The timer runs at 13MHz / 32, i.e. 406.25kHz */
/* 4062 ticks until expiry yields 100Hz interrupt */
hwtimer_load(2, 4062);
hwtimer_config(2, 0, 1);
hwtimer_enable(2, 1);
/* Attach and enable the timer interrupt */
irq_attach(IRQ_SYSTIMER, (xcpt_t)up_timerisr);
up_enable_irq(IRQ_SYSTIMER);
}

17
arch/arm/src/calypso/calypso_uwire.c
View File

@ -49,7 +49,8 @@
#define BASE_ADDR_UWIRE 0xfffe4000
#define UWIRE_REG(n) (BASE_ADDR_UWIRE+(n))
enum uwire_regs {
enum uwire_regs
{
REG_DATA = 0x00,
REG_CSR = 0x02,
REG_SR1 = 0x04,
@ -90,7 +91,9 @@ static inline void _uwire_wait(int mask, int val)
void uwire_init(void)
{
putreg16(UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2, UWIRE_REG(REG_SR3));
/* FIXME only init CS0 for now */
putreg16(((UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2) << UWIRE_CSn_SHIFT(0)),
UWIRE_REG(UWIRE_CSn_REG(0)));
putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
@ -103,6 +106,7 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
if (bitlen <= 0 || bitlen > 16)
return -1;
if (cs < 0 || cs > 4)
return -1;
@ -111,14 +115,17 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
dbg("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen);
/* select the chip */
putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
_uwire_wait(UWIRE_CSR_CSRB, 0);
if (dout) {
if (dout)
{
if (bitlen <= 8)
tmp = *(uint8_t *)dout;
else if (bitlen <= 16)
tmp = *(uint16_t *)dout;
tmp <<= 16 - bitlen; /* align to MSB */
putreg16(tmp, UWIRE_REG(REG_DATA));
dbg(", data_out=0x%04hx", tmp);
@ -128,10 +135,10 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
(din ? UWIRE_CSR_BITS_RD(bitlen) : 0) |
UWIRE_CSR_START;
putreg16(tmp, UWIRE_REG(REG_CSR));
_uwire_wait(UWIRE_CSR_CSRB, 0);
if (din) {
if (din)
{
_uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB);
tmp = getreg16(UWIRE_REG(REG_DATA));
@ -142,7 +149,9 @@ int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
else if (bitlen <= 16)
*(uint16_t *)din = tmp & 0xffff;
}
/* unselect the chip */
putreg16(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR));
_uwire_wait(UWIRE_CSR_CSRB, 0);

18
arch/arm/src/calypso/clock.c
View File

@ -63,7 +63,8 @@
#define BASE_ADDR_CLKM 0xfffffd00
#define CLKM_REG(m) (BASE_ADDR_CLKM+(m))
enum clkm_reg {
enum clkm_reg
{
CNTL_ARM_CLK = 0,
CNTL_CLK = 2,
CNTL_RST = 4,
@ -71,6 +72,7 @@ enum clkm_reg {
};
/* CNTL_ARM_CLK */
#define ARM_CLK_BIG_SLEEP (1 << 0) /* MCU Master Clock enabled? */
#define ARM_CLK_CLKIN_SEL0 (1 << 1) /* MCU source clock (0 = DPLL output, 1 = VTCXO or CLKIN */
#define ARM_CLK_CLKIN_SEL (1 << 2) /* 0 = VTCXO or 1 = CLKIN */
@ -93,7 +95,8 @@ enum clkm_reg {
#define BASE_ADDR_MEMIF 0xfffffb00
#define MEMIF_REG(x) (BASE_ADDR_MEMIF+(x))
enum memif_reg {
enum memif_reg
{
API_RHEA_CTL = 0x0e,
EXTRA_CONF = 0x10,
};
@ -154,25 +157,32 @@ void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div)
uint16_t cntl_arm_clk = getreg16(CLKM_REG(CNTL_ARM_CLK));
/* First set the vtcxo_div2 */
cntl_clock &= ~CLK_VCLKOUT_DIV2;
if (vtcxo_div2)
cntl_clock |= CLK_VTCXO_DIV2;
else
cntl_clock &= ~CLK_VTCXO_DIV2;
putreg16(cntl_clock, CLKM_REG(CNTL_CLK));
/* Then configure the MCLK divider */
cntl_arm_clk &= ~ARM_CLK_CLKIN_SEL0;
if (mclk_div & 0x80) {
if (mclk_div & 0x80)
{
mclk_div &= ~0x80;
cntl_arm_clk |= ARM_CLK_MCLK_DIV5;
} else
}
else
cntl_arm_clk &= ~ARM_CLK_MCLK_DIV5;
cntl_arm_clk &= ~(0x7 << ARM_CLK_MCLK_DIV_SHIFT);
cntl_arm_clk |= (mclk_div << ARM_CLK_MCLK_DIV_SHIFT);
putreg16(cntl_arm_clk, CLKM_REG(CNTL_ARM_CLK));
/* Then finally set the PLL */
calypso_pll_set(inp);
}

7
arch/rgmp/src/arm/arch_nuttx.c
View File

@ -43,22 +43,20 @@
#include <arch/arch.h>
#include <nuttx/sched.h>
void nuttx_arch_init(void)
{
}
void nuttx_arch_exit(void)
{
}
void up_initial_state(struct tcb_s *tcb)
{
struct Trapframe *tf;
if (tcb->pid != 0) {
if (tcb->pid != 0)
{
tf = (struct Trapframe *)tcb->adj_stack_ptr-1;
memset(tf, 0, sizeof(struct Trapframe));
tf->tf_cpsr = SVC_MOD;
@ -73,6 +71,7 @@ void push_xcptcontext(struct xcptcontext *xcp)
xcp->save_eflags = xcp->tf->tf_cpsr;
// set interrupts disabled
xcp->tf->tf_pc = (uint32_t)up_sigentry;
xcp->tf->tf_cpsr |= CPSR_IF;
}

5
arch/rgmp/src/bridge.c
View File

@ -108,16 +108,19 @@ int rtos_bridge_init(struct rgmp_bridge *b)
bridge->b = b;
if ((err = sem_init(&bridge->rd_lock, 0, 1)) == ERROR)
goto err1;
if ((err = sem_init(&bridge->wr_lock, 0, 1)) == ERROR)
goto err1;
// make rgmp_bridge0 to be the console
if (strcmp(b->vdev->name, "rgmp_bridge0") == 0)
strlcpy(path + 5, "console", 25);
else
strlcpy(path + 5, b->vdev->name, 25);
if ((err = register_driver(path, &up_bridge_fops, 0666, bridge)) == ERROR) {
if ((err = register_driver(path, &up_bridge_fops, 0666, bridge)) == ERROR)
{
cprintf("NuttX: register bridge %s fail\n", b->vdev->name);
goto err1;
}

24
arch/rgmp/src/rgmp.c
View File

@ -88,11 +88,11 @@ void rtos_kfree(void *addr)
kmm_free(addr);
}
/**
* The interrupt can be nested. The pair of rtos_enter_interrupt()
/* The interrupt can be nested. The pair of rtos_enter_interrupt()
* and rtos_exit_interrupt() make sure the context switch is
* performed only in the last IRQ exit.
*/
void rtos_enter_interrupt(void)
{
nest_irq++;
@ -102,17 +102,23 @@ void rtos_exit_interrupt(void)
{
local_irq_disable();
nest_irq--;
if (!nest_irq) {
if (!nest_irq)
{
struct tcb_s *rtcb = current_task;
struct tcb_s *ntcb;
if (rtcb->xcp.sigdeliver) {
if (rtcb->xcp.sigdeliver)
{
rtcb->xcp.ctx.tf = current_regs;
push_xcptcontext(&rtcb->xcp);
}
ntcb = (struct tcb_s*)g_readytorun.head;
// switch needed
if (rtcb != ntcb) {
if (rtcb != ntcb)
{
rtcb->xcp.ctx.tf = current_regs;
current_task = ntcb;
rgmp_switch_to(&ntcb->xcp.ctx);
@ -125,9 +131,8 @@ void rtos_timer_isr(void *data)
sched_process_timer();
}
/**
* RTOS semaphore operation
*/
/* RTOS semaphore operation */
int rtos_sem_init(struct semaphore *sem, int val)
{
if ((sem->sem = kmm_malloc(sizeof(sem_t))) == NULL)
@ -165,6 +170,3 @@ int rtos_vnet_init(struct rgmp_vnet *vnet)
return vnet_init(vnet);
}

7
arch/rgmp/src/x86/arch_nuttx.c
View File

@ -67,20 +67,22 @@ void nuttx_arch_exit(void)
#ifdef CONFIG_NET_E1000
e1000_mod_exit();
#endif
}
void up_initial_state(struct tcb_s *tcb)
{
struct Trapframe *tf;
if (tcb->pid) {
if (tcb->pid)
{
tf = (struct Trapframe *)tcb->adj_stack_ptr - 1;
rgmp_setup_context(&tcb->xcp.ctx, tf, tcb->start, 1);
}
else
{
rgmp_setup_context(&tcb->xcp.ctx, NULL, NULL, 0);
}
}
void push_xcptcontext(struct xcptcontext *xcp)
{
@ -88,6 +90,7 @@ void push_xcptcontext(struct xcptcontext *xcp)
xcp->save_eflags = xcp->ctx.tf->tf_eflags;
// set up signal entry with interrupts disabled
xcp->ctx.tf->tf_eip = (uint32_t)up_sigentry;
xcp->ctx.tf->tf_eflags = 0;
}