include/nuttx/i2c/i2c_master.h: Fix a small typo.
arch/mips/include/pic32mz/chip.h: Add a messing " in an error message. arch/mips/src/pic32mz: Add support for the I2C bus.
This commit is contained in:
Ouss4
Gregory Nutt
parent
6371b970f9
commit
7aefd5a45f
@ -195,7 +195,7 @@
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# define CHIP_NTRACE 1 /* Has trace capability */
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#else
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# error "Unrecognized PIC32MZ device
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# error "Unrecognized PIC32MZ device"
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#endif
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/****************************************************************************
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@ -61,6 +61,10 @@ config PIC32MZ_SPI
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bool
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default n
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config PIC32MZ_I2C
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bool
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default n
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config PIC32MZ_T1
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bool
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default y
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@ -146,22 +150,27 @@ config PIC32MZ_OC5
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config PIC32MZ_I2C1
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bool "I2C1"
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default n
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select PIC32MZ_I2C
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config PIC32MZ_I2C2
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bool "I2C2"
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default n
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select PIC32MZ_I2C
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config PIC32MZ_I2C3
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bool "I2C3"
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default n
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select PIC32MZ_I2C
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config PIC32MZ_I2C4
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bool "I2C4"
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default n
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select PIC32MZ_I2C
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config PIC32MZ_I2C5
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bool "I2C5"
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default n
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select PIC32MZ_I2C
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config PIC32MZ_SPI1
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bool "SPI1"
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@ -364,6 +373,41 @@ config PIC32MZ_SPI_REGDEBUG
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endmenu # SPI Driver Configuration
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menu "I2C Driver Configuration"
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depends on PIC32MZ_I2C
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config PIC32MZ_I2C_DYNTIMEO
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bool "Use dynamic timeouts"
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default n
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depends on PIC32MZ_I2C
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config PIC32MZ_I2C_DYNTIMEO_USECPERBYTE
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int "Timeout Microseconds per Byte"
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default 500
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depends on PIC32MZ_I2C_DYNTIMEO
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config PIC32MZ_I2C_DYNTIMEO_STARTSTOP
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int "Timeout for Idle state (Milliseconds)"
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default 1000
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depends on PIC32MZ_I2C_DYNTIMEO
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config PIC32MZ_I2CTIMEOSEC
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int "Timeout seconds"
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default 0
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depends on PIC32MZ_I2C
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config PIC32MZ_I2CTIMEOMS
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int "Timeout Milliseconds"
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default 500
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depends on PIC32MZ_I2C && !PIC32MZ_I2C_DYNTIMEO
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config PIC32MZ_I2CTIMEOTICKS
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int "Timeout for Idle state (ticks)"
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default 500
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depends on PIC32MZ_I2C && !PIC32MZ_I2C_DYNTIMEO
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endmenu # I2C Configuration
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config PIC32MZ_T1_SOSC
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bool
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default n
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@ -86,6 +86,10 @@ ifeq ($(CONFIG_PIC32MZ_SPI),y)
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CHIP_CSRCS += pic32mz-spi.c
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endif
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ifeq ($(CONFIG_PIC32MZ_I2C),y)
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CHIP_CSRCS += pic32mz-i2c.c
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endif
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ifeq ($(CONFIG_PIC32MZ_ETHERNET),y)
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CHIP_CSRCS += pic32mz-ethernet.c
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endif
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/mips/src/pic32mz/pic32mz-i2c.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -50,6 +50,7 @@
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* I2C Peripheral Offsets ***********************************************************/
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#define PIC32MZ_I2Cn_OFFSET(n) ((n) << 9)
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@ -58,7 +59,7 @@
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# define PIC32MZ_I2C3_OFFSET 0x0400
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# define PIC32MZ_I2C4_OFFSET 0x0600
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# define PIC32MZ_I2C5_OFFSET 0x0800
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#
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/* I2C Register Offsets *************************************************************/
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#define PIC32MZ_I2C_CON_OFFSET 0x0000 /* I2C control register */
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@ -95,52 +96,47 @@
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/* I2C Peripheral Addresses *********************************************************/
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#define PIC32MZ_I2Cn_K1BASE(n) (PIC32MZ_I2C_K1BASE+
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PIC32MZ_I2Cn_OFFSET(n))
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# define PIC32MZ_I2C1_K1BASE (PIC32MZ_I2C_K1BASE+
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PIC32MZ_I2C1_OFFSET)
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# define PIC32MZ_I2C2_K1BASE (PIC32MZ_I2C_K1BASE+
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PIC32MZ_I2C2_OFFSET)
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# define PIC32MZ_I2C3_K1BASE (PIC32MZ_I2C_K1BASE+
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PIC32MZ_I2C3_OFFSET)
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# define PIC32MZ_I2C4_K1BASE (PIC32MZ_I2C_K1BASE+
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PIC32MZ_I2C4_OFFSET 0x0600
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# define PIC32MZ_I2C5_K1BASE)
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PIC32MZ_I2C5_OFFSET 0x0800
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#define PIC32MZ_I2Cn_K1BASE(n) (PIC32MZ_I2C_K1BASE+PIC32MZ_I2Cn_OFFSET(n))
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# define PIC32MZ_I2C1_K1BASE (PIC32MZ_I2C_K1BASE+PIC32MZ_I2C1_OFFSET)
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# define PIC32MZ_I2C2_K1BASE (PIC32MZ_I2C_K1BASE+PIC32MZ_I2C2_OFFSET)
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# define PIC32MZ_I2C3_K1BASE (PIC32MZ_I2C_K1BASE+PIC32MZ_I2C3_OFFSET)
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# define PIC32MZ_I2C4_K1BASE (PIC32MZ_I2C_K1BASE+PIC32MZ_I2C4_OFFSET)
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# define PIC32MZ_I2C5_K1BASE (PIC32MZ_I2C_K1BASE+PIC32MZ_I2C5_OFFSET)
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/* I2C Register Addresses ***********************************************************/
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#define PIC32MZ_I2C1_CON (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_CON_OFFSET)
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#define PIC32MZ_I2C1_CONCLR (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_CONCLR_OFFSET)
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#define PIC32MZ_I2C1_CONSET (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_CONSET_OFFSET)
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#define PIC32MZ_I2C1_CONINV (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_CONINV_OFFSET)
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# define PIC32MZ_I2C1_CON (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_CON_OFFSET)
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# define PIC32MZ_I2C1_CONCLR (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_CONCLR_OFFSET)
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# define PIC32MZ_I2C1_CONSET (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_CONSET_OFFSET)
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# define PIC32MZ_I2C1_CONINV (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_CONINV_OFFSET)
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#define PIC32MZ_I2C1_STAT (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_STAT_OFFSET)
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#define PIC32MZ_I2C1_STATCLR (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_STATCLR_OFFSET)
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#define PIC32MZ_I2C1_STATSET (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_STATSET_OFFSET)
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#define PIC32MZ_I2C1_STATINV (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_STATINV_OFFSET)
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# define PIC32MZ_I2C1_STAT (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_STAT_OFFSET)
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# define PIC32MZ_I2C1_STATCLR (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_STATCLR_OFFSET)
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# define PIC32MZ_I2C1_STATSET (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_STATSET_OFFSET)
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# define PIC32MZ_I2C1_STATINV (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_STATINV_OFFSET)
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#define PIC32MZ_I2C1_ADD (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_ADD_OFFSET)
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#define PIC32MZ_I2C1_ADDCLR (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_ADDCLR_OFFSET)
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#define PIC32MZ_I2C1_ADDSET (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_ADDSET_OFFSET)
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#define PIC32MZ_I2C1_ADDINV (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_ADDINV_OFFSET)
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# define PIC32MZ_I2C1_ADD (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_ADD_OFFSET)
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# define PIC32MZ_I2C1_ADDCLR (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_ADDCLR_OFFSET)
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# define PIC32MZ_I2C1_ADDSET (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_ADDSET_OFFSET)
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# define PIC32MZ_I2C1_ADDINV (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_ADDINV_OFFSET)
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#define PIC32MZ_I2C1_MSK (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_MSK_OFFSET)
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#define PIC32MZ_I2C1_MSKCLR (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_MSKCLR_OFFSET)
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#define PIC32MZ_I2C1_MSKSET (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_MSKSET_OFFSET)
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#define PIC32MZ_I2C1_MSKINV (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_MSKINV_OFFSET)
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# define PIC32MZ_I2C1_MSK (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_MSK_OFFSET)
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# define PIC32MZ_I2C1_MSKCLR (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_MSKCLR_OFFSET)
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# define PIC32MZ_I2C1_MSKSET (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_MSKSET_OFFSET)
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# define PIC32MZ_I2C1_MSKINV (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_MSKINV_OFFSET)
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#define PIC32MZ_I2C1_BRG (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_BRG_OFFSET)
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#define PIC32MZ_I2C1_BRGSET (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_BRGSET_OFFSET)
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#define PIC32MZ_I2C1_BRGCLR (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_BRGCLR_OFFSET)
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#define PIC32MZ_I2C1_BRGINV (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_BRGINV_OFFSET)
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# define PIC32MZ_I2C1_BRG (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_BRG_OFFSET)
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# define PIC32MZ_I2C1_BRGSET (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_BRGSET_OFFSET)
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# define PIC32MZ_I2C1_BRGCLR (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_BRGCLR_OFFSET)
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# define PIC32MZ_I2C1_BRGINV (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_BRGINV_OFFSET)
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#define PIC32MZ_I2C1_TRN (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_TRN_OFFSET)
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#define PIC32MZ_I2C1_TRNCLR (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_TRNCLR_OFFSET)
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#define PIC32MZ_I2C1_TRNSET (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_TRNSET_OFFSET)
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#define PIC32MZ_I2C1_TRNINV (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_TRNINV_OFFSET)
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# define PIC32MZ_I2C1_TRN (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_TRN_OFFSET)
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# define PIC32MZ_I2C1_TRNCLR (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_TRNCLR_OFFSET)
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# define PIC32MZ_I2C1_TRNSET (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_TRNSET_OFFSET)
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# define PIC32MZ_I2C1_TRNINV (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_TRNINV_OFFSET)
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#define PIC32MZ_I2C1_RCV (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_RCV_OFFSET)
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# define PIC32MZ_I2C1_RCV (PIC32MZ_I2C1_K1BASE+PIC32MZ_I2C_RCV_OFFSET)
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#endif
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#if CHIP_NI2C > 1
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# define PIC32MZ_I2C2_CON (PIC32MZ_I2C2_K1BASE+PIC32MZ_I2C_CON_OFFSET)
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@ -306,6 +302,8 @@ PIC32MZ_I2C5_OFFSET 0x0800
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#define I2C_CON_SCIE (1 << 21) /* Bit 21: Start Condition Interrupt Enable (Slave mode) */
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#define I2C_CON_PCIE (1 << 22) /* Bit 22: Stop Condition Interrupt Enable (Slave mode) */
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/* Bits 23-31: Reserved */
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#define I2C_CON_IDLEMASK (I2C_CON_SEN | I2C_CON_RSEN | I2C_CON_PEN |\
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I2C_CON_RCEN | I2C_CON_ACKEN)
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/* I2C status register */
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@ -321,7 +319,7 @@ PIC32MZ_I2C5_OFFSET 0x0800
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#define I2C_STAT_GCSTAT (1 << 9) /* Bit 9: General call status */
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#define I2C_STAT_BCL (1 << 10) /* Bit 10: Master bus collision detect */
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/* Bits 11-12 */
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#define I2C_STAT_ACKTIM: (1 << 13) /* Bit 13: Acknowledge Time Status bit (Slave mode) */
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#define I2C_STAT_ACKTIM (1 << 13) /* Bit 13: Acknowledge Time Status bit (Slave mode) */
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#define I2C_STAT_TRSTAT (1 << 14) /* Bit 14: Transmit status (Master mode) */
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#define I2C_STAT_ACKSTAT (1 << 15) /* Bit 15: Acknowledge status (Master mode) */
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@ -339,7 +337,7 @@ PIC32MZ_I2C5_OFFSET 0x0800
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/* I2C transmit register */
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#define I2C_TRN_MASK 00000x00ff /* 8-bit transmit data */
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#define I2C_TRN_MASK 0x000000ff /* 8-bit transmit data */
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/* I2C receive buffer register */
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@ -232,6 +232,40 @@
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# define CONFIG_PIC32MZ_SPI 1
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#endif
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/* I2C ******************************************************************************/
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/* Don't enable I2C peripherals not supported by the chip. */
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#if CHIP_NI2C < 1
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# undef CONFIG_PIC32MZ_I2C1
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# undef CONFIG_PIC32MZ_I2C2
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# undef CONFIG_PIC32MZ_I2C3
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# undef CONFIG_PIC32MZ_I2C4
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# undef CONFIG_PIC32MZ_I2C5
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#elif CHIP_NI2C < 2
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# undef CONFIG_PIC32MZ_I2C2
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# undef CONFIG_PIC32MZ_I2C3
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# undef CONFIG_PIC32MZ_I2C4
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# undef CONFIG_PIC32MZ_I2C5
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#elif CHIP_NI2C < 3
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# undef CONFIG_PIC32MZ_I2C3
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# undef CONFIG_PIC32MZ_I2C4
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# undef CONFIG_PIC32MZ_I2C5
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#elif CHIP_NI2C < 4
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# undef CONFIG_PIC32MZ_I2C4
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# undef CONFIG_PIC32MZ_I2C5
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#elif CHIP_NI2C < 5
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# undef CONFIG_PIC32MZ_I2C5
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#endif
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/* Are any I2C peripherals enabled? */
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#undef CONFIG_PIC32MZ_I2C
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#if defined(CONFIG_PIC32MZ_I2C1) || defined(CONFIG_PIC32MZ_I2C2) || \
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defined(CONFIG_PIC32MZ_I2C4) || defined(CONFIG_PIC32MZ_I2C4) || \
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defined(CONFIG_PIC32MZ_I2C5)
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# define CONFIG_PIC32MZ_I2C 1
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#endif
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/* Device Configuration *************************************************************/
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/* DEVCFG3 */
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/* Configurable settings */
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1937
arch/mips/src/pic32mz/pic32mz-i2c.c
Normal file
1937
arch/mips/src/pic32mz/pic32mz-i2c.c
Normal file
File diff suppressed because it is too large
Load Diff
90
arch/mips/src/pic32mz/pic32mz-i2c.h
Normal file
90
arch/mips/src/pic32mz/pic32mz-i2c.h
Normal file
@ -0,0 +1,90 @@
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/************************************************************************************
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* arch/mips/src/pic32mz/chip/pic32mz-i2c.h
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*
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* Copyright (C) 2018 Abdelatif Guettouche. All rights reserved.
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* Author: Abdelatif Guettouche <abdelatif.guettouche@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
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* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
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* distribution.
|
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_I2C_H
|
||||
#define __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_I2C_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pic32mz_i2cbus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected I2C port. And return a unique instance of struct
|
||||
* struct i2c_master_s. This function may be called to obtain multiple
|
||||
* instances of the interface, each of which may be set up with a
|
||||
* different frequency and slave address.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Port number (for hardware that has multiple I2C interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid I2C device structure reference on succcess; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct i2c_master_s *pic32mz_i2cbus_initialize(int port);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pic32mz_i2cbus_uninitialize
|
||||
*
|
||||
* Description:
|
||||
* De-initialize the selected I2C port, and power down the device.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Device structure as returned by the pic32mz_i2cbus_initialize()
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success, ERROR when internal reference count mismatch or dev
|
||||
* points to invalid hardware device.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int pic32mz_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
|
||||
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MZ_PIC32MZ_I2C_H */
|
||||
@ -78,7 +78,7 @@
|
||||
* START/STOP Rules:
|
||||
*
|
||||
* 1. The lower half I2C driver will always issue the START condition at the
|
||||
* beginning of a message unless I2C_M_NOSTART flat is set in the
|
||||
* beginning of a message unless I2C_M_NOSTART flag is set in the
|
||||
* message.
|
||||
*
|
||||
* 2. The lower half I2C driver will always issue the STOP condition at the
|
||||
@ -213,7 +213,7 @@ struct i2c_config_s
|
||||
uint8_t addrlen; /* I2C address length (7 or 10 bits) */
|
||||
};
|
||||
|
||||
/* I2C transaction segment beginning with a START. A number of these can
|
||||
/* I2C transaction segment beginning with a START. A number of these can
|
||||
* be transferred together to form an arbitrary sequence of write/read transfer
|
||||
* to an I2C slave device.
|
||||
*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user