From 7afedda89ebd45230cd4b95ca89f7d024f05319a Mon Sep 17 00:00:00 2001 From: Petro Karashchenko Date: Fri, 25 Mar 2022 13:18:36 +0100 Subject: [PATCH] arch/risc-v: improve style consistency accross chip variants Signed-off-by: Petro Karashchenko --- arch/risc-v/include/syscall.h | 16 ++++++++-------- arch/risc-v/src/bl602/bl602_irq.c | 6 ++++++ arch/risc-v/src/bl602/bl602_irq_dispatch.c | 12 +++--------- arch/risc-v/src/c906/c906_irq.c | 2 +- arch/risc-v/src/c906/c906_irq_dispatch.c | 18 ++++++++++++------ arch/risc-v/src/common/riscv_swint.c | 4 ++-- arch/risc-v/src/fe310/fe310_irq.c | 6 ++++++ arch/risc-v/src/fe310/fe310_irq_dispatch.c | 6 +++--- arch/risc-v/src/k210/k210_irq.c | 8 -------- arch/risc-v/src/k210/k210_irq_dispatch.c | 10 ++++++++-- arch/risc-v/src/litex/litex_irq.c | 6 ++++++ arch/risc-v/src/litex/litex_irq_dispatch.c | 6 +++--- arch/risc-v/src/mpfs/mpfs_irq_dispatch.c | 14 +++++++------- arch/risc-v/src/mpfs/mpfs_timerisr.c | 4 ++-- arch/risc-v/src/qemu-rv/qemu_rv_irq.c | 6 ++++++ arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c | 8 +------- arch/risc-v/src/rv32m1/rv32m1_irq.c | 6 ++++++ arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c | 9 ++++----- 18 files changed, 84 insertions(+), 63 deletions(-) diff --git a/arch/risc-v/include/syscall.h b/arch/risc-v/include/syscall.h index 00c9d79b61..c436d44576 100644 --- a/arch/risc-v/include/syscall.h +++ b/arch/risc-v/include/syscall.h @@ -67,14 +67,14 @@ /* SYS call 1: * - * void riscv_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + * void riscv_fullcontextrestore(uintptr_t *restoreregs) noreturn_function; */ #define SYS_restore_context (1) /* SYS call 2: * - * void riscv_switchcontext(uint32_t *saveregs, uint32_t *restoreregs); + * void riscv_switchcontext(uintptr_t *saveregs, uintptr_t *restoreregs); */ #define SYS_switch_context (2) @@ -130,7 +130,7 @@ /* SYS call 0: * - * int riscv_saveusercontext(uint64_t *saveregs); + * int riscv_saveusercontext(uintptr_t *saveregs); * * Return: * 0: Normal Return @@ -138,23 +138,23 @@ */ #define riscv_saveusercontext(saveregs) \ - (int)sys_call1(SYS_save_context, (uintptr_t)saveregs) + (int)sys_call1(SYS_save_context, (uintptr_t)(saveregs)) /* SYS call 1: * - * void riscv_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + * void riscv_fullcontextrestore(uintptr_t *restoreregs) noreturn_function; */ #define riscv_fullcontextrestore(restoreregs) \ - sys_call1(SYS_restore_context, (uintptr_t)restoreregs) + sys_call1(SYS_restore_context, (uintptr_t)(restoreregs)) /* SYS call 2: * - * void riscv_switchcontext(uint32_t *saveregs, uint32_t *restoreregs); + * void riscv_switchcontext(uintptr_t *saveregs, uintptr_t *restoreregs); */ #define riscv_switchcontext(saveregs, restoreregs) \ - sys_call2(SYS_switch_context, (uintptr_t)saveregs, (uintptr_t)restoreregs) + sys_call2(SYS_switch_context, (uintptr_t)(saveregs), (uintptr_t)(restoreregs)) #ifdef CONFIG_BUILD_KERNEL /* SYS call 3: diff --git a/arch/risc-v/src/bl602/bl602_irq.c b/arch/risc-v/src/bl602/bl602_irq.c index 9540f793bd..09472a4a8b 100644 --- a/arch/risc-v/src/bl602/bl602_irq.c +++ b/arch/risc-v/src/bl602/bl602_irq.c @@ -40,6 +40,12 @@ #include "chip.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uintptr_t *g_current_regs[1]; + /**************************************************************************** * Private Functions ****************************************************************************/ diff --git a/arch/risc-v/src/bl602/bl602_irq_dispatch.c b/arch/risc-v/src/bl602/bl602_irq_dispatch.c index 10c89cad0d..ee53bd08a4 100644 --- a/arch/risc-v/src/bl602/bl602_irq_dispatch.c +++ b/arch/risc-v/src/bl602/bl602_irq_dispatch.c @@ -35,12 +35,6 @@ #include "riscv_internal.h" #include "chip.h" -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uintptr_t *g_current_regs[1]; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -51,12 +45,12 @@ volatile uintptr_t *g_current_regs[1]; void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs) { - uintptr_t irq = vector & 0x3ff; /* E24 [9:0] */ + int irq = vector & 0x3ff; /* E24 [9:0] */ uintptr_t *mepc = regs; /* If current is interrupt */ - if (vector & 0x80000000u) + if ((vector & RISCV_IRQ_BIT) != 0) { irq += RISCV_IRQ_ASYNC; } @@ -124,7 +118,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs) * switch occurred during interrupt processing. */ - regs = (uintptr_t *)CURRENT_REGS; + regs = (uintptr_t *)CURRENT_REGS; CURRENT_REGS = NULL; return regs; diff --git a/arch/risc-v/src/c906/c906_irq.c b/arch/risc-v/src/c906/c906_irq.c index e315b7456d..c7059be753 100644 --- a/arch/risc-v/src/c906/c906_irq.c +++ b/arch/risc-v/src/c906/c906_irq.c @@ -40,7 +40,7 @@ * Public Data ****************************************************************************/ -volatile uint64_t *g_current_regs[1]; +volatile uintptr_t *g_current_regs[1]; /**************************************************************************** * Public Functions diff --git a/arch/risc-v/src/c906/c906_irq_dispatch.c b/arch/risc-v/src/c906/c906_irq_dispatch.c index c032864b6f..c2bf9662c2 100644 --- a/arch/risc-v/src/c906/c906_irq_dispatch.c +++ b/arch/risc-v/src/c906/c906_irq_dispatch.c @@ -35,6 +35,12 @@ #include "riscv_internal.h" #include "group/group.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RV_IRQ_MASK 59 + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -43,16 +49,16 @@ * riscv_dispatch_irq ****************************************************************************/ -void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs) +void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs) { - uint32_t irq = (vector >> (27 + 32)) | (vector & 0xf); - uint64_t *mepc = regs; + int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf); + uintptr_t *mepc = regs; /* Check if fault happened */ if (vector < RISCV_IRQ_ECALLU) { - riscv_fault((int)irq, regs); + riscv_fault(irq, regs); } /* Firstly, check if the irq is machine external interrupt */ @@ -118,7 +124,7 @@ void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs) #ifdef CONFIG_ARCH_FPU /* Restore floating point registers */ - riscv_restorefpu((uint64_t *)CURRENT_REGS); + riscv_restorefpu((uintptr_t *)CURRENT_REGS); #endif #ifdef CONFIG_ARCH_ADDRENV @@ -141,7 +147,7 @@ void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs) * switch occurred during interrupt processing. */ - regs = (uint64_t *)CURRENT_REGS; + regs = (uintptr_t *)CURRENT_REGS; CURRENT_REGS = NULL; return regs; diff --git a/arch/risc-v/src/common/riscv_swint.c b/arch/risc-v/src/common/riscv_swint.c index 0bff030028..3c4cd53743 100644 --- a/arch/risc-v/src/common/riscv_swint.c +++ b/arch/risc-v/src/common/riscv_swint.c @@ -206,7 +206,7 @@ int riscv_swint(int irq, void *context, void *arg) /* A0=SYS_restore_context: This a restore context command: * * void - * riscv_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + * riscv_fullcontextrestore(uintptr_t *restoreregs) noreturn_function; * * At this point, the following values are saved in context: * @@ -228,7 +228,7 @@ int riscv_swint(int irq, void *context, void *arg) /* A0=SYS_switch_context: This a switch context command: * - * void riscv_switchcontext(uint64_t *saveregs, uint64_t *restoreregs); + * void riscv_switchcontext(uintptr_t *saveregs, uintptr_t *restoreregs); * * At this point, the following values are saved in context: * diff --git a/arch/risc-v/src/fe310/fe310_irq.c b/arch/risc-v/src/fe310/fe310_irq.c index 9e0e17a0e4..1a44ccf4bb 100644 --- a/arch/risc-v/src/fe310/fe310_irq.c +++ b/arch/risc-v/src/fe310/fe310_irq.c @@ -38,6 +38,12 @@ #include "riscv_internal.h" #include "fe310.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uintptr_t *g_current_regs[1]; + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/risc-v/src/fe310/fe310_irq_dispatch.c b/arch/risc-v/src/fe310/fe310_irq_dispatch.c index 906594d8c0..898f1c3157 100644 --- a/arch/risc-v/src/fe310/fe310_irq_dispatch.c +++ b/arch/risc-v/src/fe310/fe310_irq_dispatch.c @@ -37,10 +37,10 @@ #include "fe310.h" /**************************************************************************** - * Public Data + * Pre-processor Definitions ****************************************************************************/ -volatile uintptr_t *g_current_regs[1]; +#define RV_IRQ_MASK 27 /**************************************************************************** * Public Functions @@ -52,7 +52,7 @@ volatile uintptr_t *g_current_regs[1]; void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs) { - uintptr_t irq = (vector >> 27) | (vector & 0xf); + int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf); uintptr_t *mepc = regs; /* Firstly, check if the irq is machine external interrupt */ diff --git a/arch/risc-v/src/k210/k210_irq.c b/arch/risc-v/src/k210/k210_irq.c index 983c6c8611..b01ee914fd 100644 --- a/arch/risc-v/src/k210/k210_irq.c +++ b/arch/risc-v/src/k210/k210_irq.c @@ -40,16 +40,8 @@ * Public Data ****************************************************************************/ -/* For the case of configurations with multiple CPUs, then there must be one - * such value for each processor that can receive an interrupt. - */ - volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS]; -#ifdef CONFIG_SMP -extern int riscv_pause_handler(int irq, void *c, void *arg); -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/risc-v/src/k210/k210_irq_dispatch.c b/arch/risc-v/src/k210/k210_irq_dispatch.c index 5c152dc8f2..7879891b6b 100644 --- a/arch/risc-v/src/k210/k210_irq_dispatch.c +++ b/arch/risc-v/src/k210/k210_irq_dispatch.c @@ -35,6 +35,12 @@ #include "riscv_internal.h" #include "group/group.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RV_IRQ_MASK 59 + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -45,14 +51,14 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs) { - uintptr_t irq = (vector >> (27 + 32)) | (vector & 0xf); + int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf); uintptr_t *mepc = regs; /* Check if fault happened */ if (vector < RISCV_IRQ_ECALLU) { - riscv_fault((int)irq, regs); + riscv_fault(irq, regs); } /* Firstly, check if the irq is machine external interrupt */ diff --git a/arch/risc-v/src/litex/litex_irq.c b/arch/risc-v/src/litex/litex_irq.c index e1df1d3786..7f8978f0bd 100644 --- a/arch/risc-v/src/litex/litex_irq.c +++ b/arch/risc-v/src/litex/litex_irq.c @@ -38,6 +38,12 @@ #include "riscv_internal.h" #include "litex.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uintptr_t *g_current_regs[1]; + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/risc-v/src/litex/litex_irq_dispatch.c b/arch/risc-v/src/litex/litex_irq_dispatch.c index 1a4fe4a0df..309ade1f4c 100644 --- a/arch/risc-v/src/litex/litex_irq_dispatch.c +++ b/arch/risc-v/src/litex/litex_irq_dispatch.c @@ -36,10 +36,10 @@ #include "litex.h" /**************************************************************************** - * Public Data + * Pre-processor Definitions ****************************************************************************/ -volatile uintptr_t *g_current_regs[1]; +#define RV_IRQ_MASK 27 /**************************************************************************** * Public Functions @@ -51,7 +51,7 @@ volatile uintptr_t *g_current_regs[1]; void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs) { - uintptr_t irq = (vector >> 27) | (vector & 0xf); + int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf); uintptr_t *mepc = regs; int i; diff --git a/arch/risc-v/src/mpfs/mpfs_irq_dispatch.c b/arch/risc-v/src/mpfs/mpfs_irq_dispatch.c index c6c4be7cde..1e420c0c78 100755 --- a/arch/risc-v/src/mpfs/mpfs_irq_dispatch.c +++ b/arch/risc-v/src/mpfs/mpfs_irq_dispatch.c @@ -48,10 +48,10 @@ * riscv_dispatch_irq ****************************************************************************/ -void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs) +void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs) { - uint32_t irq = (vector & 0x3f); - uint64_t *mepc = regs; + int irq = (vector & 0x3f); + uintptr_t *mepc = regs; board_autoled_on(LED_INIRQ); @@ -63,10 +63,10 @@ void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs) vector == RISCV_IRQ_SROREPF || vector == RISCV_IRQ_RESERVED) { - riscv_fault((int)irq, regs); + riscv_fault(irq, regs); } - if (vector & 0x8000000000000000) + if ((vector & RISCV_IRQ_BIT) != 0) { irq += MPFS_IRQ_ASYNC; } @@ -136,7 +136,7 @@ void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs) #ifdef CONFIG_ARCH_FPU /* Restore floating point registers */ - riscv_restorefpu((uint64_t *)CURRENT_REGS); + riscv_restorefpu((uintptr_t *)CURRENT_REGS); #endif #ifdef CONFIG_ARCH_ADDRENV @@ -159,7 +159,7 @@ void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs) * switch occurred during interrupt processing. */ - regs = (uint64_t *)CURRENT_REGS; + regs = (uintptr_t *)CURRENT_REGS; CURRENT_REGS = NULL; board_autoled_off(LED_INIRQ); diff --git a/arch/risc-v/src/mpfs/mpfs_timerisr.c b/arch/risc-v/src/mpfs/mpfs_timerisr.c index 1008205ce5..b9db1e760d 100755 --- a/arch/risc-v/src/mpfs/mpfs_timerisr.c +++ b/arch/risc-v/src/mpfs/mpfs_timerisr.c @@ -47,8 +47,8 @@ * Private Data ****************************************************************************/ -static bool _b_tick_started = false; -static uint64_t *_mtime_cmp = 0L; +static bool _b_tick_started; +static uint64_t *_mtime_cmp; /**************************************************************************** * Private Functions diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_irq.c b/arch/risc-v/src/qemu-rv/qemu_rv_irq.c index a309cf8109..36c4e89d41 100644 --- a/arch/risc-v/src/qemu-rv/qemu_rv_irq.c +++ b/arch/risc-v/src/qemu-rv/qemu_rv_irq.c @@ -38,6 +38,12 @@ #include "riscv_internal.h" #include "chip.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS]; + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c b/arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c index 61b6621e01..3a3a79988b 100644 --- a/arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c +++ b/arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c @@ -46,12 +46,6 @@ # define RV_IRQ_MASK 59 #endif -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS]; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -62,7 +56,7 @@ volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS]; void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs) { - uintptr_t irq = (vector >> RV_IRQ_MASK) | (vector & 0xf); + int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf); uintptr_t *mepc = regs; if (vector < RISCV_IRQ_ECALLM) diff --git a/arch/risc-v/src/rv32m1/rv32m1_irq.c b/arch/risc-v/src/rv32m1/rv32m1_irq.c index 7692a0b298..2dc5d13e79 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_irq.c +++ b/arch/risc-v/src/rv32m1/rv32m1_irq.c @@ -38,6 +38,12 @@ #include "rv32m1.h" #include "hardware/rv32m1_eu.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uintptr_t *g_current_regs[1]; + /**************************************************************************** * Private Functions ****************************************************************************/ diff --git a/arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c b/arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c index e5bf557de9..077c78a2b2 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c +++ b/arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c @@ -37,10 +37,10 @@ #include "hardware/rv32m1_eu.h" /**************************************************************************** - * Public Data + * Pre-processor Definitions ****************************************************************************/ -volatile uintptr_t *g_current_regs[1]; +#define RV_IRQ_MASK 27 /**************************************************************************** * Public Functions @@ -53,10 +53,9 @@ volatile uintptr_t *g_current_regs[1]; LOCATE_ITCM void *rv32m1_dispatch_irq(uintptr_t vector, uintptr_t *regs) { - uintptr_t vec = vector & 0x1f; - uintptr_t irq = (vector >> 27) + vec; + uint32_t vec = vector & 0x1f; + int irq = (vector >> RV_IRQ_MASK) + vec; uintptr_t *mepc = regs; - int irqofs = 0; /* NOTE: In case of ecall, we need to adjust mepc in the context */