i.MX6: Add a system timer based on the i.MX6 GPT
This commit is contained in:
Gregory Nutt
parent
725e6878c4
commit
7b0a696498
@ -19,6 +19,13 @@ config ARMV7A_HAVE_GTM
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Selected by the configuration tool if the architecture supports the
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Global Timer (GTM)
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config ARMV7A_HAVE_PTM
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bool
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default n
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---help---
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Selected by the configuration tool if the architecture supports the
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per-processor Private Timers (PTMs)
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config ARMV7A_HAVE_L2CC
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bool
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default n
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@ -22,18 +22,21 @@ config ARCH_CHIP_IMX6_6DUALLITE
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select ARCH_HAVE_MULTICPU
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select ARMV7A_HAVE_GIC
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select ARMV7A_HAVE_GTM
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select ARMV7A_HAVE_PTM
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config ARCH_CHIP_IMX6_6DUAL
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bool "i.MX 6Dual"
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select ARCH_HAVE_MULTICPU
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select ARMV7A_HAVE_GIC
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select ARMV7A_HAVE_GTM
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select ARMV7A_HAVE_PTM
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config ARCH_CHIP_IMX6_6QUAD
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bool "i.MX 6Quad"
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select ARCH_HAVE_MULTICPU
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select ARMV7A_HAVE_GIC
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select ARMV7A_HAVE_GTM
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select ARMV7A_HAVE_PTM
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endchoice # iMX.6 Chip Selection
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@ -133,4 +133,5 @@ CHIP_ASRCS =
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# i.MX6-specific C source files
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CHIP_CSRCS = imx_boot.c imx_memorymap.c imx_clockconfig.c imx_irq.c
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CHIP_CSRCS += imx_gpio.c imx_iomuxc.c imx_serial.c imx_lowputc.c
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CHIP_CSRCS += imx_timerisr.c imx_gpio.c imx_iomuxc.c
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CHIP_CSRCS += imx_serial.c imx_lowputc.c
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@ -148,6 +148,8 @@
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#define GPT_INT_IF2 (1 << 4) /* Bit 4: IF2 Input capture 2 Flag */
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#define GPT_INT_ROV (1 << 5) /* Bit 5: Rollover flag */
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#define GPT_INT_ALL 0x0000003f
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/* GPT Output Compare Register 1,2,3 -- 32-bit compare registers */
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/* GPT Input Capture Register 1,2 -- 32-bit capture registers */
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/* GPT Counter Register -- 32-bit counter */
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236
arch/arm/src/imx6/imx_timerisr.c
Normal file
236
arch/arm/src/imx6/imx_timerisr.c
Normal file
@ -0,0 +1,236 @@
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/****************************************************************************
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* arch/arm/src/imx6/imx_timerisr.c
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <time.h>
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#include <nuttx/arch.h>
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#include <arch/irq.h>
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#include "up_arch.h"
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#include "chip/imx_gpt.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* The Peripheral Clock (ipg_clk) is selected as the GPT clock source. NOTE
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* that the ipg_clk may be turned off in low power modes, stopping the timer
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* which is probably what you want.
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*
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* REVISIT: Here we assume that the Peripheral Clock is 66MHz. That is:
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*
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* PLL528 -> CBCDR: ahb_podf -> CBCDR: ipg_podf ->ipg_clk_root
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* 3-bit timer 3-bit timer
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* default=4 default=2
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*
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* So, Peripheral Clock Frequency = 528 / 4 / 2 = 66 MHz
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*/
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#define GPT_CLOCK 66000000
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#define GPT_CLKSRC_VALUE GPT_CR_CLKSRC_PERIPHCLK
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/* The desired timer interrupt frequency is provided by the definition
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* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
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* system clock ticks per second. That value is a user configurable setting
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* that defaults to 100 (100 ticks per second = 10 MS interval).
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*
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* We should be able to use a prescaler of 1.
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*/
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#define GPT_PR_VALUE 1
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#define GPT_OCR3_VALUE ((GPT_CLOCK + ((1*CLK_TCK) >> 1)) / (1*CLK_TCK))
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#define GPT_OCR2_VALUE ((GPT_CLOCK + ((2*CLK_TCK) >> 1)) / (2*CLK_TCK))
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#define GPT_OCR1_VALUE ((GPT_CLOCK + ((3*CLK_TCK) >> 1)) / (3*CLK_TCK))
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Function: up_output_compare
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*
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* Description:
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* Handle one pending output compare interrupt.
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*
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****************************************************************************/
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static void up_output_compare(uint32_t sr, uint32_t of)
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{
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/* Check for a pending output compare interrupt */
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if ((sr & of) != 0)
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{
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/* Clear the pending output compare interrupt */
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putreg32(of, IMX_GPT_SR);
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/* Process timer interrupt event */
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sched_process_timer();
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}
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Function: up_timerisr
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*
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* Description:
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* The timer ISR will perform a variety of services for various portions
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* of the systems.
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*
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****************************************************************************/
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int up_timerisr(int irq, uint32_t *regs)
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{
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/* Sample the SR (once) and process all pending output compare interrupt */
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uint32_t sr = getreg32(IMX_GPT_SR);
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up_output_compare(sr, GPT_INT_OF1);
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up_output_compare(sr, GPT_INT_OF2);
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up_output_compare(sr, GPT_INT_OF3);
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return OK;
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}
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/****************************************************************************
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* Function: up_timer_initialize
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*
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* Description:
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* This function is called during start-up to initialize
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* the timer interrupt.
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*
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****************************************************************************/
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void up_timer_initialize(void)
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{
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uint32_t cr;
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/* Disable GPT interrupts at the GIC */
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up_disable_irq(IMX_IRQ_GPT);
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/* Disable GPT by setting EN=0 in GPT_CR register */
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cr = getreg32(IMX_GPT_CR);
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cr &= ~GPT_CR_EN;
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putreg32(cr, IMX_GPT_CR);
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/* Disable GPT interrupt register (GPT_IR) */
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putreg32(0, IMX_GPT_IR);
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/* Configure Output Mode to unconnected/ disconnected—Write zeros in OM3,
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* OM2, and OM1 in GPT_CR.
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*/
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cr &= ~(GPT_CR_OM1_MASK | GPT_CR_OM2_MASK | GPT_CR_OM3_MASK);
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cr |= (GPT_CR_OM1_DISCON | GPT_CR_OM2_DISCON | GPT_CR_OM3_DISCON);
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putreg32(cr, IMX_GPT_CR);
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/* Disable Input Capture Modes—Write zeros in IM1 and IM2 in GPT_CR */
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cr &= ~(GPT_CR_IM1_MASK | GPT_CR_IM2_MASK);
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cr |= (GPT_CR_IM1_DISABLED | GPT_CR_IM2_DISABLED);
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putreg32(cr, IMX_GPT_CR);
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/* Change clock source CLKSRC to the desired value in GPT_CR register */
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cr &= ~GPT_CR_CLKSRC_MASK;
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cr |= GPT_CLKSRC_VALUE;
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putreg32(cr, IMX_GPT_CR);
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/* Assert the SWR bit in GPT_CR register. The SWR bit is cleared when the
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* reset procedure finishes. Setting the SWR bit resets all of the
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* registers to their default reset values, except for the CLKSRC, EN,
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* ENMOD, STOPEN, WAITEN, and DBGEN bits in the GPT Control Register.
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*/
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putreg32(cr | GPT_CR_SWR, IMX_GPT_CR);
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/* Clear GPT status register */
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putreg32(GPT_INT_ALL, IMX_GPT_SR);
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/* Configure the prescaler and output compare registers */
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putreg32(GPT_OCR1_VALUE, IMX_GPT_OCR1);
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putreg32(GPT_OCR2_VALUE, IMX_GPT_OCR2);
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putreg32(GPT_OCR3_VALUE, IMX_GPT_OCR3);
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putreg32(GPT_PR_VALUE - 1, IMX_GPT_PR);
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/* Configure restart mode. Interrupts will be received on OC3, then OC2,
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* then OC1 when the counter will be reset to zero and the whole sequence
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* starts again.
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*
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* FFR=0: Restart mode
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*/
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cr &= ~GPT_CR_FFR;
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putreg32(cr | GPT_CR_SWR, IMX_GPT_CR);
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/* Set ENMOD=1 in GPT_CR register, to bring GPT counter to 0x00000000. If
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* the ENMOD bit is 1, then the Main Counter and Prescaler Counter values
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* are reset to 0 *after* GPT is enabled (EN=1).
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*/
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cr |= GPT_CR_ENMOD;
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putreg32(cr, IMX_GPT_CR);
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/* Enable GPT (EN=1) in GPT_CR register */
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cr |= GPT_CR_EN;
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putreg32(cr, IMX_GPT_CR);
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/* Attach the timer interrupt vector */
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(void)irq_attach(IMX_IRQ_GPT, (xcpt_t)up_timerisr);
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/* Enable all three GPT output compare interrupts */
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putreg32(GPT_INT_OF1 | GPT_INT_OF2 | GPT_INT_OF3, IMX_GPT_IR);
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/* And enable the timer interrupt at the GIC */
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up_enable_irq(IMX_IRQ_GPT);
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}
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