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esp32_spiflash.c: Allocate only one variable to hold the cache state in

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single CPU mode.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit is contained in:
Abdelatif Guettouche 2021-10-13 12:44:53 +02:00 committed by Xiang Xiao
parent f54a929001
commit 7b43d11435
1 changed files with 7 additions and 1 deletions
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8
arch/xtensa/src/esp32/esp32_spiflash.c
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@ -59,6 +59,12 @@
* Pre-processor Definitions
****************************************************************************/
/* Used in spiflash_cachestate_s structure even when SMP is disabled. */
#ifndef CONFIG_SMP_NCPUS
# define CONFIG_SMP_NCPUS 1
#endif
#define SPI_FLASH_WRITE_BUF_SIZE (32)
#define SPI_FLASH_READ_BUF_SIZE (64)
@ -165,7 +171,7 @@ struct spiflash_cachestate_s
int other;
#endif
irqstate_t flags;
uint32_t val[2];
uint32_t val[CONFIG_SMP_NCPUS];
};
/****************************************************************************