arch:xtensa: add xtensa_cache code support
Add xtensa_cache code support
This commit is contained in:
zhuyanlin
Xiang Xiao
parent
d6fe0f18f5
commit
7b5c39a9d3
469
arch/xtensa/src/common/xtensa_cache.c
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469
arch/xtensa/src/common/xtensa_cache.c
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/****************************************************************************
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* arch/xtensa/src/common/xtensa_cache.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/cache.h>
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#include <arch/chip/core-isa.h>
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#include <arch/xtensa/xtensa_corebits.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Inline Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_enable_icache
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*
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* Description:
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* Enable the I-Cache
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_XTENSA_ICACHE
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void up_enable_icache(void)
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{
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uint32_t memctl = 0;
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__asm__ __volatile__ ("rsr %0, memctl\n" : "=r"(memctl) :);
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memctl &= ~MEMCTL_ICWU_MASK;
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memctl |= (XCHAL_ICACHE_WAYS << MEMCTL_ICWU_SHIFT);
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memctl |= MEMCTL_INV_EN;
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__asm__ __volatile__ ("wsr %0, memctl\n" : : "r"(memctl));
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}
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#endif
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/****************************************************************************
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* Name: up_disable_icache
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*
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* Description:
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* Disable the I-Cache
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_XTENSA_ICACHE
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void up_disable_icache(void)
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{
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uint32_t memctl = 0;
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__asm__ __volatile__ ("rsr %0, memctl\n" : "=r"(memctl) :);
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memctl &= ~MEMCTL_ICWU_MASK;
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memctl |= MEMCTL_INV_EN;
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__asm__ __volatile__ ("wsr %0, memctl\n" : : "r"(memctl));
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}
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#endif
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/****************************************************************************
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* Name: up_invalidate_icache
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*
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* Description:
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* Invalidate the instruction cache within the specified region.
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*
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* Input Parameters:
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* start - virtual start address of region
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* end - virtual end address of region + 1
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*
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* Returned Value:
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*
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****************************************************************************/
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#ifdef CONFIG_XTENSA_ICACHE
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void up_invalidate_icache(uint32_t start, uint32_t end)
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{
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/* align to XCHAL_ICACHE_SIZE */
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uint32_t addr = start - (start & (XCHAL_ICACHE_LINESIZE - 1));
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for (; addr < end; addr += XCHAL_ICACHE_LINESIZE)
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{
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__asm__ __volatile__ ("ihi %0, 0\n" : : "r"(addr));
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}
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__asm__ __volatile__ ("isync\n");
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}
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#endif
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/****************************************************************************
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* Name: up_invalidate_icache_all
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*
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* Description:
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* Invalidate the entire contents of I cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_XTENSA_ICACHE
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void up_invalidate_icache_all(void)
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{
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uint32_t index;
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for (index = 0; index < XCHAL_ICACHE_SIZE; index += XCHAL_ICACHE_LINESIZE)
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{
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__asm__ __volatile__ ("iii %0, 0\n": : "r"(index));
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};
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__asm__ __volatile__ ("isync\n");
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}
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#endif
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/****************************************************************************
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* Name: up_enable_dcache
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*
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* Description:
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* Enable the D-Cache
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_XTENSA_DCACHE
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void up_enable_dcache(void)
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{
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uint32_t memctl = 0;
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__asm__ __volatile__ ("rsr %0, memctl\n" : "=r"(memctl) :);
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/* set ways allocatable & ways use */
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memctl = memctl & ~(MEMCTL_DCWA_MASK | MEMCTL_DCWU_MASK);
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memctl |= (XCHAL_DCACHE_WAYS << MEMCTL_DCWA_SHIFT);
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memctl |= (XCHAL_DCACHE_WAYS << MEMCTL_DCWU_SHIFT);
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memctl |= MEMCTL_INV_EN;
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__asm__ __volatile__ ("wsr %0, memctl\n" : : "r"(memctl));
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}
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#endif
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/****************************************************************************
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* Name: up_disable_dcache
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*
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* Description:
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* Disable the D-Cache
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_XTENSA_DCACHE
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void up_disable_dcache(void)
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{
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uint32_t memctl = 0;
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__asm__ __volatile__ ("rsr %0, memctl\n" : "=r"(memctl) :);
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/* clear ways allocatable & ways use */
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memctl = memctl & ~(MEMCTL_DCWA_MASK | MEMCTL_DCWU_MASK);
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memctl |= MEMCTL_INV_EN;
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__asm__ __volatile__ ("wsr %0, memctl\n" : : "r"(memctl));
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}
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#endif
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/****************************************************************************
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* Name: up_invalidate_dcache
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*
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* Description:
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* Invalidate the data cache within the specified region; we will be
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* performing a DMA operation in this region and we want to purge old data
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* in the cache. Note that this function invalidates all cache ways
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* in sets that could be associated with the address range, regardless of
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* whether the address range is contained in the cache or not.
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*
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* Input Parameters:
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* start - virtual start address of region
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* end - virtual end address of region + 1
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* This operation is not atomic. This function assumes that the caller
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* has exclusive access to the address range so that no harm is done if
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* the operation is pre-empted.
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*
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****************************************************************************/
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#ifdef CONFIG_XTENSA_DCACHE
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void up_invalidate_dcache(uintptr_t start, uintptr_t end)
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{
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/* Align to XCHAL_DCACHE_LINESIZE */
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uint32_t addr = start - (start & (XCHAL_DCACHE_LINESIZE - 1));
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for (; addr < end; addr += XCHAL_DCACHE_LINESIZE)
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{
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__asm__ __volatile__ ("dhi %0, 0\n" : : "r"(addr));
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}
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__asm__ __volatile__ ("dsync\n");
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}
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#endif
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/****************************************************************************
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* Name: up_invalidate_dcache_all
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*
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* Description:
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* Invalidate the entire contents of D cache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_XTENSA_DCACHE
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void up_invalidate_dcache_all(void)
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{
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uint32_t index;
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for (index = 0; index < XCHAL_DCACHE_SIZE; index += XCHAL_DCACHE_LINESIZE)
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{
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__asm__ __volatile__ ("dii %0, 0\n" : : "r"(index));
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};
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__asm__ __volatile__ ("dsync\n");
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}
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#endif
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/****************************************************************************
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* Name: up_clean_dcache
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*
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* Description:
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* Clean the data cache within the specified region by flushing the
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* contents of the data cache to memory.
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*
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* NOTE: This operation is un-necessary if the DCACHE is configured in
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* write-through mode.
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*
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* Input Parameters:
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* start - virtual start address of region
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* end - virtual end address of region + 1
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* This operation is not atomic. This function assumes that the caller
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* has exclusive access to the address range so that no harm is done if
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* the operation is pre-empted.
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*
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****************************************************************************/
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#ifdef CONFIG_XTENSA_DCACHE
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void up_clean_dcache(uintptr_t start, uintptr_t end)
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{
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/* Align to XCHAL_DCACHE_SIZE */
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uint32_t addr = start - (start & (XCHAL_DCACHE_SIZE - 1));
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for (; addr < end; addr += XCHAL_DCACHE_SIZE)
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{
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__asm__ __volatile__ ("dhwb %0, 0\n" : : "r"(addr));
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}
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__asm__ __volatile__ ("dsync\n");
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}
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#endif
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/****************************************************************************
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* Name: up_clean_dcache_all
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*
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* Description:
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* Clean the entire data cache within the specified region by flushing the
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* contents of the data cache to memory.
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*
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* NOTE: This operation is un-necessary if the DCACHE is configured in
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* write-through mode.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* This operation is not atomic. This function assumes that the caller
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* has exclusive access to the address range so that no harm is done if
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* the operation is pre-empted.
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*
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****************************************************************************/
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#ifdef CONFIG_XTENSA_DCACHE
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void up_clean_dcache_all(void)
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{
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uint32_t index;
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for (index = 0; index < XCHAL_DCACHE_SIZE; index += XCHAL_DCACHE_LINESIZE)
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{
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__asm__ __volatile__ ("diwb %0, 0\n" : : "r"(index));
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};
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__asm__ __volatile__ ("dsync\n");
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}
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#endif
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/****************************************************************************
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* Name: up_flush_dcache
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*
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* Description:
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* Flush the data cache within the specified region by cleaning and
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* invalidating the D cache.
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*
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* NOTE: If DCACHE write-through is configured, then this operation is the
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* same as up_invalidate_cache().
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*
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* Input Parameters:
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* start - virtual start address of region
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* end - virtual end address of region + 1
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* This operation is not atomic. This function assumes that the caller
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* has exclusive access to the address range so that no harm is done if
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* the operation is pre-empted.
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*
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****************************************************************************/
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#ifdef CONFIG_XTENSA_DCACHE
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void up_flush_dcache(uintptr_t start, uintptr_t end)
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{
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/* Align to XCHAL_DCACHE_LINESIZE */
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uint32_t addr = start - (start & (XCHAL_DCACHE_LINESIZE - 1));
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for (; addr < end; addr += XCHAL_DCACHE_LINESIZE)
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{
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__asm__ __volatile__ ("dhwbi %0, 0\n" : : "r"(addr));
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}
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__asm__ __volatile__ ("dsync\n");
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}
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#endif
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/****************************************************************************
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* Name: up_flush_dcache_all
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*
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* Description:
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* Flush the entire data cache by cleaning and invalidating the D cache.
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*
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* NOTE: If DCACHE write-through is configured, then this operation is the
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* same as up_invalidate_cache_all().
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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* Assumptions:
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* This operation is not atomic. This function assumes that the caller
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* has exclusive access to the address range so that no harm is done if
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* the operation is pre-empted.
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*
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****************************************************************************/
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#ifdef CONFIG_XTENSA_DCACHE
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void up_flush_dcache_all(void)
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{
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uint32_t index;
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for (index = 0; index < XCHAL_ICACHE_SIZE; index += XCHAL_DCACHE_LINESIZE)
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{
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__asm__ __volatile__ ("diwbi %0, 0\n" : : "r"(index));
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};
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__asm__ __volatile__ ("dsync\n");
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}
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#endif
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/****************************************************************************
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* Name: up_coherent_dcache
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*
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* Description:
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* Ensure that the I and D caches are coherent within specified region
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* by cleaning the D cache (i.e., flushing the D cache contents to memory)
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* and invalidating the I cache. This is typically used when code has been
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* written to a memory region, and will be executed.
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*
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* Input Parameters:
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* addr - virtual start address of region
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* len - Size of the address region in bytes
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#if defined(CONFIG_XTENSA_ICACHE) && defined(CONFIG_XTENSA_DCACHE)
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void up_coherent_dcache(uintptr_t addr, size_t len)
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{
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if (len > 0)
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{
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up_clean_dcache(addr, addr + len);
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up_invalidate_icache(addr, add + len);
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}
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}
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#endif
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