diff --git a/arch/arm/src/sama5/sam_dmac.c b/arch/arm/src/sama5/sam_dmac.c
index da58c2971c..f332db7152 100644
--- a/arch/arm/src/sama5/sam_dmac.c
+++ b/arch/arm/src/sama5/sam_dmac.c
@@ -1487,11 +1487,13 @@ static void sam_freelinklist(struct sam_dmach_s *dmach)
 
       DEBUGASSERT(desc->saddr != 0);
 
-      /* Get the physical address of the next desriptor in the list */
+      /* Get the physical address of the next descriptor in the list */
 
       paddr = desc->dscr;
 
-      /* Free the descriptor by simply nullifying it */
+      /* Free the descriptor by simply nullifying it and bumping up the
+       * semaphore count.
+       */
 
       memset(desc, 0, sizeof(struct dma_linklist_s));
       sam_givedsem(dmac);
diff --git a/configs/sama5d3x-ek/README.txt b/configs/sama5d3x-ek/README.txt
index 4c14af7d3e..390fb1b5ba 100644
--- a/configs/sama5d3x-ek/README.txt
+++ b/configs/sama5d3x-ek/README.txt
@@ -1358,9 +1358,9 @@ NAND Support
   verified, but there is no way to use it in the current NuttX architecture
   other than through the raw MTD interface.
 
-  NAND should be considered a work in progress.  You will not want to use
-  NAND unless you are interested in investing a little effort, particularly
-  in infrastructure. See the "STATUS SUMMARY" section below.
+  NAND should still be considered a work in progress.  You will not want to
+  use NAND unless you are interested in investing a little effort,
+  particularly in infrastructure. See the "STATUS SUMMARY" section below.
 
   NAND Support
   ------------
@@ -1652,13 +1652,12 @@ NAND Support
      work correctly:  The MBR is written and read back correctly, but gets
      corrupted later for unknown reasons.
 
-  2. DMA works (with software ECC), but I have seen occasional failurs.  I
-     believe that these issue have been resolved but I recommend enabling
-     DMA with caution.
+  2. DMA works (at least with software ECC), but I have seen occasional
+     failures.  I recommend enabling DMA with caution.
 
      In NuttX, DMA will also cost two context switches (and, hence, four
      register state transfers).  With smaller NAND page sizes (say 2KiB and
-     below), I would not expect a great  performance improvement with DMA
+     below), I would expect little or no performance improvement with DMA
      for this reason.
 
   3. NXFFS does not work with NAND. NAND differs from other other FLASH