Merged in jjlange/nuttx/mx25l_4B (pull request #1016)
Add support for 4-byte addressing on >128Mb Macronix flash parts
* Save CONFIG_ARCH_BOARD_CUSTOM when running 'make savedefconfig'
* Only use PCLKSEL0 for ADC on LPC176x family.
* Made grep search expression more specific.
* Added missing '=' to second grep
* Revert "Only use PCLKSEL0 for ADC on LPC176x family."
This reverts commit 835b5e9d6fcbea02cb0203c063b0e121fa57ba9e.
* Revert "Added missing '=' to second grep"
This reverts commit 38b51f0c6d9612de755c102a53846ca7488cdf14.
* Added a missing '=' in the second grep statement
* Added support for 4-byte addressing on >128Mb Macronix flash parts
Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
jjlange
Gregory Nutt
parent
6ddd4752b0
commit
7b6cff6f84
@ -100,6 +100,11 @@
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#define MX25L_MX25L25635F_NSECTORS 8192
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#define MX25L_MX25L25635F_PAGE_SHIFT 8 /* Page size 1 << 8 = 256 */
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/* Parts larger than 128Mbit require 4-byte addressing */
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#define MX25L_ADDRESSBYTES_3 3
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#define MX25L_ADDRESSBYTES_4 4
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#ifdef CONFIG_MX25L_SECTOR512 /* Simulate a 512 byte sector */
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# define MX25L_SECTOR512_SHIFT 9 /* Sector size 1 << 9 = 512 bytes */
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#endif
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@ -122,46 +127,59 @@
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#define CLR_DIRTY(p) do { (p)->flags &= ~MX25L_CACHE_DIRTY; } while (0)
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#define CLR_ERASED(p) do { (p)->flags &= ~MX25L_CACHE_ERASED; } while (0)
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/* MX25L Instructions *****************************************************************/
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/* Command Value Description Addr Data */
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/* Dummy */
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#define MX25L_READ 0x03 /* Read data bytes 3 0 >=1 */
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#define MX25L_FAST_READ 0x0b /* Higher speed read 3 1 >=1 */
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#define MX25L_2READ 0xbb /* 2 x I/O read command */
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#define MX25L_DREAD 0x3b /* 1I / 2O read command 3 1 >=1 */
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#define MX25L_4READ 0xeb /* 4 x I/O read command */
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#define MX25L_QREAD 0x6b /* 1I / 4O read command 3 1 >=1 */
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#define MX25L_WREN 0x06 /* Write Enable 0 0 0 */
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#define MX25L_WRDI 0x04 /* Write Disable 0 0 0 */
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#define MX25L_RDSR 0x05 /* Read status register 0 0 >=1 */
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#define MX25L_RDCR 0x15 /* Read config register 0 0 >=1 */
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#define MX25L_WRSR 0x01 /* Write stat/conf register 0 0 2 */
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#define MX25L_4PP 0x38 /* Quad page program 3 0 1-256 */
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#define MX25L_SE 0x20 /* 4Kb Sector erase 3 0 0 */
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#define MX25L_BE32 0x52 /* 32Kbit block Erase 3 0 0 */
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#define MX25L_BE64 0xd8 /* 64Kbit block Erase 3 0 0 */
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#define MX25L_CE 0xc7 /* Chip erase 0 0 0 */
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#define MX25L_CE_ALT 0x60 /* Chip erase (alternate) 0 0 0 */
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#define MX25L_PP 0x02 /* Page program 3 0 1-256 */
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#define MX25L_DP 0xb9 /* Deep power down 0 0 0 */
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#define MX25L_RDP 0xab /* Release deep power down 0 0 0 */
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#define MX25L_PGM_SUSPEND 0x75 /* Suspends program 0 0 0 */
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#define MX25L_ERS_SUSPEND 0xb0 /* Suspends erase 0 0 0 */
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#define MX25L_PGM_RESUME 0x7A /* Resume program 0 0 0 */
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#define MX25L_ERS_RESUME 0x30 /* Resume erase 0 0 0 */
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#define MX25L_RDID 0x9f /* Read identification 0 0 3 */
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#define MX25L_RES 0xab /* Read electronic ID 0 3 1 */
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#define MX25L_REMS 0x90 /* Read manufacture and ID 1 2 >=2 */
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#define MX25L_ENSO 0xb1 /* Enter secured OTP 0 0 0 */
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#define MX25L_EXSO 0xc1 /* Exit secured OTP 0 0 0 */
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#define MX25L_RDSCUR 0x2b /* Read security register 0 0 0 */
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#define MX25L_WRSCUR 0x2f /* Write security register 0 0 0 */
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#define MX25L_RSTEN 0x66 /* Reset Enable 0 0 0 */
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#define MX25L_RST 0x99 /* Reset Memory 0 0 0 */
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/* MX25L Instructions *******************************************************************/
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/* Command Value Description Addr Data */
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/* Dummy */
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#define MX25L_READ 0x03 /* Read data bytes 3/4 0 >=1 */
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#define MX25L_FAST_READ 0x0b /* Higher speed read 3/4 1 >=1 */
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#define MX25L_2READ 0xbb /* 2 x I/O read command */
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#define MX25L_DREAD 0x3b /* 1I / 2O read command 3/4 1 >=1 */
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#define MX25L_4READ 0xeb /* 4 x I/O read command */
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#define MX25L_QREAD 0x6b /* 1I / 4O read command 3/4 1 >=1 */
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#define MX25L_WREN 0x06 /* Write Enable 0 0 0 */
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#define MX25L_WRDI 0x04 /* Write Disable 0 0 0 */
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#define MX25L_RDSR 0x05 /* Read status register 0 0 >=1 */
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#define MX25L_RDCR 0x15 /* Read config register 0 0 >=1 */
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#define MX25L_WRSR 0x01 /* Write stat/conf register 0 0 2 */
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#define MX25L_4PP 0x38 /* Quad page program 3/4 0 1-256 */
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#define MX25L_SE 0x20 /* 4Kb Sector erase 3/4 0 0 */
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#define MX25L_BE32 0x52 /* 32Kbit block Erase 3/4 0 0 */
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#define MX25L_BE64 0xd8 /* 64Kbit block Erase 3/4 0 0 */
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#define MX25L_CE 0xc7 /* Chip erase 0 0 0 */
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#define MX25L_CE_ALT 0x60 /* Chip erase (alternate) 0 0 0 */
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#define MX25L_PP 0x02 /* Page program 3 0 1-256 */
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#define MX25L_DP 0xb9 /* Deep power down 0 0 0 */
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#define MX25L_RDP 0xab /* Release deep power down 0 0 0 */
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#define MX25L_PGM_SUSPEND 0x75 /* Suspends program 0 0 0 */
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#define MX25L_ERS_SUSPEND 0xb0 /* Suspends erase 0 0 0 */
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#define MX25L_PGM_RESUME 0x7A /* Resume program 0 0 0 */
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#define MX25L_ERS_RESUME 0x30 /* Resume erase 0 0 0 */
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#define MX25L_RDID 0x9f /* Read identification 0 0 3 */
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#define MX25L_RES 0xab /* Read electronic ID 0 3 1 */
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#define MX25L_REMS 0x90 /* Read manufacture and ID 1 2 >=2 */
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#define MX25L_ENSO 0xb1 /* Enter secured OTP 0 0 0 */
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#define MX25L_EXSO 0xc1 /* Exit secured OTP 0 0 0 */
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#define MX25L_RDSCUR 0x2b /* Read security register 0 0 0 */
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#define MX25L_WRSCUR 0x2f /* Write security register 0 0 0 */
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#define MX25L_RSTEN 0x66 /* Reset Enable 0 0 0 */
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#define MX25L_RST 0x99 /* Reset Memory 0 0 0 */
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#define MX25L_EN4B 0xb7 /* Enter 4-byte mode 0 0 0 */
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#define MX25L_EX4B 0xe9 /* Exit 4-byte mode 0 0 0 */
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#define MX25L_READ4B 0x13 /* Read data (4 Byte mode) 4 0 >=1 */
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#define MX25L_FAST_READ4B 0x0c /* Higher speed read (4B) 4 1 >=1 */
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#define MX25L_2READ4B 0xbc /* 2 x I/O read command (4B) */
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#define MX25L_DREAD4B 0x3c /* 1I / 2O read command (4B) 4 1 >=1 */
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#define MX25L_4READ4B 0xec /* 4 x I/O read command (4B) */
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#define MX25L_QREAD4B 0x6c /* 1I / 4O read command (4B) 4 1 >=1 */
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#define MX25L_4PP4B 0x3e /* Quad page program (4B) 4 0 1-256 */
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#define MX25L_SE4B 0x21 /* 4Kb Sector erase (4B) 4 0 0 */
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#define MX25L_BE32K4B 0x5c /* 32Kbit block Erase (4B) 4 0 0 */
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#define MX25L_BE64K4B 0xdc /* 64Kbit block Erase (4B) 4 0 0 */
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#define MX25L_PP4B 0x12 /* Page program (4B) 4 0 1-256 */
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#define MX25L_RDSFDP 0x5a /* read out until CS# high */
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#define MX25L_SBL 0xc0 /* Set Burst Length */
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#define MX25L_SBL_ALT 0x77 /* Set Burst Length */
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#define MX25L_NOP 0x00 /* No Operation 0 0 0 */
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#define MX25L_NOP 0x00 /* No Operation 0 0 0 */
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/* MX25L Registers ******************************************************************/
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/* Read ID (RDID) register values */
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@ -186,7 +204,7 @@
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#define MX25L_SR_QE (1 << 6) /* Bit 6: Quad enable */
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#define MX25L_SR_SRWD (1 << 7) /* Bit 7: Status register write protect */
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/* Configuration registerregister bit definitions */
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/* Configuration register bit definitions */
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#define MX25L_CR_ODS (1 << 0) /* Bit 0: Output driver strength */
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#define MX25L_CR_TB (1 << 3) /* Bit 3: Top/bottom selected */
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@ -219,6 +237,7 @@ struct mx25l_dev_s
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FAR struct spi_dev_s *dev; /* Saved SPI interface instance */
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uint8_t sectorshift;
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uint8_t pageshift;
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uint8_t addressbytes; /*Number of address bytes required */
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uint16_t nsectors;
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#if defined(CONFIG_MX25L_SECTOR512)
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uint8_t flags; /* Buffered sector flags */
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@ -349,27 +368,30 @@ static inline int mx25l_readid(FAR struct mx25l_dev_s *priv)
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{
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/* Save the FLASH geometry */
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priv->sectorshift = MX25L_MX25L3233F_SECTOR_SHIFT;
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priv->nsectors = MX25L_MX25L3233F_NSECTORS;
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priv->pageshift = MX25L_MX25L3233F_PAGE_SHIFT;
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priv->sectorshift = MX25L_MX25L3233F_SECTOR_SHIFT;
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priv->nsectors = MX25L_MX25L3233F_NSECTORS;
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priv->pageshift = MX25L_MX25L3233F_PAGE_SHIFT;
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priv->addressbytes = MX25L_ADDRESSBYTES_3;
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return OK;
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}
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else if (capacity == MX25L_JEDEC_MX25L6433F_CAPACITY)
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{
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/* Save the FLASH geometry */
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priv->sectorshift = MX25L_MX25L6433F_SECTOR_SHIFT;
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priv->nsectors = MX25L_MX25L6433F_NSECTORS;
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priv->pageshift = MX25L_MX25L6433F_PAGE_SHIFT;
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priv->sectorshift = MX25L_MX25L6433F_SECTOR_SHIFT;
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priv->nsectors = MX25L_MX25L6433F_NSECTORS;
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priv->pageshift = MX25L_MX25L6433F_PAGE_SHIFT;
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priv->addressbytes = MX25L_ADDRESSBYTES_3;
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return OK;
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}
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else if (capacity == MX25L_JEDEC_MX25L25635F_CAPACITY)
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{
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/* Save the FLASH geometry */
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priv->sectorshift = MX25L_MX25L25635F_SECTOR_SHIFT;
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priv->nsectors = MX25L_MX25L25635F_NSECTORS;
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priv->pageshift = MX25L_MX25L25635F_PAGE_SHIFT;
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priv->sectorshift = MX25L_MX25L25635F_SECTOR_SHIFT;
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priv->nsectors = MX25L_MX25L25635F_NSECTORS;
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priv->pageshift = MX25L_MX25L25635F_PAGE_SHIFT;
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priv->addressbytes = MX25L_ADDRESSBYTES_4;
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return OK;
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}
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}
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@ -488,16 +510,31 @@ static void mx25l_sectorerase(FAR struct mx25l_dev_s *priv, off_t sector)
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* that was passed in as the erase type.
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*/
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(void)SPI_SEND(priv->dev, MX25L_SE);
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/* The command we send varies depending on if we need 3 or 4 address bytes */
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if (priv->addressbytes == MX25L_ADDRESSBYTES_4)
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{
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(void)SPI_SEND(priv->dev, MX25L_SE4B);
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/* Send the sector offset high byte first. For all of the supported
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* parts, the sector number is completely contained in the first byte
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* and the values used in the following two bytes don't really matter.
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*/
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/* Send the sector offset high byte first. */
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(void)SPI_SEND(priv->dev, (offset >> 16) & 0xff);
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(void)SPI_SEND(priv->dev, (offset >> 8) & 0xff);
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(void)SPI_SEND(priv->dev, offset & 0xff);
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(void)SPI_SEND(priv->dev, (offset >> 24) & 0xff);
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(void)SPI_SEND(priv->dev, (offset >> 16) & 0xff);
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(void)SPI_SEND(priv->dev, (offset >> 8) & 0xff);
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(void)SPI_SEND(priv->dev, offset & 0xff);
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}
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else
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{
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(void)SPI_SEND(priv->dev, MX25L_SE);
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/* Send the sector offset high byte first. For all of the supported
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* parts, the sector number is completely contained in the first byte
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* and the values used in the following two bytes don't really matter.
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*/
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(void)SPI_SEND(priv->dev, (offset >> 16) & 0xff);
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(void)SPI_SEND(priv->dev, (offset >> 8) & 0xff);
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(void)SPI_SEND(priv->dev, offset & 0xff);
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}
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/* Deselect the FLASH */
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@ -559,15 +596,33 @@ static void mx25l_byteread(FAR struct mx25l_dev_s *priv, FAR uint8_t *buffer,
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SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true);
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/* Send "Read from Memory " instruction */
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/* The command we send varies depending on if we need 3 or 4 address bytes */
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(void)SPI_SEND(priv->dev, MX25L_FAST_READ);
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if (priv->addressbytes == MX25L_ADDRESSBYTES_4)
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{
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/* Send "Read from Memory - 4 byte mode" instruction */
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/* Send the address high byte first. */
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(void)SPI_SEND(priv->dev, MX25L_FAST_READ4B);
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(void)SPI_SEND(priv->dev, (address >> 16) & 0xff);
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(void)SPI_SEND(priv->dev, (address >> 8) & 0xff);
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(void)SPI_SEND(priv->dev, address & 0xff);
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/* Send the address high byte first. */
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(void)SPI_SEND(priv->dev, (address >> 24) & 0xff);
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(void)SPI_SEND(priv->dev, (address >> 16) & 0xff);
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(void)SPI_SEND(priv->dev, (address >> 8) & 0xff);
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(void)SPI_SEND(priv->dev, address & 0xff);
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}
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else
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{
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/* Send "Read from Memory " instruction */
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(void)SPI_SEND(priv->dev, MX25L_FAST_READ);
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/* Send the address high byte first. */
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(void)SPI_SEND(priv->dev, (address >> 16) & 0xff);
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(void)SPI_SEND(priv->dev, (address >> 8) & 0xff);
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(void)SPI_SEND(priv->dev, address & 0xff);
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}
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/* Send a dummy byte */
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@ -602,16 +657,31 @@ static inline void mx25l_pagewrite(FAR struct mx25l_dev_s *priv,
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SPI_SELECT(priv->dev, SPIDEV_FLASH(0), true);
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/* Send the "Page Program (MX25L_PP)" Command */
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if (priv->addressbytes == MX25L_ADDRESSBYTES_4)
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{
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/* Send the "Page Program - 4 byte mode (MX25L_PP4B)" Command */
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SPI_SEND(priv->dev, MX25L_PP);
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SPI_SEND(priv->dev, MX25L_PP4B);
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/* Send the address high byte first. */
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/* Send the address high byte first. */
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(void)SPI_SEND(priv->dev, (address >> 16) & 0xff);
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(void)SPI_SEND(priv->dev, (address >> 8) & 0xff);
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(void)SPI_SEND(priv->dev, address & 0xff);
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(void)SPI_SEND(priv->dev, (address >> 24) & 0xff);
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(void)SPI_SEND(priv->dev, (address >> 16) & 0xff);
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(void)SPI_SEND(priv->dev, (address >> 8) & 0xff);
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(void)SPI_SEND(priv->dev, address & 0xff);
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}
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else
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{
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/* Send the "Page Program (MX25L_PP)" Command */
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SPI_SEND(priv->dev, MX25L_PP);
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/* Send the address high byte first. */
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(void)SPI_SEND(priv->dev, (address >> 16) & 0xff);
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(void)SPI_SEND(priv->dev, (address >> 8) & 0xff);
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(void)SPI_SEND(priv->dev, address & 0xff);
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}
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/* Then send the page of data */
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SPI_SNDBLOCK(priv->dev, buffer, 1 << priv->pageshift);
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