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SAM4L: Re-order some clock initialization. There was a dependency of GCLK0 on DFLL, but DFLL was being enabled after GCLK0

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This commit is contained in:
Gregory Nutt 2015-05-23 11:01:22 -06:00
parent b246e7adf2
commit 7b7da5ded4
1 changed files with 18 additions and 18 deletions
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36
arch/arm/src/samdl/saml_clockconfig.c
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@ -1233,24 +1233,6 @@ static inline void sam_config_gclks(void)
{
sam_gclk_config(&g_gclkconfig[i]);
}
/* Enable DFLL reference clock if the DFLL is enabled in closed loop mode */
sam_dfll48m_refclk();
/* Enable FDPLL reference clock if the DFLL is enabled */
sam_fdpll96m_refclk();
/* Setup CPU and BUS clocks */
sam_cpu_dividers();
/* Configure the GCLK_MAIN last as it may depend on the DFLL or other
* generators
*/
sam_gclk_config(&g_gclkconfig[0]);
}
#else
# define sam_config_gclks()
@ -1337,14 +1319,32 @@ void sam_clockconfig(void)
sam_config_gclks();
/* Enable DFLL reference clock if the DFLL is enabled in closed loop mode */
sam_dfll48m_refclk();
/* Enable DFLL48M */
sam_dfll48m_enable();
/* Enable FDPLL reference clock if the DFLL is enabled */
sam_fdpll96m_refclk();
/* Configure and enable FDPLL96M */
sam_fdpll96m_config();
/* Setup CPU and BUS clocks */
sam_cpu_dividers();
/* Configure the GCLK_MAIN last as it may depend on the DFLL, FDPLL or
* other generators
*/
sam_gclk_config(&g_gclkconfig[0]);
#if BOARD_CPU_FREQUENCY <= 12000000
/* If CPU frequency is less than 12MHz, scale down performance level to
* PL0.