Add STM32 ethernet MAC and DMA initialization
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4152 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
27a51442d7
commit
7b8d118a60
@ -524,8 +524,10 @@
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#define ETH_DMABMR_DA (1 << 1) /* Bit 1: DMA Arbitration */
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#define ETH_DMABMR_DSL_SHIFT (2) /* Bits 2-6: Descriptor skip length */
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#define ETH_DMABMR_DSL_MASK (31 << ETH_DMABMR_DSL_SHIFT)
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# define ETH_DMABMR_DSL(n) ((n) << ETH_DMABMR_DSL_SHIFT)
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#define ETH_DMABMR_EDFE (1 << 7) /* Bit 7: Enhanced descriptor format enable */
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#define ETH_DMABMR_PBL_SHIFT (8) /* Bits 8-13: Programmable burst length */
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# define ETH_DMABMR_PBL(n) ((n) << ETH_DMABMR_PBL_SHIFT) /* n=1, 2, 4, 8, 16, 32 */
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#define ETH_DMABMR_PBL_MASK (0x3f << ETH_DMABMR_PBL_SHIFT)
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#define ETH_DMABMR_RTPR_SHIFT (14) /* Bits 14-15: Rx Tx priority ratio */
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#define ETH_DMABMR_RTPR_MASK (3 << ETH_DMABMR_RTPR_SHIFT)
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@ -594,11 +596,11 @@
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#define ETH_DMAOMR_SR (1 << 1) /* Bit 1: Start/stop receive */
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#define ETH_DMAOMR_OSF (1 << 2) /* Bit 2: Operate on second frame */
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#define ETH_DMAOMR_RTC_SHIFT (3) /* Bits 3-4: Receive threshold control */
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#define ETH_DMAOMR_RTC_MASK (3 << ETH_DMAOMR_RTC_MASK)
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# define ETH_DMAOMR_RTC_64 (0 << ETH_DMAOMR_RTC_MASK)
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# define ETH_DMAOMR_RTC_32 (1 << ETH_DMAOMR_RTC_MASK)
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# define ETH_DMAOMR_RTC_96 (2 << ETH_DMAOMR_RTC_MASK)
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# define ETH_DMAOMR_RTC_128 (3 << ETH_DMAOMR_RTC_MASK)
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#define ETH_DMAOMR_RTC_MASK (3 << ETH_DMAOMR_RTC_SHIFT)
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# define ETH_DMAOMR_RTC_64 (0 << ETH_DMAOMR_RTC_SHIFT)
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# define ETH_DMAOMR_RTC_32 (1 << ETH_DMAOMR_RTC_SHIFT)
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# define ETH_DMAOMR_RTC_96 (2 << ETH_DMAOMR_RTC_SHIFT)
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# define ETH_DMAOMR_RTC_128 (3 << ETH_DMAOMR_RTC_SHIFT)
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#define ETH_DMAOMR_FUGF (1 << 6) /* Bit 6: Forward undersized good frames */
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#define ETH_DMAOMR_FEF (1 << 7) /* Bit 7: Forward error frames */
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#define ETH_DMAOMR_ST (1 << 13) /* Bit 13: Start/stop transmission */
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@ -136,6 +136,7 @@
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*/
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#define CONFIG_STM32_ETH_ENHANCEDDESC 1
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#undef CONFIG_STM32_ETH_HWCHECKSUM
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/* Ethernet buffer sizes and numbers */
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@ -190,6 +191,242 @@
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#define PHY_READ_TIMEOUT (0x0004ffff)
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#define PHY_WRITE_TIMEOUT (0x0004ffff)
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#define PHY_RETRY_TIMEOUT (0x0004ffff)
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/* Register values **********************************************************/
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/* Clear the MACCR bits that will be setup during MAC initialization (or that
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* are cleared unconditionally). Per the reference manual, all reserved bits
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* must be retained at their reset value.
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*
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* ETH_MACCR_RE Bit 2: Receiver enable
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* ETH_MACCR_TE Bit 3: Transmitter enable
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* ETH_MACCR_DC Bit 4: Deferral check
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* ETH_MACCR_BL Bits 5-6: Back-off limit
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* ETH_MACCR_APCS Bit 7: Automatic pad/CRC stripping
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* ETH_MACCR_RD Bit 9: Retry disable
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* ETH_MACCR_IPCO Bit 10: IPv4 checksum offload
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* ETH_MACCR_DM Bit 11: Duplex mode
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* ETH_MACCR_LM Bit 12: Loopback mode
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* ETH_MACCR_ROD Bit 13: Receive own disable
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* ETH_MACCR_FES Bit 14: Fast Ethernet speed
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* ETH_MACCR_CSD Bit 16: Carrier sense disable
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* ETH_MACCR_IFG Bits 17-19: Interframe gap
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* ETH_MACCR_JD Bit 22: Jabber disable
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* ETH_MACCR_WD Bit 23: Watchdog disable
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* ETH_MACCR_CSTF Bits 25: CRC stripping for Type frames
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*/
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#define MACCR_CLEAR_BITS \
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( ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \
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ETH_MACCR_APCS | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_DM | \
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ETH_MACCR_LM | ETH_MACCR_ROD | ETH_MACCR_FES | ETH_MACCR_CSD | \
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ETH_MACCR_IFG_MASK | ETH_MACCR_JD | ETH_MACCR_WD | ETH_MACCR_CSTF )
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/* The following bits are set or left zero unconditionally in all modes.
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*
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* ETH_MACCR_RE Receiver enable 0 (disabled)
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* ETH_MACCR_TE Transmitter enable 0 (disabled)
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* ETH_MACCR_DC Deferral check 0 (disabled)
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* ETH_MACCR_BL Back-off limit 0 (10)
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* ETH_MACCR_APCS Automatic pad/CRC stripping 0 (disabled)
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* ETH_MACCR_RD Retry disable 1 (disabled)
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* ETH_MACCR_IPCO IPv4 checksum offload Depends on CONFIG_STM32_ETH_HWCHECKSUM
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* ETH_MACCR_LM Loopback mode 0 (disabled)
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* ETH_MACCR_ROD Receive own disable 0 (enabled)
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* ETH_MACCR_CSD Carrier sense disable 0 (enabled)
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* ETH_MACCR_IFG Interframe gap 0 (96 bits)
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* ETH_MACCR_JD Jabber disable 0 (enabled)
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* ETH_MACCR_WD Watchdog disable 0 (enabled)
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* ETH_MACCR_CSTF CRC stripping for Type frames 0 (disabled)
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*
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* The following are set conditioinally based on mode and speed.
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*
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* ETH_MACCR_DM Duplex mode Depends on priv->fduplex
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* ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100
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*/
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#ifdef CONFIG_STM32_ETH_HWCHECKSUM
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# define MACCR_SET_BITS \
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(ETH_MACCR_BL_10 | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_IFG(96))
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#else
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# define MACCR_SET_BITS \
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(ETH_MACCR_BL_10 | ETH_MACCR_RD | ETH_MACCR_IFG(96))
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#endif
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/* Clear the MACCR bits that will be setup during MAC initialization (or that
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* are cleared unconditionally). Per the reference manual, all reserved bits
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* must be retained at their reset value.
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*
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* ETH_MACFFR_PM Bit 0: Promiscuous mode
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* ETH_MACFFR_HU Bit 1: Hash unicast
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* ETH_MACFFR_HM Bit 2: Hash multicast
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* ETH_MACFFR_DAIF Bit 3: Destination address inverse filtering
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* ETH_MACFFR_PAM Bit 4: Pass all multicast
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* ETH_MACFFR_BFD Bit 5: Broadcast frames disable
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* ETH_MACFFR_PCF Bits 6-7: Pass control frames
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* ETH_MACFFR_SAIF Bit 8: Source address inverse filtering
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* ETH_MACFFR_SAF Bit 9: Source address filter
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* ETH_MACFFR_HPF Bit 10: Hash or perfect filter
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* ETH_MACFFR_RA Bit 31: Receive all
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*/
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#define MACFFR_CLEAR_BITS \
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(ETH_MACFFR_PM | ETH_MACFFR_HU | ETH_MACFFR_HM | ETH_MACFFR_DAIF | \
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ETH_MACFFR_PAM | ETH_MACFFR_BFD | ETH_MACFFR_PCF_MASK | ETH_MACFFR_SAIF | \
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ETH_MACFFR_SAF | ETH_MACFFR_HPF | ETH_MACFFR_RA)
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/* The following bits are set or left zero unconditionally in all modes.
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*
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* ETH_MACFFR_PM Promiscuous mode 0 (disabled)
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* ETH_MACFFR_HU Hash unicast 0 (perfect dest filtering)
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* ETH_MACFFR_HM Hash multicast 0 (perfect dest filtering)
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* ETH_MACFFR_DAIF Destination address inverse filtering 0 (normal)
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* ETH_MACFFR_PAM Pass all multicast 0 (Depends on HM bit)
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* ETH_MACFFR_BFD Broadcast frames disable 0 (enabled)
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* ETH_MACFFR_PCF Pass control frames 1 (block all but PAUSE)
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* ETH_MACFFR_SAIF Source address inverse filtering 0 (not used)
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* ETH_MACFFR_SAF Source address filter 0 (disabled)
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* ETH_MACFFR_HPF Hash or perfect filter 0 (Only matching frames passed)
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* ETH_MACFFR_RA Receive all 0 (disabled)
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*/
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#define MACFFR_SET_BITS (ETH_MACFFR_PCF_PAUSE)
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/* Clear the MACFCR bits that will be setup during MAC initialization (or that
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* are cleared unconditionally). Per the reference manual, all reserved bits
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* must be retained at their reset value.
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*
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* ETH_MACFCR_FCB_BPA Bit 0: Flow control busy/back pressure activate
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* ETH_MACFCR_TFCE Bit 1: Transmit flow control enable
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* ETH_MACFCR_RFCE Bit 2: Receive flow control enable
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* ETH_MACFCR_UPFD Bit 3: Unicast pause frame detect
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* ETH_MACFCR_PLT Bits 4-5: Pause low threshold
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* ETH_MACFCR_ZQPD Bit 7: Zero-quanta pause disable
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* ETH_MACFCR_PT Bits 16-31: Pause time
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*/
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#define MACFCR_CLEAR_MASK \
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(ETH_MACFCR_FCB_BPA | ETH_MACFCR_TFCE | ETH_MACFCR_RFCE | ETH_MACFCR_UPFD | \
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ETH_MACFCR_PLT_MASK | ETH_MACFCR_ZQPD | ETH_MACFCR_PT_MASK)
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/* The following bits are set or left zero unconditionally in all modes.
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*
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* ETH_MACFCR_FCB_BPA Flow control busy/back pressure activate 0 (no pause control frame)
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* ETH_MACFCR_TFCE Transmit flow control enable 0 (disabled)
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* ETH_MACFCR_RFCE Receive flow control enable 0 (disabled)
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* ETH_MACFCR_UPFD Unicast pause frame detect 0 (disabled)
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* ETH_MACFCR_PLT Pause low threshold 0 (pause time - 4)
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* ETH_MACFCR_ZQPD Zero-quanta pause disable 1 (disabled)
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* ETH_MACFCR_PT Pause time 0
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*/
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#define MACFCR_SET_MASK (ETH_MACFCR_PLT_M4 | ETH_MACFCR_ZQPD)
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/* Clear the DMAOMR bits that will be setup during MAC initialization (or that
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* are cleared unconditionally). Per the reference manual, all reserved bits
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* must be retained at their reset value.
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*
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* ETH_DMAOMR_SR Bit 1: Start/stop receive
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* TH_DMAOMR_OSF Bit 2: Operate on second frame
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* ETH_DMAOMR_RTC Bits 3-4: Receive threshold control
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* ETH_DMAOMR_FUGF Bit 6: Forward undersized good frames
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* ETH_DMAOMR_FEF Bit 7: Forward error frames
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* ETH_DMAOMR_ST Bit 13: Start/stop transmission
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* ETH_DMAOMR_TTC Bits 14-16: Transmit threshold control
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* ETH_DMAOMR_FTF Bit 20: Flush transmit FIFO
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* ETH_DMAOMR_TSF Bit 21: Transmit store and forward
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* ETH_DMAOMR_DFRF Bit 24: Disable flushing of received frames
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* ETH_DMAOMR_RSF Bit 25: Receive store and forward
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* TH_DMAOMR_DTCEFD Bit 26: Dropping of TCP/IP checksum error frames disable
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*/
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#define DMAOMR_CLEAR_MASK \
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(ETH_DMAOMR_SR | ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_MASK | ETH_DMAOMR_FUGF | \
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ETH_DMAOMR_FEF | ETH_DMAOMR_ST | ETH_DMAOMR_TTC_MASK | ETH_DMAOMR_FTF | \
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ETH_DMAOMR_TSF | ETH_DMAOMR_DFRF | ETH_DMAOMR_RSF | ETH_DMAOMR_DTCEFD)
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/* The following bits are set or left zero unconditionally in all modes.
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*
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* ETH_DMAOMR_SR Start/stop receive 0 (not running)
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* TH_DMAOMR_OSF Operate on second frame 1 (enabled)
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* ETH_DMAOMR_RTC Receive threshold control 0 (64 bytes)
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* ETH_DMAOMR_FUGF Forward undersized good frames 0 (disabled)
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* ETH_DMAOMR_FEF Forward error frames 0 (disabled)
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* ETH_DMAOMR_ST Start/stop transmission 0 (not running)
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* ETH_DMAOMR_TTC Transmit threshold control 0 (64 bytes)
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* ETH_DMAOMR_FTF Flush transmit FIFO 0 (no flush)
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* ETH_DMAOMR_TSF Transmit store and forward Depends on CONFIG_STM32_ETH_HWCHECKSUM
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* ETH_DMAOMR_DFRF Disable flushing of received frames 0 (enabled)
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* ETH_DMAOMR_RSF Receive store and forward Depends on CONFIG_STM32_ETH_HWCHECKSUM
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* TH_DMAOMR_DTCEFD Dropping of TCP/IP checksum error Depends on CONFIG_STM32_ETH_HWCHECKSUM
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* frames disable
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*
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* When the checksum offload feature is enabled, we need to enable the Store
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* and Forward mode: the store and forward guarantee that a whole frame is
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* stored in the FIFO, so the MAC can insert/verify the checksum, if the
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* checksum is OK the DMA can handle the frame otherwise the frame is dropped
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*/
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#if CONFIG_STM32_ETH_HWCHECKSUM
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# define DMAOMR_SET_MASK \
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(ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_64 | ETH_DMAOMR_TTC_64 | \
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ETH_DMAOMR_TSF | ETH_DMAOMR_RSF)
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#else
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# define DMAOMR_SET_MASK \
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(ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_64 | ETH_DMAOMR_TTC_64 | \
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ETH_DMAOMR_DTCEFD)
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#endif
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/* Clear the DMABMR bits that will be setup during MAC initialization (or that
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* are cleared unconditionally). Per the reference manual, all reserved bits
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* must be retained at their reset value.
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*
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* ETH_DMABMR_SR Bit 0: Software reset
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* ETH_DMABMR_DA Bit 1: DMA Arbitration
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* ETH_DMABMR_DSL Bits 2-6: Descriptor skip length
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* ETH_DMABMR_EDFE Bit 7: Enhanced descriptor format enable
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* ETH_DMABMR_PBL Bits 8-13: Programmable burst length
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* ETH_DMABMR_RTPR Bits 14-15: Rx Tx priority ratio
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* ETH_DMABMR_FB Bit 16: Fixed burst
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* ETH_DMABMR_RDP Bits 17-22: Rx DMA PBL
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* ETH_DMABMR_USP Bit 23: Use separate PBL
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* ETH_DMABMR_FPM Bit 24: 4xPBL mode
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* ETH_DMABMR_AAB Bit 25: Address-aligned beats
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* ETH_DMABMR_MB Bit 26: Mixed burst
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*/
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#define DMABMR_CLEAR_MASK \
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(ETH_DMABMR_SR | ETH_DMABMR_DA | ETH_DMABMR_DSL_MASK | ETH_DMABMR_EDFE | \
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ETH_DMABMR_PBL_MASK | ETH_DMABMR_RTPR_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \
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ETH_DMABMR_USP | ETH_DMABMR_FPM | ETH_DMABMR_AAB | ETH_DMABMR_MB)
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/* The following bits are set or left zero unconditionally in all modes.
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*
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*
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* ETH_DMABMR_SR Software reset 0 (no reset)
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* ETH_DMABMR_DA DMA Arbitration 0 (round robin)
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* ETH_DMABMR_DSL Descriptor skip length 0
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* ETH_DMABMR_EDFE Enhanced descriptor format enable Depends on CONFIG_STM32_ETH_ENHANCEDDESC
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* ETH_DMABMR_PBL Programmable burst length 32 beats
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* ETH_DMABMR_RTPR Rx Tx priority ratio 2:1
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* ETH_DMABMR_FB Fixed burst 1 (enabled)
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* ETH_DMABMR_RDP Rx DMA PBL 32 beats
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* ETH_DMABMR_USP Use separate PBL 1 (enabled)
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* ETH_DMABMR_FPM 4xPBL mode 0 (disabled)
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* ETH_DMABMR_AAB Address-aligned beats 1 (enabled)
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* ETH_DMABMR_MB Mixed burst 0 (disabled)
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*/
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#ifdef CONFIG_STM32_ETH_ENHANCEDDESC
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# define DMABMR_SET_MASK \
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(ETH_DMABMR_DSL(0) | ETH_DMABMR_PBL(32) | ETH_DMABMR_EDFE | ETH_DMABMR_RTPR_2TO1 | \
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ETH_DMABMR_FB | ETH_DMABMR_RDP(32) | ETH_DMABMR_USP | ETH_DMABMR_AAB)
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#else
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# define DMABMR_SET_MASK \
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(ETH_DMABMR_DSL(0) | ETH_DMABMR_PBL(32) | ETH_DMABMR_RTPR_2TO1 | ETH_DMABMR_FB | \
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ETH_DMABMR_RDP(32) | ETH_DMABMR_USP | ETH_DMABMR_AAB)
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#endif
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/* Helpers ******************************************************************/
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/* This is a helper pointer for accessing the contents of the Ethernet
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@ -588,12 +825,19 @@ static void stm32_polltimer(int argc, uint32_t arg, ...)
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static int stm32_ifup(struct uip_driver_s *dev)
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{
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FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)dev->d_private;
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int ret;
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ndbg("Bringing up: %d.%d.%d.%d\n",
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dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
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(dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24 );
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/* Initialize PHYs, the Ethernet interface, and setup up Ethernet interrupts */
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/* Configure the Ethernet interface for DMA operation. */
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ret = stm32_ethconfig(priv);
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if (ret < 0)
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{
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return ret;
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}
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/* Set and activate a timer process */
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@ -642,6 +886,8 @@ static int stm32_ifdown(struct uip_driver_s *dev)
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* successfully brings the interface back up.
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*/
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stm32_ethreset(priv);
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/* Mark the device "down" */
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priv->ifup = false;
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@ -915,7 +1161,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
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#ifdef CONFIG_STM32_AUTONEG
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/* Wait for link status */
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for (timeout = 0; timeout < PHY_READ_TIMEOUT; timeout++)
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for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++)
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{
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ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval);
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if (ret < 0)
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@ -928,7 +1174,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
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}
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}
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if (timeout >= PHY_READ_TIMEOUT)
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if (timeout >= PHY_RETRY_TIMEOUT)
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{
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ndbg("Timed out waiting for link status\n");
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return -ETIMEDOUT;
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@ -944,7 +1190,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
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/* Wait until auto-negotiation completes */
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for (timeout = 0; timeout < PHY_READ_TIMEOUT; timeout++)
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for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++)
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{
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ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval);
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if (ret < 0)
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@ -957,7 +1203,7 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
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}
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}
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if (timeout >= PHY_READ_TIMEOUT)
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if (timeout >= PHY_RETRY_TIMEOUT)
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{
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ndbg("Timed out waiting for auto-negotiation\n");
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return -ETIMEDOUT;
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@ -1190,8 +1436,69 @@ static void stm32_ethreset(FAR struct stm32_ethmac_s *priv)
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static int stm32_macconfig(FAR struct stm32_ethmac_s *priv)
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{
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#warning "Missing logic"
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return -ENOSYS;
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uint32_t regval;
|
||||
|
||||
/* Set up the MACCR register */
|
||||
|
||||
regval = getreg32(STM32_ETH_MACCR);
|
||||
regval &= ~MACCR_CLEAR_BITS;
|
||||
regval |= MACCR_SET_BITS;
|
||||
|
||||
if (priv->fduplex)
|
||||
{
|
||||
/* Set the DM bit for full duplex support */
|
||||
|
||||
regval |= ETH_MACCR_DM;
|
||||
}
|
||||
|
||||
if (priv->mbps100)
|
||||
{
|
||||
/* Set the FES bit for 100Mbps fast ethernet support */
|
||||
|
||||
regval |= ETH_MACCR_FES;
|
||||
}
|
||||
|
||||
putreg32(regval, STM32_ETH_MACCR);
|
||||
|
||||
/* Set up the MACFFR register */
|
||||
|
||||
regval = getreg32(STM32_ETH_MACFFR);
|
||||
regval &= ~MACFFR_CLEAR_BITS;
|
||||
regval |= MACFFR_SET_BITS;
|
||||
putreg32(regval, STM32_ETH_MACFFR);
|
||||
|
||||
/* Set up the MACHTHR and MACHTLR registers */
|
||||
|
||||
putreg32(0, STM32_ETH_MACHTHR);
|
||||
putreg32(0, STM32_ETH_MACHTLR);
|
||||
|
||||
/* Setup up the MACFCR register */
|
||||
|
||||
regval = getreg32(STM32_ETH_MACFCR);
|
||||
regval &= ~MACFCR_CLEAR_MASK;
|
||||
regval |= MACFCR_SET_MASK;
|
||||
putreg32(regval, STM32_ETH_MACFCR);
|
||||
|
||||
/* Setup up the MACVLANTR register */
|
||||
|
||||
putreg32(0, STM32_ETH_MACVLANTR);
|
||||
|
||||
/* DMA Configuration */
|
||||
/* Set up the DMAOMR register */
|
||||
|
||||
regval = getreg32(STM32_ETH_DMAOMR);
|
||||
regval &= ~DMAOMR_CLEAR_MASK;
|
||||
regval |= DMAOMR_SET_MASK;
|
||||
putreg32(regval, STM32_ETH_DMAOMR);
|
||||
|
||||
/* Set up the DMABMR register */
|
||||
|
||||
regval = getreg32(STM32_ETH_DMABMR);
|
||||
regval &= ~DMABMR_CLEAR_MASK;
|
||||
regval |= DMABMR_SET_MASK;
|
||||
putreg32(regval, STM32_ETH_DMABMR);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -1266,7 +1573,6 @@ static inline
|
||||
int stm32_ethinitialize(int intf)
|
||||
{
|
||||
struct stm32_ethmac_s *priv;
|
||||
int ret;
|
||||
|
||||
/* Get the interface structure associated with this interface number. */
|
||||
|
||||
@ -1294,14 +1600,6 @@ int stm32_ethinitialize(int intf)
|
||||
|
||||
stm32_ethgpioconfig(priv);
|
||||
|
||||
/* Configure the Ethernet interface for DMA operation. */
|
||||
|
||||
ret = stm32_ethconfig(priv);
|
||||
if (ret < 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Attach the IRQ to the driver */
|
||||
|
||||
if (irq_attach(STM32_IRQ_ETH, stm32_interrupt))
|
||||
@ -1315,9 +1613,6 @@ int stm32_ethinitialize(int intf)
|
||||
|
||||
stm32_ifdown(&priv->dev);
|
||||
|
||||
/* Read the MAC address from the hardware into priv->dev.d_mac.ether_addr_octet */
|
||||
#warning "Missing logic"
|
||||
|
||||
/* Register the device with the OS so that socket IOCTLs can be performed */
|
||||
|
||||
(void)netdev_register(&priv->dev);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user